56 CPU_CAVIUM = 'C',
57 CPU_DEC = 'D',
58 CPU_INFINEON = 'I',
59 CPU_MOTOROLA = 'M',
60 CPU_NVIDIA = 'N',
61 CPU_AMCC = 'P',
62 CPU_QUALCOM = 'Q',
63 CPU_MARVELL = 'V',
64 CPU_INTEL = 'i',
65 };
66
67 enum Feature_Flag {
68 CPU_FP = (1<<0),
69 CPU_ASIMD = (1<<1),
70 CPU_EVTSTRM = (1<<2),
71 CPU_AES = (1<<3),
72 CPU_PMULL = (1<<4),
73 CPU_SHA1 = (1<<5),
74 CPU_SHA2 = (1<<6),
75 CPU_CRC32 = (1<<7),
76 CPU_A53MAC = (1 << 30),
77 CPU_DMB_ATOMICS = (1 << 31),
78 };
79
80 static int cpu_family() { return _cpu; }
81 static int cpu_model() { return _model; }
82 static int cpu_model2() { return _model2; }
83 static int cpu_variant() { return _variant; }
84 static int cpu_revision() { return _revision; }
85 };
86
87 #endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
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56 CPU_CAVIUM = 'C',
57 CPU_DEC = 'D',
58 CPU_INFINEON = 'I',
59 CPU_MOTOROLA = 'M',
60 CPU_NVIDIA = 'N',
61 CPU_AMCC = 'P',
62 CPU_QUALCOM = 'Q',
63 CPU_MARVELL = 'V',
64 CPU_INTEL = 'i',
65 };
66
67 enum Feature_Flag {
68 CPU_FP = (1<<0),
69 CPU_ASIMD = (1<<1),
70 CPU_EVTSTRM = (1<<2),
71 CPU_AES = (1<<3),
72 CPU_PMULL = (1<<4),
73 CPU_SHA1 = (1<<5),
74 CPU_SHA2 = (1<<6),
75 CPU_CRC32 = (1<<7),
76 CPU_LSE = (1<<8),
77 CPU_A53MAC = (1 << 30),
78 CPU_DMB_ATOMICS = (1 << 31),
79 };
80
81 static int cpu_family() { return _cpu; }
82 static int cpu_model() { return _model; }
83 static int cpu_model2() { return _model2; }
84 static int cpu_variant() { return _variant; }
85 static int cpu_revision() { return _revision; }
86 };
87
88 #endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
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