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src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp

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rev 12447 : 8171537: aarch64: compiler/c1/Test6849574.java generates guarantee failure in C1
Reviewed-by: aph


3094           inst->remove_at(start_insn);
3095         }
3096         // Insert the tableswitch instruction
3097         inst->insert_before(start_insn,
3098                             new LIR_Op2(lir_cmp, lir_cond_always,
3099                                         LIR_OprFact::intConst(tableswitch_count),
3100                                         reg_opr));
3101         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3102         tableswitch_count++;
3103       }
3104       reg = noreg;
3105       last_key = -2147483648;
3106     }
3107   next_state:
3108     ;
3109   }
3110 #endif
3111 }
3112 
3113 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3114   Address addr = as_Address(src->as_address_ptr(), noreg);
3115   BasicType type = src->type();
3116   bool is_oop = type == T_OBJECT || type == T_ARRAY;
3117 
3118   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3119   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3120 
3121   switch(type) {
3122   case T_INT:
3123     xchg = &MacroAssembler::atomic_xchgalw;
3124     add = &MacroAssembler::atomic_addalw;
3125     break;
3126   case T_LONG:
3127     xchg = &MacroAssembler::atomic_xchgal;
3128     add = &MacroAssembler::atomic_addal;
3129     break;
3130   case T_OBJECT:
3131   case T_ARRAY:
3132     if (UseCompressedOops) {
3133       xchg = &MacroAssembler::atomic_xchgalw;
3134       add = &MacroAssembler::atomic_addalw;




3094           inst->remove_at(start_insn);
3095         }
3096         // Insert the tableswitch instruction
3097         inst->insert_before(start_insn,
3098                             new LIR_Op2(lir_cmp, lir_cond_always,
3099                                         LIR_OprFact::intConst(tableswitch_count),
3100                                         reg_opr));
3101         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3102         tableswitch_count++;
3103       }
3104       reg = noreg;
3105       last_key = -2147483648;
3106     }
3107   next_state:
3108     ;
3109   }
3110 #endif
3111 }
3112 
3113 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3114   Address addr = as_Address(src->as_address_ptr());
3115   BasicType type = src->type();
3116   bool is_oop = type == T_OBJECT || type == T_ARRAY;
3117 
3118   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3119   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3120 
3121   switch(type) {
3122   case T_INT:
3123     xchg = &MacroAssembler::atomic_xchgalw;
3124     add = &MacroAssembler::atomic_addalw;
3125     break;
3126   case T_LONG:
3127     xchg = &MacroAssembler::atomic_xchgal;
3128     add = &MacroAssembler::atomic_addal;
3129     break;
3130   case T_OBJECT:
3131   case T_ARRAY:
3132     if (UseCompressedOops) {
3133       xchg = &MacroAssembler::atomic_xchgalw;
3134       add = &MacroAssembler::atomic_addalw;
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