1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include <sys/types.h> 27 28 #include "precompiled.hpp" 29 #include "asm/assembler.hpp" 30 #include "asm/assembler.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 33 #include "compiler/disassembler.hpp" 34 #include "memory/resourceArea.hpp" 35 #include "nativeInst_aarch64.hpp" 36 #include "oops/klass.inline.hpp" 37 #include "oops/oop.inline.hpp" 38 #include "opto/compile.hpp" 39 #include "opto/node.hpp" 40 #include "runtime/biasedLocking.hpp" 41 #include "runtime/icache.hpp" 42 #include "runtime/interfaceSupport.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/thread.hpp" 45 46 #if INCLUDE_ALL_GCS 47 #include "gc/g1/g1CollectedHeap.inline.hpp" 48 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 49 #include "gc/g1/heapRegion.hpp" 50 #endif 51 52 #ifdef PRODUCT 53 #define BLOCK_COMMENT(str) /* nothing */ 54 #define STOP(error) stop(error) 55 #else 56 #define BLOCK_COMMENT(str) block_comment(str) 57 #define STOP(error) block_comment(error); stop(error) 58 #endif 59 60 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 61 62 // Patch any kind of instruction; there may be several instructions. 63 // Return the total length (in bytes) of the instructions. 64 int MacroAssembler::pd_patch_instruction_size(address branch, address target) { 65 int instructions = 1; 66 assert((uint64_t)target < (1ul << 48), "48-bit overflow in address constant"); 67 long offset = (target - branch) >> 2; 68 unsigned insn = *(unsigned*)branch; 69 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) { 70 // Load register (literal) 71 Instruction_aarch64::spatch(branch, 23, 5, offset); 72 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 73 // Unconditional branch (immediate) 74 Instruction_aarch64::spatch(branch, 25, 0, offset); 75 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 76 // Conditional branch (immediate) 77 Instruction_aarch64::spatch(branch, 23, 5, offset); 78 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 79 // Compare & branch (immediate) 80 Instruction_aarch64::spatch(branch, 23, 5, offset); 81 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 82 // Test & branch (immediate) 83 Instruction_aarch64::spatch(branch, 18, 5, offset); 84 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 85 // PC-rel. addressing 86 offset = target-branch; 87 int shift = Instruction_aarch64::extract(insn, 31, 31); 88 if (shift) { 89 u_int64_t dest = (u_int64_t)target; 90 uint64_t pc_page = (uint64_t)branch >> 12; 91 uint64_t adr_page = (uint64_t)target >> 12; 92 unsigned offset_lo = dest & 0xfff; 93 offset = adr_page - pc_page; 94 95 // We handle 4 types of PC relative addressing 96 // 1 - adrp Rx, target_page 97 // ldr/str Ry, [Rx, #offset_in_page] 98 // 2 - adrp Rx, target_page 99 // add Ry, Rx, #offset_in_page 100 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 101 // movk Rx, #imm16<<32 102 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 103 // In the first 3 cases we must check that Rx is the same in the adrp and the 104 // subsequent ldr/str, add or movk instruction. Otherwise we could accidentally end 105 // up treating a type 4 relocation as a type 1, 2 or 3 just because it happened 106 // to be followed by a random unrelated ldr/str, add or movk instruction. 107 // 108 unsigned insn2 = ((unsigned*)branch)[1]; 109 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 110 Instruction_aarch64::extract(insn, 4, 0) == 111 Instruction_aarch64::extract(insn2, 9, 5)) { 112 // Load/store register (unsigned immediate) 113 unsigned size = Instruction_aarch64::extract(insn2, 31, 30); 114 Instruction_aarch64::patch(branch + sizeof (unsigned), 115 21, 10, offset_lo >> size); 116 guarantee(((dest >> size) << size) == dest, "misaligned target"); 117 instructions = 2; 118 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 119 Instruction_aarch64::extract(insn, 4, 0) == 120 Instruction_aarch64::extract(insn2, 4, 0)) { 121 // add (immediate) 122 Instruction_aarch64::patch(branch + sizeof (unsigned), 123 21, 10, offset_lo); 124 instructions = 2; 125 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 126 Instruction_aarch64::extract(insn, 4, 0) == 127 Instruction_aarch64::extract(insn2, 4, 0)) { 128 // movk #imm16<<32 129 Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32); 130 long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L); 131 long pc_page = (long)branch >> 12; 132 long adr_page = (long)dest >> 12; 133 offset = adr_page - pc_page; 134 instructions = 2; 135 } 136 } 137 int offset_lo = offset & 3; 138 offset >>= 2; 139 Instruction_aarch64::spatch(branch, 23, 5, offset); 140 Instruction_aarch64::patch(branch, 30, 29, offset_lo); 141 } else if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010100) { 142 u_int64_t dest = (u_int64_t)target; 143 // Move wide constant 144 assert(nativeInstruction_at(branch+4)->is_movk(), "wrong insns in patch"); 145 assert(nativeInstruction_at(branch+8)->is_movk(), "wrong insns in patch"); 146 Instruction_aarch64::patch(branch, 20, 5, dest & 0xffff); 147 Instruction_aarch64::patch(branch+4, 20, 5, (dest >>= 16) & 0xffff); 148 Instruction_aarch64::patch(branch+8, 20, 5, (dest >>= 16) & 0xffff); 149 assert(target_addr_for_insn(branch) == target, "should be"); 150 instructions = 3; 151 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 152 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 153 // nothing to do 154 assert(target == 0, "did not expect to relocate target for polling page load"); 155 } else { 156 ShouldNotReachHere(); 157 } 158 return instructions * NativeInstruction::instruction_size; 159 } 160 161 int MacroAssembler::patch_oop(address insn_addr, address o) { 162 int instructions; 163 unsigned insn = *(unsigned*)insn_addr; 164 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch"); 165 166 // OOPs are either narrow (32 bits) or wide (48 bits). We encode 167 // narrow OOPs by setting the upper 16 bits in the first 168 // instruction. 169 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) { 170 // Move narrow OOP 171 narrowOop n = oopDesc::encode_heap_oop((oop)o); 172 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16); 173 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff); 174 instructions = 2; 175 } else { 176 // Move wide OOP 177 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch"); 178 uintptr_t dest = (uintptr_t)o; 179 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff); 180 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff); 181 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff); 182 instructions = 3; 183 } 184 return instructions * NativeInstruction::instruction_size; 185 } 186 187 address MacroAssembler::target_addr_for_insn(address insn_addr, unsigned insn) { 188 long offset = 0; 189 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000) { 190 // Load register (literal) 191 offset = Instruction_aarch64::sextract(insn, 23, 5); 192 return address(((uint64_t)insn_addr + (offset << 2))); 193 } else if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) { 194 // Unconditional branch (immediate) 195 offset = Instruction_aarch64::sextract(insn, 25, 0); 196 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) { 197 // Conditional branch (immediate) 198 offset = Instruction_aarch64::sextract(insn, 23, 5); 199 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) { 200 // Compare & branch (immediate) 201 offset = Instruction_aarch64::sextract(insn, 23, 5); 202 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) { 203 // Test & branch (immediate) 204 offset = Instruction_aarch64::sextract(insn, 18, 5); 205 } else if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) { 206 // PC-rel. addressing 207 offset = Instruction_aarch64::extract(insn, 30, 29); 208 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2; 209 int shift = Instruction_aarch64::extract(insn, 31, 31) ? 12 : 0; 210 if (shift) { 211 offset <<= shift; 212 uint64_t target_page = ((uint64_t)insn_addr) + offset; 213 target_page &= ((uint64_t)-1) << shift; 214 // Return the target address for the following sequences 215 // 1 - adrp Rx, target_page 216 // ldr/str Ry, [Rx, #offset_in_page] 217 // 2 - adrp Rx, target_page 218 // add Ry, Rx, #offset_in_page 219 // 3 - adrp Rx, target_page (page aligned reloc, offset == 0) 220 // movk Rx, #imm12<<32 221 // 4 - adrp Rx, target_page (page aligned reloc, offset == 0) 222 // 223 // In the first two cases we check that the register is the same and 224 // return the target_page + the offset within the page. 225 // Otherwise we assume it is a page aligned relocation and return 226 // the target page only. 227 // 228 unsigned insn2 = ((unsigned*)insn_addr)[1]; 229 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 && 230 Instruction_aarch64::extract(insn, 4, 0) == 231 Instruction_aarch64::extract(insn2, 9, 5)) { 232 // Load/store register (unsigned immediate) 233 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 234 unsigned int size = Instruction_aarch64::extract(insn2, 31, 30); 235 return address(target_page + (byte_offset << size)); 236 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 && 237 Instruction_aarch64::extract(insn, 4, 0) == 238 Instruction_aarch64::extract(insn2, 4, 0)) { 239 // add (immediate) 240 unsigned int byte_offset = Instruction_aarch64::extract(insn2, 21, 10); 241 return address(target_page + byte_offset); 242 } else { 243 if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 && 244 Instruction_aarch64::extract(insn, 4, 0) == 245 Instruction_aarch64::extract(insn2, 4, 0)) { 246 target_page = (target_page & 0xffffffff) | 247 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32); 248 } 249 return (address)target_page; 250 } 251 } else { 252 ShouldNotReachHere(); 253 } 254 } else if (Instruction_aarch64::extract(insn, 31, 23) == 0b110100101) { 255 u_int32_t *insns = (u_int32_t *)insn_addr; 256 // Move wide constant: movz, movk, movk. See movptr(). 257 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch"); 258 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch"); 259 return address(u_int64_t(Instruction_aarch64::extract(insns[0], 20, 5)) 260 + (u_int64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16) 261 + (u_int64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32)); 262 } else if (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 && 263 Instruction_aarch64::extract(insn, 4, 0) == 0b11111) { 264 return 0; 265 } else { 266 ShouldNotReachHere(); 267 } 268 return address(((uint64_t)insn_addr + (offset << 2))); 269 } 270 271 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 272 dsb(Assembler::SY); 273 } 274 275 276 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 277 bool clear_pc) { 278 // we must set sp to zero to clear frame 279 str(zr, Address(rthread, JavaThread::last_Java_sp_offset())); 280 // must clear fp, so that compiled frames are not confused; it is 281 // possible that we need it only for debugging 282 if (clear_fp) { 283 str(zr, Address(rthread, JavaThread::last_Java_fp_offset())); 284 } 285 286 if (clear_pc) { 287 str(zr, Address(rthread, JavaThread::last_Java_pc_offset())); 288 } 289 } 290 291 // Calls to C land 292 // 293 // When entering C land, the rfp, & resp of the last Java frame have to be recorded 294 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 295 // has to be reset to 0. This is required to allow proper stack traversal. 296 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 297 Register last_java_fp, 298 Register last_java_pc, 299 Register scratch) { 300 301 if (last_java_pc->is_valid()) { 302 str(last_java_pc, Address(rthread, 303 JavaThread::frame_anchor_offset() 304 + JavaFrameAnchor::last_Java_pc_offset())); 305 } 306 307 // determine last_java_sp register 308 if (last_java_sp == sp) { 309 mov(scratch, sp); 310 last_java_sp = scratch; 311 } else if (!last_java_sp->is_valid()) { 312 last_java_sp = esp; 313 } 314 315 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset())); 316 317 // last_java_fp is optional 318 if (last_java_fp->is_valid()) { 319 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset())); 320 } 321 } 322 323 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 324 Register last_java_fp, 325 address last_java_pc, 326 Register scratch) { 327 if (last_java_pc != NULL) { 328 adr(scratch, last_java_pc); 329 } else { 330 // FIXME: This is almost never correct. We should delete all 331 // cases of set_last_Java_frame with last_java_pc=NULL and use the 332 // correct return address instead. 333 adr(scratch, pc()); 334 } 335 336 str(scratch, Address(rthread, 337 JavaThread::frame_anchor_offset() 338 + JavaFrameAnchor::last_Java_pc_offset())); 339 340 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch); 341 } 342 343 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 344 Register last_java_fp, 345 Label &L, 346 Register scratch) { 347 if (L.is_bound()) { 348 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch); 349 } else { 350 InstructionMark im(this); 351 L.add_patch_at(code(), locator()); 352 set_last_Java_frame(last_java_sp, last_java_fp, (address)NULL, scratch); 353 } 354 } 355 356 void MacroAssembler::far_call(Address entry, CodeBuffer *cbuf, Register tmp) { 357 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 358 assert(CodeCache::find_blob(entry.target()) != NULL, 359 "destination of far call not found in code cache"); 360 if (far_branches()) { 361 unsigned long offset; 362 // We can use ADRP here because we know that the total size of 363 // the code cache cannot exceed 2Gb. 364 adrp(tmp, entry, offset); 365 add(tmp, tmp, offset); 366 if (cbuf) cbuf->set_insts_mark(); 367 blr(tmp); 368 } else { 369 if (cbuf) cbuf->set_insts_mark(); 370 bl(entry); 371 } 372 } 373 374 void MacroAssembler::far_jump(Address entry, CodeBuffer *cbuf, Register tmp) { 375 assert(ReservedCodeCacheSize < 4*G, "branch out of range"); 376 assert(CodeCache::find_blob(entry.target()) != NULL, 377 "destination of far call not found in code cache"); 378 if (far_branches()) { 379 unsigned long offset; 380 // We can use ADRP here because we know that the total size of 381 // the code cache cannot exceed 2Gb. 382 adrp(tmp, entry, offset); 383 add(tmp, tmp, offset); 384 if (cbuf) cbuf->set_insts_mark(); 385 br(tmp); 386 } else { 387 if (cbuf) cbuf->set_insts_mark(); 388 b(entry); 389 } 390 } 391 392 int MacroAssembler::biased_locking_enter(Register lock_reg, 393 Register obj_reg, 394 Register swap_reg, 395 Register tmp_reg, 396 bool swap_reg_contains_mark, 397 Label& done, 398 Label* slow_case, 399 BiasedLockingCounters* counters) { 400 assert(UseBiasedLocking, "why call this otherwise?"); 401 assert_different_registers(lock_reg, obj_reg, swap_reg); 402 403 if (PrintBiasedLockingStatistics && counters == NULL) 404 counters = BiasedLocking::counters(); 405 406 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg); 407 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 408 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 409 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); 410 Address saved_mark_addr(lock_reg, 0); 411 412 // Biased locking 413 // See whether the lock is currently biased toward our thread and 414 // whether the epoch is still valid 415 // Note that the runtime guarantees sufficient alignment of JavaThread 416 // pointers to allow age to be placed into low bits 417 // First check to see whether biasing is even enabled for this object 418 Label cas_label; 419 int null_check_offset = -1; 420 if (!swap_reg_contains_mark) { 421 null_check_offset = offset(); 422 ldr(swap_reg, mark_addr); 423 } 424 andr(tmp_reg, swap_reg, markOopDesc::biased_lock_mask_in_place); 425 cmp(tmp_reg, markOopDesc::biased_lock_pattern); 426 br(Assembler::NE, cas_label); 427 // The bias pattern is present in the object's header. Need to check 428 // whether the bias owner and the epoch are both still current. 429 load_prototype_header(tmp_reg, obj_reg); 430 orr(tmp_reg, tmp_reg, rthread); 431 eor(tmp_reg, swap_reg, tmp_reg); 432 andr(tmp_reg, tmp_reg, ~((int) markOopDesc::age_mask_in_place)); 433 if (counters != NULL) { 434 Label around; 435 cbnz(tmp_reg, around); 436 atomic_incw(Address((address)counters->biased_lock_entry_count_addr()), tmp_reg, rscratch1, rscratch2); 437 b(done); 438 bind(around); 439 } else { 440 cbz(tmp_reg, done); 441 } 442 443 Label try_revoke_bias; 444 Label try_rebias; 445 446 // At this point we know that the header has the bias pattern and 447 // that we are not the bias owner in the current epoch. We need to 448 // figure out more details about the state of the header in order to 449 // know what operations can be legally performed on the object's 450 // header. 451 452 // If the low three bits in the xor result aren't clear, that means 453 // the prototype header is no longer biased and we have to revoke 454 // the bias on this object. 455 andr(rscratch1, tmp_reg, markOopDesc::biased_lock_mask_in_place); 456 cbnz(rscratch1, try_revoke_bias); 457 458 // Biasing is still enabled for this data type. See whether the 459 // epoch of the current bias is still valid, meaning that the epoch 460 // bits of the mark word are equal to the epoch bits of the 461 // prototype header. (Note that the prototype header's epoch bits 462 // only change at a safepoint.) If not, attempt to rebias the object 463 // toward the current thread. Note that we must be absolutely sure 464 // that the current epoch is invalid in order to do this because 465 // otherwise the manipulations it performs on the mark word are 466 // illegal. 467 andr(rscratch1, tmp_reg, markOopDesc::epoch_mask_in_place); 468 cbnz(rscratch1, try_rebias); 469 470 // The epoch of the current bias is still valid but we know nothing 471 // about the owner; it might be set or it might be clear. Try to 472 // acquire the bias of the object using an atomic operation. If this 473 // fails we will go in to the runtime to revoke the object's bias. 474 // Note that we first construct the presumed unbiased header so we 475 // don't accidentally blow away another thread's valid bias. 476 { 477 Label here; 478 mov(rscratch1, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 479 andr(swap_reg, swap_reg, rscratch1); 480 orr(tmp_reg, swap_reg, rthread); 481 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 482 // If the biasing toward our thread failed, this means that 483 // another thread succeeded in biasing it toward itself and we 484 // need to revoke that bias. The revocation will occur in the 485 // interpreter runtime in the slow case. 486 bind(here); 487 if (counters != NULL) { 488 atomic_incw(Address((address)counters->anonymously_biased_lock_entry_count_addr()), 489 tmp_reg, rscratch1, rscratch2); 490 } 491 } 492 b(done); 493 494 bind(try_rebias); 495 // At this point we know the epoch has expired, meaning that the 496 // current "bias owner", if any, is actually invalid. Under these 497 // circumstances _only_, we are allowed to use the current header's 498 // value as the comparison value when doing the cas to acquire the 499 // bias in the current epoch. In other words, we allow transfer of 500 // the bias from one thread to another directly in this situation. 501 // 502 // FIXME: due to a lack of registers we currently blow away the age 503 // bits in this situation. Should attempt to preserve them. 504 { 505 Label here; 506 load_prototype_header(tmp_reg, obj_reg); 507 orr(tmp_reg, rthread, tmp_reg); 508 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, slow_case); 509 // If the biasing toward our thread failed, then another thread 510 // succeeded in biasing it toward itself and we need to revoke that 511 // bias. The revocation will occur in the runtime in the slow case. 512 bind(here); 513 if (counters != NULL) { 514 atomic_incw(Address((address)counters->rebiased_lock_entry_count_addr()), 515 tmp_reg, rscratch1, rscratch2); 516 } 517 } 518 b(done); 519 520 bind(try_revoke_bias); 521 // The prototype mark in the klass doesn't have the bias bit set any 522 // more, indicating that objects of this data type are not supposed 523 // to be biased any more. We are going to try to reset the mark of 524 // this object to the prototype value and fall through to the 525 // CAS-based locking scheme. Note that if our CAS fails, it means 526 // that another thread raced us for the privilege of revoking the 527 // bias of this particular object, so it's okay to continue in the 528 // normal locking code. 529 // 530 // FIXME: due to a lack of registers we currently blow away the age 531 // bits in this situation. Should attempt to preserve them. 532 { 533 Label here, nope; 534 load_prototype_header(tmp_reg, obj_reg); 535 cmpxchgptr(swap_reg, tmp_reg, obj_reg, rscratch1, here, &nope); 536 bind(here); 537 538 // Fall through to the normal CAS-based lock, because no matter what 539 // the result of the above CAS, some thread must have succeeded in 540 // removing the bias bit from the object's header. 541 if (counters != NULL) { 542 atomic_incw(Address((address)counters->revoked_lock_entry_count_addr()), tmp_reg, 543 rscratch1, rscratch2); 544 } 545 bind(nope); 546 } 547 548 bind(cas_label); 549 550 return null_check_offset; 551 } 552 553 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 554 assert(UseBiasedLocking, "why call this otherwise?"); 555 556 // Check for biased locking unlock case, which is a no-op 557 // Note: we do not have to check the thread ID for two reasons. 558 // First, the interpreter checks for IllegalMonitorStateException at 559 // a higher level. Second, if the bias was revoked while we held the 560 // lock, the object could not be rebiased toward another thread, so 561 // the bias bit would be clear. 562 ldr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 563 andr(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place); 564 cmp(temp_reg, markOopDesc::biased_lock_pattern); 565 br(Assembler::EQ, done); 566 } 567 568 569 // added to make this compile 570 571 REGISTER_DEFINITION(Register, noreg); 572 573 static void pass_arg0(MacroAssembler* masm, Register arg) { 574 if (c_rarg0 != arg ) { 575 masm->mov(c_rarg0, arg); 576 } 577 } 578 579 static void pass_arg1(MacroAssembler* masm, Register arg) { 580 if (c_rarg1 != arg ) { 581 masm->mov(c_rarg1, arg); 582 } 583 } 584 585 static void pass_arg2(MacroAssembler* masm, Register arg) { 586 if (c_rarg2 != arg ) { 587 masm->mov(c_rarg2, arg); 588 } 589 } 590 591 static void pass_arg3(MacroAssembler* masm, Register arg) { 592 if (c_rarg3 != arg ) { 593 masm->mov(c_rarg3, arg); 594 } 595 } 596 597 void MacroAssembler::call_VM_base(Register oop_result, 598 Register java_thread, 599 Register last_java_sp, 600 address entry_point, 601 int number_of_arguments, 602 bool check_exceptions) { 603 // determine java_thread register 604 if (!java_thread->is_valid()) { 605 java_thread = rthread; 606 } 607 608 // determine last_java_sp register 609 if (!last_java_sp->is_valid()) { 610 last_java_sp = esp; 611 } 612 613 // debugging support 614 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 615 assert(java_thread == rthread, "unexpected register"); 616 #ifdef ASSERT 617 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 618 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?"); 619 #endif // ASSERT 620 621 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 622 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 623 624 // push java thread (becomes first argument of C function) 625 626 mov(c_rarg0, java_thread); 627 628 // set last Java frame before call 629 assert(last_java_sp != rfp, "can't use rfp"); 630 631 Label l; 632 set_last_Java_frame(last_java_sp, rfp, l, rscratch1); 633 634 // do the call, remove parameters 635 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l); 636 637 // reset last Java frame 638 // Only interpreter should have to clear fp 639 reset_last_Java_frame(true, true); 640 641 // C++ interp handles this in the interpreter 642 check_and_handle_popframe(java_thread); 643 check_and_handle_earlyret(java_thread); 644 645 if (check_exceptions) { 646 // check for pending exceptions (java_thread is set upon return) 647 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset()))); 648 Label ok; 649 cbz(rscratch1, ok); 650 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry())); 651 br(rscratch1); 652 bind(ok); 653 } 654 655 // get oop result if there is one and reset the value in the thread 656 if (oop_result->is_valid()) { 657 get_vm_result(oop_result, java_thread); 658 } 659 } 660 661 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 662 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 663 } 664 665 // Maybe emit a call via a trampoline. If the code cache is small 666 // trampolines won't be emitted. 667 668 address MacroAssembler::trampoline_call(Address entry, CodeBuffer *cbuf) { 669 assert(entry.rspec().type() == relocInfo::runtime_call_type 670 || entry.rspec().type() == relocInfo::opt_virtual_call_type 671 || entry.rspec().type() == relocInfo::static_call_type 672 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type"); 673 674 unsigned int start_offset = offset(); 675 if (far_branches() && !Compile::current()->in_scratch_emit_size()) { 676 address stub = emit_trampoline_stub(start_offset, entry.target()); 677 if (stub == NULL) { 678 return NULL; // CodeCache is full 679 } 680 } 681 682 if (cbuf) cbuf->set_insts_mark(); 683 relocate(entry.rspec()); 684 if (!far_branches()) { 685 bl(entry.target()); 686 } else { 687 bl(pc()); 688 } 689 // just need to return a non-null address 690 return pc(); 691 } 692 693 694 // Emit a trampoline stub for a call to a target which is too far away. 695 // 696 // code sequences: 697 // 698 // call-site: 699 // branch-and-link to <destination> or <trampoline stub> 700 // 701 // Related trampoline stub for this call site in the stub section: 702 // load the call target from the constant pool 703 // branch (LR still points to the call site above) 704 705 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset, 706 address dest) { 707 address stub = start_a_stub(Compile::MAX_stubs_size/2); 708 if (stub == NULL) { 709 return NULL; // CodeBuffer::expand failed 710 } 711 712 // Create a trampoline stub relocation which relates this trampoline stub 713 // with the call instruction at insts_call_instruction_offset in the 714 // instructions code-section. 715 align(wordSize); 716 relocate(trampoline_stub_Relocation::spec(code()->insts()->start() 717 + insts_call_instruction_offset)); 718 const int stub_start_offset = offset(); 719 720 // Now, create the trampoline stub's code: 721 // - load the call 722 // - call 723 Label target; 724 ldr(rscratch1, target); 725 br(rscratch1); 726 bind(target); 727 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset, 728 "should be"); 729 emit_int64((int64_t)dest); 730 731 const address stub_start_addr = addr_at(stub_start_offset); 732 733 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 734 735 end_a_stub(); 736 return stub; 737 } 738 739 address MacroAssembler::ic_call(address entry, jint method_index) { 740 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 741 // address const_ptr = long_constant((jlong)Universe::non_oop_word()); 742 // unsigned long offset; 743 // ldr_constant(rscratch2, const_ptr); 744 movptr(rscratch2, (uintptr_t)Universe::non_oop_word()); 745 return trampoline_call(Address(entry, rh)); 746 } 747 748 // Implementation of call_VM versions 749 750 void MacroAssembler::call_VM(Register oop_result, 751 address entry_point, 752 bool check_exceptions) { 753 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 754 } 755 756 void MacroAssembler::call_VM(Register oop_result, 757 address entry_point, 758 Register arg_1, 759 bool check_exceptions) { 760 pass_arg1(this, arg_1); 761 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 762 } 763 764 void MacroAssembler::call_VM(Register oop_result, 765 address entry_point, 766 Register arg_1, 767 Register arg_2, 768 bool check_exceptions) { 769 assert(arg_1 != c_rarg2, "smashed arg"); 770 pass_arg2(this, arg_2); 771 pass_arg1(this, arg_1); 772 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 773 } 774 775 void MacroAssembler::call_VM(Register oop_result, 776 address entry_point, 777 Register arg_1, 778 Register arg_2, 779 Register arg_3, 780 bool check_exceptions) { 781 assert(arg_1 != c_rarg3, "smashed arg"); 782 assert(arg_2 != c_rarg3, "smashed arg"); 783 pass_arg3(this, arg_3); 784 785 assert(arg_1 != c_rarg2, "smashed arg"); 786 pass_arg2(this, arg_2); 787 788 pass_arg1(this, arg_1); 789 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 790 } 791 792 void MacroAssembler::call_VM(Register oop_result, 793 Register last_java_sp, 794 address entry_point, 795 int number_of_arguments, 796 bool check_exceptions) { 797 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 798 } 799 800 void MacroAssembler::call_VM(Register oop_result, 801 Register last_java_sp, 802 address entry_point, 803 Register arg_1, 804 bool check_exceptions) { 805 pass_arg1(this, arg_1); 806 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 807 } 808 809 void MacroAssembler::call_VM(Register oop_result, 810 Register last_java_sp, 811 address entry_point, 812 Register arg_1, 813 Register arg_2, 814 bool check_exceptions) { 815 816 assert(arg_1 != c_rarg2, "smashed arg"); 817 pass_arg2(this, arg_2); 818 pass_arg1(this, arg_1); 819 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 820 } 821 822 void MacroAssembler::call_VM(Register oop_result, 823 Register last_java_sp, 824 address entry_point, 825 Register arg_1, 826 Register arg_2, 827 Register arg_3, 828 bool check_exceptions) { 829 assert(arg_1 != c_rarg3, "smashed arg"); 830 assert(arg_2 != c_rarg3, "smashed arg"); 831 pass_arg3(this, arg_3); 832 assert(arg_1 != c_rarg2, "smashed arg"); 833 pass_arg2(this, arg_2); 834 pass_arg1(this, arg_1); 835 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 836 } 837 838 839 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 840 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 841 str(zr, Address(java_thread, JavaThread::vm_result_offset())); 842 verify_oop(oop_result, "broken oop in call_VM_base"); 843 } 844 845 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 846 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 847 str(zr, Address(java_thread, JavaThread::vm_result_2_offset())); 848 } 849 850 void MacroAssembler::align(int modulus) { 851 while (offset() % modulus != 0) nop(); 852 } 853 854 // these are no-ops overridden by InterpreterMacroAssembler 855 856 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { } 857 858 void MacroAssembler::check_and_handle_popframe(Register java_thread) { } 859 860 861 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 862 Register tmp, 863 int offset) { 864 intptr_t value = *delayed_value_addr; 865 if (value != 0) 866 return RegisterOrConstant(value + offset); 867 868 // load indirectly to solve generation ordering problem 869 ldr(tmp, ExternalAddress((address) delayed_value_addr)); 870 871 if (offset != 0) 872 add(tmp, tmp, offset); 873 874 return RegisterOrConstant(tmp); 875 } 876 877 878 void MacroAssembler:: notify(int type) { 879 if (type == bytecode_start) { 880 // set_last_Java_frame(esp, rfp, (address)NULL); 881 Assembler:: notify(type); 882 // reset_last_Java_frame(true, false); 883 } 884 else 885 Assembler:: notify(type); 886 } 887 888 // Look up the method for a megamorphic invokeinterface call. 889 // The target method is determined by <intf_klass, itable_index>. 890 // The receiver klass is in recv_klass. 891 // On success, the result will be in method_result, and execution falls through. 892 // On failure, execution transfers to the given label. 893 void MacroAssembler::lookup_interface_method(Register recv_klass, 894 Register intf_klass, 895 RegisterOrConstant itable_index, 896 Register method_result, 897 Register scan_temp, 898 Label& L_no_such_interface) { 899 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 900 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 901 "caller must use same register for non-constant itable index as for method"); 902 903 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 904 int vtable_base = in_bytes(Klass::vtable_start_offset()); 905 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 906 int scan_step = itableOffsetEntry::size() * wordSize; 907 int vte_size = vtableEntry::size_in_bytes(); 908 assert(vte_size == wordSize, "else adjust times_vte_scale"); 909 910 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 911 912 // %%% Could store the aligned, prescaled offset in the klassoop. 913 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 914 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3))); 915 add(scan_temp, scan_temp, vtable_base); 916 917 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 918 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 919 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 920 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3))); 921 if (itentry_off) 922 add(recv_klass, recv_klass, itentry_off); 923 924 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 925 // if (scan->interface() == intf) { 926 // result = (klass + scan->offset() + itable_index); 927 // } 928 // } 929 Label search, found_method; 930 931 for (int peel = 1; peel >= 0; peel--) { 932 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 933 cmp(intf_klass, method_result); 934 935 if (peel) { 936 br(Assembler::EQ, found_method); 937 } else { 938 br(Assembler::NE, search); 939 // (invert the test to fall through to found_method...) 940 } 941 942 if (!peel) break; 943 944 bind(search); 945 946 // Check that the previous entry is non-null. A null entry means that 947 // the receiver class doesn't implement the interface, and wasn't the 948 // same as when the caller was compiled. 949 cbz(method_result, L_no_such_interface); 950 add(scan_temp, scan_temp, scan_step); 951 } 952 953 bind(found_method); 954 955 // Got a hit. 956 ldr(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 957 ldr(method_result, Address(recv_klass, scan_temp)); 958 } 959 960 // virtual method calling 961 void MacroAssembler::lookup_virtual_method(Register recv_klass, 962 RegisterOrConstant vtable_index, 963 Register method_result) { 964 const int base = in_bytes(Klass::vtable_start_offset()); 965 assert(vtableEntry::size() * wordSize == 8, 966 "adjust the scaling in the code below"); 967 int vtable_offset_in_bytes = base + vtableEntry::method_offset_in_bytes(); 968 969 if (vtable_index.is_register()) { 970 lea(method_result, Address(recv_klass, 971 vtable_index.as_register(), 972 Address::lsl(LogBytesPerWord))); 973 ldr(method_result, Address(method_result, vtable_offset_in_bytes)); 974 } else { 975 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize; 976 ldr(method_result, Address(recv_klass, vtable_offset_in_bytes)); 977 } 978 } 979 980 void MacroAssembler::check_klass_subtype(Register sub_klass, 981 Register super_klass, 982 Register temp_reg, 983 Label& L_success) { 984 Label L_failure; 985 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 986 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 987 bind(L_failure); 988 } 989 990 991 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 992 Register super_klass, 993 Register temp_reg, 994 Label* L_success, 995 Label* L_failure, 996 Label* L_slow_path, 997 RegisterOrConstant super_check_offset) { 998 assert_different_registers(sub_klass, super_klass, temp_reg); 999 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 1000 if (super_check_offset.is_register()) { 1001 assert_different_registers(sub_klass, super_klass, 1002 super_check_offset.as_register()); 1003 } else if (must_load_sco) { 1004 assert(temp_reg != noreg, "supply either a temp or a register offset"); 1005 } 1006 1007 Label L_fallthrough; 1008 int label_nulls = 0; 1009 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1010 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1011 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 1012 assert(label_nulls <= 1, "at most one NULL in the batch"); 1013 1014 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1015 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 1016 Address super_check_offset_addr(super_klass, sco_offset); 1017 1018 // Hacked jmp, which may only be used just before L_fallthrough. 1019 #define final_jmp(label) \ 1020 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 1021 else b(label) /*omit semi*/ 1022 1023 // If the pointers are equal, we are done (e.g., String[] elements). 1024 // This self-check enables sharing of secondary supertype arrays among 1025 // non-primary types such as array-of-interface. Otherwise, each such 1026 // type would need its own customized SSA. 1027 // We move this check to the front of the fast path because many 1028 // type checks are in fact trivially successful in this manner, 1029 // so we get a nicely predicted branch right at the start of the check. 1030 cmp(sub_klass, super_klass); 1031 br(Assembler::EQ, *L_success); 1032 1033 // Check the supertype display: 1034 if (must_load_sco) { 1035 ldrw(temp_reg, super_check_offset_addr); 1036 super_check_offset = RegisterOrConstant(temp_reg); 1037 } 1038 Address super_check_addr(sub_klass, super_check_offset); 1039 ldr(rscratch1, super_check_addr); 1040 cmp(super_klass, rscratch1); // load displayed supertype 1041 1042 // This check has worked decisively for primary supers. 1043 // Secondary supers are sought in the super_cache ('super_cache_addr'). 1044 // (Secondary supers are interfaces and very deeply nested subtypes.) 1045 // This works in the same check above because of a tricky aliasing 1046 // between the super_cache and the primary super display elements. 1047 // (The 'super_check_addr' can address either, as the case requires.) 1048 // Note that the cache is updated below if it does not help us find 1049 // what we need immediately. 1050 // So if it was a primary super, we can just fail immediately. 1051 // Otherwise, it's the slow path for us (no success at this point). 1052 1053 if (super_check_offset.is_register()) { 1054 br(Assembler::EQ, *L_success); 1055 cmp(super_check_offset.as_register(), sc_offset); 1056 if (L_failure == &L_fallthrough) { 1057 br(Assembler::EQ, *L_slow_path); 1058 } else { 1059 br(Assembler::NE, *L_failure); 1060 final_jmp(*L_slow_path); 1061 } 1062 } else if (super_check_offset.as_constant() == sc_offset) { 1063 // Need a slow path; fast failure is impossible. 1064 if (L_slow_path == &L_fallthrough) { 1065 br(Assembler::EQ, *L_success); 1066 } else { 1067 br(Assembler::NE, *L_slow_path); 1068 final_jmp(*L_success); 1069 } 1070 } else { 1071 // No slow path; it's a fast decision. 1072 if (L_failure == &L_fallthrough) { 1073 br(Assembler::EQ, *L_success); 1074 } else { 1075 br(Assembler::NE, *L_failure); 1076 final_jmp(*L_success); 1077 } 1078 } 1079 1080 bind(L_fallthrough); 1081 1082 #undef final_jmp 1083 } 1084 1085 // These two are taken from x86, but they look generally useful 1086 1087 // scans count pointer sized words at [addr] for occurence of value, 1088 // generic 1089 void MacroAssembler::repne_scan(Register addr, Register value, Register count, 1090 Register scratch) { 1091 Label Lloop, Lexit; 1092 cbz(count, Lexit); 1093 bind(Lloop); 1094 ldr(scratch, post(addr, wordSize)); 1095 cmp(value, scratch); 1096 br(EQ, Lexit); 1097 sub(count, count, 1); 1098 cbnz(count, Lloop); 1099 bind(Lexit); 1100 } 1101 1102 // scans count 4 byte words at [addr] for occurence of value, 1103 // generic 1104 void MacroAssembler::repne_scanw(Register addr, Register value, Register count, 1105 Register scratch) { 1106 Label Lloop, Lexit; 1107 cbz(count, Lexit); 1108 bind(Lloop); 1109 ldrw(scratch, post(addr, wordSize)); 1110 cmpw(value, scratch); 1111 br(EQ, Lexit); 1112 sub(count, count, 1); 1113 cbnz(count, Lloop); 1114 bind(Lexit); 1115 } 1116 1117 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 1118 Register super_klass, 1119 Register temp_reg, 1120 Register temp2_reg, 1121 Label* L_success, 1122 Label* L_failure, 1123 bool set_cond_codes) { 1124 assert_different_registers(sub_klass, super_klass, temp_reg); 1125 if (temp2_reg != noreg) 1126 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1); 1127 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 1128 1129 Label L_fallthrough; 1130 int label_nulls = 0; 1131 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 1132 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 1133 assert(label_nulls <= 1, "at most one NULL in the batch"); 1134 1135 // a couple of useful fields in sub_klass: 1136 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 1137 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 1138 Address secondary_supers_addr(sub_klass, ss_offset); 1139 Address super_cache_addr( sub_klass, sc_offset); 1140 1141 BLOCK_COMMENT("check_klass_subtype_slow_path"); 1142 1143 // Do a linear scan of the secondary super-klass chain. 1144 // This code is rarely used, so simplicity is a virtue here. 1145 // The repne_scan instruction uses fixed registers, which we must spill. 1146 // Don't worry too much about pre-existing connections with the input regs. 1147 1148 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super) 1149 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter) 1150 1151 // Get super_klass value into r0 (even if it was in r5 or r2). 1152 RegSet pushed_registers; 1153 if (!IS_A_TEMP(r2)) pushed_registers += r2; 1154 if (!IS_A_TEMP(r5)) pushed_registers += r5; 1155 1156 if (super_klass != r0 || UseCompressedOops) { 1157 if (!IS_A_TEMP(r0)) pushed_registers += r0; 1158 } 1159 1160 push(pushed_registers, sp); 1161 1162 #ifndef PRODUCT 1163 mov(rscratch2, (address)&SharedRuntime::_partial_subtype_ctr); 1164 Address pst_counter_addr(rscratch2); 1165 ldr(rscratch1, pst_counter_addr); 1166 add(rscratch1, rscratch1, 1); 1167 str(rscratch1, pst_counter_addr); 1168 #endif //PRODUCT 1169 1170 // We will consult the secondary-super array. 1171 ldr(r5, secondary_supers_addr); 1172 // Load the array length. 1173 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes())); 1174 // Skip to start of data. 1175 add(r5, r5, Array<Klass*>::base_offset_in_bytes()); 1176 1177 cmp(sp, zr); // Clear Z flag; SP is never zero 1178 // Scan R2 words at [R5] for an occurrence of R0. 1179 // Set NZ/Z based on last compare. 1180 repne_scan(r5, r0, r2, rscratch1); 1181 1182 // Unspill the temp. registers: 1183 pop(pushed_registers, sp); 1184 1185 br(Assembler::NE, *L_failure); 1186 1187 // Success. Cache the super we found and proceed in triumph. 1188 str(super_klass, super_cache_addr); 1189 1190 if (L_success != &L_fallthrough) { 1191 b(*L_success); 1192 } 1193 1194 #undef IS_A_TEMP 1195 1196 bind(L_fallthrough); 1197 } 1198 1199 1200 void MacroAssembler::verify_oop(Register reg, const char* s) { 1201 if (!VerifyOops) return; 1202 1203 // Pass register number to verify_oop_subroutine 1204 const char* b = NULL; 1205 { 1206 ResourceMark rm; 1207 stringStream ss; 1208 ss.print("verify_oop: %s: %s", reg->name(), s); 1209 b = code_string(ss.as_string()); 1210 } 1211 BLOCK_COMMENT("verify_oop {"); 1212 1213 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1214 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1215 1216 mov(r0, reg); 1217 mov(rscratch1, (address)b); 1218 1219 // call indirectly to solve generation ordering problem 1220 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1221 ldr(rscratch2, Address(rscratch2)); 1222 blr(rscratch2); 1223 1224 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1225 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1226 1227 BLOCK_COMMENT("} verify_oop"); 1228 } 1229 1230 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 1231 if (!VerifyOops) return; 1232 1233 const char* b = NULL; 1234 { 1235 ResourceMark rm; 1236 stringStream ss; 1237 ss.print("verify_oop_addr: %s", s); 1238 b = code_string(ss.as_string()); 1239 } 1240 BLOCK_COMMENT("verify_oop_addr {"); 1241 1242 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize))); 1243 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize))); 1244 1245 // addr may contain sp so we will have to adjust it based on the 1246 // pushes that we just did. 1247 if (addr.uses(sp)) { 1248 lea(r0, addr); 1249 ldr(r0, Address(r0, 4 * wordSize)); 1250 } else { 1251 ldr(r0, addr); 1252 } 1253 mov(rscratch1, (address)b); 1254 1255 // call indirectly to solve generation ordering problem 1256 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 1257 ldr(rscratch2, Address(rscratch2)); 1258 blr(rscratch2); 1259 1260 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize))); 1261 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize))); 1262 1263 BLOCK_COMMENT("} verify_oop_addr"); 1264 } 1265 1266 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 1267 int extra_slot_offset) { 1268 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 1269 int stackElementSize = Interpreter::stackElementSize; 1270 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 1271 #ifdef ASSERT 1272 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 1273 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 1274 #endif 1275 if (arg_slot.is_constant()) { 1276 return Address(esp, arg_slot.as_constant() * stackElementSize 1277 + offset); 1278 } else { 1279 add(rscratch1, esp, arg_slot.as_register(), 1280 ext::uxtx, exact_log2(stackElementSize)); 1281 return Address(rscratch1, offset); 1282 } 1283 } 1284 1285 void MacroAssembler::call_VM_leaf_base(address entry_point, 1286 int number_of_arguments, 1287 Label *retaddr) { 1288 call_VM_leaf_base1(entry_point, number_of_arguments, 0, ret_type_integral, retaddr); 1289 } 1290 1291 void MacroAssembler::call_VM_leaf_base1(address entry_point, 1292 int number_of_gp_arguments, 1293 int number_of_fp_arguments, 1294 ret_type type, 1295 Label *retaddr) { 1296 Label E, L; 1297 1298 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize))); 1299 1300 // We add 1 to number_of_arguments because the thread in arg0 is 1301 // not counted 1302 mov(rscratch1, entry_point); 1303 blrt(rscratch1, number_of_gp_arguments + 1, number_of_fp_arguments, type); 1304 if (retaddr) 1305 bind(*retaddr); 1306 1307 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize))); 1308 maybe_isb(); 1309 } 1310 1311 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1312 call_VM_leaf_base(entry_point, number_of_arguments); 1313 } 1314 1315 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1316 pass_arg0(this, arg_0); 1317 call_VM_leaf_base(entry_point, 1); 1318 } 1319 1320 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1321 pass_arg0(this, arg_0); 1322 pass_arg1(this, arg_1); 1323 call_VM_leaf_base(entry_point, 2); 1324 } 1325 1326 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, 1327 Register arg_1, Register arg_2) { 1328 pass_arg0(this, arg_0); 1329 pass_arg1(this, arg_1); 1330 pass_arg2(this, arg_2); 1331 call_VM_leaf_base(entry_point, 3); 1332 } 1333 1334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1335 pass_arg0(this, arg_0); 1336 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1337 } 1338 1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1340 1341 assert(arg_0 != c_rarg1, "smashed arg"); 1342 pass_arg1(this, arg_1); 1343 pass_arg0(this, arg_0); 1344 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1345 } 1346 1347 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1348 assert(arg_0 != c_rarg2, "smashed arg"); 1349 assert(arg_1 != c_rarg2, "smashed arg"); 1350 pass_arg2(this, arg_2); 1351 assert(arg_0 != c_rarg1, "smashed arg"); 1352 pass_arg1(this, arg_1); 1353 pass_arg0(this, arg_0); 1354 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1355 } 1356 1357 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1358 assert(arg_0 != c_rarg3, "smashed arg"); 1359 assert(arg_1 != c_rarg3, "smashed arg"); 1360 assert(arg_2 != c_rarg3, "smashed arg"); 1361 pass_arg3(this, arg_3); 1362 assert(arg_0 != c_rarg2, "smashed arg"); 1363 assert(arg_1 != c_rarg2, "smashed arg"); 1364 pass_arg2(this, arg_2); 1365 assert(arg_0 != c_rarg1, "smashed arg"); 1366 pass_arg1(this, arg_1); 1367 pass_arg0(this, arg_0); 1368 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1369 } 1370 1371 void MacroAssembler::null_check(Register reg, int offset) { 1372 if (needs_explicit_null_check(offset)) { 1373 // provoke OS NULL exception if reg = NULL by 1374 // accessing M[reg] w/o changing any registers 1375 // NOTE: this is plenty to provoke a segv 1376 ldr(zr, Address(reg)); 1377 } else { 1378 // nothing to do, (later) access of M[reg + offset] 1379 // will provoke OS NULL exception if reg = NULL 1380 } 1381 } 1382 1383 // MacroAssembler protected routines needed to implement 1384 // public methods 1385 1386 void MacroAssembler::mov(Register r, Address dest) { 1387 code_section()->relocate(pc(), dest.rspec()); 1388 u_int64_t imm64 = (u_int64_t)dest.target(); 1389 movptr(r, imm64); 1390 } 1391 1392 // Move a constant pointer into r. In AArch64 mode the virtual 1393 // address space is 48 bits in size, so we only need three 1394 // instructions to create a patchable instruction sequence that can 1395 // reach anywhere. 1396 void MacroAssembler::movptr(Register r, uintptr_t imm64) { 1397 #ifndef PRODUCT 1398 { 1399 char buffer[64]; 1400 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1401 block_comment(buffer); 1402 } 1403 #endif 1404 assert(imm64 < (1ul << 48), "48-bit overflow in address constant"); 1405 movz(r, imm64 & 0xffff); 1406 imm64 >>= 16; 1407 movk(r, imm64 & 0xffff, 16); 1408 imm64 >>= 16; 1409 movk(r, imm64 & 0xffff, 32); 1410 } 1411 1412 // Macro to mov replicated immediate to vector register. 1413 // Vd will get the following values for different arrangements in T 1414 // imm32 == hex 000000gh T8B: Vd = ghghghghghghghgh 1415 // imm32 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh 1416 // imm32 == hex 0000efgh T4H: Vd = efghefghefghefgh 1417 // imm32 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh 1418 // imm32 == hex abcdefgh T2S: Vd = abcdefghabcdefgh 1419 // imm32 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh 1420 // T1D/T2D: invalid 1421 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32) { 1422 assert(T != T1D && T != T2D, "invalid arrangement"); 1423 if (T == T8B || T == T16B) { 1424 assert((imm32 & ~0xff) == 0, "extraneous bits in unsigned imm32 (T8B/T16B)"); 1425 movi(Vd, T, imm32 & 0xff, 0); 1426 return; 1427 } 1428 u_int32_t nimm32 = ~imm32; 1429 if (T == T4H || T == T8H) { 1430 assert((imm32 & ~0xffff) == 0, "extraneous bits in unsigned imm32 (T4H/T8H)"); 1431 imm32 &= 0xffff; 1432 nimm32 &= 0xffff; 1433 } 1434 u_int32_t x = imm32; 1435 int movi_cnt = 0; 1436 int movn_cnt = 0; 1437 while (x) { if (x & 0xff) movi_cnt++; x >>= 8; } 1438 x = nimm32; 1439 while (x) { if (x & 0xff) movn_cnt++; x >>= 8; } 1440 if (movn_cnt < movi_cnt) imm32 = nimm32; 1441 unsigned lsl = 0; 1442 while (imm32 && (imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1443 if (movn_cnt < movi_cnt) 1444 mvni(Vd, T, imm32 & 0xff, lsl); 1445 else 1446 movi(Vd, T, imm32 & 0xff, lsl); 1447 imm32 >>= 8; lsl += 8; 1448 while (imm32) { 1449 while ((imm32 & 0xff) == 0) { lsl += 8; imm32 >>= 8; } 1450 if (movn_cnt < movi_cnt) 1451 bici(Vd, T, imm32 & 0xff, lsl); 1452 else 1453 orri(Vd, T, imm32 & 0xff, lsl); 1454 lsl += 8; imm32 >>= 8; 1455 } 1456 } 1457 1458 void MacroAssembler::mov_immediate64(Register dst, u_int64_t imm64) 1459 { 1460 #ifndef PRODUCT 1461 { 1462 char buffer[64]; 1463 snprintf(buffer, sizeof(buffer), "0x%"PRIX64, imm64); 1464 block_comment(buffer); 1465 } 1466 #endif 1467 if (operand_valid_for_logical_immediate(false, imm64)) { 1468 orr(dst, zr, imm64); 1469 } else { 1470 // we can use a combination of MOVZ or MOVN with 1471 // MOVK to build up the constant 1472 u_int64_t imm_h[4]; 1473 int zero_count = 0; 1474 int neg_count = 0; 1475 int i; 1476 for (i = 0; i < 4; i++) { 1477 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL); 1478 if (imm_h[i] == 0) { 1479 zero_count++; 1480 } else if (imm_h[i] == 0xffffL) { 1481 neg_count++; 1482 } 1483 } 1484 if (zero_count == 4) { 1485 // one MOVZ will do 1486 movz(dst, 0); 1487 } else if (neg_count == 4) { 1488 // one MOVN will do 1489 movn(dst, 0); 1490 } else if (zero_count == 3) { 1491 for (i = 0; i < 4; i++) { 1492 if (imm_h[i] != 0L) { 1493 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1494 break; 1495 } 1496 } 1497 } else if (neg_count == 3) { 1498 // one MOVN will do 1499 for (int i = 0; i < 4; i++) { 1500 if (imm_h[i] != 0xffffL) { 1501 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1502 break; 1503 } 1504 } 1505 } else if (zero_count == 2) { 1506 // one MOVZ and one MOVK will do 1507 for (i = 0; i < 3; i++) { 1508 if (imm_h[i] != 0L) { 1509 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1510 i++; 1511 break; 1512 } 1513 } 1514 for (;i < 4; i++) { 1515 if (imm_h[i] != 0L) { 1516 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1517 } 1518 } 1519 } else if (neg_count == 2) { 1520 // one MOVN and one MOVK will do 1521 for (i = 0; i < 4; i++) { 1522 if (imm_h[i] != 0xffffL) { 1523 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1524 i++; 1525 break; 1526 } 1527 } 1528 for (;i < 4; i++) { 1529 if (imm_h[i] != 0xffffL) { 1530 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1531 } 1532 } 1533 } else if (zero_count == 1) { 1534 // one MOVZ and two MOVKs will do 1535 for (i = 0; i < 4; i++) { 1536 if (imm_h[i] != 0L) { 1537 movz(dst, (u_int32_t)imm_h[i], (i << 4)); 1538 i++; 1539 break; 1540 } 1541 } 1542 for (;i < 4; i++) { 1543 if (imm_h[i] != 0x0L) { 1544 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1545 } 1546 } 1547 } else if (neg_count == 1) { 1548 // one MOVN and two MOVKs will do 1549 for (i = 0; i < 4; i++) { 1550 if (imm_h[i] != 0xffffL) { 1551 movn(dst, (u_int32_t)imm_h[i] ^ 0xffffL, (i << 4)); 1552 i++; 1553 break; 1554 } 1555 } 1556 for (;i < 4; i++) { 1557 if (imm_h[i] != 0xffffL) { 1558 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1559 } 1560 } 1561 } else { 1562 // use a MOVZ and 3 MOVKs (makes it easier to debug) 1563 movz(dst, (u_int32_t)imm_h[0], 0); 1564 for (i = 1; i < 4; i++) { 1565 movk(dst, (u_int32_t)imm_h[i], (i << 4)); 1566 } 1567 } 1568 } 1569 } 1570 1571 void MacroAssembler::mov_immediate32(Register dst, u_int32_t imm32) 1572 { 1573 #ifndef PRODUCT 1574 { 1575 char buffer[64]; 1576 snprintf(buffer, sizeof(buffer), "0x%"PRIX32, imm32); 1577 block_comment(buffer); 1578 } 1579 #endif 1580 if (operand_valid_for_logical_immediate(true, imm32)) { 1581 orrw(dst, zr, imm32); 1582 } else { 1583 // we can use MOVZ, MOVN or two calls to MOVK to build up the 1584 // constant 1585 u_int32_t imm_h[2]; 1586 imm_h[0] = imm32 & 0xffff; 1587 imm_h[1] = ((imm32 >> 16) & 0xffff); 1588 if (imm_h[0] == 0) { 1589 movzw(dst, imm_h[1], 16); 1590 } else if (imm_h[0] == 0xffff) { 1591 movnw(dst, imm_h[1] ^ 0xffff, 16); 1592 } else if (imm_h[1] == 0) { 1593 movzw(dst, imm_h[0], 0); 1594 } else if (imm_h[1] == 0xffff) { 1595 movnw(dst, imm_h[0] ^ 0xffff, 0); 1596 } else { 1597 // use a MOVZ and MOVK (makes it easier to debug) 1598 movzw(dst, imm_h[0], 0); 1599 movkw(dst, imm_h[1], 16); 1600 } 1601 } 1602 } 1603 1604 // Form an address from base + offset in Rd. Rd may or may 1605 // not actually be used: you must use the Address that is returned. 1606 // It is up to you to ensure that the shift provided matches the size 1607 // of your data. 1608 Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) { 1609 if (Address::offset_ok_for_immed(byte_offset, shift)) 1610 // It fits; no need for any heroics 1611 return Address(base, byte_offset); 1612 1613 // Don't do anything clever with negative or misaligned offsets 1614 unsigned mask = (1 << shift) - 1; 1615 if (byte_offset < 0 || byte_offset & mask) { 1616 mov(Rd, byte_offset); 1617 add(Rd, base, Rd); 1618 return Address(Rd); 1619 } 1620 1621 // See if we can do this with two 12-bit offsets 1622 { 1623 unsigned long word_offset = byte_offset >> shift; 1624 unsigned long masked_offset = word_offset & 0xfff000; 1625 if (Address::offset_ok_for_immed(word_offset - masked_offset) 1626 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) { 1627 add(Rd, base, masked_offset << shift); 1628 word_offset -= masked_offset; 1629 return Address(Rd, word_offset << shift); 1630 } 1631 } 1632 1633 // Do it the hard way 1634 mov(Rd, byte_offset); 1635 add(Rd, base, Rd); 1636 return Address(Rd); 1637 } 1638 1639 void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) { 1640 Label retry_load; 1641 prfm(Address(counter_addr), PSTL1STRM); 1642 bind(retry_load); 1643 // flush and load exclusive from the memory location 1644 ldxrw(tmp, counter_addr); 1645 addw(tmp, tmp, 1); 1646 // if we store+flush with no intervening write tmp wil be zero 1647 stxrw(tmp2, tmp, counter_addr); 1648 cbnzw(tmp2, retry_load); 1649 } 1650 1651 1652 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb, 1653 bool want_remainder, Register scratch) 1654 { 1655 // Full implementation of Java idiv and irem. The function 1656 // returns the (pc) offset of the div instruction - may be needed 1657 // for implicit exceptions. 1658 // 1659 // constraint : ra/rb =/= scratch 1660 // normal case 1661 // 1662 // input : ra: dividend 1663 // rb: divisor 1664 // 1665 // result: either 1666 // quotient (= ra idiv rb) 1667 // remainder (= ra irem rb) 1668 1669 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1670 1671 int idivl_offset = offset(); 1672 if (! want_remainder) { 1673 sdivw(result, ra, rb); 1674 } else { 1675 sdivw(scratch, ra, rb); 1676 Assembler::msubw(result, scratch, rb, ra); 1677 } 1678 1679 return idivl_offset; 1680 } 1681 1682 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb, 1683 bool want_remainder, Register scratch) 1684 { 1685 // Full implementation of Java ldiv and lrem. The function 1686 // returns the (pc) offset of the div instruction - may be needed 1687 // for implicit exceptions. 1688 // 1689 // constraint : ra/rb =/= scratch 1690 // normal case 1691 // 1692 // input : ra: dividend 1693 // rb: divisor 1694 // 1695 // result: either 1696 // quotient (= ra idiv rb) 1697 // remainder (= ra irem rb) 1698 1699 assert(ra != scratch && rb != scratch, "reg cannot be scratch"); 1700 1701 int idivq_offset = offset(); 1702 if (! want_remainder) { 1703 sdiv(result, ra, rb); 1704 } else { 1705 sdiv(scratch, ra, rb); 1706 Assembler::msub(result, scratch, rb, ra); 1707 } 1708 1709 return idivq_offset; 1710 } 1711 1712 void MacroAssembler::membar(Membar_mask_bits order_constraint) { 1713 address prev = pc() - NativeMembar::instruction_size; 1714 if (prev == code()->last_membar()) { 1715 NativeMembar *bar = NativeMembar_at(prev); 1716 // We are merging two memory barrier instructions. On AArch64 we 1717 // can do this simply by ORing them together. 1718 bar->set_kind(bar->get_kind() | order_constraint); 1719 BLOCK_COMMENT("merged membar"); 1720 } else { 1721 code()->set_last_membar(pc()); 1722 dmb(Assembler::barrier(order_constraint)); 1723 } 1724 } 1725 1726 // MacroAssembler routines found actually to be needed 1727 1728 void MacroAssembler::push(Register src) 1729 { 1730 str(src, Address(pre(esp, -1 * wordSize))); 1731 } 1732 1733 void MacroAssembler::pop(Register dst) 1734 { 1735 ldr(dst, Address(post(esp, 1 * wordSize))); 1736 } 1737 1738 // Note: load_unsigned_short used to be called load_unsigned_word. 1739 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 1740 int off = offset(); 1741 ldrh(dst, src); 1742 return off; 1743 } 1744 1745 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 1746 int off = offset(); 1747 ldrb(dst, src); 1748 return off; 1749 } 1750 1751 int MacroAssembler::load_signed_short(Register dst, Address src) { 1752 int off = offset(); 1753 ldrsh(dst, src); 1754 return off; 1755 } 1756 1757 int MacroAssembler::load_signed_byte(Register dst, Address src) { 1758 int off = offset(); 1759 ldrsb(dst, src); 1760 return off; 1761 } 1762 1763 int MacroAssembler::load_signed_short32(Register dst, Address src) { 1764 int off = offset(); 1765 ldrshw(dst, src); 1766 return off; 1767 } 1768 1769 int MacroAssembler::load_signed_byte32(Register dst, Address src) { 1770 int off = offset(); 1771 ldrsbw(dst, src); 1772 return off; 1773 } 1774 1775 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 1776 switch (size_in_bytes) { 1777 case 8: ldr(dst, src); break; 1778 case 4: ldrw(dst, src); break; 1779 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 1780 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 1781 default: ShouldNotReachHere(); 1782 } 1783 } 1784 1785 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 1786 switch (size_in_bytes) { 1787 case 8: str(src, dst); break; 1788 case 4: strw(src, dst); break; 1789 case 2: strh(src, dst); break; 1790 case 1: strb(src, dst); break; 1791 default: ShouldNotReachHere(); 1792 } 1793 } 1794 1795 void MacroAssembler::decrementw(Register reg, int value) 1796 { 1797 if (value < 0) { incrementw(reg, -value); return; } 1798 if (value == 0) { return; } 1799 if (value < (1 << 12)) { subw(reg, reg, value); return; } 1800 /* else */ { 1801 guarantee(reg != rscratch2, "invalid dst for register decrement"); 1802 movw(rscratch2, (unsigned)value); 1803 subw(reg, reg, rscratch2); 1804 } 1805 } 1806 1807 void MacroAssembler::decrement(Register reg, int value) 1808 { 1809 if (value < 0) { increment(reg, -value); return; } 1810 if (value == 0) { return; } 1811 if (value < (1 << 12)) { sub(reg, reg, value); return; } 1812 /* else */ { 1813 assert(reg != rscratch2, "invalid dst for register decrement"); 1814 mov(rscratch2, (unsigned long)value); 1815 sub(reg, reg, rscratch2); 1816 } 1817 } 1818 1819 void MacroAssembler::decrementw(Address dst, int value) 1820 { 1821 assert(!dst.uses(rscratch1), "invalid dst for address decrement"); 1822 ldrw(rscratch1, dst); 1823 decrementw(rscratch1, value); 1824 strw(rscratch1, dst); 1825 } 1826 1827 void MacroAssembler::decrement(Address dst, int value) 1828 { 1829 assert(!dst.uses(rscratch1), "invalid address for decrement"); 1830 ldr(rscratch1, dst); 1831 decrement(rscratch1, value); 1832 str(rscratch1, dst); 1833 } 1834 1835 void MacroAssembler::incrementw(Register reg, int value) 1836 { 1837 if (value < 0) { decrementw(reg, -value); return; } 1838 if (value == 0) { return; } 1839 if (value < (1 << 12)) { addw(reg, reg, value); return; } 1840 /* else */ { 1841 assert(reg != rscratch2, "invalid dst for register increment"); 1842 movw(rscratch2, (unsigned)value); 1843 addw(reg, reg, rscratch2); 1844 } 1845 } 1846 1847 void MacroAssembler::increment(Register reg, int value) 1848 { 1849 if (value < 0) { decrement(reg, -value); return; } 1850 if (value == 0) { return; } 1851 if (value < (1 << 12)) { add(reg, reg, value); return; } 1852 /* else */ { 1853 assert(reg != rscratch2, "invalid dst for register increment"); 1854 movw(rscratch2, (unsigned)value); 1855 add(reg, reg, rscratch2); 1856 } 1857 } 1858 1859 void MacroAssembler::incrementw(Address dst, int value) 1860 { 1861 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1862 ldrw(rscratch1, dst); 1863 incrementw(rscratch1, value); 1864 strw(rscratch1, dst); 1865 } 1866 1867 void MacroAssembler::increment(Address dst, int value) 1868 { 1869 assert(!dst.uses(rscratch1), "invalid dst for address increment"); 1870 ldr(rscratch1, dst); 1871 increment(rscratch1, value); 1872 str(rscratch1, dst); 1873 } 1874 1875 1876 void MacroAssembler::pusha() { 1877 push(0x7fffffff, sp); 1878 } 1879 1880 void MacroAssembler::popa() { 1881 pop(0x7fffffff, sp); 1882 } 1883 1884 // Push lots of registers in the bit set supplied. Don't push sp. 1885 // Return the number of words pushed 1886 int MacroAssembler::push(unsigned int bitset, Register stack) { 1887 int words_pushed = 0; 1888 1889 // Scan bitset to accumulate register pairs 1890 unsigned char regs[32]; 1891 int count = 0; 1892 for (int reg = 0; reg <= 30; reg++) { 1893 if (1 & bitset) 1894 regs[count++] = reg; 1895 bitset >>= 1; 1896 } 1897 regs[count++] = zr->encoding_nocheck(); 1898 count &= ~1; // Only push an even nuber of regs 1899 1900 if (count) { 1901 stp(as_Register(regs[0]), as_Register(regs[1]), 1902 Address(pre(stack, -count * wordSize))); 1903 words_pushed += 2; 1904 } 1905 for (int i = 2; i < count; i += 2) { 1906 stp(as_Register(regs[i]), as_Register(regs[i+1]), 1907 Address(stack, i * wordSize)); 1908 words_pushed += 2; 1909 } 1910 1911 assert(words_pushed == count, "oops, pushed != count"); 1912 1913 return count; 1914 } 1915 1916 int MacroAssembler::pop(unsigned int bitset, Register stack) { 1917 int words_pushed = 0; 1918 1919 // Scan bitset to accumulate register pairs 1920 unsigned char regs[32]; 1921 int count = 0; 1922 for (int reg = 0; reg <= 30; reg++) { 1923 if (1 & bitset) 1924 regs[count++] = reg; 1925 bitset >>= 1; 1926 } 1927 regs[count++] = zr->encoding_nocheck(); 1928 count &= ~1; 1929 1930 for (int i = 2; i < count; i += 2) { 1931 ldp(as_Register(regs[i]), as_Register(regs[i+1]), 1932 Address(stack, i * wordSize)); 1933 words_pushed += 2; 1934 } 1935 if (count) { 1936 ldp(as_Register(regs[0]), as_Register(regs[1]), 1937 Address(post(stack, count * wordSize))); 1938 words_pushed += 2; 1939 } 1940 1941 assert(words_pushed == count, "oops, pushed != count"); 1942 1943 return count; 1944 } 1945 #ifdef ASSERT 1946 void MacroAssembler::verify_heapbase(const char* msg) { 1947 #if 0 1948 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed"); 1949 assert (Universe::heap() != NULL, "java heap should be initialized"); 1950 if (CheckCompressedOops) { 1951 Label ok; 1952 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1 1953 cmpptr(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 1954 br(Assembler::EQ, ok); 1955 stop(msg); 1956 bind(ok); 1957 pop(1 << rscratch1->encoding(), sp); 1958 } 1959 #endif 1960 } 1961 #endif 1962 1963 void MacroAssembler::stop(const char* msg) { 1964 address ip = pc(); 1965 pusha(); 1966 mov(c_rarg0, (address)msg); 1967 mov(c_rarg1, (address)ip); 1968 mov(c_rarg2, sp); 1969 mov(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64)); 1970 // call(c_rarg3); 1971 blrt(c_rarg3, 3, 0, 1); 1972 hlt(0); 1973 } 1974 1975 // If a constant does not fit in an immediate field, generate some 1976 // number of MOV instructions and then perform the operation. 1977 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm, 1978 add_sub_imm_insn insn1, 1979 add_sub_reg_insn insn2) { 1980 assert(Rd != zr, "Rd = zr and not setting flags?"); 1981 if (operand_valid_for_add_sub_immediate((int)imm)) { 1982 (this->*insn1)(Rd, Rn, imm); 1983 } else { 1984 if (uabs(imm) < (1 << 24)) { 1985 (this->*insn1)(Rd, Rn, imm & -(1 << 12)); 1986 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1)); 1987 } else { 1988 assert_different_registers(Rd, Rn); 1989 mov(Rd, (uint64_t)imm); 1990 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 1991 } 1992 } 1993 } 1994 1995 // Seperate vsn which sets the flags. Optimisations are more restricted 1996 // because we must set the flags correctly. 1997 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm, 1998 add_sub_imm_insn insn1, 1999 add_sub_reg_insn insn2) { 2000 if (operand_valid_for_add_sub_immediate((int)imm)) { 2001 (this->*insn1)(Rd, Rn, imm); 2002 } else { 2003 assert_different_registers(Rd, Rn); 2004 assert(Rd != zr, "overflow in immediate operand"); 2005 mov(Rd, (uint64_t)imm); 2006 (this->*insn2)(Rd, Rn, Rd, LSL, 0); 2007 } 2008 } 2009 2010 2011 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) { 2012 if (increment.is_register()) { 2013 add(Rd, Rn, increment.as_register()); 2014 } else { 2015 add(Rd, Rn, increment.as_constant()); 2016 } 2017 } 2018 2019 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) { 2020 if (increment.is_register()) { 2021 addw(Rd, Rn, increment.as_register()); 2022 } else { 2023 addw(Rd, Rn, increment.as_constant()); 2024 } 2025 } 2026 2027 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) { 2028 if (decrement.is_register()) { 2029 sub(Rd, Rn, decrement.as_register()); 2030 } else { 2031 sub(Rd, Rn, decrement.as_constant()); 2032 } 2033 } 2034 2035 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) { 2036 if (decrement.is_register()) { 2037 subw(Rd, Rn, decrement.as_register()); 2038 } else { 2039 subw(Rd, Rn, decrement.as_constant()); 2040 } 2041 } 2042 2043 void MacroAssembler::reinit_heapbase() 2044 { 2045 if (UseCompressedOops) { 2046 if (Universe::is_fully_initialized()) { 2047 mov(rheapbase, Universe::narrow_ptrs_base()); 2048 } else { 2049 lea(rheapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 2050 ldr(rheapbase, Address(rheapbase)); 2051 } 2052 } 2053 } 2054 2055 // this simulates the behaviour of the x86 cmpxchg instruction using a 2056 // load linked/store conditional pair. we use the acquire/release 2057 // versions of these instructions so that we flush pending writes as 2058 // per Java semantics. 2059 2060 // n.b the x86 version assumes the old value to be compared against is 2061 // in rax and updates rax with the value located in memory if the 2062 // cmpxchg fails. we supply a register for the old value explicitly 2063 2064 // the aarch64 load linked/store conditional instructions do not 2065 // accept an offset. so, unlike x86, we must provide a plain register 2066 // to identify the memory word to be compared/exchanged rather than a 2067 // register+offset Address. 2068 2069 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, 2070 Label &succeed, Label *fail) { 2071 // oldv holds comparison value 2072 // newv holds value to write in exchange 2073 // addr identifies memory word to compare against/update 2074 if (UseLSE) { 2075 mov(tmp, oldv); 2076 casal(Assembler::xword, oldv, newv, addr); 2077 cmp(tmp, oldv); 2078 br(Assembler::EQ, succeed); 2079 membar(AnyAny); 2080 } else { 2081 Label retry_load, nope; 2082 prfm(Address(addr), PSTL1STRM); 2083 bind(retry_load); 2084 // flush and load exclusive from the memory location 2085 // and fail if it is not what we expect 2086 ldaxr(tmp, addr); 2087 cmp(tmp, oldv); 2088 br(Assembler::NE, nope); 2089 // if we store+flush with no intervening write tmp wil be zero 2090 stlxr(tmp, newv, addr); 2091 cbzw(tmp, succeed); 2092 // retry so we only ever return after a load fails to compare 2093 // ensures we don't return a stale value after a failed write. 2094 b(retry_load); 2095 // if the memory word differs we return it in oldv and signal a fail 2096 bind(nope); 2097 membar(AnyAny); 2098 mov(oldv, tmp); 2099 } 2100 if (fail) 2101 b(*fail); 2102 } 2103 2104 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp, 2105 Label &succeed, Label *fail) { 2106 // oldv holds comparison value 2107 // newv holds value to write in exchange 2108 // addr identifies memory word to compare against/update 2109 // tmp returns 0/1 for success/failure 2110 if (UseLSE) { 2111 mov(tmp, oldv); 2112 casal(Assembler::word, oldv, newv, addr); 2113 cmp(tmp, oldv); 2114 br(Assembler::EQ, succeed); 2115 membar(AnyAny); 2116 } else { 2117 Label retry_load, nope; 2118 prfm(Address(addr), PSTL1STRM); 2119 bind(retry_load); 2120 // flush and load exclusive from the memory location 2121 // and fail if it is not what we expect 2122 ldaxrw(tmp, addr); 2123 cmp(tmp, oldv); 2124 br(Assembler::NE, nope); 2125 // if we store+flush with no intervening write tmp wil be zero 2126 stlxrw(tmp, newv, addr); 2127 cbzw(tmp, succeed); 2128 // retry so we only ever return after a load fails to compare 2129 // ensures we don't return a stale value after a failed write. 2130 b(retry_load); 2131 // if the memory word differs we return it in oldv and signal a fail 2132 bind(nope); 2133 membar(AnyAny); 2134 mov(oldv, tmp); 2135 } 2136 if (fail) 2137 b(*fail); 2138 } 2139 2140 // A generic CAS; success or failure is in the EQ flag. 2141 void MacroAssembler::cmpxchg(Register addr, Register expected, 2142 Register new_val, 2143 enum operand_size size, 2144 bool acquire, bool release, 2145 Register tmp) { 2146 if (UseLSE) { 2147 mov(tmp, expected); 2148 lse_cas(tmp, new_val, addr, size, acquire, release, /*not_pair*/ true); 2149 cmp(tmp, expected); 2150 } else { 2151 BLOCK_COMMENT("cmpxchg {"); 2152 Label retry_load, done; 2153 prfm(Address(addr), PSTL1STRM); 2154 bind(retry_load); 2155 load_exclusive(tmp, addr, size, acquire); 2156 if (size == xword) 2157 cmp(tmp, expected); 2158 else 2159 cmpw(tmp, expected); 2160 br(Assembler::NE, done); 2161 store_exclusive(tmp, new_val, addr, size, release); 2162 cbnzw(tmp, retry_load); 2163 bind(done); 2164 BLOCK_COMMENT("} cmpxchg"); 2165 } 2166 } 2167 2168 static bool different(Register a, RegisterOrConstant b, Register c) { 2169 if (b.is_constant()) 2170 return a != c; 2171 else 2172 return a != b.as_register() && a != c && b.as_register() != c; 2173 } 2174 2175 #define ATOMIC_OP(LDXR, OP, IOP, STXR) \ 2176 void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Register addr) { \ 2177 Register result = rscratch2; \ 2178 if (prev->is_valid()) \ 2179 result = different(prev, incr, addr) ? prev : rscratch2; \ 2180 \ 2181 Label retry_load; \ 2182 prfm(Address(addr), PSTL1STRM); \ 2183 bind(retry_load); \ 2184 LDXR(result, addr); \ 2185 OP(rscratch1, result, incr); \ 2186 STXR(rscratch2, rscratch1, addr); \ 2187 cbnzw(rscratch2, retry_load); \ 2188 if (prev->is_valid() && prev != result) { \ 2189 IOP(prev, rscratch1, incr); \ 2190 } \ 2191 } 2192 2193 ATOMIC_OP(ldxr, add, sub, stxr) 2194 ATOMIC_OP(ldxrw, addw, subw, stxrw) 2195 2196 #undef ATOMIC_OP 2197 2198 #define ATOMIC_XCHG(OP, LDXR, STXR) \ 2199 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \ 2200 Register result = rscratch2; \ 2201 if (prev->is_valid()) \ 2202 result = different(prev, newv, addr) ? prev : rscratch2; \ 2203 \ 2204 Label retry_load; \ 2205 prfm(Address(addr), PSTL1STRM); \ 2206 bind(retry_load); \ 2207 LDXR(result, addr); \ 2208 STXR(rscratch1, newv, addr); \ 2209 cbnzw(rscratch1, retry_load); \ 2210 if (prev->is_valid() && prev != result) \ 2211 mov(prev, result); \ 2212 } 2213 2214 ATOMIC_XCHG(xchg, ldxr, stxr) 2215 ATOMIC_XCHG(xchgw, ldxrw, stxrw) 2216 2217 #undef ATOMIC_XCHG 2218 2219 void MacroAssembler::incr_allocated_bytes(Register thread, 2220 Register var_size_in_bytes, 2221 int con_size_in_bytes, 2222 Register t1) { 2223 if (!thread->is_valid()) { 2224 thread = rthread; 2225 } 2226 assert(t1->is_valid(), "need temp reg"); 2227 2228 ldr(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2229 if (var_size_in_bytes->is_valid()) { 2230 add(t1, t1, var_size_in_bytes); 2231 } else { 2232 add(t1, t1, con_size_in_bytes); 2233 } 2234 str(t1, Address(thread, in_bytes(JavaThread::allocated_bytes_offset()))); 2235 } 2236 2237 #ifndef PRODUCT 2238 extern "C" void findpc(intptr_t x); 2239 #endif 2240 2241 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) 2242 { 2243 // In order to get locks to work, we need to fake a in_VM state 2244 if (ShowMessageBoxOnError ) { 2245 JavaThread* thread = JavaThread::current(); 2246 JavaThreadState saved_state = thread->thread_state(); 2247 thread->set_thread_state(_thread_in_vm); 2248 #ifndef PRODUCT 2249 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 2250 ttyLocker ttyl; 2251 BytecodeCounter::print(); 2252 } 2253 #endif 2254 if (os::message_box(msg, "Execution stopped, print registers?")) { 2255 ttyLocker ttyl; 2256 tty->print_cr(" pc = 0x%016lx", pc); 2257 #ifndef PRODUCT 2258 tty->cr(); 2259 findpc(pc); 2260 tty->cr(); 2261 #endif 2262 tty->print_cr(" r0 = 0x%016lx", regs[0]); 2263 tty->print_cr(" r1 = 0x%016lx", regs[1]); 2264 tty->print_cr(" r2 = 0x%016lx", regs[2]); 2265 tty->print_cr(" r3 = 0x%016lx", regs[3]); 2266 tty->print_cr(" r4 = 0x%016lx", regs[4]); 2267 tty->print_cr(" r5 = 0x%016lx", regs[5]); 2268 tty->print_cr(" r6 = 0x%016lx", regs[6]); 2269 tty->print_cr(" r7 = 0x%016lx", regs[7]); 2270 tty->print_cr(" r8 = 0x%016lx", regs[8]); 2271 tty->print_cr(" r9 = 0x%016lx", regs[9]); 2272 tty->print_cr("r10 = 0x%016lx", regs[10]); 2273 tty->print_cr("r11 = 0x%016lx", regs[11]); 2274 tty->print_cr("r12 = 0x%016lx", regs[12]); 2275 tty->print_cr("r13 = 0x%016lx", regs[13]); 2276 tty->print_cr("r14 = 0x%016lx", regs[14]); 2277 tty->print_cr("r15 = 0x%016lx", regs[15]); 2278 tty->print_cr("r16 = 0x%016lx", regs[16]); 2279 tty->print_cr("r17 = 0x%016lx", regs[17]); 2280 tty->print_cr("r18 = 0x%016lx", regs[18]); 2281 tty->print_cr("r19 = 0x%016lx", regs[19]); 2282 tty->print_cr("r20 = 0x%016lx", regs[20]); 2283 tty->print_cr("r21 = 0x%016lx", regs[21]); 2284 tty->print_cr("r22 = 0x%016lx", regs[22]); 2285 tty->print_cr("r23 = 0x%016lx", regs[23]); 2286 tty->print_cr("r24 = 0x%016lx", regs[24]); 2287 tty->print_cr("r25 = 0x%016lx", regs[25]); 2288 tty->print_cr("r26 = 0x%016lx", regs[26]); 2289 tty->print_cr("r27 = 0x%016lx", regs[27]); 2290 tty->print_cr("r28 = 0x%016lx", regs[28]); 2291 tty->print_cr("r30 = 0x%016lx", regs[30]); 2292 tty->print_cr("r31 = 0x%016lx", regs[31]); 2293 BREAKPOINT; 2294 } 2295 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 2296 } else { 2297 ttyLocker ttyl; 2298 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 2299 msg); 2300 assert(false, "DEBUG MESSAGE: %s", msg); 2301 } 2302 } 2303 2304 #ifdef BUILTIN_SIM 2305 // routine to generate an x86 prolog for a stub function which 2306 // bootstraps into the generated ARM code which directly follows the 2307 // stub 2308 // 2309 // the argument encodes the number of general and fp registers 2310 // passed by the caller and the callng convention (currently just 2311 // the number of general registers and assumes C argument passing) 2312 2313 extern "C" { 2314 int aarch64_stub_prolog_size(); 2315 void aarch64_stub_prolog(); 2316 void aarch64_prolog(); 2317 } 2318 2319 void MacroAssembler::c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, 2320 address *prolog_ptr) 2321 { 2322 int calltype = (((ret_type & 0x3) << 8) | 2323 ((fp_arg_count & 0xf) << 4) | 2324 (gp_arg_count & 0xf)); 2325 2326 // the addresses for the x86 to ARM entry code we need to use 2327 address start = pc(); 2328 // printf("start = %lx\n", start); 2329 int byteCount = aarch64_stub_prolog_size(); 2330 // printf("byteCount = %x\n", byteCount); 2331 int instructionCount = (byteCount + 3)/ 4; 2332 // printf("instructionCount = %x\n", instructionCount); 2333 for (int i = 0; i < instructionCount; i++) { 2334 nop(); 2335 } 2336 2337 memcpy(start, (void*)aarch64_stub_prolog, byteCount); 2338 2339 // write the address of the setup routine and the call format at the 2340 // end of into the copied code 2341 u_int64_t *patch_end = (u_int64_t *)(start + byteCount); 2342 if (prolog_ptr) 2343 patch_end[-2] = (u_int64_t)prolog_ptr; 2344 patch_end[-1] = calltype; 2345 } 2346 #endif 2347 2348 void MacroAssembler::push_call_clobbered_registers() { 2349 push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2350 2351 // Push v0-v7, v16-v31. 2352 for (int i = 30; i >= 0; i -= 2) { 2353 if (i <= v7->encoding() || i >= v16->encoding()) { 2354 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2355 Address(pre(sp, -2 * wordSize))); 2356 } 2357 } 2358 } 2359 2360 void MacroAssembler::pop_call_clobbered_registers() { 2361 2362 for (int i = 0; i < 32; i += 2) { 2363 if (i <= v7->encoding() || i >= v16->encoding()) { 2364 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2365 Address(post(sp, 2 * wordSize))); 2366 } 2367 } 2368 2369 pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); 2370 } 2371 2372 void MacroAssembler::push_CPU_state(bool save_vectors) { 2373 push(0x3fffffff, sp); // integer registers except lr & sp 2374 2375 if (!save_vectors) { 2376 for (int i = 30; i >= 0; i -= 2) 2377 stpd(as_FloatRegister(i), as_FloatRegister(i+1), 2378 Address(pre(sp, -2 * wordSize))); 2379 } else { 2380 for (int i = 30; i >= 0; i -= 2) 2381 stpq(as_FloatRegister(i), as_FloatRegister(i+1), 2382 Address(pre(sp, -4 * wordSize))); 2383 } 2384 } 2385 2386 void MacroAssembler::pop_CPU_state(bool restore_vectors) { 2387 if (!restore_vectors) { 2388 for (int i = 0; i < 32; i += 2) 2389 ldpd(as_FloatRegister(i), as_FloatRegister(i+1), 2390 Address(post(sp, 2 * wordSize))); 2391 } else { 2392 for (int i = 0; i < 32; i += 2) 2393 ldpq(as_FloatRegister(i), as_FloatRegister(i+1), 2394 Address(post(sp, 4 * wordSize))); 2395 } 2396 2397 pop(0x3fffffff, sp); // integer registers except lr & sp 2398 } 2399 2400 /** 2401 * Helpers for multiply_to_len(). 2402 */ 2403 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo, 2404 Register src1, Register src2) { 2405 adds(dest_lo, dest_lo, src1); 2406 adc(dest_hi, dest_hi, zr); 2407 adds(dest_lo, dest_lo, src2); 2408 adc(final_dest_hi, dest_hi, zr); 2409 } 2410 2411 // Generate an address from (r + r1 extend offset). "size" is the 2412 // size of the operand. The result may be in rscratch2. 2413 Address MacroAssembler::offsetted_address(Register r, Register r1, 2414 Address::extend ext, int offset, int size) { 2415 if (offset || (ext.shift() % size != 0)) { 2416 lea(rscratch2, Address(r, r1, ext)); 2417 return Address(rscratch2, offset); 2418 } else { 2419 return Address(r, r1, ext); 2420 } 2421 } 2422 2423 Address MacroAssembler::spill_address(int size, int offset, Register tmp) 2424 { 2425 assert(offset >= 0, "spill to negative address?"); 2426 // Offset reachable ? 2427 // Not aligned - 9 bits signed offset 2428 // Aligned - 12 bits unsigned offset shifted 2429 Register base = sp; 2430 if ((offset & (size-1)) && offset >= (1<<8)) { 2431 add(tmp, base, offset & ((1<<12)-1)); 2432 base = tmp; 2433 offset &= -1<<12; 2434 } 2435 2436 if (offset >= (1<<12) * size) { 2437 add(tmp, base, offset & (((1<<12)-1)<<12)); 2438 base = tmp; 2439 offset &= ~(((1<<12)-1)<<12); 2440 } 2441 2442 return Address(base, offset); 2443 } 2444 2445 /** 2446 * Multiply 64 bit by 64 bit first loop. 2447 */ 2448 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 2449 Register y, Register y_idx, Register z, 2450 Register carry, Register product, 2451 Register idx, Register kdx) { 2452 // 2453 // jlong carry, x[], y[], z[]; 2454 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2455 // huge_128 product = y[idx] * x[xstart] + carry; 2456 // z[kdx] = (jlong)product; 2457 // carry = (jlong)(product >>> 64); 2458 // } 2459 // z[xstart] = carry; 2460 // 2461 2462 Label L_first_loop, L_first_loop_exit; 2463 Label L_one_x, L_one_y, L_multiply; 2464 2465 subsw(xstart, xstart, 1); 2466 br(Assembler::MI, L_one_x); 2467 2468 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt))); 2469 ldr(x_xstart, Address(rscratch1)); 2470 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian 2471 2472 bind(L_first_loop); 2473 subsw(idx, idx, 1); 2474 br(Assembler::MI, L_first_loop_exit); 2475 subsw(idx, idx, 1); 2476 br(Assembler::MI, L_one_y); 2477 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2478 ldr(y_idx, Address(rscratch1)); 2479 ror(y_idx, y_idx, 32); // convert big-endian to little-endian 2480 bind(L_multiply); 2481 2482 // AArch64 has a multiply-accumulate instruction that we can't use 2483 // here because it has no way to process carries, so we have to use 2484 // separate add and adc instructions. Bah. 2485 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product 2486 mul(product, x_xstart, y_idx); 2487 adds(product, product, carry); 2488 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product 2489 2490 subw(kdx, kdx, 2); 2491 ror(product, product, 32); // back to big-endian 2492 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong)); 2493 2494 b(L_first_loop); 2495 2496 bind(L_one_y); 2497 ldrw(y_idx, Address(y, 0)); 2498 b(L_multiply); 2499 2500 bind(L_one_x); 2501 ldrw(x_xstart, Address(x, 0)); 2502 b(L_first_loop); 2503 2504 bind(L_first_loop_exit); 2505 } 2506 2507 /** 2508 * Multiply 128 bit by 128. Unrolled inner loop. 2509 * 2510 */ 2511 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z, 2512 Register carry, Register carry2, 2513 Register idx, Register jdx, 2514 Register yz_idx1, Register yz_idx2, 2515 Register tmp, Register tmp3, Register tmp4, 2516 Register tmp6, Register product_hi) { 2517 2518 // jlong carry, x[], y[], z[]; 2519 // int kdx = ystart+1; 2520 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 2521 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry; 2522 // jlong carry2 = (jlong)(tmp3 >>> 64); 2523 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2; 2524 // carry = (jlong)(tmp4 >>> 64); 2525 // z[kdx+idx+1] = (jlong)tmp3; 2526 // z[kdx+idx] = (jlong)tmp4; 2527 // } 2528 // idx += 2; 2529 // if (idx > 0) { 2530 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry; 2531 // z[kdx+idx] = (jlong)yz_idx1; 2532 // carry = (jlong)(yz_idx1 >>> 64); 2533 // } 2534 // 2535 2536 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 2537 2538 lsrw(jdx, idx, 2); 2539 2540 bind(L_third_loop); 2541 2542 subsw(jdx, jdx, 1); 2543 br(Assembler::MI, L_third_loop_exit); 2544 subw(idx, idx, 4); 2545 2546 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2547 2548 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0)); 2549 2550 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2551 2552 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 2553 ror(yz_idx2, yz_idx2, 32); 2554 2555 ldp(rscratch2, rscratch1, Address(tmp6, 0)); 2556 2557 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2558 umulh(tmp4, product_hi, yz_idx1); 2559 2560 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian 2561 ror(rscratch2, rscratch2, 32); 2562 2563 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp 2564 umulh(carry2, product_hi, yz_idx2); 2565 2566 // propagate sum of both multiplications into carry:tmp4:tmp3 2567 adds(tmp3, tmp3, carry); 2568 adc(tmp4, tmp4, zr); 2569 adds(tmp3, tmp3, rscratch1); 2570 adcs(tmp4, tmp4, tmp); 2571 adc(carry, carry2, zr); 2572 adds(tmp4, tmp4, rscratch2); 2573 adc(carry, carry, zr); 2574 2575 ror(tmp3, tmp3, 32); // convert little-endian to big-endian 2576 ror(tmp4, tmp4, 32); 2577 stp(tmp4, tmp3, Address(tmp6, 0)); 2578 2579 b(L_third_loop); 2580 bind (L_third_loop_exit); 2581 2582 andw (idx, idx, 0x3); 2583 cbz(idx, L_post_third_loop_done); 2584 2585 Label L_check_1; 2586 subsw(idx, idx, 2); 2587 br(Assembler::MI, L_check_1); 2588 2589 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2590 ldr(yz_idx1, Address(rscratch1, 0)); 2591 ror(yz_idx1, yz_idx1, 32); 2592 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3 2593 umulh(tmp4, product_hi, yz_idx1); 2594 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2595 ldr(yz_idx2, Address(rscratch1, 0)); 2596 ror(yz_idx2, yz_idx2, 32); 2597 2598 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2); 2599 2600 ror(tmp3, tmp3, 32); 2601 str(tmp3, Address(rscratch1, 0)); 2602 2603 bind (L_check_1); 2604 2605 andw (idx, idx, 0x1); 2606 subsw(idx, idx, 1); 2607 br(Assembler::MI, L_post_third_loop_done); 2608 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt))); 2609 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3 2610 umulh(carry2, tmp4, product_hi); 2611 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2612 2613 add2_with_carry(carry2, tmp3, tmp4, carry); 2614 2615 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt))); 2616 extr(carry, carry2, tmp3, 32); 2617 2618 bind(L_post_third_loop_done); 2619 } 2620 2621 /** 2622 * Code for BigInteger::multiplyToLen() instrinsic. 2623 * 2624 * r0: x 2625 * r1: xlen 2626 * r2: y 2627 * r3: ylen 2628 * r4: z 2629 * r5: zlen 2630 * r10: tmp1 2631 * r11: tmp2 2632 * r12: tmp3 2633 * r13: tmp4 2634 * r14: tmp5 2635 * r15: tmp6 2636 * r16: tmp7 2637 * 2638 */ 2639 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, 2640 Register z, Register zlen, 2641 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 2642 Register tmp5, Register tmp6, Register product_hi) { 2643 2644 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6); 2645 2646 const Register idx = tmp1; 2647 const Register kdx = tmp2; 2648 const Register xstart = tmp3; 2649 2650 const Register y_idx = tmp4; 2651 const Register carry = tmp5; 2652 const Register product = xlen; 2653 const Register x_xstart = zlen; // reuse register 2654 2655 // First Loop. 2656 // 2657 // final static long LONG_MASK = 0xffffffffL; 2658 // int xstart = xlen - 1; 2659 // int ystart = ylen - 1; 2660 // long carry = 0; 2661 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 2662 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 2663 // z[kdx] = (int)product; 2664 // carry = product >>> 32; 2665 // } 2666 // z[xstart] = (int)carry; 2667 // 2668 2669 movw(idx, ylen); // idx = ylen; 2670 movw(kdx, zlen); // kdx = xlen+ylen; 2671 mov(carry, zr); // carry = 0; 2672 2673 Label L_done; 2674 2675 movw(xstart, xlen); 2676 subsw(xstart, xstart, 1); 2677 br(Assembler::MI, L_done); 2678 2679 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 2680 2681 Label L_second_loop; 2682 cbzw(kdx, L_second_loop); 2683 2684 Label L_carry; 2685 subw(kdx, kdx, 1); 2686 cbzw(kdx, L_carry); 2687 2688 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2689 lsr(carry, carry, 32); 2690 subw(kdx, kdx, 1); 2691 2692 bind(L_carry); 2693 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt))); 2694 2695 // Second and third (nested) loops. 2696 // 2697 // for (int i = xstart-1; i >= 0; i--) { // Second loop 2698 // carry = 0; 2699 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 2700 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 2701 // (z[k] & LONG_MASK) + carry; 2702 // z[k] = (int)product; 2703 // carry = product >>> 32; 2704 // } 2705 // z[i] = (int)carry; 2706 // } 2707 // 2708 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi 2709 2710 const Register jdx = tmp1; 2711 2712 bind(L_second_loop); 2713 mov(carry, zr); // carry = 0; 2714 movw(jdx, ylen); // j = ystart+1 2715 2716 subsw(xstart, xstart, 1); // i = xstart-1; 2717 br(Assembler::MI, L_done); 2718 2719 str(z, Address(pre(sp, -4 * wordSize))); 2720 2721 Label L_last_x; 2722 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j 2723 subsw(xstart, xstart, 1); // i = xstart-1; 2724 br(Assembler::MI, L_last_x); 2725 2726 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt))); 2727 ldr(product_hi, Address(rscratch1)); 2728 ror(product_hi, product_hi, 32); // convert big-endian to little-endian 2729 2730 Label L_third_loop_prologue; 2731 bind(L_third_loop_prologue); 2732 2733 str(ylen, Address(sp, wordSize)); 2734 stp(x, xstart, Address(sp, 2 * wordSize)); 2735 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product, 2736 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi); 2737 ldp(z, ylen, Address(post(sp, 2 * wordSize))); 2738 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen 2739 2740 addw(tmp3, xlen, 1); 2741 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2742 subsw(tmp3, tmp3, 1); 2743 br(Assembler::MI, L_done); 2744 2745 lsr(carry, carry, 32); 2746 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt))); 2747 b(L_second_loop); 2748 2749 // Next infrequent code is moved outside loops. 2750 bind(L_last_x); 2751 ldrw(product_hi, Address(x, 0)); 2752 b(L_third_loop_prologue); 2753 2754 bind(L_done); 2755 } 2756 2757 /** 2758 * Emits code to update CRC-32 with a byte value according to constants in table 2759 * 2760 * @param [in,out]crc Register containing the crc. 2761 * @param [in]val Register containing the byte to fold into the CRC. 2762 * @param [in]table Register containing the table of crc constants. 2763 * 2764 * uint32_t crc; 2765 * val = crc_table[(val ^ crc) & 0xFF]; 2766 * crc = val ^ (crc >> 8); 2767 * 2768 */ 2769 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 2770 eor(val, val, crc); 2771 andr(val, val, 0xff); 2772 ldrw(val, Address(table, val, Address::lsl(2))); 2773 eor(crc, val, crc, Assembler::LSR, 8); 2774 } 2775 2776 /** 2777 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3 2778 * 2779 * @param [in,out]crc Register containing the crc. 2780 * @param [in]v Register containing the 32-bit to fold into the CRC. 2781 * @param [in]table0 Register containing table 0 of crc constants. 2782 * @param [in]table1 Register containing table 1 of crc constants. 2783 * @param [in]table2 Register containing table 2 of crc constants. 2784 * @param [in]table3 Register containing table 3 of crc constants. 2785 * 2786 * uint32_t crc; 2787 * v = crc ^ v 2788 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24] 2789 * 2790 */ 2791 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp, 2792 Register table0, Register table1, Register table2, Register table3, 2793 bool upper) { 2794 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0); 2795 uxtb(tmp, v); 2796 ldrw(crc, Address(table3, tmp, Address::lsl(2))); 2797 ubfx(tmp, v, 8, 8); 2798 ldrw(tmp, Address(table2, tmp, Address::lsl(2))); 2799 eor(crc, crc, tmp); 2800 ubfx(tmp, v, 16, 8); 2801 ldrw(tmp, Address(table1, tmp, Address::lsl(2))); 2802 eor(crc, crc, tmp); 2803 ubfx(tmp, v, 24, 8); 2804 ldrw(tmp, Address(table0, tmp, Address::lsl(2))); 2805 eor(crc, crc, tmp); 2806 } 2807 2808 /** 2809 * @param crc register containing existing CRC (32-bit) 2810 * @param buf register pointing to input byte buffer (byte*) 2811 * @param len register containing number of bytes 2812 * @param table register that will contain address of CRC table 2813 * @param tmp scratch register 2814 */ 2815 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, 2816 Register table0, Register table1, Register table2, Register table3, 2817 Register tmp, Register tmp2, Register tmp3) { 2818 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit; 2819 unsigned long offset; 2820 2821 ornw(crc, zr, crc); 2822 2823 if (UseCRC32) { 2824 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 2825 2826 subs(len, len, 64); 2827 br(Assembler::GE, CRC_by64_loop); 2828 adds(len, len, 64-4); 2829 br(Assembler::GE, CRC_by4_loop); 2830 adds(len, len, 4); 2831 br(Assembler::GT, CRC_by1_loop); 2832 b(L_exit); 2833 2834 BIND(CRC_by4_loop); 2835 ldrw(tmp, Address(post(buf, 4))); 2836 subs(len, len, 4); 2837 crc32w(crc, crc, tmp); 2838 br(Assembler::GE, CRC_by4_loop); 2839 adds(len, len, 4); 2840 br(Assembler::LE, L_exit); 2841 BIND(CRC_by1_loop); 2842 ldrb(tmp, Address(post(buf, 1))); 2843 subs(len, len, 1); 2844 crc32b(crc, crc, tmp); 2845 br(Assembler::GT, CRC_by1_loop); 2846 b(L_exit); 2847 2848 align(CodeEntryAlignment); 2849 BIND(CRC_by64_loop); 2850 subs(len, len, 64); 2851 ldp(tmp, tmp3, Address(post(buf, 16))); 2852 crc32x(crc, crc, tmp); 2853 crc32x(crc, crc, tmp3); 2854 ldp(tmp, tmp3, Address(post(buf, 16))); 2855 crc32x(crc, crc, tmp); 2856 crc32x(crc, crc, tmp3); 2857 ldp(tmp, tmp3, Address(post(buf, 16))); 2858 crc32x(crc, crc, tmp); 2859 crc32x(crc, crc, tmp3); 2860 ldp(tmp, tmp3, Address(post(buf, 16))); 2861 crc32x(crc, crc, tmp); 2862 crc32x(crc, crc, tmp3); 2863 br(Assembler::GE, CRC_by64_loop); 2864 adds(len, len, 64-4); 2865 br(Assembler::GE, CRC_by4_loop); 2866 adds(len, len, 4); 2867 br(Assembler::GT, CRC_by1_loop); 2868 BIND(L_exit); 2869 ornw(crc, zr, crc); 2870 return; 2871 } 2872 2873 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2874 if (offset) add(table0, table0, offset); 2875 add(table1, table0, 1*256*sizeof(juint)); 2876 add(table2, table0, 2*256*sizeof(juint)); 2877 add(table3, table0, 3*256*sizeof(juint)); 2878 2879 if (UseNeon) { 2880 cmp(len, 64); 2881 br(Assembler::LT, L_by16); 2882 eor(v16, T16B, v16, v16); 2883 2884 Label L_fold; 2885 2886 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants 2887 2888 ld1(v0, v1, T2D, post(buf, 32)); 2889 ld1r(v4, T2D, post(tmp, 8)); 2890 ld1r(v5, T2D, post(tmp, 8)); 2891 ld1r(v6, T2D, post(tmp, 8)); 2892 ld1r(v7, T2D, post(tmp, 8)); 2893 mov(v16, T4S, 0, crc); 2894 2895 eor(v0, T16B, v0, v16); 2896 sub(len, len, 64); 2897 2898 BIND(L_fold); 2899 pmull(v22, T8H, v0, v5, T8B); 2900 pmull(v20, T8H, v0, v7, T8B); 2901 pmull(v23, T8H, v0, v4, T8B); 2902 pmull(v21, T8H, v0, v6, T8B); 2903 2904 pmull2(v18, T8H, v0, v5, T16B); 2905 pmull2(v16, T8H, v0, v7, T16B); 2906 pmull2(v19, T8H, v0, v4, T16B); 2907 pmull2(v17, T8H, v0, v6, T16B); 2908 2909 uzp1(v24, v20, v22, T8H); 2910 uzp2(v25, v20, v22, T8H); 2911 eor(v20, T16B, v24, v25); 2912 2913 uzp1(v26, v16, v18, T8H); 2914 uzp2(v27, v16, v18, T8H); 2915 eor(v16, T16B, v26, v27); 2916 2917 ushll2(v22, T4S, v20, T8H, 8); 2918 ushll(v20, T4S, v20, T4H, 8); 2919 2920 ushll2(v18, T4S, v16, T8H, 8); 2921 ushll(v16, T4S, v16, T4H, 8); 2922 2923 eor(v22, T16B, v23, v22); 2924 eor(v18, T16B, v19, v18); 2925 eor(v20, T16B, v21, v20); 2926 eor(v16, T16B, v17, v16); 2927 2928 uzp1(v17, v16, v20, T2D); 2929 uzp2(v21, v16, v20, T2D); 2930 eor(v17, T16B, v17, v21); 2931 2932 ushll2(v20, T2D, v17, T4S, 16); 2933 ushll(v16, T2D, v17, T2S, 16); 2934 2935 eor(v20, T16B, v20, v22); 2936 eor(v16, T16B, v16, v18); 2937 2938 uzp1(v17, v20, v16, T2D); 2939 uzp2(v21, v20, v16, T2D); 2940 eor(v28, T16B, v17, v21); 2941 2942 pmull(v22, T8H, v1, v5, T8B); 2943 pmull(v20, T8H, v1, v7, T8B); 2944 pmull(v23, T8H, v1, v4, T8B); 2945 pmull(v21, T8H, v1, v6, T8B); 2946 2947 pmull2(v18, T8H, v1, v5, T16B); 2948 pmull2(v16, T8H, v1, v7, T16B); 2949 pmull2(v19, T8H, v1, v4, T16B); 2950 pmull2(v17, T8H, v1, v6, T16B); 2951 2952 ld1(v0, v1, T2D, post(buf, 32)); 2953 2954 uzp1(v24, v20, v22, T8H); 2955 uzp2(v25, v20, v22, T8H); 2956 eor(v20, T16B, v24, v25); 2957 2958 uzp1(v26, v16, v18, T8H); 2959 uzp2(v27, v16, v18, T8H); 2960 eor(v16, T16B, v26, v27); 2961 2962 ushll2(v22, T4S, v20, T8H, 8); 2963 ushll(v20, T4S, v20, T4H, 8); 2964 2965 ushll2(v18, T4S, v16, T8H, 8); 2966 ushll(v16, T4S, v16, T4H, 8); 2967 2968 eor(v22, T16B, v23, v22); 2969 eor(v18, T16B, v19, v18); 2970 eor(v20, T16B, v21, v20); 2971 eor(v16, T16B, v17, v16); 2972 2973 uzp1(v17, v16, v20, T2D); 2974 uzp2(v21, v16, v20, T2D); 2975 eor(v16, T16B, v17, v21); 2976 2977 ushll2(v20, T2D, v16, T4S, 16); 2978 ushll(v16, T2D, v16, T2S, 16); 2979 2980 eor(v20, T16B, v22, v20); 2981 eor(v16, T16B, v16, v18); 2982 2983 uzp1(v17, v20, v16, T2D); 2984 uzp2(v21, v20, v16, T2D); 2985 eor(v20, T16B, v17, v21); 2986 2987 shl(v16, T2D, v28, 1); 2988 shl(v17, T2D, v20, 1); 2989 2990 eor(v0, T16B, v0, v16); 2991 eor(v1, T16B, v1, v17); 2992 2993 subs(len, len, 32); 2994 br(Assembler::GE, L_fold); 2995 2996 mov(crc, 0); 2997 mov(tmp, v0, T1D, 0); 2998 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 2999 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3000 mov(tmp, v0, T1D, 1); 3001 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3002 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3003 mov(tmp, v1, T1D, 0); 3004 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3005 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3006 mov(tmp, v1, T1D, 1); 3007 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3008 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3009 3010 add(len, len, 32); 3011 } 3012 3013 BIND(L_by16); 3014 subs(len, len, 16); 3015 br(Assembler::GE, L_by16_loop); 3016 adds(len, len, 16-4); 3017 br(Assembler::GE, L_by4_loop); 3018 adds(len, len, 4); 3019 br(Assembler::GT, L_by1_loop); 3020 b(L_exit); 3021 3022 BIND(L_by4_loop); 3023 ldrw(tmp, Address(post(buf, 4))); 3024 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3); 3025 subs(len, len, 4); 3026 br(Assembler::GE, L_by4_loop); 3027 adds(len, len, 4); 3028 br(Assembler::LE, L_exit); 3029 BIND(L_by1_loop); 3030 subs(len, len, 1); 3031 ldrb(tmp, Address(post(buf, 1))); 3032 update_byte_crc32(crc, tmp, table0); 3033 br(Assembler::GT, L_by1_loop); 3034 b(L_exit); 3035 3036 align(CodeEntryAlignment); 3037 BIND(L_by16_loop); 3038 subs(len, len, 16); 3039 ldp(tmp, tmp3, Address(post(buf, 16))); 3040 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false); 3041 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true); 3042 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false); 3043 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true); 3044 br(Assembler::GE, L_by16_loop); 3045 adds(len, len, 16-4); 3046 br(Assembler::GE, L_by4_loop); 3047 adds(len, len, 4); 3048 br(Assembler::GT, L_by1_loop); 3049 BIND(L_exit); 3050 ornw(crc, zr, crc); 3051 } 3052 3053 /** 3054 * @param crc register containing existing CRC (32-bit) 3055 * @param buf register pointing to input byte buffer (byte*) 3056 * @param len register containing number of bytes 3057 * @param table register that will contain address of CRC table 3058 * @param tmp scratch register 3059 */ 3060 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len, 3061 Register table0, Register table1, Register table2, Register table3, 3062 Register tmp, Register tmp2, Register tmp3) { 3063 Label L_exit; 3064 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop; 3065 3066 subs(len, len, 64); 3067 br(Assembler::GE, CRC_by64_loop); 3068 adds(len, len, 64-4); 3069 br(Assembler::GE, CRC_by4_loop); 3070 adds(len, len, 4); 3071 br(Assembler::GT, CRC_by1_loop); 3072 b(L_exit); 3073 3074 BIND(CRC_by4_loop); 3075 ldrw(tmp, Address(post(buf, 4))); 3076 subs(len, len, 4); 3077 crc32cw(crc, crc, tmp); 3078 br(Assembler::GE, CRC_by4_loop); 3079 adds(len, len, 4); 3080 br(Assembler::LE, L_exit); 3081 BIND(CRC_by1_loop); 3082 ldrb(tmp, Address(post(buf, 1))); 3083 subs(len, len, 1); 3084 crc32cb(crc, crc, tmp); 3085 br(Assembler::GT, CRC_by1_loop); 3086 b(L_exit); 3087 3088 align(CodeEntryAlignment); 3089 BIND(CRC_by64_loop); 3090 subs(len, len, 64); 3091 ldp(tmp, tmp3, Address(post(buf, 16))); 3092 crc32cx(crc, crc, tmp); 3093 crc32cx(crc, crc, tmp3); 3094 ldp(tmp, tmp3, Address(post(buf, 16))); 3095 crc32cx(crc, crc, tmp); 3096 crc32cx(crc, crc, tmp3); 3097 ldp(tmp, tmp3, Address(post(buf, 16))); 3098 crc32cx(crc, crc, tmp); 3099 crc32cx(crc, crc, tmp3); 3100 ldp(tmp, tmp3, Address(post(buf, 16))); 3101 crc32cx(crc, crc, tmp); 3102 crc32cx(crc, crc, tmp3); 3103 br(Assembler::GE, CRC_by64_loop); 3104 adds(len, len, 64-4); 3105 br(Assembler::GE, CRC_by4_loop); 3106 adds(len, len, 4); 3107 br(Assembler::GT, CRC_by1_loop); 3108 BIND(L_exit); 3109 return; 3110 } 3111 3112 SkipIfEqual::SkipIfEqual( 3113 MacroAssembler* masm, const bool* flag_addr, bool value) { 3114 _masm = masm; 3115 unsigned long offset; 3116 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset); 3117 _masm->ldrb(rscratch1, Address(rscratch1, offset)); 3118 _masm->cbzw(rscratch1, _label); 3119 } 3120 3121 SkipIfEqual::~SkipIfEqual() { 3122 _masm->bind(_label); 3123 } 3124 3125 void MacroAssembler::addptr(const Address &dst, int32_t src) { 3126 Address adr; 3127 switch(dst.getMode()) { 3128 case Address::base_plus_offset: 3129 // This is the expected mode, although we allow all the other 3130 // forms below. 3131 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord); 3132 break; 3133 default: 3134 lea(rscratch2, dst); 3135 adr = Address(rscratch2); 3136 break; 3137 } 3138 ldr(rscratch1, adr); 3139 add(rscratch1, rscratch1, src); 3140 str(rscratch1, adr); 3141 } 3142 3143 void MacroAssembler::cmpptr(Register src1, Address src2) { 3144 unsigned long offset; 3145 adrp(rscratch1, src2, offset); 3146 ldr(rscratch1, Address(rscratch1, offset)); 3147 cmp(src1, rscratch1); 3148 } 3149 3150 void MacroAssembler::store_check(Register obj, Address dst) { 3151 store_check(obj); 3152 } 3153 3154 void MacroAssembler::store_check(Register obj) { 3155 // Does a store check for the oop in register obj. The content of 3156 // register obj is destroyed afterwards. 3157 3158 BarrierSet* bs = Universe::heap()->barrier_set(); 3159 assert(bs->kind() == BarrierSet::CardTableForRS || 3160 bs->kind() == BarrierSet::CardTableExtension, 3161 "Wrong barrier set kind"); 3162 3163 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 3164 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3165 3166 lsr(obj, obj, CardTableModRefBS::card_shift); 3167 3168 assert(CardTableModRefBS::dirty_card_val() == 0, "must be"); 3169 3170 load_byte_map_base(rscratch1); 3171 3172 if (UseCondCardMark) { 3173 Label L_already_dirty; 3174 membar(StoreLoad); 3175 ldrb(rscratch2, Address(obj, rscratch1)); 3176 cbz(rscratch2, L_already_dirty); 3177 strb(zr, Address(obj, rscratch1)); 3178 bind(L_already_dirty); 3179 } else { 3180 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) { 3181 membar(StoreStore); 3182 } 3183 strb(zr, Address(obj, rscratch1)); 3184 } 3185 } 3186 3187 void MacroAssembler::load_klass(Register dst, Register src) { 3188 if (UseCompressedClassPointers) { 3189 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3190 decode_klass_not_null(dst); 3191 } else { 3192 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 3193 } 3194 } 3195 3196 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) { 3197 if (UseCompressedClassPointers) { 3198 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3199 if (Universe::narrow_klass_base() == NULL) { 3200 cmp(trial_klass, tmp, LSL, Universe::narrow_klass_shift()); 3201 return; 3202 } else if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3203 && Universe::narrow_klass_shift() == 0) { 3204 // Only the bottom 32 bits matter 3205 cmpw(trial_klass, tmp); 3206 return; 3207 } 3208 decode_klass_not_null(tmp); 3209 } else { 3210 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes())); 3211 } 3212 cmp(trial_klass, tmp); 3213 } 3214 3215 void MacroAssembler::load_prototype_header(Register dst, Register src) { 3216 load_klass(dst, src); 3217 ldr(dst, Address(dst, Klass::prototype_header_offset())); 3218 } 3219 3220 void MacroAssembler::store_klass(Register dst, Register src) { 3221 // FIXME: Should this be a store release? concurrent gcs assumes 3222 // klass length is valid if klass field is not null. 3223 if (UseCompressedClassPointers) { 3224 encode_klass_not_null(src); 3225 strw(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3226 } else { 3227 str(src, Address(dst, oopDesc::klass_offset_in_bytes())); 3228 } 3229 } 3230 3231 void MacroAssembler::store_klass_gap(Register dst, Register src) { 3232 if (UseCompressedClassPointers) { 3233 // Store to klass gap in destination 3234 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes())); 3235 } 3236 } 3237 3238 // Algorithm must match oop.inline.hpp encode_heap_oop. 3239 void MacroAssembler::encode_heap_oop(Register d, Register s) { 3240 #ifdef ASSERT 3241 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 3242 #endif 3243 verify_oop(s, "broken oop in encode_heap_oop"); 3244 if (Universe::narrow_oop_base() == NULL) { 3245 if (Universe::narrow_oop_shift() != 0) { 3246 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3247 lsr(d, s, LogMinObjAlignmentInBytes); 3248 } else { 3249 mov(d, s); 3250 } 3251 } else { 3252 subs(d, s, rheapbase); 3253 csel(d, d, zr, Assembler::HS); 3254 lsr(d, d, LogMinObjAlignmentInBytes); 3255 3256 /* Old algorithm: is this any worse? 3257 Label nonnull; 3258 cbnz(r, nonnull); 3259 sub(r, r, rheapbase); 3260 bind(nonnull); 3261 lsr(r, r, LogMinObjAlignmentInBytes); 3262 */ 3263 } 3264 } 3265 3266 void MacroAssembler::encode_heap_oop_not_null(Register r) { 3267 #ifdef ASSERT 3268 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 3269 if (CheckCompressedOops) { 3270 Label ok; 3271 cbnz(r, ok); 3272 stop("null oop passed to encode_heap_oop_not_null"); 3273 bind(ok); 3274 } 3275 #endif 3276 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 3277 if (Universe::narrow_oop_base() != NULL) { 3278 sub(r, r, rheapbase); 3279 } 3280 if (Universe::narrow_oop_shift() != 0) { 3281 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3282 lsr(r, r, LogMinObjAlignmentInBytes); 3283 } 3284 } 3285 3286 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 3287 #ifdef ASSERT 3288 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 3289 if (CheckCompressedOops) { 3290 Label ok; 3291 cbnz(src, ok); 3292 stop("null oop passed to encode_heap_oop_not_null2"); 3293 bind(ok); 3294 } 3295 #endif 3296 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 3297 3298 Register data = src; 3299 if (Universe::narrow_oop_base() != NULL) { 3300 sub(dst, src, rheapbase); 3301 data = dst; 3302 } 3303 if (Universe::narrow_oop_shift() != 0) { 3304 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3305 lsr(dst, data, LogMinObjAlignmentInBytes); 3306 data = dst; 3307 } 3308 if (data == src) 3309 mov(dst, src); 3310 } 3311 3312 void MacroAssembler::decode_heap_oop(Register d, Register s) { 3313 #ifdef ASSERT 3314 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 3315 #endif 3316 if (Universe::narrow_oop_base() == NULL) { 3317 if (Universe::narrow_oop_shift() != 0 || d != s) { 3318 lsl(d, s, Universe::narrow_oop_shift()); 3319 } 3320 } else { 3321 Label done; 3322 if (d != s) 3323 mov(d, s); 3324 cbz(s, done); 3325 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes); 3326 bind(done); 3327 } 3328 verify_oop(d, "broken oop in decode_heap_oop"); 3329 } 3330 3331 void MacroAssembler::decode_heap_oop_not_null(Register r) { 3332 assert (UseCompressedOops, "should only be used for compressed headers"); 3333 assert (Universe::heap() != NULL, "java heap should be initialized"); 3334 // Cannot assert, unverified entry point counts instructions (see .ad file) 3335 // vtableStubs also counts instructions in pd_code_size_limit. 3336 // Also do not verify_oop as this is called by verify_oop. 3337 if (Universe::narrow_oop_shift() != 0) { 3338 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3339 if (Universe::narrow_oop_base() != NULL) { 3340 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3341 } else { 3342 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes); 3343 } 3344 } else { 3345 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3346 } 3347 } 3348 3349 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 3350 assert (UseCompressedOops, "should only be used for compressed headers"); 3351 assert (Universe::heap() != NULL, "java heap should be initialized"); 3352 // Cannot assert, unverified entry point counts instructions (see .ad file) 3353 // vtableStubs also counts instructions in pd_code_size_limit. 3354 // Also do not verify_oop as this is called by verify_oop. 3355 if (Universe::narrow_oop_shift() != 0) { 3356 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 3357 if (Universe::narrow_oop_base() != NULL) { 3358 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3359 } else { 3360 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes); 3361 } 3362 } else { 3363 assert (Universe::narrow_oop_base() == NULL, "sanity"); 3364 if (dst != src) { 3365 mov(dst, src); 3366 } 3367 } 3368 } 3369 3370 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 3371 if (Universe::narrow_klass_base() == NULL) { 3372 if (Universe::narrow_klass_shift() != 0) { 3373 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3374 lsr(dst, src, LogKlassAlignmentInBytes); 3375 } else { 3376 if (dst != src) mov(dst, src); 3377 } 3378 return; 3379 } 3380 3381 if (use_XOR_for_compressed_class_base) { 3382 if (Universe::narrow_klass_shift() != 0) { 3383 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3384 lsr(dst, dst, LogKlassAlignmentInBytes); 3385 } else { 3386 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3387 } 3388 return; 3389 } 3390 3391 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3392 && Universe::narrow_klass_shift() == 0) { 3393 movw(dst, src); 3394 return; 3395 } 3396 3397 #ifdef ASSERT 3398 verify_heapbase("MacroAssembler::encode_klass_not_null2: heap base corrupted?"); 3399 #endif 3400 3401 Register rbase = dst; 3402 if (dst == src) rbase = rheapbase; 3403 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3404 sub(dst, src, rbase); 3405 if (Universe::narrow_klass_shift() != 0) { 3406 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3407 lsr(dst, dst, LogKlassAlignmentInBytes); 3408 } 3409 if (dst == src) reinit_heapbase(); 3410 } 3411 3412 void MacroAssembler::encode_klass_not_null(Register r) { 3413 encode_klass_not_null(r, r); 3414 } 3415 3416 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 3417 Register rbase = dst; 3418 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3419 3420 if (Universe::narrow_klass_base() == NULL) { 3421 if (Universe::narrow_klass_shift() != 0) { 3422 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3423 lsl(dst, src, LogKlassAlignmentInBytes); 3424 } else { 3425 if (dst != src) mov(dst, src); 3426 } 3427 return; 3428 } 3429 3430 if (use_XOR_for_compressed_class_base) { 3431 if (Universe::narrow_klass_shift() != 0) { 3432 lsl(dst, src, LogKlassAlignmentInBytes); 3433 eor(dst, dst, (uint64_t)Universe::narrow_klass_base()); 3434 } else { 3435 eor(dst, src, (uint64_t)Universe::narrow_klass_base()); 3436 } 3437 return; 3438 } 3439 3440 if (((uint64_t)Universe::narrow_klass_base() & 0xffffffff) == 0 3441 && Universe::narrow_klass_shift() == 0) { 3442 if (dst != src) 3443 movw(dst, src); 3444 movk(dst, (uint64_t)Universe::narrow_klass_base() >> 32, 32); 3445 return; 3446 } 3447 3448 // Cannot assert, unverified entry point counts instructions (see .ad file) 3449 // vtableStubs also counts instructions in pd_code_size_limit. 3450 // Also do not verify_oop as this is called by verify_oop. 3451 if (dst == src) rbase = rheapbase; 3452 mov(rbase, (uint64_t)Universe::narrow_klass_base()); 3453 if (Universe::narrow_klass_shift() != 0) { 3454 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 3455 add(dst, rbase, src, Assembler::LSL, LogKlassAlignmentInBytes); 3456 } else { 3457 add(dst, rbase, src); 3458 } 3459 if (dst == src) reinit_heapbase(); 3460 } 3461 3462 void MacroAssembler::decode_klass_not_null(Register r) { 3463 decode_klass_not_null(r, r); 3464 } 3465 3466 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 3467 assert (UseCompressedOops, "should only be used for compressed oops"); 3468 assert (Universe::heap() != NULL, "java heap should be initialized"); 3469 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3470 3471 int oop_index = oop_recorder()->find_index(obj); 3472 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3473 3474 InstructionMark im(this); 3475 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3476 code_section()->relocate(inst_mark(), rspec); 3477 movz(dst, 0xDEAD, 16); 3478 movk(dst, 0xBEEF); 3479 } 3480 3481 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 3482 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 3483 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3484 int index = oop_recorder()->find_index(k); 3485 assert(! Universe::heap()->is_in_reserved(k), "should not be an oop"); 3486 3487 InstructionMark im(this); 3488 RelocationHolder rspec = metadata_Relocation::spec(index); 3489 code_section()->relocate(inst_mark(), rspec); 3490 narrowKlass nk = Klass::encode_klass(k); 3491 movz(dst, (nk >> 16), 16); 3492 movk(dst, nk & 0xffff); 3493 } 3494 3495 void MacroAssembler::load_heap_oop(Register dst, Address src) 3496 { 3497 if (UseCompressedOops) { 3498 ldrw(dst, src); 3499 decode_heap_oop(dst); 3500 } else { 3501 ldr(dst, src); 3502 } 3503 } 3504 3505 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) 3506 { 3507 if (UseCompressedOops) { 3508 ldrw(dst, src); 3509 decode_heap_oop_not_null(dst); 3510 } else { 3511 ldr(dst, src); 3512 } 3513 } 3514 3515 void MacroAssembler::store_heap_oop(Address dst, Register src) { 3516 if (UseCompressedOops) { 3517 assert(!dst.uses(src), "not enough registers"); 3518 encode_heap_oop(src); 3519 strw(src, dst); 3520 } else 3521 str(src, dst); 3522 } 3523 3524 // Used for storing NULLs. 3525 void MacroAssembler::store_heap_oop_null(Address dst) { 3526 if (UseCompressedOops) { 3527 strw(zr, dst); 3528 } else 3529 str(zr, dst); 3530 } 3531 3532 #if INCLUDE_ALL_GCS 3533 void MacroAssembler::g1_write_barrier_pre(Register obj, 3534 Register pre_val, 3535 Register thread, 3536 Register tmp, 3537 bool tosca_live, 3538 bool expand_call) { 3539 // If expand_call is true then we expand the call_VM_leaf macro 3540 // directly to skip generating the check by 3541 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 3542 3543 assert(thread == rthread, "must be"); 3544 3545 Label done; 3546 Label runtime; 3547 3548 assert(pre_val != noreg, "check this code"); 3549 3550 if (obj != noreg) 3551 assert_different_registers(obj, pre_val, tmp); 3552 3553 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3554 SATBMarkQueue::byte_offset_of_active())); 3555 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3556 SATBMarkQueue::byte_offset_of_index())); 3557 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 3558 SATBMarkQueue::byte_offset_of_buf())); 3559 3560 3561 // Is marking active? 3562 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 3563 ldrw(tmp, in_progress); 3564 } else { 3565 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 3566 ldrb(tmp, in_progress); 3567 } 3568 cbzw(tmp, done); 3569 3570 // Do we need to load the previous value? 3571 if (obj != noreg) { 3572 load_heap_oop(pre_val, Address(obj, 0)); 3573 } 3574 3575 // Is the previous value null? 3576 cbz(pre_val, done); 3577 3578 // Can we store original value in the thread's buffer? 3579 // Is index == 0? 3580 // (The index field is typed as size_t.) 3581 3582 ldr(tmp, index); // tmp := *index_adr 3583 cbz(tmp, runtime); // tmp == 0? 3584 // If yes, goto runtime 3585 3586 sub(tmp, tmp, wordSize); // tmp := tmp - wordSize 3587 str(tmp, index); // *index_adr := tmp 3588 ldr(rscratch1, buffer); 3589 add(tmp, tmp, rscratch1); // tmp := tmp + *buffer_adr 3590 3591 // Record the previous value 3592 str(pre_val, Address(tmp, 0)); 3593 b(done); 3594 3595 bind(runtime); 3596 // save the live input values 3597 push(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3598 3599 // Calling the runtime using the regular call_VM_leaf mechanism generates 3600 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 3601 // that checks that the *(rfp+frame::interpreter_frame_last_sp) == NULL. 3602 // 3603 // If we care generating the pre-barrier without a frame (e.g. in the 3604 // intrinsified Reference.get() routine) then ebp might be pointing to 3605 // the caller frame and so this check will most likely fail at runtime. 3606 // 3607 // Expanding the call directly bypasses the generation of the check. 3608 // So when we do not have have a full interpreter frame on the stack 3609 // expand_call should be passed true. 3610 3611 if (expand_call) { 3612 assert(pre_val != c_rarg1, "smashed arg"); 3613 pass_arg1(this, thread); 3614 pass_arg0(this, pre_val); 3615 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 3616 } else { 3617 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 3618 } 3619 3620 pop(r0->bit(tosca_live) | obj->bit(obj != noreg) | pre_val->bit(true), sp); 3621 3622 bind(done); 3623 } 3624 3625 void MacroAssembler::g1_write_barrier_post(Register store_addr, 3626 Register new_val, 3627 Register thread, 3628 Register tmp, 3629 Register tmp2) { 3630 assert(thread == rthread, "must be"); 3631 3632 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3633 DirtyCardQueue::byte_offset_of_index())); 3634 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 3635 DirtyCardQueue::byte_offset_of_buf())); 3636 3637 BarrierSet* bs = Universe::heap()->barrier_set(); 3638 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 3639 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3640 3641 Label done; 3642 Label runtime; 3643 3644 // Does store cross heap regions? 3645 3646 eor(tmp, store_addr, new_val); 3647 lsr(tmp, tmp, HeapRegion::LogOfHRGrainBytes); 3648 cbz(tmp, done); 3649 3650 // crosses regions, storing NULL? 3651 3652 cbz(new_val, done); 3653 3654 // storing region crossing non-NULL, is card already dirty? 3655 3656 ExternalAddress cardtable((address) ct->byte_map_base); 3657 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 3658 const Register card_addr = tmp; 3659 3660 lsr(card_addr, store_addr, CardTableModRefBS::card_shift); 3661 3662 // get the address of the card 3663 load_byte_map_base(tmp2); 3664 add(card_addr, card_addr, tmp2); 3665 ldrb(tmp2, Address(card_addr)); 3666 cmpw(tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val()); 3667 br(Assembler::EQ, done); 3668 3669 assert((int)CardTableModRefBS::dirty_card_val() == 0, "must be 0"); 3670 3671 membar(Assembler::StoreLoad); 3672 3673 ldrb(tmp2, Address(card_addr)); 3674 cbzw(tmp2, done); 3675 3676 // storing a region crossing, non-NULL oop, card is clean. 3677 // dirty card and log. 3678 3679 strb(zr, Address(card_addr)); 3680 3681 ldr(rscratch1, queue_index); 3682 cbz(rscratch1, runtime); 3683 sub(rscratch1, rscratch1, wordSize); 3684 str(rscratch1, queue_index); 3685 3686 ldr(tmp2, buffer); 3687 str(card_addr, Address(tmp2, rscratch1)); 3688 b(done); 3689 3690 bind(runtime); 3691 // save the live input values 3692 push(store_addr->bit(true) | new_val->bit(true), sp); 3693 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 3694 pop(store_addr->bit(true) | new_val->bit(true), sp); 3695 3696 bind(done); 3697 } 3698 3699 #endif // INCLUDE_ALL_GCS 3700 3701 Address MacroAssembler::allocate_metadata_address(Metadata* obj) { 3702 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 3703 int index = oop_recorder()->allocate_metadata_index(obj); 3704 RelocationHolder rspec = metadata_Relocation::spec(index); 3705 return Address((address)obj, rspec); 3706 } 3707 3708 // Move an oop into a register. immediate is true if we want 3709 // immediate instrcutions, i.e. we are not going to patch this 3710 // instruction while the code is being executed by another thread. In 3711 // that case we can use move immediates rather than the constant pool. 3712 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) { 3713 int oop_index; 3714 if (obj == NULL) { 3715 oop_index = oop_recorder()->allocate_oop_index(obj); 3716 } else { 3717 oop_index = oop_recorder()->find_index(obj); 3718 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "should be real oop"); 3719 } 3720 RelocationHolder rspec = oop_Relocation::spec(oop_index); 3721 if (! immediate) { 3722 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address 3723 ldr_constant(dst, Address(dummy, rspec)); 3724 } else 3725 mov(dst, Address((address)obj, rspec)); 3726 } 3727 3728 // Move a metadata address into a register. 3729 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 3730 int oop_index; 3731 if (obj == NULL) { 3732 oop_index = oop_recorder()->allocate_metadata_index(obj); 3733 } else { 3734 oop_index = oop_recorder()->find_index(obj); 3735 } 3736 RelocationHolder rspec = metadata_Relocation::spec(oop_index); 3737 mov(dst, Address((address)obj, rspec)); 3738 } 3739 3740 Address MacroAssembler::constant_oop_address(jobject obj) { 3741 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 3742 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); 3743 int oop_index = oop_recorder()->find_index(obj); 3744 return Address((address)obj, oop_Relocation::spec(oop_index)); 3745 } 3746 3747 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3748 void MacroAssembler::tlab_allocate(Register obj, 3749 Register var_size_in_bytes, 3750 int con_size_in_bytes, 3751 Register t1, 3752 Register t2, 3753 Label& slow_case) { 3754 assert_different_registers(obj, t2); 3755 assert_different_registers(obj, var_size_in_bytes); 3756 Register end = t2; 3757 3758 // verify_tlab(); 3759 3760 ldr(obj, Address(rthread, JavaThread::tlab_top_offset())); 3761 if (var_size_in_bytes == noreg) { 3762 lea(end, Address(obj, con_size_in_bytes)); 3763 } else { 3764 lea(end, Address(obj, var_size_in_bytes)); 3765 } 3766 ldr(rscratch1, Address(rthread, JavaThread::tlab_end_offset())); 3767 cmp(end, rscratch1); 3768 br(Assembler::HI, slow_case); 3769 3770 // update the tlab top pointer 3771 str(end, Address(rthread, JavaThread::tlab_top_offset())); 3772 3773 // recover var_size_in_bytes if necessary 3774 if (var_size_in_bytes == end) { 3775 sub(var_size_in_bytes, var_size_in_bytes, obj); 3776 } 3777 // verify_tlab(); 3778 } 3779 3780 // Preserves r19, and r3. 3781 Register MacroAssembler::tlab_refill(Label& retry, 3782 Label& try_eden, 3783 Label& slow_case) { 3784 Register top = r0; 3785 Register t1 = r2; 3786 Register t2 = r4; 3787 assert_different_registers(top, rthread, t1, t2, /* preserve: */ r19, r3); 3788 Label do_refill, discard_tlab; 3789 3790 if (!Universe::heap()->supports_inline_contig_alloc()) { 3791 // No allocation in the shared eden. 3792 b(slow_case); 3793 } 3794 3795 ldr(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3796 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3797 3798 // calculate amount of free space 3799 sub(t1, t1, top); 3800 lsr(t1, t1, LogHeapWordSize); 3801 3802 // Retain tlab and allocate object in shared space if 3803 // the amount free in the tlab is too large to discard. 3804 3805 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3806 cmp(t1, rscratch1); 3807 br(Assembler::LE, discard_tlab); 3808 3809 // Retain 3810 // ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3811 mov(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 3812 add(rscratch1, rscratch1, t2); 3813 str(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 3814 3815 if (TLABStats) { 3816 // increment number of slow_allocations 3817 addmw(Address(rthread, in_bytes(JavaThread::tlab_slow_allocations_offset())), 3818 1, rscratch1); 3819 } 3820 b(try_eden); 3821 3822 bind(discard_tlab); 3823 if (TLABStats) { 3824 // increment number of refills 3825 addmw(Address(rthread, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1, 3826 rscratch1); 3827 // accumulate wastage -- t1 is amount free in tlab 3828 addmw(Address(rthread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1, 3829 rscratch1); 3830 } 3831 3832 // if tlab is currently allocated (top or end != null) then 3833 // fill [top, end + alignment_reserve) with array object 3834 cbz(top, do_refill); 3835 3836 // set up the mark word 3837 mov(rscratch1, (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 3838 str(rscratch1, Address(top, oopDesc::mark_offset_in_bytes())); 3839 // set the length to the remaining space 3840 sub(t1, t1, typeArrayOopDesc::header_size(T_INT)); 3841 add(t1, t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 3842 lsl(t1, t1, log2_intptr(HeapWordSize/sizeof(jint))); 3843 strw(t1, Address(top, arrayOopDesc::length_offset_in_bytes())); 3844 // set klass to intArrayKlass 3845 { 3846 unsigned long offset; 3847 // dubious reloc why not an oop reloc? 3848 adrp(rscratch1, ExternalAddress((address)Universe::intArrayKlassObj_addr()), 3849 offset); 3850 ldr(t1, Address(rscratch1, offset)); 3851 } 3852 // store klass last. concurrent gcs assumes klass length is valid if 3853 // klass field is not null. 3854 store_klass(top, t1); 3855 3856 mov(t1, top); 3857 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3858 sub(t1, t1, rscratch1); 3859 incr_allocated_bytes(rthread, t1, 0, rscratch1); 3860 3861 // refill the tlab with an eden allocation 3862 bind(do_refill); 3863 ldr(t1, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3864 lsl(t1, t1, LogHeapWordSize); 3865 // allocate new tlab, address returned in top 3866 eden_allocate(top, t1, 0, t2, slow_case); 3867 3868 // Check that t1 was preserved in eden_allocate. 3869 #ifdef ASSERT 3870 if (UseTLAB) { 3871 Label ok; 3872 Register tsize = r4; 3873 assert_different_registers(tsize, rthread, t1); 3874 str(tsize, Address(pre(sp, -16))); 3875 ldr(tsize, Address(rthread, in_bytes(JavaThread::tlab_size_offset()))); 3876 lsl(tsize, tsize, LogHeapWordSize); 3877 cmp(t1, tsize); 3878 br(Assembler::EQ, ok); 3879 STOP("assert(t1 != tlab size)"); 3880 should_not_reach_here(); 3881 3882 bind(ok); 3883 ldr(tsize, Address(post(sp, 16))); 3884 } 3885 #endif 3886 str(top, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3887 str(top, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3888 add(top, top, t1); 3889 sub(top, top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 3890 str(top, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3891 verify_tlab(); 3892 b(retry); 3893 3894 return rthread; // for use by caller 3895 } 3896 3897 // Defines obj, preserves var_size_in_bytes 3898 void MacroAssembler::eden_allocate(Register obj, 3899 Register var_size_in_bytes, 3900 int con_size_in_bytes, 3901 Register t1, 3902 Label& slow_case) { 3903 assert_different_registers(obj, var_size_in_bytes, t1); 3904 if (!Universe::heap()->supports_inline_contig_alloc()) { 3905 b(slow_case); 3906 } else { 3907 Register end = t1; 3908 Register heap_end = rscratch2; 3909 Label retry; 3910 bind(retry); 3911 { 3912 unsigned long offset; 3913 adrp(rscratch1, ExternalAddress((address) Universe::heap()->end_addr()), offset); 3914 ldr(heap_end, Address(rscratch1, offset)); 3915 } 3916 3917 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 3918 3919 // Get the current top of the heap 3920 { 3921 unsigned long offset; 3922 adrp(rscratch1, heap_top, offset); 3923 // Use add() here after ARDP, rather than lea(). 3924 // lea() does not generate anything if its offset is zero. 3925 // However, relocs expect to find either an ADD or a load/store 3926 // insn after an ADRP. add() always generates an ADD insn, even 3927 // for add(Rn, Rn, 0). 3928 add(rscratch1, rscratch1, offset); 3929 ldaxr(obj, rscratch1); 3930 } 3931 3932 // Adjust it my the size of our new object 3933 if (var_size_in_bytes == noreg) { 3934 lea(end, Address(obj, con_size_in_bytes)); 3935 } else { 3936 lea(end, Address(obj, var_size_in_bytes)); 3937 } 3938 3939 // if end < obj then we wrapped around high memory 3940 cmp(end, obj); 3941 br(Assembler::LO, slow_case); 3942 3943 cmp(end, heap_end); 3944 br(Assembler::HI, slow_case); 3945 3946 // If heap_top hasn't been changed by some other thread, update it. 3947 stlxr(rscratch2, end, rscratch1); 3948 cbnzw(rscratch2, retry); 3949 } 3950 } 3951 3952 void MacroAssembler::verify_tlab() { 3953 #ifdef ASSERT 3954 if (UseTLAB && VerifyOops) { 3955 Label next, ok; 3956 3957 stp(rscratch2, rscratch1, Address(pre(sp, -16))); 3958 3959 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3960 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset()))); 3961 cmp(rscratch2, rscratch1); 3962 br(Assembler::HS, next); 3963 STOP("assert(top >= start)"); 3964 should_not_reach_here(); 3965 3966 bind(next); 3967 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset()))); 3968 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset()))); 3969 cmp(rscratch2, rscratch1); 3970 br(Assembler::HS, ok); 3971 STOP("assert(top <= end)"); 3972 should_not_reach_here(); 3973 3974 bind(ok); 3975 ldp(rscratch2, rscratch1, Address(post(sp, 16))); 3976 } 3977 #endif 3978 } 3979 3980 // Writes to stack successive pages until offset reached to check for 3981 // stack overflow + shadow pages. This clobbers tmp. 3982 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 3983 assert_different_registers(tmp, size, rscratch1); 3984 mov(tmp, sp); 3985 // Bang stack for total size given plus shadow page size. 3986 // Bang one page at a time because large size can bang beyond yellow and 3987 // red zones. 3988 Label loop; 3989 mov(rscratch1, os::vm_page_size()); 3990 bind(loop); 3991 lea(tmp, Address(tmp, -os::vm_page_size())); 3992 subsw(size, size, rscratch1); 3993 str(size, Address(tmp)); 3994 br(Assembler::GT, loop); 3995 3996 // Bang down shadow pages too. 3997 // At this point, (tmp-0) is the last address touched, so don't 3998 // touch it again. (It was touched as (tmp-pagesize) but then tmp 3999 // was post-decremented.) Skip this address by starting at i=1, and 4000 // touch a few more pages below. N.B. It is important to touch all 4001 // the way down to and including i=StackShadowPages. 4002 for (int i = 0; i < (int)(JavaThread::stack_shadow_zone_size() / os::vm_page_size()) - 1; i++) { 4003 // this could be any sized move but this is can be a debugging crumb 4004 // so the bigger the better. 4005 lea(tmp, Address(tmp, -os::vm_page_size())); 4006 str(size, Address(tmp)); 4007 } 4008 } 4009 4010 4011 address MacroAssembler::read_polling_page(Register r, address page, relocInfo::relocType rtype) { 4012 unsigned long off; 4013 adrp(r, Address(page, rtype), off); 4014 InstructionMark im(this); 4015 code_section()->relocate(inst_mark(), rtype); 4016 ldrw(zr, Address(r, off)); 4017 return inst_mark(); 4018 } 4019 4020 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) { 4021 InstructionMark im(this); 4022 code_section()->relocate(inst_mark(), rtype); 4023 ldrw(zr, Address(r, 0)); 4024 return inst_mark(); 4025 } 4026 4027 void MacroAssembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) { 4028 relocInfo::relocType rtype = dest.rspec().reloc()->type(); 4029 unsigned long low_page = (unsigned long)CodeCache::low_bound() >> 12; 4030 unsigned long high_page = (unsigned long)(CodeCache::high_bound()-1) >> 12; 4031 unsigned long dest_page = (unsigned long)dest.target() >> 12; 4032 long offset_low = dest_page - low_page; 4033 long offset_high = dest_page - high_page; 4034 4035 assert(is_valid_AArch64_address(dest.target()), "bad address"); 4036 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address"); 4037 4038 InstructionMark im(this); 4039 code_section()->relocate(inst_mark(), dest.rspec()); 4040 // 8143067: Ensure that the adrp can reach the dest from anywhere within 4041 // the code cache so that if it is relocated we know it will still reach 4042 if (offset_high >= -(1<<20) && offset_low < (1<<20)) { 4043 _adrp(reg1, dest.target()); 4044 } else { 4045 unsigned long target = (unsigned long)dest.target(); 4046 unsigned long adrp_target 4047 = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL); 4048 4049 _adrp(reg1, (address)adrp_target); 4050 movk(reg1, target >> 32, 32); 4051 } 4052 byte_offset = (unsigned long)dest.target() & 0xfff; 4053 } 4054 4055 void MacroAssembler::load_byte_map_base(Register reg) { 4056 jbyte *byte_map_base = 4057 ((CardTableModRefBS*)(Universe::heap()->barrier_set()))->byte_map_base; 4058 4059 if (is_valid_AArch64_address((address)byte_map_base)) { 4060 // Strictly speaking the byte_map_base isn't an address at all, 4061 // and it might even be negative. 4062 unsigned long offset; 4063 adrp(reg, ExternalAddress((address)byte_map_base), offset); 4064 assert(offset == 0, "misaligned card table base"); 4065 } else { 4066 mov(reg, (uint64_t)byte_map_base); 4067 } 4068 } 4069 4070 void MacroAssembler::build_frame(int framesize) { 4071 assert(framesize > 0, "framesize must be > 0"); 4072 if (framesize < ((1 << 9) + 2 * wordSize)) { 4073 sub(sp, sp, framesize); 4074 stp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4075 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize); 4076 } else { 4077 stp(rfp, lr, Address(pre(sp, -2 * wordSize))); 4078 if (PreserveFramePointer) mov(rfp, sp); 4079 if (framesize < ((1 << 12) + 2 * wordSize)) 4080 sub(sp, sp, framesize - 2 * wordSize); 4081 else { 4082 mov(rscratch1, framesize - 2 * wordSize); 4083 sub(sp, sp, rscratch1); 4084 } 4085 } 4086 } 4087 4088 void MacroAssembler::remove_frame(int framesize) { 4089 assert(framesize > 0, "framesize must be > 0"); 4090 if (framesize < ((1 << 9) + 2 * wordSize)) { 4091 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize)); 4092 add(sp, sp, framesize); 4093 } else { 4094 if (framesize < ((1 << 12) + 2 * wordSize)) 4095 add(sp, sp, framesize - 2 * wordSize); 4096 else { 4097 mov(rscratch1, framesize - 2 * wordSize); 4098 add(sp, sp, rscratch1); 4099 } 4100 ldp(rfp, lr, Address(post(sp, 2 * wordSize))); 4101 } 4102 } 4103 4104 4105 // Search for str1 in str2 and return index or -1 4106 void MacroAssembler::string_indexof(Register str2, Register str1, 4107 Register cnt2, Register cnt1, 4108 Register tmp1, Register tmp2, 4109 Register tmp3, Register tmp4, 4110 int icnt1, Register result) { 4111 Label BM, LINEARSEARCH, DONE, NOMATCH, MATCH; 4112 4113 Register ch1 = rscratch1; 4114 Register ch2 = rscratch2; 4115 Register cnt1tmp = tmp1; 4116 Register cnt2tmp = tmp2; 4117 Register cnt1_neg = cnt1; 4118 Register cnt2_neg = cnt2; 4119 Register result_tmp = tmp4; 4120 4121 // Note, inline_string_indexOf() generates checks: 4122 // if (substr.count > string.count) return -1; 4123 // if (substr.count == 0) return 0; 4124 4125 // We have two strings, a source string in str2, cnt2 and a pattern string 4126 // in str1, cnt1. Find the 1st occurence of pattern in source or return -1. 4127 4128 // For larger pattern and source we use a simplified Boyer Moore algorithm. 4129 // With a small pattern and source we use linear scan. 4130 4131 if (icnt1 == -1) { 4132 cmp(cnt1, 256); // Use Linear Scan if cnt1 < 8 || cnt1 >= 256 4133 ccmp(cnt1, 8, 0b0000, LO); // Can't handle skip >= 256 because we use 4134 br(LO, LINEARSEARCH); // a byte array. 4135 cmp(cnt1, cnt2, LSR, 2); // Source must be 4 * pattern for BM 4136 br(HS, LINEARSEARCH); 4137 } 4138 4139 // The Boyer Moore alogorithm is based on the description here:- 4140 // 4141 // http://en.wikipedia.org/wiki/Boyer%E2%80%93Moore_string_search_algorithm 4142 // 4143 // This describes and algorithm with 2 shift rules. The 'Bad Character' rule 4144 // and the 'Good Suffix' rule. 4145 // 4146 // These rules are essentially heuristics for how far we can shift the 4147 // pattern along the search string. 4148 // 4149 // The implementation here uses the 'Bad Character' rule only because of the 4150 // complexity of initialisation for the 'Good Suffix' rule. 4151 // 4152 // This is also known as the Boyer-Moore-Horspool algorithm:- 4153 // 4154 // http://en.wikipedia.org/wiki/Boyer-Moore-Horspool_algorithm 4155 // 4156 // #define ASIZE 128 4157 // 4158 // int bm(unsigned char *x, int m, unsigned char *y, int n) { 4159 // int i, j; 4160 // unsigned c; 4161 // unsigned char bc[ASIZE]; 4162 // 4163 // /* Preprocessing */ 4164 // for (i = 0; i < ASIZE; ++i) 4165 // bc[i] = 0; 4166 // for (i = 0; i < m - 1; ) { 4167 // c = x[i]; 4168 // ++i; 4169 // if (c < ASIZE) bc[c] = i; 4170 // } 4171 // 4172 // /* Searching */ 4173 // j = 0; 4174 // while (j <= n - m) { 4175 // c = y[i+j]; 4176 // if (x[m-1] == c) 4177 // for (i = m - 2; i >= 0 && x[i] == y[i + j]; --i); 4178 // if (i < 0) return j; 4179 // if (c < ASIZE) 4180 // j = j - bc[y[j+m-1]] + m; 4181 // else 4182 // j += 1; // Advance by 1 only if char >= ASIZE 4183 // } 4184 // } 4185 4186 if (icnt1 == -1) { 4187 BIND(BM); 4188 4189 Label ZLOOP, BCLOOP, BCSKIP, BMLOOPSTR2, BMLOOPSTR1, BMSKIP; 4190 Label BMADV, BMMATCH, BMCHECKEND; 4191 4192 Register cnt1end = tmp2; 4193 Register str2end = cnt2; 4194 Register skipch = tmp2; 4195 4196 // Restrict ASIZE to 128 to reduce stack space/initialisation. 4197 // The presence of chars >= ASIZE in the target string does not affect 4198 // performance, but we must be careful not to initialise them in the stack 4199 // array. 4200 // The presence of chars >= ASIZE in the source string may adversely affect 4201 // performance since we can only advance by one when we encounter one. 4202 4203 stp(zr, zr, pre(sp, -128)); 4204 for (int i = 1; i < 8; i++) 4205 stp(zr, zr, Address(sp, i*16)); 4206 4207 mov(cnt1tmp, 0); 4208 sub(cnt1end, cnt1, 1); 4209 BIND(BCLOOP); 4210 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4211 cmp(ch1, 128); 4212 add(cnt1tmp, cnt1tmp, 1); 4213 br(HS, BCSKIP); 4214 strb(cnt1tmp, Address(sp, ch1)); 4215 BIND(BCSKIP); 4216 cmp(cnt1tmp, cnt1end); 4217 br(LT, BCLOOP); 4218 4219 mov(result_tmp, str2); 4220 4221 sub(cnt2, cnt2, cnt1); 4222 add(str2end, str2, cnt2, LSL, 1); 4223 BIND(BMLOOPSTR2); 4224 sub(cnt1tmp, cnt1, 1); 4225 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4226 ldrh(skipch, Address(str2, cnt1tmp, Address::lsl(1))); 4227 cmp(ch1, skipch); 4228 br(NE, BMSKIP); 4229 subs(cnt1tmp, cnt1tmp, 1); 4230 br(LT, BMMATCH); 4231 BIND(BMLOOPSTR1); 4232 ldrh(ch1, Address(str1, cnt1tmp, Address::lsl(1))); 4233 ldrh(ch2, Address(str2, cnt1tmp, Address::lsl(1))); 4234 cmp(ch1, ch2); 4235 br(NE, BMSKIP); 4236 subs(cnt1tmp, cnt1tmp, 1); 4237 br(GE, BMLOOPSTR1); 4238 BIND(BMMATCH); 4239 sub(result_tmp, str2, result_tmp); 4240 lsr(result, result_tmp, 1); 4241 add(sp, sp, 128); 4242 b(DONE); 4243 BIND(BMADV); 4244 add(str2, str2, 2); 4245 b(BMCHECKEND); 4246 BIND(BMSKIP); 4247 cmp(skipch, 128); 4248 br(HS, BMADV); 4249 ldrb(ch2, Address(sp, skipch)); 4250 add(str2, str2, cnt1, LSL, 1); 4251 sub(str2, str2, ch2, LSL, 1); 4252 BIND(BMCHECKEND); 4253 cmp(str2, str2end); 4254 br(LE, BMLOOPSTR2); 4255 add(sp, sp, 128); 4256 b(NOMATCH); 4257 } 4258 4259 BIND(LINEARSEARCH); 4260 { 4261 Label DO1, DO2, DO3; 4262 4263 Register str2tmp = tmp2; 4264 Register first = tmp3; 4265 4266 if (icnt1 == -1) 4267 { 4268 Label DOSHORT, FIRST_LOOP, STR2_NEXT, STR1_LOOP, STR1_NEXT, LAST_WORD; 4269 4270 cmp(cnt1, 4); 4271 br(LT, DOSHORT); 4272 4273 sub(cnt2, cnt2, cnt1); 4274 sub(cnt1, cnt1, 4); 4275 mov(result_tmp, cnt2); 4276 4277 lea(str1, Address(str1, cnt1, Address::uxtw(1))); 4278 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4279 sub(cnt1_neg, zr, cnt1, LSL, 1); 4280 sub(cnt2_neg, zr, cnt2, LSL, 1); 4281 ldr(first, Address(str1, cnt1_neg)); 4282 4283 BIND(FIRST_LOOP); 4284 ldr(ch2, Address(str2, cnt2_neg)); 4285 cmp(first, ch2); 4286 br(EQ, STR1_LOOP); 4287 BIND(STR2_NEXT); 4288 adds(cnt2_neg, cnt2_neg, 2); 4289 br(LE, FIRST_LOOP); 4290 b(NOMATCH); 4291 4292 BIND(STR1_LOOP); 4293 adds(cnt1tmp, cnt1_neg, 8); 4294 add(cnt2tmp, cnt2_neg, 8); 4295 br(GE, LAST_WORD); 4296 4297 BIND(STR1_NEXT); 4298 ldr(ch1, Address(str1, cnt1tmp)); 4299 ldr(ch2, Address(str2, cnt2tmp)); 4300 cmp(ch1, ch2); 4301 br(NE, STR2_NEXT); 4302 adds(cnt1tmp, cnt1tmp, 8); 4303 add(cnt2tmp, cnt2tmp, 8); 4304 br(LT, STR1_NEXT); 4305 4306 BIND(LAST_WORD); 4307 ldr(ch1, Address(str1)); 4308 sub(str2tmp, str2, cnt1_neg); // adjust to corresponding 4309 ldr(ch2, Address(str2tmp, cnt2_neg)); // word in str2 4310 cmp(ch1, ch2); 4311 br(NE, STR2_NEXT); 4312 b(MATCH); 4313 4314 BIND(DOSHORT); 4315 cmp(cnt1, 2); 4316 br(LT, DO1); 4317 br(GT, DO3); 4318 } 4319 4320 if (icnt1 == 4) { 4321 Label CH1_LOOP; 4322 4323 ldr(ch1, str1); 4324 sub(cnt2, cnt2, 4); 4325 mov(result_tmp, cnt2); 4326 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4327 sub(cnt2_neg, zr, cnt2, LSL, 1); 4328 4329 BIND(CH1_LOOP); 4330 ldr(ch2, Address(str2, cnt2_neg)); 4331 cmp(ch1, ch2); 4332 br(EQ, MATCH); 4333 adds(cnt2_neg, cnt2_neg, 2); 4334 br(LE, CH1_LOOP); 4335 b(NOMATCH); 4336 } 4337 4338 if (icnt1 == -1 || icnt1 == 2) { 4339 Label CH1_LOOP; 4340 4341 BIND(DO2); 4342 ldrw(ch1, str1); 4343 sub(cnt2, cnt2, 2); 4344 mov(result_tmp, cnt2); 4345 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4346 sub(cnt2_neg, zr, cnt2, LSL, 1); 4347 4348 BIND(CH1_LOOP); 4349 ldrw(ch2, Address(str2, cnt2_neg)); 4350 cmp(ch1, ch2); 4351 br(EQ, MATCH); 4352 adds(cnt2_neg, cnt2_neg, 2); 4353 br(LE, CH1_LOOP); 4354 b(NOMATCH); 4355 } 4356 4357 if (icnt1 == -1 || icnt1 == 3) { 4358 Label FIRST_LOOP, STR2_NEXT, STR1_LOOP; 4359 4360 BIND(DO3); 4361 ldrw(first, str1); 4362 ldrh(ch1, Address(str1, 4)); 4363 4364 sub(cnt2, cnt2, 3); 4365 mov(result_tmp, cnt2); 4366 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4367 sub(cnt2_neg, zr, cnt2, LSL, 1); 4368 4369 BIND(FIRST_LOOP); 4370 ldrw(ch2, Address(str2, cnt2_neg)); 4371 cmpw(first, ch2); 4372 br(EQ, STR1_LOOP); 4373 BIND(STR2_NEXT); 4374 adds(cnt2_neg, cnt2_neg, 2); 4375 br(LE, FIRST_LOOP); 4376 b(NOMATCH); 4377 4378 BIND(STR1_LOOP); 4379 add(cnt2tmp, cnt2_neg, 4); 4380 ldrh(ch2, Address(str2, cnt2tmp)); 4381 cmp(ch1, ch2); 4382 br(NE, STR2_NEXT); 4383 b(MATCH); 4384 } 4385 4386 if (icnt1 == -1 || icnt1 == 1) { 4387 Label CH1_LOOP, HAS_ZERO; 4388 Label DO1_SHORT, DO1_LOOP; 4389 4390 BIND(DO1); 4391 ldrh(ch1, str1); 4392 cmp(cnt2, 4); 4393 br(LT, DO1_SHORT); 4394 4395 orr(ch1, ch1, ch1, LSL, 16); 4396 orr(ch1, ch1, ch1, LSL, 32); 4397 4398 sub(cnt2, cnt2, 4); 4399 mov(result_tmp, cnt2); 4400 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4401 sub(cnt2_neg, zr, cnt2, LSL, 1); 4402 4403 mov(tmp3, 0x0001000100010001); 4404 BIND(CH1_LOOP); 4405 ldr(ch2, Address(str2, cnt2_neg)); 4406 eor(ch2, ch1, ch2); 4407 sub(tmp1, ch2, tmp3); 4408 orr(tmp2, ch2, 0x7fff7fff7fff7fff); 4409 bics(tmp1, tmp1, tmp2); 4410 br(NE, HAS_ZERO); 4411 adds(cnt2_neg, cnt2_neg, 8); 4412 br(LT, CH1_LOOP); 4413 4414 cmp(cnt2_neg, 8); 4415 mov(cnt2_neg, 0); 4416 br(LT, CH1_LOOP); 4417 b(NOMATCH); 4418 4419 BIND(HAS_ZERO); 4420 rev(tmp1, tmp1); 4421 clz(tmp1, tmp1); 4422 add(cnt2_neg, cnt2_neg, tmp1, LSR, 3); 4423 b(MATCH); 4424 4425 BIND(DO1_SHORT); 4426 mov(result_tmp, cnt2); 4427 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4428 sub(cnt2_neg, zr, cnt2, LSL, 1); 4429 BIND(DO1_LOOP); 4430 ldrh(ch2, Address(str2, cnt2_neg)); 4431 cmpw(ch1, ch2); 4432 br(EQ, MATCH); 4433 adds(cnt2_neg, cnt2_neg, 2); 4434 br(LT, DO1_LOOP); 4435 } 4436 } 4437 BIND(NOMATCH); 4438 mov(result, -1); 4439 b(DONE); 4440 BIND(MATCH); 4441 add(result, result_tmp, cnt2_neg, ASR, 1); 4442 BIND(DONE); 4443 } 4444 4445 // Compare strings. 4446 void MacroAssembler::string_compare(Register str1, Register str2, 4447 Register cnt1, Register cnt2, Register result, 4448 Register tmp1) { 4449 Label LENGTH_DIFF, DONE, SHORT_LOOP, SHORT_STRING, 4450 NEXT_WORD, DIFFERENCE; 4451 4452 BLOCK_COMMENT("string_compare {"); 4453 4454 // Compute the minimum of the string lengths and save the difference. 4455 subsw(tmp1, cnt1, cnt2); 4456 cselw(cnt2, cnt1, cnt2, Assembler::LE); // min 4457 4458 // A very short string 4459 cmpw(cnt2, 4); 4460 br(Assembler::LT, SHORT_STRING); 4461 4462 // Check if the strings start at the same location. 4463 cmp(str1, str2); 4464 br(Assembler::EQ, LENGTH_DIFF); 4465 4466 // Compare longwords 4467 { 4468 subw(cnt2, cnt2, 4); // The last longword is a special case 4469 4470 // Move both string pointers to the last longword of their 4471 // strings, negate the remaining count, and convert it to bytes. 4472 lea(str1, Address(str1, cnt2, Address::uxtw(1))); 4473 lea(str2, Address(str2, cnt2, Address::uxtw(1))); 4474 sub(cnt2, zr, cnt2, LSL, 1); 4475 4476 // Loop, loading longwords and comparing them into rscratch2. 4477 bind(NEXT_WORD); 4478 ldr(result, Address(str1, cnt2)); 4479 ldr(cnt1, Address(str2, cnt2)); 4480 adds(cnt2, cnt2, wordSize); 4481 eor(rscratch2, result, cnt1); 4482 cbnz(rscratch2, DIFFERENCE); 4483 br(Assembler::LT, NEXT_WORD); 4484 4485 // Last longword. In the case where length == 4 we compare the 4486 // same longword twice, but that's still faster than another 4487 // conditional branch. 4488 4489 ldr(result, Address(str1)); 4490 ldr(cnt1, Address(str2)); 4491 eor(rscratch2, result, cnt1); 4492 cbz(rscratch2, LENGTH_DIFF); 4493 4494 // Find the first different characters in the longwords and 4495 // compute their difference. 4496 bind(DIFFERENCE); 4497 rev(rscratch2, rscratch2); 4498 clz(rscratch2, rscratch2); 4499 andr(rscratch2, rscratch2, -16); 4500 lsrv(result, result, rscratch2); 4501 uxthw(result, result); 4502 lsrv(cnt1, cnt1, rscratch2); 4503 uxthw(cnt1, cnt1); 4504 subw(result, result, cnt1); 4505 b(DONE); 4506 } 4507 4508 bind(SHORT_STRING); 4509 // Is the minimum length zero? 4510 cbz(cnt2, LENGTH_DIFF); 4511 4512 bind(SHORT_LOOP); 4513 load_unsigned_short(result, Address(post(str1, 2))); 4514 load_unsigned_short(cnt1, Address(post(str2, 2))); 4515 subw(result, result, cnt1); 4516 cbnz(result, DONE); 4517 sub(cnt2, cnt2, 1); 4518 cbnz(cnt2, SHORT_LOOP); 4519 4520 // Strings are equal up to min length. Return the length difference. 4521 bind(LENGTH_DIFF); 4522 mov(result, tmp1); 4523 4524 // That's it 4525 bind(DONE); 4526 4527 BLOCK_COMMENT("} string_compare"); 4528 } 4529 4530 // Compare Strings or char/byte arrays. 4531 4532 // is_string is true iff this is a string comparison. 4533 4534 // For Strings we're passed the address of the first characters in a1 4535 // and a2 and the length in cnt1. 4536 4537 // For byte and char arrays we're passed the arrays themselves and we 4538 // have to extract length fields and do null checks here. 4539 4540 // elem_size is the element size in bytes: either 1 or 2. 4541 4542 // There are two implementations. For arrays >= 8 bytes, all 4543 // comparisons (including the final one, which may overlap) are 4544 // performed 8 bytes at a time. For arrays < 8 bytes, we compare a 4545 // halfword, then a short, and then a byte. 4546 4547 void MacroAssembler::arrays_equals(Register a1, Register a2, 4548 Register result, Register cnt1, 4549 int elem_size, bool is_string) 4550 { 4551 Label SAME, DONE, SHORT, NEXT_WORD, ONE; 4552 Register tmp1 = rscratch1; 4553 Register tmp2 = rscratch2; 4554 Register cnt2 = tmp2; // cnt2 only used in array length compare 4555 int elem_per_word = wordSize/elem_size; 4556 int log_elem_size = exact_log2(elem_size); 4557 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4558 int base_offset 4559 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE); 4560 4561 assert(elem_size == 1 || elem_size == 2, "must be char or byte"); 4562 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2); 4563 4564 BLOCK_COMMENT(is_string ? "string_equals {" : "array_equals {"); 4565 4566 mov(result, false); 4567 4568 if (!is_string) { 4569 // if (a==a2) 4570 // return true; 4571 eor(rscratch1, a1, a2); 4572 cbz(rscratch1, SAME); 4573 // if (a==null || a2==null) 4574 // return false; 4575 cbz(a1, DONE); 4576 cbz(a2, DONE); 4577 // if (a1.length != a2.length) 4578 // return false; 4579 ldrw(cnt1, Address(a1, length_offset)); 4580 ldrw(cnt2, Address(a2, length_offset)); 4581 eorw(tmp1, cnt1, cnt2); 4582 cbnzw(tmp1, DONE); 4583 4584 lea(a1, Address(a1, base_offset)); 4585 lea(a2, Address(a2, base_offset)); 4586 } 4587 4588 // Check for short strings, i.e. smaller than wordSize. 4589 subs(cnt1, cnt1, elem_per_word); 4590 br(Assembler::LT, SHORT); 4591 // Main 8 byte comparison loop. 4592 bind(NEXT_WORD); { 4593 ldr(tmp1, Address(post(a1, wordSize))); 4594 ldr(tmp2, Address(post(a2, wordSize))); 4595 subs(cnt1, cnt1, elem_per_word); 4596 eor(tmp1, tmp1, tmp2); 4597 cbnz(tmp1, DONE); 4598 } br(GT, NEXT_WORD); 4599 // Last longword. In the case where length == 4 we compare the 4600 // same longword twice, but that's still faster than another 4601 // conditional branch. 4602 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when 4603 // length == 4. 4604 if (log_elem_size > 0) 4605 lsl(cnt1, cnt1, log_elem_size); 4606 ldr(tmp1, Address(a1, cnt1)); 4607 ldr(tmp2, Address(a2, cnt1)); 4608 eor(tmp1, tmp1, tmp2); 4609 cbnz(tmp1, DONE); 4610 b(SAME); 4611 4612 bind(SHORT); 4613 Label TAIL03, TAIL01; 4614 4615 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left. 4616 { 4617 ldrw(tmp1, Address(post(a1, 4))); 4618 ldrw(tmp2, Address(post(a2, 4))); 4619 eorw(tmp1, tmp1, tmp2); 4620 cbnzw(tmp1, DONE); 4621 } 4622 bind(TAIL03); 4623 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left. 4624 { 4625 ldrh(tmp1, Address(post(a1, 2))); 4626 ldrh(tmp2, Address(post(a2, 2))); 4627 eorw(tmp1, tmp1, tmp2); 4628 cbnzw(tmp1, DONE); 4629 } 4630 bind(TAIL01); 4631 if (elem_size == 1) { // Only needed when comparing byte arrays. 4632 tbz(cnt1, 0, SAME); // 0-1 bytes left. 4633 { 4634 ldrb(tmp1, a1); 4635 ldrb(tmp2, a2); 4636 eorw(tmp1, tmp1, tmp2); 4637 cbnzw(tmp1, DONE); 4638 } 4639 } 4640 // Arrays are equal. 4641 bind(SAME); 4642 mov(result, true); 4643 4644 // That's it. 4645 bind(DONE); 4646 BLOCK_COMMENT(is_string ? "} string_equals" : "} array_equals"); 4647 } 4648 4649 4650 // encode char[] to byte[] in ISO_8859_1 4651 void MacroAssembler::encode_iso_array(Register src, Register dst, 4652 Register len, Register result, 4653 FloatRegister Vtmp1, FloatRegister Vtmp2, 4654 FloatRegister Vtmp3, FloatRegister Vtmp4) 4655 { 4656 Label DONE, NEXT_32, LOOP_8, NEXT_8, LOOP_1, NEXT_1; 4657 Register tmp1 = rscratch1; 4658 4659 mov(result, len); // Save initial len 4660 4661 #ifndef BUILTIN_SIM 4662 subs(len, len, 32); 4663 br(LT, LOOP_8); 4664 4665 // The following code uses the SIMD 'uqxtn' and 'uqxtn2' instructions 4666 // to convert chars to bytes. These set the 'QC' bit in the FPSR if 4667 // any char could not fit in a byte, so clear the FPSR so we can test it. 4668 clear_fpsr(); 4669 4670 BIND(NEXT_32); 4671 ld1(Vtmp1, Vtmp2, Vtmp3, Vtmp4, T8H, src); 4672 uqxtn(Vtmp1, T8B, Vtmp1, T8H); // uqxtn - write bottom half 4673 uqxtn(Vtmp1, T16B, Vtmp2, T8H); // uqxtn2 - write top half 4674 uqxtn(Vtmp2, T8B, Vtmp3, T8H); 4675 uqxtn(Vtmp2, T16B, Vtmp4, T8H); // uqxtn2 4676 get_fpsr(tmp1); 4677 cbnzw(tmp1, LOOP_8); 4678 st1(Vtmp1, Vtmp2, T16B, post(dst, 32)); 4679 subs(len, len, 32); 4680 add(src, src, 64); 4681 br(GE, NEXT_32); 4682 4683 BIND(LOOP_8); 4684 adds(len, len, 32-8); 4685 br(LT, LOOP_1); 4686 clear_fpsr(); // QC may be set from loop above, clear again 4687 BIND(NEXT_8); 4688 ld1(Vtmp1, T8H, src); 4689 uqxtn(Vtmp1, T8B, Vtmp1, T8H); 4690 get_fpsr(tmp1); 4691 cbnzw(tmp1, LOOP_1); 4692 st1(Vtmp1, T8B, post(dst, 8)); 4693 subs(len, len, 8); 4694 add(src, src, 16); 4695 br(GE, NEXT_8); 4696 4697 BIND(LOOP_1); 4698 adds(len, len, 8); 4699 br(LE, DONE); 4700 #else 4701 cbz(len, DONE); 4702 #endif 4703 BIND(NEXT_1); 4704 ldrh(tmp1, Address(post(src, 2))); 4705 tst(tmp1, 0xff00); 4706 br(NE, DONE); 4707 strb(tmp1, Address(post(dst, 1))); 4708 subs(len, len, 1); 4709 br(GT, NEXT_1); 4710 4711 BIND(DONE); 4712 sub(result, result, len); // Return index where we stopped 4713 } 4714 4715 // get_thread() can be called anywhere inside generated code so we 4716 // need to save whatever non-callee save context might get clobbered 4717 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed, 4718 // the call setup code. 4719 // 4720 // aarch64_get_thread_helper() clobbers only r0, r1, and flags. 4721 // 4722 void MacroAssembler::get_thread(Register dst) { 4723 RegSet saved_regs = RegSet::range(r0, r1) + lr - dst; 4724 push(saved_regs, sp); 4725 4726 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)); 4727 blrt(lr, 1, 0, 1); 4728 if (dst != c_rarg0) { 4729 mov(dst, c_rarg0); 4730 } 4731 4732 pop(saved_regs, sp); 4733 }