3172 // Note: src is destroyed
3173 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3174   Register rs = src->as_register();
3175   Register rd = dst->as_register_lo();
3176   __ sllx(rs, 32, rs);
3177   __ srl(rs->successor(), 0, rs->successor());
3178   __ or3(rs, rs->successor(), rd);
3179 }
3180 
3181 // Unpack a 64 bit value in a register into
3182 // two sequential registers.
3183 // src is unpacked into dst and dst->successor()
3184 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3185   Register rs = src->as_register_lo();
3186   Register rd = dst->as_register_hi();
3187   assert_different_registers(rs, rd, rd->successor());
3188   __ srlx(rs, 32, rd);
3189   __ srl (rs,  0, rd->successor());
3190 }
3191 
3192 
3193 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3194   LIR_Address* addr = addr_opr->as_address_ptr();
3195   assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");


3196 
3197   if (Assembler::is_simm13(addr->disp())) {
3198     __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());







3199   } else {
3200     __ set(addr->disp(), G3_scratch);
3201     __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());





3202   }
3203 }
3204 
3205 
3206 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3207   assert(result_reg->is_register(), "check");
3208   __ mov(G2_thread, result_reg->as_register());
3209 }
3210 
3211 #ifdef ASSERT
3212 // emit run-time assertion
3213 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3214   assert(op->code() == lir_assert, "must be");
3215 
3216   if (op->in_opr1()->is_valid()) {
3217     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3218     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3219   } else {
3220     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3221     assert(op->condition() == lir_cond_always, "no other conditions allowed");

3172 // Note: src is destroyed
3173 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3174   Register rs = src->as_register();
3175   Register rd = dst->as_register_lo();
3176   __ sllx(rs, 32, rs);
3177   __ srl(rs->successor(), 0, rs->successor());
3178   __ or3(rs, rs->successor(), rd);
3179 }
3180 
3181 // Unpack a 64 bit value in a register into
3182 // two sequential registers.
3183 // src is unpacked into dst and dst->successor()
3184 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3185   Register rs = src->as_register_lo();
3186   Register rd = dst->as_register_hi();
3187   assert_different_registers(rs, rd, rd->successor());
3188   __ srlx(rs, 32, rd);
3189   __ srl (rs,  0, rd->successor());
3190 }
3191 

3192 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3193   const LIR_Address* addr = addr_opr->as_address_ptr();
3194   assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3195   const Register dest_reg = dest->as_pointer_register();
3196   const Register base_reg = addr->base()->as_pointer_register();
3197 
3198   if (Assembler::is_simm13(addr->disp())) {
3199     if (addr->index()->is_valid()) {
3200       const Register index_reg = addr->index()->as_pointer_register();
3201       assert(index_reg != G3_scratch, "invariant");
3202       __ add(base_reg, addr->disp(), G3_scratch);
3203       __ add(index_reg, G3_scratch, dest_reg);
3204     } else {
3205       __ add(base_reg, addr->disp(), dest_reg);
3206     }
3207   } else {
3208     __ set(addr->disp(), G3_scratch);
3209     if (addr->index()->is_valid()) {
3210       const Register index_reg = addr->index()->as_pointer_register();
3211       assert(index_reg != G3_scratch, "invariant");
3212       __ add(index_reg, G3_scratch, G3_scratch);
3213     }
3214     __ add(base_reg, G3_scratch, dest_reg);
3215   }
3216 }
3217 
3218 
3219 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3220   assert(result_reg->is_register(), "check");
3221   __ mov(G2_thread, result_reg->as_register());
3222 }
3223 
3224 #ifdef ASSERT
3225 // emit run-time assertion
3226 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3227   assert(op->code() == lir_assert, "must be");
3228 
3229   if (op->in_opr1()->is_valid()) {
3230     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3231     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3232   } else {
3233     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3234     assert(op->condition() == lir_cond_always, "no other conditions allowed");