1 /*
2 * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2007, 2008, 2011, 2015, Red Hat, Inc.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef OS_CPU_BSD_ZERO_VM_ATOMIC_BSD_ZERO_HPP
27 #define OS_CPU_BSD_ZERO_VM_ATOMIC_BSD_ZERO_HPP
28
29 #include "runtime/os.hpp"
30
31 // Implementation of class atomic
32
33 #ifdef M68K
34
35 /*
36 * __m68k_cmpxchg
37 *
38 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
39 * Returns newval on success and oldval if no exchange happened.
40 * This implementation is processor specific and works on
41 * 68020 68030 68040 and 68060.
42 *
43 * It will not work on ColdFire, 68000 and 68010 since they lack the CAS
44 * instruction.
45 * Using a kernelhelper would be better for arch complete implementation.
46 *
47 */
48
49 static inline int __m68k_cmpxchg(int oldval, int newval, volatile int *ptr) {
50 int ret;
51 __asm __volatile ("cas%.l %0,%2,%1"
52 : "=d" (ret), "+m" (*(ptr))
53 : "d" (newval), "0" (oldval));
54 return ret;
55 }
56
57 /* Perform an atomic compare and swap: if the current value of `*PTR'
58 is OLDVAL, then write NEWVAL into `*PTR'. Return the contents of
59 `*PTR' before the operation.*/
60 static inline int m68k_compare_and_swap(volatile int *ptr,
61 int oldval,
62 int newval) {
63 for (;;) {
64 int prev = *ptr;
65 if (prev != oldval)
66 return prev;
67
68 if (__m68k_cmpxchg (prev, newval, ptr) == newval)
69 // Success.
70 return prev;
71
72 // We failed even though prev == oldval. Try again.
73 }
74 }
75
76 /* Atomically add an int to memory. */
77 static inline int m68k_add_and_fetch(volatile int *ptr, int add_value) {
78 for (;;) {
79 // Loop until success.
80
81 int prev = *ptr;
82
83 if (__m68k_cmpxchg (prev, prev + add_value, ptr) == prev + add_value)
84 return prev + add_value;
85 }
86 }
87
88 /* Atomically write VALUE into `*PTR' and returns the previous
89 contents of `*PTR'. */
90 static inline int m68k_lock_test_and_set(volatile int *ptr, int newval) {
91 for (;;) {
92 // Loop until success.
93 int prev = *ptr;
94
95 if (__m68k_cmpxchg (prev, newval, ptr) == prev)
96 return prev;
97 }
98 }
99 #endif // M68K
100
101 #ifdef ARM
102
103 /*
104 * __kernel_cmpxchg
105 *
106 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
107 * Return zero if *ptr was changed or non-zero if no exchange happened.
108 * The C flag is also set if *ptr was changed to allow for assembly
109 * optimization in the calling code.
110 *
111 */
112
113 typedef int (__kernel_cmpxchg_t)(int oldval, int newval, volatile int *ptr);
114 #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *) 0xffff0fc0)
115
116
117
118 /* Perform an atomic compare and swap: if the current value of `*PTR'
119 is OLDVAL, then write NEWVAL into `*PTR'. Return the contents of
120 `*PTR' before the operation.*/
121 static inline int arm_compare_and_swap(volatile int *ptr,
122 int oldval,
123 int newval) {
124 for (;;) {
125 int prev = *ptr;
126 if (prev != oldval)
127 return prev;
128
129 if (__kernel_cmpxchg (prev, newval, ptr) == 0)
130 // Success.
131 return prev;
132
133 // We failed even though prev == oldval. Try again.
134 }
135 }
136
137 /* Atomically add an int to memory. */
138 static inline int arm_add_and_fetch(volatile int *ptr, int add_value) {
139 for (;;) {
140 // Loop until a __kernel_cmpxchg succeeds.
141
142 int prev = *ptr;
143
144 if (__kernel_cmpxchg (prev, prev + add_value, ptr) == 0)
145 return prev + add_value;
146 }
147 }
148
149 /* Atomically write VALUE into `*PTR' and returns the previous
150 contents of `*PTR'. */
151 static inline int arm_lock_test_and_set(volatile int *ptr, int newval) {
152 for (;;) {
153 // Loop until a __kernel_cmpxchg succeeds.
154 int prev = *ptr;
155
156 if (__kernel_cmpxchg (prev, newval, ptr) == 0)
157 return prev;
158 }
159 }
160 #endif // ARM
161
162 #ifdef _LP64
163
164 template<>
165 inline void Atomic::specialized_store<int64_t>(int64_t store_value, volatile int64_t* dest) {
166 #if !defined(ARM) && !defined(M68K)
167 __sync_synchronize();
168 #endif
169 *dest = store_value;
170 }
171
172 template <>
173 inline int64_t Atomic::specialized_add<int64_t>(int64_t add_value, volatile int64_t* dest) {
174 #ifdef ARM
175 return arm_add_and_fetch(dest, add_value);
176 #else
177 #ifdef M68K
178 return m68k_add_and_fetch(dest, add_value);
179 #else
180 return __sync_add_and_fetch(dest, add_value);
181 #endif // M68K
182 #endif // ARM
183 }
184
185 template <>
186 inline int64_t Atomic::specialized_xchg<int64_t>(int64_t exchange_value, volatile int64_t* dest) {
187 #ifdef ARM
188 return arm_lock_test_and_set(dest, exchange_value);
189 #else
190 #ifdef M68K
191 return m68k_lock_test_and_set(dest, exchange_value);
192 #else
193 intptr_t result = __sync_lock_test_and_set (dest, exchange_value);
194 __sync_synchronize();
195 return result;
196 #endif // M68K
197 #endif // ARM
198 }
199
200 #else // _LP64
201
202 template<>
203 inline int64_t Atomic::specialized_load<int64_t>(const volatile int64_t* src) {
204 volatile int64_t dest;
205 os::atomic_copy64(src, &dest);
206 return dest;
207 }
208
209 template<>
210 inline void Atomic::specialized_store<int64_t>(int64_t store_value, volatile int64_t* dest) {
211 os::atomic_copy64((volatile int64_t*)&store_value, dest);
212 }
213
214 #endif // _LP64
215
216 template<>
217 inline void Atomic::specialized_store<int32_t>(int32_t store_value, volatile int32_t* dest) {
218 #if !defined(ARM) && !defined(M68K)
219 __sync_synchronize();
220 #endif
221 *dest = store_value;
222 }
223
224 template <>
225 inline int32_t Atomic::specialized_add<int32_t>(int32_t add_value, volatile int32_t* dest) {
226 #ifdef ARM
227 return arm_add_and_fetch(dest, add_value);
228 #else
229 #ifdef M68K
230 return m68k_add_and_fetch(dest, add_value);
231 #else
232 return __sync_add_and_fetch(dest, add_value);
233 #endif // M68K
234 #endif // ARM
235 }
236
237
238 template <>
239 inline int32_t Atomic::specialized_xchg<int32_t>(int32_t exchange_value, volatile int32_t* dest) {
240 #ifdef ARM
241 return arm_lock_test_and_set(dest, exchange_value);
242 #else
243 #ifdef M68K
244 return m68k_lock_test_and_set(dest, exchange_value);
245 #else
246 // __sync_lock_test_and_set is a bizarrely named atomic exchange
247 // operation. Note that some platforms only support this with the
248 // limitation that the only valid value to store is the immediate
249 // constant 1. There is a test for this in JNI_CreateJavaVM().
250 int32_t result = __sync_lock_test_and_set (dest, exchange_value);
251 // All atomic operations are expected to be full memory barriers
252 // (see atomic.hpp). However, __sync_lock_test_and_set is not
253 // a full memory barrier, but an acquire barrier. Hence, this added
254 // barrier.
255 __sync_synchronize();
256 return result;
257 #endif // M68K
258 #endif // ARM
259 }
260
261
262 template <>
263 inline int32_t Atomic::specialized_cmpxchg<int32_t>(int32_t exchange_value, volatile int32_t* dest, int32_t compare_value, cmpxchg_memory_order order) {
264 #ifdef ARM
265 return arm_compare_and_swap(dest, compare_value, exchange_value);
266 #else
267 #ifdef M68K
268 return m68k_compare_and_swap(dest, compare_value, exchange_value);
269 #else
270 return __sync_val_compare_and_swap(dest, compare_value, exchange_value);
271 #endif // M68K
272 #endif // ARM
273 }
274
275 template <>
276 inline int64_t Atomic::specialized_cmpxchg<int64_t>(int64_t exchange_value, volatile int64_t* dest, int64_t compare_value, cmpxchg_memory_order order) {
277 return __sync_val_compare_and_swap(dest, compare_value, exchange_value);
278 }
279
280 #endif // OS_CPU_BSD_ZERO_VM_ATOMIC_BSD_ZERO_HPP