1 /*
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   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  23  */
  24 
  25 #ifndef OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP
  26 #define OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP
  27 
  28 #include "runtime/os.hpp"
  29 #include "vm_version_arm.hpp"
  30 
  31 // Implementation of class atomic
  32 
  33 /*
  34  * Atomic long operations on 32-bit ARM
  35  * ARM v7 supports LDREXD/STREXD synchronization instructions so no problem.
  36  * ARM < v7 does not have explicit 64 atomic load/store capability.
  37  * However, gcc emits LDRD/STRD instructions on v5te and LDM/STM on v5t
  38  * when loading/storing 64 bits.
  39  * For non-MP machines (which is all we support for ARM < v7)
  40  * under current Linux distros these instructions appear atomic.
  41  * See section A3.5.3 of ARM Architecture Reference Manual for ARM v7.
  42  * Also, for cmpxchg64, if ARM < v7 we check for cmpxchg64 support in the
  43  * Linux kernel using _kuser_helper_version. See entry-armv.S in the Linux
  44  * kernel source or kernel_user_helpers.txt in Linux Doc.
  45  */
  46 
  47 inline void Atomic::store    (jbyte    store_value, jbyte*    dest) { *dest = store_value; }
  48 inline void Atomic::store    (jshort   store_value, jshort*   dest) { *dest = store_value; }
  49 inline void Atomic::store    (jint     store_value, jint*     dest) { *dest = store_value; }
  50 inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; }
  51 inline void Atomic::store_ptr(void*    store_value, void*     dest) { *(void**)dest = store_value; }
  52 
  53 inline void Atomic::store    (jbyte    store_value, volatile jbyte*    dest) { *dest = store_value; }
  54 inline void Atomic::store    (jshort   store_value, volatile jshort*   dest) { *dest = store_value; }
  55 inline void Atomic::store    (jint     store_value, volatile jint*     dest) { *dest = store_value; }
  56 inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; }
  57 inline void Atomic::store_ptr(void*    store_value, volatile void*     dest) { *(void* volatile *)dest = store_value; }
  58 
  59 inline jlong Atomic::load (const volatile jlong* src) {
  60   assert(((intx)src & (sizeof(jlong)-1)) == 0, "Atomic load jlong mis-aligned");
  61 #ifdef AARCH64
  62   return *src;
  63 #else
  64   return (*os::atomic_load_long_func)(src);
  65 #endif
  66 }
  67 
  68 inline void Atomic::store (jlong value, volatile jlong* dest) {
  69   assert(((intx)dest & (sizeof(jlong)-1)) == 0, "Atomic store jlong mis-aligned");
  70 #ifdef AARCH64
  71   *dest = value;
  72 #else
  73   (*os::atomic_store_long_func)(value, dest);
  74 #endif
  75 }
  76 
  77 inline void Atomic::store (jlong value, jlong* dest) {
  78   store(value, (volatile jlong*)dest);
  79 }
  80 
  81 // As per atomic.hpp all read-modify-write operations have to provide two-way
  82 // barriers semantics. For AARCH64 we are using load-acquire-with-reservation and
  83 // store-release-with-reservation. While load-acquire combined with store-release
  84 // do not generally form two-way barriers, their use with reservations does - the
  85 // ARMv8 architecture manual Section F "Barrier Litmus Tests" indicates they
  86 // provide sequentially consistent semantics. All we need to add is an explicit
  87 // barrier in the failure path of the cmpxchg operations (as these don't execute
  88 // the store) - arguably this may be overly cautious as there is a very low
  89 // likelihood that the hardware would pull loads/stores into the region guarded
  90 // by the reservation.
  91 //
  92 // For ARMv7 we add explicit barriers in the stubs.
  93 
  94 template<size_t byte_size>
  95 struct Atomic::PlatformAdd
  96   : Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> >
  97 {
  98   template<typename I, typename D>
  99   D add_and_fetch(I add_value, D volatile* dest) const;
 100 };
 101 
 102 template<>
 103 template<typename I, typename D>
 104 inline D Atomic::PlatformAdd<4>::add_and_fetch(I add_value, D volatile* dest) const {
 105   STATIC_ASSERT(4 == sizeof(I));
 106   STATIC_ASSERT(4 == sizeof(D));
 107 #ifdef AARCH64
 108   D val;
 109   int tmp;
 110   __asm__ volatile(
 111     "1:\n\t"
 112     " ldaxr %w[val], [%[dest]]\n\t"
 113     " add %w[val], %w[val], %w[add_val]\n\t"
 114     " stlxr %w[tmp], %w[val], [%[dest]]\n\t"
 115     " cbnz %w[tmp], 1b\n\t"
 116     : [val] "=&r" (val), [tmp] "=&r" (tmp)
 117     : [add_val] "r" (add_value), [dest] "r" (dest)
 118     : "memory");
 119   return val;
 120 #else
 121   return add_using_helper<jint>(os::atomic_add_func, add_value, dest);
 122 #endif
 123 }
 124 
 125 inline void Atomic::inc(volatile jint* dest) {
 126   Atomic::add(1, (volatile jint *)dest);
 127 }
 128 
 129 inline void Atomic::dec(volatile jint* dest) {
 130   Atomic::add(-1, (volatile jint *)dest);
 131 }
 132 
 133 #ifdef AARCH64
 134 template<>
 135 template<typename I, typename D>
 136 inline D Atomic::PlatformAdd<8>::add_and_fetch(I add_value, D volatile* dest) const {
 137   STATIC_ASSERT(8 == sizeof(I));
 138   STATIC_ASSERT(8 == sizeof(D));
 139   D val;
 140   int tmp;
 141   __asm__ volatile(
 142     "1:\n\t"
 143     " ldaxr %[val], [%[dest]]\n\t"
 144     " add %[val], %[val], %[add_val]\n\t"
 145     " stlxr %w[tmp], %[val], [%[dest]]\n\t"
 146     " cbnz %w[tmp], 1b\n\t"
 147     : [val] "=&r" (val), [tmp] "=&r" (tmp)
 148     : [add_val] "r" (add_value), [dest] "r" (dest)
 149     : "memory");
 150   return val;
 151 }
 152 #endif // AARCH64
 153 
 154 template<>
 155 struct Atomic::PlatformAdd<2>: Atomic::AddShortUsingInt {};
 156 
 157 inline void Atomic::inc_ptr(volatile intptr_t* dest) {
 158   Atomic::add_ptr(1, dest);
 159 }
 160 
 161 inline void Atomic::dec_ptr(volatile intptr_t* dest) {
 162   Atomic::add_ptr(-1, dest);
 163 }
 164 
 165 inline void Atomic::inc_ptr(volatile void* dest) {
 166   inc_ptr((volatile intptr_t*)dest);
 167 }
 168 
 169 inline void Atomic::dec_ptr(volatile void* dest) {
 170   dec_ptr((volatile intptr_t*)dest);
 171 }
 172 
 173 
 174 inline jint Atomic::xchg(jint exchange_value, volatile jint* dest) {
 175 #ifdef AARCH64
 176   jint old_val;
 177   int tmp;
 178   __asm__ volatile(
 179     "1:\n\t"
 180     " ldaxr %w[old_val], [%[dest]]\n\t"
 181     " stlxr %w[tmp], %w[new_val], [%[dest]]\n\t"
 182     " cbnz %w[tmp], 1b\n\t"
 183     : [old_val] "=&r" (old_val), [tmp] "=&r" (tmp)
 184     : [new_val] "r" (exchange_value), [dest] "r" (dest)
 185     : "memory");
 186   return old_val;
 187 #else
 188   return (*os::atomic_xchg_func)(exchange_value, dest);
 189 #endif
 190 }
 191 
 192 inline intptr_t Atomic::xchg_ptr(intptr_t exchange_value, volatile intptr_t* dest) {
 193 #ifdef AARCH64
 194   intptr_t old_val;
 195   int tmp;
 196   __asm__ volatile(
 197     "1:\n\t"
 198     " ldaxr %[old_val], [%[dest]]\n\t"
 199     " stlxr %w[tmp], %[new_val], [%[dest]]\n\t"
 200     " cbnz %w[tmp], 1b\n\t"
 201     : [old_val] "=&r" (old_val), [tmp] "=&r" (tmp)
 202     : [new_val] "r" (exchange_value), [dest] "r" (dest)
 203     : "memory");
 204   return old_val;
 205 #else
 206   return (intptr_t)xchg((jint)exchange_value, (volatile jint*)dest);
 207 #endif
 208 }
 209 
 210 inline void* Atomic::xchg_ptr(void* exchange_value, volatile void* dest) {
 211   return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest);
 212 }
 213 
 214 // The memory_order parameter is ignored - we always provide the strongest/most-conservative ordering
 215 
 216 // No direct support for cmpxchg of bytes; emulate using int.
 217 template<>
 218 struct Atomic::PlatformCmpxchg<1> : Atomic::CmpxchgByteUsingInt {};
 219 
 220 #ifndef AARCH64
 221 
 222 inline jint reorder_cmpxchg_func(jint exchange_value,
 223                                  jint volatile* dest,
 224                                  jint compare_value) {
 225   // Warning:  Arguments are swapped to avoid moving them for kernel call
 226   return (*os::atomic_cmpxchg_func)(compare_value, exchange_value, dest);
 227 }
 228 
 229 inline jlong reorder_cmpxchg_long_func(jlong exchange_value,
 230                                        jlong volatile* dest,
 231                                        jlong compare_value) {
 232   assert(VM_Version::supports_cx8(), "Atomic compare and exchange jlong not supported on this architecture!");
 233   // Warning:  Arguments are swapped to avoid moving them for kernel call
 234   return (*os::atomic_cmpxchg_long_func)(compare_value, exchange_value, dest);
 235 }
 236 
 237 #endif // !AARCH64
 238 
 239 template<>
 240 template<typename T>
 241 inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value,
 242                                                 T volatile* dest,
 243                                                 T compare_value,
 244                                                 cmpxchg_memory_order order) const {
 245   STATIC_ASSERT(4 == sizeof(T));
 246 #ifdef AARCH64
 247   T rv;
 248   int tmp;
 249   __asm__ volatile(
 250     "1:\n\t"
 251     " ldaxr %w[rv], [%[dest]]\n\t"
 252     " cmp %w[rv], %w[cv]\n\t"
 253     " b.ne 2f\n\t"
 254     " stlxr %w[tmp], %w[ev], [%[dest]]\n\t"
 255     " cbnz %w[tmp], 1b\n\t"
 256     " b 3f\n\t"
 257     "2:\n\t"
 258     " dmb sy\n\t"
 259     "3:\n\t"
 260     : [rv] "=&r" (rv), [tmp] "=&r" (tmp)
 261     : [ev] "r" (exchange_value), [dest] "r" (dest), [cv] "r" (compare_value)
 262     : "memory");
 263   return rv;
 264 #else
 265   return cmpxchg_using_helper<jint>(reorder_cmpxchg_func, exchange_value, dest, compare_value);
 266 #endif
 267 }
 268 
 269 template<>
 270 template<typename T>
 271 inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
 272                                                 T volatile* dest,
 273                                                 T compare_value,
 274                                                 cmpxchg_memory_order order) const {
 275   STATIC_ASSERT(8 == sizeof(T));
 276 #ifdef AARCH64
 277   T rv;
 278   int tmp;
 279   __asm__ volatile(
 280     "1:\n\t"
 281     " ldaxr %[rv], [%[dest]]\n\t"
 282     " cmp %[rv], %[cv]\n\t"
 283     " b.ne 2f\n\t"
 284     " stlxr %w[tmp], %[ev], [%[dest]]\n\t"
 285     " cbnz %w[tmp], 1b\n\t"
 286     " b 3f\n\t"
 287     "2:\n\t"
 288     " dmb sy\n\t"
 289     "3:\n\t"
 290     : [rv] "=&r" (rv), [tmp] "=&r" (tmp)
 291     : [ev] "r" (exchange_value), [dest] "r" (dest), [cv] "r" (compare_value)
 292     : "memory");
 293   return rv;
 294 #else
 295   return cmpxchg_using_helper<jlong>(reorder_cmpxchg_long_func, exchange_value, dest, compare_value);
 296 #endif
 297 }
 298 
 299 #endif // OS_CPU_LINUX_ARM_VM_ATOMIC_LINUX_ARM_HPP