1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
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24 */
25
26 #ifndef OS_CPU_LINUX_PPC_VM_ATOMIC_LINUX_PPC_HPP
27 #define OS_CPU_LINUX_PPC_VM_ATOMIC_LINUX_PPC_HPP
28
29 #ifndef PPC64
30 #error "Atomic currently only implemented for PPC64"
31 #endif
32
33 // Implementation of class atomic
34
35 inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; }
36 inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; }
37 inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; }
38 inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; }
39 inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; }
40 inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; }
41
42 inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; }
43 inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; }
44 inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; }
45 inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; }
46 inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; }
47 inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; }
48
49 inline jlong Atomic::load(const volatile jlong* src) { return *src; }
50
51 //
52 // machine barrier instructions:
53 //
54 // - sync two-way memory barrier, aka fence
55 // - lwsync orders Store|Store,
56 // Load|Store,
57 // Load|Load,
58 // but not Store|Load
59 // - eieio orders memory accesses for device memory (only)
60 // - isync invalidates speculatively executed instructions
61 // From the POWER ISA 2.06 documentation:
62 // "[...] an isync instruction prevents the execution of
63 // instructions following the isync until instructions
64 // preceding the isync have completed, [...]"
65 // From IBM's AIX assembler reference:
66 // "The isync [...] instructions causes the processor to
67 // refetch any instructions that might have been fetched
68 // prior to the isync instruction. The instruction isync
69 // causes the processor to wait for all previous instructions
70 // to complete. Then any instructions already fetched are
71 // discarded and instruction processing continues in the
72 // environment established by the previous instructions."
73 //
74 // semantic barrier instructions:
75 // (as defined in orderAccess.hpp)
76 //
77 // - release orders Store|Store, (maps to lwsync)
78 // Load|Store
79 // - acquire orders Load|Store, (maps to lwsync)
80 // Load|Load
81 // - fence orders Store|Store, (maps to sync)
82 // Load|Store,
83 // Load|Load,
84 // Store|Load
85 //
86
87 #define strasm_sync "\n sync \n"
88 #define strasm_lwsync "\n lwsync \n"
89 #define strasm_isync "\n isync \n"
90 #define strasm_release strasm_lwsync
91 #define strasm_acquire strasm_lwsync
92 #define strasm_fence strasm_sync
93 #define strasm_nobarrier ""
94 #define strasm_nobarrier_clobber_memory ""
95
96 template<size_t byte_size>
97 struct Atomic::PlatformAdd
98 : Atomic::AddAndFetch<Atomic::PlatformAdd<byte_size> >
99 {
100 template<typename I, typename D>
101 D add_and_fetch(I add_value, D volatile* dest) const;
102 };
103
104 template<>
105 template<typename I, typename D>
106 inline D Atomic::PlatformAdd<4>::add_and_fetch(I add_value, D volatile* dest) const {
107 STATIC_ASSERT(4 == sizeof(I));
108 STATIC_ASSERT(4 == sizeof(D));
109
110 D result;
111
112 __asm__ __volatile__ (
113 strasm_lwsync
114 "1: lwarx %0, 0, %2 \n"
115 " add %0, %0, %1 \n"
116 " stwcx. %0, 0, %2 \n"
117 " bne- 1b \n"
118 strasm_isync
119 : /*%0*/"=&r" (result)
120 : /*%1*/"r" (add_value), /*%2*/"r" (dest)
121 : "cc", "memory" );
122
123 return result;
124 }
125
126
127 template<>
128 template<typename I, typename D>
129 inline D Atomic::PlatformAdd<8>::add_and_fetch(I add_value, D volatile* dest) const {
130 STATIC_ASSERT(8 == sizeof(I));
131 STATIC_ASSERT(8 == sizeof(D));
132
133 D result;
134
135 __asm__ __volatile__ (
136 strasm_lwsync
137 "1: ldarx %0, 0, %2 \n"
138 " add %0, %0, %1 \n"
139 " stdcx. %0, 0, %2 \n"
140 " bne- 1b \n"
141 strasm_isync
142 : /*%0*/"=&r" (result)
143 : /*%1*/"r" (add_value), /*%2*/"r" (dest)
144 : "cc", "memory" );
145
146 return result;
147 }
148
149 template<>
150 template<typename T>
151 inline T Atomic::PlatformXchg<4>::operator()(T exchange_value,
152 T volatile* dest) const {
153 // Note that xchg_ptr doesn't necessarily do an acquire
154 // (see synchronizer.cpp).
155
156 T old_value;
157 const uint64_t zero = 0;
158
159 __asm__ __volatile__ (
160 /* lwsync */
161 strasm_lwsync
162 /* atomic loop */
163 "1: \n"
164 " lwarx %[old_value], %[dest], %[zero] \n"
165 " stwcx. %[exchange_value], %[dest], %[zero] \n"
166 " bne- 1b \n"
167 /* isync */
168 strasm_sync
169 /* exit */
170 "2: \n"
171 /* out */
172 : [old_value] "=&r" (old_value),
173 "=m" (*dest)
174 /* in */
175 : [dest] "b" (dest),
176 [zero] "r" (zero),
177 [exchange_value] "r" (exchange_value),
178 "m" (*dest)
179 /* clobber */
180 : "cc",
181 "memory"
182 );
183
184 return old_value;
185 }
186
187 template<>
188 template<typename T>
189 inline T Atomic::PlatformXchg<8>::operator()(T exchange_value,
190 T volatile* dest) const {
191 STATIC_ASSERT(8 == sizeof(T));
192 // Note that xchg_ptr doesn't necessarily do an acquire
193 // (see synchronizer.cpp).
194
195 T old_value;
196 const uint64_t zero = 0;
197
198 __asm__ __volatile__ (
199 /* lwsync */
200 strasm_lwsync
201 /* atomic loop */
202 "1: \n"
203 " ldarx %[old_value], %[dest], %[zero] \n"
204 " stdcx. %[exchange_value], %[dest], %[zero] \n"
205 " bne- 1b \n"
206 /* isync */
207 strasm_sync
208 /* exit */
209 "2: \n"
210 /* out */
211 : [old_value] "=&r" (old_value),
212 "=m" (*dest)
213 /* in */
214 : [dest] "b" (dest),
215 [zero] "r" (zero),
216 [exchange_value] "r" (exchange_value),
217 "m" (*dest)
218 /* clobber */
219 : "cc",
220 "memory"
221 );
222
223 return old_value;
224 }
225
226 inline void cmpxchg_pre_membar(cmpxchg_memory_order order) {
227 if (order != memory_order_relaxed) {
228 __asm__ __volatile__ (
229 /* fence */
230 strasm_sync
231 );
232 }
233 }
234
235 inline void cmpxchg_post_membar(cmpxchg_memory_order order) {
236 if (order != memory_order_relaxed) {
237 __asm__ __volatile__ (
238 /* fence */
239 strasm_sync
240 );
241 }
242 }
243
244 template<>
245 template<typename T>
246 inline T Atomic::PlatformCmpxchg<1>::operator()(T exchange_value,
247 T volatile* dest,
248 T compare_value,
249 cmpxchg_memory_order order) const {
250 STATIC_ASSERT(1 == sizeof(T));
251
252 // Note that cmpxchg guarantees a two-way memory barrier across
253 // the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
254 // specified otherwise (see atomic.hpp).
255
256 // Using 32 bit internally.
257 volatile int *dest_base = (volatile int*)((uintptr_t)dest & ~3);
258
259 #ifdef VM_LITTLE_ENDIAN
260 const unsigned int shift_amount = ((uintptr_t)dest & 3) * 8;
261 #else
262 const unsigned int shift_amount = ((~(uintptr_t)dest) & 3) * 8;
263 #endif
264 const unsigned int masked_compare_val = ((unsigned int)(unsigned char)compare_value),
265 masked_exchange_val = ((unsigned int)(unsigned char)exchange_value),
266 xor_value = (masked_compare_val ^ masked_exchange_val) << shift_amount;
267
268 unsigned int old_value, value32;
269
270 cmpxchg_pre_membar(order);
271
272 __asm__ __volatile__ (
273 /* simple guard */
274 " lbz %[old_value], 0(%[dest]) \n"
275 " cmpw %[masked_compare_val], %[old_value] \n"
276 " bne- 2f \n"
277 /* atomic loop */
278 "1: \n"
279 " lwarx %[value32], 0, %[dest_base] \n"
280 /* extract byte and compare */
281 " srd %[old_value], %[value32], %[shift_amount] \n"
282 " clrldi %[old_value], %[old_value], 56 \n"
283 " cmpw %[masked_compare_val], %[old_value] \n"
284 " bne- 2f \n"
285 /* replace byte and try to store */
286 " xor %[value32], %[xor_value], %[value32] \n"
287 " stwcx. %[value32], 0, %[dest_base] \n"
288 " bne- 1b \n"
289 /* exit */
290 "2: \n"
291 /* out */
292 : [old_value] "=&r" (old_value),
293 [value32] "=&r" (value32),
294 "=m" (*dest),
295 "=m" (*dest_base)
296 /* in */
297 : [dest] "b" (dest),
298 [dest_base] "b" (dest_base),
299 [shift_amount] "r" (shift_amount),
300 [masked_compare_val] "r" (masked_compare_val),
301 [xor_value] "r" (xor_value),
302 "m" (*dest),
303 "m" (*dest_base)
304 /* clobber */
305 : "cc",
306 "memory"
307 );
308
309 cmpxchg_post_membar(order);
310
311 return PrimitiveConversions::cast<T>((unsigned char)old_value);
312 }
313
314 template<>
315 template<typename T>
316 inline T Atomic::PlatformCmpxchg<4>::operator()(T exchange_value,
317 T volatile* dest,
318 T compare_value,
319 cmpxchg_memory_order order) const {
320 STATIC_ASSERT(4 == sizeof(T));
321
322 // Note that cmpxchg guarantees a two-way memory barrier across
323 // the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
324 // specified otherwise (see atomic.hpp).
325
326 T old_value;
327 const uint64_t zero = 0;
328
329 cmpxchg_pre_membar(order);
330
331 __asm__ __volatile__ (
332 /* simple guard */
333 " lwz %[old_value], 0(%[dest]) \n"
334 " cmpw %[compare_value], %[old_value] \n"
335 " bne- 2f \n"
336 /* atomic loop */
337 "1: \n"
338 " lwarx %[old_value], %[dest], %[zero] \n"
339 " cmpw %[compare_value], %[old_value] \n"
340 " bne- 2f \n"
341 " stwcx. %[exchange_value], %[dest], %[zero] \n"
342 " bne- 1b \n"
343 /* exit */
344 "2: \n"
345 /* out */
346 : [old_value] "=&r" (old_value),
347 "=m" (*dest)
348 /* in */
349 : [dest] "b" (dest),
350 [zero] "r" (zero),
351 [compare_value] "r" (compare_value),
352 [exchange_value] "r" (exchange_value),
353 "m" (*dest)
354 /* clobber */
355 : "cc",
356 "memory"
357 );
358
359 cmpxchg_post_membar(order);
360
361 return old_value;
362 }
363
364 template<>
365 template<typename T>
366 inline T Atomic::PlatformCmpxchg<8>::operator()(T exchange_value,
367 T volatile* dest,
368 T compare_value,
369 cmpxchg_memory_order order) const {
370 STATIC_ASSERT(8 == sizeof(T));
371
372 // Note that cmpxchg guarantees a two-way memory barrier across
373 // the cmpxchg, so it's really a a 'fence_cmpxchg_fence' if not
374 // specified otherwise (see atomic.hpp).
375
376 T old_value;
377 const uint64_t zero = 0;
378
379 cmpxchg_pre_membar(order);
380
381 __asm__ __volatile__ (
382 /* simple guard */
383 " ld %[old_value], 0(%[dest]) \n"
384 " cmpd %[compare_value], %[old_value] \n"
385 " bne- 2f \n"
386 /* atomic loop */
387 "1: \n"
388 " ldarx %[old_value], %[dest], %[zero] \n"
389 " cmpd %[compare_value], %[old_value] \n"
390 " bne- 2f \n"
391 " stdcx. %[exchange_value], %[dest], %[zero] \n"
392 " bne- 1b \n"
393 /* exit */
394 "2: \n"
395 /* out */
396 : [old_value] "=&r" (old_value),
397 "=m" (*dest)
398 /* in */
399 : [dest] "b" (dest),
400 [zero] "r" (zero),
401 [compare_value] "r" (compare_value),
402 [exchange_value] "r" (exchange_value),
403 "m" (*dest)
404 /* clobber */
405 : "cc",
406 "memory"
407 );
408
409 cmpxchg_post_membar(order);
410
411 return old_value;
412 }
413
414 #undef strasm_sync
415 #undef strasm_lwsync
416 #undef strasm_isync
417 #undef strasm_release
418 #undef strasm_acquire
419 #undef strasm_fence
420 #undef strasm_nobarrier
421 #undef strasm_nobarrier_clobber_memory
422
423 #endif // OS_CPU_LINUX_PPC_VM_ATOMIC_LINUX_PPC_HPP