< prev index next >

src/hotspot/os_cpu/linux_sparc/orderAccess_linux_sparc.inline.hpp

Print this page
rev 47383 : [mq]: OrderAccess_refactoring
   1 /*
   2  * Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


  30 // Implementation of class OrderAccess.
  31 
  32 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
  33 static inline void compiler_barrier() {
  34   __asm__ volatile ("" : : : "memory");
  35 }
  36 
  37 // Assume TSO.
  38 
  39 inline void OrderAccess::loadload()   { compiler_barrier(); }
  40 inline void OrderAccess::storestore() { compiler_barrier(); }
  41 inline void OrderAccess::loadstore()  { compiler_barrier(); }
  42 inline void OrderAccess::storeload()  { fence();            }
  43 
  44 inline void OrderAccess::acquire()    { compiler_barrier(); }
  45 inline void OrderAccess::release()    { compiler_barrier(); }
  46 
  47 inline void OrderAccess::fence() {
  48   __asm__ volatile ("membar  #StoreLoad" : : : "memory");
  49 }
  50 
  51 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1
  52 
  53 #endif // OS_CPU_LINUX_SPARC_VM_ORDERACCESS_LINUX_SPARC_INLINE_HPP
   1 /*
   2  * Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *


  30 // Implementation of class OrderAccess.
  31 
  32 // A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
  33 static inline void compiler_barrier() {
  34   __asm__ volatile ("" : : : "memory");
  35 }
  36 
  37 // Assume TSO.
  38 
  39 inline void OrderAccess::loadload()   { compiler_barrier(); }
  40 inline void OrderAccess::storestore() { compiler_barrier(); }
  41 inline void OrderAccess::loadstore()  { compiler_barrier(); }
  42 inline void OrderAccess::storeload()  { fence();            }
  43 
  44 inline void OrderAccess::acquire()    { compiler_barrier(); }
  45 inline void OrderAccess::release()    { compiler_barrier(); }
  46 
  47 inline void OrderAccess::fence() {
  48   __asm__ volatile ("membar  #StoreLoad" : : : "memory");
  49 }


  50 
  51 #endif // OS_CPU_LINUX_SPARC_VM_ORDERACCESS_LINUX_SPARC_INLINE_HPP
< prev index next >