1 /*
   2  * Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright 2007, 2008, 2009 Red Hat, Inc.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP
  27 #define OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP
  28 
  29 #include "runtime/orderAccess.hpp"
  30 
  31 #ifdef ARM
  32 
  33 /*
  34  * ARM Kernel helper for memory barrier.
  35  * Using __asm __volatile ("":::"memory") does not work reliable on ARM
  36  * and gcc __sync_synchronize(); implementation does not use the kernel
  37  * helper for all gcc versions so it is unreliable to use as well.
  38  */
  39 typedef void (__kernel_dmb_t) (void);
  40 #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
  41 
  42 #define FULL_MEM_BARRIER __kernel_dmb()
  43 #define LIGHT_MEM_BARRIER __kernel_dmb()
  44 
  45 #else // ARM
  46 
  47 #define FULL_MEM_BARRIER __sync_synchronize()
  48 
  49 #ifdef PPC
  50 
  51 #ifdef __NO_LWSYNC__
  52 #define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
  53 #else
  54 #define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
  55 #endif
  56 
  57 #else // PPC
  58 
  59 #ifdef ALPHA
  60 
  61 #define LIGHT_MEM_BARRIER __sync_synchronize()
  62 
  63 #else // ALPHA
  64 
  65 #define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
  66 
  67 #endif // ALPHA
  68 
  69 #endif // PPC
  70 
  71 #endif // ARM
  72 
  73 // Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
  74 // to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.
  75 
  76 inline void OrderAccess::loadload()   { LIGHT_MEM_BARRIER; }
  77 inline void OrderAccess::storestore() { LIGHT_MEM_BARRIER; }
  78 inline void OrderAccess::loadstore()  { LIGHT_MEM_BARRIER; }
  79 inline void OrderAccess::storeload()  { FULL_MEM_BARRIER;  }
  80 
  81 inline void OrderAccess::acquire()    { LIGHT_MEM_BARRIER; }
  82 inline void OrderAccess::release()    { LIGHT_MEM_BARRIER; }
  83 
  84 inline void OrderAccess::fence()      { FULL_MEM_BARRIER;  }
  85 
  86 #define VM_HAS_GENERALIZED_ORDER_ACCESS 1
  87 
  88 #endif // OS_CPU_LINUX_ZERO_VM_ORDERACCESS_LINUX_ZERO_INLINE_HPP