1 /*
   2  * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "c1/c1_Defs.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "ci/ciUtilities.hpp"
  32 #include "gc/shared/cardTable.hpp"
  33 #include "gc/shared/cardTableModRefBS.hpp"
  34 #include "interpreter/interpreter.hpp"
  35 #include "nativeInst_arm.hpp"
  36 #include "oops/compiledICHolder.hpp"
  37 #include "oops/oop.inline.hpp"
  38 #include "prims/jvmtiExport.hpp"
  39 #include "register_arm.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "runtime/signature.hpp"
  42 #include "runtime/vframeArray.hpp"
  43 #include "utilities/align.hpp"
  44 #include "vmreg_arm.inline.hpp"
  45 #if INCLUDE_ALL_GCS
  46 #include "gc/g1/g1CardTable.hpp"
  47 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
  48 #endif
  49 
  50 // Note: Rtemp usage is this file should not impact C2 and should be
  51 // correct as long as it is not implicitly used in lower layers (the
  52 // arm [macro]assembler) and used with care in the other C1 specific
  53 // files.
  54 
  55 // Implementation of StubAssembler
  56 
  57 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
  58   mov(R0, Rthread);
  59 
  60   int call_offset = set_last_Java_frame(SP, FP, false, Rtemp);
  61 
  62   call(entry);
  63   if (call_offset == -1) { // PC not saved
  64     call_offset = offset();
  65   }
  66   reset_last_Java_frame(Rtemp);
  67 
  68   assert(frame_size() != no_frame_size, "frame must be fixed");
  69   if (_stub_id != Runtime1::forward_exception_id) {
  70     ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
  71   }
  72 
  73   if (oop_result1->is_valid()) {
  74     assert_different_registers(oop_result1, R3, Rtemp);
  75     get_vm_result(oop_result1, Rtemp);
  76   }
  77   if (metadata_result->is_valid()) {
  78     assert_different_registers(metadata_result, R3, Rtemp);
  79     get_vm_result_2(metadata_result, Rtemp);
  80   }
  81 
  82   // Check for pending exception
  83   // unpack_with_exception_in_tls path is taken through
  84   // Runtime1::exception_handler_for_pc
  85   if (_stub_id != Runtime1::forward_exception_id) {
  86     assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id");
  87 #ifdef AARCH64
  88     Label skip;
  89     cbz(R3, skip);
  90     jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp);
  91     bind(skip);
  92 #else
  93     cmp(R3, 0);
  94     jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne);
  95 #endif // AARCH64
  96   } else {
  97 #ifdef ASSERT
  98     // Should not have pending exception in forward_exception stub
  99     ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
 100     cmp(R3, 0);
 101     breakpoint(ne);
 102 #endif // ASSERT
 103   }
 104   return call_offset;
 105 }
 106 
 107 
 108 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
 109   if (arg1 != R1) {
 110     mov(R1, arg1);
 111   }
 112   return call_RT(oop_result1, metadata_result, entry, 1);
 113 }
 114 
 115 
 116 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
 117   assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise");
 118   return call_RT(oop_result1, metadata_result, entry, 2);
 119 }
 120 
 121 
 122 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
 123   assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise");
 124   return call_RT(oop_result1, metadata_result, entry, 3);
 125 }
 126 
 127 
 128 #define __ sasm->
 129 
 130 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime?
 131 #ifdef AARCH64
 132 
 133   //
 134   // On AArch64 registers save area has the following layout:
 135   //
 136   // |---------------------|
 137   // | return address (LR) |
 138   // | FP                  |
 139   // |---------------------|
 140   // | D31                 |
 141   // | ...                 |
 142   // | D0                  |
 143   // |---------------------|
 144   // | padding             |
 145   // |---------------------|
 146   // | R28                 |
 147   // | ...                 |
 148   // | R0                  |
 149   // |---------------------| <-- SP
 150   //
 151 
 152 enum RegisterLayout {
 153   number_of_saved_gprs = 29,
 154   number_of_saved_fprs = FloatRegisterImpl::number_of_registers,
 155 
 156   R0_offset  = 0,
 157   D0_offset  = R0_offset + number_of_saved_gprs + 1,
 158   FP_offset  = D0_offset + number_of_saved_fprs,
 159   LR_offset  = FP_offset + 1,
 160 
 161   reg_save_size = LR_offset + 1,
 162 
 163   arg1_offset = reg_save_size * wordSize,
 164   arg2_offset = (reg_save_size + 1) * wordSize
 165 };
 166 
 167 #else
 168 
 169 enum RegisterLayout {
 170   fpu_save_size = pd_nof_fpu_regs_reg_alloc,
 171 #ifndef __SOFTFP__
 172   D0_offset = 0,
 173 #endif
 174   R0_offset = fpu_save_size,
 175   R1_offset,
 176   R2_offset,
 177   R3_offset,
 178   R4_offset,
 179   R5_offset,
 180   R6_offset,
 181 #if (FP_REG_NUM != 7)
 182   R7_offset,
 183 #endif
 184   R8_offset,
 185   R9_offset,
 186   R10_offset,
 187 #if (FP_REG_NUM != 11)
 188   R11_offset,
 189 #endif
 190   R12_offset,
 191   FP_offset,
 192   LR_offset,
 193   reg_save_size,
 194   arg1_offset = reg_save_size * wordSize,
 195   arg2_offset = (reg_save_size + 1) * wordSize
 196 };
 197 
 198 #endif // AARCH64
 199 
 200 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
 201   sasm->set_frame_size(reg_save_size /* in words */);
 202 
 203   // Record saved value locations in an OopMap.
 204   // Locations are offsets from sp after runtime call.
 205   OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0);
 206 
 207 #ifdef AARCH64
 208   for (int i = 0; i < number_of_saved_gprs; i++) {
 209     map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());
 210   }
 211   map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg());
 212   map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg());
 213 
 214   if (save_fpu_registers) {
 215     for (int i = 0; i < number_of_saved_fprs; i++) {
 216       map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());
 217     }
 218   }
 219 #else
 220   int j=0;
 221   for (int i = R0_offset; i < R10_offset; i++) {
 222     if (j == FP_REG_NUM) {
 223       // skip the FP register, saved below
 224       j++;
 225     }
 226     map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
 227     j++;
 228   }
 229   assert(j == R10->encoding(), "must be");
 230 #if (FP_REG_NUM != 11)
 231   // add R11, if not saved as FP
 232   map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
 233 #endif
 234   map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg());
 235   map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg());
 236 
 237   if (save_fpu_registers) {
 238     for (int i = 0; i < fpu_save_size; i++) {
 239       map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
 240     }
 241   }
 242 #endif // AARCH64
 243 
 244   return map;
 245 }
 246 
 247 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
 248   __ block_comment("save_live_registers");
 249   sasm->set_frame_size(reg_save_size /* in words */);
 250 
 251 #ifdef AARCH64
 252   assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");
 253 
 254   __ raw_push(FP, LR);
 255 
 256   __ sub(SP, SP, (reg_save_size - 2) * wordSize);
 257 
 258   for (int i = 0; i < align_down((int)number_of_saved_gprs, 2); i += 2) {
 259     __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
 260   }
 261 
 262   if (is_odd(number_of_saved_gprs)) {
 263     int i = number_of_saved_gprs - 1;
 264     __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize));
 265   }
 266 
 267   if (save_fpu_registers) {
 268     assert (is_even(number_of_saved_fprs), "adjust this code");
 269     for (int i = 0; i < number_of_saved_fprs; i += 2) {
 270       __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
 271     }
 272   }
 273 #else
 274   __ push(RegisterSet(FP) | RegisterSet(LR));
 275   __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
 276   if (save_fpu_registers) {
 277     __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
 278   } else {
 279     __ sub(SP, SP, fpu_save_size * wordSize);
 280   }
 281 #endif // AARCH64
 282 
 283   return generate_oop_map(sasm, save_fpu_registers);
 284 }
 285 
 286 
 287 static void restore_live_registers(StubAssembler* sasm,
 288                                    bool restore_R0,
 289                                    bool restore_FP_LR,
 290                                    bool do_return,
 291                                    bool restore_fpu_registers = HaveVFP) {
 292   __ block_comment("restore_live_registers");
 293 
 294 #ifdef AARCH64
 295   if (restore_R0) {
 296     __ ldr(R0, Address(SP, R0_offset * wordSize));
 297   }
 298 
 299   assert(is_odd(number_of_saved_gprs), "adjust this code");
 300   for (int i = 1; i < number_of_saved_gprs; i += 2) {
 301     __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
 302   }
 303 
 304   if (restore_fpu_registers) {
 305     assert (is_even(number_of_saved_fprs), "adjust this code");
 306     for (int i = 0; i < number_of_saved_fprs; i += 2) {
 307       __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
 308     }
 309   }
 310 
 311   __ add(SP, SP, (reg_save_size - 2) * wordSize);
 312 
 313   if (restore_FP_LR) {
 314     __ raw_pop(FP, LR);
 315     if (do_return) {
 316       __ ret();
 317     }
 318   } else {
 319     assert (!do_return, "return without restoring FP/LR");
 320   }
 321 #else
 322   if (restore_fpu_registers) {
 323     __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
 324     if (!restore_R0) {
 325       __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize);
 326     }
 327   } else {
 328     __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize);
 329   }
 330   __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
 331   if (restore_FP_LR) {
 332     __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR));
 333   } else {
 334     assert (!do_return, "return without restoring FP/LR");
 335   }
 336 #endif // AARCH64
 337 }
 338 
 339 
 340 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 341   restore_live_registers(sasm, false, true, true, restore_fpu_registers);
 342 }
 343 
 344 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 345   restore_live_registers(sasm, true, true, true, restore_fpu_registers);
 346 }
 347 
 348 #ifndef AARCH64
 349 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 350   restore_live_registers(sasm, true, false, false, restore_fpu_registers);
 351 }
 352 #endif // !AARCH64
 353 
 354 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
 355   restore_live_registers(sasm, true, true, false, restore_fpu_registers);
 356 }
 357 
 358 
 359 void Runtime1::initialize_pd() {
 360 }
 361 
 362 
 363 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
 364   OopMap* oop_map = save_live_registers(sasm);
 365 
 366   if (has_argument) {
 367     __ ldr(R1, Address(SP, arg1_offset));
 368   }
 369 
 370   int call_offset = __ call_RT(noreg, noreg, target);
 371   OopMapSet* oop_maps = new OopMapSet();
 372   oop_maps->add_gc_map(call_offset, oop_map);
 373 
 374   DEBUG_ONLY(STOP("generate_exception_throw");)  // Should not reach here
 375   return oop_maps;
 376 }
 377 
 378 
 379 static void restore_sp_for_method_handle(StubAssembler* sasm) {
 380   // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site.
 381   __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset()));
 382 #ifdef AARCH64
 383   Label skip;
 384   __ cbz(Rtemp, skip);
 385   __ mov(SP, Rmh_SP_save);
 386   __ bind(skip);
 387 #else
 388   __ cmp(Rtemp, 0);
 389   __ mov(SP, Rmh_SP_save, ne);
 390 #endif // AARCH64
 391 }
 392 
 393 
 394 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
 395   __ block_comment("generate_handle_exception");
 396 
 397   bool save_fpu_registers = false;
 398 
 399   // Save registers, if required.
 400   OopMapSet* oop_maps = new OopMapSet();
 401   OopMap* oop_map = NULL;
 402 
 403   switch (id) {
 404   case forward_exception_id: {
 405     save_fpu_registers = HaveVFP;
 406     oop_map = generate_oop_map(sasm);
 407     __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset()));
 408     __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize));
 409     Register zero = __ zero_register(Rtemp);
 410     __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
 411     break;
 412   }
 413   case handle_exception_id:
 414     save_fpu_registers = HaveVFP;
 415     // fall-through
 416   case handle_exception_nofpu_id:
 417     // At this point all registers MAY be live.
 418     oop_map = save_live_registers(sasm, save_fpu_registers);
 419     break;
 420   case handle_exception_from_callee_id:
 421     // At this point all registers except exception oop (R4/R19) and
 422     // exception pc (R5/R20) are dead.
 423     oop_map = save_live_registers(sasm);  // TODO it's not required to save all registers
 424     break;
 425   default:  ShouldNotReachHere();
 426   }
 427 
 428   __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
 429   __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
 430 
 431   __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address
 432 
 433   int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
 434   oop_maps->add_gc_map(call_offset, oop_map);
 435 
 436   // Exception handler found
 437   __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address
 438 
 439   // Restore the registers that were saved at the beginning, remove
 440   // frame and jump to the exception handler.
 441   switch (id) {
 442   case forward_exception_id:
 443   case handle_exception_nofpu_id:
 444   case handle_exception_id:
 445     restore_live_registers(sasm, save_fpu_registers);
 446     // Note: the restore live registers includes the jump to LR (patched to R0)
 447     break;
 448   case handle_exception_from_callee_id:
 449     restore_live_registers_without_return(sasm); // must not jump immediatly to handler
 450     restore_sp_for_method_handle(sasm);
 451     __ ret();
 452     break;
 453   default:  ShouldNotReachHere();
 454   }
 455 
 456   DEBUG_ONLY(STOP("generate_handle_exception");)  // Should not reach here
 457 
 458   return oop_maps;
 459 }
 460 
 461 
 462 void Runtime1::generate_unwind_exception(StubAssembler* sasm) {
 463   // FP no longer used to find the frame start
 464   // on entry, remove_frame() has already been called (restoring FP and LR)
 465 
 466   // search the exception handler address of the caller (using the return address)
 467   __ mov(c_rarg0, Rthread);
 468   __ mov(Rexception_pc, LR);
 469   __ mov(c_rarg1, LR);
 470   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1);
 471 
 472   // Exception oop should be still in Rexception_obj and pc in Rexception_pc
 473   // Jump to handler
 474   __ verify_not_null_oop(Rexception_obj);
 475 
 476   // JSR292 extension
 477   restore_sp_for_method_handle(sasm);
 478 
 479   __ jump(R0);
 480 }
 481 
 482 
 483 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
 484   OopMap* oop_map = save_live_registers(sasm);
 485 
 486   // call the runtime patching routine, returns non-zero if nmethod got deopted.
 487   int call_offset = __ call_RT(noreg, noreg, target);
 488   OopMapSet* oop_maps = new OopMapSet();
 489   oop_maps->add_gc_map(call_offset, oop_map);
 490 
 491   DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
 492   assert(deopt_blob != NULL, "deoptimization blob must have been created");
 493 
 494   __ cmp_32(R0, 0);
 495 
 496 #ifdef AARCH64
 497   Label call_deopt;
 498 
 499   restore_live_registers_without_return(sasm);
 500   __ b(call_deopt, ne);
 501   __ ret();
 502 
 503   __ bind(call_deopt);
 504 #else
 505   restore_live_registers_except_FP_LR(sasm);
 506   __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
 507 
 508   // Deoptimization needed
 509   // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back
 510   __ pop(RegisterSet(FP) | RegisterSet(LR));
 511 #endif // AARCH64
 512 
 513   __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
 514 
 515   DEBUG_ONLY(STOP("generate_patching");)  // Should not reach here
 516   return oop_maps;
 517 }
 518 
 519 
 520 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
 521   const bool must_gc_arguments = true;
 522   const bool dont_gc_arguments = false;
 523 
 524   OopMapSet* oop_maps = NULL;
 525   bool save_fpu_registers = HaveVFP;
 526 
 527   switch (id) {
 528     case forward_exception_id:
 529       {
 530         oop_maps = generate_handle_exception(id, sasm);
 531         // does not return on ARM
 532       }
 533       break;
 534 
 535 #if INCLUDE_ALL_GCS
 536     case g1_pre_barrier_slow_id:
 537       {
 538         // Input:
 539         // - pre_val pushed on the stack
 540 
 541         __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
 542 
 543         // save at least the registers that need saving if the runtime is called
 544 #ifdef AARCH64
 545         __ raw_push(R0, R1);
 546         __ raw_push(R2, R3);
 547         const int nb_saved_regs = 4;
 548 #else // AARCH64
 549         const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
 550         const int nb_saved_regs = 6;
 551         assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
 552         __ push(saved_regs);
 553 #endif // AARCH64
 554 
 555         const Register r_pre_val_0  = R0; // must be R0, to be ready for the runtime call
 556         const Register r_index_1    = R1;
 557         const Register r_buffer_2   = R2;
 558 
 559         Address queue_active(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
 560                                                SATBMarkQueue::byte_offset_of_active()));
 561         Address queue_index(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
 562                                               SATBMarkQueue::byte_offset_of_index()));
 563         Address buffer(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
 564                                          SATBMarkQueue::byte_offset_of_buf()));
 565 
 566         Label done;
 567         Label runtime;
 568 
 569         // Is marking still active?
 570         assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
 571         __ ldrb(R1, queue_active);
 572         __ cbz(R1, done);
 573 
 574         __ ldr(r_index_1, queue_index);
 575         __ ldr(r_pre_val_0, Address(SP, nb_saved_regs*wordSize));
 576         __ ldr(r_buffer_2, buffer);
 577 
 578         __ subs(r_index_1, r_index_1, wordSize);
 579         __ b(runtime, lt);
 580 
 581         __ str(r_index_1, queue_index);
 582         __ str(r_pre_val_0, Address(r_buffer_2, r_index_1));
 583 
 584         __ bind(done);
 585 
 586 #ifdef AARCH64
 587         __ raw_pop(R2, R3);
 588         __ raw_pop(R0, R1);
 589 #else // AARCH64
 590         __ pop(saved_regs);
 591 #endif // AARCH64
 592 
 593         __ ret();
 594 
 595         __ bind(runtime);
 596 
 597         save_live_registers(sasm);
 598 
 599         assert(r_pre_val_0 == c_rarg0, "pre_val should be in R0");
 600         __ mov(c_rarg1, Rthread);
 601         __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, c_rarg1);
 602 
 603         restore_live_registers_without_return(sasm);
 604 
 605         __ b(done);
 606       }
 607       break;
 608     case g1_post_barrier_slow_id:
 609       {
 610         // Input:
 611         // - store_addr, pushed on the stack
 612 
 613         __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
 614 
 615         Label done;
 616         Label recheck;
 617         Label runtime;
 618 
 619         Address queue_index(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
 620                                               DirtyCardQueue::byte_offset_of_index()));
 621         Address buffer(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
 622                                          DirtyCardQueue::byte_offset_of_buf()));
 623 
 624         AddressLiteral cardtable(ci_card_table_address_as<address>(), relocInfo::none);
 625 
 626         // save at least the registers that need saving if the runtime is called
 627 #ifdef AARCH64
 628         __ raw_push(R0, R1);
 629         __ raw_push(R2, R3);
 630         const int nb_saved_regs = 4;
 631 #else // AARCH64
 632         const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
 633         const int nb_saved_regs = 6;
 634         assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
 635         __ push(saved_regs);
 636 #endif // AARCH64
 637 
 638         const Register r_card_addr_0 = R0; // must be R0 for the slow case
 639         const Register r_obj_0 = R0;
 640         const Register r_card_base_1 = R1;
 641         const Register r_tmp2 = R2;
 642         const Register r_index_2 = R2;
 643         const Register r_buffer_3 = R3;
 644         const Register tmp1 = Rtemp;
 645 
 646         __ ldr(r_obj_0, Address(SP, nb_saved_regs*wordSize));
 647         // Note: there is a comment in x86 code about not using
 648         // ExternalAddress / lea, due to relocation not working
 649         // properly for that address. Should be OK for arm, where we
 650         // explicitly specify that 'cardtable' has a relocInfo::none
 651         // type.
 652         __ lea(r_card_base_1, cardtable);
 653         __ add(r_card_addr_0, r_card_base_1, AsmOperand(r_obj_0, lsr, CardTable::card_shift));
 654 
 655         // first quick check without barrier
 656         __ ldrb(r_tmp2, Address(r_card_addr_0));
 657 
 658         __ cmp(r_tmp2, (int)G1CardTable::g1_young_card_val());
 659         __ b(recheck, ne);
 660 
 661         __ bind(done);
 662 
 663 #ifdef AARCH64
 664         __ raw_pop(R2, R3);
 665         __ raw_pop(R0, R1);
 666 #else // AARCH64
 667         __ pop(saved_regs);
 668 #endif // AARCH64
 669 
 670         __ ret();
 671 
 672         __ bind(recheck);
 673 
 674         __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1);
 675 
 676         // reload card state after the barrier that ensures the stored oop was visible
 677         __ ldrb(r_tmp2, Address(r_card_addr_0));
 678 
 679         assert(CardTable::dirty_card_val() == 0, "adjust this code");
 680         __ cbz(r_tmp2, done);
 681 
 682         // storing region crossing non-NULL, card is clean.
 683         // dirty card and log.
 684 
 685         assert(0 == (int)CardTable::dirty_card_val(), "adjust this code");
 686         if ((ci_card_table_address_as<intptr_t>() & 0xff) == 0) {
 687           // Card table is aligned so the lowest byte of the table address base is zero.
 688           __ strb(r_card_base_1, Address(r_card_addr_0));
 689         } else {
 690           __ strb(__ zero_register(r_tmp2), Address(r_card_addr_0));
 691         }
 692 
 693         __ ldr(r_index_2, queue_index);
 694         __ ldr(r_buffer_3, buffer);
 695 
 696         __ subs(r_index_2, r_index_2, wordSize);
 697         __ b(runtime, lt); // go to runtime if now negative
 698 
 699         __ str(r_index_2, queue_index);
 700 
 701         __ str(r_card_addr_0, Address(r_buffer_3, r_index_2));
 702 
 703         __ b(done);
 704 
 705         __ bind(runtime);
 706 
 707         save_live_registers(sasm);
 708 
 709         assert(r_card_addr_0 == c_rarg0, "card_addr should be in R0");
 710         __ mov(c_rarg1, Rthread);
 711         __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), c_rarg0, c_rarg1);
 712 
 713         restore_live_registers_without_return(sasm);
 714 
 715         __ b(done);
 716       }
 717       break;
 718 #endif // INCLUDE_ALL_GCS
 719     case new_instance_id:
 720     case fast_new_instance_id:
 721     case fast_new_instance_init_check_id:
 722       {
 723         const Register result = R0;
 724         const Register klass  = R1;
 725 
 726         if (UseTLAB && Universe::heap()->supports_inline_contig_alloc() && id != new_instance_id) {
 727           // We come here when TLAB allocation failed.
 728           // In this case we try to allocate directly from eden.
 729           Label slow_case, slow_case_no_pop;
 730 
 731           // Make sure the class is fully initialized
 732           if (id == fast_new_instance_init_check_id) {
 733             __ ldrb(result, Address(klass, InstanceKlass::init_state_offset()));
 734             __ cmp(result, InstanceKlass::fully_initialized);
 735             __ b(slow_case_no_pop, ne);
 736           }
 737 
 738           // Free some temporary registers
 739           const Register obj_size = R4;
 740           const Register tmp1     = R5;
 741           const Register tmp2     = LR;
 742           const Register obj_end  = Rtemp;
 743 
 744           __ raw_push(R4, R5, LR);
 745 
 746           __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
 747           __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case);        // initializes result and obj_end
 748           __ incr_allocated_bytes(obj_size, tmp2);
 749           __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
 750                                instanceOopDesc::header_size() * HeapWordSize, -1,
 751                                /* is_tlab_allocated */ false);
 752           __ raw_pop_and_ret(R4, R5);
 753 
 754           __ bind(slow_case);
 755           __ raw_pop(R4, R5, LR);
 756 
 757           __ bind(slow_case_no_pop);
 758         }
 759 
 760         OopMap* map = save_live_registers(sasm);
 761         int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
 762         oop_maps = new OopMapSet();
 763         oop_maps->add_gc_map(call_offset, map);
 764 
 765         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 766 
 767         restore_live_registers_except_R0(sasm);
 768       }
 769       break;
 770 
 771     case counter_overflow_id:
 772       {
 773         OopMap* oop_map = save_live_registers(sasm);
 774         __ ldr(R1, Address(SP, arg1_offset));
 775         __ ldr(R2, Address(SP, arg2_offset));
 776         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2);
 777         oop_maps = new OopMapSet();
 778         oop_maps->add_gc_map(call_offset, oop_map);
 779         restore_live_registers(sasm);
 780       }
 781       break;
 782 
 783     case new_type_array_id:
 784     case new_object_array_id:
 785       {
 786         if (id == new_type_array_id) {
 787           __ set_info("new_type_array", dont_gc_arguments);
 788         } else {
 789           __ set_info("new_object_array", dont_gc_arguments);
 790         }
 791 
 792         const Register result = R0;
 793         const Register klass  = R1;
 794         const Register length = R2;
 795 
 796         if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) {
 797           // We come here when TLAB allocation failed.
 798           // In this case we try to allocate directly from eden.
 799           Label slow_case, slow_case_no_pop;
 800 
 801 #ifdef AARCH64
 802           __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length);
 803           __ cmp_32(length, Rtemp);
 804 #else
 805           __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length);
 806 #endif // AARCH64
 807           __ b(slow_case_no_pop, hs);
 808 
 809           // Free some temporary registers
 810           const Register arr_size = R4;
 811           const Register tmp1     = R5;
 812           const Register tmp2     = LR;
 813           const Register tmp3     = Rtemp;
 814           const Register obj_end  = tmp3;
 815 
 816           __ raw_push(R4, R5, LR);
 817 
 818           // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
 819           __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
 820           __ mov(arr_size, MinObjAlignmentInBytesMask);
 821           __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
 822 
 823 #ifdef AARCH64
 824           __ lslv_w(tmp3, length, tmp1);
 825           __ add(arr_size, arr_size, tmp3);
 826 #else
 827           __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
 828 #endif // AARCH64
 829 
 830           __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
 831           __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
 832 
 833           // eden_allocate destroys tmp2, so reload header_size after allocation
 834           // eden_allocate initializes result and obj_end
 835           __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case);
 836           __ incr_allocated_bytes(arr_size, tmp2);
 837           __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) +
 838                                        Klass::_lh_header_size_shift / BitsPerByte));
 839           __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false);
 840           __ raw_pop_and_ret(R4, R5);
 841 
 842           __ bind(slow_case);
 843           __ raw_pop(R4, R5, LR);
 844           __ bind(slow_case_no_pop);
 845         }
 846 
 847         OopMap* map = save_live_registers(sasm);
 848         int call_offset;
 849         if (id == new_type_array_id) {
 850           call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
 851         } else {
 852           call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
 853         }
 854         oop_maps = new OopMapSet();
 855         oop_maps->add_gc_map(call_offset, map);
 856 
 857         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 858 
 859         restore_live_registers_except_R0(sasm);
 860       }
 861       break;
 862 
 863     case new_multi_array_id:
 864       {
 865         __ set_info("new_multi_array", dont_gc_arguments);
 866 
 867         // R0: klass
 868         // R2: rank
 869         // SP: address of 1st dimension
 870         const Register result = R0;
 871         OopMap* map = save_live_registers(sasm);
 872 
 873         __ mov(R1, R0);
 874         __ add(R3, SP, arg1_offset);
 875         int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3);
 876 
 877         oop_maps = new OopMapSet();
 878         oop_maps->add_gc_map(call_offset, map);
 879 
 880         // MacroAssembler::StoreStore useless (included in the runtime exit path)
 881 
 882         restore_live_registers_except_R0(sasm);
 883       }
 884       break;
 885 
 886     case register_finalizer_id:
 887       {
 888         __ set_info("register_finalizer", dont_gc_arguments);
 889 
 890         // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
 891         __ load_klass(Rtemp, R0);
 892         __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
 893 
 894 #ifdef AARCH64
 895         Label L;
 896         __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L);
 897         __ ret();
 898         __ bind(L);
 899 #else
 900         __ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
 901         __ bx(LR, eq);
 902 #endif // AARCH64
 903 
 904         // Call VM
 905         OopMap* map = save_live_registers(sasm);
 906         oop_maps = new OopMapSet();
 907         int call_offset = __ call_RT(noreg, noreg,
 908                                      CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0);
 909         oop_maps->add_gc_map(call_offset, map);
 910         restore_live_registers(sasm);
 911       }
 912       break;
 913 
 914     case throw_range_check_failed_id:
 915       {
 916         __ set_info("range_check_failed", dont_gc_arguments);
 917         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
 918       }
 919       break;
 920 
 921     case throw_index_exception_id:
 922       {
 923         __ set_info("index_range_check_failed", dont_gc_arguments);
 924 #ifdef AARCH64
 925         __ NOT_TESTED();
 926 #endif
 927         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
 928       }
 929       break;
 930 
 931     case throw_div0_exception_id:
 932       {
 933         __ set_info("throw_div0_exception", dont_gc_arguments);
 934         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
 935       }
 936       break;
 937 
 938     case throw_null_pointer_exception_id:
 939       {
 940         __ set_info("throw_null_pointer_exception", dont_gc_arguments);
 941         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
 942       }
 943       break;
 944 
 945     case handle_exception_nofpu_id:
 946     case handle_exception_id:
 947       {
 948         __ set_info("handle_exception", dont_gc_arguments);
 949         oop_maps = generate_handle_exception(id, sasm);
 950       }
 951       break;
 952 
 953     case handle_exception_from_callee_id:
 954       {
 955         __ set_info("handle_exception_from_callee", dont_gc_arguments);
 956         oop_maps = generate_handle_exception(id, sasm);
 957       }
 958       break;
 959 
 960     case unwind_exception_id:
 961       {
 962         __ set_info("unwind_exception", dont_gc_arguments);
 963         generate_unwind_exception(sasm);
 964       }
 965       break;
 966 
 967     case throw_array_store_exception_id:
 968       {
 969         __ set_info("throw_array_store_exception", dont_gc_arguments);
 970         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
 971       }
 972       break;
 973 
 974     case throw_class_cast_exception_id:
 975       {
 976         __ set_info("throw_class_cast_exception", dont_gc_arguments);
 977         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
 978       }
 979       break;
 980 
 981     case throw_incompatible_class_change_error_id:
 982       {
 983         __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
 984 #ifdef AARCH64
 985         __ NOT_TESTED();
 986 #endif
 987         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
 988       }
 989       break;
 990 
 991     case slow_subtype_check_id:
 992       {
 993         // (in)  R0 - sub, destroyed,
 994         // (in)  R1 - super, not changed
 995         // (out) R0 - result: 1 if check passed, 0 otherwise
 996         __ raw_push(R2, R3, LR);
 997 
 998         // Load an array of secondary_supers
 999         __ ldr(R2, Address(R0, Klass::secondary_supers_offset()));
1000         // Length goes to R3
1001         __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes()));
1002         __ add(R2, R2, Array<Klass*>::base_offset_in_bytes());
1003 
1004         Label loop, miss;
1005         __ bind(loop);
1006         __ cbz(R3, miss);
1007         __ ldr(LR, Address(R2, wordSize, post_indexed));
1008         __ sub(R3, R3, 1);
1009         __ cmp(LR, R1);
1010         __ b(loop, ne);
1011 
1012         // We get here if an equal cache entry is found
1013         __ str(R1, Address(R0, Klass::secondary_super_cache_offset()));
1014         __ mov(R0, 1);
1015         __ raw_pop_and_ret(R2, R3);
1016 
1017         // A cache entry not found - return false
1018         __ bind(miss);
1019         __ mov(R0, 0);
1020         __ raw_pop_and_ret(R2, R3);
1021       }
1022       break;
1023 
1024     case monitorenter_nofpu_id:
1025       save_fpu_registers = false;
1026       // fall through
1027     case monitorenter_id:
1028       {
1029         __ set_info("monitorenter", dont_gc_arguments);
1030         const Register obj  = R1;
1031         const Register lock = R2;
1032         OopMap* map = save_live_registers(sasm, save_fpu_registers);
1033         __ ldr(obj, Address(SP, arg1_offset));
1034         __ ldr(lock, Address(SP, arg2_offset));
1035         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock);
1036         oop_maps = new OopMapSet();
1037         oop_maps->add_gc_map(call_offset, map);
1038         restore_live_registers(sasm, save_fpu_registers);
1039       }
1040       break;
1041 
1042     case monitorexit_nofpu_id:
1043       save_fpu_registers = false;
1044       // fall through
1045     case monitorexit_id:
1046       {
1047         __ set_info("monitorexit", dont_gc_arguments);
1048         const Register lock = R1;
1049         OopMap* map = save_live_registers(sasm, save_fpu_registers);
1050         __ ldr(lock, Address(SP, arg1_offset));
1051         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock);
1052         oop_maps = new OopMapSet();
1053         oop_maps->add_gc_map(call_offset, map);
1054         restore_live_registers(sasm, save_fpu_registers);
1055       }
1056       break;
1057 
1058     case deoptimize_id:
1059       {
1060         __ set_info("deoptimize", dont_gc_arguments);
1061         OopMap* oop_map = save_live_registers(sasm);
1062         const Register trap_request = R1;
1063         __ ldr(trap_request, Address(SP, arg1_offset));
1064         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request);
1065         oop_maps = new OopMapSet();
1066         oop_maps->add_gc_map(call_offset, oop_map);
1067         restore_live_registers_without_return(sasm);
1068         DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1069         assert(deopt_blob != NULL, "deoptimization blob must have been created");
1070         __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg));
1071       }
1072       break;
1073 
1074     case access_field_patching_id:
1075       {
1076         __ set_info("access_field_patching", dont_gc_arguments);
1077         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1078       }
1079       break;
1080 
1081     case load_klass_patching_id:
1082       {
1083         __ set_info("load_klass_patching", dont_gc_arguments);
1084         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1085       }
1086       break;
1087 
1088     case load_appendix_patching_id:
1089       {
1090         __ set_info("load_appendix_patching", dont_gc_arguments);
1091         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1092       }
1093       break;
1094 
1095     case load_mirror_patching_id:
1096       {
1097         __ set_info("load_mirror_patching", dont_gc_arguments);
1098         oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1099       }
1100       break;
1101 
1102     case predicate_failed_trap_id:
1103       {
1104         __ set_info("predicate_failed_trap", dont_gc_arguments);
1105 
1106         OopMap* oop_map = save_live_registers(sasm);
1107         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1108 
1109         oop_maps = new OopMapSet();
1110         oop_maps->add_gc_map(call_offset, oop_map);
1111 
1112         restore_live_registers_without_return(sasm);
1113 
1114         DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1115         assert(deopt_blob != NULL, "deoptimization blob must have been created");
1116         __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
1117       }
1118       break;
1119 
1120     default:
1121       {
1122         __ set_info("unimplemented entry", dont_gc_arguments);
1123         STOP("unimplemented entry");
1124       }
1125       break;
1126   }
1127   return oop_maps;
1128 }
1129 
1130 #undef __
1131 
1132 #ifdef __SOFTFP__
1133 const char *Runtime1::pd_name_for_address(address entry) {
1134 
1135 #define FUNCTION_CASE(a, f) \
1136   if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f))  return #f
1137 
1138   FUNCTION_CASE(entry, __aeabi_fadd_glibc);
1139   FUNCTION_CASE(entry, __aeabi_fmul);
1140   FUNCTION_CASE(entry, __aeabi_fsub_glibc);
1141   FUNCTION_CASE(entry, __aeabi_fdiv);
1142 
1143   // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269.
1144   FUNCTION_CASE(entry, __aeabi_dadd_glibc);
1145   FUNCTION_CASE(entry, __aeabi_dmul);
1146   FUNCTION_CASE(entry, __aeabi_dsub_glibc);
1147   FUNCTION_CASE(entry, __aeabi_ddiv);
1148 
1149   FUNCTION_CASE(entry, __aeabi_f2d);
1150   FUNCTION_CASE(entry, __aeabi_d2f);
1151   FUNCTION_CASE(entry, __aeabi_i2f);
1152   FUNCTION_CASE(entry, __aeabi_i2d);
1153   FUNCTION_CASE(entry, __aeabi_f2iz);
1154 
1155   FUNCTION_CASE(entry, SharedRuntime::fcmpl);
1156   FUNCTION_CASE(entry, SharedRuntime::fcmpg);
1157   FUNCTION_CASE(entry, SharedRuntime::dcmpl);
1158   FUNCTION_CASE(entry, SharedRuntime::dcmpg);
1159 
1160   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt);
1161   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt);
1162   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple);
1163   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple);
1164   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge);
1165   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge);
1166   FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt);
1167   FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt);
1168 
1169   FUNCTION_CASE(entry, SharedRuntime::fneg);
1170   FUNCTION_CASE(entry, SharedRuntime::dneg);
1171 
1172   FUNCTION_CASE(entry, __aeabi_fcmpeq);
1173   FUNCTION_CASE(entry, __aeabi_fcmplt);
1174   FUNCTION_CASE(entry, __aeabi_fcmple);
1175   FUNCTION_CASE(entry, __aeabi_fcmpge);
1176   FUNCTION_CASE(entry, __aeabi_fcmpgt);
1177 
1178   FUNCTION_CASE(entry, __aeabi_dcmpeq);
1179   FUNCTION_CASE(entry, __aeabi_dcmplt);
1180   FUNCTION_CASE(entry, __aeabi_dcmple);
1181   FUNCTION_CASE(entry, __aeabi_dcmpge);
1182   FUNCTION_CASE(entry, __aeabi_dcmpgt);
1183 #undef FUNCTION_CASE
1184   return "";
1185 }
1186 #else  // __SOFTFP__
1187 const char *Runtime1::pd_name_for_address(address entry) {
1188   return "<unknown function>";
1189 }
1190 #endif // __SOFTFP__