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src/hotspot/cpu/arm/templateTable_arm.cpp

G1BarrierSet_merge

175 
176 //----------------------------------------------------------------------------------------------------                               
177 // Miscelaneous helper routines                                                                                                      
178 
179 // Store an oop (or NULL) at the address described by obj.                                                                           
180 // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).                                                 
181 // Also destroys new_val and obj.base().                                                                                             
182 static void do_oop_store(InterpreterMacroAssembler* _masm,                                                                           
183                          Address obj,                                                                                                
184                          Register new_val,                                                                                           
185                          Register tmp1,                                                                                              
186                          Register tmp2,                                                                                              
187                          Register tmp3,                                                                                              
188                          BarrierSet::Name barrier,                                                                                   
189                          bool precise,                                                                                               
190                          bool is_null) {                                                                                             
191 
192   assert_different_registers(obj.base(), new_val, tmp1, tmp2, tmp3, noreg);                                                          
193   switch (barrier) {                                                                                                                 
194 #if INCLUDE_ALL_GCS                                                                                                                  
195     case BarrierSet::G1SATBCTLogging:                                                                                                
196       {                                                                                                                              
197         // flatten object address if needed                                                                                          
198         assert (obj.mode() == basic_offset, "pre- or post-indexing is not supported here");                                          
199 
200         const Register store_addr = obj.base();                                                                                      
201         if (obj.index() != noreg) {                                                                                                  
202           assert (obj.disp() == 0, "index or displacement, not both");                                                               
203 #ifdef AARCH64                                                                                                                       
204           __ add(store_addr, obj.base(), obj.index(), obj.extend(), obj.shift_imm());                                                
205 #else                                                                                                                                
206           assert(obj.offset_op() == add_offset, "addition is expected");                                                             
207           __ add(store_addr, obj.base(), AsmOperand(obj.index(), obj.shift(), obj.shift_imm()));                                     
208 #endif // AARCH64                                                                                                                    
209         } else if (obj.disp() != 0) {                                                                                                
210           __ add(store_addr, obj.base(), obj.disp());                                                                                
211         }                                                                                                                            
212 
213         __ g1_write_barrier_pre(store_addr, new_val, tmp1, tmp2, tmp3);                                                              
214         if (is_null) {                                                                                                               

175 
176 //----------------------------------------------------------------------------------------------------
177 // Miscelaneous helper routines
178 
179 // Store an oop (or NULL) at the address described by obj.
180 // Blows all volatile registers (R0-R3 on 32-bit ARM, R0-R18 on AArch64, Rtemp, LR).
181 // Also destroys new_val and obj.base().
182 static void do_oop_store(InterpreterMacroAssembler* _masm,
183                          Address obj,
184                          Register new_val,
185                          Register tmp1,
186                          Register tmp2,
187                          Register tmp3,
188                          BarrierSet::Name barrier,
189                          bool precise,
190                          bool is_null) {
191 
192   assert_different_registers(obj.base(), new_val, tmp1, tmp2, tmp3, noreg);
193   switch (barrier) {
194 #if INCLUDE_ALL_GCS
195     case BarrierSet::G1BarrierSet:
196       {
197         // flatten object address if needed
198         assert (obj.mode() == basic_offset, "pre- or post-indexing is not supported here");
199 
200         const Register store_addr = obj.base();
201         if (obj.index() != noreg) {
202           assert (obj.disp() == 0, "index or displacement, not both");
203 #ifdef AARCH64
204           __ add(store_addr, obj.base(), obj.index(), obj.extend(), obj.shift_imm());
205 #else
206           assert(obj.offset_op() == add_offset, "addition is expected");
207           __ add(store_addr, obj.base(), AsmOperand(obj.index(), obj.shift(), obj.shift_imm()));
208 #endif // AARCH64
209         } else if (obj.disp() != 0) {
210           __ add(store_addr, obj.base(), obj.disp());
211         }
212 
213         __ g1_write_barrier_pre(store_addr, new_val, tmp1, tmp2, tmp3);
214         if (is_null) {
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