1 /*
2 * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "ci/ciUtilities.hpp"
31 #include "gc/shared/cardTable.hpp"
32 #include "gc/shared/cardTableModRefBS.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "nativeInst_x86.hpp"
35 #include "oops/compiledICHolder.hpp"
36 #include "oops/oop.inline.hpp"
37 #include "prims/jvmtiExport.hpp"
38 #include "register_x86.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/signature.hpp"
41 #include "runtime/vframeArray.hpp"
42 #include "utilities/macros.hpp"
43 #include "vmreg_x86.inline.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1BarrierSet.hpp"
46 #include "gc/g1/g1CardTable.hpp"
47 #endif
48
49
50 // Implementation of StubAssembler
51
52 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
53 // setup registers
54 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
55 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
56 assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
57 assert(args_size >= 0, "illegal args_size");
58 bool align_stack = false;
59 #ifdef _LP64
60 // At a method handle call, the stack may not be properly aligned
61 // when returning with an exception.
62 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
63 #endif
64
65 #ifdef _LP64
66 mov(c_rarg0, thread);
67 set_num_rt_args(0); // Nothing on stack
68 #else
69 set_num_rt_args(1 + args_size);
70
71 // push java thread (becomes first argument of C function)
72 get_thread(thread);
73 push(thread);
74 #endif // _LP64
75
76 int call_offset;
77 if (!align_stack) {
78 set_last_Java_frame(thread, noreg, rbp, NULL);
79 } else {
80 address the_pc = pc();
81 call_offset = offset();
82 set_last_Java_frame(thread, noreg, rbp, the_pc);
83 andptr(rsp, -(StackAlignmentInBytes)); // Align stack
84 }
85
86 // do the call
87 call(RuntimeAddress(entry));
88 if (!align_stack) {
89 call_offset = offset();
90 }
91 // verify callee-saved register
92 #ifdef ASSERT
93 guarantee(thread != rax, "change this code");
94 push(rax);
95 { Label L;
96 get_thread(rax);
97 cmpptr(thread, rax);
98 jcc(Assembler::equal, L);
99 int3();
100 stop("StubAssembler::call_RT: rdi not callee saved?");
101 bind(L);
102 }
103 pop(rax);
104 #endif
105 reset_last_Java_frame(thread, true);
106
107 // discard thread and arguments
108 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
109
110 // check for pending exceptions
111 { Label L;
112 cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
113 jcc(Assembler::equal, L);
114 // exception pending => remove activation and forward to exception handler
115 movptr(rax, Address(thread, Thread::pending_exception_offset()));
116 // make sure that the vm_results are cleared
117 if (oop_result1->is_valid()) {
118 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
119 }
120 if (metadata_result->is_valid()) {
121 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
122 }
123 if (frame_size() == no_frame_size) {
124 leave();
125 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
126 } else if (_stub_id == Runtime1::forward_exception_id) {
127 should_not_reach_here();
128 } else {
129 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
130 }
131 bind(L);
132 }
133 // get oop results if there are any and reset the values in the thread
134 if (oop_result1->is_valid()) {
135 get_vm_result(oop_result1, thread);
136 }
137 if (metadata_result->is_valid()) {
138 get_vm_result_2(metadata_result, thread);
139 }
140 return call_offset;
141 }
142
143
144 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
145 #ifdef _LP64
146 mov(c_rarg1, arg1);
147 #else
148 push(arg1);
149 #endif // _LP64
150 return call_RT(oop_result1, metadata_result, entry, 1);
151 }
152
153
154 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
155 #ifdef _LP64
156 if (c_rarg1 == arg2) {
157 if (c_rarg2 == arg1) {
158 xchgq(arg1, arg2);
159 } else {
160 mov(c_rarg2, arg2);
161 mov(c_rarg1, arg1);
162 }
163 } else {
164 mov(c_rarg1, arg1);
165 mov(c_rarg2, arg2);
166 }
167 #else
168 push(arg2);
169 push(arg1);
170 #endif // _LP64
171 return call_RT(oop_result1, metadata_result, entry, 2);
172 }
173
174
175 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
176 #ifdef _LP64
177 // if there is any conflict use the stack
178 if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
179 arg2 == c_rarg1 || arg1 == c_rarg3 ||
180 arg3 == c_rarg1 || arg1 == c_rarg2) {
181 push(arg3);
182 push(arg2);
183 push(arg1);
184 pop(c_rarg1);
185 pop(c_rarg2);
186 pop(c_rarg3);
187 } else {
188 mov(c_rarg1, arg1);
189 mov(c_rarg2, arg2);
190 mov(c_rarg3, arg3);
191 }
192 #else
193 push(arg3);
194 push(arg2);
195 push(arg1);
196 #endif // _LP64
197 return call_RT(oop_result1, metadata_result, entry, 3);
198 }
199
200
201 // Implementation of StubFrame
202
203 class StubFrame: public StackObj {
204 private:
205 StubAssembler* _sasm;
206
207 public:
208 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
209 void load_argument(int offset_in_words, Register reg);
210
211 ~StubFrame();
212 };
213
214
215 #define __ _sasm->
216
217 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
218 _sasm = sasm;
219 __ set_info(name, must_gc_arguments);
220 __ enter();
221 }
222
223 // load parameters that were stored with LIR_Assembler::store_parameter
224 // Note: offsets for store_parameter and load_argument must match
225 void StubFrame::load_argument(int offset_in_words, Register reg) {
226 // rbp, + 0: link
227 // + 1: return address
228 // + 2: argument with offset 0
229 // + 3: argument with offset 1
230 // + 4: ...
231
232 __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
233 }
234
235
236 StubFrame::~StubFrame() {
237 __ leave();
238 __ ret(0);
239 }
240
241 #undef __
242
243
244 // Implementation of Runtime1
245
246 #define __ sasm->
247
248 const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
249 const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
250
251 // Stack layout for saving/restoring all the registers needed during a runtime
252 // call (this includes deoptimization)
253 // Note: note that users of this frame may well have arguments to some runtime
254 // while these values are on the stack. These positions neglect those arguments
255 // but the code in save_live_registers will take the argument count into
256 // account.
257 //
258 #ifdef _LP64
259 #define SLOT2(x) x,
260 #define SLOT_PER_WORD 2
261 #else
262 #define SLOT2(x)
263 #define SLOT_PER_WORD 1
264 #endif // _LP64
265
266 enum reg_save_layout {
267 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
268 // happen and will assert if the stack size we create is misaligned
269 #ifdef _LP64
270 align_dummy_0, align_dummy_1,
271 #endif // _LP64
272 #ifdef _WIN64
273 // Windows always allocates space for it's argument registers (see
274 // frame::arg_reg_save_area_bytes).
275 arg_reg_save_1, arg_reg_save_1H, // 0, 4
276 arg_reg_save_2, arg_reg_save_2H, // 8, 12
277 arg_reg_save_3, arg_reg_save_3H, // 16, 20
278 arg_reg_save_4, arg_reg_save_4H, // 24, 28
279 #endif // _WIN64
280 xmm_regs_as_doubles_off, // 32
281 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
282 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
283 // fpu_state_end_off is exclusive
284 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
285 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
286 extra_space_offset, // 360
287 #ifdef _LP64
288 r15_off = extra_space_offset, r15H_off, // 360, 364
289 r14_off, r14H_off, // 368, 372
290 r13_off, r13H_off, // 376, 380
291 r12_off, r12H_off, // 384, 388
292 r11_off, r11H_off, // 392, 396
293 r10_off, r10H_off, // 400, 404
294 r9_off, r9H_off, // 408, 412
295 r8_off, r8H_off, // 416, 420
296 rdi_off, rdiH_off, // 424, 428
297 #else
298 rdi_off = extra_space_offset,
299 #endif // _LP64
300 rsi_off, SLOT2(rsiH_off) // 432, 436
301 rbp_off, SLOT2(rbpH_off) // 440, 444
302 rsp_off, SLOT2(rspH_off) // 448, 452
303 rbx_off, SLOT2(rbxH_off) // 456, 460
304 rdx_off, SLOT2(rdxH_off) // 464, 468
305 rcx_off, SLOT2(rcxH_off) // 472, 476
306 rax_off, SLOT2(raxH_off) // 480, 484
307 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
308 return_off, SLOT2(returnH_off) // 496, 500
309 reg_save_frame_size // As noted: neglects any parameters to runtime // 504
310 };
311
312
313
314 // Save off registers which might be killed by calls into the runtime.
315 // Tries to smart of about FP registers. In particular we separate
316 // saving and describing the FPU registers for deoptimization since we
317 // have to save the FPU registers twice if we describe them and on P4
318 // saving FPU registers which don't contain anything appears
319 // expensive. The deopt blob is the only thing which needs to
320 // describe FPU registers. In all other cases it should be sufficient
321 // to simply save their current value.
322
323 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
324 bool save_fpu_registers = true) {
325
326 // In 64bit all the args are in regs so there are no additional stack slots
327 LP64_ONLY(num_rt_args = 0);
328 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
329 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
330 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word);
331
332 // record saved value locations in an OopMap
333 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
334 OopMap* map = new OopMap(frame_size_in_slots, 0);
335 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
336 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
337 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
338 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
339 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
340 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
341 #ifdef _LP64
342 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
343 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
344 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
345 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
346 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
347 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
348 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
349 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
350
351 // This is stupid but needed.
352 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
353 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
354 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
355 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
356 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
357 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
358
359 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
360 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
361 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
362 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
363 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
364 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
365 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
366 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
367 #endif // _LP64
368
369 int xmm_bypass_limit = FrameMap::nof_xmm_regs;
370 #ifdef _LP64
371 if (UseAVX < 3) {
372 xmm_bypass_limit = xmm_bypass_limit / 2;
373 }
374 #endif
375
376 if (save_fpu_registers) {
377 if (UseSSE < 2) {
378 int fpu_off = float_regs_as_doubles_off;
379 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
380 VMReg fpu_name_0 = FrameMap::fpu_regname(n);
381 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0);
382 // %%% This is really a waste but we'll keep things as they were for now
383 if (true) {
384 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());
385 }
386 fpu_off += 2;
387 }
388 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");
389 }
390
391 if (UseSSE >= 2) {
392 int xmm_off = xmm_regs_as_doubles_off;
393 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
394 if (n < xmm_bypass_limit) {
395 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
396 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
397 // %%% This is really a waste but we'll keep things as they were for now
398 if (true) {
399 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
400 }
401 }
402 xmm_off += 2;
403 }
404 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
405
406 } else if (UseSSE == 1) {
407 int xmm_off = xmm_regs_as_doubles_off;
408 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
409 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
410 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
411 xmm_off += 2;
412 }
413 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
414 }
415 }
416
417 return map;
418 }
419
420 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
421 bool save_fpu_registers = true) {
422 __ block_comment("save_live_registers");
423
424 __ pusha(); // integer registers
425
426 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
427 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
428
429 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
430
431 #ifdef ASSERT
432 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
433 #endif
434
435 if (save_fpu_registers) {
436 if (UseSSE < 2) {
437 // save FPU stack
438 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
439 __ fwait();
440
441 #ifdef ASSERT
442 Label ok;
443 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
444 __ jccb(Assembler::equal, ok);
445 __ stop("corrupted control word detected");
446 __ bind(ok);
447 #endif
448
449 // Reset the control word to guard against exceptions being unmasked
450 // since fstp_d can cause FPU stack underflow exceptions. Write it
451 // into the on stack copy and then reload that to make sure that the
452 // current and future values are correct.
453 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
454 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
455
456 // Save the FPU registers in de-opt-able form
457 int offset = 0;
458 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
459 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
460 offset += 8;
461 }
462 }
463
464 if (UseSSE >= 2) {
465 // save XMM registers
466 // XMM registers can contain float or double values, but this is not known here,
467 // so always save them as doubles.
468 // note that float values are _not_ converted automatically, so for float values
469 // the second word contains only garbage data.
470 int xmm_bypass_limit = FrameMap::nof_xmm_regs;
471 int offset = 0;
472 #ifdef _LP64
473 if (UseAVX < 3) {
474 xmm_bypass_limit = xmm_bypass_limit / 2;
475 }
476 #endif
477 for (int n = 0; n < xmm_bypass_limit; n++) {
478 XMMRegister xmm_name = as_XMMRegister(n);
479 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
480 offset += 8;
481 }
482 } else if (UseSSE == 1) {
483 // save XMM registers as float because double not supported without SSE2(num MMX == num fpu)
484 int offset = 0;
485 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
486 XMMRegister xmm_name = as_XMMRegister(n);
487 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name);
488 offset += 8;
489 }
490 }
491 }
492
493 // FPU stack must be empty now
494 __ verify_FPU(0, "save_live_registers");
495
496 return generate_oop_map(sasm, num_rt_args, save_fpu_registers);
497 }
498
499
500 static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {
501 if (restore_fpu_registers) {
502 if (UseSSE >= 2) {
503 // restore XMM registers
504 int xmm_bypass_limit = FrameMap::nof_xmm_regs;
505 #ifdef _LP64
506 if (UseAVX < 3) {
507 xmm_bypass_limit = xmm_bypass_limit / 2;
508 }
509 #endif
510 int offset = 0;
511 for (int n = 0; n < xmm_bypass_limit; n++) {
512 XMMRegister xmm_name = as_XMMRegister(n);
513 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
514 offset += 8;
515 }
516 } else if (UseSSE == 1) {
517 // restore XMM registers(num MMX == num fpu)
518 int offset = 0;
519 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
520 XMMRegister xmm_name = as_XMMRegister(n);
521 __ movflt(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset));
522 offset += 8;
523 }
524 }
525
526 if (UseSSE < 2) {
527 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
528 } else {
529 // check that FPU stack is really empty
530 __ verify_FPU(0, "restore_live_registers");
531 }
532
533 } else {
534 // check that FPU stack is really empty
535 __ verify_FPU(0, "restore_live_registers");
536 }
537
538 #ifdef ASSERT
539 {
540 Label ok;
541 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
542 __ jcc(Assembler::equal, ok);
543 __ stop("bad offsets in frame");
544 __ bind(ok);
545 }
546 #endif // ASSERT
547
548 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
549 }
550
551
552 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
553 __ block_comment("restore_live_registers");
554
555 restore_fpu(sasm, restore_fpu_registers);
556 __ popa();
557 }
558
559
560 static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) {
561 __ block_comment("restore_live_registers_except_rax");
562
563 restore_fpu(sasm, restore_fpu_registers);
564
565 #ifdef _LP64
566 __ movptr(r15, Address(rsp, 0));
567 __ movptr(r14, Address(rsp, wordSize));
568 __ movptr(r13, Address(rsp, 2 * wordSize));
569 __ movptr(r12, Address(rsp, 3 * wordSize));
570 __ movptr(r11, Address(rsp, 4 * wordSize));
571 __ movptr(r10, Address(rsp, 5 * wordSize));
572 __ movptr(r9, Address(rsp, 6 * wordSize));
573 __ movptr(r8, Address(rsp, 7 * wordSize));
574 __ movptr(rdi, Address(rsp, 8 * wordSize));
575 __ movptr(rsi, Address(rsp, 9 * wordSize));
576 __ movptr(rbp, Address(rsp, 10 * wordSize));
577 // skip rsp
578 __ movptr(rbx, Address(rsp, 12 * wordSize));
579 __ movptr(rdx, Address(rsp, 13 * wordSize));
580 __ movptr(rcx, Address(rsp, 14 * wordSize));
581
582 __ addptr(rsp, 16 * wordSize);
583 #else
584
585 __ pop(rdi);
586 __ pop(rsi);
587 __ pop(rbp);
588 __ pop(rbx); // skip this value
589 __ pop(rbx);
590 __ pop(rdx);
591 __ pop(rcx);
592 __ addptr(rsp, BytesPerWord);
593 #endif // _LP64
594 }
595
596
597 void Runtime1::initialize_pd() {
598 // nothing to do
599 }
600
601
602 // target: the entry point of the method that creates and posts the exception oop
603 // has_argument: true if the exception needs an argument (passed on stack because registers must be preserved)
604
605 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
606 // preserve all registers
607 int num_rt_args = has_argument ? 2 : 1;
608 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
609
610 // now all registers are saved and can be used freely
611 // verify that no old value is used accidentally
612 __ invalidate_registers(true, true, true, true, true, true);
613
614 // registers used by this stub
615 const Register temp_reg = rbx;
616
617 // load argument for exception that is passed as an argument into the stub
618 if (has_argument) {
619 #ifdef _LP64
620 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
621 #else
622 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
623 __ push(temp_reg);
624 #endif // _LP64
625 }
626 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
627
628 OopMapSet* oop_maps = new OopMapSet();
629 oop_maps->add_gc_map(call_offset, oop_map);
630
631 __ stop("should not reach here");
632
633 return oop_maps;
634 }
635
636
637 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
638 __ block_comment("generate_handle_exception");
639
640 // incoming parameters
641 const Register exception_oop = rax;
642 const Register exception_pc = rdx;
643 // other registers used in this stub
644 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
645
646 // Save registers, if required.
647 OopMapSet* oop_maps = new OopMapSet();
648 OopMap* oop_map = NULL;
649 switch (id) {
650 case forward_exception_id:
651 // We're handling an exception in the context of a compiled frame.
652 // The registers have been saved in the standard places. Perform
653 // an exception lookup in the caller and dispatch to the handler
654 // if found. Otherwise unwind and dispatch to the callers
655 // exception handler.
656 oop_map = generate_oop_map(sasm, 1 /*thread*/);
657
658 // load and clear pending exception oop into RAX
659 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
660 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
661
662 // load issuing PC (the return address for this stub) into rdx
663 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
664
665 // make sure that the vm_results are cleared (may be unnecessary)
666 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
667 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
668 break;
669 case handle_exception_nofpu_id:
670 case handle_exception_id:
671 // At this point all registers MAY be live.
672 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
673 break;
674 case handle_exception_from_callee_id: {
675 // At this point all registers except exception oop (RAX) and
676 // exception pc (RDX) are dead.
677 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord);
678 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
679 sasm->set_frame_size(frame_size);
680 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes));
681 break;
682 }
683 default: ShouldNotReachHere();
684 }
685
686 #ifdef TIERED
687 // C2 can leave the fpu stack dirty
688 if (UseSSE < 2) {
689 __ empty_FPU_stack();
690 }
691 #endif // TIERED
692
693 // verify that only rax, and rdx is valid at this time
694 __ invalidate_registers(false, true, true, false, true, true);
695 // verify that rax, contains a valid exception
696 __ verify_not_null_oop(exception_oop);
697
698 // load address of JavaThread object for thread-local data
699 NOT_LP64(__ get_thread(thread);)
700
701 #ifdef ASSERT
702 // check that fields in JavaThread for exception oop and issuing pc are
703 // empty before writing to them
704 Label oop_empty;
705 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
706 __ jcc(Assembler::equal, oop_empty);
707 __ stop("exception oop already set");
708 __ bind(oop_empty);
709
710 Label pc_empty;
711 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
712 __ jcc(Assembler::equal, pc_empty);
713 __ stop("exception pc already set");
714 __ bind(pc_empty);
715 #endif
716
717 // save exception oop and issuing pc into JavaThread
718 // (exception handler will load it from here)
719 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
720 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
721
722 // patch throwing pc into return address (has bci & oop map)
723 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
724
725 // compute the exception handler.
726 // the exception oop and the throwing pc are read from the fields in JavaThread
727 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
728 oop_maps->add_gc_map(call_offset, oop_map);
729
730 // rax: handler address
731 // will be the deopt blob if nmethod was deoptimized while we looked up
732 // handler regardless of whether handler existed in the nmethod.
733
734 // only rax, is valid at this time, all other registers have been destroyed by the runtime call
735 __ invalidate_registers(false, true, true, true, true, true);
736
737 // patch the return address, this stub will directly return to the exception handler
738 __ movptr(Address(rbp, 1*BytesPerWord), rax);
739
740 switch (id) {
741 case forward_exception_id:
742 case handle_exception_nofpu_id:
743 case handle_exception_id:
744 // Restore the registers that were saved at the beginning.
745 restore_live_registers(sasm, id != handle_exception_nofpu_id);
746 break;
747 case handle_exception_from_callee_id:
748 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
749 // since we do a leave anyway.
750
751 // Pop the return address.
752 __ leave();
753 __ pop(rcx);
754 __ jmp(rcx); // jump to exception handler
755 break;
756 default: ShouldNotReachHere();
757 }
758
759 return oop_maps;
760 }
761
762
763 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
764 // incoming parameters
765 const Register exception_oop = rax;
766 // callee-saved copy of exception_oop during runtime call
767 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14);
768 // other registers used in this stub
769 const Register exception_pc = rdx;
770 const Register handler_addr = rbx;
771 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
772
773 // verify that only rax, is valid at this time
774 __ invalidate_registers(false, true, true, true, true, true);
775
776 #ifdef ASSERT
777 // check that fields in JavaThread for exception oop and issuing pc are empty
778 NOT_LP64(__ get_thread(thread);)
779 Label oop_empty;
780 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
781 __ jcc(Assembler::equal, oop_empty);
782 __ stop("exception oop must be empty");
783 __ bind(oop_empty);
784
785 Label pc_empty;
786 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
787 __ jcc(Assembler::equal, pc_empty);
788 __ stop("exception pc must be empty");
789 __ bind(pc_empty);
790 #endif
791
792 // clear the FPU stack in case any FPU results are left behind
793 __ empty_FPU_stack();
794
795 // save exception_oop in callee-saved register to preserve it during runtime calls
796 __ verify_not_null_oop(exception_oop);
797 __ movptr(exception_oop_callee_saved, exception_oop);
798
799 NOT_LP64(__ get_thread(thread);)
800 // Get return address (is on top of stack after leave).
801 __ movptr(exception_pc, Address(rsp, 0));
802
803 // search the exception handler address of the caller (using the return address)
804 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
805 // rax: exception handler address of the caller
806
807 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call.
808 __ invalidate_registers(false, true, true, true, false, true);
809
810 // move result of call into correct register
811 __ movptr(handler_addr, rax);
812
813 // Restore exception oop to RAX (required convention of exception handler).
814 __ movptr(exception_oop, exception_oop_callee_saved);
815
816 // verify that there is really a valid exception in rax
817 __ verify_not_null_oop(exception_oop);
818
819 // get throwing pc (= return address).
820 // rdx has been destroyed by the call, so it must be set again
821 // the pop is also necessary to simulate the effect of a ret(0)
822 __ pop(exception_pc);
823
824 // continue at exception handler (return address removed)
825 // note: do *not* remove arguments when unwinding the
826 // activation since the caller assumes having
827 // all arguments on the stack when entering the
828 // runtime to determine the exception handler
829 // (GC happens at call site with arguments!)
830 // rax: exception oop
831 // rdx: throwing pc
832 // rbx: exception handler
833 __ jmp(handler_addr);
834 }
835
836
837 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
838 // use the maximum number of runtime-arguments here because it is difficult to
839 // distinguish each RT-Call.
840 // Note: This number affects also the RT-Call in generate_handle_exception because
841 // the oop-map is shared for all calls.
842 const int num_rt_args = 2; // thread + dummy
843
844 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
845 assert(deopt_blob != NULL, "deoptimization blob must have been created");
846
847 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
848
849 #ifdef _LP64
850 const Register thread = r15_thread;
851 // No need to worry about dummy
852 __ mov(c_rarg0, thread);
853 #else
854 __ push(rax); // push dummy
855
856 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
857 // push java thread (becomes first argument of C function)
858 __ get_thread(thread);
859 __ push(thread);
860 #endif // _LP64
861 __ set_last_Java_frame(thread, noreg, rbp, NULL);
862 // do the call
863 __ call(RuntimeAddress(target));
864 OopMapSet* oop_maps = new OopMapSet();
865 oop_maps->add_gc_map(__ offset(), oop_map);
866 // verify callee-saved register
867 #ifdef ASSERT
868 guarantee(thread != rax, "change this code");
869 __ push(rax);
870 { Label L;
871 __ get_thread(rax);
872 __ cmpptr(thread, rax);
873 __ jcc(Assembler::equal, L);
874 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
875 __ bind(L);
876 }
877 __ pop(rax);
878 #endif
879 __ reset_last_Java_frame(thread, true);
880 #ifndef _LP64
881 __ pop(rcx); // discard thread arg
882 __ pop(rcx); // discard dummy
883 #endif // _LP64
884
885 // check for pending exceptions
886 { Label L;
887 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
888 __ jcc(Assembler::equal, L);
889 // exception pending => remove activation and forward to exception handler
890
891 __ testptr(rax, rax); // have we deoptimized?
892 __ jump_cc(Assembler::equal,
893 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
894
895 // the deopt blob expects exceptions in the special fields of
896 // JavaThread, so copy and clear pending exception.
897
898 // load and clear pending exception
899 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
900 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
901
902 // check that there is really a valid exception
903 __ verify_not_null_oop(rax);
904
905 // load throwing pc: this is the return address of the stub
906 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
907
908 #ifdef ASSERT
909 // check that fields in JavaThread for exception oop and issuing pc are empty
910 Label oop_empty;
911 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
912 __ jcc(Assembler::equal, oop_empty);
913 __ stop("exception oop must be empty");
914 __ bind(oop_empty);
915
916 Label pc_empty;
917 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
918 __ jcc(Assembler::equal, pc_empty);
919 __ stop("exception pc must be empty");
920 __ bind(pc_empty);
921 #endif
922
923 // store exception oop and throwing pc to JavaThread
924 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
925 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
926
927 restore_live_registers(sasm);
928
929 __ leave();
930 __ addptr(rsp, BytesPerWord); // remove return address from stack
931
932 // Forward the exception directly to deopt blob. We can blow no
933 // registers and must leave throwing pc on the stack. A patch may
934 // have values live in registers so the entry point with the
935 // exception in tls.
936 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls()));
937
938 __ bind(L);
939 }
940
941
942 // Runtime will return true if the nmethod has been deoptimized during
943 // the patching process. In that case we must do a deopt reexecute instead.
944
945 Label reexecuteEntry, cont;
946
947 __ testptr(rax, rax); // have we deoptimized?
948 __ jcc(Assembler::equal, cont); // no
949
950 // Will reexecute. Proper return address is already on the stack we just restore
951 // registers, pop all of our frame but the return address and jump to the deopt blob
952 restore_live_registers(sasm);
953 __ leave();
954 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
955
956 __ bind(cont);
957 restore_live_registers(sasm);
958 __ leave();
959 __ ret(0);
960
961 return oop_maps;
962 }
963
964
965 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
966
967 // for better readability
968 const bool must_gc_arguments = true;
969 const bool dont_gc_arguments = false;
970
971 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu
972 bool save_fpu_registers = true;
973
974 // stub code & info for the different stubs
975 OopMapSet* oop_maps = NULL;
976 switch (id) {
977 case forward_exception_id:
978 {
979 oop_maps = generate_handle_exception(id, sasm);
980 __ leave();
981 __ ret(0);
982 }
983 break;
984
985 case new_instance_id:
986 case fast_new_instance_id:
987 case fast_new_instance_init_check_id:
988 {
989 Register klass = rdx; // Incoming
990 Register obj = rax; // Result
991
992 if (id == new_instance_id) {
993 __ set_info("new_instance", dont_gc_arguments);
994 } else if (id == fast_new_instance_id) {
995 __ set_info("fast new_instance", dont_gc_arguments);
996 } else {
997 assert(id == fast_new_instance_init_check_id, "bad StubID");
998 __ set_info("fast new_instance init check", dont_gc_arguments);
999 }
1000
1001 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) && UseTLAB
1002 && Universe::heap()->supports_inline_contig_alloc()) {
1003 Label slow_path;
1004 Register obj_size = rcx;
1005 Register t1 = rbx;
1006 Register t2 = rsi;
1007 assert_different_registers(klass, obj, obj_size, t1, t2);
1008
1009 __ push(rdi);
1010 __ push(rbx);
1011
1012 if (id == fast_new_instance_init_check_id) {
1013 // make sure the klass is initialized
1014 __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
1015 __ jcc(Assembler::notEqual, slow_path);
1016 }
1017
1018 #ifdef ASSERT
1019 // assert object can be fast path allocated
1020 {
1021 Label ok, not_ok;
1022 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1023 __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0)
1024 __ jcc(Assembler::lessEqual, not_ok);
1025 __ testl(obj_size, Klass::_lh_instance_slow_path_bit);
1026 __ jcc(Assembler::zero, ok);
1027 __ bind(not_ok);
1028 __ stop("assert(can be fast path allocated)");
1029 __ should_not_reach_here();
1030 __ bind(ok);
1031 }
1032 #endif // ASSERT
1033
1034 // if we got here then the TLAB allocation failed, so try
1035 // refilling the TLAB or allocating directly from eden.
1036 Label retry_tlab, try_eden;
1037 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
1038 NOT_LP64(__ get_thread(thread));
1039
1040 __ bind(try_eden);
1041 // get the instance size (size is postive so movl is fine for 64bit)
1042 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1043
1044 __ eden_allocate(obj, obj_size, 0, t1, slow_path);
1045 __ incr_allocated_bytes(thread, obj_size, 0);
1046
1047 __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ false);
1048 __ verify_oop(obj);
1049 __ pop(rbx);
1050 __ pop(rdi);
1051 __ ret(0);
1052
1053 __ bind(slow_path);
1054 __ pop(rbx);
1055 __ pop(rdi);
1056 }
1057
1058 __ enter();
1059 OopMap* map = save_live_registers(sasm, 2);
1060 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
1061 oop_maps = new OopMapSet();
1062 oop_maps->add_gc_map(call_offset, map);
1063 restore_live_registers_except_rax(sasm);
1064 __ verify_oop(obj);
1065 __ leave();
1066 __ ret(0);
1067
1068 // rax,: new instance
1069 }
1070
1071 break;
1072
1073 case counter_overflow_id:
1074 {
1075 Register bci = rax, method = rbx;
1076 __ enter();
1077 OopMap* map = save_live_registers(sasm, 3);
1078 // Retrieve bci
1079 __ movl(bci, Address(rbp, 2*BytesPerWord));
1080 // And a pointer to the Method*
1081 __ movptr(method, Address(rbp, 3*BytesPerWord));
1082 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1083 oop_maps = new OopMapSet();
1084 oop_maps->add_gc_map(call_offset, map);
1085 restore_live_registers(sasm);
1086 __ leave();
1087 __ ret(0);
1088 }
1089 break;
1090
1091 case new_type_array_id:
1092 case new_object_array_id:
1093 {
1094 Register length = rbx; // Incoming
1095 Register klass = rdx; // Incoming
1096 Register obj = rax; // Result
1097
1098 if (id == new_type_array_id) {
1099 __ set_info("new_type_array", dont_gc_arguments);
1100 } else {
1101 __ set_info("new_object_array", dont_gc_arguments);
1102 }
1103
1104 #ifdef ASSERT
1105 // assert object type is really an array of the proper kind
1106 {
1107 Label ok;
1108 Register t0 = obj;
1109 __ movl(t0, Address(klass, Klass::layout_helper_offset()));
1110 __ sarl(t0, Klass::_lh_array_tag_shift);
1111 int tag = ((id == new_type_array_id)
1112 ? Klass::_lh_array_tag_type_value
1113 : Klass::_lh_array_tag_obj_value);
1114 __ cmpl(t0, tag);
1115 __ jcc(Assembler::equal, ok);
1116 __ stop("assert(is an array klass)");
1117 __ should_not_reach_here();
1118 __ bind(ok);
1119 }
1120 #endif // ASSERT
1121
1122 // If we got here, the TLAB allocation failed, so try allocating from
1123 // eden if inline contiguous allocations are supported.
1124 if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) {
1125 Register arr_size = rsi;
1126 Register t1 = rcx; // must be rcx for use as shift count
1127 Register t2 = rdi;
1128 Label slow_path;
1129
1130 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1131 // since size is positive movl does right thing on 64bit
1132 __ movl(t1, Address(klass, Klass::layout_helper_offset()));
1133 // since size is postive movl does right thing on 64bit
1134 __ movl(arr_size, length);
1135 assert(t1 == rcx, "fixed register usage");
1136 __ shlptr(arr_size /* by t1=rcx, mod 32 */);
1137 __ shrptr(t1, Klass::_lh_header_size_shift);
1138 __ andptr(t1, Klass::_lh_header_size_mask);
1139 __ addptr(arr_size, t1);
1140 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
1141 __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
1142
1143 __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size
1144
1145 // Using t2 for non 64-bit.
1146 const Register thread = NOT_LP64(t2) LP64_ONLY(r15_thread);
1147 NOT_LP64(__ get_thread(thread));
1148 __ incr_allocated_bytes(thread, arr_size, 0);
1149
1150 __ initialize_header(obj, klass, length, t1, t2);
1151 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
1152 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1153 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1154 __ andptr(t1, Klass::_lh_header_size_mask);
1155 __ subptr(arr_size, t1); // body length
1156 __ addptr(t1, obj); // body start
1157 __ initialize_body(t1, arr_size, 0, t2);
1158 __ verify_oop(obj);
1159 __ ret(0);
1160
1161 __ bind(slow_path);
1162 }
1163
1164 __ enter();
1165 OopMap* map = save_live_registers(sasm, 3);
1166 int call_offset;
1167 if (id == new_type_array_id) {
1168 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
1169 } else {
1170 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
1171 }
1172
1173 oop_maps = new OopMapSet();
1174 oop_maps->add_gc_map(call_offset, map);
1175 restore_live_registers_except_rax(sasm);
1176
1177 __ verify_oop(obj);
1178 __ leave();
1179 __ ret(0);
1180
1181 // rax,: new array
1182 }
1183 break;
1184
1185 case new_multi_array_id:
1186 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
1187 // rax,: klass
1188 // rbx,: rank
1189 // rcx: address of 1st dimension
1190 OopMap* map = save_live_registers(sasm, 4);
1191 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx);
1192
1193 oop_maps = new OopMapSet();
1194 oop_maps->add_gc_map(call_offset, map);
1195 restore_live_registers_except_rax(sasm);
1196
1197 // rax,: new multi array
1198 __ verify_oop(rax);
1199 }
1200 break;
1201
1202 case register_finalizer_id:
1203 {
1204 __ set_info("register_finalizer", dont_gc_arguments);
1205
1206 // This is called via call_runtime so the arguments
1207 // will be place in C abi locations
1208
1209 #ifdef _LP64
1210 __ verify_oop(c_rarg0);
1211 __ mov(rax, c_rarg0);
1212 #else
1213 // The object is passed on the stack and we haven't pushed a
1214 // frame yet so it's one work away from top of stack.
1215 __ movptr(rax, Address(rsp, 1 * BytesPerWord));
1216 __ verify_oop(rax);
1217 #endif // _LP64
1218
1219 // load the klass and check the has finalizer flag
1220 Label register_finalizer;
1221 Register t = rsi;
1222 __ load_klass(t, rax);
1223 __ movl(t, Address(t, Klass::access_flags_offset()));
1224 __ testl(t, JVM_ACC_HAS_FINALIZER);
1225 __ jcc(Assembler::notZero, register_finalizer);
1226 __ ret(0);
1227
1228 __ bind(register_finalizer);
1229 __ enter();
1230 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */);
1231 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax);
1232 oop_maps = new OopMapSet();
1233 oop_maps->add_gc_map(call_offset, oop_map);
1234
1235 // Now restore all the live registers
1236 restore_live_registers(sasm);
1237
1238 __ leave();
1239 __ ret(0);
1240 }
1241 break;
1242
1243 case throw_range_check_failed_id:
1244 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
1245 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
1246 }
1247 break;
1248
1249 case throw_index_exception_id:
1250 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
1251 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
1252 }
1253 break;
1254
1255 case throw_div0_exception_id:
1256 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
1257 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
1258 }
1259 break;
1260
1261 case throw_null_pointer_exception_id:
1262 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
1263 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
1264 }
1265 break;
1266
1267 case handle_exception_nofpu_id:
1268 case handle_exception_id:
1269 { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
1270 oop_maps = generate_handle_exception(id, sasm);
1271 }
1272 break;
1273
1274 case handle_exception_from_callee_id:
1275 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
1276 oop_maps = generate_handle_exception(id, sasm);
1277 }
1278 break;
1279
1280 case unwind_exception_id:
1281 { __ set_info("unwind_exception", dont_gc_arguments);
1282 // note: no stubframe since we are about to leave the current
1283 // activation and we are calling a leaf VM function only.
1284 generate_unwind_exception(sasm);
1285 }
1286 break;
1287
1288 case throw_array_store_exception_id:
1289 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
1290 // tos + 0: link
1291 // + 1: return address
1292 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1293 }
1294 break;
1295
1296 case throw_class_cast_exception_id:
1297 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
1298 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1299 }
1300 break;
1301
1302 case throw_incompatible_class_change_error_id:
1303 { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
1304 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1305 }
1306 break;
1307
1308 case slow_subtype_check_id:
1309 {
1310 // Typical calling sequence:
1311 // __ push(klass_RInfo); // object klass or other subclass
1312 // __ push(sup_k_RInfo); // array element klass or other superclass
1313 // __ call(slow_subtype_check);
1314 // Note that the subclass is pushed first, and is therefore deepest.
1315 // Previous versions of this code reversed the names 'sub' and 'super'.
1316 // This was operationally harmless but made the code unreadable.
1317 enum layout {
1318 rax_off, SLOT2(raxH_off)
1319 rcx_off, SLOT2(rcxH_off)
1320 rsi_off, SLOT2(rsiH_off)
1321 rdi_off, SLOT2(rdiH_off)
1322 // saved_rbp_off, SLOT2(saved_rbpH_off)
1323 return_off, SLOT2(returnH_off)
1324 sup_k_off, SLOT2(sup_kH_off)
1325 klass_off, SLOT2(superH_off)
1326 framesize,
1327 result_off = klass_off // deepest argument is also the return value
1328 };
1329
1330 __ set_info("slow_subtype_check", dont_gc_arguments);
1331 __ push(rdi);
1332 __ push(rsi);
1333 __ push(rcx);
1334 __ push(rax);
1335
1336 // This is called by pushing args and not with C abi
1337 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass
1338 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass
1339
1340 Label miss;
1341 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss);
1342
1343 // fallthrough on success:
1344 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result
1345 __ pop(rax);
1346 __ pop(rcx);
1347 __ pop(rsi);
1348 __ pop(rdi);
1349 __ ret(0);
1350
1351 __ bind(miss);
1352 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result
1353 __ pop(rax);
1354 __ pop(rcx);
1355 __ pop(rsi);
1356 __ pop(rdi);
1357 __ ret(0);
1358 }
1359 break;
1360
1361 case monitorenter_nofpu_id:
1362 save_fpu_registers = false;
1363 // fall through
1364 case monitorenter_id:
1365 {
1366 StubFrame f(sasm, "monitorenter", dont_gc_arguments);
1367 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
1368
1369 // Called with store_parameter and not C abi
1370
1371 f.load_argument(1, rax); // rax,: object
1372 f.load_argument(0, rbx); // rbx,: lock address
1373
1374 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx);
1375
1376 oop_maps = new OopMapSet();
1377 oop_maps->add_gc_map(call_offset, map);
1378 restore_live_registers(sasm, save_fpu_registers);
1379 }
1380 break;
1381
1382 case monitorexit_nofpu_id:
1383 save_fpu_registers = false;
1384 // fall through
1385 case monitorexit_id:
1386 {
1387 StubFrame f(sasm, "monitorexit", dont_gc_arguments);
1388 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
1389
1390 // Called with store_parameter and not C abi
1391
1392 f.load_argument(0, rax); // rax,: lock address
1393
1394 // note: really a leaf routine but must setup last java sp
1395 // => use call_RT for now (speed can be improved by
1396 // doing last java sp setup manually)
1397 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax);
1398
1399 oop_maps = new OopMapSet();
1400 oop_maps->add_gc_map(call_offset, map);
1401 restore_live_registers(sasm, save_fpu_registers);
1402 }
1403 break;
1404
1405 case deoptimize_id:
1406 {
1407 StubFrame f(sasm, "deoptimize", dont_gc_arguments);
1408 const int num_rt_args = 2; // thread, trap_request
1409 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
1410 f.load_argument(0, rax);
1411 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), rax);
1412 oop_maps = new OopMapSet();
1413 oop_maps->add_gc_map(call_offset, oop_map);
1414 restore_live_registers(sasm);
1415 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1416 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1417 __ leave();
1418 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1419 }
1420 break;
1421
1422 case access_field_patching_id:
1423 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
1424 // we should set up register map
1425 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1426 }
1427 break;
1428
1429 case load_klass_patching_id:
1430 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
1431 // we should set up register map
1432 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1433 }
1434 break;
1435
1436 case load_mirror_patching_id:
1437 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments);
1438 // we should set up register map
1439 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1440 }
1441 break;
1442
1443 case load_appendix_patching_id:
1444 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
1445 // we should set up register map
1446 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1447 }
1448 break;
1449
1450 case dtrace_object_alloc_id:
1451 { // rax,: object
1452 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
1453 // we can't gc here so skip the oopmap but make sure that all
1454 // the live registers get saved.
1455 save_live_registers(sasm, 1);
1456
1457 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
1458 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
1459 NOT_LP64(__ pop(rax));
1460
1461 restore_live_registers(sasm);
1462 }
1463 break;
1464
1465 case fpu2long_stub_id:
1466 {
1467 // rax, and rdx are destroyed, but should be free since the result is returned there
1468 // preserve rsi,ecx
1469 __ push(rsi);
1470 __ push(rcx);
1471 LP64_ONLY(__ push(rdx);)
1472
1473 // check for NaN
1474 Label return0, do_return, return_min_jlong, do_convert;
1475
1476 Address value_high_word(rsp, wordSize + 4);
1477 Address value_low_word(rsp, wordSize);
1478 Address result_high_word(rsp, 3*wordSize + 4);
1479 Address result_low_word(rsp, 3*wordSize);
1480
1481 __ subptr(rsp, 32); // more than enough on 32bit
1482 __ fst_d(value_low_word);
1483 __ movl(rax, value_high_word);
1484 __ andl(rax, 0x7ff00000);
1485 __ cmpl(rax, 0x7ff00000);
1486 __ jcc(Assembler::notEqual, do_convert);
1487 __ movl(rax, value_high_word);
1488 __ andl(rax, 0xfffff);
1489 __ orl(rax, value_low_word);
1490 __ jcc(Assembler::notZero, return0);
1491
1492 __ bind(do_convert);
1493 __ fnstcw(Address(rsp, 0));
1494 __ movzwl(rax, Address(rsp, 0));
1495 __ orl(rax, 0xc00);
1496 __ movw(Address(rsp, 2), rax);
1497 __ fldcw(Address(rsp, 2));
1498 __ fwait();
1499 __ fistp_d(result_low_word);
1500 __ fldcw(Address(rsp, 0));
1501 __ fwait();
1502 // This gets the entire long in rax on 64bit
1503 __ movptr(rax, result_low_word);
1504 // testing of high bits
1505 __ movl(rdx, result_high_word);
1506 __ mov(rcx, rax);
1507 // What the heck is the point of the next instruction???
1508 __ xorl(rcx, 0x0);
1509 __ movl(rsi, 0x80000000);
1510 __ xorl(rsi, rdx);
1511 __ orl(rcx, rsi);
1512 __ jcc(Assembler::notEqual, do_return);
1513 __ fldz();
1514 __ fcomp_d(value_low_word);
1515 __ fnstsw_ax();
1516 #ifdef _LP64
1517 __ testl(rax, 0x4100); // ZF & CF == 0
1518 __ jcc(Assembler::equal, return_min_jlong);
1519 #else
1520 __ sahf();
1521 __ jcc(Assembler::above, return_min_jlong);
1522 #endif // _LP64
1523 // return max_jlong
1524 #ifndef _LP64
1525 __ movl(rdx, 0x7fffffff);
1526 __ movl(rax, 0xffffffff);
1527 #else
1528 __ mov64(rax, CONST64(0x7fffffffffffffff));
1529 #endif // _LP64
1530 __ jmp(do_return);
1531
1532 __ bind(return_min_jlong);
1533 #ifndef _LP64
1534 __ movl(rdx, 0x80000000);
1535 __ xorl(rax, rax);
1536 #else
1537 __ mov64(rax, UCONST64(0x8000000000000000));
1538 #endif // _LP64
1539 __ jmp(do_return);
1540
1541 __ bind(return0);
1542 __ fpop();
1543 #ifndef _LP64
1544 __ xorptr(rdx,rdx);
1545 __ xorptr(rax,rax);
1546 #else
1547 __ xorptr(rax, rax);
1548 #endif // _LP64
1549
1550 __ bind(do_return);
1551 __ addptr(rsp, 32);
1552 LP64_ONLY(__ pop(rdx);)
1553 __ pop(rcx);
1554 __ pop(rsi);
1555 __ ret(0);
1556 }
1557 break;
1558
1559 #if INCLUDE_ALL_GCS
1560 case g1_pre_barrier_slow_id:
1561 {
1562 StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments);
1563 // arg0 : previous value of memory
1564
1565 BarrierSet* bs = Universe::heap()->barrier_set();
1566 if (bs->kind() != BarrierSet::G1BarrierSet) {
1567 __ movptr(rax, (int)id);
1568 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1569 __ should_not_reach_here();
1570 break;
1571 }
1572 __ push(rax);
1573 __ push(rdx);
1574
1575 const Register pre_val = rax;
1576 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
1577 const Register tmp = rdx;
1578
1579 NOT_LP64(__ get_thread(thread);)
1580
1581 Address queue_active(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1582 SATBMarkQueue::byte_offset_of_active()));
1583 Address queue_index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1584 SATBMarkQueue::byte_offset_of_index()));
1585 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1586 SATBMarkQueue::byte_offset_of_buf()));
1587
1588 Label done;
1589 Label runtime;
1590
1591 // Is marking still active?
1592 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
1593 __ cmpl(queue_active, 0);
1594 } else {
1595 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
1596 __ cmpb(queue_active, 0);
1597 }
1598 __ jcc(Assembler::equal, done);
1599
1600 // Can we store original value in the thread's buffer?
1601
1602 __ movptr(tmp, queue_index);
1603 __ testptr(tmp, tmp);
1604 __ jcc(Assembler::zero, runtime);
1605 __ subptr(tmp, wordSize);
1606 __ movptr(queue_index, tmp);
1607 __ addptr(tmp, buffer);
1608
1609 // prev_val (rax)
1610 f.load_argument(0, pre_val);
1611 __ movptr(Address(tmp, 0), pre_val);
1612 __ jmp(done);
1613
1614 __ bind(runtime);
1615
1616 save_live_registers(sasm, 3);
1617
1618 // load the pre-value
1619 f.load_argument(0, rcx);
1620 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread);
1621
1622 restore_live_registers(sasm);
1623
1624 __ bind(done);
1625
1626 __ pop(rdx);
1627 __ pop(rax);
1628 }
1629 break;
1630
1631 case g1_post_barrier_slow_id:
1632 {
1633 StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments);
1634
1635
1636 // arg0: store_address
1637 Address store_addr(rbp, 2*BytesPerWord);
1638
1639 Label done;
1640 Label enqueued;
1641 Label runtime;
1642
1643 // At this point we know new_value is non-NULL and the new_value crosses regions.
1644 // Must check to see if card is already dirty
1645
1646 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
1647
1648 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1649 DirtyCardQueue::byte_offset_of_index()));
1650 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1651 DirtyCardQueue::byte_offset_of_buf()));
1652
1653 __ push(rax);
1654 __ push(rcx);
1655
1656 const Register cardtable = rax;
1657 const Register card_addr = rcx;
1658
1659 f.load_argument(0, card_addr);
1660 __ shrptr(card_addr, CardTable::card_shift);
1661 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
1662 // a valid address and therefore is not properly handled by the relocation code.
1663 __ movptr(cardtable, ci_card_table_address_as<intptr_t>());
1664 __ addptr(card_addr, cardtable);
1665
1666 NOT_LP64(__ get_thread(thread);)
1667
1668 __ cmpb(Address(card_addr, 0), (int)G1CardTable::g1_young_card_val());
1669 __ jcc(Assembler::equal, done);
1670
1671 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
1672 __ cmpb(Address(card_addr, 0), (int)CardTable::dirty_card_val());
1673 __ jcc(Assembler::equal, done);
1674
1675 // storing region crossing non-NULL, card is clean.
1676 // dirty card and log.
1677
1678 __ movb(Address(card_addr, 0), (int)CardTable::dirty_card_val());
1679
1680 const Register tmp = rdx;
1681 __ push(rdx);
1682
1683 __ movptr(tmp, queue_index);
1684 __ testptr(tmp, tmp);
1685 __ jcc(Assembler::zero, runtime);
1686 __ subptr(tmp, wordSize);
1687 __ movptr(queue_index, tmp);
1688 __ addptr(tmp, buffer);
1689 __ movptr(Address(tmp, 0), card_addr);
1690 __ jmp(enqueued);
1691
1692 __ bind(runtime);
1693
1694 save_live_registers(sasm, 3);
1695
1696 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1697
1698 restore_live_registers(sasm);
1699
1700 __ bind(enqueued);
1701 __ pop(rdx);
1702
1703 __ bind(done);
1704 __ pop(rcx);
1705 __ pop(rax);
1706 }
1707 break;
1708 #endif // INCLUDE_ALL_GCS
1709
1710 case predicate_failed_trap_id:
1711 {
1712 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
1713
1714 OopMap* map = save_live_registers(sasm, 1);
1715
1716 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1717 oop_maps = new OopMapSet();
1718 oop_maps->add_gc_map(call_offset, map);
1719 restore_live_registers(sasm);
1720 __ leave();
1721 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1722 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1723
1724 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1725 }
1726 break;
1727
1728 default:
1729 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
1730 __ movptr(rax, (int)id);
1731 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1732 __ should_not_reach_here();
1733 }
1734 break;
1735 }
1736 return oop_maps;
1737 }
1738
1739 #undef __
1740
1741 const char *Runtime1::pd_name_for_address(address entry) {
1742 return "<unknown function>";
1743 }