1 /*
 2  * Copyright (c) 2008, 2014, Oracle and/or its affiliates. All rights reserved.
 3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 4  *
 5  * This code is free software; you can redistribute it and/or modify it
 6  * under the terms of the GNU General Public License version 2 only, as
 7  * published by the Free Software Foundation.
 8  *
 9  * This code is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  * version 2 for more details (a copy is included in the LICENSE file that
13  * accompanied this code).
14  *
15  * You should have received a copy of the GNU General Public License version
16  * 2 along with this work; if not, write to the Free Software Foundation,
17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18  *
19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20  * or visit www.oracle.com if you need additional information or have any
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24 
25 #ifndef CPU_ARM_VM_C1_DEFS_ARM_HPP
26 #define CPU_ARM_VM_C1_DEFS_ARM_HPP
27 
28 // native word offsets from memory address (little endian)
29 enum {
30   pd_lo_word_offset_in_bytes = 0,
31   pd_hi_word_offset_in_bytes = BytesPerWord
32 };
33 
34 // explicit rounding operations are required to implement the strictFP mode
35 enum {
36   pd_strict_fp_requires_explicit_rounding = false
37 };
38 
39 #ifdef __SOFTFP__
40 #define SOFT(n) n
41 #define VFP(n)
42 #else  // __SOFTFP__
43 #define SOFT(n)
44 #define VFP(n)        n
45 #endif // __SOFTFP__
46 
47 
48 // registers
49 enum {
50   pd_nof_cpu_regs_frame_map             = AARCH64_ONLY(33) NOT_AARCH64(16), // number of registers used during code emission
51   pd_nof_caller_save_cpu_regs_frame_map = AARCH64_ONLY(27) NOT_AARCH64(10), // number of registers killed by calls
52   pd_nof_cpu_regs_reg_alloc             = AARCH64_ONLY(27) NOT_AARCH64(10), // number of registers that are visible to register allocator (including Rheap_base which is visible only if compressed pointers are not enabled)
53   pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map,                   // number of registers visible to linear scan
54   pd_nof_cpu_regs_processed_in_linearscan = pd_nof_cpu_regs_reg_alloc + 1,  // number of registers processed in linear scan; includes LR as it is used as temporary register in c1_LIRGenerator_arm
55   pd_first_cpu_reg = 0,
56   pd_last_cpu_reg  = pd_nof_cpu_regs_frame_map - 1,
57 
58   pd_nof_fpu_regs_frame_map             = VFP(32) SOFT(0),                               // number of float registers used during code emission
59   pd_nof_caller_save_fpu_regs_frame_map = VFP(32) SOFT(0),                               // number of float registers killed by calls
60   pd_nof_fpu_regs_reg_alloc             = AARCH64_ONLY(32) NOT_AARCH64(VFP(30) SOFT(0)), // number of float registers that are visible to register allocator
61   pd_nof_fpu_regs_linearscan            = pd_nof_fpu_regs_frame_map,                     // number of float registers visible to linear scan
62   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
63   pd_last_fpu_reg  = pd_first_fpu_reg + pd_nof_fpu_regs_frame_map - 1,
64 
65   pd_nof_xmm_regs_linearscan = 0,
66   pd_nof_caller_save_xmm_regs = 0,
67   pd_first_xmm_reg = -1,
68   pd_last_xmm_reg  = -1
69 };
70 
71 
72 // encoding of float value in debug info:
73 enum {
74   pd_float_saved_as_double = false
75 };
76 
77 #ifdef AARCH64
78 #define PATCHED_ADDR 0xff8
79 #else
80 #define PATCHED_ADDR (204)
81 #endif
82 #define CARDTABLEBARRIERSET_POST_BARRIER_HELPER
83 #define GENERATE_ADDRESS_IS_PREFERRED
84 
85 #endif // CPU_ARM_VM_C1_DEFS_ARM_HPP