8199604_cardtablemodrefbs_rename
17 *
18 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
19 * or visit www.oracle.com if you need additional information or have any
20 * questions.
21 *
22 */
23
24 #include "precompiled.hpp"
25 #include "c1/c1_Compilation.hpp"
26 #include "c1/c1_FrameMap.hpp"
27 #include "c1/c1_Instruction.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_LIRGenerator.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArray.hpp"
33 #include "ci/ciObjArrayKlass.hpp"
34 #include "ci/ciTypeArrayKlass.hpp"
35 #include "ci/ciUtilities.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/cardTableModRefBS.hpp"
38 #include "runtime/sharedRuntime.hpp"
39 #include "runtime/stubRoutines.hpp"
40 #include "vmreg_arm.inline.hpp"
41
42 #ifdef ASSERT
43 #define __ gen()->lir(__FILE__, __LINE__)->
44 #else
45 #define __ gen()->lir()->
46 #endif
47
48 void LIRItem::load_byte_item() {
49 load_item();
50 }
51
52 void LIRItem::load_nonconstant() {
53 LIR_Opr r = value()->operand();
54 if (_gen->can_inline_as_constant(value())) {
55 if (!r->is_constant()) {
56 r = LIR_OprFact::value_type(value()->type());
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17 *
18 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
19 * or visit www.oracle.com if you need additional information or have any
20 * questions.
21 *
22 */
23
24 #include "precompiled.hpp"
25 #include "c1/c1_Compilation.hpp"
26 #include "c1/c1_FrameMap.hpp"
27 #include "c1/c1_Instruction.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_LIRGenerator.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArray.hpp"
33 #include "ci/ciObjArrayKlass.hpp"
34 #include "ci/ciTypeArrayKlass.hpp"
35 #include "ci/ciUtilities.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "runtime/sharedRuntime.hpp"
39 #include "runtime/stubRoutines.hpp"
40 #include "vmreg_arm.inline.hpp"
41
42 #ifdef ASSERT
43 #define __ gen()->lir(__FILE__, __LINE__)->
44 #else
45 #define __ gen()->lir()->
46 #endif
47
48 void LIRItem::load_byte_item() {
49 load_item();
50 }
51
52 void LIRItem::load_nonconstant() {
53 LIR_Opr r = value()->operand();
54 if (_gen->can_inline_as_constant(value())) {
55 if (!r->is_constant()) {
56 r = LIR_OprFact::value_type(value()->type());
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479 assert(CardTable::dirty_card_val() == 0,
480 "Cannot use ZR register (aarch64) or the register containing the card table base address directly (aarch32) otherwise");
481 #ifdef AARCH64
482 // AARCH64 has a register that is constant zero. We can use that one to set the
483 // value in the card table to dirty.
484 __ move(FrameMap::ZR_opr, card_addr);
485 #else // AARCH64
486 if((ci_card_table_address_as<intx>() & 0xff) == 0) {
487 // If the card table base address is aligned to 256 bytes, we can use the register
488 // that contains the card_table_base_address.
489 __ move(value, card_addr);
490 } else {
491 // Otherwise we need to create a register containing that value.
492 LIR_Opr tmp_zero = new_register(T_INT);
493 __ move(LIR_OprFact::intConst(CardTable::dirty_card_val()), tmp_zero);
494 __ move(tmp_zero, card_addr);
495 }
496 #endif // AARCH64
497 }
498
499 void LIRGenerator::CardTableModRef_post_barrier_helper(LIR_OprDesc* addr, LIR_Const* card_table_base) {
500 assert(addr->is_register(), "must be a register at this point");
501
502 LIR_Opr tmp = FrameMap::LR_ptr_opr;
503
504 // TODO-AARCH64: check performance
505 bool load_card_table_base_const = AARCH64_ONLY(false) NOT_AARCH64(VM_Version::supports_movw());
506 if (load_card_table_base_const) {
507 __ move((LIR_Opr)card_table_base, tmp);
508 } else {
509 __ move(new LIR_Address(FrameMap::Rthread_opr, in_bytes(JavaThread::card_table_base_offset()), T_ADDRESS), tmp);
510 }
511
512 #ifdef AARCH64
513 LIR_Address* shifted_reg_operand = new LIR_Address(tmp, addr, (LIR_Address::Scale) -CardTable::card_shift, 0, T_BYTE);
514 LIR_Opr tmp2 = tmp;
515 __ add(tmp, LIR_OprFact::address(shifted_reg_operand), tmp2); // tmp2 = tmp + (addr >> CardTable::card_shift)
516 LIR_Address* card_addr = new LIR_Address(tmp2, T_BYTE);
517 #else
518 // Use unsigned type T_BOOLEAN here rather than (signed) T_BYTE since signed load
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479 assert(CardTable::dirty_card_val() == 0,
480 "Cannot use ZR register (aarch64) or the register containing the card table base address directly (aarch32) otherwise");
481 #ifdef AARCH64
482 // AARCH64 has a register that is constant zero. We can use that one to set the
483 // value in the card table to dirty.
484 __ move(FrameMap::ZR_opr, card_addr);
485 #else // AARCH64
486 if((ci_card_table_address_as<intx>() & 0xff) == 0) {
487 // If the card table base address is aligned to 256 bytes, we can use the register
488 // that contains the card_table_base_address.
489 __ move(value, card_addr);
490 } else {
491 // Otherwise we need to create a register containing that value.
492 LIR_Opr tmp_zero = new_register(T_INT);
493 __ move(LIR_OprFact::intConst(CardTable::dirty_card_val()), tmp_zero);
494 __ move(tmp_zero, card_addr);
495 }
496 #endif // AARCH64
497 }
498
499 void LIRGenerator::CardTableBarrierSet_post_barrier_helper(LIR_OprDesc* addr, LIR_Const* card_table_base) {
500 assert(addr->is_register(), "must be a register at this point");
501
502 LIR_Opr tmp = FrameMap::LR_ptr_opr;
503
504 // TODO-AARCH64: check performance
505 bool load_card_table_base_const = AARCH64_ONLY(false) NOT_AARCH64(VM_Version::supports_movw());
506 if (load_card_table_base_const) {
507 __ move((LIR_Opr)card_table_base, tmp);
508 } else {
509 __ move(new LIR_Address(FrameMap::Rthread_opr, in_bytes(JavaThread::card_table_base_offset()), T_ADDRESS), tmp);
510 }
511
512 #ifdef AARCH64
513 LIR_Address* shifted_reg_operand = new LIR_Address(tmp, addr, (LIR_Address::Scale) -CardTable::card_shift, 0, T_BYTE);
514 LIR_Opr tmp2 = tmp;
515 __ add(tmp, LIR_OprFact::address(shifted_reg_operand), tmp2); // tmp2 = tmp + (addr >> CardTable::card_shift)
516 LIR_Address* card_addr = new LIR_Address(tmp2, T_BYTE);
517 #else
518 // Use unsigned type T_BOOLEAN here rather than (signed) T_BYTE since signed load
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