1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/safepointMechanism.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41
42 #define __ _masm->
43
44
45 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
46
47
48 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
49 Unimplemented(); return false; // Currently not used on this platform.
50 }
51
52
53 LIR_Opr LIR_Assembler::receiverOpr() {
54 return FrameMap::R3_oop_opr;
55 }
56
57
58 LIR_Opr LIR_Assembler::osrBufferPointer() {
59 return FrameMap::R3_opr;
60 }
61
62
63 // This specifies the stack pointer decrement needed to build the frame.
64 int LIR_Assembler::initial_frame_size_in_bytes() const {
65 return in_bytes(frame_map()->framesize_in_bytes());
66 }
67
68
69 // Inline cache check: the inline cached class is in inline_cache_reg;
70 // we fetch the class of the receiver and compare it with the cached class.
71 // If they do not match we jump to slow case.
72 int LIR_Assembler::check_icache() {
73 int offset = __ offset();
74 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
75 return offset;
76 }
77
78
79 void LIR_Assembler::osr_entry() {
80 // On-stack-replacement entry sequence:
81 //
82 // 1. Create a new compiled activation.
83 // 2. Initialize local variables in the compiled activation. The expression
84 // stack must be empty at the osr_bci; it is not initialized.
85 // 3. Jump to the continuation address in compiled code to resume execution.
86
87 // OSR entry point
88 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
89 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
90 ValueStack* entry_state = osr_entry->end()->state();
91 int number_of_locks = entry_state->locks_size();
92
93 // Create a frame for the compiled activation.
94 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
95
96 // OSR buffer is
97 //
98 // locals[nlocals-1..0]
99 // monitors[number_of_locks-1..0]
100 //
101 // Locals is a direct copy of the interpreter frame so in the osr buffer
102 // the first slot in the local array is the last local from the interpreter
103 // and the last slot is local[0] (receiver) from the interpreter.
104 //
105 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
106 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
107 // in the interpreter frame (the method lock if a sync method).
108
109 // Initialize monitors in the compiled activation.
110 // R3: pointer to osr buffer
111 //
112 // All other registers are dead at this point and the locals will be
113 // copied into place by code emitted in the IR.
114
115 Register OSR_buf = osrBufferPointer()->as_register();
116 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
117 int monitor_offset = BytesPerWord * method()->max_locals() +
118 (2 * BytesPerWord) * (number_of_locks - 1);
119 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
120 // the OSR buffer using 2 word entries: first the lock and then
121 // the oop.
122 for (int i = 0; i < number_of_locks; i++) {
123 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
124 #ifdef ASSERT
125 // Verify the interpreter's monitor has a non-null object.
126 {
127 Label L;
128 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
129 __ cmpdi(CCR0, R0, 0);
130 __ bne(CCR0, L);
131 __ stop("locked object is NULL");
132 __ bind(L);
133 }
134 #endif // ASSERT
135 // Copy the lock field into the compiled activation.
136 Address ml = frame_map()->address_for_monitor_lock(i),
137 mo = frame_map()->address_for_monitor_object(i);
138 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
139 __ ld(R0, slot_offset + 0, OSR_buf);
140 __ std(R0, ml.disp(), ml.base());
141 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
142 __ std(R0, mo.disp(), mo.base());
143 }
144 }
145 }
146
147
148 int LIR_Assembler::emit_exception_handler() {
149 // If the last instruction is a call (typically to do a throw which
150 // is coming at the end after block reordering) the return address
151 // must still point into the code area in order to avoid assertion
152 // failures when searching for the corresponding bci => add a nop
153 // (was bug 5/14/1999 - gri).
154 __ nop();
155
156 // Generate code for the exception handler.
157 address handler_base = __ start_a_stub(exception_handler_size());
158
159 if (handler_base == NULL) {
160 // Not enough space left for the handler.
161 bailout("exception handler overflow");
162 return -1;
163 }
164
165 int offset = code_offset();
166 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
167 //__ load_const_optimized(R0, entry_point);
168 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
169 __ mtctr(R0);
170 __ bctr();
171
172 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
173 __ end_a_stub();
174
175 return offset;
176 }
177
178
179 // Emit the code to remove the frame from the stack in the exception
180 // unwind path.
181 int LIR_Assembler::emit_unwind_handler() {
182 _masm->block_comment("Unwind handler");
183
184 int offset = code_offset();
185 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
186 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
187
188 // Fetch the exception from TLS and clear out exception related thread state.
189 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
190 __ li(R0, 0);
191 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
192 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
193
194 __ bind(_unwind_handler_entry);
195 __ verify_not_null_oop(Rexception);
196 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
197
198 // Perform needed unlocking
199 MonitorExitStub* stub = NULL;
200 if (method()->is_synchronized()) {
201 monitor_address(0, FrameMap::R4_opr);
202 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
203 __ unlock_object(R5, R6, R4, *stub->entry());
204 __ bind(*stub->continuation());
205 }
206
207 if (compilation()->env()->dtrace_method_probes()) {
208 Unimplemented();
209 }
210
211 // Dispatch to the unwind logic.
212 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
213 //__ load_const_optimized(R0, unwind_stub);
214 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
215 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
216 __ mtctr(R0);
217 __ bctr();
218
219 // Emit the slow path assembly.
220 if (stub != NULL) {
221 stub->emit_code(this);
222 }
223
224 return offset;
225 }
226
227
228 int LIR_Assembler::emit_deopt_handler() {
229 // If the last instruction is a call (typically to do a throw which
230 // is coming at the end after block reordering) the return address
231 // must still point into the code area in order to avoid assertion
232 // failures when searching for the corresponding bci => add a nop
233 // (was bug 5/14/1999 - gri).
234 __ nop();
235
236 // Generate code for deopt handler.
237 address handler_base = __ start_a_stub(deopt_handler_size());
238
239 if (handler_base == NULL) {
240 // Not enough space left for the handler.
241 bailout("deopt handler overflow");
242 return -1;
243 }
244
245 int offset = code_offset();
246 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
247
248 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
249 __ end_a_stub();
250
251 return offset;
252 }
253
254
255 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
256 if (o == NULL) {
257 __ li(reg, 0);
258 } else {
259 AddressLiteral addrlit = __ constant_oop_address(o);
260 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
261 }
262 }
263
264
265 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
266 // Allocate a new index in table to hold the object once it's been patched.
267 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
268 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
269
270 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
271 __ load_const(reg, addrlit, R0);
272
273 patching_epilog(patch, lir_patch_normal, reg, info);
274 }
275
276
277 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
278 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
279 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
280 }
281
282
283 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
284 // Allocate a new index in table to hold the klass once it's been patched.
285 int index = __ oop_recorder()->allocate_metadata_index(NULL);
286 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
287
288 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
289 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
290 __ load_const(reg, addrlit, R0);
291
292 patching_epilog(patch, lir_patch_normal, reg, info);
293 }
294
295
296 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
297 const bool is_int = result->is_single_cpu();
298 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
299 Register Rdivisor = noreg;
300 Register Rscratch = temp->as_register();
301 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
302 long divisor = -1;
303
304 if (right->is_register()) {
305 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
306 } else {
307 divisor = is_int ? right->as_constant_ptr()->as_jint()
308 : right->as_constant_ptr()->as_jlong();
309 }
310
311 assert(Rdividend != Rscratch, "");
312 assert(Rdivisor != Rscratch, "");
313 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
314
315 if (Rdivisor == noreg) {
316 if (divisor == 1) { // stupid, but can happen
317 if (code == lir_idiv) {
318 __ mr_if_needed(Rresult, Rdividend);
319 } else {
320 __ li(Rresult, 0);
321 }
322
323 } else if (is_power_of_2(divisor)) {
324 // Convert division by a power of two into some shifts and logical operations.
325 int log2 = log2_intptr(divisor);
326
327 // Round towards 0.
328 if (divisor == 2) {
329 if (is_int) {
330 __ srwi(Rscratch, Rdividend, 31);
331 } else {
332 __ srdi(Rscratch, Rdividend, 63);
333 }
334 } else {
335 if (is_int) {
336 __ srawi(Rscratch, Rdividend, 31);
337 } else {
338 __ sradi(Rscratch, Rdividend, 63);
339 }
340 __ clrldi(Rscratch, Rscratch, 64-log2);
341 }
342 __ add(Rscratch, Rdividend, Rscratch);
343
344 if (code == lir_idiv) {
345 if (is_int) {
346 __ srawi(Rresult, Rscratch, log2);
347 } else {
348 __ sradi(Rresult, Rscratch, log2);
349 }
350 } else { // lir_irem
351 __ clrrdi(Rscratch, Rscratch, log2);
352 __ sub(Rresult, Rdividend, Rscratch);
353 }
354
355 } else if (divisor == -1) {
356 if (code == lir_idiv) {
357 __ neg(Rresult, Rdividend);
358 } else {
359 __ li(Rresult, 0);
360 }
361
362 } else {
363 __ load_const_optimized(Rscratch, divisor);
364 if (code == lir_idiv) {
365 if (is_int) {
366 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
367 } else {
368 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
369 }
370 } else {
371 assert(Rscratch != R0, "need both");
372 if (is_int) {
373 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
374 __ mullw(Rscratch, R0, Rscratch);
375 } else {
376 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
377 __ mulld(Rscratch, R0, Rscratch);
378 }
379 __ sub(Rresult, Rdividend, Rscratch);
380 }
381
382 }
383 return;
384 }
385
386 Label regular, done;
387 if (is_int) {
388 __ cmpwi(CCR0, Rdivisor, -1);
389 } else {
390 __ cmpdi(CCR0, Rdivisor, -1);
391 }
392 __ bne(CCR0, regular);
393 if (code == lir_idiv) {
394 __ neg(Rresult, Rdividend);
395 __ b(done);
396 __ bind(regular);
397 if (is_int) {
398 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
399 } else {
400 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
401 }
402 } else { // lir_irem
403 __ li(Rresult, 0);
404 __ b(done);
405 __ bind(regular);
406 if (is_int) {
407 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
408 __ mullw(Rscratch, Rscratch, Rdivisor);
409 } else {
410 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
411 __ mulld(Rscratch, Rscratch, Rdivisor);
412 }
413 __ sub(Rresult, Rdividend, Rscratch);
414 }
415 __ bind(done);
416 }
417
418
419 void LIR_Assembler::emit_op3(LIR_Op3* op) {
420 switch (op->code()) {
421 case lir_idiv:
422 case lir_irem:
423 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
424 op->result_opr(), op->info());
425 break;
426 case lir_fmad:
427 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
428 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
429 break;
430 case lir_fmaf:
431 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
432 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
433 break;
434 default: ShouldNotReachHere(); break;
435 }
436 }
437
438
439 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
440 #ifdef ASSERT
441 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
442 if (op->block() != NULL) _branch_target_blocks.append(op->block());
443 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
444 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
445 #endif
446
447 Label *L = op->label();
448 if (op->cond() == lir_cond_always) {
449 __ b(*L);
450 } else {
451 Label done;
452 bool is_unordered = false;
453 if (op->code() == lir_cond_float_branch) {
454 assert(op->ublock() != NULL, "must have unordered successor");
455 is_unordered = true;
456 } else {
457 assert(op->code() == lir_branch, "just checking");
458 }
459
460 bool positive = false;
461 Assembler::Condition cond = Assembler::equal;
462 switch (op->cond()) {
463 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
464 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
465 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
466 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
467 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
468 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
469 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
470 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
471 default: ShouldNotReachHere();
472 }
473 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
474 int bi = Assembler::bi0(BOOL_RESULT, cond);
475 if (is_unordered) {
476 if (positive) {
477 if (op->ublock() == op->block()) {
478 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
479 }
480 } else {
481 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
482 }
483 }
484 __ bc_far_optimized(bo, bi, *L);
485 __ bind(done);
486 }
487 }
488
489
490 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
491 Bytecodes::Code code = op->bytecode();
492 LIR_Opr src = op->in_opr(),
493 dst = op->result_opr();
494
495 switch(code) {
496 case Bytecodes::_i2l: {
497 __ extsw(dst->as_register_lo(), src->as_register());
498 break;
499 }
500 case Bytecodes::_l2i: {
501 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
502 break;
503 }
504 case Bytecodes::_i2b: {
505 __ extsb(dst->as_register(), src->as_register());
506 break;
507 }
508 case Bytecodes::_i2c: {
509 __ clrldi(dst->as_register(), src->as_register(), 64-16);
510 break;
511 }
512 case Bytecodes::_i2s: {
513 __ extsh(dst->as_register(), src->as_register());
514 break;
515 }
516 case Bytecodes::_i2d:
517 case Bytecodes::_l2d: {
518 bool src_in_memory = !VM_Version::has_mtfprd();
519 FloatRegister rdst = dst->as_double_reg();
520 FloatRegister rsrc;
521 if (src_in_memory) {
522 rsrc = src->as_double_reg(); // via mem
523 } else {
524 // move src to dst register
525 if (code == Bytecodes::_i2d) {
526 __ mtfprwa(rdst, src->as_register());
527 } else {
528 __ mtfprd(rdst, src->as_register_lo());
529 }
530 rsrc = rdst;
531 }
532 __ fcfid(rdst, rsrc);
533 break;
534 }
535 case Bytecodes::_i2f:
536 case Bytecodes::_l2f: {
537 bool src_in_memory = !VM_Version::has_mtfprd();
538 FloatRegister rdst = dst->as_float_reg();
539 FloatRegister rsrc;
540 if (src_in_memory) {
541 rsrc = src->as_double_reg(); // via mem
542 } else {
543 // move src to dst register
544 if (code == Bytecodes::_i2f) {
545 __ mtfprwa(rdst, src->as_register());
546 } else {
547 __ mtfprd(rdst, src->as_register_lo());
548 }
549 rsrc = rdst;
550 }
551 if (VM_Version::has_fcfids()) {
552 __ fcfids(rdst, rsrc);
553 } else {
554 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
555 __ fcfid(rdst, rsrc);
556 __ frsp(rdst, rdst);
557 }
558 break;
559 }
560 case Bytecodes::_f2d: {
561 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
562 break;
563 }
564 case Bytecodes::_d2f: {
565 __ frsp(dst->as_float_reg(), src->as_double_reg());
566 break;
567 }
568 case Bytecodes::_d2i:
569 case Bytecodes::_f2i: {
570 bool dst_in_memory = !VM_Version::has_mtfprd();
571 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
572 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
573 Label L;
574 // Result must be 0 if value is NaN; test by comparing value to itself.
575 __ fcmpu(CCR0, rsrc, rsrc);
576 if (dst_in_memory) {
577 __ li(R0, 0); // 0 in case of NAN
578 __ std(R0, addr.disp(), addr.base());
579 } else {
580 __ li(dst->as_register(), 0);
581 }
582 __ bso(CCR0, L);
583 __ fctiwz(rsrc, rsrc); // USE_KILL
584 if (dst_in_memory) {
585 __ stfd(rsrc, addr.disp(), addr.base());
586 } else {
587 __ mffprd(dst->as_register(), rsrc);
588 }
589 __ bind(L);
590 break;
591 }
592 case Bytecodes::_d2l:
593 case Bytecodes::_f2l: {
594 bool dst_in_memory = !VM_Version::has_mtfprd();
595 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
596 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
597 Label L;
598 // Result must be 0 if value is NaN; test by comparing value to itself.
599 __ fcmpu(CCR0, rsrc, rsrc);
600 if (dst_in_memory) {
601 __ li(R0, 0); // 0 in case of NAN
602 __ std(R0, addr.disp(), addr.base());
603 } else {
604 __ li(dst->as_register_lo(), 0);
605 }
606 __ bso(CCR0, L);
607 __ fctidz(rsrc, rsrc); // USE_KILL
608 if (dst_in_memory) {
609 __ stfd(rsrc, addr.disp(), addr.base());
610 } else {
611 __ mffprd(dst->as_register_lo(), rsrc);
612 }
613 __ bind(L);
614 break;
615 }
616
617 default: ShouldNotReachHere();
618 }
619 }
620
621
622 void LIR_Assembler::align_call(LIR_Code) {
623 // do nothing since all instructions are word aligned on ppc
624 }
625
626
627 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
628 int start_offset = __ offset();
629 // Put the entry point as a constant into the constant pool.
630 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
631 if (entry_point_toc_addr == NULL) {
632 bailout("const section overflow");
633 return false;
634 }
635 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
636
637 // Emit the trampoline stub which will be related to the branch-and-link below.
638 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
639 if (!stub) {
640 bailout("no space for trampoline stub");
641 return false;
642 }
643 return true;
644 }
645
646
647 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
648 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
649
650 bool success = emit_trampoline_stub_for_call(op->addr());
651 if (!success) { return; }
652
653 __ relocate(rtype);
654 // Note: At this point we do not have the address of the trampoline
655 // stub, and the entry point might be too far away for bl, so __ pc()
656 // serves as dummy and the bl will be patched later.
657 __ code()->set_insts_mark();
658 __ bl(__ pc());
659 add_call_info(code_offset(), op->info());
660 }
661
662
663 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
664 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
665
666 // Virtual call relocation will point to ic load.
667 address virtual_call_meta_addr = __ pc();
668 // Load a clear inline cache.
669 AddressLiteral empty_ic((address) Universe::non_oop_word());
670 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
671 if (!success) {
672 bailout("const section overflow");
673 return;
674 }
675 // Call to fixup routine. Fixup routine uses ScopeDesc info
676 // to determine who we intended to call.
677 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
678
679 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
680 if (!success) { return; }
681
682 // Note: At this point we do not have the address of the trampoline
683 // stub, and the entry point might be too far away for bl, so __ pc()
684 // serves as dummy and the bl will be patched later.
685 __ bl(__ pc());
686 add_call_info(code_offset(), op->info());
687 }
688
689
690 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
691 ShouldNotReachHere(); // ic_call is used instead.
692 }
693
694
695 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
696 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
697 __ null_check(addr, stub->entry());
698 append_code_stub(stub);
699 }
700
701
702 // Attention: caller must encode oop if needed
703 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
704 int store_offset;
705 if (!Assembler::is_simm16(offset)) {
706 // For offsets larger than a simm16 we setup the offset.
707 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
708 __ load_const_optimized(R0, offset);
709 store_offset = store(from_reg, base, R0, type, wide);
710 } else {
711 store_offset = code_offset();
712 switch (type) {
713 case T_BOOLEAN: // fall through
714 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
715 case T_CHAR :
716 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
717 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
718 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
719 case T_ADDRESS:
720 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
721 case T_ARRAY : // fall through
722 case T_OBJECT:
723 {
724 if (UseCompressedOops && !wide) {
725 // Encoding done in caller
726 __ stw(from_reg->as_register(), offset, base);
727 } else {
728 __ std(from_reg->as_register(), offset, base);
729 }
730 __ verify_oop(from_reg->as_register());
731 break;
732 }
733 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
734 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
735 default : ShouldNotReachHere();
736 }
737 }
738 return store_offset;
739 }
740
741
742 // Attention: caller must encode oop if needed
743 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
744 int store_offset = code_offset();
745 switch (type) {
746 case T_BOOLEAN: // fall through
747 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
748 case T_CHAR :
749 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
750 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
751 case T_LONG :
752 #ifdef _LP64
753 __ stdx(from_reg->as_register_lo(), base, disp);
754 #else
755 Unimplemented();
756 #endif
757 break;
758 case T_ADDRESS:
759 __ stdx(from_reg->as_register(), base, disp);
760 break;
761 case T_ARRAY : // fall through
762 case T_OBJECT:
763 {
764 if (UseCompressedOops && !wide) {
765 // Encoding done in caller.
766 __ stwx(from_reg->as_register(), base, disp);
767 } else {
768 __ stdx(from_reg->as_register(), base, disp);
769 }
770 __ verify_oop(from_reg->as_register()); // kills R0
771 break;
772 }
773 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
774 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
775 default : ShouldNotReachHere();
776 }
777 return store_offset;
778 }
779
780
781 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
782 int load_offset;
783 if (!Assembler::is_simm16(offset)) {
784 // For offsets larger than a simm16 we setup the offset.
785 __ load_const_optimized(R0, offset);
786 load_offset = load(base, R0, to_reg, type, wide);
787 } else {
788 load_offset = code_offset();
789 switch(type) {
790 case T_BOOLEAN: // fall through
791 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
792 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
793 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
794 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
795 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
796 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
797 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
798 case T_ADDRESS:
799 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
800 __ lwz(to_reg->as_register(), offset, base);
801 __ decode_klass_not_null(to_reg->as_register());
802 } else {
803 __ ld(to_reg->as_register(), offset, base);
804 }
805 break;
806 case T_ARRAY : // fall through
807 case T_OBJECT:
808 {
809 if (UseCompressedOops && !wide) {
810 __ lwz(to_reg->as_register(), offset, base);
811 __ decode_heap_oop(to_reg->as_register());
812 } else {
813 __ ld(to_reg->as_register(), offset, base);
814 }
815 __ verify_oop(to_reg->as_register());
816 break;
817 }
818 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
819 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
820 default : ShouldNotReachHere();
821 }
822 }
823 return load_offset;
824 }
825
826
827 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
828 int load_offset = code_offset();
829 switch(type) {
830 case T_BOOLEAN: // fall through
831 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
832 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
833 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
834 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
835 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
836 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
837 case T_ARRAY : // fall through
838 case T_OBJECT:
839 {
840 if (UseCompressedOops && !wide) {
841 __ lwzx(to_reg->as_register(), base, disp);
842 __ decode_heap_oop(to_reg->as_register());
843 } else {
844 __ ldx(to_reg->as_register(), base, disp);
845 }
846 __ verify_oop(to_reg->as_register());
847 break;
848 }
849 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
850 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
851 case T_LONG :
852 #ifdef _LP64
853 __ ldx(to_reg->as_register_lo(), base, disp);
854 #else
855 Unimplemented();
856 #endif
857 break;
858 default : ShouldNotReachHere();
859 }
860 return load_offset;
861 }
862
863
864 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
865 LIR_Const* c = src->as_constant_ptr();
866 Register src_reg = R0;
867 switch (c->type()) {
868 case T_INT:
869 case T_FLOAT: {
870 int value = c->as_jint_bits();
871 __ load_const_optimized(src_reg, value);
872 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
873 __ stw(src_reg, addr.disp(), addr.base());
874 break;
875 }
876 case T_ADDRESS: {
877 int value = c->as_jint_bits();
878 __ load_const_optimized(src_reg, value);
879 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
880 __ std(src_reg, addr.disp(), addr.base());
881 break;
882 }
883 case T_OBJECT: {
884 jobject2reg(c->as_jobject(), src_reg);
885 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
886 __ std(src_reg, addr.disp(), addr.base());
887 break;
888 }
889 case T_LONG:
890 case T_DOUBLE: {
891 int value = c->as_jlong_bits();
892 __ load_const_optimized(src_reg, value);
893 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
894 __ std(src_reg, addr.disp(), addr.base());
895 break;
896 }
897 default:
898 Unimplemented();
899 }
900 }
901
902
903 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
904 LIR_Const* c = src->as_constant_ptr();
905 LIR_Address* addr = dest->as_address_ptr();
906 Register base = addr->base()->as_pointer_register();
907 LIR_Opr tmp = LIR_OprFact::illegalOpr;
908 int offset = -1;
909 // Null check for large offsets in LIRGenerator::do_StoreField.
910 bool needs_explicit_null_check = !ImplicitNullChecks;
911
912 if (info != NULL && needs_explicit_null_check) {
913 explicit_null_check(base, info);
914 }
915
916 switch (c->type()) {
917 case T_FLOAT: type = T_INT;
918 case T_INT:
919 case T_ADDRESS: {
920 tmp = FrameMap::R0_opr;
921 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
922 break;
923 }
924 case T_DOUBLE: type = T_LONG;
925 case T_LONG: {
926 tmp = FrameMap::R0_long_opr;
927 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
928 break;
929 }
930 case T_OBJECT: {
931 tmp = FrameMap::R0_opr;
932 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
933 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
934 __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
935 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
936 __ ori(R0, R0, oop_addr.value() & 0xffff);
937 } else {
938 jobject2reg(c->as_jobject(), R0);
939 }
940 break;
941 }
942 default:
943 Unimplemented();
944 }
945
946 // Handle either reg+reg or reg+disp address.
947 if (addr->index()->is_valid()) {
948 assert(addr->disp() == 0, "must be zero");
949 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
950 } else {
951 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
952 offset = store(tmp, base, addr->disp(), type, wide, false);
953 }
954
955 if (info != NULL) {
956 assert(offset != -1, "offset should've been set");
957 if (!needs_explicit_null_check) {
958 add_debug_info_for_null_check(offset, info);
959 }
960 }
961 }
962
963
964 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
965 LIR_Const* c = src->as_constant_ptr();
966 LIR_Opr to_reg = dest;
967
968 switch (c->type()) {
969 case T_INT: {
970 assert(patch_code == lir_patch_none, "no patching handled here");
971 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
972 break;
973 }
974 case T_ADDRESS: {
975 assert(patch_code == lir_patch_none, "no patching handled here");
976 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
977 break;
978 }
979 case T_LONG: {
980 assert(patch_code == lir_patch_none, "no patching handled here");
981 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
982 break;
983 }
984
985 case T_OBJECT: {
986 if (patch_code == lir_patch_none) {
987 jobject2reg(c->as_jobject(), to_reg->as_register());
988 } else {
989 jobject2reg_with_patching(to_reg->as_register(), info);
990 }
991 break;
992 }
993
994 case T_METADATA:
995 {
996 if (patch_code == lir_patch_none) {
997 metadata2reg(c->as_metadata(), to_reg->as_register());
998 } else {
999 klass2reg_with_patching(to_reg->as_register(), info);
1000 }
1001 }
1002 break;
1003
1004 case T_FLOAT:
1005 {
1006 if (to_reg->is_single_fpu()) {
1007 address const_addr = __ float_constant(c->as_jfloat());
1008 if (const_addr == NULL) {
1009 bailout("const section overflow");
1010 break;
1011 }
1012 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1013 __ relocate(rspec);
1014 __ load_const(R0, const_addr);
1015 __ lfsx(to_reg->as_float_reg(), R0);
1016 } else {
1017 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1018 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1019 }
1020 }
1021 break;
1022
1023 case T_DOUBLE:
1024 {
1025 if (to_reg->is_double_fpu()) {
1026 address const_addr = __ double_constant(c->as_jdouble());
1027 if (const_addr == NULL) {
1028 bailout("const section overflow");
1029 break;
1030 }
1031 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1032 __ relocate(rspec);
1033 __ load_const(R0, const_addr);
1034 __ lfdx(to_reg->as_double_reg(), R0);
1035 } else {
1036 assert(to_reg->is_double_cpu(), "Must be a long register.");
1037 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1038 }
1039 }
1040 break;
1041
1042 default:
1043 ShouldNotReachHere();
1044 }
1045 }
1046
1047
1048 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1049 Unimplemented(); return Address();
1050 }
1051
1052
1053 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1054 if (addr->index()->is_illegal()) {
1055 return (RegisterOrConstant)(addr->disp());
1056 } else {
1057 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1058 }
1059 }
1060
1061
1062 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1063 const Register tmp = R0;
1064 switch (type) {
1065 case T_INT:
1066 case T_FLOAT: {
1067 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1068 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1069 __ lwz(tmp, from.disp(), from.base());
1070 __ stw(tmp, to.disp(), to.base());
1071 break;
1072 }
1073 case T_ADDRESS:
1074 case T_OBJECT: {
1075 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1076 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1077 __ ld(tmp, from.disp(), from.base());
1078 __ std(tmp, to.disp(), to.base());
1079 break;
1080 }
1081 case T_LONG:
1082 case T_DOUBLE: {
1083 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1084 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1085 __ ld(tmp, from.disp(), from.base());
1086 __ std(tmp, to.disp(), to.base());
1087 break;
1088 }
1089
1090 default:
1091 ShouldNotReachHere();
1092 }
1093 }
1094
1095
1096 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1097 Unimplemented(); return Address();
1098 }
1099
1100
1101 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1102 Unimplemented(); return Address();
1103 }
1104
1105
1106 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1107 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1108
1109 assert(type != T_METADATA, "load of metadata ptr not supported");
1110 LIR_Address* addr = src_opr->as_address_ptr();
1111 LIR_Opr to_reg = dest;
1112
1113 Register src = addr->base()->as_pointer_register();
1114 Register disp_reg = noreg;
1115 int disp_value = addr->disp();
1116 bool needs_patching = (patch_code != lir_patch_none);
1117 // null check for large offsets in LIRGenerator::do_LoadField
1118 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1119
1120 if (info != NULL && needs_explicit_null_check) {
1121 explicit_null_check(src, info);
1122 }
1123
1124 if (addr->base()->type() == T_OBJECT) {
1125 __ verify_oop(src);
1126 }
1127
1128 PatchingStub* patch = NULL;
1129 if (needs_patching) {
1130 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1131 assert(!to_reg->is_double_cpu() ||
1132 patch_code == lir_patch_none ||
1133 patch_code == lir_patch_normal, "patching doesn't match register");
1134 }
1135
1136 if (addr->index()->is_illegal()) {
1137 if (!Assembler::is_simm16(disp_value)) {
1138 if (needs_patching) {
1139 __ load_const32(R0, 0); // patchable int
1140 } else {
1141 __ load_const_optimized(R0, disp_value);
1142 }
1143 disp_reg = R0;
1144 }
1145 } else {
1146 disp_reg = addr->index()->as_pointer_register();
1147 assert(disp_value == 0, "can't handle 3 operand addresses");
1148 }
1149
1150 // Remember the offset of the load. The patching_epilog must be done
1151 // before the call to add_debug_info, otherwise the PcDescs don't get
1152 // entered in increasing order.
1153 int offset;
1154
1155 if (disp_reg == noreg) {
1156 assert(Assembler::is_simm16(disp_value), "should have set this up");
1157 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1158 } else {
1159 assert(!unaligned, "unexpected");
1160 offset = load(src, disp_reg, to_reg, type, wide);
1161 }
1162
1163 if (patch != NULL) {
1164 patching_epilog(patch, patch_code, src, info);
1165 }
1166 if (info != NULL && !needs_explicit_null_check) {
1167 add_debug_info_for_null_check(offset, info);
1168 }
1169 }
1170
1171
1172 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1173 Address addr;
1174 if (src->is_single_word()) {
1175 addr = frame_map()->address_for_slot(src->single_stack_ix());
1176 } else if (src->is_double_word()) {
1177 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1178 }
1179
1180 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1181 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1182 }
1183
1184
1185 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1186 Address addr;
1187 if (dest->is_single_word()) {
1188 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1189 } else if (dest->is_double_word()) {
1190 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1191 }
1192 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1193 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1194 }
1195
1196
1197 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1198 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1199 if (from_reg->is_double_fpu()) {
1200 // double to double moves
1201 assert(to_reg->is_double_fpu(), "should match");
1202 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1203 } else {
1204 // float to float moves
1205 assert(to_reg->is_single_fpu(), "should match");
1206 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1207 }
1208 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1209 if (from_reg->is_double_cpu()) {
1210 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1211 } else if (to_reg->is_double_cpu()) {
1212 // int to int moves
1213 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1214 } else {
1215 // int to int moves
1216 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1217 }
1218 } else {
1219 ShouldNotReachHere();
1220 }
1221 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1222 __ verify_oop(to_reg->as_register());
1223 }
1224 }
1225
1226
1227 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1228 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1229 bool wide, bool unaligned) {
1230 assert(type != T_METADATA, "store of metadata ptr not supported");
1231 LIR_Address* addr = dest->as_address_ptr();
1232
1233 Register src = addr->base()->as_pointer_register();
1234 Register disp_reg = noreg;
1235 int disp_value = addr->disp();
1236 bool needs_patching = (patch_code != lir_patch_none);
1237 bool compress_oop = (type == T_ARRAY || type == T_OBJECT) && UseCompressedOops && !wide &&
1238 Universe::narrow_oop_mode() != Universe::UnscaledNarrowOop;
1239 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1240 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1241 // Null check for large offsets in LIRGenerator::do_StoreField.
1242 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1243
1244 if (info != NULL && needs_explicit_null_check) {
1245 explicit_null_check(src, info);
1246 }
1247
1248 if (addr->base()->is_oop_register()) {
1249 __ verify_oop(src);
1250 }
1251
1252 PatchingStub* patch = NULL;
1253 if (needs_patching) {
1254 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1255 assert(!from_reg->is_double_cpu() ||
1256 patch_code == lir_patch_none ||
1257 patch_code == lir_patch_normal, "patching doesn't match register");
1258 }
1259
1260 if (addr->index()->is_illegal()) {
1261 if (load_disp) {
1262 disp_reg = use_R29 ? R29_TOC : R0;
1263 if (needs_patching) {
1264 __ load_const32(disp_reg, 0); // patchable int
1265 } else {
1266 __ load_const_optimized(disp_reg, disp_value);
1267 }
1268 }
1269 } else {
1270 disp_reg = addr->index()->as_pointer_register();
1271 assert(disp_value == 0, "can't handle 3 operand addresses");
1272 }
1273
1274 // remember the offset of the store. The patching_epilog must be done
1275 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1276 // entered in increasing order.
1277 int offset;
1278
1279 if (compress_oop) {
1280 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1281 from_reg = FrameMap::as_opr(co);
1282 }
1283
1284 if (disp_reg == noreg) {
1285 assert(Assembler::is_simm16(disp_value), "should have set this up");
1286 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1287 } else {
1288 assert(!unaligned, "unexpected");
1289 offset = store(from_reg, src, disp_reg, type, wide);
1290 }
1291
1292 if (use_R29) {
1293 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1294 }
1295
1296 if (patch != NULL) {
1297 patching_epilog(patch, patch_code, src, info);
1298 }
1299
1300 if (info != NULL && !needs_explicit_null_check) {
1301 add_debug_info_for_null_check(offset, info);
1302 }
1303 }
1304
1305
1306 void LIR_Assembler::return_op(LIR_Opr result) {
1307 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1308 const Register polling_page = R12;
1309
1310 // Pop the stack before the safepoint code.
1311 int frame_size = initial_frame_size_in_bytes();
1312 if (Assembler::is_simm(frame_size, 16)) {
1313 __ addi(R1_SP, R1_SP, frame_size);
1314 } else {
1315 __ pop_frame();
1316 }
1317
1318 if (SafepointMechanism::uses_thread_local_poll()) {
1319 __ ld(polling_page, in_bytes(Thread::polling_page_offset()), R16_thread);
1320 } else {
1321 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0);
1322 }
1323
1324 // Restore return pc relative to callers' sp.
1325 __ ld(return_pc, _abi(lr), R1_SP);
1326 // Move return pc to LR.
1327 __ mtlr(return_pc);
1328
1329 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1330 __ reserved_stack_check(return_pc);
1331 }
1332
1333 // We need to mark the code position where the load from the safepoint
1334 // polling page was emitted as relocInfo::poll_return_type here.
1335 __ relocate(relocInfo::poll_return_type);
1336 __ load_from_polling_page(polling_page);
1337
1338 // Return.
1339 __ blr();
1340 }
1341
1342
1343 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1344 const Register poll_addr = tmp->as_register();
1345 if (SafepointMechanism::uses_thread_local_poll()) {
1346 __ ld(poll_addr, in_bytes(Thread::polling_page_offset()), R16_thread);
1347 } else {
1348 __ load_const_optimized(poll_addr, (intptr_t)os::get_polling_page(), R0);
1349 }
1350 if (info != NULL) {
1351 add_debug_info_for_branch(info);
1352 }
1353 int offset = __ offset();
1354 __ relocate(relocInfo::poll_type);
1355 __ load_from_polling_page(poll_addr);
1356
1357 return offset;
1358 }
1359
1360
1361 void LIR_Assembler::emit_static_call_stub() {
1362 address call_pc = __ pc();
1363 address stub = __ start_a_stub(static_call_stub_size());
1364 if (stub == NULL) {
1365 bailout("static call stub overflow");
1366 return;
1367 }
1368
1369 // For java_to_interp stubs we use R11_scratch1 as scratch register
1370 // and in call trampoline stubs we use R12_scratch2. This way we
1371 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1372 const Register reg_scratch = R11_scratch1;
1373
1374 // Create a static stub relocation which relates this stub
1375 // with the call instruction at insts_call_instruction_offset in the
1376 // instructions code-section.
1377 int start = __ offset();
1378 __ relocate(static_stub_Relocation::spec(call_pc));
1379
1380 // Now, create the stub's code:
1381 // - load the TOC
1382 // - load the inline cache oop from the constant pool
1383 // - load the call target from the constant pool
1384 // - call
1385 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1386 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1387 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1388
1389 if (ReoptimizeCallSequences) {
1390 __ b64_patchable((address)-1, relocInfo::none);
1391 } else {
1392 AddressLiteral a((address)-1);
1393 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1394 __ mtctr(reg_scratch);
1395 __ bctr();
1396 }
1397 if (!success) {
1398 bailout("const section overflow");
1399 return;
1400 }
1401
1402 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1403 __ end_a_stub();
1404 }
1405
1406
1407 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1408 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1409 if (opr1->is_single_fpu()) {
1410 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1411 } else if (opr1->is_double_fpu()) {
1412 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1413 } else if (opr1->is_single_cpu()) {
1414 if (opr2->is_constant()) {
1415 switch (opr2->as_constant_ptr()->type()) {
1416 case T_INT:
1417 {
1418 jint con = opr2->as_constant_ptr()->as_jint();
1419 if (unsigned_comp) {
1420 if (Assembler::is_uimm(con, 16)) {
1421 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1422 } else {
1423 __ load_const_optimized(R0, con);
1424 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1425 }
1426 } else {
1427 if (Assembler::is_simm(con, 16)) {
1428 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1429 } else {
1430 __ load_const_optimized(R0, con);
1431 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1432 }
1433 }
1434 }
1435 break;
1436
1437 case T_OBJECT:
1438 // There are only equal/notequal comparisons on objects.
1439 {
1440 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1441 jobject con = opr2->as_constant_ptr()->as_jobject();
1442 if (con == NULL) {
1443 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1444 } else {
1445 jobject2reg(con, R0);
1446 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1447 }
1448 }
1449 break;
1450
1451 default:
1452 ShouldNotReachHere();
1453 break;
1454 }
1455 } else {
1456 if (opr2->is_address()) {
1457 DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment.
1458 LIR_Address *addr = opr2->as_address_ptr();
1459 BasicType type = addr->type();
1460 if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); }
1461 else { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); }
1462 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1463 } else {
1464 if (unsigned_comp) {
1465 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1466 } else {
1467 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1468 }
1469 }
1470 }
1471 } else if (opr1->is_double_cpu()) {
1472 if (opr2->is_constant()) {
1473 jlong con = opr2->as_constant_ptr()->as_jlong();
1474 if (unsigned_comp) {
1475 if (Assembler::is_uimm(con, 16)) {
1476 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1477 } else {
1478 __ load_const_optimized(R0, con);
1479 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1480 }
1481 } else {
1482 if (Assembler::is_simm(con, 16)) {
1483 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1484 } else {
1485 __ load_const_optimized(R0, con);
1486 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1487 }
1488 }
1489 } else if (opr2->is_register()) {
1490 if (unsigned_comp) {
1491 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1492 } else {
1493 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1494 }
1495 } else {
1496 ShouldNotReachHere();
1497 }
1498 } else if (opr1->is_address()) {
1499 DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment.
1500 LIR_Address * addr = opr1->as_address_ptr();
1501 BasicType type = addr->type();
1502 assert (opr2->is_constant(), "Checking");
1503 if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); }
1504 else { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); }
1505 __ cmpdi(BOOL_RESULT, R0, opr2->as_constant_ptr()->as_jint());
1506 } else {
1507 ShouldNotReachHere();
1508 }
1509 }
1510
1511
1512 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1513 const Register Rdst = dst->as_register();
1514 Label done;
1515 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1516 bool is_unordered_less = (code == lir_ucmp_fd2i);
1517 if (left->is_single_fpu()) {
1518 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1519 } else if (left->is_double_fpu()) {
1520 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1521 } else {
1522 ShouldNotReachHere();
1523 }
1524 __ li(Rdst, is_unordered_less ? -1 : 1);
1525 __ bso(CCR0, done);
1526 } else if (code == lir_cmp_l2i) {
1527 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1528 } else {
1529 ShouldNotReachHere();
1530 }
1531 __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01
1532 __ srwi(Rdst, R0, 30);
1533 __ srawi(R0, R0, 31);
1534 __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1
1535 __ bind(done);
1536 }
1537
1538
1539 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1540 if (src->is_constant()) {
1541 lasm->const2reg(src, dst, lir_patch_none, NULL);
1542 } else if (src->is_register()) {
1543 lasm->reg2reg(src, dst);
1544 } else if (src->is_stack()) {
1545 lasm->stack2reg(src, dst, dst->type());
1546 } else {
1547 ShouldNotReachHere();
1548 }
1549 }
1550
1551
1552 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1553 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1554 load_to_reg(this, opr1, result); // Condition doesn't matter.
1555 return;
1556 }
1557
1558 bool positive = false;
1559 Assembler::Condition cond = Assembler::equal;
1560 switch (condition) {
1561 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1562 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1563 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1564 case lir_cond_belowEqual:
1565 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1566 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1567 case lir_cond_aboveEqual:
1568 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1569 default: ShouldNotReachHere();
1570 }
1571
1572 // Try to use isel on >=Power7.
1573 if (VM_Version::has_isel() && result->is_cpu_register()) {
1574 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1575 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1576
1577 // We can use result_reg to load one operand if not already in register.
1578 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1579 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1580
1581 if (first != second) {
1582 if (!o1_is_reg) {
1583 load_to_reg(this, opr1, result);
1584 }
1585
1586 if (!o2_is_reg) {
1587 load_to_reg(this, opr2, result);
1588 }
1589
1590 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1591 return;
1592 }
1593 } // isel
1594
1595 load_to_reg(this, opr1, result);
1596
1597 Label skip;
1598 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1599 int bi = Assembler::bi0(BOOL_RESULT, cond);
1600 __ bc(bo, bi, skip);
1601
1602 load_to_reg(this, opr2, result);
1603 __ bind(skip);
1604 }
1605
1606
1607 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1608 CodeEmitInfo* info, bool pop_fpu_stack) {
1609 assert(info == NULL, "unused on this code path");
1610 assert(left->is_register(), "wrong items state");
1611 assert(dest->is_register(), "wrong items state");
1612
1613 if (right->is_register()) {
1614 if (dest->is_float_kind()) {
1615
1616 FloatRegister lreg, rreg, res;
1617 if (right->is_single_fpu()) {
1618 lreg = left->as_float_reg();
1619 rreg = right->as_float_reg();
1620 res = dest->as_float_reg();
1621 switch (code) {
1622 case lir_add: __ fadds(res, lreg, rreg); break;
1623 case lir_sub: __ fsubs(res, lreg, rreg); break;
1624 case lir_mul: // fall through
1625 case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break;
1626 case lir_div: // fall through
1627 case lir_div_strictfp: __ fdivs(res, lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630 } else {
1631 lreg = left->as_double_reg();
1632 rreg = right->as_double_reg();
1633 res = dest->as_double_reg();
1634 switch (code) {
1635 case lir_add: __ fadd(res, lreg, rreg); break;
1636 case lir_sub: __ fsub(res, lreg, rreg); break;
1637 case lir_mul: // fall through
1638 case lir_mul_strictfp: __ fmul(res, lreg, rreg); break;
1639 case lir_div: // fall through
1640 case lir_div_strictfp: __ fdiv(res, lreg, rreg); break;
1641 default: ShouldNotReachHere();
1642 }
1643 }
1644
1645 } else if (dest->is_double_cpu()) {
1646
1647 Register dst_lo = dest->as_register_lo();
1648 Register op1_lo = left->as_pointer_register();
1649 Register op2_lo = right->as_pointer_register();
1650
1651 switch (code) {
1652 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1653 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1654 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1655 default: ShouldNotReachHere();
1656 }
1657 } else {
1658 assert (right->is_single_cpu(), "Just Checking");
1659
1660 Register lreg = left->as_register();
1661 Register res = dest->as_register();
1662 Register rreg = right->as_register();
1663 switch (code) {
1664 case lir_add: __ add (res, lreg, rreg); break;
1665 case lir_sub: __ sub (res, lreg, rreg); break;
1666 case lir_mul: __ mullw(res, lreg, rreg); break;
1667 default: ShouldNotReachHere();
1668 }
1669 }
1670 } else {
1671 assert (right->is_constant(), "must be constant");
1672
1673 if (dest->is_single_cpu()) {
1674 Register lreg = left->as_register();
1675 Register res = dest->as_register();
1676 int simm16 = right->as_constant_ptr()->as_jint();
1677
1678 switch (code) {
1679 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1680 simm16 = -simm16;
1681 case lir_add: if (res == lreg && simm16 == 0) break;
1682 __ addi(res, lreg, simm16); break;
1683 case lir_mul: if (res == lreg && simm16 == 1) break;
1684 __ mulli(res, lreg, simm16); break;
1685 default: ShouldNotReachHere();
1686 }
1687 } else {
1688 Register lreg = left->as_pointer_register();
1689 Register res = dest->as_register_lo();
1690 long con = right->as_constant_ptr()->as_jlong();
1691 assert(Assembler::is_simm16(con), "must be simm16");
1692
1693 switch (code) {
1694 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1695 con = -con;
1696 case lir_add: if (res == lreg && con == 0) break;
1697 __ addi(res, lreg, (int)con); break;
1698 case lir_mul: if (res == lreg && con == 1) break;
1699 __ mulli(res, lreg, (int)con); break;
1700 default: ShouldNotReachHere();
1701 }
1702 }
1703 }
1704 }
1705
1706
1707 void LIR_Assembler::fpop() {
1708 Unimplemented();
1709 // do nothing
1710 }
1711
1712
1713 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1714 switch (code) {
1715 case lir_sqrt: {
1716 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1717 break;
1718 }
1719 case lir_abs: {
1720 __ fabs(dest->as_double_reg(), value->as_double_reg());
1721 break;
1722 }
1723 default: {
1724 ShouldNotReachHere();
1725 break;
1726 }
1727 }
1728 }
1729
1730
1731 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1732 if (right->is_constant()) { // see do_LogicOp
1733 long uimm;
1734 Register d, l;
1735 if (dest->is_single_cpu()) {
1736 uimm = right->as_constant_ptr()->as_jint();
1737 d = dest->as_register();
1738 l = left->as_register();
1739 } else {
1740 uimm = right->as_constant_ptr()->as_jlong();
1741 d = dest->as_register_lo();
1742 l = left->as_register_lo();
1743 }
1744 long uimms = (unsigned long)uimm >> 16,
1745 uimmss = (unsigned long)uimm >> 32;
1746
1747 switch (code) {
1748 case lir_logic_and:
1749 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) {
1750 __ andi(d, l, uimm); // special cases
1751 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1752 else { __ andi_(d, l, uimm); }
1753 break;
1754
1755 case lir_logic_or:
1756 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1757 else { __ ori(d, l, uimm); }
1758 break;
1759
1760 case lir_logic_xor:
1761 if (uimm == -1) { __ nand(d, l, l); } // special case
1762 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1763 else { __ xori(d, l, uimm); }
1764 break;
1765
1766 default: ShouldNotReachHere();
1767 }
1768 } else {
1769 assert(right->is_register(), "right should be in register");
1770
1771 if (dest->is_single_cpu()) {
1772 switch (code) {
1773 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1774 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1775 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1776 default: ShouldNotReachHere();
1777 }
1778 } else {
1779 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1780 left->as_register_lo();
1781 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1782 right->as_register_lo();
1783
1784 switch (code) {
1785 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1786 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1787 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1788 default: ShouldNotReachHere();
1789 }
1790 }
1791 }
1792 }
1793
1794
1795 int LIR_Assembler::shift_amount(BasicType t) {
1796 int elem_size = type2aelembytes(t);
1797 switch (elem_size) {
1798 case 1 : return 0;
1799 case 2 : return 1;
1800 case 4 : return 2;
1801 case 8 : return 3;
1802 }
1803 ShouldNotReachHere();
1804 return -1;
1805 }
1806
1807
1808 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1809 info->add_register_oop(exceptionOop);
1810
1811 // Reuse the debug info from the safepoint poll for the throw op itself.
1812 address pc_for_athrow = __ pc();
1813 int pc_for_athrow_offset = __ offset();
1814 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1815 //__ relocate(rspec);
1816 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1817 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1818 add_call_info(pc_for_athrow_offset, info); // for exception handler
1819
1820 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1821 : Runtime1::handle_exception_nofpu_id);
1822 //__ load_const_optimized(R0, stub);
1823 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1824 __ mtctr(R0);
1825 __ bctr();
1826 }
1827
1828
1829 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1830 // Note: Not used with EnableDebuggingOnDemand.
1831 assert(exceptionOop->as_register() == R3, "should match");
1832 __ b(_unwind_handler_entry);
1833 }
1834
1835
1836 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1837 Register src = op->src()->as_register();
1838 Register dst = op->dst()->as_register();
1839 Register src_pos = op->src_pos()->as_register();
1840 Register dst_pos = op->dst_pos()->as_register();
1841 Register length = op->length()->as_register();
1842 Register tmp = op->tmp()->as_register();
1843 Register tmp2 = R0;
1844
1845 int flags = op->flags();
1846 ciArrayKlass* default_type = op->expected_type();
1847 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1848 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1849
1850 // Set up the arraycopy stub information.
1851 ArrayCopyStub* stub = op->stub();
1852 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1853
1854 // Always do stub if no type information is available. It's ok if
1855 // the known type isn't loaded since the code sanity checks
1856 // in debug mode and the type isn't required when we know the exact type
1857 // also check that the type is an array type.
1858 if (op->expected_type() == NULL) {
1859 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1860 length->is_nonvolatile(), "must preserve");
1861 address copyfunc_addr = StubRoutines::generic_arraycopy();
1862 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1863
1864 // 3 parms are int. Convert to long.
1865 __ mr(R3_ARG1, src);
1866 __ extsw(R4_ARG2, src_pos);
1867 __ mr(R5_ARG3, dst);
1868 __ extsw(R6_ARG4, dst_pos);
1869 __ extsw(R7_ARG5, length);
1870
1871 #ifndef PRODUCT
1872 if (PrintC1Statistics) {
1873 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1874 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1875 __ lwz(R11_scratch1, simm16_offs, tmp);
1876 __ addi(R11_scratch1, R11_scratch1, 1);
1877 __ stw(R11_scratch1, simm16_offs, tmp);
1878 }
1879 #endif
1880 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1881
1882 __ nand(tmp, R3_RET, R3_RET);
1883 __ subf(length, tmp, length);
1884 __ add(src_pos, tmp, src_pos);
1885 __ add(dst_pos, tmp, dst_pos);
1886
1887 __ cmpwi(CCR0, R3_RET, 0);
1888 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1889 __ bind(*stub->continuation());
1890 return;
1891 }
1892
1893 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1894 Label cont, slow, copyfunc;
1895
1896 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1897 LIR_OpArrayCopy::dst_null_check |
1898 LIR_OpArrayCopy::src_pos_positive_check |
1899 LIR_OpArrayCopy::dst_pos_positive_check |
1900 LIR_OpArrayCopy::length_positive_check);
1901
1902 // Use only one conditional branch for simple checks.
1903 if (simple_check_flag_set) {
1904 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1905
1906 // Make sure src and dst are non-null.
1907 if (flags & LIR_OpArrayCopy::src_null_check) {
1908 __ cmpdi(combined_check, src, 0);
1909 tmp_check = CCR0;
1910 }
1911
1912 if (flags & LIR_OpArrayCopy::dst_null_check) {
1913 __ cmpdi(tmp_check, dst, 0);
1914 if (tmp_check != combined_check) {
1915 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1916 }
1917 tmp_check = CCR0;
1918 }
1919
1920 // Clear combined_check.eq if not already used.
1921 if (tmp_check == combined_check) {
1922 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1923 tmp_check = CCR0;
1924 }
1925
1926 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1927 // Test src_pos register.
1928 __ cmpwi(tmp_check, src_pos, 0);
1929 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1930 }
1931
1932 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1933 // Test dst_pos register.
1934 __ cmpwi(tmp_check, dst_pos, 0);
1935 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1936 }
1937
1938 if (flags & LIR_OpArrayCopy::length_positive_check) {
1939 // Make sure length isn't negative.
1940 __ cmpwi(tmp_check, length, 0);
1941 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1942 }
1943
1944 __ beq(combined_check, slow);
1945 }
1946
1947 // If the compiler was not able to prove that exact type of the source or the destination
1948 // of the arraycopy is an array type, check at runtime if the source or the destination is
1949 // an instance type.
1950 if (flags & LIR_OpArrayCopy::type_check) {
1951 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1952 __ load_klass(tmp, dst);
1953 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1954 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1955 __ bge(CCR0, slow);
1956 }
1957
1958 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1959 __ load_klass(tmp, src);
1960 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1961 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1962 __ bge(CCR0, slow);
1963 }
1964 }
1965
1966 // Higher 32bits must be null.
1967 __ extsw(length, length);
1968
1969 __ extsw(src_pos, src_pos);
1970 if (flags & LIR_OpArrayCopy::src_range_check) {
1971 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1972 __ add(tmp, length, src_pos);
1973 __ cmpld(CCR0, tmp2, tmp);
1974 __ ble(CCR0, slow);
1975 }
1976
1977 __ extsw(dst_pos, dst_pos);
1978 if (flags & LIR_OpArrayCopy::dst_range_check) {
1979 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1980 __ add(tmp, length, dst_pos);
1981 __ cmpld(CCR0, tmp2, tmp);
1982 __ ble(CCR0, slow);
1983 }
1984
1985 int shift = shift_amount(basic_type);
1986
1987 if (!(flags & LIR_OpArrayCopy::type_check)) {
1988 __ b(cont);
1989 } else {
1990 // We don't know the array types are compatible.
1991 if (basic_type != T_OBJECT) {
1992 // Simple test for basic type arrays.
1993 if (UseCompressedClassPointers) {
1994 // We don't need decode because we just need to compare.
1995 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1996 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1997 __ cmpw(CCR0, tmp, tmp2);
1998 } else {
1999 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
2000 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2001 __ cmpd(CCR0, tmp, tmp2);
2002 }
2003 __ beq(CCR0, cont);
2004 } else {
2005 // For object arrays, if src is a sub class of dst then we can
2006 // safely do the copy.
2007 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2008
2009 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2010 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2011
2012 __ load_klass(sub_klass, src);
2013 __ load_klass(super_klass, dst);
2014
2015 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2016 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
2017
2018 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2019 //__ load_const_optimized(tmp, slow_stc, tmp2);
2020 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2021 __ mtctr(tmp);
2022 __ bctrl(); // sets CR0
2023 __ beq(CCR0, cont);
2024
2025 if (copyfunc_addr != NULL) { // Use stub if available.
2026 __ bind(copyfunc);
2027 // Src is not a sub class of dst so we have to do a
2028 // per-element check.
2029 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2030 if ((flags & mask) != mask) {
2031 assert(flags & mask, "one of the two should be known to be an object array");
2032
2033 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2034 __ load_klass(tmp, src);
2035 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2036 __ load_klass(tmp, dst);
2037 }
2038
2039 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2040
2041 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2042 __ load_const_optimized(tmp, objArray_lh);
2043 __ cmpw(CCR0, tmp, tmp2);
2044 __ bne(CCR0, slow);
2045 }
2046
2047 Register src_ptr = R3_ARG1;
2048 Register dst_ptr = R4_ARG2;
2049 Register len = R5_ARG3;
2050 Register chk_off = R6_ARG4;
2051 Register super_k = R7_ARG5;
2052
2053 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2054 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2055 if (shift == 0) {
2056 __ add(src_ptr, src_pos, src_ptr);
2057 __ add(dst_ptr, dst_pos, dst_ptr);
2058 } else {
2059 __ sldi(tmp, src_pos, shift);
2060 __ sldi(tmp2, dst_pos, shift);
2061 __ add(src_ptr, tmp, src_ptr);
2062 __ add(dst_ptr, tmp2, dst_ptr);
2063 }
2064
2065 __ load_klass(tmp, dst);
2066 __ mr(len, length);
2067
2068 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2069 __ ld(super_k, ek_offset, tmp);
2070
2071 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2072 __ lwz(chk_off, sco_offset, super_k);
2073
2074 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2075
2076 #ifndef PRODUCT
2077 if (PrintC1Statistics) {
2078 Label failed;
2079 __ cmpwi(CCR0, R3_RET, 0);
2080 __ bne(CCR0, failed);
2081 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2082 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2083 __ lwz(R11_scratch1, simm16_offs, tmp);
2084 __ addi(R11_scratch1, R11_scratch1, 1);
2085 __ stw(R11_scratch1, simm16_offs, tmp);
2086 __ bind(failed);
2087 }
2088 #endif
2089
2090 __ nand(tmp, R3_RET, R3_RET);
2091 __ cmpwi(CCR0, R3_RET, 0);
2092 __ beq(CCR0, *stub->continuation());
2093
2094 #ifndef PRODUCT
2095 if (PrintC1Statistics) {
2096 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2097 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2098 __ lwz(R11_scratch1, simm16_offs, tmp);
2099 __ addi(R11_scratch1, R11_scratch1, 1);
2100 __ stw(R11_scratch1, simm16_offs, tmp);
2101 }
2102 #endif
2103
2104 __ subf(length, tmp, length);
2105 __ add(src_pos, tmp, src_pos);
2106 __ add(dst_pos, tmp, dst_pos);
2107 }
2108 }
2109 }
2110 __ bind(slow);
2111 __ b(*stub->entry());
2112 __ bind(cont);
2113
2114 #ifdef ASSERT
2115 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2116 // Sanity check the known type with the incoming class. For the
2117 // primitive case the types must match exactly with src.klass and
2118 // dst.klass each exactly matching the default type. For the
2119 // object array case, if no type check is needed then either the
2120 // dst type is exactly the expected type and the src type is a
2121 // subtype which we can't check or src is the same array as dst
2122 // but not necessarily exactly of type default_type.
2123 Label known_ok, halt;
2124 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2125 if (UseCompressedClassPointers) {
2126 // Tmp holds the default type. It currently comes uncompressed after the
2127 // load of a constant, so encode it.
2128 __ encode_klass_not_null(tmp);
2129 // Load the raw value of the dst klass, since we will be comparing
2130 // uncompressed values directly.
2131 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2132 __ cmpw(CCR0, tmp, tmp2);
2133 if (basic_type != T_OBJECT) {
2134 __ bne(CCR0, halt);
2135 // Load the raw value of the src klass.
2136 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2137 __ cmpw(CCR0, tmp, tmp2);
2138 __ beq(CCR0, known_ok);
2139 } else {
2140 __ beq(CCR0, known_ok);
2141 __ cmpw(CCR0, src, dst);
2142 __ beq(CCR0, known_ok);
2143 }
2144 } else {
2145 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2146 __ cmpd(CCR0, tmp, tmp2);
2147 if (basic_type != T_OBJECT) {
2148 __ bne(CCR0, halt);
2149 // Load the raw value of the src klass.
2150 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2151 __ cmpd(CCR0, tmp, tmp2);
2152 __ beq(CCR0, known_ok);
2153 } else {
2154 __ beq(CCR0, known_ok);
2155 __ cmpd(CCR0, src, dst);
2156 __ beq(CCR0, known_ok);
2157 }
2158 }
2159 __ bind(halt);
2160 __ stop("incorrect type information in arraycopy");
2161 __ bind(known_ok);
2162 }
2163 #endif
2164
2165 #ifndef PRODUCT
2166 if (PrintC1Statistics) {
2167 address counter = Runtime1::arraycopy_count_address(basic_type);
2168 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2169 __ lwz(R11_scratch1, simm16_offs, tmp);
2170 __ addi(R11_scratch1, R11_scratch1, 1);
2171 __ stw(R11_scratch1, simm16_offs, tmp);
2172 }
2173 #endif
2174
2175 Register src_ptr = R3_ARG1;
2176 Register dst_ptr = R4_ARG2;
2177 Register len = R5_ARG3;
2178
2179 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2180 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2181 if (shift == 0) {
2182 __ add(src_ptr, src_pos, src_ptr);
2183 __ add(dst_ptr, dst_pos, dst_ptr);
2184 } else {
2185 __ sldi(tmp, src_pos, shift);
2186 __ sldi(tmp2, dst_pos, shift);
2187 __ add(src_ptr, tmp, src_ptr);
2188 __ add(dst_ptr, tmp2, dst_ptr);
2189 }
2190
2191 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2192 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2193 const char *name;
2194 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2195
2196 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2197 __ mr(len, length);
2198 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2199
2200 __ bind(*stub->continuation());
2201 }
2202
2203
2204 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2205 if (dest->is_single_cpu()) {
2206 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2207 #ifdef _LP64
2208 if (left->type() == T_OBJECT) {
2209 switch (code) {
2210 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2211 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2212 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2213 default: ShouldNotReachHere();
2214 }
2215 } else
2216 #endif
2217 switch (code) {
2218 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2219 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2220 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2221 default: ShouldNotReachHere();
2222 }
2223 } else {
2224 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2225 switch (code) {
2226 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2227 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2228 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2229 default: ShouldNotReachHere();
2230 }
2231 }
2232 }
2233
2234
2235 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2236 #ifdef _LP64
2237 if (left->type() == T_OBJECT) {
2238 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2239 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2240 else {
2241 switch (code) {
2242 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2243 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2244 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2245 default: ShouldNotReachHere();
2246 }
2247 }
2248 return;
2249 }
2250 #endif
2251
2252 if (dest->is_single_cpu()) {
2253 count = count & 0x1F; // Java spec
2254 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2255 else {
2256 switch (code) {
2257 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2258 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2259 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2260 default: ShouldNotReachHere();
2261 }
2262 }
2263 } else if (dest->is_double_cpu()) {
2264 count = count & 63; // Java spec
2265 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2266 else {
2267 switch (code) {
2268 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2269 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2270 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2271 default: ShouldNotReachHere();
2272 }
2273 }
2274 } else {
2275 ShouldNotReachHere();
2276 }
2277 }
2278
2279
2280 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2281 if (op->init_check()) {
2282 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2283 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2284 } else {
2285 add_debug_info_for_null_check_here(op->stub()->info());
2286 }
2287 __ lbz(op->tmp1()->as_register(),
2288 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2289 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2290 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2291 }
2292 __ allocate_object(op->obj()->as_register(),
2293 op->tmp1()->as_register(),
2294 op->tmp2()->as_register(),
2295 op->tmp3()->as_register(),
2296 op->header_size(),
2297 op->object_size(),
2298 op->klass()->as_register(),
2299 *op->stub()->entry());
2300
2301 __ bind(*op->stub()->continuation());
2302 __ verify_oop(op->obj()->as_register());
2303 }
2304
2305
2306 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2307 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2308 if (UseSlowPath ||
2309 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2310 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2311 __ b(*op->stub()->entry());
2312 } else {
2313 __ allocate_array(op->obj()->as_register(),
2314 op->len()->as_register(),
2315 op->tmp1()->as_register(),
2316 op->tmp2()->as_register(),
2317 op->tmp3()->as_register(),
2318 arrayOopDesc::header_size(op->type()),
2319 type2aelembytes(op->type()),
2320 op->klass()->as_register(),
2321 *op->stub()->entry());
2322 }
2323 __ bind(*op->stub()->continuation());
2324 }
2325
2326
2327 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2328 ciMethodData *md, ciProfileData *data,
2329 Register recv, Register tmp1, Label* update_done) {
2330 uint i;
2331 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2332 Label next_test;
2333 // See if the receiver is receiver[n].
2334 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2335 __ verify_klass_ptr(tmp1);
2336 __ cmpd(CCR0, recv, tmp1);
2337 __ bne(CCR0, next_test);
2338
2339 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2340 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2341 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2342 __ b(*update_done);
2343
2344 __ bind(next_test);
2345 }
2346
2347 // Didn't find receiver; find next empty slot and fill it in.
2348 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2349 Label next_test;
2350 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2351 __ cmpdi(CCR0, tmp1, 0);
2352 __ bne(CCR0, next_test);
2353 __ li(tmp1, DataLayout::counter_increment);
2354 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2355 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2356 __ b(*update_done);
2357
2358 __ bind(next_test);
2359 }
2360 }
2361
2362
2363 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2364 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2365 md = method->method_data_or_null();
2366 assert(md != NULL, "Sanity");
2367 data = md->bci_to_data(bci);
2368 assert(data != NULL, "need data for checkcast");
2369 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2370 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2371 // The offset is large so bias the mdo by the base of the slot so
2372 // that the ld can use simm16s to reference the slots of the data.
2373 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2374 }
2375 }
2376
2377
2378 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2379 Register obj = op->object()->as_register();
2380 Register k_RInfo = op->tmp1()->as_register();
2381 Register klass_RInfo = op->tmp2()->as_register();
2382 Register Rtmp1 = op->tmp3()->as_register();
2383 Register dst = op->result_opr()->as_register();
2384 ciKlass* k = op->klass();
2385 bool should_profile = op->should_profile();
2386 bool move_obj_to_dst = (op->code() == lir_checkcast);
2387 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2388 bool reg_conflict = (obj == k_RInfo || obj == klass_RInfo || obj == Rtmp1);
2389 bool restore_obj = move_obj_to_dst && reg_conflict;
2390
2391 __ cmpdi(CCR0, obj, 0);
2392 if (move_obj_to_dst || reg_conflict) {
2393 __ mr_if_needed(dst, obj);
2394 if (reg_conflict) { obj = dst; }
2395 }
2396
2397 ciMethodData* md;
2398 ciProfileData* data;
2399 int mdo_offset_bias = 0;
2400 if (should_profile) {
2401 ciMethod* method = op->profiled_method();
2402 assert(method != NULL, "Should have method");
2403 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2404
2405 Register mdo = k_RInfo;
2406 Register data_val = Rtmp1;
2407 Label not_null;
2408 __ bne(CCR0, not_null);
2409 metadata2reg(md->constant_encoding(), mdo);
2410 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2411 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2412 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2413 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2414 __ b(*obj_is_null);
2415 __ bind(not_null);
2416 } else {
2417 __ beq(CCR0, *obj_is_null);
2418 }
2419
2420 // get object class
2421 __ load_klass(klass_RInfo, obj);
2422
2423 if (k->is_loaded()) {
2424 metadata2reg(k->constant_encoding(), k_RInfo);
2425 } else {
2426 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2427 }
2428
2429 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2430 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2431 Label *success_target = should_profile ? &profile_cast_success : success;
2432
2433 if (op->fast_check()) {
2434 assert_different_registers(klass_RInfo, k_RInfo);
2435 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2436 if (should_profile) {
2437 __ bne(CCR0, *failure_target);
2438 // Fall through to success case.
2439 } else {
2440 __ beq(CCR0, *success);
2441 // Fall through to failure case.
2442 }
2443 } else {
2444 bool need_slow_path = true;
2445 if (k->is_loaded()) {
2446 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2447 need_slow_path = false;
2448 }
2449 // Perform the fast part of the checking logic.
2450 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2451 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2452 } else {
2453 // Perform the fast part of the checking logic.
2454 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2455 }
2456 if (!need_slow_path) {
2457 if (!should_profile) { __ b(*success); }
2458 } else {
2459 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2460 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2461 //__ load_const_optimized(Rtmp1, entry, R0);
2462 __ calculate_address_from_global_toc(Rtmp1, entry, true, true, false);
2463 __ mtctr(Rtmp1);
2464 __ bctrl(); // sets CR0
2465 if (should_profile) {
2466 __ bne(CCR0, *failure_target);
2467 // Fall through to success case.
2468 } else {
2469 __ beq(CCR0, *success);
2470 // Fall through to failure case.
2471 }
2472 }
2473 }
2474
2475 if (should_profile) {
2476 Register mdo = k_RInfo, recv = klass_RInfo;
2477 assert_different_registers(mdo, recv, Rtmp1);
2478 __ bind(profile_cast_success);
2479 metadata2reg(md->constant_encoding(), mdo);
2480 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2481 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2482 __ b(*success);
2483
2484 // Cast failure case.
2485 __ bind(profile_cast_failure);
2486 metadata2reg(md->constant_encoding(), mdo);
2487 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2488 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2489 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2490 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2491 }
2492
2493 __ bind(*failure);
2494
2495 if (restore_obj) {
2496 __ mr(op->object()->as_register(), dst);
2497 // Fall through to failure case.
2498 }
2499 }
2500
2501
2502 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2503 LIR_Code code = op->code();
2504 if (code == lir_store_check) {
2505 Register value = op->object()->as_register();
2506 Register array = op->array()->as_register();
2507 Register k_RInfo = op->tmp1()->as_register();
2508 Register klass_RInfo = op->tmp2()->as_register();
2509 Register Rtmp1 = op->tmp3()->as_register();
2510 bool should_profile = op->should_profile();
2511
2512 __ verify_oop(value);
2513 CodeStub* stub = op->stub();
2514 // Check if it needs to be profiled.
2515 ciMethodData* md;
2516 ciProfileData* data;
2517 int mdo_offset_bias = 0;
2518 if (should_profile) {
2519 ciMethod* method = op->profiled_method();
2520 assert(method != NULL, "Should have method");
2521 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2522 }
2523 Label profile_cast_success, failure, done;
2524 Label *success_target = should_profile ? &profile_cast_success : &done;
2525
2526 __ cmpdi(CCR0, value, 0);
2527 if (should_profile) {
2528 Label not_null;
2529 __ bne(CCR0, not_null);
2530 Register mdo = k_RInfo;
2531 Register data_val = Rtmp1;
2532 metadata2reg(md->constant_encoding(), mdo);
2533 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2534 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2535 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2536 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2537 __ b(done);
2538 __ bind(not_null);
2539 } else {
2540 __ beq(CCR0, done);
2541 }
2542 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2543 explicit_null_check(array, op->info_for_exception());
2544 } else {
2545 add_debug_info_for_null_check_here(op->info_for_exception());
2546 }
2547 __ load_klass(k_RInfo, array);
2548 __ load_klass(klass_RInfo, value);
2549
2550 // Get instance klass.
2551 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2552 // Perform the fast part of the checking logic.
2553 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2554
2555 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2556 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2557 //__ load_const_optimized(R0, slow_path);
2558 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2559 __ mtctr(R0);
2560 __ bctrl(); // sets CR0
2561 if (!should_profile) {
2562 __ beq(CCR0, done);
2563 __ bind(failure);
2564 } else {
2565 __ bne(CCR0, failure);
2566 // Fall through to the success case.
2567
2568 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2569 assert_different_registers(value, mdo, recv, tmp1);
2570 __ bind(profile_cast_success);
2571 metadata2reg(md->constant_encoding(), mdo);
2572 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2573 __ load_klass(recv, value);
2574 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2575 __ b(done);
2576
2577 // Cast failure case.
2578 __ bind(failure);
2579 metadata2reg(md->constant_encoding(), mdo);
2580 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2581 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2582 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2583 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2584 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2585 }
2586 __ b(*stub->entry());
2587 __ bind(done);
2588
2589 } else if (code == lir_checkcast) {
2590 Label success, failure;
2591 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success); // Moves obj to dst.
2592 __ b(*op->stub()->entry());
2593 __ align(32, 12);
2594 __ bind(success);
2595 } else if (code == lir_instanceof) {
2596 Register dst = op->result_opr()->as_register();
2597 Label success, failure, done;
2598 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2599 __ li(dst, 0);
2600 __ b(done);
2601 __ align(32, 12);
2602 __ bind(success);
2603 __ li(dst, 1);
2604 __ bind(done);
2605 } else {
2606 ShouldNotReachHere();
2607 }
2608 }
2609
2610
2611 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2612 Register addr = op->addr()->as_pointer_register();
2613 Register cmp_value = noreg, new_value = noreg;
2614 bool is_64bit = false;
2615
2616 if (op->code() == lir_cas_long) {
2617 cmp_value = op->cmp_value()->as_register_lo();
2618 new_value = op->new_value()->as_register_lo();
2619 is_64bit = true;
2620 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2621 cmp_value = op->cmp_value()->as_register();
2622 new_value = op->new_value()->as_register();
2623 if (op->code() == lir_cas_obj) {
2624 if (UseCompressedOops) {
2625 Register t1 = op->tmp1()->as_register();
2626 Register t2 = op->tmp2()->as_register();
2627 cmp_value = __ encode_heap_oop(t1, cmp_value);
2628 new_value = __ encode_heap_oop(t2, new_value);
2629 } else {
2630 is_64bit = true;
2631 }
2632 }
2633 } else {
2634 Unimplemented();
2635 }
2636
2637 if (is_64bit) {
2638 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2639 MacroAssembler::MemBarNone,
2640 MacroAssembler::cmpxchgx_hint_atomic_update(),
2641 noreg, NULL, /*check without ldarx first*/true);
2642 } else {
2643 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2644 MacroAssembler::MemBarNone,
2645 MacroAssembler::cmpxchgx_hint_atomic_update(),
2646 noreg, /*check without ldarx first*/true);
2647 }
2648
2649 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2650 __ isync();
2651 } else {
2652 __ sync();
2653 }
2654 }
2655
2656
2657 void LIR_Assembler::set_24bit_FPU() {
2658 Unimplemented();
2659 }
2660
2661 void LIR_Assembler::reset_FPU() {
2662 Unimplemented();
2663 }
2664
2665
2666 void LIR_Assembler::breakpoint() {
2667 __ illtrap();
2668 }
2669
2670
2671 void LIR_Assembler::push(LIR_Opr opr) {
2672 Unimplemented();
2673 }
2674
2675 void LIR_Assembler::pop(LIR_Opr opr) {
2676 Unimplemented();
2677 }
2678
2679
2680 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2681 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2682 Register dst = dst_opr->as_register();
2683 Register reg = mon_addr.base();
2684 int offset = mon_addr.disp();
2685 // Compute pointer to BasicLock.
2686 __ add_const_optimized(dst, reg, offset);
2687 }
2688
2689
2690 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2691 Register obj = op->obj_opr()->as_register();
2692 Register hdr = op->hdr_opr()->as_register();
2693 Register lock = op->lock_opr()->as_register();
2694
2695 // Obj may not be an oop.
2696 if (op->code() == lir_lock) {
2697 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2698 if (UseFastLocking) {
2699 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2700 // Add debug info for NullPointerException only if one is possible.
2701 if (op->info() != NULL) {
2702 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2703 explicit_null_check(obj, op->info());
2704 } else {
2705 add_debug_info_for_null_check_here(op->info());
2706 }
2707 }
2708 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2709 } else {
2710 // always do slow locking
2711 // note: The slow locking code could be inlined here, however if we use
2712 // slow locking, speed doesn't matter anyway and this solution is
2713 // simpler and requires less duplicated code - additionally, the
2714 // slow locking code is the same in either case which simplifies
2715 // debugging.
2716 __ b(*op->stub()->entry());
2717 }
2718 } else {
2719 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2720 if (UseFastLocking) {
2721 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2722 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2723 } else {
2724 // always do slow unlocking
2725 // note: The slow unlocking code could be inlined here, however if we use
2726 // slow unlocking, speed doesn't matter anyway and this solution is
2727 // simpler and requires less duplicated code - additionally, the
2728 // slow unlocking code is the same in either case which simplifies
2729 // debugging.
2730 __ b(*op->stub()->entry());
2731 }
2732 }
2733 __ bind(*op->stub()->continuation());
2734 }
2735
2736
2737 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2738 ciMethod* method = op->profiled_method();
2739 int bci = op->profiled_bci();
2740 ciMethod* callee = op->profiled_callee();
2741
2742 // Update counter for all call types.
2743 ciMethodData* md = method->method_data_or_null();
2744 assert(md != NULL, "Sanity");
2745 ciProfileData* data = md->bci_to_data(bci);
2746 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2747 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2748 Register mdo = op->mdo()->as_register();
2749 #ifdef _LP64
2750 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2751 Register tmp1 = op->tmp1()->as_register_lo();
2752 #else
2753 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2754 Register tmp1 = op->tmp1()->as_register();
2755 #endif
2756 metadata2reg(md->constant_encoding(), mdo);
2757 int mdo_offset_bias = 0;
2758 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2759 data->size_in_bytes())) {
2760 // The offset is large so bias the mdo by the base of the slot so
2761 // that the ld can use simm16s to reference the slots of the data.
2762 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2763 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2764 }
2765
2766 // Perform additional virtual call profiling for invokevirtual and
2767 // invokeinterface bytecodes
2768 if (op->should_profile_receiver_type()) {
2769 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2770 Register recv = op->recv()->as_register();
2771 assert_different_registers(mdo, tmp1, recv);
2772 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2773 ciKlass* known_klass = op->known_holder();
2774 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2775 // We know the type that will be seen at this call site; we can
2776 // statically update the MethodData* rather than needing to do
2777 // dynamic tests on the receiver type.
2778
2779 // NOTE: we should probably put a lock around this search to
2780 // avoid collisions by concurrent compilations.
2781 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2782 uint i;
2783 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2784 ciKlass* receiver = vc_data->receiver(i);
2785 if (known_klass->equals(receiver)) {
2786 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2787 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2788 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2789 return;
2790 }
2791 }
2792
2793 // Receiver type not found in profile data; select an empty slot.
2794
2795 // Note that this is less efficient than it should be because it
2796 // always does a write to the receiver part of the
2797 // VirtualCallData rather than just the first time.
2798 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2799 ciKlass* receiver = vc_data->receiver(i);
2800 if (receiver == NULL) {
2801 metadata2reg(known_klass->constant_encoding(), tmp1);
2802 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2803
2804 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2805 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2806 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2807 return;
2808 }
2809 }
2810 } else {
2811 __ load_klass(recv, recv);
2812 Label update_done;
2813 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2814 // Receiver did not match any saved receiver and there is no empty row for it.
2815 // Increment total counter to indicate polymorphic case.
2816 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2817 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2818 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2819
2820 __ bind(update_done);
2821 }
2822 } else {
2823 // Static call
2824 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2825 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2826 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2827 }
2828 }
2829
2830
2831 void LIR_Assembler::align_backward_branch_target() {
2832 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2833 }
2834
2835
2836 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2837 Unimplemented();
2838 }
2839
2840
2841 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2842 assert(left->is_register(), "can only handle registers");
2843
2844 if (left->is_single_cpu()) {
2845 __ neg(dest->as_register(), left->as_register());
2846 } else if (left->is_single_fpu()) {
2847 __ fneg(dest->as_float_reg(), left->as_float_reg());
2848 } else if (left->is_double_fpu()) {
2849 __ fneg(dest->as_double_reg(), left->as_double_reg());
2850 } else {
2851 assert (left->is_double_cpu(), "Must be a long");
2852 __ neg(dest->as_register_lo(), left->as_register_lo());
2853 }
2854 }
2855
2856
2857 void LIR_Assembler::fxch(int i) {
2858 Unimplemented();
2859 }
2860
2861 void LIR_Assembler::fld(int i) {
2862 Unimplemented();
2863 }
2864
2865 void LIR_Assembler::ffree(int i) {
2866 Unimplemented();
2867 }
2868
2869
2870 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2871 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2872 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2873 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2874 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2875 //__ load_const_optimized(R0, dest);
2876 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2877 __ mtctr(R0);
2878 __ bctrl();
2879 assert(info != NULL, "sanity");
2880 add_call_info_here(info);
2881 return;
2882 }
2883
2884 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2885 if (info != NULL) {
2886 add_call_info_here(info);
2887 }
2888 }
2889
2890
2891 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2892 ShouldNotReachHere(); // Not needed on _LP64.
2893 }
2894
2895 void LIR_Assembler::membar() {
2896 __ fence();
2897 }
2898
2899 void LIR_Assembler::membar_acquire() {
2900 __ acquire();
2901 }
2902
2903 void LIR_Assembler::membar_release() {
2904 __ release();
2905 }
2906
2907 void LIR_Assembler::membar_loadload() {
2908 __ membar(Assembler::LoadLoad);
2909 }
2910
2911 void LIR_Assembler::membar_storestore() {
2912 __ membar(Assembler::StoreStore);
2913 }
2914
2915 void LIR_Assembler::membar_loadstore() {
2916 __ membar(Assembler::LoadStore);
2917 }
2918
2919 void LIR_Assembler::membar_storeload() {
2920 __ membar(Assembler::StoreLoad);
2921 }
2922
2923 void LIR_Assembler::on_spin_wait() {
2924 Unimplemented();
2925 }
2926
2927 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
2928 LIR_Address* addr = addr_opr->as_address_ptr();
2929 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2930 if (addr->index()->is_illegal()) {
2931 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2932 } else {
2933 assert(addr->disp() == 0, "can't have both: index and disp");
2934 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2935 }
2936 }
2937
2938
2939 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2940 ShouldNotReachHere();
2941 }
2942
2943
2944 #ifdef ASSERT
2945 // Emit run-time assertion.
2946 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2947 Unimplemented();
2948 }
2949 #endif
2950
2951
2952 void LIR_Assembler::peephole(LIR_List* lir) {
2953 // Optimize instruction pairs before emitting.
2954 LIR_OpList* inst = lir->instructions_list();
2955 for (int i = 1; i < inst->length(); i++) {
2956 LIR_Op* op = inst->at(i);
2957
2958 // 2 register-register-moves
2959 if (op->code() == lir_move) {
2960 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2961 res2 = ((LIR_Op1*)op)->result_opr();
2962 if (in2->is_register() && res2->is_register()) {
2963 LIR_Op* prev = inst->at(i - 1);
2964 if (prev && prev->code() == lir_move) {
2965 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2966 res1 = ((LIR_Op1*)prev)->result_opr();
2967 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2968 inst->remove_at(i);
2969 }
2970 }
2971 }
2972 }
2973
2974 }
2975 return;
2976 }
2977
2978
2979 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2980 const Register Rptr = src->as_pointer_register(),
2981 Rtmp = tmp->as_register();
2982 Register Rco = noreg;
2983 if (UseCompressedOops && data->is_oop()) {
2984 Rco = __ encode_heap_oop(Rtmp, data->as_register());
2985 }
2986
2987 Label Lretry;
2988 __ bind(Lretry);
2989
2990 if (data->type() == T_INT) {
2991 const Register Rold = dest->as_register(),
2992 Rsrc = data->as_register();
2993 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2994 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2995 if (code == lir_xadd) {
2996 __ add(Rtmp, Rsrc, Rold);
2997 __ stwcx_(Rtmp, Rptr);
2998 } else {
2999 __ stwcx_(Rsrc, Rptr);
3000 }
3001 } else if (data->is_oop()) {
3002 assert(code == lir_xchg, "xadd for oops");
3003 const Register Rold = dest->as_register();
3004 if (UseCompressedOops) {
3005 assert_different_registers(Rptr, Rold, Rco);
3006 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3007 __ stwcx_(Rco, Rptr);
3008 } else {
3009 const Register Robj = data->as_register();
3010 assert_different_registers(Rptr, Rold, Robj);
3011 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3012 __ stdcx_(Robj, Rptr);
3013 }
3014 } else if (data->type() == T_LONG) {
3015 const Register Rold = dest->as_register_lo(),
3016 Rsrc = data->as_register_lo();
3017 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3018 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3019 if (code == lir_xadd) {
3020 __ add(Rtmp, Rsrc, Rold);
3021 __ stdcx_(Rtmp, Rptr);
3022 } else {
3023 __ stdcx_(Rsrc, Rptr);
3024 }
3025 } else {
3026 ShouldNotReachHere();
3027 }
3028
3029 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3030 __ bne_predict_not_taken(CCR0, Lretry);
3031 } else {
3032 __ bne( CCR0, Lretry);
3033 }
3034
3035 if (UseCompressedOops && data->is_oop()) {
3036 __ decode_heap_oop(dest->as_register());
3037 }
3038 }
3039
3040
3041 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3042 Register obj = op->obj()->as_register();
3043 Register tmp = op->tmp()->as_pointer_register();
3044 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3045 ciKlass* exact_klass = op->exact_klass();
3046 intptr_t current_klass = op->current_klass();
3047 bool not_null = op->not_null();
3048 bool no_conflict = op->no_conflict();
3049
3050 Label Lupdate, Ldo_update, Ldone;
3051
3052 bool do_null = !not_null;
3053 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3054 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3055
3056 assert(do_null || do_update, "why are we here?");
3057 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3058
3059 __ verify_oop(obj);
3060
3061 if (do_null) {
3062 if (!TypeEntries::was_null_seen(current_klass)) {
3063 __ cmpdi(CCR0, obj, 0);
3064 __ bne(CCR0, Lupdate);
3065 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3066 __ ori(R0, R0, TypeEntries::null_seen);
3067 if (do_update) {
3068 __ b(Ldo_update);
3069 } else {
3070 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3071 }
3072 } else {
3073 if (do_update) {
3074 __ cmpdi(CCR0, obj, 0);
3075 __ beq(CCR0, Ldone);
3076 }
3077 }
3078 #ifdef ASSERT
3079 } else {
3080 __ cmpdi(CCR0, obj, 0);
3081 __ bne(CCR0, Lupdate);
3082 __ stop("unexpect null obj", 0x9652);
3083 #endif
3084 }
3085
3086 __ bind(Lupdate);
3087 if (do_update) {
3088 Label Lnext;
3089 const Register klass = R29_TOC; // kill and reload
3090 bool klass_reg_used = false;
3091 #ifdef ASSERT
3092 if (exact_klass != NULL) {
3093 Label ok;
3094 klass_reg_used = true;
3095 __ load_klass(klass, obj);
3096 metadata2reg(exact_klass->constant_encoding(), R0);
3097 __ cmpd(CCR0, klass, R0);
3098 __ beq(CCR0, ok);
3099 __ stop("exact klass and actual klass differ", 0x8564);
3100 __ bind(ok);
3101 }
3102 #endif
3103
3104 if (!no_conflict) {
3105 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3106 klass_reg_used = true;
3107 if (exact_klass != NULL) {
3108 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3109 metadata2reg(exact_klass->constant_encoding(), klass);
3110 } else {
3111 __ load_klass(klass, obj);
3112 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3113 }
3114
3115 // Like InterpreterMacroAssembler::profile_obj_type
3116 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3117 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3118 __ cmpd(CCR1, R0, klass);
3119 // Klass seen before, nothing to do (regardless of unknown bit).
3120 //beq(CCR1, do_nothing);
3121
3122 __ andi_(R0, klass, TypeEntries::type_unknown);
3123 // Already unknown. Nothing to do anymore.
3124 //bne(CCR0, do_nothing);
3125 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3126 __ beq(CCR0, Lnext);
3127
3128 if (TypeEntries::is_type_none(current_klass)) {
3129 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3130 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3131 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3132 }
3133
3134 } else {
3135 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3136 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3137
3138 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3139 __ andi_(R0, tmp, TypeEntries::type_unknown);
3140 // Already unknown. Nothing to do anymore.
3141 __ bne(CCR0, Lnext);
3142 }
3143
3144 // Different than before. Cannot keep accurate profile.
3145 __ ori(R0, tmp, TypeEntries::type_unknown);
3146 } else {
3147 // There's a single possible klass at this profile point
3148 assert(exact_klass != NULL, "should be");
3149 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3150
3151 if (TypeEntries::is_type_none(current_klass)) {
3152 klass_reg_used = true;
3153 metadata2reg(exact_klass->constant_encoding(), klass);
3154
3155 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3156 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3157 __ cmpd(CCR1, R0, klass);
3158 // Klass seen before, nothing to do (regardless of unknown bit).
3159 __ beq(CCR1, Lnext);
3160 #ifdef ASSERT
3161 {
3162 Label ok;
3163 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3164 __ beq(CCR0, ok); // First time here.
3165
3166 __ stop("unexpected profiling mismatch", 0x7865);
3167 __ bind(ok);
3168 }
3169 #endif
3170 // First time here. Set profile type.
3171 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3172 } else {
3173 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3174 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3175
3176 // Already unknown. Nothing to do anymore.
3177 __ andi_(R0, tmp, TypeEntries::type_unknown);
3178 __ bne(CCR0, Lnext);
3179
3180 // Different than before. Cannot keep accurate profile.
3181 __ ori(R0, tmp, TypeEntries::type_unknown);
3182 }
3183 }
3184
3185 __ bind(Ldo_update);
3186 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3187
3188 __ bind(Lnext);
3189 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3190 }
3191 __ bind(Ldone);
3192 }
3193
3194
3195 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3196 assert(op->crc()->is_single_cpu(), "crc must be register");
3197 assert(op->val()->is_single_cpu(), "byte value must be register");
3198 assert(op->result_opr()->is_single_cpu(), "result must be register");
3199 Register crc = op->crc()->as_register();
3200 Register val = op->val()->as_register();
3201 Register res = op->result_opr()->as_register();
3202
3203 assert_different_registers(val, crc, res);
3204
3205 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3206 __ kernel_crc32_singleByteReg(crc, val, res, true);
3207 __ mr(res, crc);
3208 }
3209
3210 #undef __