1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableModRefBS.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/jniHandles.inline.hpp"
39 #include "runtime/safepointMechanism.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41
42 #define __ _masm->
43
44
45 //------------------------------------------------------------
46
47
48 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
49 if (opr->is_constant()) {
50 LIR_Const* constant = opr->as_constant_ptr();
51 switch (constant->type()) {
52 case T_INT: {
53 jint value = constant->as_jint();
54 return Assembler::is_simm13(value);
55 }
56
57 default:
58 return false;
59 }
60 }
61 return false;
62 }
63
64
65 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
66 switch (op->code()) {
67 case lir_null_check:
68 return true;
69
70
71 case lir_add:
72 case lir_ushr:
73 case lir_shr:
74 case lir_shl:
75 // integer shifts and adds are always one instruction
76 return op->result_opr()->is_single_cpu();
77
78
79 case lir_move: {
80 LIR_Op1* op1 = op->as_Op1();
81 LIR_Opr src = op1->in_opr();
82 LIR_Opr dst = op1->result_opr();
83
84 if (src == dst) {
85 NEEDS_CLEANUP;
86 // this works around a problem where moves with the same src and dst
87 // end up in the delay slot and then the assembler swallows the mov
88 // since it has no effect and then it complains because the delay slot
89 // is empty. returning false stops the optimizer from putting this in
90 // the delay slot
91 return false;
92 }
93
94 // don't put moves involving oops into the delay slot since the VerifyOops code
95 // will make it much larger than a single instruction.
96 if (VerifyOops) {
97 return false;
98 }
99
100 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
101 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
102 return false;
103 }
104
105 if (UseCompressedOops) {
106 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
107 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
108 }
109
110 if (UseCompressedClassPointers) {
111 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
112 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
113 }
114
115 if (dst->is_register()) {
116 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
117 return !PatchALot;
118 } else if (src->is_single_stack()) {
119 return true;
120 }
121 }
122
123 if (src->is_register()) {
124 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
125 return !PatchALot;
126 } else if (dst->is_single_stack()) {
127 return true;
128 }
129 }
130
131 if (dst->is_register() &&
132 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
133 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
134 return true;
135 }
136
137 return false;
138 }
139
140 default:
141 return false;
142 }
143 ShouldNotReachHere();
144 }
145
146
147 LIR_Opr LIR_Assembler::receiverOpr() {
148 return FrameMap::O0_oop_opr;
149 }
150
151
152 LIR_Opr LIR_Assembler::osrBufferPointer() {
153 return FrameMap::I0_opr;
154 }
155
156
157 int LIR_Assembler::initial_frame_size_in_bytes() const {
158 return in_bytes(frame_map()->framesize_in_bytes());
159 }
160
161
162 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
163 // we fetch the class of the receiver (O0) and compare it with the cached class.
164 // If they do not match we jump to slow case.
165 int LIR_Assembler::check_icache() {
166 int offset = __ offset();
167 __ inline_cache_check(O0, G5_inline_cache_reg);
168 return offset;
169 }
170
171
172 void LIR_Assembler::osr_entry() {
173 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
174 //
175 // 1. Create a new compiled activation.
176 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
177 // at the osr_bci; it is not initialized.
178 // 3. Jump to the continuation address in compiled code to resume execution.
179
180 // OSR entry point
181 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
182 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
183 ValueStack* entry_state = osr_entry->end()->state();
184 int number_of_locks = entry_state->locks_size();
185
186 // Create a frame for the compiled activation.
187 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
188
189 // OSR buffer is
190 //
191 // locals[nlocals-1..0]
192 // monitors[number_of_locks-1..0]
193 //
194 // locals is a direct copy of the interpreter frame so in the osr buffer
195 // so first slot in the local array is the last local from the interpreter
196 // and last slot is local[0] (receiver) from the interpreter
197 //
198 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
199 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
200 // in the interpreter frame (the method lock if a sync method)
201
202 // Initialize monitors in the compiled activation.
203 // I0: pointer to osr buffer
204 //
205 // All other registers are dead at this point and the locals will be
206 // copied into place by code emitted in the IR.
207
208 Register OSR_buf = osrBufferPointer()->as_register();
209 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
210 int monitor_offset = BytesPerWord * method()->max_locals() +
211 (2 * BytesPerWord) * (number_of_locks - 1);
212 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
213 // the OSR buffer using 2 word entries: first the lock and then
214 // the oop.
215 for (int i = 0; i < number_of_locks; i++) {
216 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
217 #ifdef ASSERT
218 // verify the interpreter's monitor has a non-null object
219 {
220 Label L;
221 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
222 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
223 __ stop("locked object is NULL");
224 __ bind(L);
225 }
226 #endif // ASSERT
227 // Copy the lock field into the compiled activation.
228 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
229 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
230 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
231 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
232 }
233 }
234 }
235
236
237 // --------------------------------------------------------------------------------------------
238
239 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
240 if (!GenerateSynchronizationCode) return;
241
242 Register obj_reg = obj_opr->as_register();
243 Register lock_reg = lock_opr->as_register();
244
245 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
246 Register reg = mon_addr.base();
247 int offset = mon_addr.disp();
248 // compute pointer to BasicLock
249 if (mon_addr.is_simm13()) {
250 __ add(reg, offset, lock_reg);
251 }
252 else {
253 __ set(offset, lock_reg);
254 __ add(reg, lock_reg, lock_reg);
255 }
256 // unlock object
257 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
258 // _slow_case_stubs->append(slow_case);
259 // temporary fix: must be created after exceptionhandler, therefore as call stub
260 _slow_case_stubs->append(slow_case);
261 if (UseFastLocking) {
262 // try inlined fast unlocking first, revert to slow locking if it fails
263 // note: lock_reg points to the displaced header since the displaced header offset is 0!
264 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
265 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
266 } else {
267 // always do slow unlocking
268 // note: the slow unlocking code could be inlined here, however if we use
269 // slow unlocking, speed doesn't matter anyway and this solution is
270 // simpler and requires less duplicated code - additionally, the
271 // slow unlocking code is the same in either case which simplifies
272 // debugging
273 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
274 __ delayed()->nop();
275 }
276 // done
277 __ bind(*slow_case->continuation());
278 }
279
280
281 int LIR_Assembler::emit_exception_handler() {
282 // if the last instruction is a call (typically to do a throw which
283 // is coming at the end after block reordering) the return address
284 // must still point into the code area in order to avoid assertion
285 // failures when searching for the corresponding bci => add a nop
286 // (was bug 5/14/1999 - gri)
287 __ nop();
288
289 // generate code for exception handler
290 ciMethod* method = compilation()->method();
291
292 address handler_base = __ start_a_stub(exception_handler_size());
293
294 if (handler_base == NULL) {
295 // not enough space left for the handler
296 bailout("exception handler overflow");
297 return -1;
298 }
299
300 int offset = code_offset();
301
302 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
303 __ delayed()->nop();
304 __ should_not_reach_here();
305 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
306 __ end_a_stub();
307
308 return offset;
309 }
310
311
312 // Emit the code to remove the frame from the stack in the exception
313 // unwind path.
314 int LIR_Assembler::emit_unwind_handler() {
315 #ifndef PRODUCT
316 if (CommentedAssembly) {
317 _masm->block_comment("Unwind handler");
318 }
319 #endif
320
321 int offset = code_offset();
322
323 // Fetch the exception from TLS and clear out exception related thread state
324 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
325 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
326 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
327
328 __ bind(_unwind_handler_entry);
329 __ verify_not_null_oop(O0);
330 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
331 __ mov(O0, I0); // Preserve the exception
332 }
333
334 // Preform needed unlocking
335 MonitorExitStub* stub = NULL;
336 if (method()->is_synchronized()) {
337 monitor_address(0, FrameMap::I1_opr);
338 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
339 __ unlock_object(I3, I2, I1, *stub->entry());
340 __ bind(*stub->continuation());
341 }
342
343 if (compilation()->env()->dtrace_method_probes()) {
344 __ mov(G2_thread, O0);
345 __ save_thread(I1); // need to preserve thread in G2 across
346 // runtime call
347 metadata2reg(method()->constant_encoding(), O1);
348 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
349 __ delayed()->nop();
350 __ restore_thread(I1);
351 }
352
353 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
354 __ mov(I0, O0); // Restore the exception
355 }
356
357 // dispatch to the unwind logic
358 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
359 __ delayed()->nop();
360
361 // Emit the slow path assembly
362 if (stub != NULL) {
363 stub->emit_code(this);
364 }
365
366 return offset;
367 }
368
369
370 int LIR_Assembler::emit_deopt_handler() {
371 // if the last instruction is a call (typically to do a throw which
372 // is coming at the end after block reordering) the return address
373 // must still point into the code area in order to avoid assertion
374 // failures when searching for the corresponding bci => add a nop
375 // (was bug 5/14/1999 - gri)
376 __ nop();
377
378 // generate code for deopt handler
379 ciMethod* method = compilation()->method();
380 address handler_base = __ start_a_stub(deopt_handler_size());
381 if (handler_base == NULL) {
382 // not enough space left for the handler
383 bailout("deopt handler overflow");
384 return -1;
385 }
386
387 int offset = code_offset();
388 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
389 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
390 __ delayed()->nop();
391 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
392 __ end_a_stub();
393
394 return offset;
395 }
396
397
398 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
399 if (o == NULL) {
400 __ set(NULL_WORD, reg);
401 } else {
402 #ifdef ASSERT
403 {
404 ThreadInVMfromNative tiv(JavaThread::current());
405 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
406 }
407 #endif
408 int oop_index = __ oop_recorder()->find_index(o);
409 RelocationHolder rspec = oop_Relocation::spec(oop_index);
410 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
411 }
412 }
413
414
415 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
416 // Allocate a new index in table to hold the object once it's been patched
417 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
418 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
419
420 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
421 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
422 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
423 // NULL will be dynamically patched later and the patched value may be large. We must
424 // therefore generate the sethi/add as a placeholders
425 __ patchable_set(addrlit, reg);
426
427 patching_epilog(patch, lir_patch_normal, reg, info);
428 }
429
430
431 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
432 __ set_metadata_constant(o, reg);
433 }
434
435 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
436 // Allocate a new index in table to hold the klass once it's been patched
437 int index = __ oop_recorder()->allocate_metadata_index(NULL);
438 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
439 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
440 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
441 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
442 // NULL will be dynamically patched later and the patched value may be large. We must
443 // therefore generate the sethi/add as a placeholders
444 __ patchable_set(addrlit, reg);
445
446 patching_epilog(patch, lir_patch_normal, reg, info);
447 }
448
449 void LIR_Assembler::emit_op3(LIR_Op3* op) {
450 switch (op->code()) {
451 case lir_idiv:
452 case lir_irem: // Both idiv & irem are handled after the switch (below).
453 break;
454 case lir_fmaf:
455 __ fmadd(FloatRegisterImpl::S,
456 op->in_opr1()->as_float_reg(),
457 op->in_opr2()->as_float_reg(),
458 op->in_opr3()->as_float_reg(),
459 op->result_opr()->as_float_reg());
460 return;
461 case lir_fmad:
462 __ fmadd(FloatRegisterImpl::D,
463 op->in_opr1()->as_double_reg(),
464 op->in_opr2()->as_double_reg(),
465 op->in_opr3()->as_double_reg(),
466 op->result_opr()->as_double_reg());
467 return;
468 default:
469 ShouldNotReachHere();
470 break;
471 }
472
473 // Handle idiv & irem:
474
475 Register Rdividend = op->in_opr1()->as_register();
476 Register Rdivisor = noreg;
477 Register Rscratch = op->in_opr3()->as_register();
478 Register Rresult = op->result_opr()->as_register();
479 int divisor = -1;
480
481 if (op->in_opr2()->is_register()) {
482 Rdivisor = op->in_opr2()->as_register();
483 } else {
484 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
485 assert(Assembler::is_simm13(divisor), "can only handle simm13");
486 }
487
488 assert(Rdividend != Rscratch, "");
489 assert(Rdivisor != Rscratch, "");
490 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
491
492 if (Rdivisor == noreg && is_power_of_2(divisor)) {
493 // convert division by a power of two into some shifts and logical operations
494 if (op->code() == lir_idiv) {
495 if (divisor == 2) {
496 __ srl(Rdividend, 31, Rscratch);
497 } else {
498 __ sra(Rdividend, 31, Rscratch);
499 __ and3(Rscratch, divisor - 1, Rscratch);
500 }
501 __ add(Rdividend, Rscratch, Rscratch);
502 __ sra(Rscratch, log2_intptr(divisor), Rresult);
503 return;
504 } else {
505 if (divisor == 2) {
506 __ srl(Rdividend, 31, Rscratch);
507 } else {
508 __ sra(Rdividend, 31, Rscratch);
509 __ and3(Rscratch, divisor - 1,Rscratch);
510 }
511 __ add(Rdividend, Rscratch, Rscratch);
512 __ andn(Rscratch, divisor - 1,Rscratch);
513 __ sub(Rdividend, Rscratch, Rresult);
514 return;
515 }
516 }
517
518 __ sra(Rdividend, 31, Rscratch);
519 __ wry(Rscratch);
520
521 add_debug_info_for_div0_here(op->info());
522
523 if (Rdivisor != noreg) {
524 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
525 } else {
526 assert(Assembler::is_simm13(divisor), "can only handle simm13");
527 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
528 }
529
530 Label skip;
531 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
532 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
533 __ bind(skip);
534
535 if (op->code() == lir_irem) {
536 if (Rdivisor != noreg) {
537 __ smul(Rscratch, Rdivisor, Rscratch);
538 } else {
539 __ smul(Rscratch, divisor, Rscratch);
540 }
541 __ sub(Rdividend, Rscratch, Rresult);
542 }
543 }
544
545
546 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
547 #ifdef ASSERT
548 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
549 if (op->block() != NULL) _branch_target_blocks.append(op->block());
550 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
551 #endif
552 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
553
554 if (op->cond() == lir_cond_always) {
555 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
556 } else if (op->code() == lir_cond_float_branch) {
557 assert(op->ublock() != NULL, "must have unordered successor");
558 bool is_unordered = (op->ublock() == op->block());
559 Assembler::Condition acond;
560 switch (op->cond()) {
561 case lir_cond_equal: acond = Assembler::f_equal; break;
562 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
563 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
564 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
565 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
566 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
567 default : ShouldNotReachHere();
568 }
569 __ fb( acond, false, Assembler::pn, *(op->label()));
570 } else {
571 assert (op->code() == lir_branch, "just checking");
572
573 Assembler::Condition acond;
574 switch (op->cond()) {
575 case lir_cond_equal: acond = Assembler::equal; break;
576 case lir_cond_notEqual: acond = Assembler::notEqual; break;
577 case lir_cond_less: acond = Assembler::less; break;
578 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
579 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
580 case lir_cond_greater: acond = Assembler::greater; break;
581 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
582 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
583 default: ShouldNotReachHere();
584 };
585
586 // sparc has different condition codes for testing 32-bit
587 // vs. 64-bit values. We could always test xcc is we could
588 // guarantee that 32-bit loads always sign extended but that isn't
589 // true and since sign extension isn't free, it would impose a
590 // slight cost.
591 if (op->type() == T_INT) {
592 __ br(acond, false, Assembler::pn, *(op->label()));
593 } else
594 __ brx(acond, false, Assembler::pn, *(op->label()));
595 }
596 // The peephole pass fills the delay slot
597 }
598
599
600 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
601 Bytecodes::Code code = op->bytecode();
602 LIR_Opr dst = op->result_opr();
603
604 switch(code) {
605 case Bytecodes::_i2l: {
606 Register rlo = dst->as_register_lo();
607 Register rhi = dst->as_register_hi();
608 Register rval = op->in_opr()->as_register();
609 __ sra(rval, 0, rlo);
610 break;
611 }
612 case Bytecodes::_i2d:
613 case Bytecodes::_i2f: {
614 bool is_double = (code == Bytecodes::_i2d);
615 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
616 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
617 FloatRegister rsrc = op->in_opr()->as_float_reg();
618 if (rsrc != rdst) {
619 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
620 }
621 __ fitof(w, rdst, rdst);
622 break;
623 }
624 case Bytecodes::_f2i:{
625 FloatRegister rsrc = op->in_opr()->as_float_reg();
626 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
627 Label L;
628 // result must be 0 if value is NaN; test by comparing value to itself
629 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
630 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
631 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
632 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
633 // move integer result from float register to int register
634 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
635 __ bind (L);
636 break;
637 }
638 case Bytecodes::_l2i: {
639 Register rlo = op->in_opr()->as_register_lo();
640 Register rhi = op->in_opr()->as_register_hi();
641 Register rdst = dst->as_register();
642 __ sra(rlo, 0, rdst);
643 break;
644 }
645 case Bytecodes::_d2f:
646 case Bytecodes::_f2d: {
647 bool is_double = (code == Bytecodes::_f2d);
648 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
649 LIR_Opr val = op->in_opr();
650 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
651 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
652 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
653 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
654 __ ftof(vw, dw, rval, rdst);
655 break;
656 }
657 case Bytecodes::_i2s:
658 case Bytecodes::_i2b: {
659 Register rval = op->in_opr()->as_register();
660 Register rdst = dst->as_register();
661 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
662 __ sll (rval, shift, rdst);
663 __ sra (rdst, shift, rdst);
664 break;
665 }
666 case Bytecodes::_i2c: {
667 Register rval = op->in_opr()->as_register();
668 Register rdst = dst->as_register();
669 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
670 __ sll (rval, shift, rdst);
671 __ srl (rdst, shift, rdst);
672 break;
673 }
674
675 default: ShouldNotReachHere();
676 }
677 }
678
679
680 void LIR_Assembler::align_call(LIR_Code) {
681 // do nothing since all instructions are word aligned on sparc
682 }
683
684
685 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
686 __ call(op->addr(), rtype);
687 // The peephole pass fills the delay slot, add_call_info is done in
688 // LIR_Assembler::emit_delay.
689 }
690
691
692 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
693 __ ic_call(op->addr(), false);
694 // The peephole pass fills the delay slot, add_call_info is done in
695 // LIR_Assembler::emit_delay.
696 }
697
698
699 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
700 add_debug_info_for_null_check_here(op->info());
701 __ load_klass(O0, G3_scratch);
702 if (Assembler::is_simm13(op->vtable_offset())) {
703 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
704 } else {
705 // This will generate 2 instructions
706 __ set(op->vtable_offset(), G5_method);
707 // ld_ptr, set_hi, set
708 __ ld_ptr(G3_scratch, G5_method, G5_method);
709 }
710 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
711 __ callr(G3_scratch, G0);
712 // the peephole pass fills the delay slot
713 }
714
715 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
716 int store_offset;
717 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
718 assert(base != O7, "destroying register");
719 assert(!unaligned, "can't handle this");
720 // for offsets larger than a simm13 we setup the offset in O7
721 __ set(offset, O7);
722 store_offset = store(from_reg, base, O7, type, wide);
723 } else {
724 if (type == T_ARRAY || type == T_OBJECT) {
725 __ verify_oop(from_reg->as_register());
726 }
727 store_offset = code_offset();
728 switch (type) {
729 case T_BOOLEAN: // fall through
730 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
731 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
732 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
733 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
734 case T_LONG :
735 if (unaligned || PatchALot) {
736 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
737 assert(G3_scratch != base, "can't handle this");
738 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
739 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
740 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
741 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
742 } else {
743 __ stx(from_reg->as_register_lo(), base, offset);
744 }
745 break;
746 case T_ADDRESS:
747 case T_METADATA:
748 __ st_ptr(from_reg->as_register(), base, offset);
749 break;
750 case T_ARRAY : // fall through
751 case T_OBJECT:
752 {
753 if (UseCompressedOops && !wide) {
754 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
755 store_offset = code_offset();
756 __ stw(G3_scratch, base, offset);
757 } else {
758 __ st_ptr(from_reg->as_register(), base, offset);
759 }
760 break;
761 }
762
763 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
764 case T_DOUBLE:
765 {
766 FloatRegister reg = from_reg->as_double_reg();
767 // split unaligned stores
768 if (unaligned || PatchALot) {
769 assert(Assembler::is_simm13(offset + 4), "must be");
770 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
771 __ stf(FloatRegisterImpl::S, reg, base, offset);
772 } else {
773 __ stf(FloatRegisterImpl::D, reg, base, offset);
774 }
775 break;
776 }
777 default : ShouldNotReachHere();
778 }
779 }
780 return store_offset;
781 }
782
783
784 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
785 if (type == T_ARRAY || type == T_OBJECT) {
786 __ verify_oop(from_reg->as_register());
787 }
788 int store_offset = code_offset();
789 switch (type) {
790 case T_BOOLEAN: // fall through
791 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
792 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
793 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
794 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
795 case T_LONG :
796 __ stx(from_reg->as_register_lo(), base, disp);
797 break;
798 case T_ADDRESS:
799 __ st_ptr(from_reg->as_register(), base, disp);
800 break;
801 case T_ARRAY : // fall through
802 case T_OBJECT:
803 {
804 if (UseCompressedOops && !wide) {
805 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
806 store_offset = code_offset();
807 __ stw(G3_scratch, base, disp);
808 } else {
809 __ st_ptr(from_reg->as_register(), base, disp);
810 }
811 break;
812 }
813 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
814 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
815 default : ShouldNotReachHere();
816 }
817 return store_offset;
818 }
819
820
821 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
822 int load_offset;
823 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
824 assert(base != O7, "destroying register");
825 assert(!unaligned, "can't handle this");
826 // for offsets larger than a simm13 we setup the offset in O7
827 __ set(offset, O7);
828 load_offset = load(base, O7, to_reg, type, wide);
829 } else {
830 load_offset = code_offset();
831 switch(type) {
832 case T_BOOLEAN: // fall through
833 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
834 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
835 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
836 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
837 case T_LONG :
838 if (!unaligned && !PatchALot) {
839 __ ldx(base, offset, to_reg->as_register_lo());
840 } else {
841 assert(base != to_reg->as_register_lo(), "can't handle this");
842 assert(O7 != to_reg->as_register_lo(), "can't handle this");
843 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
844 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
845 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
846 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
847 }
848 break;
849 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
850 case T_ADDRESS:
851 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
852 __ lduw(base, offset, to_reg->as_register());
853 __ decode_klass_not_null(to_reg->as_register());
854 } else
855 {
856 __ ld_ptr(base, offset, to_reg->as_register());
857 }
858 break;
859 case T_ARRAY : // fall through
860 case T_OBJECT:
861 {
862 if (UseCompressedOops && !wide) {
863 __ lduw(base, offset, to_reg->as_register());
864 __ decode_heap_oop(to_reg->as_register());
865 } else {
866 __ ld_ptr(base, offset, to_reg->as_register());
867 }
868 break;
869 }
870 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
871 case T_DOUBLE:
872 {
873 FloatRegister reg = to_reg->as_double_reg();
874 // split unaligned loads
875 if (unaligned || PatchALot) {
876 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
877 __ ldf(FloatRegisterImpl::S, base, offset, reg);
878 } else {
879 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
880 }
881 break;
882 }
883 default : ShouldNotReachHere();
884 }
885 if (type == T_ARRAY || type == T_OBJECT) {
886 __ verify_oop(to_reg->as_register());
887 }
888 }
889 return load_offset;
890 }
891
892
893 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
894 int load_offset = code_offset();
895 switch(type) {
896 case T_BOOLEAN: // fall through
897 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
898 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
899 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
900 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
901 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
902 case T_ARRAY : // fall through
903 case T_OBJECT:
904 {
905 if (UseCompressedOops && !wide) {
906 __ lduw(base, disp, to_reg->as_register());
907 __ decode_heap_oop(to_reg->as_register());
908 } else {
909 __ ld_ptr(base, disp, to_reg->as_register());
910 }
911 break;
912 }
913 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
914 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
915 case T_LONG :
916 __ ldx(base, disp, to_reg->as_register_lo());
917 break;
918 default : ShouldNotReachHere();
919 }
920 if (type == T_ARRAY || type == T_OBJECT) {
921 __ verify_oop(to_reg->as_register());
922 }
923 return load_offset;
924 }
925
926 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
927 LIR_Const* c = src->as_constant_ptr();
928 switch (c->type()) {
929 case T_INT:
930 case T_FLOAT: {
931 Register src_reg = O7;
932 int value = c->as_jint_bits();
933 if (value == 0) {
934 src_reg = G0;
935 } else {
936 __ set(value, O7);
937 }
938 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
939 __ stw(src_reg, addr.base(), addr.disp());
940 break;
941 }
942 case T_ADDRESS: {
943 Register src_reg = O7;
944 int value = c->as_jint_bits();
945 if (value == 0) {
946 src_reg = G0;
947 } else {
948 __ set(value, O7);
949 }
950 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
951 __ st_ptr(src_reg, addr.base(), addr.disp());
952 break;
953 }
954 case T_OBJECT: {
955 Register src_reg = O7;
956 jobject2reg(c->as_jobject(), src_reg);
957 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
958 __ st_ptr(src_reg, addr.base(), addr.disp());
959 break;
960 }
961 case T_LONG:
962 case T_DOUBLE: {
963 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
964
965 Register tmp = O7;
966 int value_lo = c->as_jint_lo_bits();
967 if (value_lo == 0) {
968 tmp = G0;
969 } else {
970 __ set(value_lo, O7);
971 }
972 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
973 int value_hi = c->as_jint_hi_bits();
974 if (value_hi == 0) {
975 tmp = G0;
976 } else {
977 __ set(value_hi, O7);
978 }
979 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
980 break;
981 }
982 default:
983 Unimplemented();
984 }
985 }
986
987
988 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
989 LIR_Const* c = src->as_constant_ptr();
990 LIR_Address* addr = dest->as_address_ptr();
991 Register base = addr->base()->as_pointer_register();
992 int offset = -1;
993
994 switch (c->type()) {
995 case T_FLOAT: type = T_INT; // Float constants are stored by int store instructions.
996 case T_INT:
997 case T_ADDRESS: {
998 LIR_Opr tmp = FrameMap::O7_opr;
999 int value = c->as_jint_bits();
1000 if (value == 0) {
1001 tmp = FrameMap::G0_opr;
1002 } else if (Assembler::is_simm13(value)) {
1003 __ set(value, O7);
1004 }
1005 if (addr->index()->is_valid()) {
1006 assert(addr->disp() == 0, "must be zero");
1007 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1008 } else {
1009 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1010 offset = store(tmp, base, addr->disp(), type, wide, false);
1011 }
1012 break;
1013 }
1014 case T_LONG:
1015 case T_DOUBLE: {
1016 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1017 assert(Assembler::is_simm13(addr->disp()) &&
1018 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1019
1020 LIR_Opr tmp = FrameMap::O7_opr;
1021 int value_lo = c->as_jint_lo_bits();
1022 if (value_lo == 0) {
1023 tmp = FrameMap::G0_opr;
1024 } else {
1025 __ set(value_lo, O7);
1026 }
1027 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1028 int value_hi = c->as_jint_hi_bits();
1029 if (value_hi == 0) {
1030 tmp = FrameMap::G0_opr;
1031 } else {
1032 __ set(value_hi, O7);
1033 }
1034 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1035 break;
1036 }
1037 case T_OBJECT: {
1038 jobject obj = c->as_jobject();
1039 LIR_Opr tmp;
1040 if (obj == NULL) {
1041 tmp = FrameMap::G0_opr;
1042 } else {
1043 tmp = FrameMap::O7_opr;
1044 jobject2reg(c->as_jobject(), O7);
1045 }
1046 // handle either reg+reg or reg+disp address
1047 if (addr->index()->is_valid()) {
1048 assert(addr->disp() == 0, "must be zero");
1049 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1050 } else {
1051 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1052 offset = store(tmp, base, addr->disp(), type, wide, false);
1053 }
1054
1055 break;
1056 }
1057 default:
1058 Unimplemented();
1059 }
1060 if (info != NULL) {
1061 assert(offset != -1, "offset should've been set");
1062 add_debug_info_for_null_check(offset, info);
1063 }
1064 }
1065
1066
1067 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1068 LIR_Const* c = src->as_constant_ptr();
1069 LIR_Opr to_reg = dest;
1070
1071 switch (c->type()) {
1072 case T_INT:
1073 case T_ADDRESS:
1074 {
1075 jint con = c->as_jint();
1076 if (to_reg->is_single_cpu()) {
1077 assert(patch_code == lir_patch_none, "no patching handled here");
1078 __ set(con, to_reg->as_register());
1079 } else {
1080 ShouldNotReachHere();
1081 assert(to_reg->is_single_fpu(), "wrong register kind");
1082
1083 __ set(con, O7);
1084 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1085 __ st(O7, temp_slot);
1086 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1087 }
1088 }
1089 break;
1090
1091 case T_LONG:
1092 {
1093 jlong con = c->as_jlong();
1094
1095 if (to_reg->is_double_cpu()) {
1096 __ set(con, to_reg->as_register_lo());
1097 } else if (to_reg->is_single_cpu()) {
1098 __ set(con, to_reg->as_register());
1099 } else {
1100 ShouldNotReachHere();
1101 assert(to_reg->is_double_fpu(), "wrong register kind");
1102 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1103 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1104 __ set(low(con), O7);
1105 __ st(O7, temp_slot_lo);
1106 __ set(high(con), O7);
1107 __ st(O7, temp_slot_hi);
1108 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1109 }
1110 }
1111 break;
1112
1113 case T_OBJECT:
1114 {
1115 if (patch_code == lir_patch_none) {
1116 jobject2reg(c->as_jobject(), to_reg->as_register());
1117 } else {
1118 jobject2reg_with_patching(to_reg->as_register(), info);
1119 }
1120 }
1121 break;
1122
1123 case T_METADATA:
1124 {
1125 if (patch_code == lir_patch_none) {
1126 metadata2reg(c->as_metadata(), to_reg->as_register());
1127 } else {
1128 klass2reg_with_patching(to_reg->as_register(), info);
1129 }
1130 }
1131 break;
1132
1133 case T_FLOAT:
1134 {
1135 address const_addr = __ float_constant(c->as_jfloat());
1136 if (const_addr == NULL) {
1137 bailout("const section overflow");
1138 break;
1139 }
1140 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1141 AddressLiteral const_addrlit(const_addr, rspec);
1142 if (to_reg->is_single_fpu()) {
1143 __ patchable_sethi(const_addrlit, O7);
1144 __ relocate(rspec);
1145 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1146
1147 } else {
1148 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1149
1150 __ set(const_addrlit, O7);
1151 __ ld(O7, 0, to_reg->as_register());
1152 }
1153 }
1154 break;
1155
1156 case T_DOUBLE:
1157 {
1158 address const_addr = __ double_constant(c->as_jdouble());
1159 if (const_addr == NULL) {
1160 bailout("const section overflow");
1161 break;
1162 }
1163 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1164
1165 if (to_reg->is_double_fpu()) {
1166 AddressLiteral const_addrlit(const_addr, rspec);
1167 __ patchable_sethi(const_addrlit, O7);
1168 __ relocate(rspec);
1169 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1170 } else {
1171 assert(to_reg->is_double_cpu(), "Must be a long register.");
1172 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1173 }
1174
1175 }
1176 break;
1177
1178 default:
1179 ShouldNotReachHere();
1180 }
1181 }
1182
1183 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1184 Register reg = addr->base()->as_pointer_register();
1185 LIR_Opr index = addr->index();
1186 if (index->is_illegal()) {
1187 return Address(reg, addr->disp());
1188 } else {
1189 assert (addr->disp() == 0, "unsupported address mode");
1190 return Address(reg, index->as_pointer_register());
1191 }
1192 }
1193
1194
1195 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1196 switch (type) {
1197 case T_INT:
1198 case T_FLOAT: {
1199 Register tmp = O7;
1200 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1201 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1202 __ lduw(from.base(), from.disp(), tmp);
1203 __ stw(tmp, to.base(), to.disp());
1204 break;
1205 }
1206 case T_ADDRESS:
1207 case T_OBJECT: {
1208 Register tmp = O7;
1209 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1210 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1211 __ ld_ptr(from.base(), from.disp(), tmp);
1212 __ st_ptr(tmp, to.base(), to.disp());
1213 break;
1214 }
1215 case T_LONG:
1216 case T_DOUBLE: {
1217 Register tmp = O7;
1218 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1219 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1220 __ lduw(from.base(), from.disp(), tmp);
1221 __ stw(tmp, to.base(), to.disp());
1222 __ lduw(from.base(), from.disp() + 4, tmp);
1223 __ stw(tmp, to.base(), to.disp() + 4);
1224 break;
1225 }
1226
1227 default:
1228 ShouldNotReachHere();
1229 }
1230 }
1231
1232
1233 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1234 Address base = as_Address(addr);
1235 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1236 }
1237
1238
1239 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1240 Address base = as_Address(addr);
1241 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1242 }
1243
1244
1245 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1246 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1247
1248 assert(type != T_METADATA, "load of metadata ptr not supported");
1249 LIR_Address* addr = src_opr->as_address_ptr();
1250 LIR_Opr to_reg = dest;
1251
1252 Register src = addr->base()->as_pointer_register();
1253 Register disp_reg = noreg;
1254 int disp_value = addr->disp();
1255 bool needs_patching = (patch_code != lir_patch_none);
1256
1257 if (addr->base()->type() == T_OBJECT) {
1258 __ verify_oop(src);
1259 }
1260
1261 PatchingStub* patch = NULL;
1262 if (needs_patching) {
1263 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1264 assert(!to_reg->is_double_cpu() ||
1265 patch_code == lir_patch_none ||
1266 patch_code == lir_patch_normal, "patching doesn't match register");
1267 }
1268
1269 if (addr->index()->is_illegal()) {
1270 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1271 if (needs_patching) {
1272 __ patchable_set(0, O7);
1273 } else {
1274 __ set(disp_value, O7);
1275 }
1276 disp_reg = O7;
1277 }
1278 } else if (unaligned || PatchALot) {
1279 __ add(src, addr->index()->as_pointer_register(), O7);
1280 src = O7;
1281 } else {
1282 disp_reg = addr->index()->as_pointer_register();
1283 assert(disp_value == 0, "can't handle 3 operand addresses");
1284 }
1285
1286 // remember the offset of the load. The patching_epilog must be done
1287 // before the call to add_debug_info, otherwise the PcDescs don't get
1288 // entered in increasing order.
1289 int offset = code_offset();
1290
1291 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1292 if (disp_reg == noreg) {
1293 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1294 } else {
1295 assert(!unaligned, "can't handle this");
1296 offset = load(src, disp_reg, to_reg, type, wide);
1297 }
1298
1299 if (patch != NULL) {
1300 patching_epilog(patch, patch_code, src, info);
1301 }
1302 if (info != NULL) add_debug_info_for_null_check(offset, info);
1303 }
1304
1305
1306 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1307 Address addr;
1308 if (src->is_single_word()) {
1309 addr = frame_map()->address_for_slot(src->single_stack_ix());
1310 } else if (src->is_double_word()) {
1311 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1312 }
1313
1314 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1315 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1316 }
1317
1318
1319 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1320 Address addr;
1321 if (dest->is_single_word()) {
1322 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1323 } else if (dest->is_double_word()) {
1324 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1325 }
1326 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1327 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1328 }
1329
1330
1331 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1332 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1333 if (from_reg->is_double_fpu()) {
1334 // double to double moves
1335 assert(to_reg->is_double_fpu(), "should match");
1336 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1337 } else {
1338 // float to float moves
1339 assert(to_reg->is_single_fpu(), "should match");
1340 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1341 }
1342 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1343 if (from_reg->is_double_cpu()) {
1344 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1345 } else if (to_reg->is_double_cpu()) {
1346 // int to int moves
1347 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1348 } else {
1349 // int to int moves
1350 __ mov(from_reg->as_register(), to_reg->as_register());
1351 }
1352 } else {
1353 ShouldNotReachHere();
1354 }
1355 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1356 __ verify_oop(to_reg->as_register());
1357 }
1358 }
1359
1360 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1361 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1362 bool wide, bool unaligned) {
1363 assert(type != T_METADATA, "store of metadata ptr not supported");
1364 LIR_Address* addr = dest->as_address_ptr();
1365
1366 Register src = addr->base()->as_pointer_register();
1367 Register disp_reg = noreg;
1368 int disp_value = addr->disp();
1369 bool needs_patching = (patch_code != lir_patch_none);
1370
1371 if (addr->base()->is_oop_register()) {
1372 __ verify_oop(src);
1373 }
1374
1375 PatchingStub* patch = NULL;
1376 if (needs_patching) {
1377 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1378 assert(!from_reg->is_double_cpu() ||
1379 patch_code == lir_patch_none ||
1380 patch_code == lir_patch_normal, "patching doesn't match register");
1381 }
1382
1383 if (addr->index()->is_illegal()) {
1384 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1385 if (needs_patching) {
1386 __ patchable_set(0, O7);
1387 } else {
1388 __ set(disp_value, O7);
1389 }
1390 disp_reg = O7;
1391 }
1392 } else if (unaligned || PatchALot) {
1393 __ add(src, addr->index()->as_pointer_register(), O7);
1394 src = O7;
1395 } else {
1396 disp_reg = addr->index()->as_pointer_register();
1397 assert(disp_value == 0, "can't handle 3 operand addresses");
1398 }
1399
1400 // remember the offset of the store. The patching_epilog must be done
1401 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1402 // entered in increasing order.
1403 int offset;
1404
1405 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1406 if (disp_reg == noreg) {
1407 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1408 } else {
1409 assert(!unaligned, "can't handle this");
1410 offset = store(from_reg, src, disp_reg, type, wide);
1411 }
1412
1413 if (patch != NULL) {
1414 patching_epilog(patch, patch_code, src, info);
1415 }
1416
1417 if (info != NULL) add_debug_info_for_null_check(offset, info);
1418 }
1419
1420
1421 void LIR_Assembler::return_op(LIR_Opr result) {
1422 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1423 __ reserved_stack_check();
1424 }
1425 if (SafepointMechanism::uses_thread_local_poll()) {
1426 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0);
1427 } else {
1428 __ set((intptr_t)os::get_polling_page(), L0);
1429 }
1430 __ relocate(relocInfo::poll_return_type);
1431 __ ld_ptr(L0, 0, G0);
1432 __ ret();
1433 __ delayed()->restore();
1434 }
1435
1436
1437 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1438 if (SafepointMechanism::uses_thread_local_poll()) {
1439 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), tmp->as_register());
1440 } else {
1441 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1442 }
1443 if (info != NULL) {
1444 add_debug_info_for_branch(info);
1445 }
1446 int offset = __ offset();
1447
1448 __ relocate(relocInfo::poll_type);
1449 __ ld_ptr(tmp->as_register(), 0, G0);
1450 return offset;
1451 }
1452
1453
1454 void LIR_Assembler::emit_static_call_stub() {
1455 address call_pc = __ pc();
1456 address stub = __ start_a_stub(call_stub_size());
1457 if (stub == NULL) {
1458 bailout("static call stub overflow");
1459 return;
1460 }
1461
1462 int start = __ offset();
1463 __ relocate(static_stub_Relocation::spec(call_pc));
1464
1465 __ set_metadata(NULL, G5);
1466 // must be set to -1 at code generation time
1467 AddressLiteral addrlit(-1);
1468 __ jump_to(addrlit, G3);
1469 __ delayed()->nop();
1470
1471 assert(__ offset() - start <= call_stub_size(), "stub too big");
1472 __ end_a_stub();
1473 }
1474
1475
1476 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1477 if (opr1->is_single_fpu()) {
1478 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1479 } else if (opr1->is_double_fpu()) {
1480 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1481 } else if (opr1->is_single_cpu()) {
1482 if (opr2->is_constant()) {
1483 switch (opr2->as_constant_ptr()->type()) {
1484 case T_INT:
1485 { jint con = opr2->as_constant_ptr()->as_jint();
1486 if (Assembler::is_simm13(con)) {
1487 __ cmp(opr1->as_register(), con);
1488 } else {
1489 __ set(con, O7);
1490 __ cmp(opr1->as_register(), O7);
1491 }
1492 }
1493 break;
1494
1495 case T_OBJECT:
1496 // there are only equal/notequal comparisions on objects
1497 { jobject con = opr2->as_constant_ptr()->as_jobject();
1498 if (con == NULL) {
1499 __ cmp(opr1->as_register(), 0);
1500 } else {
1501 jobject2reg(con, O7);
1502 __ cmp(opr1->as_register(), O7);
1503 }
1504 }
1505 break;
1506
1507 default:
1508 ShouldNotReachHere();
1509 break;
1510 }
1511 } else {
1512 if (opr2->is_address()) {
1513 LIR_Address * addr = opr2->as_address_ptr();
1514 BasicType type = addr->type();
1515 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1516 else __ ld(as_Address(addr), O7);
1517 __ cmp(opr1->as_register(), O7);
1518 } else {
1519 __ cmp(opr1->as_register(), opr2->as_register());
1520 }
1521 }
1522 } else if (opr1->is_double_cpu()) {
1523 Register xlo = opr1->as_register_lo();
1524 Register xhi = opr1->as_register_hi();
1525 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1526 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1527 __ orcc(xhi, G0, G0);
1528 } else if (opr2->is_register()) {
1529 Register ylo = opr2->as_register_lo();
1530 Register yhi = opr2->as_register_hi();
1531 __ cmp(xlo, ylo);
1532 } else {
1533 ShouldNotReachHere();
1534 }
1535 } else if (opr1->is_address()) {
1536 LIR_Address * addr = opr1->as_address_ptr();
1537 BasicType type = addr->type();
1538 assert (opr2->is_constant(), "Checking");
1539 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1540 else __ ld(as_Address(addr), O7);
1541 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1542 } else {
1543 ShouldNotReachHere();
1544 }
1545 }
1546
1547
1548 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1549 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1550 bool is_unordered_less = (code == lir_ucmp_fd2i);
1551 if (left->is_single_fpu()) {
1552 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1553 } else if (left->is_double_fpu()) {
1554 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1555 } else {
1556 ShouldNotReachHere();
1557 }
1558 } else if (code == lir_cmp_l2i) {
1559 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1560 } else {
1561 ShouldNotReachHere();
1562 }
1563 }
1564
1565
1566 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1567 Assembler::Condition acond;
1568 switch (condition) {
1569 case lir_cond_equal: acond = Assembler::equal; break;
1570 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1571 case lir_cond_less: acond = Assembler::less; break;
1572 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1573 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1574 case lir_cond_greater: acond = Assembler::greater; break;
1575 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1576 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1577 default: ShouldNotReachHere();
1578 };
1579
1580 if (opr1->is_constant() && opr1->type() == T_INT) {
1581 Register dest = result->as_register();
1582 // load up first part of constant before branch
1583 // and do the rest in the delay slot.
1584 if (!Assembler::is_simm13(opr1->as_jint())) {
1585 __ sethi(opr1->as_jint(), dest);
1586 }
1587 } else if (opr1->is_constant()) {
1588 const2reg(opr1, result, lir_patch_none, NULL);
1589 } else if (opr1->is_register()) {
1590 reg2reg(opr1, result);
1591 } else if (opr1->is_stack()) {
1592 stack2reg(opr1, result, result->type());
1593 } else {
1594 ShouldNotReachHere();
1595 }
1596 Label skip;
1597 if (type == T_INT) {
1598 __ br(acond, false, Assembler::pt, skip);
1599 } else {
1600 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1601 }
1602 if (opr1->is_constant() && opr1->type() == T_INT) {
1603 Register dest = result->as_register();
1604 if (Assembler::is_simm13(opr1->as_jint())) {
1605 __ delayed()->or3(G0, opr1->as_jint(), dest);
1606 } else {
1607 // the sethi has been done above, so just put in the low 10 bits
1608 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1609 }
1610 } else {
1611 // can't do anything useful in the delay slot
1612 __ delayed()->nop();
1613 }
1614 if (opr2->is_constant()) {
1615 const2reg(opr2, result, lir_patch_none, NULL);
1616 } else if (opr2->is_register()) {
1617 reg2reg(opr2, result);
1618 } else if (opr2->is_stack()) {
1619 stack2reg(opr2, result, result->type());
1620 } else {
1621 ShouldNotReachHere();
1622 }
1623 __ bind(skip);
1624 }
1625
1626
1627 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1628 assert(info == NULL, "unused on this code path");
1629 assert(left->is_register(), "wrong items state");
1630 assert(dest->is_register(), "wrong items state");
1631
1632 if (right->is_register()) {
1633 if (dest->is_float_kind()) {
1634
1635 FloatRegister lreg, rreg, res;
1636 FloatRegisterImpl::Width w;
1637 if (right->is_single_fpu()) {
1638 w = FloatRegisterImpl::S;
1639 lreg = left->as_float_reg();
1640 rreg = right->as_float_reg();
1641 res = dest->as_float_reg();
1642 } else {
1643 w = FloatRegisterImpl::D;
1644 lreg = left->as_double_reg();
1645 rreg = right->as_double_reg();
1646 res = dest->as_double_reg();
1647 }
1648
1649 switch (code) {
1650 case lir_add: __ fadd(w, lreg, rreg, res); break;
1651 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1652 case lir_mul: // fall through
1653 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1654 case lir_div: // fall through
1655 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1656 default: ShouldNotReachHere();
1657 }
1658
1659 } else if (dest->is_double_cpu()) {
1660 Register dst_lo = dest->as_register_lo();
1661 Register op1_lo = left->as_pointer_register();
1662 Register op2_lo = right->as_pointer_register();
1663
1664 switch (code) {
1665 case lir_add:
1666 __ add(op1_lo, op2_lo, dst_lo);
1667 break;
1668
1669 case lir_sub:
1670 __ sub(op1_lo, op2_lo, dst_lo);
1671 break;
1672
1673 default: ShouldNotReachHere();
1674 }
1675 } else {
1676 assert (right->is_single_cpu(), "Just Checking");
1677
1678 Register lreg = left->as_register();
1679 Register res = dest->as_register();
1680 Register rreg = right->as_register();
1681 switch (code) {
1682 case lir_add: __ add (lreg, rreg, res); break;
1683 case lir_sub: __ sub (lreg, rreg, res); break;
1684 case lir_mul: __ mulx (lreg, rreg, res); break;
1685 default: ShouldNotReachHere();
1686 }
1687 }
1688 } else {
1689 assert (right->is_constant(), "must be constant");
1690
1691 if (dest->is_single_cpu()) {
1692 Register lreg = left->as_register();
1693 Register res = dest->as_register();
1694 int simm13 = right->as_constant_ptr()->as_jint();
1695
1696 switch (code) {
1697 case lir_add: __ add (lreg, simm13, res); break;
1698 case lir_sub: __ sub (lreg, simm13, res); break;
1699 case lir_mul: __ mulx (lreg, simm13, res); break;
1700 default: ShouldNotReachHere();
1701 }
1702 } else {
1703 Register lreg = left->as_pointer_register();
1704 Register res = dest->as_register_lo();
1705 long con = right->as_constant_ptr()->as_jlong();
1706 assert(Assembler::is_simm13(con), "must be simm13");
1707
1708 switch (code) {
1709 case lir_add: __ add (lreg, (int)con, res); break;
1710 case lir_sub: __ sub (lreg, (int)con, res); break;
1711 case lir_mul: __ mulx (lreg, (int)con, res); break;
1712 default: ShouldNotReachHere();
1713 }
1714 }
1715 }
1716 }
1717
1718
1719 void LIR_Assembler::fpop() {
1720 // do nothing
1721 }
1722
1723
1724 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1725 switch (code) {
1726 case lir_tan: {
1727 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1728 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1729 break;
1730 }
1731 case lir_sqrt: {
1732 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1733 FloatRegister src_reg = value->as_double_reg();
1734 FloatRegister dst_reg = dest->as_double_reg();
1735 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1736 break;
1737 }
1738 case lir_abs: {
1739 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1740 FloatRegister src_reg = value->as_double_reg();
1741 FloatRegister dst_reg = dest->as_double_reg();
1742 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1743 break;
1744 }
1745 default: {
1746 ShouldNotReachHere();
1747 break;
1748 }
1749 }
1750 }
1751
1752
1753 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1754 if (right->is_constant()) {
1755 if (dest->is_single_cpu()) {
1756 int simm13 = right->as_constant_ptr()->as_jint();
1757 switch (code) {
1758 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1759 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1760 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1761 default: ShouldNotReachHere();
1762 }
1763 } else {
1764 long c = right->as_constant_ptr()->as_jlong();
1765 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1766 int simm13 = (int)c;
1767 switch (code) {
1768 case lir_logic_and:
1769 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1770 break;
1771
1772 case lir_logic_or:
1773 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1774 break;
1775
1776 case lir_logic_xor:
1777 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1778 break;
1779
1780 default: ShouldNotReachHere();
1781 }
1782 }
1783 } else {
1784 assert(right->is_register(), "right should be in register");
1785
1786 if (dest->is_single_cpu()) {
1787 switch (code) {
1788 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1789 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1790 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1791 default: ShouldNotReachHere();
1792 }
1793 } else {
1794 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1795 left->as_register_lo();
1796 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1797 right->as_register_lo();
1798
1799 switch (code) {
1800 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1801 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1802 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1803 default: ShouldNotReachHere();
1804 }
1805 }
1806 }
1807 }
1808
1809
1810 int LIR_Assembler::shift_amount(BasicType t) {
1811 int elem_size = type2aelembytes(t);
1812 switch (elem_size) {
1813 case 1 : return 0;
1814 case 2 : return 1;
1815 case 4 : return 2;
1816 case 8 : return 3;
1817 }
1818 ShouldNotReachHere();
1819 return -1;
1820 }
1821
1822
1823 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1824 assert(exceptionOop->as_register() == Oexception, "should match");
1825 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1826
1827 info->add_register_oop(exceptionOop);
1828
1829 // reuse the debug info from the safepoint poll for the throw op itself
1830 address pc_for_athrow = __ pc();
1831 int pc_for_athrow_offset = __ offset();
1832 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1833 __ set(pc_for_athrow, Oissuing_pc, rspec);
1834 add_call_info(pc_for_athrow_offset, info); // for exception handler
1835
1836 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1837 __ delayed()->nop();
1838 }
1839
1840
1841 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1842 assert(exceptionOop->as_register() == Oexception, "should match");
1843
1844 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1845 __ delayed()->nop();
1846 }
1847
1848 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1849 Register src = op->src()->as_register();
1850 Register dst = op->dst()->as_register();
1851 Register src_pos = op->src_pos()->as_register();
1852 Register dst_pos = op->dst_pos()->as_register();
1853 Register length = op->length()->as_register();
1854 Register tmp = op->tmp()->as_register();
1855 Register tmp2 = O7;
1856
1857 int flags = op->flags();
1858 ciArrayKlass* default_type = op->expected_type();
1859 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1860 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1861
1862 // higher 32bits must be null
1863 __ sra(dst_pos, 0, dst_pos);
1864 __ sra(src_pos, 0, src_pos);
1865 __ sra(length, 0, length);
1866
1867 // set up the arraycopy stub information
1868 ArrayCopyStub* stub = op->stub();
1869
1870 // always do stub if no type information is available. it's ok if
1871 // the known type isn't loaded since the code sanity checks
1872 // in debug mode and the type isn't required when we know the exact type
1873 // also check that the type is an array type.
1874 if (op->expected_type() == NULL) {
1875 __ mov(src, O0);
1876 __ mov(src_pos, O1);
1877 __ mov(dst, O2);
1878 __ mov(dst_pos, O3);
1879 __ mov(length, O4);
1880 address copyfunc_addr = StubRoutines::generic_arraycopy();
1881 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1882
1883 #ifndef PRODUCT
1884 if (PrintC1Statistics) {
1885 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1886 __ inc_counter(counter, G1, G3);
1887 }
1888 #endif
1889 __ call_VM_leaf(tmp, copyfunc_addr);
1890
1891 __ xor3(O0, -1, tmp);
1892 __ sub(length, tmp, length);
1893 __ add(src_pos, tmp, src_pos);
1894 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1895 __ delayed()->add(dst_pos, tmp, dst_pos);
1896 __ bind(*stub->continuation());
1897 return;
1898 }
1899
1900 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1901
1902 // make sure src and dst are non-null and load array length
1903 if (flags & LIR_OpArrayCopy::src_null_check) {
1904 __ tst(src);
1905 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1906 __ delayed()->nop();
1907 }
1908
1909 if (flags & LIR_OpArrayCopy::dst_null_check) {
1910 __ tst(dst);
1911 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1912 __ delayed()->nop();
1913 }
1914
1915 // If the compiler was not able to prove that exact type of the source or the destination
1916 // of the arraycopy is an array type, check at runtime if the source or the destination is
1917 // an instance type.
1918 if (flags & LIR_OpArrayCopy::type_check) {
1919 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
1920 __ load_klass(dst, tmp);
1921 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1922 __ cmp(tmp2, Klass::_lh_neutral_value);
1923 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1924 __ delayed()->nop();
1925 }
1926
1927 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
1928 __ load_klass(src, tmp);
1929 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1930 __ cmp(tmp2, Klass::_lh_neutral_value);
1931 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1932 __ delayed()->nop();
1933 }
1934 }
1935
1936 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1937 // test src_pos register
1938 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1939 __ delayed()->nop();
1940 }
1941
1942 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1943 // test dst_pos register
1944 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1945 __ delayed()->nop();
1946 }
1947
1948 if (flags & LIR_OpArrayCopy::length_positive_check) {
1949 // make sure length isn't negative
1950 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1951 __ delayed()->nop();
1952 }
1953
1954 if (flags & LIR_OpArrayCopy::src_range_check) {
1955 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1956 __ add(length, src_pos, tmp);
1957 __ cmp(tmp2, tmp);
1958 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1959 __ delayed()->nop();
1960 }
1961
1962 if (flags & LIR_OpArrayCopy::dst_range_check) {
1963 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1964 __ add(length, dst_pos, tmp);
1965 __ cmp(tmp2, tmp);
1966 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1967 __ delayed()->nop();
1968 }
1969
1970 int shift = shift_amount(basic_type);
1971
1972 if (flags & LIR_OpArrayCopy::type_check) {
1973 // We don't know the array types are compatible
1974 if (basic_type != T_OBJECT) {
1975 // Simple test for basic type arrays
1976 if (UseCompressedClassPointers) {
1977 // We don't need decode because we just need to compare
1978 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1979 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1980 __ cmp(tmp, tmp2);
1981 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1982 } else {
1983 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1984 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1985 __ cmp(tmp, tmp2);
1986 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1987 }
1988 __ delayed()->nop();
1989 } else {
1990 // For object arrays, if src is a sub class of dst then we can
1991 // safely do the copy.
1992 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1993
1994 Label cont, slow;
1995 assert_different_registers(tmp, tmp2, G3, G1);
1996
1997 __ load_klass(src, G3);
1998 __ load_klass(dst, G1);
1999
2000 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2001
2002 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2003 __ delayed()->nop();
2004
2005 __ cmp(G3, 0);
2006 if (copyfunc_addr != NULL) { // use stub if available
2007 // src is not a sub class of dst so we have to do a
2008 // per-element check.
2009 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2010 __ delayed()->nop();
2011
2012 __ bind(slow);
2013
2014 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2015 if ((flags & mask) != mask) {
2016 // Check that at least both of them object arrays.
2017 assert(flags & mask, "one of the two should be known to be an object array");
2018
2019 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2020 __ load_klass(src, tmp);
2021 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2022 __ load_klass(dst, tmp);
2023 }
2024 int lh_offset = in_bytes(Klass::layout_helper_offset());
2025
2026 __ lduw(tmp, lh_offset, tmp2);
2027
2028 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2029 __ set(objArray_lh, tmp);
2030 __ cmp(tmp, tmp2);
2031 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2032 __ delayed()->nop();
2033 }
2034
2035 Register src_ptr = O0;
2036 Register dst_ptr = O1;
2037 Register len = O2;
2038 Register chk_off = O3;
2039 Register super_k = O4;
2040
2041 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2042 if (shift == 0) {
2043 __ add(src_ptr, src_pos, src_ptr);
2044 } else {
2045 __ sll(src_pos, shift, tmp);
2046 __ add(src_ptr, tmp, src_ptr);
2047 }
2048
2049 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2050 if (shift == 0) {
2051 __ add(dst_ptr, dst_pos, dst_ptr);
2052 } else {
2053 __ sll(dst_pos, shift, tmp);
2054 __ add(dst_ptr, tmp, dst_ptr);
2055 }
2056 __ mov(length, len);
2057 __ load_klass(dst, tmp);
2058
2059 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2060 __ ld_ptr(tmp, ek_offset, super_k);
2061
2062 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2063 __ lduw(super_k, sco_offset, chk_off);
2064
2065 __ call_VM_leaf(tmp, copyfunc_addr);
2066
2067 #ifndef PRODUCT
2068 if (PrintC1Statistics) {
2069 Label failed;
2070 __ br_notnull_short(O0, Assembler::pn, failed);
2071 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2072 __ bind(failed);
2073 }
2074 #endif
2075
2076 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2077 __ delayed()->xor3(O0, -1, tmp);
2078
2079 #ifndef PRODUCT
2080 if (PrintC1Statistics) {
2081 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2082 }
2083 #endif
2084
2085 __ sub(length, tmp, length);
2086 __ add(src_pos, tmp, src_pos);
2087 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2088 __ delayed()->add(dst_pos, tmp, dst_pos);
2089
2090 __ bind(cont);
2091 } else {
2092 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2093 __ delayed()->nop();
2094 __ bind(cont);
2095 }
2096 }
2097 }
2098
2099 #ifdef ASSERT
2100 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2101 // Sanity check the known type with the incoming class. For the
2102 // primitive case the types must match exactly with src.klass and
2103 // dst.klass each exactly matching the default type. For the
2104 // object array case, if no type check is needed then either the
2105 // dst type is exactly the expected type and the src type is a
2106 // subtype which we can't check or src is the same array as dst
2107 // but not necessarily exactly of type default_type.
2108 Label known_ok, halt;
2109 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2110 if (UseCompressedClassPointers) {
2111 // tmp holds the default type. It currently comes uncompressed after the
2112 // load of a constant, so encode it.
2113 __ encode_klass_not_null(tmp);
2114 // load the raw value of the dst klass, since we will be comparing
2115 // uncompressed values directly.
2116 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2117 if (basic_type != T_OBJECT) {
2118 __ cmp(tmp, tmp2);
2119 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2120 // load the raw value of the src klass.
2121 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2122 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2123 } else {
2124 __ cmp(tmp, tmp2);
2125 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2126 __ delayed()->cmp(src, dst);
2127 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2128 __ delayed()->nop();
2129 }
2130 } else {
2131 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2132 if (basic_type != T_OBJECT) {
2133 __ cmp(tmp, tmp2);
2134 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2135 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2136 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2137 } else {
2138 __ cmp(tmp, tmp2);
2139 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2140 __ delayed()->cmp(src, dst);
2141 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2142 __ delayed()->nop();
2143 }
2144 }
2145 __ bind(halt);
2146 __ stop("incorrect type information in arraycopy");
2147 __ bind(known_ok);
2148 }
2149 #endif
2150
2151 #ifndef PRODUCT
2152 if (PrintC1Statistics) {
2153 address counter = Runtime1::arraycopy_count_address(basic_type);
2154 __ inc_counter(counter, G1, G3);
2155 }
2156 #endif
2157
2158 Register src_ptr = O0;
2159 Register dst_ptr = O1;
2160 Register len = O2;
2161
2162 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2163 if (shift == 0) {
2164 __ add(src_ptr, src_pos, src_ptr);
2165 } else {
2166 __ sll(src_pos, shift, tmp);
2167 __ add(src_ptr, tmp, src_ptr);
2168 }
2169
2170 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2171 if (shift == 0) {
2172 __ add(dst_ptr, dst_pos, dst_ptr);
2173 } else {
2174 __ sll(dst_pos, shift, tmp);
2175 __ add(dst_ptr, tmp, dst_ptr);
2176 }
2177
2178 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2179 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2180 const char *name;
2181 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2182
2183 // arraycopy stubs takes a length in number of elements, so don't scale it.
2184 __ mov(length, len);
2185 __ call_VM_leaf(tmp, entry);
2186
2187 __ bind(*stub->continuation());
2188 }
2189
2190
2191 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2192 if (dest->is_single_cpu()) {
2193 if (left->type() == T_OBJECT) {
2194 switch (code) {
2195 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2196 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2197 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2198 default: ShouldNotReachHere();
2199 }
2200 } else
2201 switch (code) {
2202 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2203 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2204 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2205 default: ShouldNotReachHere();
2206 }
2207 } else {
2208 switch (code) {
2209 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2210 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2211 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2212 default: ShouldNotReachHere();
2213 }
2214 }
2215 }
2216
2217
2218 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2219 if (left->type() == T_OBJECT) {
2220 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2221 Register l = left->as_register();
2222 Register d = dest->as_register_lo();
2223 switch (code) {
2224 case lir_shl: __ sllx (l, count, d); break;
2225 case lir_shr: __ srax (l, count, d); break;
2226 case lir_ushr: __ srlx (l, count, d); break;
2227 default: ShouldNotReachHere();
2228 }
2229 return;
2230 }
2231
2232 if (dest->is_single_cpu()) {
2233 count = count & 0x1F; // Java spec
2234 switch (code) {
2235 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2236 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2237 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2238 default: ShouldNotReachHere();
2239 }
2240 } else if (dest->is_double_cpu()) {
2241 count = count & 63; // Java spec
2242 switch (code) {
2243 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2244 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2245 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2246 default: ShouldNotReachHere();
2247 }
2248 } else {
2249 ShouldNotReachHere();
2250 }
2251 }
2252
2253
2254 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2255 assert(op->tmp1()->as_register() == G1 &&
2256 op->tmp2()->as_register() == G3 &&
2257 op->tmp3()->as_register() == G4 &&
2258 op->obj()->as_register() == O0 &&
2259 op->klass()->as_register() == G5, "must be");
2260 if (op->init_check()) {
2261 add_debug_info_for_null_check_here(op->stub()->info());
2262 __ ldub(op->klass()->as_register(),
2263 in_bytes(InstanceKlass::init_state_offset()),
2264 op->tmp1()->as_register());
2265 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2266 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2267 __ delayed()->nop();
2268 }
2269 __ allocate_object(op->obj()->as_register(),
2270 op->tmp1()->as_register(),
2271 op->tmp2()->as_register(),
2272 op->tmp3()->as_register(),
2273 op->header_size(),
2274 op->object_size(),
2275 op->klass()->as_register(),
2276 *op->stub()->entry());
2277 __ bind(*op->stub()->continuation());
2278 __ verify_oop(op->obj()->as_register());
2279 }
2280
2281
2282 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2283 assert(op->tmp1()->as_register() == G1 &&
2284 op->tmp2()->as_register() == G3 &&
2285 op->tmp3()->as_register() == G4 &&
2286 op->tmp4()->as_register() == O1 &&
2287 op->klass()->as_register() == G5, "must be");
2288
2289 __ signx(op->len()->as_register());
2290 if (UseSlowPath ||
2291 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2292 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2293 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2294 __ delayed()->nop();
2295 } else {
2296 __ allocate_array(op->obj()->as_register(),
2297 op->len()->as_register(),
2298 op->tmp1()->as_register(),
2299 op->tmp2()->as_register(),
2300 op->tmp3()->as_register(),
2301 arrayOopDesc::header_size(op->type()),
2302 type2aelembytes(op->type()),
2303 op->klass()->as_register(),
2304 *op->stub()->entry());
2305 }
2306 __ bind(*op->stub()->continuation());
2307 }
2308
2309
2310 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2311 ciMethodData *md, ciProfileData *data,
2312 Register recv, Register tmp1, Label* update_done) {
2313 uint i;
2314 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2315 Label next_test;
2316 // See if the receiver is receiver[n].
2317 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2318 mdo_offset_bias);
2319 __ ld_ptr(receiver_addr, tmp1);
2320 __ verify_klass_ptr(tmp1);
2321 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2322 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2323 mdo_offset_bias);
2324 __ ld_ptr(data_addr, tmp1);
2325 __ add(tmp1, DataLayout::counter_increment, tmp1);
2326 __ st_ptr(tmp1, data_addr);
2327 __ ba(*update_done);
2328 __ delayed()->nop();
2329 __ bind(next_test);
2330 }
2331
2332 // Didn't find receiver; find next empty slot and fill it in
2333 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2334 Label next_test;
2335 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2336 mdo_offset_bias);
2337 __ ld_ptr(recv_addr, tmp1);
2338 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2339 __ st_ptr(recv, recv_addr);
2340 __ set(DataLayout::counter_increment, tmp1);
2341 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2342 mdo_offset_bias);
2343 __ ba(*update_done);
2344 __ delayed()->nop();
2345 __ bind(next_test);
2346 }
2347 }
2348
2349
2350 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2351 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2352 md = method->method_data_or_null();
2353 assert(md != NULL, "Sanity");
2354 data = md->bci_to_data(bci);
2355 assert(data != NULL, "need data for checkcast");
2356 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2357 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2358 // The offset is large so bias the mdo by the base of the slot so
2359 // that the ld can use simm13s to reference the slots of the data
2360 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2361 }
2362 }
2363
2364 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2365 // we always need a stub for the failure case.
2366 CodeStub* stub = op->stub();
2367 Register obj = op->object()->as_register();
2368 Register k_RInfo = op->tmp1()->as_register();
2369 Register klass_RInfo = op->tmp2()->as_register();
2370 Register dst = op->result_opr()->as_register();
2371 Register Rtmp1 = op->tmp3()->as_register();
2372 ciKlass* k = op->klass();
2373
2374
2375 if (obj == k_RInfo) {
2376 k_RInfo = klass_RInfo;
2377 klass_RInfo = obj;
2378 }
2379
2380 ciMethodData* md;
2381 ciProfileData* data;
2382 int mdo_offset_bias = 0;
2383 if (op->should_profile()) {
2384 ciMethod* method = op->profiled_method();
2385 assert(method != NULL, "Should have method");
2386 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2387
2388 Label not_null;
2389 __ br_notnull_short(obj, Assembler::pn, not_null);
2390 Register mdo = k_RInfo;
2391 Register data_val = Rtmp1;
2392 metadata2reg(md->constant_encoding(), mdo);
2393 if (mdo_offset_bias > 0) {
2394 __ set(mdo_offset_bias, data_val);
2395 __ add(mdo, data_val, mdo);
2396 }
2397 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2398 __ ldub(flags_addr, data_val);
2399 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2400 __ stb(data_val, flags_addr);
2401 __ ba(*obj_is_null);
2402 __ delayed()->nop();
2403 __ bind(not_null);
2404 } else {
2405 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2406 __ delayed()->nop();
2407 }
2408
2409 Label profile_cast_failure, profile_cast_success;
2410 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2411 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2412
2413 // patching may screw with our temporaries on sparc,
2414 // so let's do it before loading the class
2415 if (k->is_loaded()) {
2416 metadata2reg(k->constant_encoding(), k_RInfo);
2417 } else {
2418 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2419 }
2420 assert(obj != k_RInfo, "must be different");
2421
2422 // get object class
2423 // not a safepoint as obj null check happens earlier
2424 __ load_klass(obj, klass_RInfo);
2425 if (op->fast_check()) {
2426 assert_different_registers(klass_RInfo, k_RInfo);
2427 __ cmp(k_RInfo, klass_RInfo);
2428 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2429 __ delayed()->nop();
2430 } else {
2431 bool need_slow_path = true;
2432 if (k->is_loaded()) {
2433 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2434 need_slow_path = false;
2435 // perform the fast part of the checking logic
2436 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2437 (need_slow_path ? success_target : NULL),
2438 failure_target, NULL,
2439 RegisterOrConstant(k->super_check_offset()));
2440 } else {
2441 // perform the fast part of the checking logic
2442 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2443 failure_target, NULL);
2444 }
2445 if (need_slow_path) {
2446 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2447 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2448 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2449 __ delayed()->nop();
2450 __ cmp(G3, 0);
2451 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2452 __ delayed()->nop();
2453 // Fall through to success case
2454 }
2455 }
2456
2457 if (op->should_profile()) {
2458 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2459 assert_different_registers(obj, mdo, recv, tmp1);
2460 __ bind(profile_cast_success);
2461 metadata2reg(md->constant_encoding(), mdo);
2462 if (mdo_offset_bias > 0) {
2463 __ set(mdo_offset_bias, tmp1);
2464 __ add(mdo, tmp1, mdo);
2465 }
2466 __ load_klass(obj, recv);
2467 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2468 // Jump over the failure case
2469 __ ba(*success);
2470 __ delayed()->nop();
2471 // Cast failure case
2472 __ bind(profile_cast_failure);
2473 metadata2reg(md->constant_encoding(), mdo);
2474 if (mdo_offset_bias > 0) {
2475 __ set(mdo_offset_bias, tmp1);
2476 __ add(mdo, tmp1, mdo);
2477 }
2478 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2479 __ ld_ptr(data_addr, tmp1);
2480 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2481 __ st_ptr(tmp1, data_addr);
2482 __ ba(*failure);
2483 __ delayed()->nop();
2484 }
2485 __ ba(*success);
2486 __ delayed()->nop();
2487 }
2488
2489 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2490 LIR_Code code = op->code();
2491 if (code == lir_store_check) {
2492 Register value = op->object()->as_register();
2493 Register array = op->array()->as_register();
2494 Register k_RInfo = op->tmp1()->as_register();
2495 Register klass_RInfo = op->tmp2()->as_register();
2496 Register Rtmp1 = op->tmp3()->as_register();
2497
2498 __ verify_oop(value);
2499 CodeStub* stub = op->stub();
2500 // check if it needs to be profiled
2501 ciMethodData* md;
2502 ciProfileData* data;
2503 int mdo_offset_bias = 0;
2504 if (op->should_profile()) {
2505 ciMethod* method = op->profiled_method();
2506 assert(method != NULL, "Should have method");
2507 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2508 }
2509 Label profile_cast_success, profile_cast_failure, done;
2510 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2511 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2512
2513 if (op->should_profile()) {
2514 Label not_null;
2515 __ br_notnull_short(value, Assembler::pn, not_null);
2516 Register mdo = k_RInfo;
2517 Register data_val = Rtmp1;
2518 metadata2reg(md->constant_encoding(), mdo);
2519 if (mdo_offset_bias > 0) {
2520 __ set(mdo_offset_bias, data_val);
2521 __ add(mdo, data_val, mdo);
2522 }
2523 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2524 __ ldub(flags_addr, data_val);
2525 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2526 __ stb(data_val, flags_addr);
2527 __ ba_short(done);
2528 __ bind(not_null);
2529 } else {
2530 __ br_null_short(value, Assembler::pn, done);
2531 }
2532 add_debug_info_for_null_check_here(op->info_for_exception());
2533 __ load_klass(array, k_RInfo);
2534 __ load_klass(value, klass_RInfo);
2535
2536 // get instance klass
2537 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2538 // perform the fast part of the checking logic
2539 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2540
2541 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2542 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2543 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2544 __ delayed()->nop();
2545 __ cmp(G3, 0);
2546 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2547 __ delayed()->nop();
2548 // fall through to the success case
2549
2550 if (op->should_profile()) {
2551 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2552 assert_different_registers(value, mdo, recv, tmp1);
2553 __ bind(profile_cast_success);
2554 metadata2reg(md->constant_encoding(), mdo);
2555 if (mdo_offset_bias > 0) {
2556 __ set(mdo_offset_bias, tmp1);
2557 __ add(mdo, tmp1, mdo);
2558 }
2559 __ load_klass(value, recv);
2560 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2561 __ ba_short(done);
2562 // Cast failure case
2563 __ bind(profile_cast_failure);
2564 metadata2reg(md->constant_encoding(), mdo);
2565 if (mdo_offset_bias > 0) {
2566 __ set(mdo_offset_bias, tmp1);
2567 __ add(mdo, tmp1, mdo);
2568 }
2569 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2570 __ ld_ptr(data_addr, tmp1);
2571 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2572 __ st_ptr(tmp1, data_addr);
2573 __ ba(*stub->entry());
2574 __ delayed()->nop();
2575 }
2576 __ bind(done);
2577 } else if (code == lir_checkcast) {
2578 Register obj = op->object()->as_register();
2579 Register dst = op->result_opr()->as_register();
2580 Label success;
2581 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2582 __ bind(success);
2583 __ mov(obj, dst);
2584 } else if (code == lir_instanceof) {
2585 Register obj = op->object()->as_register();
2586 Register dst = op->result_opr()->as_register();
2587 Label success, failure, done;
2588 emit_typecheck_helper(op, &success, &failure, &failure);
2589 __ bind(failure);
2590 __ set(0, dst);
2591 __ ba_short(done);
2592 __ bind(success);
2593 __ set(1, dst);
2594 __ bind(done);
2595 } else {
2596 ShouldNotReachHere();
2597 }
2598
2599 }
2600
2601
2602 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2603 if (op->code() == lir_cas_long) {
2604 assert(VM_Version::supports_cx8(), "wrong machine");
2605 Register addr = op->addr()->as_pointer_register();
2606 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2607 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2608 Register new_value_lo = op->new_value()->as_register_lo();
2609 Register new_value_hi = op->new_value()->as_register_hi();
2610 Register t1 = op->tmp1()->as_register();
2611 Register t2 = op->tmp2()->as_register();
2612 __ mov(cmp_value_lo, t1);
2613 __ mov(new_value_lo, t2);
2614 // perform the compare and swap operation
2615 __ casx(addr, t1, t2);
2616 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2617 // overwritten with the original value in "addr" and will be equal to t1.
2618 __ cmp(t1, t2);
2619 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2620 Register addr = op->addr()->as_pointer_register();
2621 Register cmp_value = op->cmp_value()->as_register();
2622 Register new_value = op->new_value()->as_register();
2623 Register t1 = op->tmp1()->as_register();
2624 Register t2 = op->tmp2()->as_register();
2625 __ mov(cmp_value, t1);
2626 __ mov(new_value, t2);
2627 if (op->code() == lir_cas_obj) {
2628 if (UseCompressedOops) {
2629 __ encode_heap_oop(t1);
2630 __ encode_heap_oop(t2);
2631 __ cas(addr, t1, t2);
2632 } else {
2633 __ cas_ptr(addr, t1, t2);
2634 }
2635 } else {
2636 __ cas(addr, t1, t2);
2637 }
2638 __ cmp(t1, t2);
2639 } else {
2640 Unimplemented();
2641 }
2642 }
2643
2644 void LIR_Assembler::set_24bit_FPU() {
2645 Unimplemented();
2646 }
2647
2648
2649 void LIR_Assembler::reset_FPU() {
2650 Unimplemented();
2651 }
2652
2653
2654 void LIR_Assembler::breakpoint() {
2655 __ breakpoint_trap();
2656 }
2657
2658
2659 void LIR_Assembler::push(LIR_Opr opr) {
2660 Unimplemented();
2661 }
2662
2663
2664 void LIR_Assembler::pop(LIR_Opr opr) {
2665 Unimplemented();
2666 }
2667
2668
2669 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2670 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2671 Register dst = dst_opr->as_register();
2672 Register reg = mon_addr.base();
2673 int offset = mon_addr.disp();
2674 // compute pointer to BasicLock
2675 if (mon_addr.is_simm13()) {
2676 __ add(reg, offset, dst);
2677 } else {
2678 __ set(offset, dst);
2679 __ add(dst, reg, dst);
2680 }
2681 }
2682
2683 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2684 assert(op->crc()->is_single_cpu(), "crc must be register");
2685 assert(op->val()->is_single_cpu(), "byte value must be register");
2686 assert(op->result_opr()->is_single_cpu(), "result must be register");
2687 Register crc = op->crc()->as_register();
2688 Register val = op->val()->as_register();
2689 Register table = op->result_opr()->as_register();
2690 Register res = op->result_opr()->as_register();
2691
2692 assert_different_registers(val, crc, table);
2693
2694 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2695 __ not1(crc);
2696 __ clruwu(crc);
2697 __ update_byte_crc32(crc, val, table);
2698 __ not1(crc);
2699
2700 __ mov(crc, res);
2701 }
2702
2703 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2704 Register obj = op->obj_opr()->as_register();
2705 Register hdr = op->hdr_opr()->as_register();
2706 Register lock = op->lock_opr()->as_register();
2707
2708 // obj may not be an oop
2709 if (op->code() == lir_lock) {
2710 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2711 if (UseFastLocking) {
2712 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2713 // add debug info for NullPointerException only if one is possible
2714 if (op->info() != NULL) {
2715 add_debug_info_for_null_check_here(op->info());
2716 }
2717 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2718 } else {
2719 // always do slow locking
2720 // note: the slow locking code could be inlined here, however if we use
2721 // slow locking, speed doesn't matter anyway and this solution is
2722 // simpler and requires less duplicated code - additionally, the
2723 // slow locking code is the same in either case which simplifies
2724 // debugging
2725 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2726 __ delayed()->nop();
2727 }
2728 } else {
2729 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2730 if (UseFastLocking) {
2731 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2732 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2733 } else {
2734 // always do slow unlocking
2735 // note: the slow unlocking code could be inlined here, however if we use
2736 // slow unlocking, speed doesn't matter anyway and this solution is
2737 // simpler and requires less duplicated code - additionally, the
2738 // slow unlocking code is the same in either case which simplifies
2739 // debugging
2740 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2741 __ delayed()->nop();
2742 }
2743 }
2744 __ bind(*op->stub()->continuation());
2745 }
2746
2747
2748 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2749 ciMethod* method = op->profiled_method();
2750 int bci = op->profiled_bci();
2751 ciMethod* callee = op->profiled_callee();
2752
2753 // Update counter for all call types
2754 ciMethodData* md = method->method_data_or_null();
2755 assert(md != NULL, "Sanity");
2756 ciProfileData* data = md->bci_to_data(bci);
2757 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2758 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2759 Register mdo = op->mdo()->as_register();
2760 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2761 Register tmp1 = op->tmp1()->as_register_lo();
2762 metadata2reg(md->constant_encoding(), mdo);
2763 int mdo_offset_bias = 0;
2764 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2765 data->size_in_bytes())) {
2766 // The offset is large so bias the mdo by the base of the slot so
2767 // that the ld can use simm13s to reference the slots of the data
2768 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2769 __ set(mdo_offset_bias, O7);
2770 __ add(mdo, O7, mdo);
2771 }
2772
2773 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2774 // Perform additional virtual call profiling for invokevirtual and
2775 // invokeinterface bytecodes
2776 if (op->should_profile_receiver_type()) {
2777 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2778 Register recv = op->recv()->as_register();
2779 assert_different_registers(mdo, tmp1, recv);
2780 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2781 ciKlass* known_klass = op->known_holder();
2782 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2783 // We know the type that will be seen at this call site; we can
2784 // statically update the MethodData* rather than needing to do
2785 // dynamic tests on the receiver type
2786
2787 // NOTE: we should probably put a lock around this search to
2788 // avoid collisions by concurrent compilations
2789 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2790 uint i;
2791 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2792 ciKlass* receiver = vc_data->receiver(i);
2793 if (known_klass->equals(receiver)) {
2794 Address data_addr(mdo, md->byte_offset_of_slot(data,
2795 VirtualCallData::receiver_count_offset(i)) -
2796 mdo_offset_bias);
2797 __ ld_ptr(data_addr, tmp1);
2798 __ add(tmp1, DataLayout::counter_increment, tmp1);
2799 __ st_ptr(tmp1, data_addr);
2800 return;
2801 }
2802 }
2803
2804 // Receiver type not found in profile data; select an empty slot
2805
2806 // Note that this is less efficient than it should be because it
2807 // always does a write to the receiver part of the
2808 // VirtualCallData rather than just the first time
2809 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2810 ciKlass* receiver = vc_data->receiver(i);
2811 if (receiver == NULL) {
2812 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2813 mdo_offset_bias);
2814 metadata2reg(known_klass->constant_encoding(), tmp1);
2815 __ st_ptr(tmp1, recv_addr);
2816 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2817 mdo_offset_bias);
2818 __ ld_ptr(data_addr, tmp1);
2819 __ add(tmp1, DataLayout::counter_increment, tmp1);
2820 __ st_ptr(tmp1, data_addr);
2821 return;
2822 }
2823 }
2824 } else {
2825 __ load_klass(recv, recv);
2826 Label update_done;
2827 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2828 // Receiver did not match any saved receiver and there is no empty row for it.
2829 // Increment total counter to indicate polymorphic case.
2830 __ ld_ptr(counter_addr, tmp1);
2831 __ add(tmp1, DataLayout::counter_increment, tmp1);
2832 __ st_ptr(tmp1, counter_addr);
2833
2834 __ bind(update_done);
2835 }
2836 } else {
2837 // Static call
2838 __ ld_ptr(counter_addr, tmp1);
2839 __ add(tmp1, DataLayout::counter_increment, tmp1);
2840 __ st_ptr(tmp1, counter_addr);
2841 }
2842 }
2843
2844 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2845 Register obj = op->obj()->as_register();
2846 Register tmp1 = op->tmp()->as_pointer_register();
2847 Register tmp2 = G1;
2848 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2849 ciKlass* exact_klass = op->exact_klass();
2850 intptr_t current_klass = op->current_klass();
2851 bool not_null = op->not_null();
2852 bool no_conflict = op->no_conflict();
2853
2854 Label update, next, none;
2855
2856 bool do_null = !not_null;
2857 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2858 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2859
2860 assert(do_null || do_update, "why are we here?");
2861 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2862
2863 __ verify_oop(obj);
2864
2865 if (tmp1 != obj) {
2866 __ mov(obj, tmp1);
2867 }
2868 if (do_null) {
2869 __ br_notnull_short(tmp1, Assembler::pt, update);
2870 if (!TypeEntries::was_null_seen(current_klass)) {
2871 __ ld_ptr(mdo_addr, tmp1);
2872 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2873 __ st_ptr(tmp1, mdo_addr);
2874 }
2875 if (do_update) {
2876 __ ba(next);
2877 __ delayed()->nop();
2878 }
2879 #ifdef ASSERT
2880 } else {
2881 __ br_notnull_short(tmp1, Assembler::pt, update);
2882 __ stop("unexpect null obj");
2883 #endif
2884 }
2885
2886 __ bind(update);
2887
2888 if (do_update) {
2889 #ifdef ASSERT
2890 if (exact_klass != NULL) {
2891 Label ok;
2892 __ load_klass(tmp1, tmp1);
2893 metadata2reg(exact_klass->constant_encoding(), tmp2);
2894 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
2895 __ stop("exact klass and actual klass differ");
2896 __ bind(ok);
2897 }
2898 #endif
2899
2900 Label do_update;
2901 __ ld_ptr(mdo_addr, tmp2);
2902
2903 if (!no_conflict) {
2904 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2905 if (exact_klass != NULL) {
2906 metadata2reg(exact_klass->constant_encoding(), tmp1);
2907 } else {
2908 __ load_klass(tmp1, tmp1);
2909 }
2910
2911 __ xor3(tmp1, tmp2, tmp1);
2912 __ btst(TypeEntries::type_klass_mask, tmp1);
2913 // klass seen before, nothing to do. The unknown bit may have been
2914 // set already but no need to check.
2915 __ brx(Assembler::zero, false, Assembler::pt, next);
2916 __ delayed()->
2917
2918 btst(TypeEntries::type_unknown, tmp1);
2919 // already unknown. Nothing to do anymore.
2920 __ brx(Assembler::notZero, false, Assembler::pt, next);
2921
2922 if (TypeEntries::is_type_none(current_klass)) {
2923 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2924 __ brx(Assembler::zero, true, Assembler::pt, do_update);
2925 // first time here. Set profile type.
2926 __ delayed()->or3(tmp2, tmp1, tmp2);
2927 } else {
2928 __ delayed()->nop();
2929 }
2930 } else {
2931 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2932 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2933
2934 __ btst(TypeEntries::type_unknown, tmp2);
2935 // already unknown. Nothing to do anymore.
2936 __ brx(Assembler::notZero, false, Assembler::pt, next);
2937 __ delayed()->nop();
2938 }
2939
2940 // different than before. Cannot keep accurate profile.
2941 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
2942 } else {
2943 // There's a single possible klass at this profile point
2944 assert(exact_klass != NULL, "should be");
2945 if (TypeEntries::is_type_none(current_klass)) {
2946 metadata2reg(exact_klass->constant_encoding(), tmp1);
2947 __ xor3(tmp1, tmp2, tmp1);
2948 __ btst(TypeEntries::type_klass_mask, tmp1);
2949 __ brx(Assembler::zero, false, Assembler::pt, next);
2950 #ifdef ASSERT
2951
2952 {
2953 Label ok;
2954 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2955 __ brx(Assembler::zero, true, Assembler::pt, ok);
2956 __ delayed()->nop();
2957
2958 __ stop("unexpected profiling mismatch");
2959 __ bind(ok);
2960 }
2961 // first time here. Set profile type.
2962 __ or3(tmp2, tmp1, tmp2);
2963 #else
2964 // first time here. Set profile type.
2965 __ delayed()->or3(tmp2, tmp1, tmp2);
2966 #endif
2967
2968 } else {
2969 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2970 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2971
2972 // already unknown. Nothing to do anymore.
2973 __ btst(TypeEntries::type_unknown, tmp2);
2974 __ brx(Assembler::notZero, false, Assembler::pt, next);
2975 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
2976 }
2977 }
2978
2979 __ bind(do_update);
2980 __ st_ptr(tmp2, mdo_addr);
2981
2982 __ bind(next);
2983 }
2984 }
2985
2986 void LIR_Assembler::align_backward_branch_target() {
2987 __ align(OptoLoopAlignment);
2988 }
2989
2990
2991 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2992 // make sure we are expecting a delay
2993 // this has the side effect of clearing the delay state
2994 // so we can use _masm instead of _masm->delayed() to do the
2995 // code generation.
2996 __ delayed();
2997
2998 // make sure we only emit one instruction
2999 int offset = code_offset();
3000 op->delay_op()->emit_code(this);
3001 #ifdef ASSERT
3002 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3003 op->delay_op()->print();
3004 }
3005 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3006 "only one instruction can go in a delay slot");
3007 #endif
3008
3009 // we may also be emitting the call info for the instruction
3010 // which we are the delay slot of.
3011 CodeEmitInfo* call_info = op->call_info();
3012 if (call_info) {
3013 add_call_info(code_offset(), call_info);
3014 }
3015
3016 if (VerifyStackAtCalls) {
3017 _masm->sub(FP, SP, O7);
3018 _masm->cmp(O7, initial_frame_size_in_bytes());
3019 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3020 }
3021 }
3022
3023
3024 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3025 assert(left->is_register(), "can only handle registers");
3026
3027 if (left->is_single_cpu()) {
3028 __ neg(left->as_register(), dest->as_register());
3029 } else if (left->is_single_fpu()) {
3030 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3031 } else if (left->is_double_fpu()) {
3032 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3033 } else {
3034 assert (left->is_double_cpu(), "Must be a long");
3035 Register Rlow = left->as_register_lo();
3036 Register Rhi = left->as_register_hi();
3037 __ sub(G0, Rlow, dest->as_register_lo());
3038 }
3039 }
3040
3041
3042 void LIR_Assembler::fxch(int i) {
3043 Unimplemented();
3044 }
3045
3046 void LIR_Assembler::fld(int i) {
3047 Unimplemented();
3048 }
3049
3050 void LIR_Assembler::ffree(int i) {
3051 Unimplemented();
3052 }
3053
3054 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3055 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3056
3057 // if tmp is invalid, then the function being called doesn't destroy the thread
3058 if (tmp->is_valid()) {
3059 __ save_thread(tmp->as_pointer_register());
3060 }
3061 __ call(dest, relocInfo::runtime_call_type);
3062 __ delayed()->nop();
3063 if (info != NULL) {
3064 add_call_info_here(info);
3065 }
3066 if (tmp->is_valid()) {
3067 __ restore_thread(tmp->as_pointer_register());
3068 }
3069
3070 #ifdef ASSERT
3071 __ verify_thread();
3072 #endif // ASSERT
3073 }
3074
3075
3076 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3077 ShouldNotReachHere();
3078
3079 NEEDS_CLEANUP;
3080 if (type == T_LONG) {
3081 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3082
3083 // (extended to allow indexed as well as constant displaced for JSR-166)
3084 Register idx = noreg; // contains either constant offset or index
3085
3086 int disp = mem_addr->disp();
3087 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3088 if (!Assembler::is_simm13(disp)) {
3089 idx = O7;
3090 __ set(disp, idx);
3091 }
3092 } else {
3093 assert(disp == 0, "not both indexed and disp");
3094 idx = mem_addr->index()->as_register();
3095 }
3096
3097 int null_check_offset = -1;
3098
3099 Register base = mem_addr->base()->as_register();
3100 if (src->is_register() && dest->is_address()) {
3101 // G4 is high half, G5 is low half
3102 // clear the top bits of G5, and scale up G4
3103 __ srl (src->as_register_lo(), 0, G5);
3104 __ sllx(src->as_register_hi(), 32, G4);
3105 // combine the two halves into the 64 bits of G4
3106 __ or3(G4, G5, G4);
3107 null_check_offset = __ offset();
3108 if (idx == noreg) {
3109 __ stx(G4, base, disp);
3110 } else {
3111 __ stx(G4, base, idx);
3112 }
3113 } else if (src->is_address() && dest->is_register()) {
3114 null_check_offset = __ offset();
3115 if (idx == noreg) {
3116 __ ldx(base, disp, G5);
3117 } else {
3118 __ ldx(base, idx, G5);
3119 }
3120 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3121 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3122 } else {
3123 Unimplemented();
3124 }
3125 if (info != NULL) {
3126 add_debug_info_for_null_check(null_check_offset, info);
3127 }
3128
3129 } else {
3130 // use normal move for all other volatiles since they don't need
3131 // special handling to remain atomic.
3132 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3133 }
3134 }
3135
3136 void LIR_Assembler::membar() {
3137 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3138 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3139 }
3140
3141 void LIR_Assembler::membar_acquire() {
3142 // no-op on TSO
3143 }
3144
3145 void LIR_Assembler::membar_release() {
3146 // no-op on TSO
3147 }
3148
3149 void LIR_Assembler::membar_loadload() {
3150 // no-op
3151 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3152 }
3153
3154 void LIR_Assembler::membar_storestore() {
3155 // no-op
3156 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3157 }
3158
3159 void LIR_Assembler::membar_loadstore() {
3160 // no-op
3161 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3162 }
3163
3164 void LIR_Assembler::membar_storeload() {
3165 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3166 }
3167
3168 void LIR_Assembler::on_spin_wait() {
3169 Unimplemented();
3170 }
3171
3172 // Pack two sequential registers containing 32 bit values
3173 // into a single 64 bit register.
3174 // src and src->successor() are packed into dst
3175 // src and dst may be the same register.
3176 // Note: src is destroyed
3177 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3178 Register rs = src->as_register();
3179 Register rd = dst->as_register_lo();
3180 __ sllx(rs, 32, rs);
3181 __ srl(rs->successor(), 0, rs->successor());
3182 __ or3(rs, rs->successor(), rd);
3183 }
3184
3185 // Unpack a 64 bit value in a register into
3186 // two sequential registers.
3187 // src is unpacked into dst and dst->successor()
3188 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3189 Register rs = src->as_register_lo();
3190 Register rd = dst->as_register_hi();
3191 assert_different_registers(rs, rd, rd->successor());
3192 __ srlx(rs, 32, rd);
3193 __ srl (rs, 0, rd->successor());
3194 }
3195
3196 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3197 const LIR_Address* addr = addr_opr->as_address_ptr();
3198 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3199 const Register dest_reg = dest->as_pointer_register();
3200 const Register base_reg = addr->base()->as_pointer_register();
3201
3202 if (Assembler::is_simm13(addr->disp())) {
3203 if (addr->index()->is_valid()) {
3204 const Register index_reg = addr->index()->as_pointer_register();
3205 assert(index_reg != G3_scratch, "invariant");
3206 __ add(base_reg, addr->disp(), G3_scratch);
3207 __ add(index_reg, G3_scratch, dest_reg);
3208 } else {
3209 __ add(base_reg, addr->disp(), dest_reg);
3210 }
3211 } else {
3212 __ set(addr->disp(), G3_scratch);
3213 if (addr->index()->is_valid()) {
3214 const Register index_reg = addr->index()->as_pointer_register();
3215 assert(index_reg != G3_scratch, "invariant");
3216 __ add(index_reg, G3_scratch, G3_scratch);
3217 }
3218 __ add(base_reg, G3_scratch, dest_reg);
3219 }
3220 }
3221
3222
3223 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3224 assert(result_reg->is_register(), "check");
3225 __ mov(G2_thread, result_reg->as_register());
3226 }
3227
3228 #ifdef ASSERT
3229 // emit run-time assertion
3230 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3231 assert(op->code() == lir_assert, "must be");
3232
3233 if (op->in_opr1()->is_valid()) {
3234 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3235 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3236 } else {
3237 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3238 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3239 }
3240
3241 Label ok;
3242 if (op->condition() != lir_cond_always) {
3243 Assembler::Condition acond;
3244 switch (op->condition()) {
3245 case lir_cond_equal: acond = Assembler::equal; break;
3246 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3247 case lir_cond_less: acond = Assembler::less; break;
3248 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3249 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3250 case lir_cond_greater: acond = Assembler::greater; break;
3251 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3252 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3253 default: ShouldNotReachHere();
3254 };
3255 __ br(acond, false, Assembler::pt, ok);
3256 __ delayed()->nop();
3257 }
3258 if (op->halt()) {
3259 const char* str = __ code_string(op->msg());
3260 __ stop(str);
3261 } else {
3262 breakpoint();
3263 }
3264 __ bind(ok);
3265 }
3266 #endif
3267
3268 void LIR_Assembler::peephole(LIR_List* lir) {
3269 LIR_OpList* inst = lir->instructions_list();
3270 for (int i = 0; i < inst->length(); i++) {
3271 LIR_Op* op = inst->at(i);
3272 switch (op->code()) {
3273 case lir_cond_float_branch:
3274 case lir_branch: {
3275 LIR_OpBranch* branch = op->as_OpBranch();
3276 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3277 LIR_Op* delay_op = NULL;
3278 // we'd like to be able to pull following instructions into
3279 // this slot but we don't know enough to do it safely yet so
3280 // only optimize block to block control flow.
3281 if (LIRFillDelaySlots && branch->block()) {
3282 LIR_Op* prev = inst->at(i - 1);
3283 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3284 // swap previous instruction into delay slot
3285 inst->at_put(i - 1, op);
3286 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3287 #ifndef PRODUCT
3288 if (LIRTracePeephole) {
3289 tty->print_cr("delayed");
3290 inst->at(i - 1)->print();
3291 inst->at(i)->print();
3292 tty->cr();
3293 }
3294 #endif
3295 continue;
3296 }
3297 }
3298
3299 if (!delay_op) {
3300 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3301 }
3302 inst->insert_before(i + 1, delay_op);
3303 break;
3304 }
3305 case lir_static_call:
3306 case lir_virtual_call:
3307 case lir_icvirtual_call:
3308 case lir_optvirtual_call:
3309 case lir_dynamic_call: {
3310 LIR_Op* prev = inst->at(i - 1);
3311 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3312 (op->code() != lir_virtual_call ||
3313 !prev->result_opr()->is_single_cpu() ||
3314 prev->result_opr()->as_register() != O0) &&
3315 LIR_Assembler::is_single_instruction(prev)) {
3316 // Only moves without info can be put into the delay slot.
3317 // Also don't allow the setup of the receiver in the delay
3318 // slot for vtable calls.
3319 inst->at_put(i - 1, op);
3320 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3321 #ifndef PRODUCT
3322 if (LIRTracePeephole) {
3323 tty->print_cr("delayed");
3324 inst->at(i - 1)->print();
3325 inst->at(i)->print();
3326 tty->cr();
3327 }
3328 #endif
3329 } else {
3330 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3331 inst->insert_before(i + 1, delay_op);
3332 i++;
3333 }
3334 break;
3335 }
3336 }
3337 }
3338 }
3339
3340 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3341 LIR_Address* addr = src->as_address_ptr();
3342
3343 assert(data == dest, "swap uses only 2 operands");
3344 assert (code == lir_xchg, "no xadd on sparc");
3345
3346 if (data->type() == T_INT) {
3347 __ swap(as_Address(addr), data->as_register());
3348 } else if (data->is_oop()) {
3349 Register obj = data->as_register();
3350 Register narrow = tmp->as_register();
3351 assert(UseCompressedOops, "swap is 32bit only");
3352 __ encode_heap_oop(obj, narrow);
3353 __ swap(as_Address(addr), narrow);
3354 __ decode_heap_oop(narrow, obj);
3355 } else {
3356 ShouldNotReachHere();
3357 }
3358 }
3359
3360 #undef __