1 /* 2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "c1/c1_Defs.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_MacroAssembler.hpp" 30 #include "c1/c1_Runtime1.hpp" 31 #include "ci/ciUtilities.hpp" 32 #include "gc/shared/cardTable.hpp" 33 #include "gc/shared/cardTableBarrierSet.hpp" 34 #include "interpreter/interpreter.hpp" 35 #include "nativeInst_arm.hpp" 36 #include "oops/compiledICHolder.hpp" 37 #include "oops/oop.inline.hpp" 38 #include "prims/jvmtiExport.hpp" 39 #include "register_arm.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/signature.hpp" 42 #include "runtime/vframeArray.hpp" 43 #include "utilities/align.hpp" 44 #include "vmreg_arm.inline.hpp" 45 46 // Note: Rtemp usage is this file should not impact C2 and should be 47 // correct as long as it is not implicitly used in lower layers (the 48 // arm [macro]assembler) and used with care in the other C1 specific 49 // files. 50 51 // Implementation of StubAssembler 52 53 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) { 54 mov(R0, Rthread); 55 56 int call_offset = set_last_Java_frame(SP, FP, false, Rtemp); 57 58 call(entry); 59 if (call_offset == -1) { // PC not saved 60 call_offset = offset(); 61 } 62 reset_last_Java_frame(Rtemp); 63 64 assert(frame_size() != no_frame_size, "frame must be fixed"); 65 if (_stub_id != Runtime1::forward_exception_id) { 66 ldr(R3, Address(Rthread, Thread::pending_exception_offset())); 67 } 68 69 if (oop_result1->is_valid()) { 70 assert_different_registers(oop_result1, R3, Rtemp); 71 get_vm_result(oop_result1, Rtemp); 72 } 73 if (metadata_result->is_valid()) { 74 assert_different_registers(metadata_result, R3, Rtemp); 75 get_vm_result_2(metadata_result, Rtemp); 76 } 77 78 // Check for pending exception 79 // unpack_with_exception_in_tls path is taken through 80 // Runtime1::exception_handler_for_pc 81 if (_stub_id != Runtime1::forward_exception_id) { 82 assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id"); 83 #ifdef AARCH64 84 Label skip; 85 cbz(R3, skip); 86 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp); 87 bind(skip); 88 #else 89 cmp(R3, 0); 90 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne); 91 #endif // AARCH64 92 } else { 93 #ifdef ASSERT 94 // Should not have pending exception in forward_exception stub 95 ldr(R3, Address(Rthread, Thread::pending_exception_offset())); 96 cmp(R3, 0); 97 breakpoint(ne); 98 #endif // ASSERT 99 } 100 return call_offset; 101 } 102 103 104 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) { 105 if (arg1 != R1) { 106 mov(R1, arg1); 107 } 108 return call_RT(oop_result1, metadata_result, entry, 1); 109 } 110 111 112 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) { 113 assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise"); 114 return call_RT(oop_result1, metadata_result, entry, 2); 115 } 116 117 118 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) { 119 assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise"); 120 return call_RT(oop_result1, metadata_result, entry, 3); 121 } 122 123 124 #define __ sasm-> 125 126 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime? 127 #ifdef AARCH64 128 129 // 130 // On AArch64 registers save area has the following layout: 131 // 132 // |---------------------| 133 // | return address (LR) | 134 // | FP | 135 // |---------------------| 136 // | D31 | 137 // | ... | 138 // | D0 | 139 // |---------------------| 140 // | padding | 141 // |---------------------| 142 // | R28 | 143 // | ... | 144 // | R0 | 145 // |---------------------| <-- SP 146 // 147 148 enum RegisterLayout { 149 number_of_saved_gprs = 29, 150 number_of_saved_fprs = FloatRegisterImpl::number_of_registers, 151 152 R0_offset = 0, 153 D0_offset = R0_offset + number_of_saved_gprs + 1, 154 FP_offset = D0_offset + number_of_saved_fprs, 155 LR_offset = FP_offset + 1, 156 157 reg_save_size = LR_offset + 1, 158 159 arg1_offset = reg_save_size * wordSize, 160 arg2_offset = (reg_save_size + 1) * wordSize 161 }; 162 163 #else 164 165 enum RegisterLayout { 166 fpu_save_size = pd_nof_fpu_regs_reg_alloc, 167 #ifndef __SOFTFP__ 168 D0_offset = 0, 169 #endif 170 R0_offset = fpu_save_size, 171 R1_offset, 172 R2_offset, 173 R3_offset, 174 R4_offset, 175 R5_offset, 176 R6_offset, 177 #if (FP_REG_NUM != 7) 178 R7_offset, 179 #endif 180 R8_offset, 181 R9_offset, 182 R10_offset, 183 #if (FP_REG_NUM != 11) 184 R11_offset, 185 #endif 186 R12_offset, 187 FP_offset, 188 LR_offset, 189 reg_save_size, 190 arg1_offset = reg_save_size * wordSize, 191 arg2_offset = (reg_save_size + 1) * wordSize 192 }; 193 194 #endif // AARCH64 195 196 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) { 197 sasm->set_frame_size(reg_save_size /* in words */); 198 199 // Record saved value locations in an OopMap. 200 // Locations are offsets from sp after runtime call. 201 OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0); 202 203 #ifdef AARCH64 204 for (int i = 0; i < number_of_saved_gprs; i++) { 205 map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg()); 206 } 207 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg()); 208 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg()); 209 210 if (save_fpu_registers) { 211 for (int i = 0; i < number_of_saved_fprs; i++) { 212 map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg()); 213 } 214 } 215 #else 216 int j=0; 217 for (int i = R0_offset; i < R10_offset; i++) { 218 if (j == FP_REG_NUM) { 219 // skip the FP register, saved below 220 j++; 221 } 222 map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg()); 223 j++; 224 } 225 assert(j == R10->encoding(), "must be"); 226 #if (FP_REG_NUM != 11) 227 // add R11, if not saved as FP 228 map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg()); 229 #endif 230 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg()); 231 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg()); 232 233 if (save_fpu_registers) { 234 for (int i = 0; i < fpu_save_size; i++) { 235 map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg()); 236 } 237 } 238 #endif // AARCH64 239 240 return map; 241 } 242 243 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) { 244 __ block_comment("save_live_registers"); 245 sasm->set_frame_size(reg_save_size /* in words */); 246 247 #ifdef AARCH64 248 assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned"); 249 250 __ raw_push(FP, LR); 251 252 __ sub(SP, SP, (reg_save_size - 2) * wordSize); 253 254 for (int i = 0; i < align_down((int)number_of_saved_gprs, 2); i += 2) { 255 __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize)); 256 } 257 258 if (is_odd(number_of_saved_gprs)) { 259 int i = number_of_saved_gprs - 1; 260 __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize)); 261 } 262 263 if (save_fpu_registers) { 264 assert (is_even(number_of_saved_fprs), "adjust this code"); 265 for (int i = 0; i < number_of_saved_fprs; i += 2) { 266 __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize)); 267 } 268 } 269 #else 270 __ push(RegisterSet(FP) | RegisterSet(LR)); 271 __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11); 272 if (save_fpu_registers) { 273 __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback); 274 } else { 275 __ sub(SP, SP, fpu_save_size * wordSize); 276 } 277 #endif // AARCH64 278 279 return generate_oop_map(sasm, save_fpu_registers); 280 } 281 282 283 static void restore_live_registers(StubAssembler* sasm, 284 bool restore_R0, 285 bool restore_FP_LR, 286 bool do_return, 287 bool restore_fpu_registers = HaveVFP) { 288 __ block_comment("restore_live_registers"); 289 290 #ifdef AARCH64 291 if (restore_R0) { 292 __ ldr(R0, Address(SP, R0_offset * wordSize)); 293 } 294 295 assert(is_odd(number_of_saved_gprs), "adjust this code"); 296 for (int i = 1; i < number_of_saved_gprs; i += 2) { 297 __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize)); 298 } 299 300 if (restore_fpu_registers) { 301 assert (is_even(number_of_saved_fprs), "adjust this code"); 302 for (int i = 0; i < number_of_saved_fprs; i += 2) { 303 __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize)); 304 } 305 } 306 307 __ add(SP, SP, (reg_save_size - 2) * wordSize); 308 309 if (restore_FP_LR) { 310 __ raw_pop(FP, LR); 311 if (do_return) { 312 __ ret(); 313 } 314 } else { 315 assert (!do_return, "return without restoring FP/LR"); 316 } 317 #else 318 if (restore_fpu_registers) { 319 __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback); 320 if (!restore_R0) { 321 __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize); 322 } 323 } else { 324 __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize); 325 } 326 __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11); 327 if (restore_FP_LR) { 328 __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR)); 329 } else { 330 assert (!do_return, "return without restoring FP/LR"); 331 } 332 #endif // AARCH64 333 } 334 335 336 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) { 337 restore_live_registers(sasm, false, true, true, restore_fpu_registers); 338 } 339 340 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) { 341 restore_live_registers(sasm, true, true, true, restore_fpu_registers); 342 } 343 344 #ifndef AARCH64 345 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) { 346 restore_live_registers(sasm, true, false, false, restore_fpu_registers); 347 } 348 #endif // !AARCH64 349 350 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) { 351 restore_live_registers(sasm, true, true, false, restore_fpu_registers); 352 } 353 354 void StubAssembler::save_live_registers() { 355 save_live_registers(this); 356 } 357 358 void StubAssembler::restore_live_registers_without_return() { 359 restore_live_registers_without_return(this); 360 } 361 362 void Runtime1::initialize_pd() { 363 } 364 365 366 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) { 367 OopMap* oop_map = save_live_registers(sasm); 368 369 if (has_argument) { 370 __ ldr(R1, Address(SP, arg1_offset)); 371 } 372 373 int call_offset = __ call_RT(noreg, noreg, target); 374 OopMapSet* oop_maps = new OopMapSet(); 375 oop_maps->add_gc_map(call_offset, oop_map); 376 377 DEBUG_ONLY(STOP("generate_exception_throw");) // Should not reach here 378 return oop_maps; 379 } 380 381 382 static void restore_sp_for_method_handle(StubAssembler* sasm) { 383 // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site. 384 __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset())); 385 #ifdef AARCH64 386 Label skip; 387 __ cbz(Rtemp, skip); 388 __ mov(SP, Rmh_SP_save); 389 __ bind(skip); 390 #else 391 __ cmp(Rtemp, 0); 392 __ mov(SP, Rmh_SP_save, ne); 393 #endif // AARCH64 394 } 395 396 397 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) { 398 __ block_comment("generate_handle_exception"); 399 400 bool save_fpu_registers = false; 401 402 // Save registers, if required. 403 OopMapSet* oop_maps = new OopMapSet(); 404 OopMap* oop_map = NULL; 405 406 switch (id) { 407 case forward_exception_id: { 408 save_fpu_registers = HaveVFP; 409 oop_map = generate_oop_map(sasm); 410 __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset())); 411 __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize)); 412 Register zero = __ zero_register(Rtemp); 413 __ str(zero, Address(Rthread, Thread::pending_exception_offset())); 414 break; 415 } 416 case handle_exception_id: 417 save_fpu_registers = HaveVFP; 418 // fall-through 419 case handle_exception_nofpu_id: 420 // At this point all registers MAY be live. 421 oop_map = save_live_registers(sasm, save_fpu_registers); 422 break; 423 case handle_exception_from_callee_id: 424 // At this point all registers except exception oop (R4/R19) and 425 // exception pc (R5/R20) are dead. 426 oop_map = save_live_registers(sasm); // TODO it's not required to save all registers 427 break; 428 default: ShouldNotReachHere(); 429 } 430 431 __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset())); 432 __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset())); 433 434 __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address 435 436 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc)); 437 oop_maps->add_gc_map(call_offset, oop_map); 438 439 // Exception handler found 440 __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address 441 442 // Restore the registers that were saved at the beginning, remove 443 // frame and jump to the exception handler. 444 switch (id) { 445 case forward_exception_id: 446 case handle_exception_nofpu_id: 447 case handle_exception_id: 448 restore_live_registers(sasm, save_fpu_registers); 449 // Note: the restore live registers includes the jump to LR (patched to R0) 450 break; 451 case handle_exception_from_callee_id: 452 restore_live_registers_without_return(sasm); // must not jump immediatly to handler 453 restore_sp_for_method_handle(sasm); 454 __ ret(); 455 break; 456 default: ShouldNotReachHere(); 457 } 458 459 DEBUG_ONLY(STOP("generate_handle_exception");) // Should not reach here 460 461 return oop_maps; 462 } 463 464 465 void Runtime1::generate_unwind_exception(StubAssembler* sasm) { 466 // FP no longer used to find the frame start 467 // on entry, remove_frame() has already been called (restoring FP and LR) 468 469 // search the exception handler address of the caller (using the return address) 470 __ mov(c_rarg0, Rthread); 471 __ mov(Rexception_pc, LR); 472 __ mov(c_rarg1, LR); 473 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1); 474 475 // Exception oop should be still in Rexception_obj and pc in Rexception_pc 476 // Jump to handler 477 __ verify_not_null_oop(Rexception_obj); 478 479 // JSR292 extension 480 restore_sp_for_method_handle(sasm); 481 482 __ jump(R0); 483 } 484 485 486 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) { 487 OopMap* oop_map = save_live_registers(sasm); 488 489 // call the runtime patching routine, returns non-zero if nmethod got deopted. 490 int call_offset = __ call_RT(noreg, noreg, target); 491 OopMapSet* oop_maps = new OopMapSet(); 492 oop_maps->add_gc_map(call_offset, oop_map); 493 494 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 495 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 496 497 __ cmp_32(R0, 0); 498 499 #ifdef AARCH64 500 Label call_deopt; 501 502 restore_live_registers_without_return(sasm); 503 __ b(call_deopt, ne); 504 __ ret(); 505 506 __ bind(call_deopt); 507 #else 508 restore_live_registers_except_FP_LR(sasm); 509 __ pop(RegisterSet(FP) | RegisterSet(PC), eq); 510 511 // Deoptimization needed 512 // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back 513 __ pop(RegisterSet(FP) | RegisterSet(LR)); 514 #endif // AARCH64 515 516 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp); 517 518 DEBUG_ONLY(STOP("generate_patching");) // Should not reach here 519 return oop_maps; 520 } 521 522 523 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) { 524 const bool must_gc_arguments = true; 525 const bool dont_gc_arguments = false; 526 527 OopMapSet* oop_maps = NULL; 528 bool save_fpu_registers = HaveVFP; 529 530 switch (id) { 531 case forward_exception_id: 532 { 533 oop_maps = generate_handle_exception(id, sasm); 534 // does not return on ARM 535 } 536 break; 537 538 case new_instance_id: 539 case fast_new_instance_id: 540 case fast_new_instance_init_check_id: 541 { 542 const Register result = R0; 543 const Register klass = R1; 544 545 if (UseTLAB && Universe::heap()->supports_inline_contig_alloc() && id != new_instance_id) { 546 // We come here when TLAB allocation failed. 547 // In this case we try to allocate directly from eden. 548 Label slow_case, slow_case_no_pop; 549 550 // Make sure the class is fully initialized 551 if (id == fast_new_instance_init_check_id) { 552 __ ldrb(result, Address(klass, InstanceKlass::init_state_offset())); 553 __ cmp(result, InstanceKlass::fully_initialized); 554 __ b(slow_case_no_pop, ne); 555 } 556 557 // Free some temporary registers 558 const Register obj_size = R4; 559 const Register tmp1 = R5; 560 const Register tmp2 = LR; 561 const Register obj_end = Rtemp; 562 563 __ raw_push(R4, R5, LR); 564 565 __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset())); 566 __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case); // initializes result and obj_end 567 __ incr_allocated_bytes(obj_size, tmp2); 568 __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2, 569 instanceOopDesc::header_size() * HeapWordSize, -1, 570 /* is_tlab_allocated */ false); 571 __ raw_pop_and_ret(R4, R5); 572 573 __ bind(slow_case); 574 __ raw_pop(R4, R5, LR); 575 576 __ bind(slow_case_no_pop); 577 } 578 579 OopMap* map = save_live_registers(sasm); 580 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass); 581 oop_maps = new OopMapSet(); 582 oop_maps->add_gc_map(call_offset, map); 583 584 // MacroAssembler::StoreStore useless (included in the runtime exit path) 585 586 restore_live_registers_except_R0(sasm); 587 } 588 break; 589 590 case counter_overflow_id: 591 { 592 OopMap* oop_map = save_live_registers(sasm); 593 __ ldr(R1, Address(SP, arg1_offset)); 594 __ ldr(R2, Address(SP, arg2_offset)); 595 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2); 596 oop_maps = new OopMapSet(); 597 oop_maps->add_gc_map(call_offset, oop_map); 598 restore_live_registers(sasm); 599 } 600 break; 601 602 case new_type_array_id: 603 case new_object_array_id: 604 { 605 if (id == new_type_array_id) { 606 __ set_info("new_type_array", dont_gc_arguments); 607 } else { 608 __ set_info("new_object_array", dont_gc_arguments); 609 } 610 611 const Register result = R0; 612 const Register klass = R1; 613 const Register length = R2; 614 615 if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) { 616 // We come here when TLAB allocation failed. 617 // In this case we try to allocate directly from eden. 618 Label slow_case, slow_case_no_pop; 619 620 #ifdef AARCH64 621 __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length); 622 __ cmp_32(length, Rtemp); 623 #else 624 __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length); 625 #endif // AARCH64 626 __ b(slow_case_no_pop, hs); 627 628 // Free some temporary registers 629 const Register arr_size = R4; 630 const Register tmp1 = R5; 631 const Register tmp2 = LR; 632 const Register tmp3 = Rtemp; 633 const Register obj_end = tmp3; 634 635 __ raw_push(R4, R5, LR); 636 637 // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size) 638 __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset())); 639 __ mov(arr_size, MinObjAlignmentInBytesMask); 640 __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift)); 641 642 #ifdef AARCH64 643 __ lslv_w(tmp3, length, tmp1); 644 __ add(arr_size, arr_size, tmp3); 645 #else 646 __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1)); 647 #endif // AARCH64 648 649 __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift)); 650 __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes); 651 652 // eden_allocate destroys tmp2, so reload header_size after allocation 653 // eden_allocate initializes result and obj_end 654 __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case); 655 __ incr_allocated_bytes(arr_size, tmp2); 656 __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) + 657 Klass::_lh_header_size_shift / BitsPerByte)); 658 __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false); 659 __ raw_pop_and_ret(R4, R5); 660 661 __ bind(slow_case); 662 __ raw_pop(R4, R5, LR); 663 __ bind(slow_case_no_pop); 664 } 665 666 OopMap* map = save_live_registers(sasm); 667 int call_offset; 668 if (id == new_type_array_id) { 669 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length); 670 } else { 671 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length); 672 } 673 oop_maps = new OopMapSet(); 674 oop_maps->add_gc_map(call_offset, map); 675 676 // MacroAssembler::StoreStore useless (included in the runtime exit path) 677 678 restore_live_registers_except_R0(sasm); 679 } 680 break; 681 682 case new_multi_array_id: 683 { 684 __ set_info("new_multi_array", dont_gc_arguments); 685 686 // R0: klass 687 // R2: rank 688 // SP: address of 1st dimension 689 const Register result = R0; 690 OopMap* map = save_live_registers(sasm); 691 692 __ mov(R1, R0); 693 __ add(R3, SP, arg1_offset); 694 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3); 695 696 oop_maps = new OopMapSet(); 697 oop_maps->add_gc_map(call_offset, map); 698 699 // MacroAssembler::StoreStore useless (included in the runtime exit path) 700 701 restore_live_registers_except_R0(sasm); 702 } 703 break; 704 705 case register_finalizer_id: 706 { 707 __ set_info("register_finalizer", dont_gc_arguments); 708 709 // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set 710 __ load_klass(Rtemp, R0); 711 __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset())); 712 713 #ifdef AARCH64 714 Label L; 715 __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L); 716 __ ret(); 717 __ bind(L); 718 #else 719 __ tst(Rtemp, JVM_ACC_HAS_FINALIZER); 720 __ bx(LR, eq); 721 #endif // AARCH64 722 723 // Call VM 724 OopMap* map = save_live_registers(sasm); 725 oop_maps = new OopMapSet(); 726 int call_offset = __ call_RT(noreg, noreg, 727 CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0); 728 oop_maps->add_gc_map(call_offset, map); 729 restore_live_registers(sasm); 730 } 731 break; 732 733 case throw_range_check_failed_id: 734 { 735 __ set_info("range_check_failed", dont_gc_arguments); 736 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true); 737 } 738 break; 739 740 case throw_index_exception_id: 741 { 742 __ set_info("index_range_check_failed", dont_gc_arguments); 743 #ifdef AARCH64 744 __ NOT_TESTED(); 745 #endif 746 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true); 747 } 748 break; 749 750 case throw_div0_exception_id: 751 { 752 __ set_info("throw_div0_exception", dont_gc_arguments); 753 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false); 754 } 755 break; 756 757 case throw_null_pointer_exception_id: 758 { 759 __ set_info("throw_null_pointer_exception", dont_gc_arguments); 760 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false); 761 } 762 break; 763 764 case handle_exception_nofpu_id: 765 case handle_exception_id: 766 { 767 __ set_info("handle_exception", dont_gc_arguments); 768 oop_maps = generate_handle_exception(id, sasm); 769 } 770 break; 771 772 case handle_exception_from_callee_id: 773 { 774 __ set_info("handle_exception_from_callee", dont_gc_arguments); 775 oop_maps = generate_handle_exception(id, sasm); 776 } 777 break; 778 779 case unwind_exception_id: 780 { 781 __ set_info("unwind_exception", dont_gc_arguments); 782 generate_unwind_exception(sasm); 783 } 784 break; 785 786 case throw_array_store_exception_id: 787 { 788 __ set_info("throw_array_store_exception", dont_gc_arguments); 789 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true); 790 } 791 break; 792 793 case throw_class_cast_exception_id: 794 { 795 __ set_info("throw_class_cast_exception", dont_gc_arguments); 796 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true); 797 } 798 break; 799 800 case throw_incompatible_class_change_error_id: 801 { 802 __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments); 803 #ifdef AARCH64 804 __ NOT_TESTED(); 805 #endif 806 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false); 807 } 808 break; 809 810 case slow_subtype_check_id: 811 { 812 // (in) R0 - sub, destroyed, 813 // (in) R1 - super, not changed 814 // (out) R0 - result: 1 if check passed, 0 otherwise 815 __ raw_push(R2, R3, LR); 816 817 // Load an array of secondary_supers 818 __ ldr(R2, Address(R0, Klass::secondary_supers_offset())); 819 // Length goes to R3 820 __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes())); 821 __ add(R2, R2, Array<Klass*>::base_offset_in_bytes()); 822 823 Label loop, miss; 824 __ bind(loop); 825 __ cbz(R3, miss); 826 __ ldr(LR, Address(R2, wordSize, post_indexed)); 827 __ sub(R3, R3, 1); 828 __ cmp(LR, R1); 829 __ b(loop, ne); 830 831 // We get here if an equal cache entry is found 832 __ str(R1, Address(R0, Klass::secondary_super_cache_offset())); 833 __ mov(R0, 1); 834 __ raw_pop_and_ret(R2, R3); 835 836 // A cache entry not found - return false 837 __ bind(miss); 838 __ mov(R0, 0); 839 __ raw_pop_and_ret(R2, R3); 840 } 841 break; 842 843 case monitorenter_nofpu_id: 844 save_fpu_registers = false; 845 // fall through 846 case monitorenter_id: 847 { 848 __ set_info("monitorenter", dont_gc_arguments); 849 const Register obj = R1; 850 const Register lock = R2; 851 OopMap* map = save_live_registers(sasm, save_fpu_registers); 852 __ ldr(obj, Address(SP, arg1_offset)); 853 __ ldr(lock, Address(SP, arg2_offset)); 854 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock); 855 oop_maps = new OopMapSet(); 856 oop_maps->add_gc_map(call_offset, map); 857 restore_live_registers(sasm, save_fpu_registers); 858 } 859 break; 860 861 case monitorexit_nofpu_id: 862 save_fpu_registers = false; 863 // fall through 864 case monitorexit_id: 865 { 866 __ set_info("monitorexit", dont_gc_arguments); 867 const Register lock = R1; 868 OopMap* map = save_live_registers(sasm, save_fpu_registers); 869 __ ldr(lock, Address(SP, arg1_offset)); 870 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock); 871 oop_maps = new OopMapSet(); 872 oop_maps->add_gc_map(call_offset, map); 873 restore_live_registers(sasm, save_fpu_registers); 874 } 875 break; 876 877 case deoptimize_id: 878 { 879 __ set_info("deoptimize", dont_gc_arguments); 880 OopMap* oop_map = save_live_registers(sasm); 881 const Register trap_request = R1; 882 __ ldr(trap_request, Address(SP, arg1_offset)); 883 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request); 884 oop_maps = new OopMapSet(); 885 oop_maps->add_gc_map(call_offset, oop_map); 886 restore_live_registers_without_return(sasm); 887 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 888 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 889 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg)); 890 } 891 break; 892 893 case access_field_patching_id: 894 { 895 __ set_info("access_field_patching", dont_gc_arguments); 896 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching)); 897 } 898 break; 899 900 case load_klass_patching_id: 901 { 902 __ set_info("load_klass_patching", dont_gc_arguments); 903 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching)); 904 } 905 break; 906 907 case load_appendix_patching_id: 908 { 909 __ set_info("load_appendix_patching", dont_gc_arguments); 910 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching)); 911 } 912 break; 913 914 case load_mirror_patching_id: 915 { 916 __ set_info("load_mirror_patching", dont_gc_arguments); 917 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching)); 918 } 919 break; 920 921 case predicate_failed_trap_id: 922 { 923 __ set_info("predicate_failed_trap", dont_gc_arguments); 924 925 OopMap* oop_map = save_live_registers(sasm); 926 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap)); 927 928 oop_maps = new OopMapSet(); 929 oop_maps->add_gc_map(call_offset, oop_map); 930 931 restore_live_registers_without_return(sasm); 932 933 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 934 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 935 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp); 936 } 937 break; 938 939 default: 940 { 941 __ set_info("unimplemented entry", dont_gc_arguments); 942 STOP("unimplemented entry"); 943 } 944 break; 945 } 946 return oop_maps; 947 } 948 949 #undef __ 950 951 #ifdef __SOFTFP__ 952 const char *Runtime1::pd_name_for_address(address entry) { 953 954 #define FUNCTION_CASE(a, f) \ 955 if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f)) return #f 956 957 FUNCTION_CASE(entry, __aeabi_fadd_glibc); 958 FUNCTION_CASE(entry, __aeabi_fmul); 959 FUNCTION_CASE(entry, __aeabi_fsub_glibc); 960 FUNCTION_CASE(entry, __aeabi_fdiv); 961 962 // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269. 963 FUNCTION_CASE(entry, __aeabi_dadd_glibc); 964 FUNCTION_CASE(entry, __aeabi_dmul); 965 FUNCTION_CASE(entry, __aeabi_dsub_glibc); 966 FUNCTION_CASE(entry, __aeabi_ddiv); 967 968 FUNCTION_CASE(entry, __aeabi_f2d); 969 FUNCTION_CASE(entry, __aeabi_d2f); 970 FUNCTION_CASE(entry, __aeabi_i2f); 971 FUNCTION_CASE(entry, __aeabi_i2d); 972 FUNCTION_CASE(entry, __aeabi_f2iz); 973 974 FUNCTION_CASE(entry, SharedRuntime::fcmpl); 975 FUNCTION_CASE(entry, SharedRuntime::fcmpg); 976 FUNCTION_CASE(entry, SharedRuntime::dcmpl); 977 FUNCTION_CASE(entry, SharedRuntime::dcmpg); 978 979 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt); 980 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt); 981 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple); 982 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple); 983 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge); 984 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge); 985 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt); 986 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt); 987 988 FUNCTION_CASE(entry, SharedRuntime::fneg); 989 FUNCTION_CASE(entry, SharedRuntime::dneg); 990 991 FUNCTION_CASE(entry, __aeabi_fcmpeq); 992 FUNCTION_CASE(entry, __aeabi_fcmplt); 993 FUNCTION_CASE(entry, __aeabi_fcmple); 994 FUNCTION_CASE(entry, __aeabi_fcmpge); 995 FUNCTION_CASE(entry, __aeabi_fcmpgt); 996 997 FUNCTION_CASE(entry, __aeabi_dcmpeq); 998 FUNCTION_CASE(entry, __aeabi_dcmplt); 999 FUNCTION_CASE(entry, __aeabi_dcmple); 1000 FUNCTION_CASE(entry, __aeabi_dcmpge); 1001 FUNCTION_CASE(entry, __aeabi_dcmpgt); 1002 #undef FUNCTION_CASE 1003 return ""; 1004 } 1005 #else // __SOFTFP__ 1006 const char *Runtime1::pd_name_for_address(address entry) { 1007 return "<unknown function>"; 1008 } 1009 #endif // __SOFTFP__