1 /* 2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "c1/c1_Compilation.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_MacroAssembler.hpp" 30 #include "c1/c1_Runtime1.hpp" 31 #include "c1/c1_ValueStack.hpp" 32 #include "ci/ciArrayKlass.hpp" 33 #include "ci/ciInstance.hpp" 34 #include "gc/shared/collectedHeap.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableBarrierSet.hpp" 37 #include "nativeInst_ppc.hpp" 38 #include "oops/objArrayKlass.hpp" 39 #include "runtime/frame.inline.hpp" 40 #include "runtime/safepointMechanism.inline.hpp" 41 #include "runtime/sharedRuntime.hpp" 42 43 #define __ _masm-> 44 45 46 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5; 47 48 49 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 50 Unimplemented(); return false; // Currently not used on this platform. 51 } 52 53 54 LIR_Opr LIR_Assembler::receiverOpr() { 55 return FrameMap::R3_oop_opr; 56 } 57 58 59 LIR_Opr LIR_Assembler::osrBufferPointer() { 60 return FrameMap::R3_opr; 61 } 62 63 64 // This specifies the stack pointer decrement needed to build the frame. 65 int LIR_Assembler::initial_frame_size_in_bytes() const { 66 return in_bytes(frame_map()->framesize_in_bytes()); 67 } 68 69 70 // Inline cache check: the inline cached class is in inline_cache_reg; 71 // we fetch the class of the receiver and compare it with the cached class. 72 // If they do not match we jump to slow case. 73 int LIR_Assembler::check_icache() { 74 int offset = __ offset(); 75 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg); 76 return offset; 77 } 78 79 80 void LIR_Assembler::osr_entry() { 81 // On-stack-replacement entry sequence: 82 // 83 // 1. Create a new compiled activation. 84 // 2. Initialize local variables in the compiled activation. The expression 85 // stack must be empty at the osr_bci; it is not initialized. 86 // 3. Jump to the continuation address in compiled code to resume execution. 87 88 // OSR entry point 89 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 90 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 91 ValueStack* entry_state = osr_entry->end()->state(); 92 int number_of_locks = entry_state->locks_size(); 93 94 // Create a frame for the compiled activation. 95 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 96 97 // OSR buffer is 98 // 99 // locals[nlocals-1..0] 100 // monitors[number_of_locks-1..0] 101 // 102 // Locals is a direct copy of the interpreter frame so in the osr buffer 103 // the first slot in the local array is the last local from the interpreter 104 // and the last slot is local[0] (receiver) from the interpreter. 105 // 106 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 107 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 108 // in the interpreter frame (the method lock if a sync method). 109 110 // Initialize monitors in the compiled activation. 111 // R3: pointer to osr buffer 112 // 113 // All other registers are dead at this point and the locals will be 114 // copied into place by code emitted in the IR. 115 116 Register OSR_buf = osrBufferPointer()->as_register(); 117 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 118 int monitor_offset = BytesPerWord * method()->max_locals() + 119 (2 * BytesPerWord) * (number_of_locks - 1); 120 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 121 // the OSR buffer using 2 word entries: first the lock and then 122 // the oop. 123 for (int i = 0; i < number_of_locks; i++) { 124 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 125 #ifdef ASSERT 126 // Verify the interpreter's monitor has a non-null object. 127 { 128 Label L; 129 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); 130 __ cmpdi(CCR0, R0, 0); 131 __ bne(CCR0, L); 132 __ stop("locked object is NULL"); 133 __ bind(L); 134 } 135 #endif // ASSERT 136 // Copy the lock field into the compiled activation. 137 Address ml = frame_map()->address_for_monitor_lock(i), 138 mo = frame_map()->address_for_monitor_object(i); 139 assert(ml.index() == noreg && mo.index() == noreg, "sanity"); 140 __ ld(R0, slot_offset + 0, OSR_buf); 141 __ std(R0, ml.disp(), ml.base()); 142 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); 143 __ std(R0, mo.disp(), mo.base()); 144 } 145 } 146 } 147 148 149 int LIR_Assembler::emit_exception_handler() { 150 // If the last instruction is a call (typically to do a throw which 151 // is coming at the end after block reordering) the return address 152 // must still point into the code area in order to avoid assertion 153 // failures when searching for the corresponding bci => add a nop 154 // (was bug 5/14/1999 - gri). 155 __ nop(); 156 157 // Generate code for the exception handler. 158 address handler_base = __ start_a_stub(exception_handler_size()); 159 160 if (handler_base == NULL) { 161 // Not enough space left for the handler. 162 bailout("exception handler overflow"); 163 return -1; 164 } 165 166 int offset = code_offset(); 167 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)); 168 //__ load_const_optimized(R0, entry_point); 169 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point)); 170 __ mtctr(R0); 171 __ bctr(); 172 173 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 174 __ end_a_stub(); 175 176 return offset; 177 } 178 179 180 // Emit the code to remove the frame from the stack in the exception 181 // unwind path. 182 int LIR_Assembler::emit_unwind_handler() { 183 _masm->block_comment("Unwind handler"); 184 185 int offset = code_offset(); 186 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes(); 187 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31; 188 189 // Fetch the exception from TLS and clear out exception related thread state. 190 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread); 191 __ li(R0, 0); 192 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread); 193 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread); 194 195 __ bind(_unwind_handler_entry); 196 __ verify_not_null_oop(Rexception); 197 if (preserve_exception) { __ mr(Rexception_save, Rexception); } 198 199 // Perform needed unlocking 200 MonitorExitStub* stub = NULL; 201 if (method()->is_synchronized()) { 202 monitor_address(0, FrameMap::R4_opr); 203 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0); 204 __ unlock_object(R5, R6, R4, *stub->entry()); 205 __ bind(*stub->continuation()); 206 } 207 208 if (compilation()->env()->dtrace_method_probes()) { 209 Unimplemented(); 210 } 211 212 // Dispatch to the unwind logic. 213 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id); 214 //__ load_const_optimized(R0, unwind_stub); 215 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub)); 216 if (preserve_exception) { __ mr(Rexception, Rexception_save); } 217 __ mtctr(R0); 218 __ bctr(); 219 220 // Emit the slow path assembly. 221 if (stub != NULL) { 222 stub->emit_code(this); 223 } 224 225 return offset; 226 } 227 228 229 int LIR_Assembler::emit_deopt_handler() { 230 // If the last instruction is a call (typically to do a throw which 231 // is coming at the end after block reordering) the return address 232 // must still point into the code area in order to avoid assertion 233 // failures when searching for the corresponding bci => add a nop 234 // (was bug 5/14/1999 - gri). 235 __ nop(); 236 237 // Generate code for deopt handler. 238 address handler_base = __ start_a_stub(deopt_handler_size()); 239 240 if (handler_base == NULL) { 241 // Not enough space left for the handler. 242 bailout("deopt handler overflow"); 243 return -1; 244 } 245 246 int offset = code_offset(); 247 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type); 248 249 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 250 __ end_a_stub(); 251 252 return offset; 253 } 254 255 256 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 257 if (o == NULL) { 258 __ li(reg, 0); 259 } else { 260 AddressLiteral addrlit = __ constant_oop_address(o); 261 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg); 262 } 263 } 264 265 266 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 267 // Allocate a new index in table to hold the object once it's been patched. 268 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 269 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 270 271 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index)); 272 __ load_const(reg, addrlit, R0); 273 274 patching_epilog(patch, lir_patch_normal, reg, info); 275 } 276 277 278 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { 279 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation) 280 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg); 281 } 282 283 284 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 285 // Allocate a new index in table to hold the klass once it's been patched. 286 int index = __ oop_recorder()->allocate_metadata_index(NULL); 287 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 288 289 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index)); 290 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 291 __ load_const(reg, addrlit, R0); 292 293 patching_epilog(patch, lir_patch_normal, reg, info); 294 } 295 296 297 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 298 const bool is_int = result->is_single_cpu(); 299 Register Rdividend = is_int ? left->as_register() : left->as_register_lo(); 300 Register Rdivisor = noreg; 301 Register Rscratch = temp->as_register(); 302 Register Rresult = is_int ? result->as_register() : result->as_register_lo(); 303 long divisor = -1; 304 305 if (right->is_register()) { 306 Rdivisor = is_int ? right->as_register() : right->as_register_lo(); 307 } else { 308 divisor = is_int ? right->as_constant_ptr()->as_jint() 309 : right->as_constant_ptr()->as_jlong(); 310 } 311 312 assert(Rdividend != Rscratch, ""); 313 assert(Rdivisor != Rscratch, ""); 314 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv"); 315 316 if (Rdivisor == noreg) { 317 if (divisor == 1) { // stupid, but can happen 318 if (code == lir_idiv) { 319 __ mr_if_needed(Rresult, Rdividend); 320 } else { 321 __ li(Rresult, 0); 322 } 323 324 } else if (is_power_of_2(divisor)) { 325 // Convert division by a power of two into some shifts and logical operations. 326 int log2 = log2_intptr(divisor); 327 328 // Round towards 0. 329 if (divisor == 2) { 330 if (is_int) { 331 __ srwi(Rscratch, Rdividend, 31); 332 } else { 333 __ srdi(Rscratch, Rdividend, 63); 334 } 335 } else { 336 if (is_int) { 337 __ srawi(Rscratch, Rdividend, 31); 338 } else { 339 __ sradi(Rscratch, Rdividend, 63); 340 } 341 __ clrldi(Rscratch, Rscratch, 64-log2); 342 } 343 __ add(Rscratch, Rdividend, Rscratch); 344 345 if (code == lir_idiv) { 346 if (is_int) { 347 __ srawi(Rresult, Rscratch, log2); 348 } else { 349 __ sradi(Rresult, Rscratch, log2); 350 } 351 } else { // lir_irem 352 __ clrrdi(Rscratch, Rscratch, log2); 353 __ sub(Rresult, Rdividend, Rscratch); 354 } 355 356 } else if (divisor == -1) { 357 if (code == lir_idiv) { 358 __ neg(Rresult, Rdividend); 359 } else { 360 __ li(Rresult, 0); 361 } 362 363 } else { 364 __ load_const_optimized(Rscratch, divisor); 365 if (code == lir_idiv) { 366 if (is_int) { 367 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1. 368 } else { 369 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1. 370 } 371 } else { 372 assert(Rscratch != R0, "need both"); 373 if (is_int) { 374 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1. 375 __ mullw(Rscratch, R0, Rscratch); 376 } else { 377 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1. 378 __ mulld(Rscratch, R0, Rscratch); 379 } 380 __ sub(Rresult, Rdividend, Rscratch); 381 } 382 383 } 384 return; 385 } 386 387 Label regular, done; 388 if (is_int) { 389 __ cmpwi(CCR0, Rdivisor, -1); 390 } else { 391 __ cmpdi(CCR0, Rdivisor, -1); 392 } 393 __ bne(CCR0, regular); 394 if (code == lir_idiv) { 395 __ neg(Rresult, Rdividend); 396 __ b(done); 397 __ bind(regular); 398 if (is_int) { 399 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1. 400 } else { 401 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1. 402 } 403 } else { // lir_irem 404 __ li(Rresult, 0); 405 __ b(done); 406 __ bind(regular); 407 if (is_int) { 408 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1. 409 __ mullw(Rscratch, Rscratch, Rdivisor); 410 } else { 411 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1. 412 __ mulld(Rscratch, Rscratch, Rdivisor); 413 } 414 __ sub(Rresult, Rdividend, Rscratch); 415 } 416 __ bind(done); 417 } 418 419 420 void LIR_Assembler::emit_op3(LIR_Op3* op) { 421 switch (op->code()) { 422 case lir_idiv: 423 case lir_irem: 424 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(), 425 op->result_opr(), op->info()); 426 break; 427 case lir_fmad: 428 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(), 429 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg()); 430 break; 431 case lir_fmaf: 432 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(), 433 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg()); 434 break; 435 default: ShouldNotReachHere(); break; 436 } 437 } 438 439 440 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 441 #ifdef ASSERT 442 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 443 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 444 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 445 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 446 #endif 447 448 Label *L = op->label(); 449 if (op->cond() == lir_cond_always) { 450 __ b(*L); 451 } else { 452 Label done; 453 bool is_unordered = false; 454 if (op->code() == lir_cond_float_branch) { 455 assert(op->ublock() != NULL, "must have unordered successor"); 456 is_unordered = true; 457 } else { 458 assert(op->code() == lir_branch, "just checking"); 459 } 460 461 bool positive = false; 462 Assembler::Condition cond = Assembler::equal; 463 switch (op->cond()) { 464 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break; 465 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break; 466 case lir_cond_less: positive = true ; cond = Assembler::less ; break; 467 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru 468 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break; 469 case lir_cond_greater: positive = true ; cond = Assembler::greater; break; 470 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru 471 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break; 472 default: ShouldNotReachHere(); 473 } 474 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0; 475 int bi = Assembler::bi0(BOOL_RESULT, cond); 476 if (is_unordered) { 477 if (positive) { 478 if (op->ublock() == op->block()) { 479 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L); 480 } 481 } else { 482 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); } 483 } 484 } 485 __ bc_far_optimized(bo, bi, *L); 486 __ bind(done); 487 } 488 } 489 490 491 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 492 Bytecodes::Code code = op->bytecode(); 493 LIR_Opr src = op->in_opr(), 494 dst = op->result_opr(); 495 496 switch(code) { 497 case Bytecodes::_i2l: { 498 __ extsw(dst->as_register_lo(), src->as_register()); 499 break; 500 } 501 case Bytecodes::_l2i: { 502 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage 503 break; 504 } 505 case Bytecodes::_i2b: { 506 __ extsb(dst->as_register(), src->as_register()); 507 break; 508 } 509 case Bytecodes::_i2c: { 510 __ clrldi(dst->as_register(), src->as_register(), 64-16); 511 break; 512 } 513 case Bytecodes::_i2s: { 514 __ extsh(dst->as_register(), src->as_register()); 515 break; 516 } 517 case Bytecodes::_i2d: 518 case Bytecodes::_l2d: { 519 bool src_in_memory = !VM_Version::has_mtfprd(); 520 FloatRegister rdst = dst->as_double_reg(); 521 FloatRegister rsrc; 522 if (src_in_memory) { 523 rsrc = src->as_double_reg(); // via mem 524 } else { 525 // move src to dst register 526 if (code == Bytecodes::_i2d) { 527 __ mtfprwa(rdst, src->as_register()); 528 } else { 529 __ mtfprd(rdst, src->as_register_lo()); 530 } 531 rsrc = rdst; 532 } 533 __ fcfid(rdst, rsrc); 534 break; 535 } 536 case Bytecodes::_i2f: 537 case Bytecodes::_l2f: { 538 bool src_in_memory = !VM_Version::has_mtfprd(); 539 FloatRegister rdst = dst->as_float_reg(); 540 FloatRegister rsrc; 541 if (src_in_memory) { 542 rsrc = src->as_double_reg(); // via mem 543 } else { 544 // move src to dst register 545 if (code == Bytecodes::_i2f) { 546 __ mtfprwa(rdst, src->as_register()); 547 } else { 548 __ mtfprd(rdst, src->as_register_lo()); 549 } 550 rsrc = rdst; 551 } 552 if (VM_Version::has_fcfids()) { 553 __ fcfids(rdst, rsrc); 554 } else { 555 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility"); 556 __ fcfid(rdst, rsrc); 557 __ frsp(rdst, rdst); 558 } 559 break; 560 } 561 case Bytecodes::_f2d: { 562 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg()); 563 break; 564 } 565 case Bytecodes::_d2f: { 566 __ frsp(dst->as_float_reg(), src->as_double_reg()); 567 break; 568 } 569 case Bytecodes::_d2i: 570 case Bytecodes::_f2i: { 571 bool dst_in_memory = !VM_Version::has_mtfprd(); 572 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg(); 573 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL; 574 Label L; 575 // Result must be 0 if value is NaN; test by comparing value to itself. 576 __ fcmpu(CCR0, rsrc, rsrc); 577 if (dst_in_memory) { 578 __ li(R0, 0); // 0 in case of NAN 579 __ std(R0, addr.disp(), addr.base()); 580 } else { 581 __ li(dst->as_register(), 0); 582 } 583 __ bso(CCR0, L); 584 __ fctiwz(rsrc, rsrc); // USE_KILL 585 if (dst_in_memory) { 586 __ stfd(rsrc, addr.disp(), addr.base()); 587 } else { 588 __ mffprd(dst->as_register(), rsrc); 589 } 590 __ bind(L); 591 break; 592 } 593 case Bytecodes::_d2l: 594 case Bytecodes::_f2l: { 595 bool dst_in_memory = !VM_Version::has_mtfprd(); 596 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg(); 597 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL; 598 Label L; 599 // Result must be 0 if value is NaN; test by comparing value to itself. 600 __ fcmpu(CCR0, rsrc, rsrc); 601 if (dst_in_memory) { 602 __ li(R0, 0); // 0 in case of NAN 603 __ std(R0, addr.disp(), addr.base()); 604 } else { 605 __ li(dst->as_register_lo(), 0); 606 } 607 __ bso(CCR0, L); 608 __ fctidz(rsrc, rsrc); // USE_KILL 609 if (dst_in_memory) { 610 __ stfd(rsrc, addr.disp(), addr.base()); 611 } else { 612 __ mffprd(dst->as_register_lo(), rsrc); 613 } 614 __ bind(L); 615 break; 616 } 617 618 default: ShouldNotReachHere(); 619 } 620 } 621 622 623 void LIR_Assembler::align_call(LIR_Code) { 624 // do nothing since all instructions are word aligned on ppc 625 } 626 627 628 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) { 629 int start_offset = __ offset(); 630 // Put the entry point as a constant into the constant pool. 631 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none); 632 if (entry_point_toc_addr == NULL) { 633 bailout("const section overflow"); 634 return false; 635 } 636 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 637 638 // Emit the trampoline stub which will be related to the branch-and-link below. 639 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc); 640 if (!stub) { 641 bailout("no space for trampoline stub"); 642 return false; 643 } 644 return true; 645 } 646 647 648 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 649 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype"); 650 651 bool success = emit_trampoline_stub_for_call(op->addr()); 652 if (!success) { return; } 653 654 __ relocate(rtype); 655 // Note: At this point we do not have the address of the trampoline 656 // stub, and the entry point might be too far away for bl, so __ pc() 657 // serves as dummy and the bl will be patched later. 658 __ code()->set_insts_mark(); 659 __ bl(__ pc()); 660 add_call_info(code_offset(), op->info()); 661 } 662 663 664 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 665 __ calculate_address_from_global_toc(R2_TOC, __ method_toc()); 666 667 // Virtual call relocation will point to ic load. 668 address virtual_call_meta_addr = __ pc(); 669 // Load a clear inline cache. 670 AddressLiteral empty_ic((address) Universe::non_oop_word()); 671 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC); 672 if (!success) { 673 bailout("const section overflow"); 674 return; 675 } 676 // Call to fixup routine. Fixup routine uses ScopeDesc info 677 // to determine who we intended to call. 678 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 679 680 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC); 681 if (!success) { return; } 682 683 // Note: At this point we do not have the address of the trampoline 684 // stub, and the entry point might be too far away for bl, so __ pc() 685 // serves as dummy and the bl will be patched later. 686 __ bl(__ pc()); 687 add_call_info(code_offset(), op->info()); 688 } 689 690 691 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 692 ShouldNotReachHere(); // ic_call is used instead. 693 } 694 695 696 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) { 697 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info); 698 __ null_check(addr, stub->entry()); 699 append_code_stub(stub); 700 } 701 702 703 // Attention: caller must encode oop if needed 704 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { 705 int store_offset; 706 if (!Assembler::is_simm16(offset)) { 707 // For offsets larger than a simm16 we setup the offset. 708 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case"); 709 __ load_const_optimized(R0, offset); 710 store_offset = store(from_reg, base, R0, type, wide); 711 } else { 712 store_offset = code_offset(); 713 switch (type) { 714 case T_BOOLEAN: // fall through 715 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break; 716 case T_CHAR : 717 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break; 718 case T_INT : __ stw(from_reg->as_register(), offset, base); break; 719 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break; 720 case T_ADDRESS: 721 case T_METADATA: __ std(from_reg->as_register(), offset, base); break; 722 case T_ARRAY : // fall through 723 case T_OBJECT: 724 { 725 if (UseCompressedOops && !wide) { 726 // Encoding done in caller 727 __ stw(from_reg->as_register(), offset, base); 728 } else { 729 __ std(from_reg->as_register(), offset, base); 730 } 731 __ verify_oop(from_reg->as_register()); 732 break; 733 } 734 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break; 735 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break; 736 default : ShouldNotReachHere(); 737 } 738 } 739 return store_offset; 740 } 741 742 743 // Attention: caller must encode oop if needed 744 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { 745 int store_offset = code_offset(); 746 switch (type) { 747 case T_BOOLEAN: // fall through 748 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break; 749 case T_CHAR : 750 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break; 751 case T_INT : __ stwx(from_reg->as_register(), base, disp); break; 752 case T_LONG : 753 #ifdef _LP64 754 __ stdx(from_reg->as_register_lo(), base, disp); 755 #else 756 Unimplemented(); 757 #endif 758 break; 759 case T_ADDRESS: 760 __ stdx(from_reg->as_register(), base, disp); 761 break; 762 case T_ARRAY : // fall through 763 case T_OBJECT: 764 { 765 if (UseCompressedOops && !wide) { 766 // Encoding done in caller. 767 __ stwx(from_reg->as_register(), base, disp); 768 } else { 769 __ stdx(from_reg->as_register(), base, disp); 770 } 771 __ verify_oop(from_reg->as_register()); // kills R0 772 break; 773 } 774 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break; 775 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break; 776 default : ShouldNotReachHere(); 777 } 778 return store_offset; 779 } 780 781 782 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { 783 int load_offset; 784 if (!Assembler::is_simm16(offset)) { 785 // For offsets larger than a simm16 we setup the offset. 786 __ load_const_optimized(R0, offset); 787 load_offset = load(base, R0, to_reg, type, wide); 788 } else { 789 load_offset = code_offset(); 790 switch(type) { 791 case T_BOOLEAN: // fall through 792 case T_BYTE : __ lbz(to_reg->as_register(), offset, base); 793 __ extsb(to_reg->as_register(), to_reg->as_register()); break; 794 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break; 795 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break; 796 case T_INT : __ lwa(to_reg->as_register(), offset, base); break; 797 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break; 798 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break; 799 case T_ADDRESS: 800 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) { 801 __ lwz(to_reg->as_register(), offset, base); 802 __ decode_klass_not_null(to_reg->as_register()); 803 } else { 804 __ ld(to_reg->as_register(), offset, base); 805 } 806 break; 807 case T_ARRAY : // fall through 808 case T_OBJECT: 809 { 810 if (UseCompressedOops && !wide) { 811 __ lwz(to_reg->as_register(), offset, base); 812 __ decode_heap_oop(to_reg->as_register()); 813 } else { 814 __ ld(to_reg->as_register(), offset, base); 815 } 816 __ verify_oop(to_reg->as_register()); 817 break; 818 } 819 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break; 820 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break; 821 default : ShouldNotReachHere(); 822 } 823 } 824 return load_offset; 825 } 826 827 828 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { 829 int load_offset = code_offset(); 830 switch(type) { 831 case T_BOOLEAN: // fall through 832 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp); 833 __ extsb(to_reg->as_register(), to_reg->as_register()); break; 834 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break; 835 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break; 836 case T_INT : __ lwax(to_reg->as_register(), base, disp); break; 837 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break; 838 case T_ARRAY : // fall through 839 case T_OBJECT: 840 { 841 if (UseCompressedOops && !wide) { 842 __ lwzx(to_reg->as_register(), base, disp); 843 __ decode_heap_oop(to_reg->as_register()); 844 } else { 845 __ ldx(to_reg->as_register(), base, disp); 846 } 847 __ verify_oop(to_reg->as_register()); 848 break; 849 } 850 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break; 851 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break; 852 case T_LONG : 853 #ifdef _LP64 854 __ ldx(to_reg->as_register_lo(), base, disp); 855 #else 856 Unimplemented(); 857 #endif 858 break; 859 default : ShouldNotReachHere(); 860 } 861 return load_offset; 862 } 863 864 865 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 866 LIR_Const* c = src->as_constant_ptr(); 867 Register src_reg = R0; 868 switch (c->type()) { 869 case T_INT: 870 case T_FLOAT: { 871 int value = c->as_jint_bits(); 872 __ load_const_optimized(src_reg, value); 873 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 874 __ stw(src_reg, addr.disp(), addr.base()); 875 break; 876 } 877 case T_ADDRESS: { 878 int value = c->as_jint_bits(); 879 __ load_const_optimized(src_reg, value); 880 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 881 __ std(src_reg, addr.disp(), addr.base()); 882 break; 883 } 884 case T_OBJECT: { 885 jobject2reg(c->as_jobject(), src_reg); 886 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 887 __ std(src_reg, addr.disp(), addr.base()); 888 break; 889 } 890 case T_LONG: 891 case T_DOUBLE: { 892 int value = c->as_jlong_bits(); 893 __ load_const_optimized(src_reg, value); 894 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 895 __ std(src_reg, addr.disp(), addr.base()); 896 break; 897 } 898 default: 899 Unimplemented(); 900 } 901 } 902 903 904 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 905 LIR_Const* c = src->as_constant_ptr(); 906 LIR_Address* addr = dest->as_address_ptr(); 907 Register base = addr->base()->as_pointer_register(); 908 LIR_Opr tmp = LIR_OprFact::illegalOpr; 909 int offset = -1; 910 // Null check for large offsets in LIRGenerator::do_StoreField. 911 bool needs_explicit_null_check = !ImplicitNullChecks; 912 913 if (info != NULL && needs_explicit_null_check) { 914 explicit_null_check(base, info); 915 } 916 917 switch (c->type()) { 918 case T_FLOAT: type = T_INT; 919 case T_INT: 920 case T_ADDRESS: { 921 tmp = FrameMap::R0_opr; 922 __ load_const_optimized(tmp->as_register(), c->as_jint_bits()); 923 break; 924 } 925 case T_DOUBLE: type = T_LONG; 926 case T_LONG: { 927 tmp = FrameMap::R0_long_opr; 928 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits()); 929 break; 930 } 931 case T_OBJECT: { 932 tmp = FrameMap::R0_opr; 933 if (UseCompressedOops && !wide && c->as_jobject() != NULL) { 934 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject()); 935 __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw). 936 __ relocate(oop_addr.rspec(), /*compressed format*/ 1); 937 __ ori(R0, R0, oop_addr.value() & 0xffff); 938 } else { 939 jobject2reg(c->as_jobject(), R0); 940 } 941 break; 942 } 943 default: 944 Unimplemented(); 945 } 946 947 // Handle either reg+reg or reg+disp address. 948 if (addr->index()->is_valid()) { 949 assert(addr->disp() == 0, "must be zero"); 950 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 951 } else { 952 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses"); 953 offset = store(tmp, base, addr->disp(), type, wide, false); 954 } 955 956 if (info != NULL) { 957 assert(offset != -1, "offset should've been set"); 958 if (!needs_explicit_null_check) { 959 add_debug_info_for_null_check(offset, info); 960 } 961 } 962 } 963 964 965 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 966 LIR_Const* c = src->as_constant_ptr(); 967 LIR_Opr to_reg = dest; 968 969 switch (c->type()) { 970 case T_INT: { 971 assert(patch_code == lir_patch_none, "no patching handled here"); 972 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); 973 break; 974 } 975 case T_ADDRESS: { 976 assert(patch_code == lir_patch_none, "no patching handled here"); 977 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ... 978 break; 979 } 980 case T_LONG: { 981 assert(patch_code == lir_patch_none, "no patching handled here"); 982 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0); 983 break; 984 } 985 986 case T_OBJECT: { 987 if (patch_code == lir_patch_none) { 988 jobject2reg(c->as_jobject(), to_reg->as_register()); 989 } else { 990 jobject2reg_with_patching(to_reg->as_register(), info); 991 } 992 break; 993 } 994 995 case T_METADATA: 996 { 997 if (patch_code == lir_patch_none) { 998 metadata2reg(c->as_metadata(), to_reg->as_register()); 999 } else { 1000 klass2reg_with_patching(to_reg->as_register(), info); 1001 } 1002 } 1003 break; 1004 1005 case T_FLOAT: 1006 { 1007 if (to_reg->is_single_fpu()) { 1008 address const_addr = __ float_constant(c->as_jfloat()); 1009 if (const_addr == NULL) { 1010 bailout("const section overflow"); 1011 break; 1012 } 1013 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1014 __ relocate(rspec); 1015 __ load_const(R0, const_addr); 1016 __ lfsx(to_reg->as_float_reg(), R0); 1017 } else { 1018 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1019 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0); 1020 } 1021 } 1022 break; 1023 1024 case T_DOUBLE: 1025 { 1026 if (to_reg->is_double_fpu()) { 1027 address const_addr = __ double_constant(c->as_jdouble()); 1028 if (const_addr == NULL) { 1029 bailout("const section overflow"); 1030 break; 1031 } 1032 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1033 __ relocate(rspec); 1034 __ load_const(R0, const_addr); 1035 __ lfdx(to_reg->as_double_reg(), R0); 1036 } else { 1037 assert(to_reg->is_double_cpu(), "Must be a long register."); 1038 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0); 1039 } 1040 } 1041 break; 1042 1043 default: 1044 ShouldNotReachHere(); 1045 } 1046 } 1047 1048 1049 Address LIR_Assembler::as_Address(LIR_Address* addr) { 1050 Unimplemented(); return Address(); 1051 } 1052 1053 1054 inline RegisterOrConstant index_or_disp(LIR_Address* addr) { 1055 if (addr->index()->is_illegal()) { 1056 return (RegisterOrConstant)(addr->disp()); 1057 } else { 1058 return (RegisterOrConstant)(addr->index()->as_pointer_register()); 1059 } 1060 } 1061 1062 1063 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1064 const Register tmp = R0; 1065 switch (type) { 1066 case T_INT: 1067 case T_FLOAT: { 1068 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1069 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1070 __ lwz(tmp, from.disp(), from.base()); 1071 __ stw(tmp, to.disp(), to.base()); 1072 break; 1073 } 1074 case T_ADDRESS: 1075 case T_OBJECT: { 1076 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1077 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1078 __ ld(tmp, from.disp(), from.base()); 1079 __ std(tmp, to.disp(), to.base()); 1080 break; 1081 } 1082 case T_LONG: 1083 case T_DOUBLE: { 1084 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1085 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1086 __ ld(tmp, from.disp(), from.base()); 1087 __ std(tmp, to.disp(), to.base()); 1088 break; 1089 } 1090 1091 default: 1092 ShouldNotReachHere(); 1093 } 1094 } 1095 1096 1097 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1098 Unimplemented(); return Address(); 1099 } 1100 1101 1102 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1103 Unimplemented(); return Address(); 1104 } 1105 1106 1107 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1108 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { 1109 1110 assert(type != T_METADATA, "load of metadata ptr not supported"); 1111 LIR_Address* addr = src_opr->as_address_ptr(); 1112 LIR_Opr to_reg = dest; 1113 1114 Register src = addr->base()->as_pointer_register(); 1115 Register disp_reg = noreg; 1116 int disp_value = addr->disp(); 1117 bool needs_patching = (patch_code != lir_patch_none); 1118 // null check for large offsets in LIRGenerator::do_LoadField 1119 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks; 1120 1121 if (info != NULL && needs_explicit_null_check) { 1122 explicit_null_check(src, info); 1123 } 1124 1125 if (addr->base()->type() == T_OBJECT) { 1126 __ verify_oop(src); 1127 } 1128 1129 PatchingStub* patch = NULL; 1130 if (needs_patching) { 1131 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1132 assert(!to_reg->is_double_cpu() || 1133 patch_code == lir_patch_none || 1134 patch_code == lir_patch_normal, "patching doesn't match register"); 1135 } 1136 1137 if (addr->index()->is_illegal()) { 1138 if (!Assembler::is_simm16(disp_value)) { 1139 if (needs_patching) { 1140 __ load_const32(R0, 0); // patchable int 1141 } else { 1142 __ load_const_optimized(R0, disp_value); 1143 } 1144 disp_reg = R0; 1145 } 1146 } else { 1147 disp_reg = addr->index()->as_pointer_register(); 1148 assert(disp_value == 0, "can't handle 3 operand addresses"); 1149 } 1150 1151 // Remember the offset of the load. The patching_epilog must be done 1152 // before the call to add_debug_info, otherwise the PcDescs don't get 1153 // entered in increasing order. 1154 int offset; 1155 1156 if (disp_reg == noreg) { 1157 assert(Assembler::is_simm16(disp_value), "should have set this up"); 1158 offset = load(src, disp_value, to_reg, type, wide, unaligned); 1159 } else { 1160 assert(!unaligned, "unexpected"); 1161 offset = load(src, disp_reg, to_reg, type, wide); 1162 } 1163 1164 if (patch != NULL) { 1165 patching_epilog(patch, patch_code, src, info); 1166 } 1167 if (info != NULL && !needs_explicit_null_check) { 1168 add_debug_info_for_null_check(offset, info); 1169 } 1170 } 1171 1172 1173 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1174 Address addr; 1175 if (src->is_single_word()) { 1176 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1177 } else if (src->is_double_word()) { 1178 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1179 } 1180 1181 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1182 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); 1183 } 1184 1185 1186 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1187 Address addr; 1188 if (dest->is_single_word()) { 1189 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1190 } else if (dest->is_double_word()) { 1191 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1192 } 1193 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1194 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); 1195 } 1196 1197 1198 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1199 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1200 if (from_reg->is_double_fpu()) { 1201 // double to double moves 1202 assert(to_reg->is_double_fpu(), "should match"); 1203 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg()); 1204 } else { 1205 // float to float moves 1206 assert(to_reg->is_single_fpu(), "should match"); 1207 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg()); 1208 } 1209 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1210 if (from_reg->is_double_cpu()) { 1211 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register()); 1212 } else if (to_reg->is_double_cpu()) { 1213 // int to int moves 1214 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register()); 1215 } else { 1216 // int to int moves 1217 __ mr_if_needed(to_reg->as_register(), from_reg->as_register()); 1218 } 1219 } else { 1220 ShouldNotReachHere(); 1221 } 1222 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1223 __ verify_oop(to_reg->as_register()); 1224 } 1225 } 1226 1227 1228 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1229 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1230 bool wide, bool unaligned) { 1231 assert(type != T_METADATA, "store of metadata ptr not supported"); 1232 LIR_Address* addr = dest->as_address_ptr(); 1233 1234 Register src = addr->base()->as_pointer_register(); 1235 Register disp_reg = noreg; 1236 int disp_value = addr->disp(); 1237 bool needs_patching = (patch_code != lir_patch_none); 1238 bool compress_oop = (type == T_ARRAY || type == T_OBJECT) && UseCompressedOops && !wide && 1239 Universe::narrow_oop_mode() != Universe::UnscaledNarrowOop; 1240 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value); 1241 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29. 1242 // Null check for large offsets in LIRGenerator::do_StoreField. 1243 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29; 1244 1245 if (info != NULL && needs_explicit_null_check) { 1246 explicit_null_check(src, info); 1247 } 1248 1249 if (addr->base()->is_oop_register()) { 1250 __ verify_oop(src); 1251 } 1252 1253 PatchingStub* patch = NULL; 1254 if (needs_patching) { 1255 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1256 assert(!from_reg->is_double_cpu() || 1257 patch_code == lir_patch_none || 1258 patch_code == lir_patch_normal, "patching doesn't match register"); 1259 } 1260 1261 if (addr->index()->is_illegal()) { 1262 if (load_disp) { 1263 disp_reg = use_R29 ? R29_TOC : R0; 1264 if (needs_patching) { 1265 __ load_const32(disp_reg, 0); // patchable int 1266 } else { 1267 __ load_const_optimized(disp_reg, disp_value); 1268 } 1269 } 1270 } else { 1271 disp_reg = addr->index()->as_pointer_register(); 1272 assert(disp_value == 0, "can't handle 3 operand addresses"); 1273 } 1274 1275 // remember the offset of the store. The patching_epilog must be done 1276 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1277 // entered in increasing order. 1278 int offset; 1279 1280 if (compress_oop) { 1281 Register co = __ encode_heap_oop(R0, from_reg->as_register()); 1282 from_reg = FrameMap::as_opr(co); 1283 } 1284 1285 if (disp_reg == noreg) { 1286 assert(Assembler::is_simm16(disp_value), "should have set this up"); 1287 offset = store(from_reg, src, disp_value, type, wide, unaligned); 1288 } else { 1289 assert(!unaligned, "unexpected"); 1290 offset = store(from_reg, src, disp_reg, type, wide); 1291 } 1292 1293 if (use_R29) { 1294 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit 1295 } 1296 1297 if (patch != NULL) { 1298 patching_epilog(patch, patch_code, src, info); 1299 } 1300 1301 if (info != NULL && !needs_explicit_null_check) { 1302 add_debug_info_for_null_check(offset, info); 1303 } 1304 } 1305 1306 1307 void LIR_Assembler::return_op(LIR_Opr result) { 1308 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone(). 1309 const Register polling_page = R12; 1310 1311 // Pop the stack before the safepoint code. 1312 int frame_size = initial_frame_size_in_bytes(); 1313 if (Assembler::is_simm(frame_size, 16)) { 1314 __ addi(R1_SP, R1_SP, frame_size); 1315 } else { 1316 __ pop_frame(); 1317 } 1318 1319 if (SafepointMechanism::uses_thread_local_poll()) { 1320 __ ld(polling_page, in_bytes(Thread::polling_page_offset()), R16_thread); 1321 } else { 1322 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0); 1323 } 1324 1325 // Restore return pc relative to callers' sp. 1326 __ ld(return_pc, _abi(lr), R1_SP); 1327 // Move return pc to LR. 1328 __ mtlr(return_pc); 1329 1330 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1331 __ reserved_stack_check(return_pc); 1332 } 1333 1334 // We need to mark the code position where the load from the safepoint 1335 // polling page was emitted as relocInfo::poll_return_type here. 1336 __ relocate(relocInfo::poll_return_type); 1337 __ load_from_polling_page(polling_page); 1338 1339 // Return. 1340 __ blr(); 1341 } 1342 1343 1344 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1345 const Register poll_addr = tmp->as_register(); 1346 if (SafepointMechanism::uses_thread_local_poll()) { 1347 __ ld(poll_addr, in_bytes(Thread::polling_page_offset()), R16_thread); 1348 } else { 1349 __ load_const_optimized(poll_addr, (intptr_t)os::get_polling_page(), R0); 1350 } 1351 if (info != NULL) { 1352 add_debug_info_for_branch(info); 1353 } 1354 int offset = __ offset(); 1355 __ relocate(relocInfo::poll_type); 1356 __ load_from_polling_page(poll_addr); 1357 1358 return offset; 1359 } 1360 1361 1362 void LIR_Assembler::emit_static_call_stub() { 1363 address call_pc = __ pc(); 1364 address stub = __ start_a_stub(static_call_stub_size()); 1365 if (stub == NULL) { 1366 bailout("static call stub overflow"); 1367 return; 1368 } 1369 1370 // For java_to_interp stubs we use R11_scratch1 as scratch register 1371 // and in call trampoline stubs we use R12_scratch2. This way we 1372 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1373 const Register reg_scratch = R11_scratch1; 1374 1375 // Create a static stub relocation which relates this stub 1376 // with the call instruction at insts_call_instruction_offset in the 1377 // instructions code-section. 1378 int start = __ offset(); 1379 __ relocate(static_stub_Relocation::spec(call_pc)); 1380 1381 // Now, create the stub's code: 1382 // - load the TOC 1383 // - load the inline cache oop from the constant pool 1384 // - load the call target from the constant pool 1385 // - call 1386 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1387 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL); 1388 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true); 1389 1390 if (ReoptimizeCallSequences) { 1391 __ b64_patchable((address)-1, relocInfo::none); 1392 } else { 1393 AddressLiteral a((address)-1); 1394 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true); 1395 __ mtctr(reg_scratch); 1396 __ bctr(); 1397 } 1398 if (!success) { 1399 bailout("const section overflow"); 1400 return; 1401 } 1402 1403 assert(__ offset() - start <= static_call_stub_size(), "stub too big"); 1404 __ end_a_stub(); 1405 } 1406 1407 1408 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1409 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual); 1410 if (opr1->is_single_fpu()) { 1411 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg()); 1412 } else if (opr1->is_double_fpu()) { 1413 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg()); 1414 } else if (opr1->is_single_cpu()) { 1415 if (opr2->is_constant()) { 1416 switch (opr2->as_constant_ptr()->type()) { 1417 case T_INT: 1418 { 1419 jint con = opr2->as_constant_ptr()->as_jint(); 1420 if (unsigned_comp) { 1421 if (Assembler::is_uimm(con, 16)) { 1422 __ cmplwi(BOOL_RESULT, opr1->as_register(), con); 1423 } else { 1424 __ load_const_optimized(R0, con); 1425 __ cmplw(BOOL_RESULT, opr1->as_register(), R0); 1426 } 1427 } else { 1428 if (Assembler::is_simm(con, 16)) { 1429 __ cmpwi(BOOL_RESULT, opr1->as_register(), con); 1430 } else { 1431 __ load_const_optimized(R0, con); 1432 __ cmpw(BOOL_RESULT, opr1->as_register(), R0); 1433 } 1434 } 1435 } 1436 break; 1437 1438 case T_OBJECT: 1439 // There are only equal/notequal comparisons on objects. 1440 { 1441 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1442 jobject con = opr2->as_constant_ptr()->as_jobject(); 1443 if (con == NULL) { 1444 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0); 1445 } else { 1446 jobject2reg(con, R0); 1447 __ cmpd(BOOL_RESULT, opr1->as_register(), R0); 1448 } 1449 } 1450 break; 1451 1452 default: 1453 ShouldNotReachHere(); 1454 break; 1455 } 1456 } else { 1457 if (opr2->is_address()) { 1458 DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment. 1459 LIR_Address *addr = opr2->as_address_ptr(); 1460 BasicType type = addr->type(); 1461 if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); } 1462 else { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); } 1463 __ cmpd(BOOL_RESULT, opr1->as_register(), R0); 1464 } else { 1465 if (unsigned_comp) { 1466 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1467 } else { 1468 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register()); 1469 } 1470 } 1471 } 1472 } else if (opr1->is_double_cpu()) { 1473 if (opr2->is_constant()) { 1474 jlong con = opr2->as_constant_ptr()->as_jlong(); 1475 if (unsigned_comp) { 1476 if (Assembler::is_uimm(con, 16)) { 1477 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con); 1478 } else { 1479 __ load_const_optimized(R0, con); 1480 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0); 1481 } 1482 } else { 1483 if (Assembler::is_simm(con, 16)) { 1484 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con); 1485 } else { 1486 __ load_const_optimized(R0, con); 1487 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0); 1488 } 1489 } 1490 } else if (opr2->is_register()) { 1491 if (unsigned_comp) { 1492 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo()); 1493 } else { 1494 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo()); 1495 } 1496 } else { 1497 ShouldNotReachHere(); 1498 } 1499 } else if (opr1->is_address()) { 1500 DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment. 1501 LIR_Address * addr = opr1->as_address_ptr(); 1502 BasicType type = addr->type(); 1503 assert (opr2->is_constant(), "Checking"); 1504 if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); } 1505 else { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); } 1506 __ cmpdi(BOOL_RESULT, R0, opr2->as_constant_ptr()->as_jint()); 1507 } else { 1508 ShouldNotReachHere(); 1509 } 1510 } 1511 1512 1513 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1514 const Register Rdst = dst->as_register(); 1515 Label done; 1516 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1517 bool is_unordered_less = (code == lir_ucmp_fd2i); 1518 if (left->is_single_fpu()) { 1519 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg()); 1520 } else if (left->is_double_fpu()) { 1521 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg()); 1522 } else { 1523 ShouldNotReachHere(); 1524 } 1525 __ li(Rdst, is_unordered_less ? -1 : 1); 1526 __ bso(CCR0, done); 1527 } else if (code == lir_cmp_l2i) { 1528 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo()); 1529 } else { 1530 ShouldNotReachHere(); 1531 } 1532 __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01 1533 __ srwi(Rdst, R0, 30); 1534 __ srawi(R0, R0, 31); 1535 __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1 1536 __ bind(done); 1537 } 1538 1539 1540 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) { 1541 if (src->is_constant()) { 1542 lasm->const2reg(src, dst, lir_patch_none, NULL); 1543 } else if (src->is_register()) { 1544 lasm->reg2reg(src, dst); 1545 } else if (src->is_stack()) { 1546 lasm->stack2reg(src, dst, dst->type()); 1547 } else { 1548 ShouldNotReachHere(); 1549 } 1550 } 1551 1552 1553 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1554 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) { 1555 load_to_reg(this, opr1, result); // Condition doesn't matter. 1556 return; 1557 } 1558 1559 bool positive = false; 1560 Assembler::Condition cond = Assembler::equal; 1561 switch (condition) { 1562 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break; 1563 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break; 1564 case lir_cond_less: positive = true ; cond = Assembler::less ; break; 1565 case lir_cond_belowEqual: 1566 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break; 1567 case lir_cond_greater: positive = true ; cond = Assembler::greater; break; 1568 case lir_cond_aboveEqual: 1569 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break; 1570 default: ShouldNotReachHere(); 1571 } 1572 1573 // Try to use isel on >=Power7. 1574 if (VM_Version::has_isel() && result->is_cpu_register()) { 1575 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register(); 1576 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo(); 1577 1578 // We can use result_reg to load one operand if not already in register. 1579 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg, 1580 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg; 1581 1582 if (first != second) { 1583 if (!o1_is_reg) { 1584 load_to_reg(this, opr1, result); 1585 } 1586 1587 if (!o2_is_reg) { 1588 load_to_reg(this, opr2, result); 1589 } 1590 1591 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second); 1592 return; 1593 } 1594 } // isel 1595 1596 load_to_reg(this, opr1, result); 1597 1598 Label skip; 1599 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0; 1600 int bi = Assembler::bi0(BOOL_RESULT, cond); 1601 __ bc(bo, bi, skip); 1602 1603 load_to_reg(this, opr2, result); 1604 __ bind(skip); 1605 } 1606 1607 1608 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, 1609 CodeEmitInfo* info, bool pop_fpu_stack) { 1610 assert(info == NULL, "unused on this code path"); 1611 assert(left->is_register(), "wrong items state"); 1612 assert(dest->is_register(), "wrong items state"); 1613 1614 if (right->is_register()) { 1615 if (dest->is_float_kind()) { 1616 1617 FloatRegister lreg, rreg, res; 1618 if (right->is_single_fpu()) { 1619 lreg = left->as_float_reg(); 1620 rreg = right->as_float_reg(); 1621 res = dest->as_float_reg(); 1622 switch (code) { 1623 case lir_add: __ fadds(res, lreg, rreg); break; 1624 case lir_sub: __ fsubs(res, lreg, rreg); break; 1625 case lir_mul: // fall through 1626 case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break; 1627 case lir_div: // fall through 1628 case lir_div_strictfp: __ fdivs(res, lreg, rreg); break; 1629 default: ShouldNotReachHere(); 1630 } 1631 } else { 1632 lreg = left->as_double_reg(); 1633 rreg = right->as_double_reg(); 1634 res = dest->as_double_reg(); 1635 switch (code) { 1636 case lir_add: __ fadd(res, lreg, rreg); break; 1637 case lir_sub: __ fsub(res, lreg, rreg); break; 1638 case lir_mul: // fall through 1639 case lir_mul_strictfp: __ fmul(res, lreg, rreg); break; 1640 case lir_div: // fall through 1641 case lir_div_strictfp: __ fdiv(res, lreg, rreg); break; 1642 default: ShouldNotReachHere(); 1643 } 1644 } 1645 1646 } else if (dest->is_double_cpu()) { 1647 1648 Register dst_lo = dest->as_register_lo(); 1649 Register op1_lo = left->as_pointer_register(); 1650 Register op2_lo = right->as_pointer_register(); 1651 1652 switch (code) { 1653 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break; 1654 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break; 1655 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break; 1656 default: ShouldNotReachHere(); 1657 } 1658 } else { 1659 assert (right->is_single_cpu(), "Just Checking"); 1660 1661 Register lreg = left->as_register(); 1662 Register res = dest->as_register(); 1663 Register rreg = right->as_register(); 1664 switch (code) { 1665 case lir_add: __ add (res, lreg, rreg); break; 1666 case lir_sub: __ sub (res, lreg, rreg); break; 1667 case lir_mul: __ mullw(res, lreg, rreg); break; 1668 default: ShouldNotReachHere(); 1669 } 1670 } 1671 } else { 1672 assert (right->is_constant(), "must be constant"); 1673 1674 if (dest->is_single_cpu()) { 1675 Register lreg = left->as_register(); 1676 Register res = dest->as_register(); 1677 int simm16 = right->as_constant_ptr()->as_jint(); 1678 1679 switch (code) { 1680 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int 1681 simm16 = -simm16; 1682 case lir_add: if (res == lreg && simm16 == 0) break; 1683 __ addi(res, lreg, simm16); break; 1684 case lir_mul: if (res == lreg && simm16 == 1) break; 1685 __ mulli(res, lreg, simm16); break; 1686 default: ShouldNotReachHere(); 1687 } 1688 } else { 1689 Register lreg = left->as_pointer_register(); 1690 Register res = dest->as_register_lo(); 1691 long con = right->as_constant_ptr()->as_jlong(); 1692 assert(Assembler::is_simm16(con), "must be simm16"); 1693 1694 switch (code) { 1695 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long 1696 con = -con; 1697 case lir_add: if (res == lreg && con == 0) break; 1698 __ addi(res, lreg, (int)con); break; 1699 case lir_mul: if (res == lreg && con == 1) break; 1700 __ mulli(res, lreg, (int)con); break; 1701 default: ShouldNotReachHere(); 1702 } 1703 } 1704 } 1705 } 1706 1707 1708 void LIR_Assembler::fpop() { 1709 Unimplemented(); 1710 // do nothing 1711 } 1712 1713 1714 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1715 switch (code) { 1716 case lir_sqrt: { 1717 __ fsqrt(dest->as_double_reg(), value->as_double_reg()); 1718 break; 1719 } 1720 case lir_abs: { 1721 __ fabs(dest->as_double_reg(), value->as_double_reg()); 1722 break; 1723 } 1724 default: { 1725 ShouldNotReachHere(); 1726 break; 1727 } 1728 } 1729 } 1730 1731 1732 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1733 if (right->is_constant()) { // see do_LogicOp 1734 long uimm; 1735 Register d, l; 1736 if (dest->is_single_cpu()) { 1737 uimm = right->as_constant_ptr()->as_jint(); 1738 d = dest->as_register(); 1739 l = left->as_register(); 1740 } else { 1741 uimm = right->as_constant_ptr()->as_jlong(); 1742 d = dest->as_register_lo(); 1743 l = left->as_register_lo(); 1744 } 1745 long uimms = (unsigned long)uimm >> 16, 1746 uimmss = (unsigned long)uimm >> 32; 1747 1748 switch (code) { 1749 case lir_logic_and: 1750 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) { 1751 __ andi(d, l, uimm); // special cases 1752 } else if (uimms != 0) { __ andis_(d, l, uimms); } 1753 else { __ andi_(d, l, uimm); } 1754 break; 1755 1756 case lir_logic_or: 1757 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); } 1758 else { __ ori(d, l, uimm); } 1759 break; 1760 1761 case lir_logic_xor: 1762 if (uimm == -1) { __ nand(d, l, l); } // special case 1763 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); } 1764 else { __ xori(d, l, uimm); } 1765 break; 1766 1767 default: ShouldNotReachHere(); 1768 } 1769 } else { 1770 assert(right->is_register(), "right should be in register"); 1771 1772 if (dest->is_single_cpu()) { 1773 switch (code) { 1774 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break; 1775 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break; 1776 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break; 1777 default: ShouldNotReachHere(); 1778 } 1779 } else { 1780 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 1781 left->as_register_lo(); 1782 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 1783 right->as_register_lo(); 1784 1785 switch (code) { 1786 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break; 1787 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break; 1788 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break; 1789 default: ShouldNotReachHere(); 1790 } 1791 } 1792 } 1793 } 1794 1795 1796 int LIR_Assembler::shift_amount(BasicType t) { 1797 int elem_size = type2aelembytes(t); 1798 switch (elem_size) { 1799 case 1 : return 0; 1800 case 2 : return 1; 1801 case 4 : return 2; 1802 case 8 : return 3; 1803 } 1804 ShouldNotReachHere(); 1805 return -1; 1806 } 1807 1808 1809 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1810 info->add_register_oop(exceptionOop); 1811 1812 // Reuse the debug info from the safepoint poll for the throw op itself. 1813 address pc_for_athrow = __ pc(); 1814 int pc_for_athrow_offset = __ offset(); 1815 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 1816 //__ relocate(rspec); 1817 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0); 1818 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true); 1819 add_call_info(pc_for_athrow_offset, info); // for exception handler 1820 1821 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id 1822 : Runtime1::handle_exception_nofpu_id); 1823 //__ load_const_optimized(R0, stub); 1824 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub)); 1825 __ mtctr(R0); 1826 __ bctr(); 1827 } 1828 1829 1830 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1831 // Note: Not used with EnableDebuggingOnDemand. 1832 assert(exceptionOop->as_register() == R3, "should match"); 1833 __ b(_unwind_handler_entry); 1834 } 1835 1836 1837 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1838 Register src = op->src()->as_register(); 1839 Register dst = op->dst()->as_register(); 1840 Register src_pos = op->src_pos()->as_register(); 1841 Register dst_pos = op->dst_pos()->as_register(); 1842 Register length = op->length()->as_register(); 1843 Register tmp = op->tmp()->as_register(); 1844 Register tmp2 = R0; 1845 1846 int flags = op->flags(); 1847 ciArrayKlass* default_type = op->expected_type(); 1848 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1849 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1850 1851 // Set up the arraycopy stub information. 1852 ArrayCopyStub* stub = op->stub(); 1853 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame. 1854 1855 // Always do stub if no type information is available. It's ok if 1856 // the known type isn't loaded since the code sanity checks 1857 // in debug mode and the type isn't required when we know the exact type 1858 // also check that the type is an array type. 1859 if (op->expected_type() == NULL) { 1860 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() && 1861 length->is_nonvolatile(), "must preserve"); 1862 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1863 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 1864 1865 // 3 parms are int. Convert to long. 1866 __ mr(R3_ARG1, src); 1867 __ extsw(R4_ARG2, src_pos); 1868 __ mr(R5_ARG3, dst); 1869 __ extsw(R6_ARG4, dst_pos); 1870 __ extsw(R7_ARG5, length); 1871 1872 #ifndef PRODUCT 1873 if (PrintC1Statistics) { 1874 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; 1875 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 1876 __ lwz(R11_scratch1, simm16_offs, tmp); 1877 __ addi(R11_scratch1, R11_scratch1, 1); 1878 __ stw(R11_scratch1, simm16_offs, tmp); 1879 } 1880 #endif 1881 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0); 1882 1883 __ nand(tmp, R3_RET, R3_RET); 1884 __ subf(length, tmp, length); 1885 __ add(src_pos, tmp, src_pos); 1886 __ add(dst_pos, tmp, dst_pos); 1887 1888 __ cmpwi(CCR0, R3_RET, 0); 1889 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry()); 1890 __ bind(*stub->continuation()); 1891 return; 1892 } 1893 1894 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 1895 Label cont, slow, copyfunc; 1896 1897 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check | 1898 LIR_OpArrayCopy::dst_null_check | 1899 LIR_OpArrayCopy::src_pos_positive_check | 1900 LIR_OpArrayCopy::dst_pos_positive_check | 1901 LIR_OpArrayCopy::length_positive_check); 1902 1903 // Use only one conditional branch for simple checks. 1904 if (simple_check_flag_set) { 1905 ConditionRegister combined_check = CCR1, tmp_check = CCR1; 1906 1907 // Make sure src and dst are non-null. 1908 if (flags & LIR_OpArrayCopy::src_null_check) { 1909 __ cmpdi(combined_check, src, 0); 1910 tmp_check = CCR0; 1911 } 1912 1913 if (flags & LIR_OpArrayCopy::dst_null_check) { 1914 __ cmpdi(tmp_check, dst, 0); 1915 if (tmp_check != combined_check) { 1916 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal); 1917 } 1918 tmp_check = CCR0; 1919 } 1920 1921 // Clear combined_check.eq if not already used. 1922 if (tmp_check == combined_check) { 1923 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal); 1924 tmp_check = CCR0; 1925 } 1926 1927 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 1928 // Test src_pos register. 1929 __ cmpwi(tmp_check, src_pos, 0); 1930 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1931 } 1932 1933 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 1934 // Test dst_pos register. 1935 __ cmpwi(tmp_check, dst_pos, 0); 1936 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1937 } 1938 1939 if (flags & LIR_OpArrayCopy::length_positive_check) { 1940 // Make sure length isn't negative. 1941 __ cmpwi(tmp_check, length, 0); 1942 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less); 1943 } 1944 1945 __ beq(combined_check, slow); 1946 } 1947 1948 // If the compiler was not able to prove that exact type of the source or the destination 1949 // of the arraycopy is an array type, check at runtime if the source or the destination is 1950 // an instance type. 1951 if (flags & LIR_OpArrayCopy::type_check) { 1952 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 1953 __ load_klass(tmp, dst); 1954 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 1955 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value); 1956 __ bge(CCR0, slow); 1957 } 1958 1959 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 1960 __ load_klass(tmp, src); 1961 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 1962 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value); 1963 __ bge(CCR0, slow); 1964 } 1965 } 1966 1967 // Higher 32bits must be null. 1968 __ extsw(length, length); 1969 1970 __ extsw(src_pos, src_pos); 1971 if (flags & LIR_OpArrayCopy::src_range_check) { 1972 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src); 1973 __ add(tmp, length, src_pos); 1974 __ cmpld(CCR0, tmp2, tmp); 1975 __ ble(CCR0, slow); 1976 } 1977 1978 __ extsw(dst_pos, dst_pos); 1979 if (flags & LIR_OpArrayCopy::dst_range_check) { 1980 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst); 1981 __ add(tmp, length, dst_pos); 1982 __ cmpld(CCR0, tmp2, tmp); 1983 __ ble(CCR0, slow); 1984 } 1985 1986 int shift = shift_amount(basic_type); 1987 1988 if (!(flags & LIR_OpArrayCopy::type_check)) { 1989 __ b(cont); 1990 } else { 1991 // We don't know the array types are compatible. 1992 if (basic_type != T_OBJECT) { 1993 // Simple test for basic type arrays. 1994 if (UseCompressedClassPointers) { 1995 // We don't need decode because we just need to compare. 1996 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src); 1997 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst); 1998 __ cmpw(CCR0, tmp, tmp2); 1999 } else { 2000 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src); 2001 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2002 __ cmpd(CCR0, tmp, tmp2); 2003 } 2004 __ beq(CCR0, cont); 2005 } else { 2006 // For object arrays, if src is a sub class of dst then we can 2007 // safely do the copy. 2008 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2009 2010 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf 2011 assert_different_registers(tmp, tmp2, sub_klass, super_klass); 2012 2013 __ load_klass(sub_klass, src); 2014 __ load_klass(super_klass, dst); 2015 2016 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2, 2017 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL); 2018 2019 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2020 //__ load_const_optimized(tmp, slow_stc, tmp2); 2021 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false); 2022 __ mtctr(tmp); 2023 __ bctrl(); // sets CR0 2024 __ beq(CCR0, cont); 2025 2026 if (copyfunc_addr != NULL) { // Use stub if available. 2027 __ bind(copyfunc); 2028 // Src is not a sub class of dst so we have to do a 2029 // per-element check. 2030 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2031 if ((flags & mask) != mask) { 2032 assert(flags & mask, "one of the two should be known to be an object array"); 2033 2034 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2035 __ load_klass(tmp, src); 2036 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2037 __ load_klass(tmp, dst); 2038 } 2039 2040 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp); 2041 2042 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2043 __ load_const_optimized(tmp, objArray_lh); 2044 __ cmpw(CCR0, tmp, tmp2); 2045 __ bne(CCR0, slow); 2046 } 2047 2048 Register src_ptr = R3_ARG1; 2049 Register dst_ptr = R4_ARG2; 2050 Register len = R5_ARG3; 2051 Register chk_off = R6_ARG4; 2052 Register super_k = R7_ARG5; 2053 2054 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type)); 2055 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type)); 2056 if (shift == 0) { 2057 __ add(src_ptr, src_pos, src_ptr); 2058 __ add(dst_ptr, dst_pos, dst_ptr); 2059 } else { 2060 __ sldi(tmp, src_pos, shift); 2061 __ sldi(tmp2, dst_pos, shift); 2062 __ add(src_ptr, tmp, src_ptr); 2063 __ add(dst_ptr, tmp2, dst_ptr); 2064 } 2065 2066 __ load_klass(tmp, dst); 2067 __ mr(len, length); 2068 2069 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); 2070 __ ld(super_k, ek_offset, tmp); 2071 2072 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2073 __ lwz(chk_off, sco_offset, super_k); 2074 2075 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0); 2076 2077 #ifndef PRODUCT 2078 if (PrintC1Statistics) { 2079 Label failed; 2080 __ cmpwi(CCR0, R3_RET, 0); 2081 __ bne(CCR0, failed); 2082 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt; 2083 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2084 __ lwz(R11_scratch1, simm16_offs, tmp); 2085 __ addi(R11_scratch1, R11_scratch1, 1); 2086 __ stw(R11_scratch1, simm16_offs, tmp); 2087 __ bind(failed); 2088 } 2089 #endif 2090 2091 __ nand(tmp, R3_RET, R3_RET); 2092 __ cmpwi(CCR0, R3_RET, 0); 2093 __ beq(CCR0, *stub->continuation()); 2094 2095 #ifndef PRODUCT 2096 if (PrintC1Statistics) { 2097 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt; 2098 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2099 __ lwz(R11_scratch1, simm16_offs, tmp); 2100 __ addi(R11_scratch1, R11_scratch1, 1); 2101 __ stw(R11_scratch1, simm16_offs, tmp); 2102 } 2103 #endif 2104 2105 __ subf(length, tmp, length); 2106 __ add(src_pos, tmp, src_pos); 2107 __ add(dst_pos, tmp, dst_pos); 2108 } 2109 } 2110 } 2111 __ bind(slow); 2112 __ b(*stub->entry()); 2113 __ bind(cont); 2114 2115 #ifdef ASSERT 2116 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2117 // Sanity check the known type with the incoming class. For the 2118 // primitive case the types must match exactly with src.klass and 2119 // dst.klass each exactly matching the default type. For the 2120 // object array case, if no type check is needed then either the 2121 // dst type is exactly the expected type and the src type is a 2122 // subtype which we can't check or src is the same array as dst 2123 // but not necessarily exactly of type default_type. 2124 Label known_ok, halt; 2125 metadata2reg(op->expected_type()->constant_encoding(), tmp); 2126 if (UseCompressedClassPointers) { 2127 // Tmp holds the default type. It currently comes uncompressed after the 2128 // load of a constant, so encode it. 2129 __ encode_klass_not_null(tmp); 2130 // Load the raw value of the dst klass, since we will be comparing 2131 // uncompressed values directly. 2132 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2133 __ cmpw(CCR0, tmp, tmp2); 2134 if (basic_type != T_OBJECT) { 2135 __ bne(CCR0, halt); 2136 // Load the raw value of the src klass. 2137 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src); 2138 __ cmpw(CCR0, tmp, tmp2); 2139 __ beq(CCR0, known_ok); 2140 } else { 2141 __ beq(CCR0, known_ok); 2142 __ cmpw(CCR0, src, dst); 2143 __ beq(CCR0, known_ok); 2144 } 2145 } else { 2146 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst); 2147 __ cmpd(CCR0, tmp, tmp2); 2148 if (basic_type != T_OBJECT) { 2149 __ bne(CCR0, halt); 2150 // Load the raw value of the src klass. 2151 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src); 2152 __ cmpd(CCR0, tmp, tmp2); 2153 __ beq(CCR0, known_ok); 2154 } else { 2155 __ beq(CCR0, known_ok); 2156 __ cmpd(CCR0, src, dst); 2157 __ beq(CCR0, known_ok); 2158 } 2159 } 2160 __ bind(halt); 2161 __ stop("incorrect type information in arraycopy"); 2162 __ bind(known_ok); 2163 } 2164 #endif 2165 2166 #ifndef PRODUCT 2167 if (PrintC1Statistics) { 2168 address counter = Runtime1::arraycopy_count_address(basic_type); 2169 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true); 2170 __ lwz(R11_scratch1, simm16_offs, tmp); 2171 __ addi(R11_scratch1, R11_scratch1, 1); 2172 __ stw(R11_scratch1, simm16_offs, tmp); 2173 } 2174 #endif 2175 2176 Register src_ptr = R3_ARG1; 2177 Register dst_ptr = R4_ARG2; 2178 Register len = R5_ARG3; 2179 2180 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type)); 2181 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type)); 2182 if (shift == 0) { 2183 __ add(src_ptr, src_pos, src_ptr); 2184 __ add(dst_ptr, dst_pos, dst_ptr); 2185 } else { 2186 __ sldi(tmp, src_pos, shift); 2187 __ sldi(tmp2, dst_pos, shift); 2188 __ add(src_ptr, tmp, src_ptr); 2189 __ add(dst_ptr, tmp2, dst_ptr); 2190 } 2191 2192 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2193 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2194 const char *name; 2195 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2196 2197 // Arraycopy stubs takes a length in number of elements, so don't scale it. 2198 __ mr(len, length); 2199 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0); 2200 2201 __ bind(*stub->continuation()); 2202 } 2203 2204 2205 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2206 if (dest->is_single_cpu()) { 2207 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5); 2208 #ifdef _LP64 2209 if (left->type() == T_OBJECT) { 2210 switch (code) { 2211 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break; 2212 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break; 2213 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break; 2214 default: ShouldNotReachHere(); 2215 } 2216 } else 2217 #endif 2218 switch (code) { 2219 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2220 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2221 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break; 2222 default: ShouldNotReachHere(); 2223 } 2224 } else { 2225 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6); 2226 switch (code) { 2227 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2228 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2229 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break; 2230 default: ShouldNotReachHere(); 2231 } 2232 } 2233 } 2234 2235 2236 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2237 #ifdef _LP64 2238 if (left->type() == T_OBJECT) { 2239 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t). 2240 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); } 2241 else { 2242 switch (code) { 2243 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break; 2244 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break; 2245 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break; 2246 default: ShouldNotReachHere(); 2247 } 2248 } 2249 return; 2250 } 2251 #endif 2252 2253 if (dest->is_single_cpu()) { 2254 count = count & 0x1F; // Java spec 2255 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); } 2256 else { 2257 switch (code) { 2258 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break; 2259 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break; 2260 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break; 2261 default: ShouldNotReachHere(); 2262 } 2263 } 2264 } else if (dest->is_double_cpu()) { 2265 count = count & 63; // Java spec 2266 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); } 2267 else { 2268 switch (code) { 2269 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2270 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2271 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break; 2272 default: ShouldNotReachHere(); 2273 } 2274 } 2275 } else { 2276 ShouldNotReachHere(); 2277 } 2278 } 2279 2280 2281 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2282 if (op->init_check()) { 2283 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2284 explicit_null_check(op->klass()->as_register(), op->stub()->info()); 2285 } else { 2286 add_debug_info_for_null_check_here(op->stub()->info()); 2287 } 2288 __ lbz(op->tmp1()->as_register(), 2289 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register()); 2290 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized); 2291 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry()); 2292 } 2293 __ allocate_object(op->obj()->as_register(), 2294 op->tmp1()->as_register(), 2295 op->tmp2()->as_register(), 2296 op->tmp3()->as_register(), 2297 op->header_size(), 2298 op->object_size(), 2299 op->klass()->as_register(), 2300 *op->stub()->entry()); 2301 2302 __ bind(*op->stub()->continuation()); 2303 __ verify_oop(op->obj()->as_register()); 2304 } 2305 2306 2307 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2308 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); ) 2309 if (UseSlowPath || 2310 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2311 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2312 __ b(*op->stub()->entry()); 2313 } else { 2314 __ allocate_array(op->obj()->as_register(), 2315 op->len()->as_register(), 2316 op->tmp1()->as_register(), 2317 op->tmp2()->as_register(), 2318 op->tmp3()->as_register(), 2319 arrayOopDesc::header_size(op->type()), 2320 type2aelembytes(op->type()), 2321 op->klass()->as_register(), 2322 *op->stub()->entry()); 2323 } 2324 __ bind(*op->stub()->continuation()); 2325 } 2326 2327 2328 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2329 ciMethodData *md, ciProfileData *data, 2330 Register recv, Register tmp1, Label* update_done) { 2331 uint i; 2332 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2333 Label next_test; 2334 // See if the receiver is receiver[n]. 2335 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2336 __ verify_klass_ptr(tmp1); 2337 __ cmpd(CCR0, recv, tmp1); 2338 __ bne(CCR0, next_test); 2339 2340 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2341 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2342 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2343 __ b(*update_done); 2344 2345 __ bind(next_test); 2346 } 2347 2348 // Didn't find receiver; find next empty slot and fill it in. 2349 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2350 Label next_test; 2351 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2352 __ cmpdi(CCR0, tmp1, 0); 2353 __ bne(CCR0, next_test); 2354 __ li(tmp1, DataLayout::counter_increment); 2355 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo); 2356 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2357 __ b(*update_done); 2358 2359 __ bind(next_test); 2360 } 2361 } 2362 2363 2364 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2365 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2366 md = method->method_data_or_null(); 2367 assert(md != NULL, "Sanity"); 2368 data = md->bci_to_data(bci); 2369 assert(data != NULL, "need data for checkcast"); 2370 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2371 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2372 // The offset is large so bias the mdo by the base of the slot so 2373 // that the ld can use simm16s to reference the slots of the data. 2374 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2375 } 2376 } 2377 2378 2379 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2380 Register obj = op->object()->as_register(); 2381 Register k_RInfo = op->tmp1()->as_register(); 2382 Register klass_RInfo = op->tmp2()->as_register(); 2383 Register Rtmp1 = op->tmp3()->as_register(); 2384 Register dst = op->result_opr()->as_register(); 2385 ciKlass* k = op->klass(); 2386 bool should_profile = op->should_profile(); 2387 bool move_obj_to_dst = (op->code() == lir_checkcast); 2388 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps. 2389 bool reg_conflict = (obj == k_RInfo || obj == klass_RInfo || obj == Rtmp1); 2390 bool restore_obj = move_obj_to_dst && reg_conflict; 2391 2392 __ cmpdi(CCR0, obj, 0); 2393 if (move_obj_to_dst || reg_conflict) { 2394 __ mr_if_needed(dst, obj); 2395 if (reg_conflict) { obj = dst; } 2396 } 2397 2398 ciMethodData* md; 2399 ciProfileData* data; 2400 int mdo_offset_bias = 0; 2401 if (should_profile) { 2402 ciMethod* method = op->profiled_method(); 2403 assert(method != NULL, "Should have method"); 2404 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2405 2406 Register mdo = k_RInfo; 2407 Register data_val = Rtmp1; 2408 Label not_null; 2409 __ bne(CCR0, not_null); 2410 metadata2reg(md->constant_encoding(), mdo); 2411 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2412 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2413 __ ori(data_val, data_val, BitData::null_seen_byte_constant()); 2414 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2415 __ b(*obj_is_null); 2416 __ bind(not_null); 2417 } else { 2418 __ beq(CCR0, *obj_is_null); 2419 } 2420 2421 // get object class 2422 __ load_klass(klass_RInfo, obj); 2423 2424 if (k->is_loaded()) { 2425 metadata2reg(k->constant_encoding(), k_RInfo); 2426 } else { 2427 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2428 } 2429 2430 Label profile_cast_failure, failure_restore_obj, profile_cast_success; 2431 Label *failure_target = should_profile ? &profile_cast_failure : failure; 2432 Label *success_target = should_profile ? &profile_cast_success : success; 2433 2434 if (op->fast_check()) { 2435 assert_different_registers(klass_RInfo, k_RInfo); 2436 __ cmpd(CCR0, k_RInfo, klass_RInfo); 2437 if (should_profile) { 2438 __ bne(CCR0, *failure_target); 2439 // Fall through to success case. 2440 } else { 2441 __ beq(CCR0, *success); 2442 // Fall through to failure case. 2443 } 2444 } else { 2445 bool need_slow_path = true; 2446 if (k->is_loaded()) { 2447 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) { 2448 need_slow_path = false; 2449 } 2450 // Perform the fast part of the checking logic. 2451 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL), 2452 failure_target, NULL, RegisterOrConstant(k->super_check_offset())); 2453 } else { 2454 // Perform the fast part of the checking logic. 2455 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target); 2456 } 2457 if (!need_slow_path) { 2458 if (!should_profile) { __ b(*success); } 2459 } else { 2460 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2461 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2462 //__ load_const_optimized(Rtmp1, entry, R0); 2463 __ calculate_address_from_global_toc(Rtmp1, entry, true, true, false); 2464 __ mtctr(Rtmp1); 2465 __ bctrl(); // sets CR0 2466 if (should_profile) { 2467 __ bne(CCR0, *failure_target); 2468 // Fall through to success case. 2469 } else { 2470 __ beq(CCR0, *success); 2471 // Fall through to failure case. 2472 } 2473 } 2474 } 2475 2476 if (should_profile) { 2477 Register mdo = k_RInfo, recv = klass_RInfo; 2478 assert_different_registers(mdo, recv, Rtmp1); 2479 __ bind(profile_cast_success); 2480 metadata2reg(md->constant_encoding(), mdo); 2481 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2482 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success); 2483 __ b(*success); 2484 2485 // Cast failure case. 2486 __ bind(profile_cast_failure); 2487 metadata2reg(md->constant_encoding(), mdo); 2488 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2489 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2490 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment); 2491 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2492 } 2493 2494 __ bind(*failure); 2495 2496 if (restore_obj) { 2497 __ mr(op->object()->as_register(), dst); 2498 // Fall through to failure case. 2499 } 2500 } 2501 2502 2503 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2504 LIR_Code code = op->code(); 2505 if (code == lir_store_check) { 2506 Register value = op->object()->as_register(); 2507 Register array = op->array()->as_register(); 2508 Register k_RInfo = op->tmp1()->as_register(); 2509 Register klass_RInfo = op->tmp2()->as_register(); 2510 Register Rtmp1 = op->tmp3()->as_register(); 2511 bool should_profile = op->should_profile(); 2512 2513 __ verify_oop(value); 2514 CodeStub* stub = op->stub(); 2515 // Check if it needs to be profiled. 2516 ciMethodData* md; 2517 ciProfileData* data; 2518 int mdo_offset_bias = 0; 2519 if (should_profile) { 2520 ciMethod* method = op->profiled_method(); 2521 assert(method != NULL, "Should have method"); 2522 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2523 } 2524 Label profile_cast_success, failure, done; 2525 Label *success_target = should_profile ? &profile_cast_success : &done; 2526 2527 __ cmpdi(CCR0, value, 0); 2528 if (should_profile) { 2529 Label not_null; 2530 __ bne(CCR0, not_null); 2531 Register mdo = k_RInfo; 2532 Register data_val = Rtmp1; 2533 metadata2reg(md->constant_encoding(), mdo); 2534 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2535 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2536 __ ori(data_val, data_val, BitData::null_seen_byte_constant()); 2537 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo); 2538 __ b(done); 2539 __ bind(not_null); 2540 } else { 2541 __ beq(CCR0, done); 2542 } 2543 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2544 explicit_null_check(array, op->info_for_exception()); 2545 } else { 2546 add_debug_info_for_null_check_here(op->info_for_exception()); 2547 } 2548 __ load_klass(k_RInfo, array); 2549 __ load_klass(klass_RInfo, value); 2550 2551 // Get instance klass. 2552 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo); 2553 // Perform the fast part of the checking logic. 2554 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL); 2555 2556 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2557 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id); 2558 //__ load_const_optimized(R0, slow_path); 2559 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path)); 2560 __ mtctr(R0); 2561 __ bctrl(); // sets CR0 2562 if (!should_profile) { 2563 __ beq(CCR0, done); 2564 __ bind(failure); 2565 } else { 2566 __ bne(CCR0, failure); 2567 // Fall through to the success case. 2568 2569 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2570 assert_different_registers(value, mdo, recv, tmp1); 2571 __ bind(profile_cast_success); 2572 metadata2reg(md->constant_encoding(), mdo); 2573 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2574 __ load_klass(recv, value); 2575 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2576 __ b(done); 2577 2578 // Cast failure case. 2579 __ bind(failure); 2580 metadata2reg(md->constant_encoding(), mdo); 2581 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2582 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2583 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2584 __ addi(tmp1, tmp1, -DataLayout::counter_increment); 2585 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2586 } 2587 __ b(*stub->entry()); 2588 __ bind(done); 2589 2590 } else if (code == lir_checkcast) { 2591 Label success, failure; 2592 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success); // Moves obj to dst. 2593 __ b(*op->stub()->entry()); 2594 __ align(32, 12); 2595 __ bind(success); 2596 } else if (code == lir_instanceof) { 2597 Register dst = op->result_opr()->as_register(); 2598 Label success, failure, done; 2599 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure); 2600 __ li(dst, 0); 2601 __ b(done); 2602 __ align(32, 12); 2603 __ bind(success); 2604 __ li(dst, 1); 2605 __ bind(done); 2606 } else { 2607 ShouldNotReachHere(); 2608 } 2609 } 2610 2611 2612 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2613 Register addr = op->addr()->as_pointer_register(); 2614 Register cmp_value = noreg, new_value = noreg; 2615 bool is_64bit = false; 2616 2617 if (op->code() == lir_cas_long) { 2618 cmp_value = op->cmp_value()->as_register_lo(); 2619 new_value = op->new_value()->as_register_lo(); 2620 is_64bit = true; 2621 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2622 cmp_value = op->cmp_value()->as_register(); 2623 new_value = op->new_value()->as_register(); 2624 if (op->code() == lir_cas_obj) { 2625 if (UseCompressedOops) { 2626 Register t1 = op->tmp1()->as_register(); 2627 Register t2 = op->tmp2()->as_register(); 2628 cmp_value = __ encode_heap_oop(t1, cmp_value); 2629 new_value = __ encode_heap_oop(t2, new_value); 2630 } else { 2631 is_64bit = true; 2632 } 2633 } 2634 } else { 2635 Unimplemented(); 2636 } 2637 2638 if (is_64bit) { 2639 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2640 MacroAssembler::MemBarNone, 2641 MacroAssembler::cmpxchgx_hint_atomic_update(), 2642 noreg, NULL, /*check without ldarx first*/true); 2643 } else { 2644 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr, 2645 MacroAssembler::MemBarNone, 2646 MacroAssembler::cmpxchgx_hint_atomic_update(), 2647 noreg, /*check without ldarx first*/true); 2648 } 2649 2650 if (support_IRIW_for_not_multiple_copy_atomic_cpu) { 2651 __ isync(); 2652 } else { 2653 __ sync(); 2654 } 2655 } 2656 2657 2658 void LIR_Assembler::set_24bit_FPU() { 2659 Unimplemented(); 2660 } 2661 2662 void LIR_Assembler::reset_FPU() { 2663 Unimplemented(); 2664 } 2665 2666 2667 void LIR_Assembler::breakpoint() { 2668 __ illtrap(); 2669 } 2670 2671 2672 void LIR_Assembler::push(LIR_Opr opr) { 2673 Unimplemented(); 2674 } 2675 2676 void LIR_Assembler::pop(LIR_Opr opr) { 2677 Unimplemented(); 2678 } 2679 2680 2681 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2682 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2683 Register dst = dst_opr->as_register(); 2684 Register reg = mon_addr.base(); 2685 int offset = mon_addr.disp(); 2686 // Compute pointer to BasicLock. 2687 __ add_const_optimized(dst, reg, offset); 2688 } 2689 2690 2691 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2692 Register obj = op->obj_opr()->as_register(); 2693 Register hdr = op->hdr_opr()->as_register(); 2694 Register lock = op->lock_opr()->as_register(); 2695 2696 // Obj may not be an oop. 2697 if (op->code() == lir_lock) { 2698 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2699 if (UseFastLocking) { 2700 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2701 // Add debug info for NullPointerException only if one is possible. 2702 if (op->info() != NULL) { 2703 if (!os::zero_page_read_protected() || !ImplicitNullChecks) { 2704 explicit_null_check(obj, op->info()); 2705 } else { 2706 add_debug_info_for_null_check_here(op->info()); 2707 } 2708 } 2709 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2710 } else { 2711 // always do slow locking 2712 // note: The slow locking code could be inlined here, however if we use 2713 // slow locking, speed doesn't matter anyway and this solution is 2714 // simpler and requires less duplicated code - additionally, the 2715 // slow locking code is the same in either case which simplifies 2716 // debugging. 2717 __ b(*op->stub()->entry()); 2718 } 2719 } else { 2720 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2721 if (UseFastLocking) { 2722 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2723 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2724 } else { 2725 // always do slow unlocking 2726 // note: The slow unlocking code could be inlined here, however if we use 2727 // slow unlocking, speed doesn't matter anyway and this solution is 2728 // simpler and requires less duplicated code - additionally, the 2729 // slow unlocking code is the same in either case which simplifies 2730 // debugging. 2731 __ b(*op->stub()->entry()); 2732 } 2733 } 2734 __ bind(*op->stub()->continuation()); 2735 } 2736 2737 2738 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2739 ciMethod* method = op->profiled_method(); 2740 int bci = op->profiled_bci(); 2741 ciMethod* callee = op->profiled_callee(); 2742 2743 // Update counter for all call types. 2744 ciMethodData* md = method->method_data_or_null(); 2745 assert(md != NULL, "Sanity"); 2746 ciProfileData* data = md->bci_to_data(bci); 2747 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2748 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2749 Register mdo = op->mdo()->as_register(); 2750 #ifdef _LP64 2751 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2752 Register tmp1 = op->tmp1()->as_register_lo(); 2753 #else 2754 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); 2755 Register tmp1 = op->tmp1()->as_register(); 2756 #endif 2757 metadata2reg(md->constant_encoding(), mdo); 2758 int mdo_offset_bias = 0; 2759 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2760 data->size_in_bytes())) { 2761 // The offset is large so bias the mdo by the base of the slot so 2762 // that the ld can use simm16s to reference the slots of the data. 2763 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2764 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0); 2765 } 2766 2767 // Perform additional virtual call profiling for invokevirtual and 2768 // invokeinterface bytecodes 2769 if (op->should_profile_receiver_type()) { 2770 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2771 Register recv = op->recv()->as_register(); 2772 assert_different_registers(mdo, tmp1, recv); 2773 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2774 ciKlass* known_klass = op->known_holder(); 2775 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2776 // We know the type that will be seen at this call site; we can 2777 // statically update the MethodData* rather than needing to do 2778 // dynamic tests on the receiver type. 2779 2780 // NOTE: we should probably put a lock around this search to 2781 // avoid collisions by concurrent compilations. 2782 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2783 uint i; 2784 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2785 ciKlass* receiver = vc_data->receiver(i); 2786 if (known_klass->equals(receiver)) { 2787 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2788 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2789 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2790 return; 2791 } 2792 } 2793 2794 // Receiver type not found in profile data; select an empty slot. 2795 2796 // Note that this is less efficient than it should be because it 2797 // always does a write to the receiver part of the 2798 // VirtualCallData rather than just the first time. 2799 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2800 ciKlass* receiver = vc_data->receiver(i); 2801 if (receiver == NULL) { 2802 metadata2reg(known_klass->constant_encoding(), tmp1); 2803 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo); 2804 2805 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2806 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2807 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo); 2808 return; 2809 } 2810 } 2811 } else { 2812 __ load_klass(recv, recv); 2813 Label update_done; 2814 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 2815 // Receiver did not match any saved receiver and there is no empty row for it. 2816 // Increment total counter to indicate polymorphic case. 2817 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2818 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2819 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2820 2821 __ bind(update_done); 2822 } 2823 } else { 2824 // Static call 2825 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2826 __ addi(tmp1, tmp1, DataLayout::counter_increment); 2827 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo); 2828 } 2829 } 2830 2831 2832 void LIR_Assembler::align_backward_branch_target() { 2833 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary. 2834 } 2835 2836 2837 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2838 Unimplemented(); 2839 } 2840 2841 2842 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 2843 assert(left->is_register(), "can only handle registers"); 2844 2845 if (left->is_single_cpu()) { 2846 __ neg(dest->as_register(), left->as_register()); 2847 } else if (left->is_single_fpu()) { 2848 __ fneg(dest->as_float_reg(), left->as_float_reg()); 2849 } else if (left->is_double_fpu()) { 2850 __ fneg(dest->as_double_reg(), left->as_double_reg()); 2851 } else { 2852 assert (left->is_double_cpu(), "Must be a long"); 2853 __ neg(dest->as_register_lo(), left->as_register_lo()); 2854 } 2855 } 2856 2857 2858 void LIR_Assembler::fxch(int i) { 2859 Unimplemented(); 2860 } 2861 2862 void LIR_Assembler::fld(int i) { 2863 Unimplemented(); 2864 } 2865 2866 void LIR_Assembler::ffree(int i) { 2867 Unimplemented(); 2868 } 2869 2870 2871 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 2872 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2873 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor). 2874 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) || 2875 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) { 2876 //__ load_const_optimized(R0, dest); 2877 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest)); 2878 __ mtctr(R0); 2879 __ bctrl(); 2880 assert(info != NULL, "sanity"); 2881 add_call_info_here(info); 2882 return; 2883 } 2884 2885 __ call_c_with_frame_resize(dest, /*no resizing*/ 0); 2886 if (info != NULL) { 2887 add_call_info_here(info); 2888 } 2889 } 2890 2891 2892 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2893 ShouldNotReachHere(); // Not needed on _LP64. 2894 } 2895 2896 void LIR_Assembler::membar() { 2897 __ fence(); 2898 } 2899 2900 void LIR_Assembler::membar_acquire() { 2901 __ acquire(); 2902 } 2903 2904 void LIR_Assembler::membar_release() { 2905 __ release(); 2906 } 2907 2908 void LIR_Assembler::membar_loadload() { 2909 __ membar(Assembler::LoadLoad); 2910 } 2911 2912 void LIR_Assembler::membar_storestore() { 2913 __ membar(Assembler::StoreStore); 2914 } 2915 2916 void LIR_Assembler::membar_loadstore() { 2917 __ membar(Assembler::LoadStore); 2918 } 2919 2920 void LIR_Assembler::membar_storeload() { 2921 __ membar(Assembler::StoreLoad); 2922 } 2923 2924 void LIR_Assembler::on_spin_wait() { 2925 Unimplemented(); 2926 } 2927 2928 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 2929 LIR_Address* addr = addr_opr->as_address_ptr(); 2930 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform"); 2931 if (addr->index()->is_illegal()) { 2932 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp()); 2933 } else { 2934 assert(addr->disp() == 0, "can't have both: index and disp"); 2935 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register()); 2936 } 2937 } 2938 2939 2940 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2941 ShouldNotReachHere(); 2942 } 2943 2944 2945 #ifdef ASSERT 2946 // Emit run-time assertion. 2947 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2948 Unimplemented(); 2949 } 2950 #endif 2951 2952 2953 void LIR_Assembler::peephole(LIR_List* lir) { 2954 // Optimize instruction pairs before emitting. 2955 LIR_OpList* inst = lir->instructions_list(); 2956 for (int i = 1; i < inst->length(); i++) { 2957 LIR_Op* op = inst->at(i); 2958 2959 // 2 register-register-moves 2960 if (op->code() == lir_move) { 2961 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(), 2962 res2 = ((LIR_Op1*)op)->result_opr(); 2963 if (in2->is_register() && res2->is_register()) { 2964 LIR_Op* prev = inst->at(i - 1); 2965 if (prev && prev->code() == lir_move) { 2966 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(), 2967 res1 = ((LIR_Op1*)prev)->result_opr(); 2968 if (in1->is_same_register(res2) && in2->is_same_register(res1)) { 2969 inst->remove_at(i); 2970 } 2971 } 2972 } 2973 } 2974 2975 } 2976 return; 2977 } 2978 2979 2980 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 2981 const Register Rptr = src->as_pointer_register(), 2982 Rtmp = tmp->as_register(); 2983 Register Rco = noreg; 2984 if (UseCompressedOops && data->is_oop()) { 2985 Rco = __ encode_heap_oop(Rtmp, data->as_register()); 2986 } 2987 2988 Label Lretry; 2989 __ bind(Lretry); 2990 2991 if (data->type() == T_INT) { 2992 const Register Rold = dest->as_register(), 2993 Rsrc = data->as_register(); 2994 assert_different_registers(Rptr, Rtmp, Rold, Rsrc); 2995 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 2996 if (code == lir_xadd) { 2997 __ add(Rtmp, Rsrc, Rold); 2998 __ stwcx_(Rtmp, Rptr); 2999 } else { 3000 __ stwcx_(Rsrc, Rptr); 3001 } 3002 } else if (data->is_oop()) { 3003 assert(code == lir_xchg, "xadd for oops"); 3004 const Register Rold = dest->as_register(); 3005 if (UseCompressedOops) { 3006 assert_different_registers(Rptr, Rold, Rco); 3007 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3008 __ stwcx_(Rco, Rptr); 3009 } else { 3010 const Register Robj = data->as_register(); 3011 assert_different_registers(Rptr, Rold, Robj); 3012 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3013 __ stdcx_(Robj, Rptr); 3014 } 3015 } else if (data->type() == T_LONG) { 3016 const Register Rold = dest->as_register_lo(), 3017 Rsrc = data->as_register_lo(); 3018 assert_different_registers(Rptr, Rtmp, Rold, Rsrc); 3019 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3020 if (code == lir_xadd) { 3021 __ add(Rtmp, Rsrc, Rold); 3022 __ stdcx_(Rtmp, Rptr); 3023 } else { 3024 __ stdcx_(Rsrc, Rptr); 3025 } 3026 } else { 3027 ShouldNotReachHere(); 3028 } 3029 3030 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3031 __ bne_predict_not_taken(CCR0, Lretry); 3032 } else { 3033 __ bne( CCR0, Lretry); 3034 } 3035 3036 if (UseCompressedOops && data->is_oop()) { 3037 __ decode_heap_oop(dest->as_register()); 3038 } 3039 } 3040 3041 3042 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 3043 Register obj = op->obj()->as_register(); 3044 Register tmp = op->tmp()->as_pointer_register(); 3045 LIR_Address* mdo_addr = op->mdp()->as_address_ptr(); 3046 ciKlass* exact_klass = op->exact_klass(); 3047 intptr_t current_klass = op->current_klass(); 3048 bool not_null = op->not_null(); 3049 bool no_conflict = op->no_conflict(); 3050 3051 Label Lupdate, Ldo_update, Ldone; 3052 3053 bool do_null = !not_null; 3054 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 3055 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 3056 3057 assert(do_null || do_update, "why are we here?"); 3058 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 3059 3060 __ verify_oop(obj); 3061 3062 if (do_null) { 3063 if (!TypeEntries::was_null_seen(current_klass)) { 3064 __ cmpdi(CCR0, obj, 0); 3065 __ bne(CCR0, Lupdate); 3066 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3067 __ ori(R0, R0, TypeEntries::null_seen); 3068 if (do_update) { 3069 __ b(Ldo_update); 3070 } else { 3071 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3072 } 3073 } else { 3074 if (do_update) { 3075 __ cmpdi(CCR0, obj, 0); 3076 __ beq(CCR0, Ldone); 3077 } 3078 } 3079 #ifdef ASSERT 3080 } else { 3081 __ cmpdi(CCR0, obj, 0); 3082 __ bne(CCR0, Lupdate); 3083 __ stop("unexpect null obj", 0x9652); 3084 #endif 3085 } 3086 3087 __ bind(Lupdate); 3088 if (do_update) { 3089 Label Lnext; 3090 const Register klass = R29_TOC; // kill and reload 3091 bool klass_reg_used = false; 3092 #ifdef ASSERT 3093 if (exact_klass != NULL) { 3094 Label ok; 3095 klass_reg_used = true; 3096 __ load_klass(klass, obj); 3097 metadata2reg(exact_klass->constant_encoding(), R0); 3098 __ cmpd(CCR0, klass, R0); 3099 __ beq(CCR0, ok); 3100 __ stop("exact klass and actual klass differ", 0x8564); 3101 __ bind(ok); 3102 } 3103 #endif 3104 3105 if (!no_conflict) { 3106 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3107 klass_reg_used = true; 3108 if (exact_klass != NULL) { 3109 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3110 metadata2reg(exact_klass->constant_encoding(), klass); 3111 } else { 3112 __ load_klass(klass, obj); 3113 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj 3114 } 3115 3116 // Like InterpreterMacroAssembler::profile_obj_type 3117 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask)); 3118 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask); 3119 __ cmpd(CCR1, R0, klass); 3120 // Klass seen before, nothing to do (regardless of unknown bit). 3121 //beq(CCR1, do_nothing); 3122 3123 __ andi_(R0, klass, TypeEntries::type_unknown); 3124 // Already unknown. Nothing to do anymore. 3125 //bne(CCR0, do_nothing); 3126 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne 3127 __ beq(CCR0, Lnext); 3128 3129 if (TypeEntries::is_type_none(current_klass)) { 3130 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask)); 3131 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3132 __ beq(CCR0, Ldo_update); // First time here. Set profile type. 3133 } 3134 3135 } else { 3136 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3137 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3138 3139 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3140 __ andi_(R0, tmp, TypeEntries::type_unknown); 3141 // Already unknown. Nothing to do anymore. 3142 __ bne(CCR0, Lnext); 3143 } 3144 3145 // Different than before. Cannot keep accurate profile. 3146 __ ori(R0, tmp, TypeEntries::type_unknown); 3147 } else { 3148 // There's a single possible klass at this profile point 3149 assert(exact_klass != NULL, "should be"); 3150 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3151 3152 if (TypeEntries::is_type_none(current_klass)) { 3153 klass_reg_used = true; 3154 metadata2reg(exact_klass->constant_encoding(), klass); 3155 3156 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask)); 3157 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask); 3158 __ cmpd(CCR1, R0, klass); 3159 // Klass seen before, nothing to do (regardless of unknown bit). 3160 __ beq(CCR1, Lnext); 3161 #ifdef ASSERT 3162 { 3163 Label ok; 3164 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask)); 3165 __ beq(CCR0, ok); // First time here. 3166 3167 __ stop("unexpected profiling mismatch", 0x7865); 3168 __ bind(ok); 3169 } 3170 #endif 3171 // First time here. Set profile type. 3172 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3173 } else { 3174 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3175 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3176 3177 // Already unknown. Nothing to do anymore. 3178 __ andi_(R0, tmp, TypeEntries::type_unknown); 3179 __ bne(CCR0, Lnext); 3180 3181 // Different than before. Cannot keep accurate profile. 3182 __ ori(R0, tmp, TypeEntries::type_unknown); 3183 } 3184 } 3185 3186 __ bind(Ldo_update); 3187 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); 3188 3189 __ bind(Lnext); 3190 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit 3191 } 3192 __ bind(Ldone); 3193 } 3194 3195 3196 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3197 assert(op->crc()->is_single_cpu(), "crc must be register"); 3198 assert(op->val()->is_single_cpu(), "byte value must be register"); 3199 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3200 Register crc = op->crc()->as_register(); 3201 Register val = op->val()->as_register(); 3202 Register res = op->result_opr()->as_register(); 3203 3204 assert_different_registers(val, crc, res); 3205 3206 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0); 3207 __ kernel_crc32_singleByteReg(crc, val, res, true); 3208 __ mr(res, crc); 3209 } 3210 3211 #undef __