1 /*
2 * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "nativeInst_s390.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/frame.inline.hpp"
40 #include "runtime/safepointMechanism.inline.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "vmreg_s390.inline.hpp"
43
44 #define __ _masm->
45
46 #ifndef PRODUCT
47 #undef __
48 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
49 #endif
50
51 //------------------------------------------------------------
52
53 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
54 // Not used on ZARCH_64
55 ShouldNotCallThis();
56 return false;
57 }
58
59 LIR_Opr LIR_Assembler::receiverOpr() {
60 return FrameMap::Z_R2_oop_opr;
61 }
62
63 LIR_Opr LIR_Assembler::osrBufferPointer() {
64 return FrameMap::Z_R2_opr;
65 }
66
67 int LIR_Assembler::initial_frame_size_in_bytes() const {
68 return in_bytes(frame_map()->framesize_in_bytes());
69 }
70
71 // Inline cache check: done before the frame is built.
72 // The inline cached class is in Z_inline_cache(Z_R9).
73 // We fetch the class of the receiver and compare it with the cached class.
74 // If they do not match we jump to the slow case.
75 int LIR_Assembler::check_icache() {
76 Register receiver = receiverOpr()->as_register();
77 int offset = __ offset();
78 __ inline_cache_check(receiver, Z_inline_cache);
79 return offset;
80 }
81
82 void LIR_Assembler::osr_entry() {
83 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
84 //
85 // 1. Create a new compiled activation.
86 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
87 // at the osr_bci; it is not initialized.
88 // 3. Jump to the continuation address in compiled code to resume execution.
89
90 // OSR entry point
91 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
92 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
93 ValueStack* entry_state = osr_entry->end()->state();
94 int number_of_locks = entry_state->locks_size();
95
96 // Create a frame for the compiled activation.
97 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
98
99 // OSR buffer is
100 //
101 // locals[nlocals-1..0]
102 // monitors[number_of_locks-1..0]
103 //
104 // Locals is a direct copy of the interpreter frame so in the osr buffer
105 // the first slot in the local array is the last local from the interpreter
106 // and the last slot is local[0] (receiver) from the interpreter
107 //
108 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
109 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
110 // in the interpreter frame (the method lock if a sync method)
111
112 // Initialize monitors in the compiled activation.
113 // I0: pointer to osr buffer
114 //
115 // All other registers are dead at this point and the locals will be
116 // copied into place by code emitted in the IR.
117
118 Register OSR_buf = osrBufferPointer()->as_register();
119 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
120 int monitor_offset = BytesPerWord * method()->max_locals() +
121 (2 * BytesPerWord) * (number_of_locks - 1);
122 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
123 // the OSR buffer using 2 word entries: first the lock and then
124 // the oop.
125 for (int i = 0; i < number_of_locks; i++) {
126 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
127 // Verify the interpreter's monitor has a non-null object.
128 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__);
129 // Copy the lock field into the compiled activation.
130 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
131 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
132 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
133 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
134 }
135 }
136 }
137
138 // --------------------------------------------------------------------------------------------
139
140 address LIR_Assembler::emit_call_c(address a) {
141 __ align_call_far_patchable(__ pc());
142 address call_addr = __ call_c_opt(a);
143 if (call_addr == NULL) {
144 bailout("const section overflow");
145 }
146 return call_addr;
147 }
148
149 int LIR_Assembler::emit_exception_handler() {
150 // If the last instruction is a call (typically to do a throw which
151 // is coming at the end after block reordering) the return address
152 // must still point into the code area in order to avoid assertion
153 // failures when searching for the corresponding bci. => Add a nop.
154 // (was bug 5/14/1999 - gri)
155 __ nop();
156
157 // Generate code for exception handler.
158 address handler_base = __ start_a_stub(exception_handler_size());
159 if (handler_base == NULL) {
160 // Not enough space left for the handler.
161 bailout("exception handler overflow");
162 return -1;
163 }
164
165 int offset = code_offset();
166
167 address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id);
168 address call_addr = emit_call_c(a);
169 CHECK_BAILOUT_(-1);
170 __ should_not_reach_here();
171 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
172 __ end_a_stub();
173
174 return offset;
175 }
176
177 // Emit the code to remove the frame from the stack in the exception
178 // unwind path.
179 int LIR_Assembler::emit_unwind_handler() {
180 #ifndef PRODUCT
181 if (CommentedAssembly) {
182 _masm->block_comment("Unwind handler");
183 }
184 #endif
185
186 int offset = code_offset();
187 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
188 Register Rtmp1 = Z_R11;
189 Register Rtmp2 = Z_R12;
190
191 // Fetch the exception from TLS and clear out exception related thread state.
192 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
193 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset());
194 __ z_lg(Z_EXC_OOP, exc_oop_addr);
195 __ clear_mem(exc_oop_addr, sizeof(oop));
196 __ clear_mem(exc_pc_addr, sizeof(intptr_t));
197
198 __ bind(_unwind_handler_entry);
199 __ verify_not_null_oop(Z_EXC_OOP);
200 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
201 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
202 }
203
204 // Preform needed unlocking.
205 MonitorExitStub* stub = NULL;
206 if (method()->is_synchronized()) {
207 // Runtime1::monitorexit_id expects lock address in Z_R1_scratch.
208 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
209 monitor_address(0, lock);
210 stub = new MonitorExitStub(lock, true, 0);
211 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
212 __ bind(*stub->continuation());
213 }
214
215 if (compilation()->env()->dtrace_method_probes()) {
216 ShouldNotReachHere(); // Not supported.
217 #if 0
218 __ mov(rdi, r15_thread);
219 __ mov_metadata(rsi, method()->constant_encoding());
220 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
221 #endif
222 }
223
224 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
225 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception.
226 }
227
228 // Remove the activation and dispatch to the unwind handler.
229 __ pop_frame();
230 __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP);
231
232 // Z_EXC_OOP: exception oop
233 // Z_EXC_PC: exception pc
234
235 // Dispatch to the unwind logic.
236 __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id));
237 __ z_br(Z_R5);
238
239 // Emit the slow path assembly.
240 if (stub != NULL) {
241 stub->emit_code(this);
242 }
243
244 return offset;
245 }
246
247 int LIR_Assembler::emit_deopt_handler() {
248 // If the last instruction is a call (typically to do a throw which
249 // is coming at the end after block reordering) the return address
250 // must still point into the code area in order to avoid assertion
251 // failures when searching for the corresponding bci. => Add a nop.
252 // (was bug 5/14/1999 - gri)
253 __ nop();
254
255 // Generate code for exception handler.
256 address handler_base = __ start_a_stub(deopt_handler_size());
257 if (handler_base == NULL) {
258 // Not enough space left for the handler.
259 bailout("deopt handler overflow");
260 return -1;
261 } int offset = code_offset();
262 // Size must be constant (see HandlerImpl::emit_deopt_handler).
263 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
264 __ call(Z_R1_scratch);
265 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
266 __ end_a_stub();
267
268 return offset;
269 }
270
271 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
272 if (o == NULL) {
273 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
274 } else {
275 AddressLiteral a = __ allocate_oop_address(o);
276 bool success = __ load_oop_from_toc(reg, a, reg);
277 if (!success) {
278 bailout("const section overflow");
279 }
280 }
281 }
282
283 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
284 // Allocate a new index in table to hold the object once it's been patched.
285 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
286 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
287
288 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
289 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
290 // The NULL will be dynamically patched later so the sequence to
291 // load the address literal must not be optimized.
292 __ load_const(reg, addrlit);
293
294 patching_epilog(patch, lir_patch_normal, reg, info);
295 }
296
297 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
298 bool success = __ set_metadata_constant(md, reg);
299 if (!success) {
300 bailout("const section overflow");
301 return;
302 }
303 }
304
305 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
306 // Allocate a new index in table to hold the klass once it's been patched.
307 int index = __ oop_recorder()->allocate_metadata_index(NULL);
308 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
309 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
310 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
311 // The NULL will be dynamically patched later so the sequence to
312 // load the address literal must not be optimized.
313 __ load_const(reg, addrlit);
314
315 patching_epilog(patch, lir_patch_normal, reg, info);
316 }
317
318 void LIR_Assembler::emit_op3(LIR_Op3* op) {
319 switch (op->code()) {
320 case lir_idiv:
321 case lir_irem:
322 arithmetic_idiv(op->code(),
323 op->in_opr1(),
324 op->in_opr2(),
325 op->in_opr3(),
326 op->result_opr(),
327 op->info());
328 break;
329 case lir_fmad: {
330 const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
331 opr2 = op->in_opr2()->as_double_reg(),
332 opr3 = op->in_opr3()->as_double_reg(),
333 res = op->result_opr()->as_double_reg();
334 __ z_madbr(opr3, opr1, opr2);
335 if (res != opr3) { __ z_ldr(res, opr3); }
336 } break;
337 case lir_fmaf: {
338 const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
339 opr2 = op->in_opr2()->as_float_reg(),
340 opr3 = op->in_opr3()->as_float_reg(),
341 res = op->result_opr()->as_float_reg();
342 __ z_maebr(opr3, opr1, opr2);
343 if (res != opr3) { __ z_ler(res, opr3); }
344 } break;
345 default: ShouldNotReachHere(); break;
346 }
347 }
348
349
350 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
351 #ifdef ASSERT
352 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
353 if (op->block() != NULL) { _branch_target_blocks.append(op->block()); }
354 if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); }
355 #endif
356
357 if (op->cond() == lir_cond_always) {
358 if (op->info() != NULL) { add_debug_info_for_branch(op->info()); }
359 __ branch_optimized(Assembler::bcondAlways, *(op->label()));
360 } else {
361 Assembler::branch_condition acond = Assembler::bcondZero;
362 if (op->code() == lir_cond_float_branch) {
363 assert(op->ublock() != NULL, "must have unordered successor");
364 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
365 }
366 switch (op->cond()) {
367 case lir_cond_equal: acond = Assembler::bcondEqual; break;
368 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break;
369 case lir_cond_less: acond = Assembler::bcondLow; break;
370 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break;
371 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break;
372 case lir_cond_greater: acond = Assembler::bcondHigh; break;
373 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break;
374 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break;
375 default: ShouldNotReachHere();
376 }
377 __ branch_optimized(acond,*(op->label()));
378 }
379 }
380
381
382 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
383 LIR_Opr src = op->in_opr();
384 LIR_Opr dest = op->result_opr();
385
386 switch (op->bytecode()) {
387 case Bytecodes::_i2l:
388 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
389 break;
390
391 case Bytecodes::_l2i:
392 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
393 break;
394
395 case Bytecodes::_i2b:
396 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
397 break;
398
399 case Bytecodes::_i2c:
400 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
401 break;
402
403 case Bytecodes::_i2s:
404 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
405 break;
406
407 case Bytecodes::_f2d:
408 assert(dest->is_double_fpu(), "check");
409 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
410 break;
411
412 case Bytecodes::_d2f:
413 assert(dest->is_single_fpu(), "check");
414 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
415 break;
416
417 case Bytecodes::_i2f:
418 __ z_cefbr(dest->as_float_reg(), src->as_register());
419 break;
420
421 case Bytecodes::_i2d:
422 __ z_cdfbr(dest->as_double_reg(), src->as_register());
423 break;
424
425 case Bytecodes::_l2f:
426 __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
427 break;
428 case Bytecodes::_l2d:
429 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
430 break;
431
432 case Bytecodes::_f2i:
433 case Bytecodes::_f2l: {
434 Label done;
435 FloatRegister Rsrc = src->as_float_reg();
436 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
437 __ clear_reg(Rdst, true, false);
438 __ z_cebr(Rsrc, Rsrc);
439 __ z_brno(done); // NaN -> 0
440 if (op->bytecode() == Bytecodes::_f2i) {
441 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
442 } else { // op->bytecode() == Bytecodes::_f2l
443 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
444 }
445 __ bind(done);
446 }
447 break;
448
449 case Bytecodes::_d2i:
450 case Bytecodes::_d2l: {
451 Label done;
452 FloatRegister Rsrc = src->as_double_reg();
453 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
454 __ clear_reg(Rdst, true, false); // Don't set CC.
455 __ z_cdbr(Rsrc, Rsrc);
456 __ z_brno(done); // NaN -> 0
457 if (op->bytecode() == Bytecodes::_d2i) {
458 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
459 } else { // Bytecodes::_d2l
460 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
461 }
462 __ bind(done);
463 }
464 break;
465
466 default: ShouldNotReachHere();
467 }
468 }
469
470 void LIR_Assembler::align_call(LIR_Code code) {
471 // End of call instruction must be 4 byte aligned.
472 int offset = __ offset();
473 switch (code) {
474 case lir_icvirtual_call:
475 offset += MacroAssembler::load_const_from_toc_size();
476 // no break
477 case lir_static_call:
478 case lir_optvirtual_call:
479 case lir_dynamic_call:
480 offset += NativeCall::call_far_pcrelative_displacement_offset;
481 break;
482 case lir_virtual_call: // currently, sparc-specific for niagara
483 default: ShouldNotReachHere();
484 }
485 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
486 __ nop();
487 }
488 }
489
490 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
491 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
492 "must be aligned (offset=%d)", __ offset());
493 assert(rtype == relocInfo::none ||
494 rtype == relocInfo::opt_virtual_call_type ||
495 rtype == relocInfo::static_call_type, "unexpected rtype");
496 // Prepend each BRASL with a nop.
497 __ relocate(rtype);
498 __ z_nop();
499 __ z_brasl(Z_R14, op->addr());
500 add_call_info(code_offset(), op->info());
501 }
502
503 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
504 address virtual_call_oop_addr = NULL;
505 AddressLiteral empty_ic((address) Universe::non_oop_word());
506 virtual_call_oop_addr = __ pc();
507 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
508 if (!success) {
509 bailout("const section overflow");
510 return;
511 }
512
513 // CALL to fixup routine. Fixup routine uses ScopeDesc info
514 // to determine who we intended to call.
515 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
516 call(op, relocInfo::none);
517 }
518
519 // not supported
520 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
521 ShouldNotReachHere();
522 }
523
524 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
525 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
526 }
527
528 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
529 assert(src->is_constant(), "should not call otherwise");
530 assert(dest->is_stack(), "should not call otherwise");
531 LIR_Const* c = src->as_constant_ptr();
532
533 unsigned int lmem = 0;
534 unsigned int lcon = 0;
535 int64_t cbits = 0;
536 Address dest_addr;
537 switch (c->type()) {
538 case T_INT: // fall through
539 case T_FLOAT:
540 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
541 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
542 break;
543
544 case T_ADDRESS:
545 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
546 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
547 break;
548
549 case T_OBJECT:
550 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
551 if (c->as_jobject() == NULL) {
552 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
553 } else {
554 jobject2reg(c->as_jobject(), Z_R1_scratch);
555 __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
556 }
557 return;
558
559 case T_LONG: // fall through
560 case T_DOUBLE:
561 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
562 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
563 break;
564
565 default:
566 ShouldNotReachHere();
567 }
568
569 __ store_const(dest_addr, cbits, lmem, lcon);
570 }
571
572 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
573 assert(src->is_constant(), "should not call otherwise");
574 assert(dest->is_address(), "should not call otherwise");
575 // See special case in LIRGenerator::do_StoreIndexed.
576 // T_BYTE: Special case for card mark store.
577 assert(type == T_BYTE || !dest->as_address_ptr()->index()->is_valid(), "not supported");
578 LIR_Const* c = src->as_constant_ptr();
579 Address addr = as_Address(dest->as_address_ptr());
580
581 int store_offset = -1;
582 unsigned int lmem = 0;
583 unsigned int lcon = 0;
584 int64_t cbits = 0;
585 switch (type) {
586 case T_INT: // fall through
587 case T_FLOAT:
588 lmem = 4; lcon = 4; cbits = c->as_jint_bits();
589 break;
590
591 case T_ADDRESS:
592 lmem = 8; lcon = 4; cbits = c->as_jint_bits();
593 break;
594
595 case T_OBJECT: // fall through
596 case T_ARRAY:
597 if (c->as_jobject() == NULL) {
598 if (UseCompressedOops && !wide) {
599 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
600 } else {
601 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
602 }
603 } else {
604 jobject2reg(c->as_jobject(), Z_R1_scratch);
605 if (UseCompressedOops && !wide) {
606 __ encode_heap_oop(Z_R1_scratch);
607 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
608 } else {
609 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
610 }
611 }
612 assert(store_offset >= 0, "check");
613 break;
614
615 case T_LONG: // fall through
616 case T_DOUBLE:
617 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
618 break;
619
620 case T_BOOLEAN: // fall through
621 case T_BYTE:
622 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
623 break;
624
625 case T_CHAR: // fall through
626 case T_SHORT:
627 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
628 break;
629
630 default:
631 ShouldNotReachHere();
632 };
633
634 // Index register is normally not supported, but for
635 // LIRGenerator::CardTableBarrierSet_post_barrier we make an exception.
636 if (type == T_BYTE && dest->as_address_ptr()->index()->is_valid()) {
637 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
638 store_offset = __ offset();
639 if (Immediate::is_uimm12(addr.disp())) {
640 __ z_stc(Z_R0_scratch, addr);
641 } else {
642 __ z_stcy(Z_R0_scratch, addr);
643 }
644 }
645
646 if (store_offset == -1) {
647 store_offset = __ store_const(addr, cbits, lmem, lcon);
648 assert(store_offset >= 0, "check");
649 }
650
651 if (info != NULL) {
652 add_debug_info_for_null_check(store_offset, info);
653 }
654 }
655
656 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
657 assert(src->is_constant(), "should not call otherwise");
658 assert(dest->is_register(), "should not call otherwise");
659 LIR_Const* c = src->as_constant_ptr();
660
661 switch (c->type()) {
662 case T_INT: {
663 assert(patch_code == lir_patch_none, "no patching handled here");
664 __ load_const_optimized(dest->as_register(), c->as_jint());
665 break;
666 }
667
668 case T_ADDRESS: {
669 assert(patch_code == lir_patch_none, "no patching handled here");
670 __ load_const_optimized(dest->as_register(), c->as_jint());
671 break;
672 }
673
674 case T_LONG: {
675 assert(patch_code == lir_patch_none, "no patching handled here");
676 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
677 break;
678 }
679
680 case T_OBJECT: {
681 if (patch_code != lir_patch_none) {
682 jobject2reg_with_patching(dest->as_register(), info);
683 } else {
684 jobject2reg(c->as_jobject(), dest->as_register());
685 }
686 break;
687 }
688
689 case T_METADATA: {
690 if (patch_code != lir_patch_none) {
691 klass2reg_with_patching(dest->as_register(), info);
692 } else {
693 metadata2reg(c->as_metadata(), dest->as_register());
694 }
695 break;
696 }
697
698 case T_FLOAT: {
699 Register toc_reg = Z_R1_scratch;
700 __ load_toc(toc_reg);
701 address const_addr = __ float_constant(c->as_jfloat());
702 if (const_addr == NULL) {
703 bailout("const section overflow");
704 break;
705 }
706 int displ = const_addr - _masm->code()->consts()->start();
707 if (dest->is_single_fpu()) {
708 __ z_ley(dest->as_float_reg(), displ, toc_reg);
709 } else {
710 assert(dest->is_single_cpu(), "Must be a cpu register.");
711 __ z_ly(dest->as_register(), displ, toc_reg);
712 }
713 }
714 break;
715
716 case T_DOUBLE: {
717 Register toc_reg = Z_R1_scratch;
718 __ load_toc(toc_reg);
719 address const_addr = __ double_constant(c->as_jdouble());
720 if (const_addr == NULL) {
721 bailout("const section overflow");
722 break;
723 }
724 int displ = const_addr - _masm->code()->consts()->start();
725 if (dest->is_double_fpu()) {
726 __ z_ldy(dest->as_double_reg(), displ, toc_reg);
727 } else {
728 assert(dest->is_double_cpu(), "Must be a long register.");
729 __ z_lg(dest->as_register_lo(), displ, toc_reg);
730 }
731 }
732 break;
733
734 default:
735 ShouldNotReachHere();
736 }
737 }
738
739 Address LIR_Assembler::as_Address(LIR_Address* addr) {
740 if (addr->base()->is_illegal()) {
741 Unimplemented();
742 }
743
744 Register base = addr->base()->as_pointer_register();
745
746 if (addr->index()->is_illegal()) {
747 return Address(base, addr->disp());
748 } else if (addr->index()->is_cpu_register()) {
749 Register index = addr->index()->as_pointer_register();
750 return Address(base, index, addr->disp());
751 } else if (addr->index()->is_constant()) {
752 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
753 return Address(base, addr_offset);
754 } else {
755 ShouldNotReachHere();
756 return Address();
757 }
758 }
759
760 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
761 switch (type) {
762 case T_INT:
763 case T_FLOAT: {
764 Register tmp = Z_R1_scratch;
765 Address from = frame_map()->address_for_slot(src->single_stack_ix());
766 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
767 __ mem2reg_opt(tmp, from, false);
768 __ reg2mem_opt(tmp, to, false);
769 break;
770 }
771 case T_ADDRESS:
772 case T_OBJECT: {
773 Register tmp = Z_R1_scratch;
774 Address from = frame_map()->address_for_slot(src->single_stack_ix());
775 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
776 __ mem2reg_opt(tmp, from, true);
777 __ reg2mem_opt(tmp, to, true);
778 break;
779 }
780 case T_LONG:
781 case T_DOUBLE: {
782 Register tmp = Z_R1_scratch;
783 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
784 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
785 __ mem2reg_opt(tmp, from, true);
786 __ reg2mem_opt(tmp, to, true);
787 break;
788 }
789
790 default:
791 ShouldNotReachHere();
792 }
793 }
794
795 // 4-byte accesses only! Don't use it to access 8 bytes!
796 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
797 ShouldNotCallThis();
798 return 0; // unused
799 }
800
801 // 4-byte accesses only! Don't use it to access 8 bytes!
802 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
803 ShouldNotCallThis();
804 return 0; // unused
805 }
806
807 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
808 CodeEmitInfo* info, bool wide, bool unaligned) {
809
810 assert(type != T_METADATA, "load of metadata ptr not supported");
811 LIR_Address* addr = src_opr->as_address_ptr();
812 LIR_Opr to_reg = dest;
813
814 Register src = addr->base()->as_pointer_register();
815 Register disp_reg = Z_R0;
816 int disp_value = addr->disp();
817 bool needs_patching = (patch_code != lir_patch_none);
818
819 if (addr->base()->type() == T_OBJECT) {
820 __ verify_oop(src);
821 }
822
823 PatchingStub* patch = NULL;
824 if (needs_patching) {
825 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
826 assert(!to_reg->is_double_cpu() ||
827 patch_code == lir_patch_none ||
828 patch_code == lir_patch_normal, "patching doesn't match register");
829 }
830
831 if (addr->index()->is_illegal()) {
832 if (!Immediate::is_simm20(disp_value)) {
833 if (needs_patching) {
834 __ load_const(Z_R1_scratch, (intptr_t)0);
835 } else {
836 __ load_const_optimized(Z_R1_scratch, disp_value);
837 }
838 disp_reg = Z_R1_scratch;
839 disp_value = 0;
840 }
841 } else {
842 if (!Immediate::is_simm20(disp_value)) {
843 __ load_const_optimized(Z_R1_scratch, disp_value);
844 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
845 disp_reg = Z_R1_scratch;
846 disp_value = 0;
847 }
848 disp_reg = addr->index()->as_pointer_register();
849 }
850
851 // Remember the offset of the load. The patching_epilog must be done
852 // before the call to add_debug_info, otherwise the PcDescs don't get
853 // entered in increasing order.
854 int offset = code_offset();
855
856 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
857
858 bool short_disp = Immediate::is_uimm12(disp_value);
859
860 switch (type) {
861 case T_BOOLEAN: // fall through
862 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break;
863 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
864 case T_SHORT :
865 if (short_disp) {
866 __ z_lh(dest->as_register(), disp_value, disp_reg, src);
867 } else {
868 __ z_lhy(dest->as_register(), disp_value, disp_reg, src);
869 }
870 break;
871 case T_INT :
872 if (short_disp) {
873 __ z_l(dest->as_register(), disp_value, disp_reg, src);
874 } else {
875 __ z_ly(dest->as_register(), disp_value, disp_reg, src);
876 }
877 break;
878 case T_ADDRESS:
879 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
880 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
881 __ decode_klass_not_null(dest->as_register());
882 } else {
883 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
884 }
885 break;
886 case T_ARRAY : // fall through
887 case T_OBJECT:
888 {
889 if (UseCompressedOops && !wide) {
890 __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
891 __ oop_decoder(dest->as_register(), dest->as_register(), true);
892 } else {
893 __ z_lg(dest->as_register(), disp_value, disp_reg, src);
894 }
895 break;
896 }
897 case T_FLOAT:
898 if (short_disp) {
899 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src);
900 } else {
901 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
902 }
903 break;
904 case T_DOUBLE:
905 if (short_disp) {
906 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src);
907 } else {
908 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
909 }
910 break;
911 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
912 default : ShouldNotReachHere();
913 }
914 if (type == T_ARRAY || type == T_OBJECT) {
915 __ verify_oop(dest->as_register());
916 }
917
918 if (patch != NULL) {
919 patching_epilog(patch, patch_code, src, info);
920 }
921 if (info != NULL) add_debug_info_for_null_check(offset, info);
922 }
923
924 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
925 assert(src->is_stack(), "should not call otherwise");
926 assert(dest->is_register(), "should not call otherwise");
927
928 if (dest->is_single_cpu()) {
929 if (type == T_ARRAY || type == T_OBJECT) {
930 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
931 __ verify_oop(dest->as_register());
932 } else if (type == T_METADATA) {
933 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
934 } else {
935 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
936 }
937 } else if (dest->is_double_cpu()) {
938 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
939 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
940 } else if (dest->is_single_fpu()) {
941 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
942 __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
943 } else if (dest->is_double_fpu()) {
944 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
945 __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
946 } else {
947 ShouldNotReachHere();
948 }
949 }
950
951 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
952 assert(src->is_register(), "should not call otherwise");
953 assert(dest->is_stack(), "should not call otherwise");
954
955 if (src->is_single_cpu()) {
956 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
957 if (type == T_OBJECT || type == T_ARRAY) {
958 __ verify_oop(src->as_register());
959 __ reg2mem_opt(src->as_register(), dst, true);
960 } else if (type == T_METADATA) {
961 __ reg2mem_opt(src->as_register(), dst, true);
962 } else {
963 __ reg2mem_opt(src->as_register(), dst, false);
964 }
965 } else if (src->is_double_cpu()) {
966 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
967 __ reg2mem_opt(src->as_register_lo(), dstLO, true);
968 } else if (src->is_single_fpu()) {
969 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
970 __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
971 } else if (src->is_double_fpu()) {
972 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
973 __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
974 } else {
975 ShouldNotReachHere();
976 }
977 }
978
979 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
980 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
981 if (from_reg->is_double_fpu()) {
982 // double to double moves
983 assert(to_reg->is_double_fpu(), "should match");
984 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
985 } else {
986 // float to float moves
987 assert(to_reg->is_single_fpu(), "should match");
988 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
989 }
990 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
991 if (from_reg->is_double_cpu()) {
992 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
993 } else if (to_reg->is_double_cpu()) {
994 // int to int moves
995 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
996 } else {
997 // int to int moves
998 __ z_lgr(to_reg->as_register(), from_reg->as_register());
999 }
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1004 __ verify_oop(to_reg->as_register());
1005 }
1006 }
1007
1008 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1009 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1010 bool wide, bool unaligned) {
1011 assert(type != T_METADATA, "store of metadata ptr not supported");
1012 LIR_Address* addr = dest_opr->as_address_ptr();
1013
1014 Register dest = addr->base()->as_pointer_register();
1015 Register disp_reg = Z_R0;
1016 int disp_value = addr->disp();
1017 bool needs_patching = (patch_code != lir_patch_none);
1018
1019 if (addr->base()->is_oop_register()) {
1020 __ verify_oop(dest);
1021 }
1022
1023 PatchingStub* patch = NULL;
1024 if (needs_patching) {
1025 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1026 assert(!from->is_double_cpu() ||
1027 patch_code == lir_patch_none ||
1028 patch_code == lir_patch_normal, "patching doesn't match register");
1029 }
1030
1031 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1032 if (addr->index()->is_illegal()) {
1033 if (!Immediate::is_simm20(disp_value)) {
1034 if (needs_patching) {
1035 __ load_const(Z_R1_scratch, (intptr_t)0);
1036 } else {
1037 __ load_const_optimized(Z_R1_scratch, disp_value);
1038 }
1039 disp_reg = Z_R1_scratch;
1040 disp_value = 0;
1041 }
1042 } else {
1043 if (!Immediate::is_simm20(disp_value)) {
1044 __ load_const_optimized(Z_R1_scratch, disp_value);
1045 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1046 disp_reg = Z_R1_scratch;
1047 disp_value = 0;
1048 }
1049 disp_reg = addr->index()->as_pointer_register();
1050 }
1051
1052 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1053
1054 if (type == T_ARRAY || type == T_OBJECT) {
1055 __ verify_oop(from->as_register());
1056 }
1057
1058 bool short_disp = Immediate::is_uimm12(disp_value);
1059
1060 // Remember the offset of the store. The patching_epilog must be done
1061 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1062 // entered in increasing order.
1063 int offset = code_offset();
1064 switch (type) {
1065 case T_BOOLEAN: // fall through
1066 case T_BYTE :
1067 if (short_disp) {
1068 __ z_stc(from->as_register(), disp_value, disp_reg, dest);
1069 } else {
1070 __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1071 }
1072 break;
1073 case T_CHAR : // fall through
1074 case T_SHORT :
1075 if (short_disp) {
1076 __ z_sth(from->as_register(), disp_value, disp_reg, dest);
1077 } else {
1078 __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1079 }
1080 break;
1081 case T_INT :
1082 if (short_disp) {
1083 __ z_st(from->as_register(), disp_value, disp_reg, dest);
1084 } else {
1085 __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1086 }
1087 break;
1088 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1089 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break;
1090 break;
1091 case T_ARRAY : // fall through
1092 case T_OBJECT:
1093 {
1094 if (UseCompressedOops && !wide) {
1095 Register compressed_src = Z_R14;
1096 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1097 offset = code_offset();
1098 if (short_disp) {
1099 __ z_st(compressed_src, disp_value, disp_reg, dest);
1100 } else {
1101 __ z_sty(compressed_src, disp_value, disp_reg, dest);
1102 }
1103 } else {
1104 __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1105 }
1106 break;
1107 }
1108 case T_FLOAT :
1109 if (short_disp) {
1110 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest);
1111 } else {
1112 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1113 }
1114 break;
1115 case T_DOUBLE:
1116 if (short_disp) {
1117 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest);
1118 } else {
1119 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1120 }
1121 break;
1122 default: ShouldNotReachHere();
1123 }
1124
1125 if (patch != NULL) {
1126 patching_epilog(patch, patch_code, dest, info);
1127 }
1128
1129 if (info != NULL) add_debug_info_for_null_check(offset, info);
1130 }
1131
1132
1133 void LIR_Assembler::return_op(LIR_Opr result) {
1134 assert(result->is_illegal() ||
1135 (result->is_single_cpu() && result->as_register() == Z_R2) ||
1136 (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1137 (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1138 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1139
1140 if (SafepointMechanism::uses_thread_local_poll()) {
1141 __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset()));
1142 } else {
1143 AddressLiteral pp(os::get_polling_page());
1144 __ load_const_optimized(Z_R1_scratch, pp);
1145 }
1146
1147 // Pop the frame before the safepoint code.
1148 __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1149
1150 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1151 __ reserved_stack_check(Z_R14);
1152 }
1153
1154 // We need to mark the code position where the load from the safepoint
1155 // polling page was emitted as relocInfo::poll_return_type here.
1156 __ relocate(relocInfo::poll_return_type);
1157 __ load_from_polling_page(Z_R1_scratch);
1158
1159 __ z_br(Z_R14); // Return to caller.
1160 }
1161
1162 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1163 const Register poll_addr = tmp->as_register_lo();
1164 if (SafepointMechanism::uses_thread_local_poll()) {
1165 __ z_lg(poll_addr, Address(Z_thread, Thread::polling_page_offset()));
1166 } else {
1167 AddressLiteral pp(os::get_polling_page());
1168 __ load_const_optimized(poll_addr, pp);
1169 }
1170 guarantee(info != NULL, "Shouldn't be NULL");
1171 add_debug_info_for_branch(info);
1172 int offset = __ offset();
1173 __ relocate(relocInfo::poll_type);
1174 __ load_from_polling_page(poll_addr);
1175 return offset;
1176 }
1177
1178 void LIR_Assembler::emit_static_call_stub() {
1179
1180 // Stub is fixed up when the corresponding call is converted from calling
1181 // compiled code to calling interpreted code.
1182
1183 address call_pc = __ pc();
1184 address stub = __ start_a_stub(call_stub_size());
1185 if (stub == NULL) {
1186 bailout("static call stub overflow");
1187 return;
1188 }
1189
1190 int start = __ offset();
1191
1192 __ relocate(static_stub_Relocation::spec(call_pc));
1193
1194 // See also Matcher::interpreter_method_oop_reg().
1195 AddressLiteral meta = __ allocate_metadata_address(NULL);
1196 bool success = __ load_const_from_toc(Z_method, meta);
1197
1198 __ set_inst_mark();
1199 AddressLiteral a((address)-1);
1200 success = success && __ load_const_from_toc(Z_R1, a);
1201 if (!success) {
1202 bailout("const section overflow");
1203 return;
1204 }
1205
1206 __ z_br(Z_R1);
1207 assert(__ offset() - start <= call_stub_size(), "stub too big");
1208 __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1209 }
1210
1211 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1212 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1213 if (opr1->is_single_cpu()) {
1214 Register reg1 = opr1->as_register();
1215 if (opr2->is_single_cpu()) {
1216 // cpu register - cpu register
1217 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1218 __ z_clgr(reg1, opr2->as_register());
1219 } else {
1220 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1221 if (unsigned_comp) {
1222 __ z_clr(reg1, opr2->as_register());
1223 } else {
1224 __ z_cr(reg1, opr2->as_register());
1225 }
1226 }
1227 } else if (opr2->is_stack()) {
1228 // cpu register - stack
1229 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1230 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1231 } else {
1232 if (unsigned_comp) {
1233 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1234 } else {
1235 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1236 }
1237 }
1238 } else if (opr2->is_constant()) {
1239 // cpu register - constant
1240 LIR_Const* c = opr2->as_constant_ptr();
1241 if (c->type() == T_INT) {
1242 if (unsigned_comp) {
1243 __ z_clfi(reg1, c->as_jint());
1244 } else {
1245 __ z_cfi(reg1, c->as_jint());
1246 }
1247 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
1248 // In 64bit oops are single register.
1249 jobject o = c->as_jobject();
1250 if (o == NULL) {
1251 __ z_ltgr(reg1, reg1);
1252 } else {
1253 jobject2reg(o, Z_R1_scratch);
1254 __ z_cgr(reg1, Z_R1_scratch);
1255 }
1256 } else {
1257 fatal("unexpected type: %s", basictype_to_str(c->type()));
1258 }
1259 // cpu register - address
1260 } else if (opr2->is_address()) {
1261 if (op->info() != NULL) {
1262 add_debug_info_for_null_check_here(op->info());
1263 }
1264 if (unsigned_comp) {
1265 __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1266 } else {
1267 __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1268 }
1269 } else {
1270 ShouldNotReachHere();
1271 }
1272
1273 } else if (opr1->is_double_cpu()) {
1274 assert(!unsigned_comp, "unexpected");
1275 Register xlo = opr1->as_register_lo();
1276 Register xhi = opr1->as_register_hi();
1277 if (opr2->is_double_cpu()) {
1278 __ z_cgr(xlo, opr2->as_register_lo());
1279 } else if (opr2->is_constant()) {
1280 // cpu register - constant 0
1281 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1282 __ z_ltgr(xlo, xlo);
1283 } else {
1284 ShouldNotReachHere();
1285 }
1286
1287 } else if (opr1->is_single_fpu()) {
1288 if (opr2->is_single_fpu()) {
1289 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1290 } else {
1291 // stack slot
1292 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1293 if (Immediate::is_uimm12(addr.disp())) {
1294 __ z_ceb(opr1->as_float_reg(), addr);
1295 } else {
1296 __ z_ley(Z_fscratch_1, addr);
1297 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1298 }
1299 }
1300 } else if (opr1->is_double_fpu()) {
1301 if (opr2->is_double_fpu()) {
1302 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1303 } else {
1304 // stack slot
1305 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1306 if (Immediate::is_uimm12(addr.disp())) {
1307 __ z_cdb(opr1->as_double_reg(), addr);
1308 } else {
1309 __ z_ldy(Z_fscratch_1, addr);
1310 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1311 }
1312 }
1313 } else {
1314 ShouldNotReachHere();
1315 }
1316 }
1317
1318 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1319 Label done;
1320 Register dreg = dst->as_register();
1321
1322 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1323 assert((left->is_single_fpu() && right->is_single_fpu()) ||
1324 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1325 bool is_single = left->is_single_fpu();
1326 bool is_unordered_less = (code == lir_ucmp_fd2i);
1327 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1328 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1329 if (is_single) {
1330 __ z_cebr(lreg, rreg);
1331 } else {
1332 __ z_cdbr(lreg, rreg);
1333 }
1334 if (VM_Version::has_LoadStoreConditional()) {
1335 Register one = Z_R0_scratch;
1336 Register minus_one = Z_R1_scratch;
1337 __ z_lghi(minus_one, -1);
1338 __ z_lghi(one, 1);
1339 __ z_lghi(dreg, 0);
1340 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered);
1341 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1342 } else {
1343 __ clear_reg(dreg, true, false);
1344 __ z_bre(done); // if (left == right) dst = 0
1345
1346 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1347 __ z_lhi(dreg, 1);
1348 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1349
1350 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1351 __ z_lhi(dreg, -1);
1352 }
1353 } else {
1354 assert(code == lir_cmp_l2i, "check");
1355 if (VM_Version::has_LoadStoreConditional()) {
1356 Register one = Z_R0_scratch;
1357 Register minus_one = Z_R1_scratch;
1358 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1359 __ z_lghi(minus_one, -1);
1360 __ z_lghi(one, 1);
1361 __ z_lghi(dreg, 0);
1362 __ z_locgr(dreg, one, Assembler::bcondHigh);
1363 __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1364 } else {
1365 __ z_cgr(left->as_register_lo(), right->as_register_lo());
1366 __ z_lghi(dreg, 0); // eq value
1367 __ z_bre(done);
1368 __ z_lghi(dreg, 1); // gt value
1369 __ z_brh(done);
1370 __ z_lghi(dreg, -1); // lt value
1371 }
1372 }
1373 __ bind(done);
1374 }
1375
1376 // result = condition ? opr1 : opr2
1377 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1378 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1379 switch (condition) {
1380 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
1381 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break;
1382 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break;
1383 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1384 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1385 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break;
1386 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break;
1387 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break;
1388 default: ShouldNotReachHere();
1389 }
1390
1391 if (opr1->is_cpu_register()) {
1392 reg2reg(opr1, result);
1393 } else if (opr1->is_stack()) {
1394 stack2reg(opr1, result, result->type());
1395 } else if (opr1->is_constant()) {
1396 const2reg(opr1, result, lir_patch_none, NULL);
1397 } else {
1398 ShouldNotReachHere();
1399 }
1400
1401 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1402 // Optimized version that does not require a branch.
1403 if (opr2->is_single_cpu()) {
1404 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1405 __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1406 } else if (opr2->is_double_cpu()) {
1407 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1408 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1409 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1410 } else if (opr2->is_single_stack()) {
1411 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1412 } else if (opr2->is_double_stack()) {
1413 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1414 } else {
1415 ShouldNotReachHere();
1416 }
1417 } else {
1418 Label skip;
1419 __ z_brc(acond, skip);
1420 if (opr2->is_cpu_register()) {
1421 reg2reg(opr2, result);
1422 } else if (opr2->is_stack()) {
1423 stack2reg(opr2, result, result->type());
1424 } else if (opr2->is_constant()) {
1425 const2reg(opr2, result, lir_patch_none, NULL);
1426 } else {
1427 ShouldNotReachHere();
1428 }
1429 __ bind(skip);
1430 }
1431 }
1432
1433 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1434 CodeEmitInfo* info, bool pop_fpu_stack) {
1435 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1436
1437 if (left->is_single_cpu()) {
1438 assert(left == dest, "left and dest must be equal");
1439 Register lreg = left->as_register();
1440
1441 if (right->is_single_cpu()) {
1442 // cpu register - cpu register
1443 Register rreg = right->as_register();
1444 switch (code) {
1445 case lir_add: __ z_ar (lreg, rreg); break;
1446 case lir_sub: __ z_sr (lreg, rreg); break;
1447 case lir_mul: __ z_msr(lreg, rreg); break;
1448 default: ShouldNotReachHere();
1449 }
1450
1451 } else if (right->is_stack()) {
1452 // cpu register - stack
1453 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1454 switch (code) {
1455 case lir_add: __ z_ay(lreg, raddr); break;
1456 case lir_sub: __ z_sy(lreg, raddr); break;
1457 default: ShouldNotReachHere();
1458 }
1459
1460 } else if (right->is_constant()) {
1461 // cpu register - constant
1462 jint c = right->as_constant_ptr()->as_jint();
1463 switch (code) {
1464 case lir_add: __ z_agfi(lreg, c); break;
1465 case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
1466 case lir_mul: __ z_msfi(lreg, c); break;
1467 default: ShouldNotReachHere();
1468 }
1469
1470 } else {
1471 ShouldNotReachHere();
1472 }
1473
1474 } else if (left->is_double_cpu()) {
1475 assert(left == dest, "left and dest must be equal");
1476 Register lreg_lo = left->as_register_lo();
1477 Register lreg_hi = left->as_register_hi();
1478
1479 if (right->is_double_cpu()) {
1480 // cpu register - cpu register
1481 Register rreg_lo = right->as_register_lo();
1482 Register rreg_hi = right->as_register_hi();
1483 assert_different_registers(lreg_lo, rreg_lo);
1484 switch (code) {
1485 case lir_add:
1486 __ z_agr(lreg_lo, rreg_lo);
1487 break;
1488 case lir_sub:
1489 __ z_sgr(lreg_lo, rreg_lo);
1490 break;
1491 case lir_mul:
1492 __ z_msgr(lreg_lo, rreg_lo);
1493 break;
1494 default:
1495 ShouldNotReachHere();
1496 }
1497
1498 } else if (right->is_constant()) {
1499 // cpu register - constant
1500 jlong c = right->as_constant_ptr()->as_jlong_bits();
1501 switch (code) {
1502 case lir_add: __ z_agfi(lreg_lo, c); break;
1503 case lir_sub:
1504 if (c != min_jint) {
1505 __ z_agfi(lreg_lo, -c);
1506 } else {
1507 // -min_jint cannot be represented as simm32 in z_agfi
1508 // min_jint sign extended: 0xffffffff80000000
1509 // -min_jint as 64 bit integer: 0x0000000080000000
1510 // 0x80000000 can be represented as uimm32 in z_algfi
1511 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1512 __ z_algfi(lreg_lo, UCONST64(0x80000000));
1513 }
1514 break;
1515 case lir_mul: __ z_msgfi(lreg_lo, c); break;
1516 default:
1517 ShouldNotReachHere();
1518 }
1519
1520 } else {
1521 ShouldNotReachHere();
1522 }
1523
1524 } else if (left->is_single_fpu()) {
1525 assert(left == dest, "left and dest must be equal");
1526 FloatRegister lreg = left->as_float_reg();
1527 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1528 Address raddr;
1529
1530 if (rreg == fnoreg) {
1531 assert(right->is_single_stack(), "constants should be loaded into register");
1532 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1533 if (!Immediate::is_uimm12(raddr.disp())) {
1534 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1535 }
1536 }
1537
1538 if (rreg != fnoreg) {
1539 switch (code) {
1540 case lir_add: __ z_aebr(lreg, rreg); break;
1541 case lir_sub: __ z_sebr(lreg, rreg); break;
1542 case lir_mul_strictfp: // fall through
1543 case lir_mul: __ z_meebr(lreg, rreg); break;
1544 case lir_div_strictfp: // fall through
1545 case lir_div: __ z_debr(lreg, rreg); break;
1546 default: ShouldNotReachHere();
1547 }
1548 } else {
1549 switch (code) {
1550 case lir_add: __ z_aeb(lreg, raddr); break;
1551 case lir_sub: __ z_seb(lreg, raddr); break;
1552 case lir_mul_strictfp: // fall through
1553 case lir_mul: __ z_meeb(lreg, raddr); break;
1554 case lir_div_strictfp: // fall through
1555 case lir_div: __ z_deb(lreg, raddr); break;
1556 default: ShouldNotReachHere();
1557 }
1558 }
1559 } else if (left->is_double_fpu()) {
1560 assert(left == dest, "left and dest must be equal");
1561 FloatRegister lreg = left->as_double_reg();
1562 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1563 Address raddr;
1564
1565 if (rreg == fnoreg) {
1566 assert(right->is_double_stack(), "constants should be loaded into register");
1567 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1568 if (!Immediate::is_uimm12(raddr.disp())) {
1569 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1570 }
1571 }
1572
1573 if (rreg != fnoreg) {
1574 switch (code) {
1575 case lir_add: __ z_adbr(lreg, rreg); break;
1576 case lir_sub: __ z_sdbr(lreg, rreg); break;
1577 case lir_mul_strictfp: // fall through
1578 case lir_mul: __ z_mdbr(lreg, rreg); break;
1579 case lir_div_strictfp: // fall through
1580 case lir_div: __ z_ddbr(lreg, rreg); break;
1581 default: ShouldNotReachHere();
1582 }
1583 } else {
1584 switch (code) {
1585 case lir_add: __ z_adb(lreg, raddr); break;
1586 case lir_sub: __ z_sdb(lreg, raddr); break;
1587 case lir_mul_strictfp: // fall through
1588 case lir_mul: __ z_mdb(lreg, raddr); break;
1589 case lir_div_strictfp: // fall through
1590 case lir_div: __ z_ddb(lreg, raddr); break;
1591 default: ShouldNotReachHere();
1592 }
1593 }
1594 } else if (left->is_address()) {
1595 assert(left == dest, "left and dest must be equal");
1596 assert(code == lir_add, "unsupported operation");
1597 assert(right->is_constant(), "unsupported operand");
1598 jint c = right->as_constant_ptr()->as_jint();
1599 LIR_Address* lir_addr = left->as_address_ptr();
1600 Address addr = as_Address(lir_addr);
1601 switch (lir_addr->type()) {
1602 case T_INT:
1603 __ add2mem_32(addr, c, Z_R1_scratch);
1604 break;
1605 case T_LONG:
1606 __ add2mem_64(addr, c, Z_R1_scratch);
1607 break;
1608 default:
1609 ShouldNotReachHere();
1610 }
1611 } else {
1612 ShouldNotReachHere();
1613 }
1614 }
1615
1616 void LIR_Assembler::fpop() {
1617 // do nothing
1618 }
1619
1620 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1621 switch (code) {
1622 case lir_sqrt: {
1623 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1624 FloatRegister src_reg = value->as_double_reg();
1625 FloatRegister dst_reg = dest->as_double_reg();
1626 __ z_sqdbr(dst_reg, src_reg);
1627 break;
1628 }
1629 case lir_abs: {
1630 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1631 FloatRegister src_reg = value->as_double_reg();
1632 FloatRegister dst_reg = dest->as_double_reg();
1633 __ z_lpdbr(dst_reg, src_reg);
1634 break;
1635 }
1636 default: {
1637 ShouldNotReachHere();
1638 break;
1639 }
1640 }
1641 }
1642
1643 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1644 if (left->is_single_cpu()) {
1645 Register reg = left->as_register();
1646 if (right->is_constant()) {
1647 int val = right->as_constant_ptr()->as_jint();
1648 switch (code) {
1649 case lir_logic_and: __ z_nilf(reg, val); break;
1650 case lir_logic_or: __ z_oilf(reg, val); break;
1651 case lir_logic_xor: __ z_xilf(reg, val); break;
1652 default: ShouldNotReachHere();
1653 }
1654 } else if (right->is_stack()) {
1655 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1656 switch (code) {
1657 case lir_logic_and: __ z_ny(reg, raddr); break;
1658 case lir_logic_or: __ z_oy(reg, raddr); break;
1659 case lir_logic_xor: __ z_xy(reg, raddr); break;
1660 default: ShouldNotReachHere();
1661 }
1662 } else {
1663 Register rright = right->as_register();
1664 switch (code) {
1665 case lir_logic_and: __ z_nr(reg, rright); break;
1666 case lir_logic_or : __ z_or(reg, rright); break;
1667 case lir_logic_xor: __ z_xr(reg, rright); break;
1668 default: ShouldNotReachHere();
1669 }
1670 }
1671 move_regs(reg, dst->as_register());
1672 } else {
1673 Register l_lo = left->as_register_lo();
1674 if (right->is_constant()) {
1675 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1676 switch (code) {
1677 case lir_logic_and:
1678 __ z_ngr(l_lo, Z_R1_scratch);
1679 break;
1680 case lir_logic_or:
1681 __ z_ogr(l_lo, Z_R1_scratch);
1682 break;
1683 case lir_logic_xor:
1684 __ z_xgr(l_lo, Z_R1_scratch);
1685 break;
1686 default: ShouldNotReachHere();
1687 }
1688 } else {
1689 Register r_lo;
1690 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
1691 r_lo = right->as_register();
1692 } else {
1693 r_lo = right->as_register_lo();
1694 }
1695 switch (code) {
1696 case lir_logic_and:
1697 __ z_ngr(l_lo, r_lo);
1698 break;
1699 case lir_logic_or:
1700 __ z_ogr(l_lo, r_lo);
1701 break;
1702 case lir_logic_xor:
1703 __ z_xgr(l_lo, r_lo);
1704 break;
1705 default: ShouldNotReachHere();
1706 }
1707 }
1708
1709 Register dst_lo = dst->as_register_lo();
1710
1711 move_regs(l_lo, dst_lo);
1712 }
1713 }
1714
1715 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1716 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1717 if (left->is_double_cpu()) {
1718 // 64 bit integer case
1719 assert(left->is_double_cpu(), "left must be register");
1720 assert(right->is_double_cpu() || is_power_of_2_long(right->as_jlong()),
1721 "right must be register or power of 2 constant");
1722 assert(result->is_double_cpu(), "result must be register");
1723
1724 Register lreg = left->as_register_lo();
1725 Register dreg = result->as_register_lo();
1726
1727 if (right->is_constant()) {
1728 // Convert division by a power of two into some shifts and logical operations.
1729 Register treg1 = Z_R0_scratch;
1730 Register treg2 = Z_R1_scratch;
1731 jlong divisor = right->as_jlong();
1732 jlong log_divisor = log2_long(right->as_jlong());
1733
1734 if (divisor == min_jlong) {
1735 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1736 if (dreg == lreg) {
1737 NearLabel done;
1738 __ load_const_optimized(treg2, min_jlong);
1739 __ z_cgr(lreg, treg2);
1740 __ z_lghi(dreg, 0); // Preserves condition code.
1741 __ z_brne(done);
1742 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1
1743 __ bind(done);
1744 } else {
1745 assert_different_registers(dreg, lreg);
1746 NearLabel done;
1747 __ z_lghi(dreg, 0);
1748 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1749 __ z_lghi(dreg, 1);
1750 __ bind(done);
1751 }
1752 return;
1753 }
1754 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1755 if (divisor == 2) {
1756 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1757 } else {
1758 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1759 __ and_imm(treg2, divisor - 1, treg1, true);
1760 }
1761 if (code == lir_idiv) {
1762 __ z_agr(dreg, treg2);
1763 __ z_srag(dreg, dreg, log_divisor);
1764 } else {
1765 assert(code == lir_irem, "check");
1766 __ z_agr(treg2, dreg);
1767 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1768 __ z_sgr(dreg, treg2);
1769 }
1770 return;
1771 }
1772
1773 // Divisor is not a power of 2 constant.
1774 Register rreg = right->as_register_lo();
1775 Register treg = temp->as_register_lo();
1776 assert(right->is_double_cpu(), "right must be register");
1777 assert(lreg == Z_R11, "see ldivInOpr()");
1778 assert(rreg != lreg, "right register must not be same as left register");
1779 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1780 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1781
1782 Register R1 = lreg->predecessor();
1783 Register R2 = rreg;
1784 assert(code != lir_idiv || lreg==dreg, "see code below");
1785 if (code == lir_idiv) {
1786 __ z_lcgr(lreg, lreg);
1787 } else {
1788 __ clear_reg(dreg, true, false);
1789 }
1790 NearLabel done;
1791 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1792 if (code == lir_idiv) {
1793 __ z_lcgr(lreg, lreg); // Revert lcgr above.
1794 }
1795 if (ImplicitDiv0Checks) {
1796 // No debug info because the idiv won't trap.
1797 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1798 // which is unnecessary, too.
1799 add_debug_info_for_div0(__ offset(), info);
1800 }
1801 __ z_dsgr(R1, R2);
1802 __ bind(done);
1803 return;
1804 }
1805
1806 // 32 bit integer case
1807
1808 assert(left->is_single_cpu(), "left must be register");
1809 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1810 assert(result->is_single_cpu(), "result must be register");
1811
1812 Register lreg = left->as_register();
1813 Register dreg = result->as_register();
1814
1815 if (right->is_constant()) {
1816 // Convert division by a power of two into some shifts and logical operations.
1817 Register treg1 = Z_R0_scratch;
1818 Register treg2 = Z_R1_scratch;
1819 jlong divisor = right->as_jint();
1820 jlong log_divisor = log2_long(right->as_jint());
1821 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1822 if (divisor == 2) {
1823 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0
1824 } else {
1825 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0
1826 __ and_imm(treg2, divisor - 1, treg1, true);
1827 }
1828 if (code == lir_idiv) {
1829 __ z_agr(dreg, treg2);
1830 __ z_srag(dreg, dreg, log_divisor);
1831 } else {
1832 assert(code == lir_irem, "check");
1833 __ z_agr(treg2, dreg);
1834 __ and_imm(treg2, ~(divisor - 1), treg1, true);
1835 __ z_sgr(dreg, treg2);
1836 }
1837 return;
1838 }
1839
1840 // Divisor is not a power of 2 constant.
1841 Register rreg = right->as_register();
1842 Register treg = temp->as_register();
1843 assert(right->is_single_cpu(), "right must be register");
1844 assert(lreg == Z_R11, "left register must be rax,");
1845 assert(rreg != lreg, "right register must not be same as left register");
1846 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1847 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1848
1849 Register R1 = lreg->predecessor();
1850 Register R2 = rreg;
1851 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1852 if (ImplicitDiv0Checks) {
1853 // No debug info because the idiv won't trap.
1854 // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1855 // which is unnecessary, too.
1856 add_debug_info_for_div0(__ offset(), info);
1857 }
1858 __ z_dsgfr(R1, R2);
1859 }
1860
1861 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1862 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1863 assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1864
1865 // Exception object is not added to oop map by LinearScan
1866 // (LinearScan assumes that no oops are in fixed registers).
1867 info->add_register_oop(exceptionOop);
1868
1869 // Reuse the debug info from the safepoint poll for the throw op itself.
1870 __ get_PC(Z_EXC_PC);
1871 add_call_info(__ offset(), info); // for exception handler
1872 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1873 : Runtime1::handle_exception_nofpu_id);
1874 emit_call_c(stub);
1875 }
1876
1877 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1878 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1879
1880 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1881 }
1882
1883 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1884 ciArrayKlass* default_type = op->expected_type();
1885 Register src = op->src()->as_register();
1886 Register dst = op->dst()->as_register();
1887 Register src_pos = op->src_pos()->as_register();
1888 Register dst_pos = op->dst_pos()->as_register();
1889 Register length = op->length()->as_register();
1890 Register tmp = op->tmp()->as_register();
1891
1892 CodeStub* stub = op->stub();
1893 int flags = op->flags();
1894 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1895 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1896
1897 // If we don't know anything, just go through the generic arraycopy.
1898 if (default_type == NULL) {
1899 address copyfunc_addr = StubRoutines::generic_arraycopy();
1900
1901 if (copyfunc_addr == NULL) {
1902 // Take a slow path for generic arraycopy.
1903 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1904 __ bind(*stub->continuation());
1905 return;
1906 }
1907
1908 Label done;
1909 // Save outgoing arguments in callee saved registers (C convention) in case
1910 // a call to System.arraycopy is needed.
1911 Register callee_saved_src = Z_R10;
1912 Register callee_saved_src_pos = Z_R11;
1913 Register callee_saved_dst = Z_R12;
1914 Register callee_saved_dst_pos = Z_R13;
1915 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1916
1917 __ lgr_if_needed(callee_saved_src, src);
1918 __ lgr_if_needed(callee_saved_src_pos, src_pos);
1919 __ lgr_if_needed(callee_saved_dst, dst);
1920 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1921 __ lgr_if_needed(callee_saved_length, length);
1922
1923 // C function requires 64 bit values.
1924 __ z_lgfr(src_pos, src_pos);
1925 __ z_lgfr(dst_pos, dst_pos);
1926 __ z_lgfr(length, length);
1927
1928 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
1929
1930 // The arguments are in the corresponding registers.
1931 assert(Z_ARG1 == src, "assumption");
1932 assert(Z_ARG2 == src_pos, "assumption");
1933 assert(Z_ARG3 == dst, "assumption");
1934 assert(Z_ARG4 == dst_pos, "assumption");
1935 assert(Z_ARG5 == length, "assumption");
1936 #ifndef PRODUCT
1937 if (PrintC1Statistics) {
1938 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
1939 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
1940 }
1941 #endif
1942 emit_call_c(copyfunc_addr);
1943 CHECK_BAILOUT();
1944
1945 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
1946
1947 __ z_lgr(tmp, Z_RET);
1948 __ z_xilf(tmp, -1);
1949
1950 // Restore values from callee saved registers so they are where the stub
1951 // expects them.
1952 __ lgr_if_needed(src, callee_saved_src);
1953 __ lgr_if_needed(src_pos, callee_saved_src_pos);
1954 __ lgr_if_needed(dst, callee_saved_dst);
1955 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
1956 __ lgr_if_needed(length, callee_saved_length);
1957
1958 __ z_sr(length, tmp);
1959 __ z_ar(src_pos, tmp);
1960 __ z_ar(dst_pos, tmp);
1961 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1962
1963 __ bind(*stub->continuation());
1964 return;
1965 }
1966
1967 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
1968
1969 int elem_size = type2aelembytes(basic_type);
1970 int shift_amount;
1971
1972 switch (elem_size) {
1973 case 1 :
1974 shift_amount = 0;
1975 break;
1976 case 2 :
1977 shift_amount = 1;
1978 break;
1979 case 4 :
1980 shift_amount = 2;
1981 break;
1982 case 8 :
1983 shift_amount = 3;
1984 break;
1985 default:
1986 shift_amount = -1;
1987 ShouldNotReachHere();
1988 }
1989
1990 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
1991 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
1992 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
1993 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
1994
1995 // Length and pos's are all sign extended at this point on 64bit.
1996
1997 // test for NULL
1998 if (flags & LIR_OpArrayCopy::src_null_check) {
1999 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2000 }
2001 if (flags & LIR_OpArrayCopy::dst_null_check) {
2002 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2003 }
2004
2005 // Check if negative.
2006 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2007 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2008 }
2009 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2010 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2011 }
2012
2013 // If the compiler was not able to prove that exact type of the source or the destination
2014 // of the arraycopy is an array type, check at runtime if the source or the destination is
2015 // an instance type.
2016 if (flags & LIR_OpArrayCopy::type_check) {
2017 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2018
2019 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2020 __ load_klass(tmp, dst);
2021 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2022 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2023 }
2024
2025 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2026 __ load_klass(tmp, src);
2027 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2028 __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2029 }
2030 }
2031
2032 if (flags & LIR_OpArrayCopy::src_range_check) {
2033 __ z_la(tmp, Address(src_pos, length));
2034 __ z_cl(tmp, src_length_addr);
2035 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2036 }
2037 if (flags & LIR_OpArrayCopy::dst_range_check) {
2038 __ z_la(tmp, Address(dst_pos, length));
2039 __ z_cl(tmp, dst_length_addr);
2040 __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2041 }
2042
2043 if (flags & LIR_OpArrayCopy::length_positive_check) {
2044 __ z_ltr(length, length);
2045 __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2046 }
2047
2048 // Stubs require 64 bit values.
2049 __ z_lgfr(src_pos, src_pos); // int -> long
2050 __ z_lgfr(dst_pos, dst_pos); // int -> long
2051 __ z_lgfr(length, length); // int -> long
2052
2053 if (flags & LIR_OpArrayCopy::type_check) {
2054 // We don't know the array types are compatible.
2055 if (basic_type != T_OBJECT) {
2056 // Simple test for basic type arrays.
2057 if (UseCompressedClassPointers) {
2058 __ z_l(tmp, src_klass_addr);
2059 __ z_c(tmp, dst_klass_addr);
2060 } else {
2061 __ z_lg(tmp, src_klass_addr);
2062 __ z_cg(tmp, dst_klass_addr);
2063 }
2064 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2065 } else {
2066 // For object arrays, if src is a sub class of dst then we can
2067 // safely do the copy.
2068 NearLabel cont, slow;
2069 Register src_klass = Z_R1_scratch;
2070 Register dst_klass = Z_R10;
2071
2072 __ load_klass(src_klass, src);
2073 __ load_klass(dst_klass, dst);
2074
2075 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL);
2076
2077 store_parameter(src_klass, 0); // sub
2078 store_parameter(dst_klass, 1); // super
2079 emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id));
2080 CHECK_BAILOUT();
2081 // Sets condition code 0 for match (2 otherwise).
2082 __ branch_optimized(Assembler::bcondEqual, cont);
2083
2084 __ bind(slow);
2085
2086 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2087 if (copyfunc_addr != NULL) { // use stub if available
2088 // Src is not a sub class of dst so we have to do a
2089 // per-element check.
2090
2091 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2092 if ((flags & mask) != mask) {
2093 // Check that at least both of them object arrays.
2094 assert(flags & mask, "one of the two should be known to be an object array");
2095
2096 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2097 __ load_klass(tmp, src);
2098 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2099 __ load_klass(tmp, dst);
2100 }
2101 Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2102 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2103 __ load_const_optimized(Z_R1_scratch, objArray_lh);
2104 __ z_c(Z_R1_scratch, klass_lh_addr);
2105 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2106 }
2107
2108 // Save outgoing arguments in callee saved registers (C convention) in case
2109 // a call to System.arraycopy is needed.
2110 Register callee_saved_src = Z_R10;
2111 Register callee_saved_src_pos = Z_R11;
2112 Register callee_saved_dst = Z_R12;
2113 Register callee_saved_dst_pos = Z_R13;
2114 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2115
2116 __ lgr_if_needed(callee_saved_src, src);
2117 __ lgr_if_needed(callee_saved_src_pos, src_pos);
2118 __ lgr_if_needed(callee_saved_dst, dst);
2119 __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2120 __ lgr_if_needed(callee_saved_length, length);
2121
2122 __ z_llgfr(length, length); // Higher 32bits must be null.
2123
2124 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2125 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2126
2127 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2128 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2129 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2130 assert_different_registers(Z_ARG2, dst, length);
2131
2132 __ z_lgr(Z_ARG3, length);
2133 assert_different_registers(Z_ARG3, dst);
2134
2135 __ load_klass(Z_ARG5, dst);
2136 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2137 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2138 emit_call_c(copyfunc_addr);
2139 CHECK_BAILOUT();
2140
2141 #ifndef PRODUCT
2142 if (PrintC1Statistics) {
2143 NearLabel failed;
2144 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2145 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2146 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2147 __ bind(failed);
2148 }
2149 #endif
2150
2151 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2152
2153 #ifndef PRODUCT
2154 if (PrintC1Statistics) {
2155 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2156 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2157 }
2158 #endif
2159
2160 __ z_lgr(tmp, Z_RET);
2161 __ z_xilf(tmp, -1);
2162
2163 // Restore previously spilled arguments
2164 __ lgr_if_needed(src, callee_saved_src);
2165 __ lgr_if_needed(src_pos, callee_saved_src_pos);
2166 __ lgr_if_needed(dst, callee_saved_dst);
2167 __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2168 __ lgr_if_needed(length, callee_saved_length);
2169
2170 __ z_sr(length, tmp);
2171 __ z_ar(src_pos, tmp);
2172 __ z_ar(dst_pos, tmp);
2173 }
2174
2175 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2176
2177 __ bind(cont);
2178 }
2179 }
2180
2181 #ifdef ASSERT
2182 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2183 // Sanity check the known type with the incoming class. For the
2184 // primitive case the types must match exactly with src.klass and
2185 // dst.klass each exactly matching the default type. For the
2186 // object array case, if no type check is needed then either the
2187 // dst type is exactly the expected type and the src type is a
2188 // subtype which we can't check or src is the same array as dst
2189 // but not necessarily exactly of type default_type.
2190 NearLabel known_ok, halt;
2191 metadata2reg(default_type->constant_encoding(), tmp);
2192 if (UseCompressedClassPointers) {
2193 __ encode_klass_not_null(tmp);
2194 }
2195
2196 if (basic_type != T_OBJECT) {
2197 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2198 else { __ z_cg(tmp, dst_klass_addr); }
2199 __ branch_optimized(Assembler::bcondNotEqual, halt);
2200 if (UseCompressedClassPointers) { __ z_c (tmp, src_klass_addr); }
2201 else { __ z_cg(tmp, src_klass_addr); }
2202 __ branch_optimized(Assembler::bcondEqual, known_ok);
2203 } else {
2204 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); }
2205 else { __ z_cg(tmp, dst_klass_addr); }
2206 __ branch_optimized(Assembler::bcondEqual, known_ok);
2207 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2208 }
2209 __ bind(halt);
2210 __ stop("incorrect type information in arraycopy");
2211 __ bind(known_ok);
2212 }
2213 #endif
2214
2215 #ifndef PRODUCT
2216 if (PrintC1Statistics) {
2217 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2218 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2219 }
2220 #endif
2221
2222 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2223 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2224
2225 assert_different_registers(Z_ARG1, dst, dst_pos, length);
2226 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2227 assert_different_registers(Z_ARG2, length);
2228 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2229 __ lgr_if_needed(Z_ARG3, length);
2230
2231 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2232 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2233 const char *name;
2234 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2235 __ call_VM_leaf(entry);
2236
2237 __ bind(*stub->continuation());
2238 }
2239
2240 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2241 if (dest->is_single_cpu()) {
2242 if (left->type() == T_OBJECT) {
2243 switch (code) {
2244 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2245 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2246 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2247 default: ShouldNotReachHere();
2248 }
2249 } else {
2250 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2251 Register masked_count = Z_R1_scratch;
2252 __ z_lr(masked_count, count->as_register());
2253 __ z_nill(masked_count, 31);
2254 switch (code) {
2255 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2256 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break;
2257 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break;
2258 default: ShouldNotReachHere();
2259 }
2260 }
2261 } else {
2262 switch (code) {
2263 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2264 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2265 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2266 default: ShouldNotReachHere();
2267 }
2268 }
2269 }
2270
2271 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2272 if (left->type() == T_OBJECT) {
2273 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2274 Register l = left->as_register();
2275 Register d = dest->as_register_lo();
2276 switch (code) {
2277 case lir_shl: __ z_sllg (d, l, count); break;
2278 case lir_shr: __ z_srag (d, l, count); break;
2279 case lir_ushr: __ z_srlg (d, l, count); break;
2280 default: ShouldNotReachHere();
2281 }
2282 return;
2283 }
2284 if (dest->is_single_cpu()) {
2285 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2286 count = count & 0x1F; // Java spec
2287 switch (code) {
2288 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break;
2289 case lir_shr: __ z_sra (dest->as_register(), count); break;
2290 case lir_ushr: __ z_srl (dest->as_register(), count); break;
2291 default: ShouldNotReachHere();
2292 }
2293 } else if (dest->is_double_cpu()) {
2294 count = count & 63; // Java spec
2295 Register l = left->as_pointer_register();
2296 Register d = dest->as_pointer_register();
2297 switch (code) {
2298 case lir_shl: __ z_sllg (d, l, count); break;
2299 case lir_shr: __ z_srag (d, l, count); break;
2300 case lir_ushr: __ z_srlg (d, l, count); break;
2301 default: ShouldNotReachHere();
2302 }
2303 } else {
2304 ShouldNotReachHere();
2305 }
2306 }
2307
2308 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2309 if (op->init_check()) {
2310 // Make sure klass is initialized & doesn't have finalizer.
2311 const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2312 Register iklass = op->klass()->as_register();
2313 add_debug_info_for_null_check_here(op->stub()->info());
2314 if (Immediate::is_uimm12(state_offset)) {
2315 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2316 } else {
2317 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2318 }
2319 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2320 }
2321 __ allocate_object(op->obj()->as_register(),
2322 op->tmp1()->as_register(),
2323 op->tmp2()->as_register(),
2324 op->header_size(),
2325 op->object_size(),
2326 op->klass()->as_register(),
2327 *op->stub()->entry());
2328 __ bind(*op->stub()->continuation());
2329 __ verify_oop(op->obj()->as_register());
2330 }
2331
2332 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2333 Register len = op->len()->as_register();
2334 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2335
2336 if (UseSlowPath ||
2337 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2338 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2339 __ z_brul(*op->stub()->entry());
2340 } else {
2341 __ allocate_array(op->obj()->as_register(),
2342 op->len()->as_register(),
2343 op->tmp1()->as_register(),
2344 op->tmp2()->as_register(),
2345 arrayOopDesc::header_size(op->type()),
2346 type2aelembytes(op->type()),
2347 op->klass()->as_register(),
2348 *op->stub()->entry());
2349 }
2350 __ bind(*op->stub()->continuation());
2351 }
2352
2353 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2354 Register recv, Register tmp1, Label* update_done) {
2355 uint i;
2356 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2357 Label next_test;
2358 // See if the receiver is receiver[n].
2359 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2360 __ z_cg(recv, receiver_addr);
2361 __ z_brne(next_test);
2362 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2363 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2364 __ branch_optimized(Assembler::bcondAlways, *update_done);
2365 __ bind(next_test);
2366 }
2367
2368 // Didn't find receiver; find next empty slot and fill it in.
2369 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2370 Label next_test;
2371 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2372 __ z_ltg(Z_R0_scratch, recv_addr);
2373 __ z_brne(next_test);
2374 __ z_stg(recv, recv_addr);
2375 __ load_const_optimized(tmp1, DataLayout::counter_increment);
2376 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2377 __ branch_optimized(Assembler::bcondAlways, *update_done);
2378 __ bind(next_test);
2379 }
2380 }
2381
2382 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2383 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2384 Unimplemented();
2385 }
2386
2387 void LIR_Assembler::store_parameter(Register r, int param_num) {
2388 assert(param_num >= 0, "invalid num");
2389 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2390 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2391 __ z_stg(r, offset_in_bytes, Z_SP);
2392 }
2393
2394 void LIR_Assembler::store_parameter(jint c, int param_num) {
2395 assert(param_num >= 0, "invalid num");
2396 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2397 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2398 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2399 }
2400
2401 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2402 // We always need a stub for the failure case.
2403 CodeStub* stub = op->stub();
2404 Register obj = op->object()->as_register();
2405 Register k_RInfo = op->tmp1()->as_register();
2406 Register klass_RInfo = op->tmp2()->as_register();
2407 Register dst = op->result_opr()->as_register();
2408 Register Rtmp1 = Z_R1_scratch;
2409 ciKlass* k = op->klass();
2410
2411 assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2412
2413 // Check if it needs to be profiled.
2414 ciMethodData* md = NULL;
2415 ciProfileData* data = NULL;
2416
2417 if (op->should_profile()) {
2418 ciMethod* method = op->profiled_method();
2419 assert(method != NULL, "Should have method");
2420 int bci = op->profiled_bci();
2421 md = method->method_data_or_null();
2422 assert(md != NULL, "Sanity");
2423 data = md->bci_to_data(bci);
2424 assert(data != NULL, "need data for type check");
2425 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2426 }
2427
2428 // Temp operands do not overlap with inputs, if this is their last
2429 // use (end of range is exclusive), so a register conflict is possible.
2430 if (obj == k_RInfo) {
2431 k_RInfo = dst;
2432 } else if (obj == klass_RInfo) {
2433 klass_RInfo = dst;
2434 }
2435 assert_different_registers(obj, k_RInfo, klass_RInfo);
2436
2437 if (op->should_profile()) {
2438 NearLabel not_null;
2439 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2440 // Object is null; update MDO and exit.
2441 Register mdo = klass_RInfo;
2442 metadata2reg(md->constant_encoding(), mdo);
2443 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2444 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2445 __ or2mem_8(data_addr, header_bits);
2446 __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2447 __ bind(not_null);
2448 } else {
2449 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2450 }
2451
2452 NearLabel profile_cast_failure, profile_cast_success;
2453 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2454 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2455
2456 // Patching may screw with our temporaries on sparc,
2457 // so let's do it before loading the class.
2458 if (k->is_loaded()) {
2459 metadata2reg(k->constant_encoding(), k_RInfo);
2460 } else {
2461 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2462 }
2463 assert(obj != k_RInfo, "must be different");
2464
2465 __ verify_oop(obj);
2466
2467 // Get object class.
2468 // Not a safepoint as obj null check happens earlier.
2469 if (op->fast_check()) {
2470 if (UseCompressedClassPointers) {
2471 __ load_klass(klass_RInfo, obj);
2472 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2473 } else {
2474 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2475 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2476 }
2477 // Successful cast, fall through to profile or jump.
2478 } else {
2479 bool need_slow_path = !k->is_loaded() ||
2480 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2481 intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L;
2482 __ load_klass(klass_RInfo, obj);
2483 // Perform the fast part of the checking logic.
2484 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2485 (need_slow_path ? success_target : NULL),
2486 failure_target, NULL,
2487 RegisterOrConstant(super_check_offset));
2488 if (need_slow_path) {
2489 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2490 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2491 store_parameter(klass_RInfo, 0); // sub
2492 store_parameter(k_RInfo, 1); // super
2493 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2494 CHECK_BAILOUT();
2495 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2496 // Fall through to success case.
2497 }
2498 }
2499
2500 if (op->should_profile()) {
2501 Register mdo = klass_RInfo, recv = k_RInfo;
2502 assert_different_registers(obj, mdo, recv);
2503 __ bind(profile_cast_success);
2504 metadata2reg(md->constant_encoding(), mdo);
2505 __ load_klass(recv, obj);
2506 type_profile_helper(mdo, md, data, recv, Rtmp1, success);
2507 __ branch_optimized(Assembler::bcondAlways, *success);
2508
2509 __ bind(profile_cast_failure);
2510 metadata2reg(md->constant_encoding(), mdo);
2511 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2512 __ branch_optimized(Assembler::bcondAlways, *failure);
2513 } else {
2514 __ branch_optimized(Assembler::bcondAlways, *success);
2515 }
2516 }
2517
2518 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2519 LIR_Code code = op->code();
2520 if (code == lir_store_check) {
2521 Register value = op->object()->as_register();
2522 Register array = op->array()->as_register();
2523 Register k_RInfo = op->tmp1()->as_register();
2524 Register klass_RInfo = op->tmp2()->as_register();
2525 Register Rtmp1 = Z_R1_scratch;
2526
2527 CodeStub* stub = op->stub();
2528
2529 // Check if it needs to be profiled.
2530 ciMethodData* md = NULL;
2531 ciProfileData* data = NULL;
2532
2533 assert_different_registers(value, k_RInfo, klass_RInfo);
2534
2535 if (op->should_profile()) {
2536 ciMethod* method = op->profiled_method();
2537 assert(method != NULL, "Should have method");
2538 int bci = op->profiled_bci();
2539 md = method->method_data_or_null();
2540 assert(md != NULL, "Sanity");
2541 data = md->bci_to_data(bci);
2542 assert(data != NULL, "need data for type check");
2543 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2544 }
2545 NearLabel profile_cast_success, profile_cast_failure, done;
2546 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2547 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2548
2549 if (op->should_profile()) {
2550 NearLabel not_null;
2551 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2552 // Object is null; update MDO and exit.
2553 Register mdo = klass_RInfo;
2554 metadata2reg(md->constant_encoding(), mdo);
2555 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2556 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2557 __ or2mem_8(data_addr, header_bits);
2558 __ branch_optimized(Assembler::bcondAlways, done);
2559 __ bind(not_null);
2560 } else {
2561 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2562 }
2563
2564 add_debug_info_for_null_check_here(op->info_for_exception());
2565 __ load_klass(k_RInfo, array);
2566 __ load_klass(klass_RInfo, value);
2567
2568 // Get instance klass (it's already uncompressed).
2569 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2570 // Perform the fast part of the checking logic.
2571 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
2572 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2573 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2574 store_parameter(klass_RInfo, 0); // sub
2575 store_parameter(k_RInfo, 1); // super
2576 emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2577 CHECK_BAILOUT();
2578 __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2579 // Fall through to success case.
2580
2581 if (op->should_profile()) {
2582 Register mdo = klass_RInfo, recv = k_RInfo;
2583 assert_different_registers(value, mdo, recv);
2584 __ bind(profile_cast_success);
2585 metadata2reg(md->constant_encoding(), mdo);
2586 __ load_klass(recv, value);
2587 type_profile_helper(mdo, md, data, recv, Rtmp1, &done);
2588 __ branch_optimized(Assembler::bcondAlways, done);
2589
2590 __ bind(profile_cast_failure);
2591 metadata2reg(md->constant_encoding(), mdo);
2592 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2593 __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2594 }
2595
2596 __ bind(done);
2597 } else {
2598 if (code == lir_checkcast) {
2599 Register obj = op->object()->as_register();
2600 Register dst = op->result_opr()->as_register();
2601 NearLabel success;
2602 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2603 __ bind(success);
2604 __ lgr_if_needed(dst, obj);
2605 } else {
2606 if (code == lir_instanceof) {
2607 Register obj = op->object()->as_register();
2608 Register dst = op->result_opr()->as_register();
2609 NearLabel success, failure, done;
2610 emit_typecheck_helper(op, &success, &failure, &failure);
2611 __ bind(failure);
2612 __ clear_reg(dst);
2613 __ branch_optimized(Assembler::bcondAlways, done);
2614 __ bind(success);
2615 __ load_const_optimized(dst, 1);
2616 __ bind(done);
2617 } else {
2618 ShouldNotReachHere();
2619 }
2620 }
2621 }
2622 }
2623
2624 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2625 Register addr = op->addr()->as_pointer_register();
2626 Register t1_cmp = Z_R1_scratch;
2627 if (op->code() == lir_cas_long) {
2628 assert(VM_Version::supports_cx8(), "wrong machine");
2629 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2630 Register new_value_lo = op->new_value()->as_register_lo();
2631 __ z_lgr(t1_cmp, cmp_value_lo);
2632 // Perform the compare and swap operation.
2633 __ z_csg(t1_cmp, new_value_lo, 0, addr);
2634 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2635 Register cmp_value = op->cmp_value()->as_register();
2636 Register new_value = op->new_value()->as_register();
2637 if (op->code() == lir_cas_obj) {
2638 if (UseCompressedOops) {
2639 t1_cmp = op->tmp1()->as_register();
2640 Register t2_new = op->tmp2()->as_register();
2641 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2642 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2643 __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2644 __ z_cs(t1_cmp, t2_new, 0, addr);
2645 } else {
2646 __ z_lgr(t1_cmp, cmp_value);
2647 __ z_csg(t1_cmp, new_value, 0, addr);
2648 }
2649 } else {
2650 __ z_lr(t1_cmp, cmp_value);
2651 __ z_cs(t1_cmp, new_value, 0, addr);
2652 }
2653 } else {
2654 ShouldNotReachHere(); // new lir_cas_??
2655 }
2656 }
2657
2658 void LIR_Assembler::set_24bit_FPU() {
2659 ShouldNotCallThis(); // x86 only
2660 }
2661
2662 void LIR_Assembler::reset_FPU() {
2663 ShouldNotCallThis(); // x86 only
2664 }
2665
2666 void LIR_Assembler::breakpoint() {
2667 Unimplemented();
2668 // __ breakpoint_trap();
2669 }
2670
2671 void LIR_Assembler::push(LIR_Opr opr) {
2672 ShouldNotCallThis(); // unused
2673 }
2674
2675 void LIR_Assembler::pop(LIR_Opr opr) {
2676 ShouldNotCallThis(); // unused
2677 }
2678
2679 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2680 Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2681 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2682 }
2683
2684 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2685 Register obj = op->obj_opr()->as_register(); // May not be an oop.
2686 Register hdr = op->hdr_opr()->as_register();
2687 Register lock = op->lock_opr()->as_register();
2688 if (!UseFastLocking) {
2689 __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry());
2690 } else if (op->code() == lir_lock) {
2691 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2692 // Add debug info for NullPointerException only if one is possible.
2693 if (op->info() != NULL) {
2694 add_debug_info_for_null_check_here(op->info());
2695 }
2696 __ lock_object(hdr, obj, lock, *op->stub()->entry());
2697 // done
2698 } else if (op->code() == lir_unlock) {
2699 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2700 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2701 } else {
2702 ShouldNotReachHere();
2703 }
2704 __ bind(*op->stub()->continuation());
2705 }
2706
2707 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2708 ciMethod* method = op->profiled_method();
2709 int bci = op->profiled_bci();
2710 ciMethod* callee = op->profiled_callee();
2711
2712 // Update counter for all call types.
2713 ciMethodData* md = method->method_data_or_null();
2714 assert(md != NULL, "Sanity");
2715 ciProfileData* data = md->bci_to_data(bci);
2716 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2717 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2718 Register mdo = op->mdo()->as_register();
2719 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2720 Register tmp1 = op->tmp1()->as_register_lo();
2721 metadata2reg(md->constant_encoding(), mdo);
2722
2723 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2724 // Perform additional virtual call profiling for invokevirtual and
2725 // invokeinterface bytecodes
2726 if (op->should_profile_receiver_type()) {
2727 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2728 Register recv = op->recv()->as_register();
2729 assert_different_registers(mdo, tmp1, recv);
2730 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2731 ciKlass* known_klass = op->known_holder();
2732 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2733 // We know the type that will be seen at this call site; we can
2734 // statically update the MethodData* rather than needing to do
2735 // dynamic tests on the receiver type.
2736
2737 // NOTE: we should probably put a lock around this search to
2738 // avoid collisions by concurrent compilations.
2739 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2740 uint i;
2741 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2742 ciKlass* receiver = vc_data->receiver(i);
2743 if (known_klass->equals(receiver)) {
2744 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2745 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2746 return;
2747 }
2748 }
2749
2750 // Receiver type not found in profile data. Select an empty slot.
2751
2752 // Note that this is less efficient than it should be because it
2753 // always does a write to the receiver part of the
2754 // VirtualCallData rather than just the first time.
2755 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2756 ciKlass* receiver = vc_data->receiver(i);
2757 if (receiver == NULL) {
2758 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2759 metadata2reg(known_klass->constant_encoding(), tmp1);
2760 __ z_stg(tmp1, recv_addr);
2761 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2762 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2763 return;
2764 }
2765 }
2766 } else {
2767 __ load_klass(recv, recv);
2768 NearLabel update_done;
2769 type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2770 // Receiver did not match any saved receiver and there is no empty row for it.
2771 // Increment total counter to indicate polymorphic case.
2772 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2773 __ bind(update_done);
2774 }
2775 } else {
2776 // static call
2777 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2778 }
2779 }
2780
2781 void LIR_Assembler::align_backward_branch_target() {
2782 __ align(OptoLoopAlignment);
2783 }
2784
2785 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2786 ShouldNotCallThis(); // There are no delay slots on ZARCH_64.
2787 }
2788
2789 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2790 assert(left->is_register(), "can only handle registers");
2791
2792 if (left->is_single_cpu()) {
2793 __ z_lcr(dest->as_register(), left->as_register());
2794 } else if (left->is_single_fpu()) {
2795 __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2796 } else if (left->is_double_fpu()) {
2797 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2798 } else {
2799 assert(left->is_double_cpu(), "Must be a long");
2800 __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2801 }
2802 }
2803
2804 void LIR_Assembler::fxch(int i) {
2805 ShouldNotCallThis(); // x86 only
2806 }
2807
2808 void LIR_Assembler::fld(int i) {
2809 ShouldNotCallThis(); // x86 only
2810 }
2811
2812 void LIR_Assembler::ffree(int i) {
2813 ShouldNotCallThis(); // x86 only
2814 }
2815
2816 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2817 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2818 assert(!tmp->is_valid(), "don't need temporary");
2819 emit_call_c(dest);
2820 CHECK_BAILOUT();
2821 if (info != NULL) {
2822 add_call_info_here(info);
2823 }
2824 }
2825
2826 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2827 ShouldNotCallThis(); // not needed on ZARCH_64
2828 }
2829
2830 void LIR_Assembler::membar() {
2831 __ z_fence();
2832 }
2833
2834 void LIR_Assembler::membar_acquire() {
2835 __ z_acquire();
2836 }
2837
2838 void LIR_Assembler::membar_release() {
2839 __ z_release();
2840 }
2841
2842 void LIR_Assembler::membar_loadload() {
2843 __ z_acquire();
2844 }
2845
2846 void LIR_Assembler::membar_storestore() {
2847 __ z_release();
2848 }
2849
2850 void LIR_Assembler::membar_loadstore() {
2851 __ z_acquire();
2852 }
2853
2854 void LIR_Assembler::membar_storeload() {
2855 __ z_fence();
2856 }
2857
2858 void LIR_Assembler::on_spin_wait() {
2859 Unimplemented();
2860 }
2861
2862 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
2863 LIR_Address* addr = addr_opr->as_address_ptr();
2864 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2865 __ load_address(dest->as_pointer_register(), as_Address(addr));
2866 }
2867
2868 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2869 ShouldNotCallThis(); // unused
2870 }
2871
2872 #ifdef ASSERT
2873 // Emit run-time assertion.
2874 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2875 Unimplemented();
2876 }
2877 #endif
2878
2879 void LIR_Assembler::peephole(LIR_List*) {
2880 // Do nothing for now.
2881 }
2882
2883 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2884 assert(code == lir_xadd, "lir_xchg not supported");
2885 Address src_addr = as_Address(src->as_address_ptr());
2886 Register base = src_addr.base();
2887 intptr_t disp = src_addr.disp();
2888 if (src_addr.index()->is_valid()) {
2889 // LAA and LAAG do not support index register.
2890 __ load_address(Z_R1_scratch, src_addr);
2891 base = Z_R1_scratch;
2892 disp = 0;
2893 }
2894 if (data->type() == T_INT) {
2895 __ z_laa(dest->as_register(), data->as_register(), disp, base);
2896 } else if (data->type() == T_LONG) {
2897 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2898 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2899 } else {
2900 ShouldNotReachHere();
2901 }
2902 }
2903
2904 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2905 Register obj = op->obj()->as_register();
2906 Register tmp1 = op->tmp()->as_pointer_register();
2907 Register tmp2 = Z_R1_scratch;
2908 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2909 ciKlass* exact_klass = op->exact_klass();
2910 intptr_t current_klass = op->current_klass();
2911 bool not_null = op->not_null();
2912 bool no_conflict = op->no_conflict();
2913
2914 Label update, next, none, null_seen, init_klass;
2915
2916 bool do_null = !not_null;
2917 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2918 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2919
2920 assert(do_null || do_update, "why are we here?");
2921 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2922
2923 __ verify_oop(obj);
2924
2925 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2926 __ z_ltgr(tmp1, obj);
2927 }
2928 if (do_null) {
2929 __ z_brnz(update);
2930 if (!TypeEntries::was_null_seen(current_klass)) {
2931 __ z_lg(tmp1, mdo_addr);
2932 __ z_oill(tmp1, TypeEntries::null_seen);
2933 __ z_stg(tmp1, mdo_addr);
2934 }
2935 if (do_update) {
2936 __ z_bru(next);
2937 }
2938 } else {
2939 __ asm_assert_ne("unexpect null obj", __LINE__);
2940 }
2941
2942 __ bind(update);
2943
2944 if (do_update) {
2945 #ifdef ASSERT
2946 if (exact_klass != NULL) {
2947 __ load_klass(tmp1, tmp1);
2948 metadata2reg(exact_klass->constant_encoding(), tmp2);
2949 __ z_cgr(tmp1, tmp2);
2950 __ asm_assert_eq("exact klass and actual klass differ", __LINE__);
2951 }
2952 #endif
2953
2954 Label do_update;
2955 __ z_lg(tmp2, mdo_addr);
2956
2957 if (!no_conflict) {
2958 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2959 if (exact_klass != NULL) {
2960 metadata2reg(exact_klass->constant_encoding(), tmp1);
2961 } else {
2962 __ load_klass(tmp1, tmp1);
2963 }
2964
2965 // Klass seen before: nothing to do (regardless of unknown bit).
2966 __ z_lgr(Z_R0_scratch, tmp2);
2967 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
2968 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
2969 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
2970
2971 // Already unknown: Nothing to do anymore.
2972 __ z_tmll(tmp2, TypeEntries::type_unknown);
2973 __ z_brc(Assembler::bcondAllOne, next);
2974
2975 if (TypeEntries::is_type_none(current_klass)) {
2976 __ z_lgr(Z_R0_scratch, tmp2);
2977 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
2978 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
2979 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
2980 }
2981 } else {
2982 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2983 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2984
2985 // Already unknown: Nothing to do anymore.
2986 __ z_tmll(tmp2, TypeEntries::type_unknown);
2987 __ z_brc(Assembler::bcondAllOne, next);
2988 }
2989
2990 // Different than before. Cannot keep accurate profile.
2991 __ z_oill(tmp2, TypeEntries::type_unknown);
2992 __ z_bru(do_update);
2993 } else {
2994 // There's a single possible klass at this profile point.
2995 assert(exact_klass != NULL, "should be");
2996 if (TypeEntries::is_type_none(current_klass)) {
2997 metadata2reg(exact_klass->constant_encoding(), tmp1);
2998 __ z_lgr(Z_R0_scratch, tmp2);
2999 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3000 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3001 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3002 #ifdef ASSERT
3003 {
3004 Label ok;
3005 __ z_lgr(Z_R0_scratch, tmp2);
3006 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3007 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3008 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
3009 __ stop("unexpected profiling mismatch");
3010 __ bind(ok);
3011 }
3012 #endif
3013
3014 } else {
3015 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3016 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3017
3018 // Already unknown: Nothing to do anymore.
3019 __ z_tmll(tmp2, TypeEntries::type_unknown);
3020 __ z_brc(Assembler::bcondAllOne, next);
3021 __ z_oill(tmp2, TypeEntries::type_unknown);
3022 __ z_bru(do_update);
3023 }
3024 }
3025
3026 __ bind(init_klass);
3027 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3028 __ z_ogr(tmp2, tmp1);
3029
3030 __ bind(do_update);
3031 __ z_stg(tmp2, mdo_addr);
3032
3033 __ bind(next);
3034 }
3035 }
3036
3037 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3038 assert(op->crc()->is_single_cpu(), "crc must be register");
3039 assert(op->val()->is_single_cpu(), "byte value must be register");
3040 assert(op->result_opr()->is_single_cpu(), "result must be register");
3041 Register crc = op->crc()->as_register();
3042 Register val = op->val()->as_register();
3043 Register res = op->result_opr()->as_register();
3044
3045 assert_different_registers(val, crc, res);
3046
3047 __ load_const_optimized(res, StubRoutines::crc_table_addr());
3048 __ kernel_crc32_singleByteReg(crc, val, res, true);
3049 __ z_lgfr(res, crc);
3050 }
3051
3052 #undef __