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src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp

BarrierSetC1_v2

9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or                                                             
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License                                                             
11  * version 2 for more details (a copy is included in the LICENSE file that                                                           
12  * accompanied this code).                                                                                                           
13  *                                                                                                                                   
14  * You should have received a copy of the GNU General Public License version                                                         
15  * 2 along with this work; if not, write to the Free Software Foundation,                                                            
16  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.                                                                     
17  *                                                                                                                                   
18  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA                                                           
19  * or visit www.oracle.com if you need additional information or have any                                                            
20  * questions.                                                                                                                        
21  *                                                                                                                                   
22  */                                                                                                                                  
23 
24 #ifndef CPU_AARCH64_GC_G1_G1BARRIERSETASSEMBLER_AARCH64_HPP                                                                          
25 #define CPU_AARCH64_GC_G1_G1BARRIERSETASSEMBLER_AARCH64_HPP                                                                          
26 
27 #include "asm/macroAssembler.hpp"                                                                                                    
28 #include "gc/shared/modRefBarrierSetAssembler.hpp"                                                                                   
                                                                                                                                     
29 
30 class LIR_Assembler;                                                                                                                 
31 class StubAssembler;                                                                                                                 
32 class G1PreBarrierStub;                                                                                                              
33 class G1PostBarrierStub;                                                                                                             
34 
35 class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {                                                                      
36 protected:                                                                                                                           
37   void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators,                                                
38                                        Register addr, Register count, RegSet saved_regs);                                            
39   void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,                                               
40                                         Register start, Register end, Register tmp, RegSet saved_regs);                              
41 
42   void g1_write_barrier_pre(MacroAssembler* masm,                                                                                    
43                             Register obj,                                                                                            
44                             Register pre_val,                                                                                        
45                             Register thread,                                                                                         
46                             Register tmp,                                                                                            
47                             bool tosca_live,                                                                                         
48                             bool expand_call);                                                                                       
49 
50   void g1_write_barrier_post(MacroAssembler* masm,                                                                                   
51                              Register store_addr,                                                                                    
52                              Register new_val,                                                                                       
53                              Register thread,                                                                                        
54                              Register tmp,                                                                                           
55                              Register tmp2);                                                                                         
56 
57   virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,                                           
58                             Address dst, Register val, Register tmp1, Register tmp2);                                                
59 
60 public:                                                                                                                              
                                                                                                                                     
61   void gen_g1_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub);                                                           
62   void gen_g1_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub);                                                         
63 
64   void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm);                                                                    
65   void generate_c1_post_barrier_runtime_stub(StubAssembler* sasm);                                                                   
                                                                                                                                     
66 
67   void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,                                                        
68                Register dst, Address src, Register tmp1, Register tmp_thread);                                                       
69 };                                                                                                                                   
70 
71 #endif // CPU_AARCH64_GC_G1_G1BARRIERSETASSEMBLER_AARCH64_HPP                                                                        

9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
11  * version 2 for more details (a copy is included in the LICENSE file that
12  * accompanied this code).
13  *
14  * You should have received a copy of the GNU General Public License version
15  * 2 along with this work; if not, write to the Free Software Foundation,
16  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
19  * or visit www.oracle.com if you need additional information or have any
20  * questions.
21  *
22  */
23 
24 #ifndef CPU_AARCH64_GC_G1_G1BARRIERSETASSEMBLER_AARCH64_HPP
25 #define CPU_AARCH64_GC_G1_G1BARRIERSETASSEMBLER_AARCH64_HPP
26 
27 #include "asm/macroAssembler.hpp"
28 #include "gc/shared/modRefBarrierSetAssembler.hpp"
29 #include "utilities/macros.hpp"
30 
31 class LIR_Assembler;
32 class StubAssembler;
33 class G1PreBarrierStub;
34 class G1PostBarrierStub;
35 
36 class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
37 protected:
38   void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators,
39                                        Register addr, Register count, RegSet saved_regs);
40   void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators,
41                                         Register start, Register end, Register tmp, RegSet saved_regs);
42 
43   void g1_write_barrier_pre(MacroAssembler* masm,
44                             Register obj,
45                             Register pre_val,
46                             Register thread,
47                             Register tmp,
48                             bool tosca_live,
49                             bool expand_call);
50 
51   void g1_write_barrier_post(MacroAssembler* masm,
52                              Register store_addr,
53                              Register new_val,
54                              Register thread,
55                              Register tmp,
56                              Register tmp2);
57 
58   virtual void oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
59                             Address dst, Register val, Register tmp1, Register tmp2);
60 
61 public:
62 #ifdef COMPILER1
63   void gen_g1_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub);
64   void gen_g1_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub);
65 
66   void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm);
67   void generate_c1_post_barrier_runtime_stub(StubAssembler* sasm);
68 #endif
69 
70   void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
71                Register dst, Address src, Register tmp1, Register tmp_thread);
72 };
73 
74 #endif // CPU_AARCH64_GC_G1_G1BARRIERSETASSEMBLER_AARCH64_HPP
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