1 /* 2 * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_ARM_GC_G1_G1BARRIERSETASSEMBLER_ARM_HPP 26 #define CPU_ARM_GC_G1_G1BARRIERSETASSEMBLER_ARM_HPP 27 28 #include "asm/macroAssembler.hpp" 29 #include "gc/shared/modRefBarrierSetAssembler.hpp" 30 31 class LIR_Assembler; 32 class StubAssembler; 33 class G1PreBarrierStub; 34 class G1PostBarrierStub; 35 36 class G1BarrierSetAssembler: public ModRefBarrierSetAssembler { 37 protected: 38 void gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, 39 Register addr, Register count, int callee_saved_regs); 40 void gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, 41 Register addr, Register count, Register tmp); 42 43 void gen_g1_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub); 44 void gen_g1_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub); 45 46 void generate_c1_pre_barrier_runtime_stub(StubAssembler* sasm); 47 void generate_c1_post_barrier_runtime_stub(StubAssembler* sasm); 48 }; 49 50 #endif // CPU_ARM_GC_G1_G1BARRIERSETASSEMBLER_ARM_HPP