8203344: Make C1 leal patchable on SPARC
3183 __ or3(rs, rs->successor(), rd);
3184 }
3185
3186 // Unpack a 64 bit value in a register into
3187 // two sequential registers.
3188 // src is unpacked into dst and dst->successor()
3189 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3190 Register rs = src->as_register_lo();
3191 Register rd = dst->as_register_hi();
3192 assert_different_registers(rs, rd, rd->successor());
3193 __ srlx(rs, 32, rd);
3194 __ srl (rs, 0, rd->successor());
3195 }
3196
3197 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3198 const LIR_Address* addr = addr_opr->as_address_ptr();
3199 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3200 const Register dest_reg = dest->as_pointer_register();
3201 const Register base_reg = addr->base()->as_pointer_register();
3202
3203 if (Assembler::is_simm13(addr->disp())) {
3204 if (addr->index()->is_valid()) {
3205 const Register index_reg = addr->index()->as_pointer_register();
3206 assert(index_reg != G3_scratch, "invariant");
3207 __ add(base_reg, addr->disp(), G3_scratch);
3208 __ add(index_reg, G3_scratch, dest_reg);
3209 } else {
3210 __ add(base_reg, addr->disp(), dest_reg);
3211 }
3212 } else {
3213 __ set(addr->disp(), G3_scratch);
3214 if (addr->index()->is_valid()) {
3215 const Register index_reg = addr->index()->as_pointer_register();
3216 assert(index_reg != G3_scratch, "invariant");
3217 __ add(index_reg, G3_scratch, G3_scratch);
3218 }
3219 __ add(base_reg, G3_scratch, dest_reg);
3220 }
3221 }
3222
3223
3224 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3225 assert(result_reg->is_register(), "check");
3226 __ mov(G2_thread, result_reg->as_register());
3227 }
3228
3229 #ifdef ASSERT
3230 // emit run-time assertion
3231 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3232 assert(op->code() == lir_assert, "must be");
3233
3234 if (op->in_opr1()->is_valid()) {
3235 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3236 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3237 } else {
3238 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
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3183 __ or3(rs, rs->successor(), rd);
3184 }
3185
3186 // Unpack a 64 bit value in a register into
3187 // two sequential registers.
3188 // src is unpacked into dst and dst->successor()
3189 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3190 Register rs = src->as_register_lo();
3191 Register rd = dst->as_register_hi();
3192 assert_different_registers(rs, rd, rd->successor());
3193 __ srlx(rs, 32, rd);
3194 __ srl (rs, 0, rd->successor());
3195 }
3196
3197 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3198 const LIR_Address* addr = addr_opr->as_address_ptr();
3199 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3200 const Register dest_reg = dest->as_pointer_register();
3201 const Register base_reg = addr->base()->as_pointer_register();
3202
3203 if (patch_code != lir_patch_none) {
3204 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3205 assert(addr->disp() != 0, "must have");
3206 assert(base_reg != G3_scratch, "invariant");
3207 __ patchable_set(0, G3_scratch);
3208 patching_epilog(patch, patch_code, base_reg, info);
3209 assert(dest_reg != G3_scratch, "invariant");
3210 if (addr->index()->is_valid()) {
3211 const Register index_reg = addr->index()->as_pointer_register();
3212 assert(index_reg != G3_scratch, "invariant");
3213 __ add(index_reg, G3_scratch, G3_scratch);
3214 }
3215 __ add(base_reg, G3_scratch, dest_reg);
3216 } else {
3217 if (Assembler::is_simm13(addr->disp())) {
3218 if (addr->index()->is_valid()) {
3219 const Register index_reg = addr->index()->as_pointer_register();
3220 assert(index_reg != G3_scratch, "invariant");
3221 __ add(base_reg, addr->disp(), G3_scratch);
3222 __ add(index_reg, G3_scratch, dest_reg);
3223 } else {
3224 __ add(base_reg, addr->disp(), dest_reg);
3225 }
3226 } else {
3227 __ set(addr->disp(), G3_scratch);
3228 if (addr->index()->is_valid()) {
3229 const Register index_reg = addr->index()->as_pointer_register();
3230 assert(index_reg != G3_scratch, "invariant");
3231 __ add(index_reg, G3_scratch, G3_scratch);
3232 }
3233 __ add(base_reg, G3_scratch, dest_reg);
3234 }
3235 }
3236 }
3237
3238
3239 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3240 assert(result_reg->is_register(), "check");
3241 __ mov(G2_thread, result_reg->as_register());
3242 }
3243
3244 #ifdef ASSERT
3245 // emit run-time assertion
3246 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3247 assert(op->code() == lir_assert, "must be");
3248
3249 if (op->in_opr1()->is_valid()) {
3250 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3251 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3252 } else {
3253 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
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