1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableBarrierSet.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/interfaceSupport.inline.hpp"
40 #include "runtime/jniHandles.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 #define __ _masm->
45
46
47 //------------------------------------------------------------
48
49
50 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
51 if (opr->is_constant()) {
52 LIR_Const* constant = opr->as_constant_ptr();
53 switch (constant->type()) {
54 case T_INT: {
55 jint value = constant->as_jint();
56 return Assembler::is_simm13(value);
57 }
58
59 default:
60 return false;
61 }
62 }
63 return false;
64 }
65
66
67 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
68 switch (op->code()) {
69 case lir_null_check:
70 return true;
71
72
73 case lir_add:
74 case lir_ushr:
75 case lir_shr:
76 case lir_shl:
77 // integer shifts and adds are always one instruction
78 return op->result_opr()->is_single_cpu();
79
80
81 case lir_move: {
82 LIR_Op1* op1 = op->as_Op1();
83 LIR_Opr src = op1->in_opr();
84 LIR_Opr dst = op1->result_opr();
85
86 if (src == dst) {
87 NEEDS_CLEANUP;
88 // this works around a problem where moves with the same src and dst
89 // end up in the delay slot and then the assembler swallows the mov
90 // since it has no effect and then it complains because the delay slot
91 // is empty. returning false stops the optimizer from putting this in
92 // the delay slot
93 return false;
94 }
95
96 // don't put moves involving oops into the delay slot since the VerifyOops code
97 // will make it much larger than a single instruction.
98 if (VerifyOops) {
99 return false;
100 }
101
102 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
103 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
104 return false;
105 }
106
107 if (UseCompressedOops) {
108 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
109 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
110 }
111
112 if (UseCompressedClassPointers) {
113 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
114 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
115 }
116
117 if (dst->is_register()) {
118 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
119 return !PatchALot;
120 } else if (src->is_single_stack()) {
121 return true;
122 }
123 }
124
125 if (src->is_register()) {
126 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
127 return !PatchALot;
128 } else if (dst->is_single_stack()) {
129 return true;
130 }
131 }
132
133 if (dst->is_register() &&
134 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
135 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
136 return true;
137 }
138
139 return false;
140 }
141
142 default:
143 return false;
144 }
145 ShouldNotReachHere();
146 }
147
148
149 LIR_Opr LIR_Assembler::receiverOpr() {
150 return FrameMap::O0_oop_opr;
151 }
152
153
154 LIR_Opr LIR_Assembler::osrBufferPointer() {
155 return FrameMap::I0_opr;
156 }
157
158
159 int LIR_Assembler::initial_frame_size_in_bytes() const {
160 return in_bytes(frame_map()->framesize_in_bytes());
161 }
162
163
164 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
165 // we fetch the class of the receiver (O0) and compare it with the cached class.
166 // If they do not match we jump to slow case.
167 int LIR_Assembler::check_icache() {
168 int offset = __ offset();
169 __ inline_cache_check(O0, G5_inline_cache_reg);
170 return offset;
171 }
172
173
174 void LIR_Assembler::osr_entry() {
175 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
176 //
177 // 1. Create a new compiled activation.
178 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
179 // at the osr_bci; it is not initialized.
180 // 3. Jump to the continuation address in compiled code to resume execution.
181
182 // OSR entry point
183 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
184 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
185 ValueStack* entry_state = osr_entry->end()->state();
186 int number_of_locks = entry_state->locks_size();
187
188 // Create a frame for the compiled activation.
189 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
190
191 // OSR buffer is
192 //
193 // locals[nlocals-1..0]
194 // monitors[number_of_locks-1..0]
195 //
196 // locals is a direct copy of the interpreter frame so in the osr buffer
197 // so first slot in the local array is the last local from the interpreter
198 // and last slot is local[0] (receiver) from the interpreter
199 //
200 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
201 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
202 // in the interpreter frame (the method lock if a sync method)
203
204 // Initialize monitors in the compiled activation.
205 // I0: pointer to osr buffer
206 //
207 // All other registers are dead at this point and the locals will be
208 // copied into place by code emitted in the IR.
209
210 Register OSR_buf = osrBufferPointer()->as_register();
211 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
212 int monitor_offset = BytesPerWord * method()->max_locals() +
213 (2 * BytesPerWord) * (number_of_locks - 1);
214 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
215 // the OSR buffer using 2 word entries: first the lock and then
216 // the oop.
217 for (int i = 0; i < number_of_locks; i++) {
218 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
219 #ifdef ASSERT
220 // verify the interpreter's monitor has a non-null object
221 {
222 Label L;
223 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
224 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
225 __ stop("locked object is NULL");
226 __ bind(L);
227 }
228 #endif // ASSERT
229 // Copy the lock field into the compiled activation.
230 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
231 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
232 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
233 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
234 }
235 }
236 }
237
238
239 // --------------------------------------------------------------------------------------------
240
241 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
242 if (!GenerateSynchronizationCode) return;
243
244 Register obj_reg = obj_opr->as_register();
245 Register lock_reg = lock_opr->as_register();
246
247 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
248 Register reg = mon_addr.base();
249 int offset = mon_addr.disp();
250 // compute pointer to BasicLock
251 if (mon_addr.is_simm13()) {
252 __ add(reg, offset, lock_reg);
253 }
254 else {
255 __ set(offset, lock_reg);
256 __ add(reg, lock_reg, lock_reg);
257 }
258 // unlock object
259 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
260 // _slow_case_stubs->append(slow_case);
261 // temporary fix: must be created after exceptionhandler, therefore as call stub
262 _slow_case_stubs->append(slow_case);
263 if (UseFastLocking) {
264 // try inlined fast unlocking first, revert to slow locking if it fails
265 // note: lock_reg points to the displaced header since the displaced header offset is 0!
266 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
267 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
268 } else {
269 // always do slow unlocking
270 // note: the slow unlocking code could be inlined here, however if we use
271 // slow unlocking, speed doesn't matter anyway and this solution is
272 // simpler and requires less duplicated code - additionally, the
273 // slow unlocking code is the same in either case which simplifies
274 // debugging
275 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
276 __ delayed()->nop();
277 }
278 // done
279 __ bind(*slow_case->continuation());
280 }
281
282
283 int LIR_Assembler::emit_exception_handler() {
284 // if the last instruction is a call (typically to do a throw which
285 // is coming at the end after block reordering) the return address
286 // must still point into the code area in order to avoid assertion
287 // failures when searching for the corresponding bci => add a nop
288 // (was bug 5/14/1999 - gri)
289 __ nop();
290
291 // generate code for exception handler
292 ciMethod* method = compilation()->method();
293
294 address handler_base = __ start_a_stub(exception_handler_size());
295
296 if (handler_base == NULL) {
297 // not enough space left for the handler
298 bailout("exception handler overflow");
299 return -1;
300 }
301
302 int offset = code_offset();
303
304 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
305 __ delayed()->nop();
306 __ should_not_reach_here();
307 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
308 __ end_a_stub();
309
310 return offset;
311 }
312
313
314 // Emit the code to remove the frame from the stack in the exception
315 // unwind path.
316 int LIR_Assembler::emit_unwind_handler() {
317 #ifndef PRODUCT
318 if (CommentedAssembly) {
319 _masm->block_comment("Unwind handler");
320 }
321 #endif
322
323 int offset = code_offset();
324
325 // Fetch the exception from TLS and clear out exception related thread state
326 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
327 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
328 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
329
330 __ bind(_unwind_handler_entry);
331 __ verify_not_null_oop(O0);
332 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
333 __ mov(O0, I0); // Preserve the exception
334 }
335
336 // Preform needed unlocking
337 MonitorExitStub* stub = NULL;
338 if (method()->is_synchronized()) {
339 monitor_address(0, FrameMap::I1_opr);
340 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
341 __ unlock_object(I3, I2, I1, *stub->entry());
342 __ bind(*stub->continuation());
343 }
344
345 if (compilation()->env()->dtrace_method_probes()) {
346 __ mov(G2_thread, O0);
347 __ save_thread(I1); // need to preserve thread in G2 across
348 // runtime call
349 metadata2reg(method()->constant_encoding(), O1);
350 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
351 __ delayed()->nop();
352 __ restore_thread(I1);
353 }
354
355 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
356 __ mov(I0, O0); // Restore the exception
357 }
358
359 // dispatch to the unwind logic
360 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
361 __ delayed()->nop();
362
363 // Emit the slow path assembly
364 if (stub != NULL) {
365 stub->emit_code(this);
366 }
367
368 return offset;
369 }
370
371
372 int LIR_Assembler::emit_deopt_handler() {
373 // if the last instruction is a call (typically to do a throw which
374 // is coming at the end after block reordering) the return address
375 // must still point into the code area in order to avoid assertion
376 // failures when searching for the corresponding bci => add a nop
377 // (was bug 5/14/1999 - gri)
378 __ nop();
379
380 // generate code for deopt handler
381 ciMethod* method = compilation()->method();
382 address handler_base = __ start_a_stub(deopt_handler_size());
383 if (handler_base == NULL) {
384 // not enough space left for the handler
385 bailout("deopt handler overflow");
386 return -1;
387 }
388
389 int offset = code_offset();
390 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
391 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
392 __ delayed()->nop();
393 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
394 __ end_a_stub();
395
396 return offset;
397 }
398
399
400 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
401 if (o == NULL) {
402 __ set(NULL_WORD, reg);
403 } else {
404 #ifdef ASSERT
405 {
406 ThreadInVMfromNative tiv(JavaThread::current());
407 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
408 }
409 #endif
410 int oop_index = __ oop_recorder()->find_index(o);
411 RelocationHolder rspec = oop_Relocation::spec(oop_index);
412 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
413 }
414 }
415
416
417 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
418 // Allocate a new index in table to hold the object once it's been patched
419 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
420 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
421
422 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
423 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
424 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
425 // NULL will be dynamically patched later and the patched value may be large. We must
426 // therefore generate the sethi/add as a placeholders
427 __ patchable_set(addrlit, reg);
428
429 patching_epilog(patch, lir_patch_normal, reg, info);
430 }
431
432
433 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
434 __ set_metadata_constant(o, reg);
435 }
436
437 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
438 // Allocate a new index in table to hold the klass once it's been patched
439 int index = __ oop_recorder()->allocate_metadata_index(NULL);
440 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
441 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
442 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
443 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
444 // NULL will be dynamically patched later and the patched value may be large. We must
445 // therefore generate the sethi/add as a placeholders
446 __ patchable_set(addrlit, reg);
447
448 patching_epilog(patch, lir_patch_normal, reg, info);
449 }
450
451 void LIR_Assembler::emit_op3(LIR_Op3* op) {
452 switch (op->code()) {
453 case lir_idiv:
454 case lir_irem: // Both idiv & irem are handled after the switch (below).
455 break;
456 case lir_fmaf:
457 __ fmadd(FloatRegisterImpl::S,
458 op->in_opr1()->as_float_reg(),
459 op->in_opr2()->as_float_reg(),
460 op->in_opr3()->as_float_reg(),
461 op->result_opr()->as_float_reg());
462 return;
463 case lir_fmad:
464 __ fmadd(FloatRegisterImpl::D,
465 op->in_opr1()->as_double_reg(),
466 op->in_opr2()->as_double_reg(),
467 op->in_opr3()->as_double_reg(),
468 op->result_opr()->as_double_reg());
469 return;
470 default:
471 ShouldNotReachHere();
472 break;
473 }
474
475 // Handle idiv & irem:
476
477 Register Rdividend = op->in_opr1()->as_register();
478 Register Rdivisor = noreg;
479 Register Rscratch = op->in_opr3()->as_register();
480 Register Rresult = op->result_opr()->as_register();
481 int divisor = -1;
482
483 if (op->in_opr2()->is_register()) {
484 Rdivisor = op->in_opr2()->as_register();
485 } else {
486 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
487 assert(Assembler::is_simm13(divisor), "can only handle simm13");
488 }
489
490 assert(Rdividend != Rscratch, "");
491 assert(Rdivisor != Rscratch, "");
492 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
493
494 if (Rdivisor == noreg && is_power_of_2(divisor)) {
495 // convert division by a power of two into some shifts and logical operations
496 if (op->code() == lir_idiv) {
497 if (divisor == 2) {
498 __ srl(Rdividend, 31, Rscratch);
499 } else {
500 __ sra(Rdividend, 31, Rscratch);
501 __ and3(Rscratch, divisor - 1, Rscratch);
502 }
503 __ add(Rdividend, Rscratch, Rscratch);
504 __ sra(Rscratch, log2_intptr(divisor), Rresult);
505 return;
506 } else {
507 if (divisor == 2) {
508 __ srl(Rdividend, 31, Rscratch);
509 } else {
510 __ sra(Rdividend, 31, Rscratch);
511 __ and3(Rscratch, divisor - 1,Rscratch);
512 }
513 __ add(Rdividend, Rscratch, Rscratch);
514 __ andn(Rscratch, divisor - 1,Rscratch);
515 __ sub(Rdividend, Rscratch, Rresult);
516 return;
517 }
518 }
519
520 __ sra(Rdividend, 31, Rscratch);
521 __ wry(Rscratch);
522
523 add_debug_info_for_div0_here(op->info());
524
525 if (Rdivisor != noreg) {
526 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
527 } else {
528 assert(Assembler::is_simm13(divisor), "can only handle simm13");
529 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
530 }
531
532 Label skip;
533 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
534 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
535 __ bind(skip);
536
537 if (op->code() == lir_irem) {
538 if (Rdivisor != noreg) {
539 __ smul(Rscratch, Rdivisor, Rscratch);
540 } else {
541 __ smul(Rscratch, divisor, Rscratch);
542 }
543 __ sub(Rdividend, Rscratch, Rresult);
544 }
545 }
546
547
548 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
549 #ifdef ASSERT
550 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
551 if (op->block() != NULL) _branch_target_blocks.append(op->block());
552 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
553 #endif
554 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
555
556 if (op->cond() == lir_cond_always) {
557 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
558 } else if (op->code() == lir_cond_float_branch) {
559 assert(op->ublock() != NULL, "must have unordered successor");
560 bool is_unordered = (op->ublock() == op->block());
561 Assembler::Condition acond;
562 switch (op->cond()) {
563 case lir_cond_equal: acond = Assembler::f_equal; break;
564 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
565 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
566 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
567 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
568 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
569 default : ShouldNotReachHere();
570 }
571 __ fb( acond, false, Assembler::pn, *(op->label()));
572 } else {
573 assert (op->code() == lir_branch, "just checking");
574
575 Assembler::Condition acond;
576 switch (op->cond()) {
577 case lir_cond_equal: acond = Assembler::equal; break;
578 case lir_cond_notEqual: acond = Assembler::notEqual; break;
579 case lir_cond_less: acond = Assembler::less; break;
580 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
581 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
582 case lir_cond_greater: acond = Assembler::greater; break;
583 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
584 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
585 default: ShouldNotReachHere();
586 };
587
588 // sparc has different condition codes for testing 32-bit
589 // vs. 64-bit values. We could always test xcc is we could
590 // guarantee that 32-bit loads always sign extended but that isn't
591 // true and since sign extension isn't free, it would impose a
592 // slight cost.
593 if (op->type() == T_INT) {
594 __ br(acond, false, Assembler::pn, *(op->label()));
595 } else
596 __ brx(acond, false, Assembler::pn, *(op->label()));
597 }
598 // The peephole pass fills the delay slot
599 }
600
601
602 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
603 Bytecodes::Code code = op->bytecode();
604 LIR_Opr dst = op->result_opr();
605
606 switch(code) {
607 case Bytecodes::_i2l: {
608 Register rlo = dst->as_register_lo();
609 Register rhi = dst->as_register_hi();
610 Register rval = op->in_opr()->as_register();
611 __ sra(rval, 0, rlo);
612 break;
613 }
614 case Bytecodes::_i2d:
615 case Bytecodes::_i2f: {
616 bool is_double = (code == Bytecodes::_i2d);
617 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
618 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
619 FloatRegister rsrc = op->in_opr()->as_float_reg();
620 if (rsrc != rdst) {
621 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
622 }
623 __ fitof(w, rdst, rdst);
624 break;
625 }
626 case Bytecodes::_f2i:{
627 FloatRegister rsrc = op->in_opr()->as_float_reg();
628 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
629 Label L;
630 // result must be 0 if value is NaN; test by comparing value to itself
631 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
632 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
633 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
634 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
635 // move integer result from float register to int register
636 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
637 __ bind (L);
638 break;
639 }
640 case Bytecodes::_l2i: {
641 Register rlo = op->in_opr()->as_register_lo();
642 Register rhi = op->in_opr()->as_register_hi();
643 Register rdst = dst->as_register();
644 __ sra(rlo, 0, rdst);
645 break;
646 }
647 case Bytecodes::_d2f:
648 case Bytecodes::_f2d: {
649 bool is_double = (code == Bytecodes::_f2d);
650 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
651 LIR_Opr val = op->in_opr();
652 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
653 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
654 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
655 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
656 __ ftof(vw, dw, rval, rdst);
657 break;
658 }
659 case Bytecodes::_i2s:
660 case Bytecodes::_i2b: {
661 Register rval = op->in_opr()->as_register();
662 Register rdst = dst->as_register();
663 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
664 __ sll (rval, shift, rdst);
665 __ sra (rdst, shift, rdst);
666 break;
667 }
668 case Bytecodes::_i2c: {
669 Register rval = op->in_opr()->as_register();
670 Register rdst = dst->as_register();
671 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
672 __ sll (rval, shift, rdst);
673 __ srl (rdst, shift, rdst);
674 break;
675 }
676
677 default: ShouldNotReachHere();
678 }
679 }
680
681
682 void LIR_Assembler::align_call(LIR_Code) {
683 // do nothing since all instructions are word aligned on sparc
684 }
685
686
687 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
688 __ call(op->addr(), rtype);
689 // The peephole pass fills the delay slot, add_call_info is done in
690 // LIR_Assembler::emit_delay.
691 }
692
693
694 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
695 __ ic_call(op->addr(), false);
696 // The peephole pass fills the delay slot, add_call_info is done in
697 // LIR_Assembler::emit_delay.
698 }
699
700
701 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
702 add_debug_info_for_null_check_here(op->info());
703 __ load_klass(O0, G3_scratch);
704 if (Assembler::is_simm13(op->vtable_offset())) {
705 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
706 } else {
707 // This will generate 2 instructions
708 __ set(op->vtable_offset(), G5_method);
709 // ld_ptr, set_hi, set
710 __ ld_ptr(G3_scratch, G5_method, G5_method);
711 }
712 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
713 __ callr(G3_scratch, G0);
714 // the peephole pass fills the delay slot
715 }
716
717 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
718 int store_offset;
719 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
720 assert(base != O7, "destroying register");
721 assert(!unaligned, "can't handle this");
722 // for offsets larger than a simm13 we setup the offset in O7
723 __ set(offset, O7);
724 store_offset = store(from_reg, base, O7, type, wide);
725 } else {
726 if (type == T_ARRAY || type == T_OBJECT) {
727 __ verify_oop(from_reg->as_register());
728 }
729 store_offset = code_offset();
730 switch (type) {
731 case T_BOOLEAN: // fall through
732 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
733 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
734 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
735 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
736 case T_LONG :
737 if (unaligned || PatchALot) {
738 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem)
739 assert(G3_scratch != base, "can't handle this");
740 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this");
741 __ srax(from_reg->as_register_lo(), 32, G3_scratch);
742 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
743 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes);
744 } else {
745 __ stx(from_reg->as_register_lo(), base, offset);
746 }
747 break;
748 case T_ADDRESS:
749 case T_METADATA:
750 __ st_ptr(from_reg->as_register(), base, offset);
751 break;
752 case T_ARRAY : // fall through
753 case T_OBJECT:
754 {
755 if (UseCompressedOops && !wide) {
756 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
757 store_offset = code_offset();
758 __ stw(G3_scratch, base, offset);
759 } else {
760 __ st_ptr(from_reg->as_register(), base, offset);
761 }
762 break;
763 }
764
765 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
766 case T_DOUBLE:
767 {
768 FloatRegister reg = from_reg->as_double_reg();
769 // split unaligned stores
770 if (unaligned || PatchALot) {
771 assert(Assembler::is_simm13(offset + 4), "must be");
772 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
773 __ stf(FloatRegisterImpl::S, reg, base, offset);
774 } else {
775 __ stf(FloatRegisterImpl::D, reg, base, offset);
776 }
777 break;
778 }
779 default : ShouldNotReachHere();
780 }
781 }
782 return store_offset;
783 }
784
785
786 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
787 if (type == T_ARRAY || type == T_OBJECT) {
788 __ verify_oop(from_reg->as_register());
789 }
790 int store_offset = code_offset();
791 switch (type) {
792 case T_BOOLEAN: // fall through
793 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
794 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
795 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
796 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
797 case T_LONG :
798 __ stx(from_reg->as_register_lo(), base, disp);
799 break;
800 case T_ADDRESS:
801 __ st_ptr(from_reg->as_register(), base, disp);
802 break;
803 case T_ARRAY : // fall through
804 case T_OBJECT:
805 {
806 if (UseCompressedOops && !wide) {
807 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
808 store_offset = code_offset();
809 __ stw(G3_scratch, base, disp);
810 } else {
811 __ st_ptr(from_reg->as_register(), base, disp);
812 }
813 break;
814 }
815 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
816 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
817 default : ShouldNotReachHere();
818 }
819 return store_offset;
820 }
821
822
823 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
824 int load_offset;
825 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
826 assert(base != O7, "destroying register");
827 assert(!unaligned, "can't handle this");
828 // for offsets larger than a simm13 we setup the offset in O7
829 __ set(offset, O7);
830 load_offset = load(base, O7, to_reg, type, wide);
831 } else {
832 load_offset = code_offset();
833 switch(type) {
834 case T_BOOLEAN: // fall through
835 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
836 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
837 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
838 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
839 case T_LONG :
840 if (!unaligned && !PatchALot) {
841 __ ldx(base, offset, to_reg->as_register_lo());
842 } else {
843 assert(base != to_reg->as_register_lo(), "can't handle this");
844 assert(O7 != to_reg->as_register_lo(), "can't handle this");
845 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
846 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
847 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
848 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
849 }
850 break;
851 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
852 case T_ADDRESS:
853 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
854 __ lduw(base, offset, to_reg->as_register());
855 __ decode_klass_not_null(to_reg->as_register());
856 } else
857 {
858 __ ld_ptr(base, offset, to_reg->as_register());
859 }
860 break;
861 case T_ARRAY : // fall through
862 case T_OBJECT:
863 {
864 if (UseCompressedOops && !wide) {
865 __ lduw(base, offset, to_reg->as_register());
866 __ decode_heap_oop(to_reg->as_register());
867 } else {
868 __ ld_ptr(base, offset, to_reg->as_register());
869 }
870 break;
871 }
872 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
873 case T_DOUBLE:
874 {
875 FloatRegister reg = to_reg->as_double_reg();
876 // split unaligned loads
877 if (unaligned || PatchALot) {
878 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
879 __ ldf(FloatRegisterImpl::S, base, offset, reg);
880 } else {
881 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
882 }
883 break;
884 }
885 default : ShouldNotReachHere();
886 }
887 if (type == T_ARRAY || type == T_OBJECT) {
888 __ verify_oop(to_reg->as_register());
889 }
890 }
891 return load_offset;
892 }
893
894
895 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
896 int load_offset = code_offset();
897 switch(type) {
898 case T_BOOLEAN: // fall through
899 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
900 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
901 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
902 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
903 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
904 case T_ARRAY : // fall through
905 case T_OBJECT:
906 {
907 if (UseCompressedOops && !wide) {
908 __ lduw(base, disp, to_reg->as_register());
909 __ decode_heap_oop(to_reg->as_register());
910 } else {
911 __ ld_ptr(base, disp, to_reg->as_register());
912 }
913 break;
914 }
915 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
916 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
917 case T_LONG :
918 __ ldx(base, disp, to_reg->as_register_lo());
919 break;
920 default : ShouldNotReachHere();
921 }
922 if (type == T_ARRAY || type == T_OBJECT) {
923 __ verify_oop(to_reg->as_register());
924 }
925 return load_offset;
926 }
927
928 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
929 LIR_Const* c = src->as_constant_ptr();
930 switch (c->type()) {
931 case T_INT:
932 case T_FLOAT: {
933 Register src_reg = O7;
934 int value = c->as_jint_bits();
935 if (value == 0) {
936 src_reg = G0;
937 } else {
938 __ set(value, O7);
939 }
940 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
941 __ stw(src_reg, addr.base(), addr.disp());
942 break;
943 }
944 case T_ADDRESS: {
945 Register src_reg = O7;
946 int value = c->as_jint_bits();
947 if (value == 0) {
948 src_reg = G0;
949 } else {
950 __ set(value, O7);
951 }
952 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
953 __ st_ptr(src_reg, addr.base(), addr.disp());
954 break;
955 }
956 case T_OBJECT: {
957 Register src_reg = O7;
958 jobject2reg(c->as_jobject(), src_reg);
959 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
960 __ st_ptr(src_reg, addr.base(), addr.disp());
961 break;
962 }
963 case T_LONG:
964 case T_DOUBLE: {
965 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
966
967 Register tmp = O7;
968 int value_lo = c->as_jint_lo_bits();
969 if (value_lo == 0) {
970 tmp = G0;
971 } else {
972 __ set(value_lo, O7);
973 }
974 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
975 int value_hi = c->as_jint_hi_bits();
976 if (value_hi == 0) {
977 tmp = G0;
978 } else {
979 __ set(value_hi, O7);
980 }
981 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
982 break;
983 }
984 default:
985 Unimplemented();
986 }
987 }
988
989
990 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
991 LIR_Const* c = src->as_constant_ptr();
992 LIR_Address* addr = dest->as_address_ptr();
993 Register base = addr->base()->as_pointer_register();
994 int offset = -1;
995
996 switch (c->type()) {
997 case T_FLOAT: type = T_INT; // Float constants are stored by int store instructions.
998 case T_INT:
999 case T_ADDRESS: {
1000 LIR_Opr tmp = FrameMap::O7_opr;
1001 int value = c->as_jint_bits();
1002 if (value == 0) {
1003 tmp = FrameMap::G0_opr;
1004 } else if (Assembler::is_simm13(value)) {
1005 __ set(value, O7);
1006 }
1007 if (addr->index()->is_valid()) {
1008 assert(addr->disp() == 0, "must be zero");
1009 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1010 } else {
1011 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1012 offset = store(tmp, base, addr->disp(), type, wide, false);
1013 }
1014 break;
1015 }
1016 case T_LONG:
1017 case T_DOUBLE: {
1018 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1019 assert(Assembler::is_simm13(addr->disp()) &&
1020 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1021
1022 LIR_Opr tmp = FrameMap::O7_opr;
1023 int value_lo = c->as_jint_lo_bits();
1024 if (value_lo == 0) {
1025 tmp = FrameMap::G0_opr;
1026 } else {
1027 __ set(value_lo, O7);
1028 }
1029 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1030 int value_hi = c->as_jint_hi_bits();
1031 if (value_hi == 0) {
1032 tmp = FrameMap::G0_opr;
1033 } else {
1034 __ set(value_hi, O7);
1035 }
1036 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1037 break;
1038 }
1039 case T_OBJECT: {
1040 jobject obj = c->as_jobject();
1041 LIR_Opr tmp;
1042 if (obj == NULL) {
1043 tmp = FrameMap::G0_opr;
1044 } else {
1045 tmp = FrameMap::O7_opr;
1046 jobject2reg(c->as_jobject(), O7);
1047 }
1048 // handle either reg+reg or reg+disp address
1049 if (addr->index()->is_valid()) {
1050 assert(addr->disp() == 0, "must be zero");
1051 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1052 } else {
1053 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1054 offset = store(tmp, base, addr->disp(), type, wide, false);
1055 }
1056
1057 break;
1058 }
1059 default:
1060 Unimplemented();
1061 }
1062 if (info != NULL) {
1063 assert(offset != -1, "offset should've been set");
1064 add_debug_info_for_null_check(offset, info);
1065 }
1066 }
1067
1068
1069 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1070 LIR_Const* c = src->as_constant_ptr();
1071 LIR_Opr to_reg = dest;
1072
1073 switch (c->type()) {
1074 case T_INT:
1075 case T_ADDRESS:
1076 {
1077 jint con = c->as_jint();
1078 if (to_reg->is_single_cpu()) {
1079 assert(patch_code == lir_patch_none, "no patching handled here");
1080 __ set(con, to_reg->as_register());
1081 } else {
1082 ShouldNotReachHere();
1083 assert(to_reg->is_single_fpu(), "wrong register kind");
1084
1085 __ set(con, O7);
1086 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1087 __ st(O7, temp_slot);
1088 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1089 }
1090 }
1091 break;
1092
1093 case T_LONG:
1094 {
1095 jlong con = c->as_jlong();
1096
1097 if (to_reg->is_double_cpu()) {
1098 __ set(con, to_reg->as_register_lo());
1099 } else if (to_reg->is_single_cpu()) {
1100 __ set(con, to_reg->as_register());
1101 } else {
1102 ShouldNotReachHere();
1103 assert(to_reg->is_double_fpu(), "wrong register kind");
1104 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1105 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1106 __ set(low(con), O7);
1107 __ st(O7, temp_slot_lo);
1108 __ set(high(con), O7);
1109 __ st(O7, temp_slot_hi);
1110 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1111 }
1112 }
1113 break;
1114
1115 case T_OBJECT:
1116 {
1117 if (patch_code == lir_patch_none) {
1118 jobject2reg(c->as_jobject(), to_reg->as_register());
1119 } else {
1120 jobject2reg_with_patching(to_reg->as_register(), info);
1121 }
1122 }
1123 break;
1124
1125 case T_METADATA:
1126 {
1127 if (patch_code == lir_patch_none) {
1128 metadata2reg(c->as_metadata(), to_reg->as_register());
1129 } else {
1130 klass2reg_with_patching(to_reg->as_register(), info);
1131 }
1132 }
1133 break;
1134
1135 case T_FLOAT:
1136 {
1137 address const_addr = __ float_constant(c->as_jfloat());
1138 if (const_addr == NULL) {
1139 bailout("const section overflow");
1140 break;
1141 }
1142 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1143 AddressLiteral const_addrlit(const_addr, rspec);
1144 if (to_reg->is_single_fpu()) {
1145 __ patchable_sethi(const_addrlit, O7);
1146 __ relocate(rspec);
1147 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1148
1149 } else {
1150 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1151
1152 __ set(const_addrlit, O7);
1153 __ ld(O7, 0, to_reg->as_register());
1154 }
1155 }
1156 break;
1157
1158 case T_DOUBLE:
1159 {
1160 address const_addr = __ double_constant(c->as_jdouble());
1161 if (const_addr == NULL) {
1162 bailout("const section overflow");
1163 break;
1164 }
1165 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1166
1167 if (to_reg->is_double_fpu()) {
1168 AddressLiteral const_addrlit(const_addr, rspec);
1169 __ patchable_sethi(const_addrlit, O7);
1170 __ relocate(rspec);
1171 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1172 } else {
1173 assert(to_reg->is_double_cpu(), "Must be a long register.");
1174 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1175 }
1176
1177 }
1178 break;
1179
1180 default:
1181 ShouldNotReachHere();
1182 }
1183 }
1184
1185 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1186 Register reg = addr->base()->as_pointer_register();
1187 LIR_Opr index = addr->index();
1188 if (index->is_illegal()) {
1189 return Address(reg, addr->disp());
1190 } else {
1191 assert (addr->disp() == 0, "unsupported address mode");
1192 return Address(reg, index->as_pointer_register());
1193 }
1194 }
1195
1196
1197 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1198 switch (type) {
1199 case T_INT:
1200 case T_FLOAT: {
1201 Register tmp = O7;
1202 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1203 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1204 __ lduw(from.base(), from.disp(), tmp);
1205 __ stw(tmp, to.base(), to.disp());
1206 break;
1207 }
1208 case T_ADDRESS:
1209 case T_OBJECT: {
1210 Register tmp = O7;
1211 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1212 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1213 __ ld_ptr(from.base(), from.disp(), tmp);
1214 __ st_ptr(tmp, to.base(), to.disp());
1215 break;
1216 }
1217 case T_LONG:
1218 case T_DOUBLE: {
1219 Register tmp = O7;
1220 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1221 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1222 __ lduw(from.base(), from.disp(), tmp);
1223 __ stw(tmp, to.base(), to.disp());
1224 __ lduw(from.base(), from.disp() + 4, tmp);
1225 __ stw(tmp, to.base(), to.disp() + 4);
1226 break;
1227 }
1228
1229 default:
1230 ShouldNotReachHere();
1231 }
1232 }
1233
1234
1235 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1236 Address base = as_Address(addr);
1237 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1238 }
1239
1240
1241 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1242 Address base = as_Address(addr);
1243 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1244 }
1245
1246
1247 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1248 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1249
1250 assert(type != T_METADATA, "load of metadata ptr not supported");
1251 LIR_Address* addr = src_opr->as_address_ptr();
1252 LIR_Opr to_reg = dest;
1253
1254 Register src = addr->base()->as_pointer_register();
1255 Register disp_reg = noreg;
1256 int disp_value = addr->disp();
1257 bool needs_patching = (patch_code != lir_patch_none);
1258
1259 if (addr->base()->type() == T_OBJECT) {
1260 __ verify_oop(src);
1261 }
1262
1263 PatchingStub* patch = NULL;
1264 if (needs_patching) {
1265 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1266 assert(!to_reg->is_double_cpu() ||
1267 patch_code == lir_patch_none ||
1268 patch_code == lir_patch_normal, "patching doesn't match register");
1269 }
1270
1271 if (addr->index()->is_illegal()) {
1272 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1273 if (needs_patching) {
1274 __ patchable_set(0, O7);
1275 } else {
1276 __ set(disp_value, O7);
1277 }
1278 disp_reg = O7;
1279 }
1280 } else if (unaligned || PatchALot) {
1281 __ add(src, addr->index()->as_pointer_register(), O7);
1282 src = O7;
1283 } else {
1284 disp_reg = addr->index()->as_pointer_register();
1285 assert(disp_value == 0, "can't handle 3 operand addresses");
1286 }
1287
1288 // remember the offset of the load. The patching_epilog must be done
1289 // before the call to add_debug_info, otherwise the PcDescs don't get
1290 // entered in increasing order.
1291 int offset = code_offset();
1292
1293 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1294 if (disp_reg == noreg) {
1295 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1296 } else {
1297 assert(!unaligned, "can't handle this");
1298 offset = load(src, disp_reg, to_reg, type, wide);
1299 }
1300
1301 if (patch != NULL) {
1302 patching_epilog(patch, patch_code, src, info);
1303 }
1304 if (info != NULL) add_debug_info_for_null_check(offset, info);
1305 }
1306
1307
1308 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1309 Address addr;
1310 if (src->is_single_word()) {
1311 addr = frame_map()->address_for_slot(src->single_stack_ix());
1312 } else if (src->is_double_word()) {
1313 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1314 }
1315
1316 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1317 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1318 }
1319
1320
1321 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1322 Address addr;
1323 if (dest->is_single_word()) {
1324 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1325 } else if (dest->is_double_word()) {
1326 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1327 }
1328 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1329 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1330 }
1331
1332
1333 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1334 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1335 if (from_reg->is_double_fpu()) {
1336 // double to double moves
1337 assert(to_reg->is_double_fpu(), "should match");
1338 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1339 } else {
1340 // float to float moves
1341 assert(to_reg->is_single_fpu(), "should match");
1342 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1343 }
1344 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1345 if (from_reg->is_double_cpu()) {
1346 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1347 } else if (to_reg->is_double_cpu()) {
1348 // int to int moves
1349 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1350 } else {
1351 // int to int moves
1352 __ mov(from_reg->as_register(), to_reg->as_register());
1353 }
1354 } else {
1355 ShouldNotReachHere();
1356 }
1357 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1358 __ verify_oop(to_reg->as_register());
1359 }
1360 }
1361
1362 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1363 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1364 bool wide, bool unaligned) {
1365 assert(type != T_METADATA, "store of metadata ptr not supported");
1366 LIR_Address* addr = dest->as_address_ptr();
1367
1368 Register src = addr->base()->as_pointer_register();
1369 Register disp_reg = noreg;
1370 int disp_value = addr->disp();
1371 bool needs_patching = (patch_code != lir_patch_none);
1372
1373 if (addr->base()->is_oop_register()) {
1374 __ verify_oop(src);
1375 }
1376
1377 PatchingStub* patch = NULL;
1378 if (needs_patching) {
1379 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1380 assert(!from_reg->is_double_cpu() ||
1381 patch_code == lir_patch_none ||
1382 patch_code == lir_patch_normal, "patching doesn't match register");
1383 }
1384
1385 if (addr->index()->is_illegal()) {
1386 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1387 if (needs_patching) {
1388 __ patchable_set(0, O7);
1389 } else {
1390 __ set(disp_value, O7);
1391 }
1392 disp_reg = O7;
1393 }
1394 } else if (unaligned || PatchALot) {
1395 __ add(src, addr->index()->as_pointer_register(), O7);
1396 src = O7;
1397 } else {
1398 disp_reg = addr->index()->as_pointer_register();
1399 assert(disp_value == 0, "can't handle 3 operand addresses");
1400 }
1401
1402 // remember the offset of the store. The patching_epilog must be done
1403 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1404 // entered in increasing order.
1405 int offset;
1406
1407 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1408 if (disp_reg == noreg) {
1409 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1410 } else {
1411 assert(!unaligned, "can't handle this");
1412 offset = store(from_reg, src, disp_reg, type, wide);
1413 }
1414
1415 if (patch != NULL) {
1416 patching_epilog(patch, patch_code, src, info);
1417 }
1418
1419 if (info != NULL) add_debug_info_for_null_check(offset, info);
1420 }
1421
1422
1423 void LIR_Assembler::return_op(LIR_Opr result) {
1424 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1425 __ reserved_stack_check();
1426 }
1427 if (SafepointMechanism::uses_thread_local_poll()) {
1428 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), L0);
1429 } else {
1430 __ set((intptr_t)os::get_polling_page(), L0);
1431 }
1432 __ relocate(relocInfo::poll_return_type);
1433 __ ld_ptr(L0, 0, G0);
1434 __ ret();
1435 __ delayed()->restore();
1436 }
1437
1438
1439 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1440 if (SafepointMechanism::uses_thread_local_poll()) {
1441 __ ld_ptr(Address(G2_thread, Thread::polling_page_offset()), tmp->as_register());
1442 } else {
1443 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1444 }
1445 if (info != NULL) {
1446 add_debug_info_for_branch(info);
1447 }
1448 int offset = __ offset();
1449
1450 __ relocate(relocInfo::poll_type);
1451 __ ld_ptr(tmp->as_register(), 0, G0);
1452 return offset;
1453 }
1454
1455
1456 void LIR_Assembler::emit_static_call_stub() {
1457 address call_pc = __ pc();
1458 address stub = __ start_a_stub(call_stub_size());
1459 if (stub == NULL) {
1460 bailout("static call stub overflow");
1461 return;
1462 }
1463
1464 int start = __ offset();
1465 __ relocate(static_stub_Relocation::spec(call_pc));
1466
1467 __ set_metadata(NULL, G5);
1468 // must be set to -1 at code generation time
1469 AddressLiteral addrlit(-1);
1470 __ jump_to(addrlit, G3);
1471 __ delayed()->nop();
1472
1473 assert(__ offset() - start <= call_stub_size(), "stub too big");
1474 __ end_a_stub();
1475 }
1476
1477
1478 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1479 if (opr1->is_single_fpu()) {
1480 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1481 } else if (opr1->is_double_fpu()) {
1482 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1483 } else if (opr1->is_single_cpu()) {
1484 if (opr2->is_constant()) {
1485 switch (opr2->as_constant_ptr()->type()) {
1486 case T_INT:
1487 { jint con = opr2->as_constant_ptr()->as_jint();
1488 if (Assembler::is_simm13(con)) {
1489 __ cmp(opr1->as_register(), con);
1490 } else {
1491 __ set(con, O7);
1492 __ cmp(opr1->as_register(), O7);
1493 }
1494 }
1495 break;
1496
1497 case T_OBJECT:
1498 // there are only equal/notequal comparisions on objects
1499 { jobject con = opr2->as_constant_ptr()->as_jobject();
1500 if (con == NULL) {
1501 __ cmp(opr1->as_register(), 0);
1502 } else {
1503 jobject2reg(con, O7);
1504 __ cmp(opr1->as_register(), O7);
1505 }
1506 }
1507 break;
1508
1509 default:
1510 ShouldNotReachHere();
1511 break;
1512 }
1513 } else {
1514 if (opr2->is_address()) {
1515 LIR_Address * addr = opr2->as_address_ptr();
1516 BasicType type = addr->type();
1517 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1518 else __ ld(as_Address(addr), O7);
1519 __ cmp(opr1->as_register(), O7);
1520 } else {
1521 __ cmp(opr1->as_register(), opr2->as_register());
1522 }
1523 }
1524 } else if (opr1->is_double_cpu()) {
1525 Register xlo = opr1->as_register_lo();
1526 Register xhi = opr1->as_register_hi();
1527 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1528 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1529 __ orcc(xhi, G0, G0);
1530 } else if (opr2->is_register()) {
1531 Register ylo = opr2->as_register_lo();
1532 Register yhi = opr2->as_register_hi();
1533 __ cmp(xlo, ylo);
1534 } else {
1535 ShouldNotReachHere();
1536 }
1537 } else if (opr1->is_address()) {
1538 LIR_Address * addr = opr1->as_address_ptr();
1539 BasicType type = addr->type();
1540 assert (opr2->is_constant(), "Checking");
1541 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1542 else __ ld(as_Address(addr), O7);
1543 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1544 } else {
1545 ShouldNotReachHere();
1546 }
1547 }
1548
1549
1550 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1551 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1552 bool is_unordered_less = (code == lir_ucmp_fd2i);
1553 if (left->is_single_fpu()) {
1554 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1555 } else if (left->is_double_fpu()) {
1556 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1557 } else {
1558 ShouldNotReachHere();
1559 }
1560 } else if (code == lir_cmp_l2i) {
1561 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1562 } else {
1563 ShouldNotReachHere();
1564 }
1565 }
1566
1567
1568 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1569 Assembler::Condition acond;
1570 switch (condition) {
1571 case lir_cond_equal: acond = Assembler::equal; break;
1572 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1573 case lir_cond_less: acond = Assembler::less; break;
1574 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1575 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1576 case lir_cond_greater: acond = Assembler::greater; break;
1577 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1578 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1579 default: ShouldNotReachHere();
1580 };
1581
1582 if (opr1->is_constant() && opr1->type() == T_INT) {
1583 Register dest = result->as_register();
1584 // load up first part of constant before branch
1585 // and do the rest in the delay slot.
1586 if (!Assembler::is_simm13(opr1->as_jint())) {
1587 __ sethi(opr1->as_jint(), dest);
1588 }
1589 } else if (opr1->is_constant()) {
1590 const2reg(opr1, result, lir_patch_none, NULL);
1591 } else if (opr1->is_register()) {
1592 reg2reg(opr1, result);
1593 } else if (opr1->is_stack()) {
1594 stack2reg(opr1, result, result->type());
1595 } else {
1596 ShouldNotReachHere();
1597 }
1598 Label skip;
1599 if (type == T_INT) {
1600 __ br(acond, false, Assembler::pt, skip);
1601 } else {
1602 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1603 }
1604 if (opr1->is_constant() && opr1->type() == T_INT) {
1605 Register dest = result->as_register();
1606 if (Assembler::is_simm13(opr1->as_jint())) {
1607 __ delayed()->or3(G0, opr1->as_jint(), dest);
1608 } else {
1609 // the sethi has been done above, so just put in the low 10 bits
1610 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1611 }
1612 } else {
1613 // can't do anything useful in the delay slot
1614 __ delayed()->nop();
1615 }
1616 if (opr2->is_constant()) {
1617 const2reg(opr2, result, lir_patch_none, NULL);
1618 } else if (opr2->is_register()) {
1619 reg2reg(opr2, result);
1620 } else if (opr2->is_stack()) {
1621 stack2reg(opr2, result, result->type());
1622 } else {
1623 ShouldNotReachHere();
1624 }
1625 __ bind(skip);
1626 }
1627
1628
1629 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1630 assert(info == NULL, "unused on this code path");
1631 assert(left->is_register(), "wrong items state");
1632 assert(dest->is_register(), "wrong items state");
1633
1634 if (right->is_register()) {
1635 if (dest->is_float_kind()) {
1636
1637 FloatRegister lreg, rreg, res;
1638 FloatRegisterImpl::Width w;
1639 if (right->is_single_fpu()) {
1640 w = FloatRegisterImpl::S;
1641 lreg = left->as_float_reg();
1642 rreg = right->as_float_reg();
1643 res = dest->as_float_reg();
1644 } else {
1645 w = FloatRegisterImpl::D;
1646 lreg = left->as_double_reg();
1647 rreg = right->as_double_reg();
1648 res = dest->as_double_reg();
1649 }
1650
1651 switch (code) {
1652 case lir_add: __ fadd(w, lreg, rreg, res); break;
1653 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1654 case lir_mul: // fall through
1655 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1656 case lir_div: // fall through
1657 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1658 default: ShouldNotReachHere();
1659 }
1660
1661 } else if (dest->is_double_cpu()) {
1662 Register dst_lo = dest->as_register_lo();
1663 Register op1_lo = left->as_pointer_register();
1664 Register op2_lo = right->as_pointer_register();
1665
1666 switch (code) {
1667 case lir_add:
1668 __ add(op1_lo, op2_lo, dst_lo);
1669 break;
1670
1671 case lir_sub:
1672 __ sub(op1_lo, op2_lo, dst_lo);
1673 break;
1674
1675 default: ShouldNotReachHere();
1676 }
1677 } else {
1678 assert (right->is_single_cpu(), "Just Checking");
1679
1680 Register lreg = left->as_register();
1681 Register res = dest->as_register();
1682 Register rreg = right->as_register();
1683 switch (code) {
1684 case lir_add: __ add (lreg, rreg, res); break;
1685 case lir_sub: __ sub (lreg, rreg, res); break;
1686 case lir_mul: __ mulx (lreg, rreg, res); break;
1687 default: ShouldNotReachHere();
1688 }
1689 }
1690 } else {
1691 assert (right->is_constant(), "must be constant");
1692
1693 if (dest->is_single_cpu()) {
1694 Register lreg = left->as_register();
1695 Register res = dest->as_register();
1696 int simm13 = right->as_constant_ptr()->as_jint();
1697
1698 switch (code) {
1699 case lir_add: __ add (lreg, simm13, res); break;
1700 case lir_sub: __ sub (lreg, simm13, res); break;
1701 case lir_mul: __ mulx (lreg, simm13, res); break;
1702 default: ShouldNotReachHere();
1703 }
1704 } else {
1705 Register lreg = left->as_pointer_register();
1706 Register res = dest->as_register_lo();
1707 long con = right->as_constant_ptr()->as_jlong();
1708 assert(Assembler::is_simm13(con), "must be simm13");
1709
1710 switch (code) {
1711 case lir_add: __ add (lreg, (int)con, res); break;
1712 case lir_sub: __ sub (lreg, (int)con, res); break;
1713 case lir_mul: __ mulx (lreg, (int)con, res); break;
1714 default: ShouldNotReachHere();
1715 }
1716 }
1717 }
1718 }
1719
1720
1721 void LIR_Assembler::fpop() {
1722 // do nothing
1723 }
1724
1725
1726 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1727 switch (code) {
1728 case lir_tan: {
1729 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1730 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1731 break;
1732 }
1733 case lir_sqrt: {
1734 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1735 FloatRegister src_reg = value->as_double_reg();
1736 FloatRegister dst_reg = dest->as_double_reg();
1737 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1738 break;
1739 }
1740 case lir_abs: {
1741 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1742 FloatRegister src_reg = value->as_double_reg();
1743 FloatRegister dst_reg = dest->as_double_reg();
1744 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1745 break;
1746 }
1747 default: {
1748 ShouldNotReachHere();
1749 break;
1750 }
1751 }
1752 }
1753
1754
1755 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1756 if (right->is_constant()) {
1757 if (dest->is_single_cpu()) {
1758 int simm13 = right->as_constant_ptr()->as_jint();
1759 switch (code) {
1760 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1761 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1762 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1763 default: ShouldNotReachHere();
1764 }
1765 } else {
1766 long c = right->as_constant_ptr()->as_jlong();
1767 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1768 int simm13 = (int)c;
1769 switch (code) {
1770 case lir_logic_and:
1771 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1772 break;
1773
1774 case lir_logic_or:
1775 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1776 break;
1777
1778 case lir_logic_xor:
1779 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1780 break;
1781
1782 default: ShouldNotReachHere();
1783 }
1784 }
1785 } else {
1786 assert(right->is_register(), "right should be in register");
1787
1788 if (dest->is_single_cpu()) {
1789 switch (code) {
1790 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1791 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1792 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1793 default: ShouldNotReachHere();
1794 }
1795 } else {
1796 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1797 left->as_register_lo();
1798 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1799 right->as_register_lo();
1800
1801 switch (code) {
1802 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1803 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
1804 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
1805 default: ShouldNotReachHere();
1806 }
1807 }
1808 }
1809 }
1810
1811
1812 int LIR_Assembler::shift_amount(BasicType t) {
1813 int elem_size = type2aelembytes(t);
1814 switch (elem_size) {
1815 case 1 : return 0;
1816 case 2 : return 1;
1817 case 4 : return 2;
1818 case 8 : return 3;
1819 }
1820 ShouldNotReachHere();
1821 return -1;
1822 }
1823
1824
1825 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1826 assert(exceptionOop->as_register() == Oexception, "should match");
1827 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
1828
1829 info->add_register_oop(exceptionOop);
1830
1831 // reuse the debug info from the safepoint poll for the throw op itself
1832 address pc_for_athrow = __ pc();
1833 int pc_for_athrow_offset = __ offset();
1834 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1835 __ set(pc_for_athrow, Oissuing_pc, rspec);
1836 add_call_info(pc_for_athrow_offset, info); // for exception handler
1837
1838 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
1839 __ delayed()->nop();
1840 }
1841
1842
1843 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1844 assert(exceptionOop->as_register() == Oexception, "should match");
1845
1846 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
1847 __ delayed()->nop();
1848 }
1849
1850 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1851 Register src = op->src()->as_register();
1852 Register dst = op->dst()->as_register();
1853 Register src_pos = op->src_pos()->as_register();
1854 Register dst_pos = op->dst_pos()->as_register();
1855 Register length = op->length()->as_register();
1856 Register tmp = op->tmp()->as_register();
1857 Register tmp2 = O7;
1858
1859 int flags = op->flags();
1860 ciArrayKlass* default_type = op->expected_type();
1861 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1862 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1863
1864 // higher 32bits must be null
1865 __ sra(dst_pos, 0, dst_pos);
1866 __ sra(src_pos, 0, src_pos);
1867 __ sra(length, 0, length);
1868
1869 // set up the arraycopy stub information
1870 ArrayCopyStub* stub = op->stub();
1871
1872 // always do stub if no type information is available. it's ok if
1873 // the known type isn't loaded since the code sanity checks
1874 // in debug mode and the type isn't required when we know the exact type
1875 // also check that the type is an array type.
1876 if (op->expected_type() == NULL) {
1877 __ mov(src, O0);
1878 __ mov(src_pos, O1);
1879 __ mov(dst, O2);
1880 __ mov(dst_pos, O3);
1881 __ mov(length, O4);
1882 address copyfunc_addr = StubRoutines::generic_arraycopy();
1883 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1884
1885 #ifndef PRODUCT
1886 if (PrintC1Statistics) {
1887 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1888 __ inc_counter(counter, G1, G3);
1889 }
1890 #endif
1891 __ call_VM_leaf(tmp, copyfunc_addr);
1892
1893 __ xor3(O0, -1, tmp);
1894 __ sub(length, tmp, length);
1895 __ add(src_pos, tmp, src_pos);
1896 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
1897 __ delayed()->add(dst_pos, tmp, dst_pos);
1898 __ bind(*stub->continuation());
1899 return;
1900 }
1901
1902 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1903
1904 // make sure src and dst are non-null and load array length
1905 if (flags & LIR_OpArrayCopy::src_null_check) {
1906 __ tst(src);
1907 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1908 __ delayed()->nop();
1909 }
1910
1911 if (flags & LIR_OpArrayCopy::dst_null_check) {
1912 __ tst(dst);
1913 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
1914 __ delayed()->nop();
1915 }
1916
1917 // If the compiler was not able to prove that exact type of the source or the destination
1918 // of the arraycopy is an array type, check at runtime if the source or the destination is
1919 // an instance type.
1920 if (flags & LIR_OpArrayCopy::type_check) {
1921 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
1922 __ load_klass(dst, tmp);
1923 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1924 __ cmp(tmp2, Klass::_lh_neutral_value);
1925 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1926 __ delayed()->nop();
1927 }
1928
1929 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
1930 __ load_klass(src, tmp);
1931 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2);
1932 __ cmp(tmp2, Klass::_lh_neutral_value);
1933 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry());
1934 __ delayed()->nop();
1935 }
1936 }
1937
1938 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1939 // test src_pos register
1940 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
1941 __ delayed()->nop();
1942 }
1943
1944 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1945 // test dst_pos register
1946 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
1947 __ delayed()->nop();
1948 }
1949
1950 if (flags & LIR_OpArrayCopy::length_positive_check) {
1951 // make sure length isn't negative
1952 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
1953 __ delayed()->nop();
1954 }
1955
1956 if (flags & LIR_OpArrayCopy::src_range_check) {
1957 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
1958 __ add(length, src_pos, tmp);
1959 __ cmp(tmp2, tmp);
1960 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1961 __ delayed()->nop();
1962 }
1963
1964 if (flags & LIR_OpArrayCopy::dst_range_check) {
1965 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
1966 __ add(length, dst_pos, tmp);
1967 __ cmp(tmp2, tmp);
1968 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
1969 __ delayed()->nop();
1970 }
1971
1972 int shift = shift_amount(basic_type);
1973
1974 if (flags & LIR_OpArrayCopy::type_check) {
1975 // We don't know the array types are compatible
1976 if (basic_type != T_OBJECT) {
1977 // Simple test for basic type arrays
1978 if (UseCompressedClassPointers) {
1979 // We don't need decode because we just need to compare
1980 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
1981 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1982 __ cmp(tmp, tmp2);
1983 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1984 } else {
1985 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
1986 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
1987 __ cmp(tmp, tmp2);
1988 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
1989 }
1990 __ delayed()->nop();
1991 } else {
1992 // For object arrays, if src is a sub class of dst then we can
1993 // safely do the copy.
1994 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1995
1996 Label cont, slow;
1997 assert_different_registers(tmp, tmp2, G3, G1);
1998
1999 __ load_klass(src, G3);
2000 __ load_klass(dst, G1);
2001
2002 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2003
2004 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2005 __ delayed()->nop();
2006
2007 __ cmp(G3, 0);
2008 if (copyfunc_addr != NULL) { // use stub if available
2009 // src is not a sub class of dst so we have to do a
2010 // per-element check.
2011 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2012 __ delayed()->nop();
2013
2014 __ bind(slow);
2015
2016 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2017 if ((flags & mask) != mask) {
2018 // Check that at least both of them object arrays.
2019 assert(flags & mask, "one of the two should be known to be an object array");
2020
2021 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2022 __ load_klass(src, tmp);
2023 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2024 __ load_klass(dst, tmp);
2025 }
2026 int lh_offset = in_bytes(Klass::layout_helper_offset());
2027
2028 __ lduw(tmp, lh_offset, tmp2);
2029
2030 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2031 __ set(objArray_lh, tmp);
2032 __ cmp(tmp, tmp2);
2033 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2034 __ delayed()->nop();
2035 }
2036
2037 Register src_ptr = O0;
2038 Register dst_ptr = O1;
2039 Register len = O2;
2040 Register chk_off = O3;
2041 Register super_k = O4;
2042
2043 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2044 if (shift == 0) {
2045 __ add(src_ptr, src_pos, src_ptr);
2046 } else {
2047 __ sll(src_pos, shift, tmp);
2048 __ add(src_ptr, tmp, src_ptr);
2049 }
2050
2051 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2052 if (shift == 0) {
2053 __ add(dst_ptr, dst_pos, dst_ptr);
2054 } else {
2055 __ sll(dst_pos, shift, tmp);
2056 __ add(dst_ptr, tmp, dst_ptr);
2057 }
2058 __ mov(length, len);
2059 __ load_klass(dst, tmp);
2060
2061 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2062 __ ld_ptr(tmp, ek_offset, super_k);
2063
2064 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2065 __ lduw(super_k, sco_offset, chk_off);
2066
2067 __ call_VM_leaf(tmp, copyfunc_addr);
2068
2069 #ifndef PRODUCT
2070 if (PrintC1Statistics) {
2071 Label failed;
2072 __ br_notnull_short(O0, Assembler::pn, failed);
2073 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2074 __ bind(failed);
2075 }
2076 #endif
2077
2078 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2079 __ delayed()->xor3(O0, -1, tmp);
2080
2081 #ifndef PRODUCT
2082 if (PrintC1Statistics) {
2083 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2084 }
2085 #endif
2086
2087 __ sub(length, tmp, length);
2088 __ add(src_pos, tmp, src_pos);
2089 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2090 __ delayed()->add(dst_pos, tmp, dst_pos);
2091
2092 __ bind(cont);
2093 } else {
2094 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2095 __ delayed()->nop();
2096 __ bind(cont);
2097 }
2098 }
2099 }
2100
2101 #ifdef ASSERT
2102 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2103 // Sanity check the known type with the incoming class. For the
2104 // primitive case the types must match exactly with src.klass and
2105 // dst.klass each exactly matching the default type. For the
2106 // object array case, if no type check is needed then either the
2107 // dst type is exactly the expected type and the src type is a
2108 // subtype which we can't check or src is the same array as dst
2109 // but not necessarily exactly of type default_type.
2110 Label known_ok, halt;
2111 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2112 if (UseCompressedClassPointers) {
2113 // tmp holds the default type. It currently comes uncompressed after the
2114 // load of a constant, so encode it.
2115 __ encode_klass_not_null(tmp);
2116 // load the raw value of the dst klass, since we will be comparing
2117 // uncompressed values directly.
2118 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2119 if (basic_type != T_OBJECT) {
2120 __ cmp(tmp, tmp2);
2121 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2122 // load the raw value of the src klass.
2123 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2124 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2125 } else {
2126 __ cmp(tmp, tmp2);
2127 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2128 __ delayed()->cmp(src, dst);
2129 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2130 __ delayed()->nop();
2131 }
2132 } else {
2133 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2134 if (basic_type != T_OBJECT) {
2135 __ cmp(tmp, tmp2);
2136 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2137 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2138 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2139 } else {
2140 __ cmp(tmp, tmp2);
2141 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2142 __ delayed()->cmp(src, dst);
2143 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2144 __ delayed()->nop();
2145 }
2146 }
2147 __ bind(halt);
2148 __ stop("incorrect type information in arraycopy");
2149 __ bind(known_ok);
2150 }
2151 #endif
2152
2153 #ifndef PRODUCT
2154 if (PrintC1Statistics) {
2155 address counter = Runtime1::arraycopy_count_address(basic_type);
2156 __ inc_counter(counter, G1, G3);
2157 }
2158 #endif
2159
2160 Register src_ptr = O0;
2161 Register dst_ptr = O1;
2162 Register len = O2;
2163
2164 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2165 if (shift == 0) {
2166 __ add(src_ptr, src_pos, src_ptr);
2167 } else {
2168 __ sll(src_pos, shift, tmp);
2169 __ add(src_ptr, tmp, src_ptr);
2170 }
2171
2172 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2173 if (shift == 0) {
2174 __ add(dst_ptr, dst_pos, dst_ptr);
2175 } else {
2176 __ sll(dst_pos, shift, tmp);
2177 __ add(dst_ptr, tmp, dst_ptr);
2178 }
2179
2180 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2181 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2182 const char *name;
2183 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2184
2185 // arraycopy stubs takes a length in number of elements, so don't scale it.
2186 __ mov(length, len);
2187 __ call_VM_leaf(tmp, entry);
2188
2189 __ bind(*stub->continuation());
2190 }
2191
2192
2193 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2194 if (dest->is_single_cpu()) {
2195 if (left->type() == T_OBJECT) {
2196 switch (code) {
2197 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2198 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2199 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2200 default: ShouldNotReachHere();
2201 }
2202 } else
2203 switch (code) {
2204 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2205 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2206 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2207 default: ShouldNotReachHere();
2208 }
2209 } else {
2210 switch (code) {
2211 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2212 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2213 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2214 default: ShouldNotReachHere();
2215 }
2216 }
2217 }
2218
2219
2220 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2221 if (left->type() == T_OBJECT) {
2222 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2223 Register l = left->as_register();
2224 Register d = dest->as_register_lo();
2225 switch (code) {
2226 case lir_shl: __ sllx (l, count, d); break;
2227 case lir_shr: __ srax (l, count, d); break;
2228 case lir_ushr: __ srlx (l, count, d); break;
2229 default: ShouldNotReachHere();
2230 }
2231 return;
2232 }
2233
2234 if (dest->is_single_cpu()) {
2235 count = count & 0x1F; // Java spec
2236 switch (code) {
2237 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2238 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2239 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2240 default: ShouldNotReachHere();
2241 }
2242 } else if (dest->is_double_cpu()) {
2243 count = count & 63; // Java spec
2244 switch (code) {
2245 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2246 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2247 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2248 default: ShouldNotReachHere();
2249 }
2250 } else {
2251 ShouldNotReachHere();
2252 }
2253 }
2254
2255
2256 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2257 assert(op->tmp1()->as_register() == G1 &&
2258 op->tmp2()->as_register() == G3 &&
2259 op->tmp3()->as_register() == G4 &&
2260 op->obj()->as_register() == O0 &&
2261 op->klass()->as_register() == G5, "must be");
2262 if (op->init_check()) {
2263 add_debug_info_for_null_check_here(op->stub()->info());
2264 __ ldub(op->klass()->as_register(),
2265 in_bytes(InstanceKlass::init_state_offset()),
2266 op->tmp1()->as_register());
2267 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2268 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2269 __ delayed()->nop();
2270 }
2271 __ allocate_object(op->obj()->as_register(),
2272 op->tmp1()->as_register(),
2273 op->tmp2()->as_register(),
2274 op->tmp3()->as_register(),
2275 op->header_size(),
2276 op->object_size(),
2277 op->klass()->as_register(),
2278 *op->stub()->entry());
2279 __ bind(*op->stub()->continuation());
2280 __ verify_oop(op->obj()->as_register());
2281 }
2282
2283
2284 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2285 assert(op->tmp1()->as_register() == G1 &&
2286 op->tmp2()->as_register() == G3 &&
2287 op->tmp3()->as_register() == G4 &&
2288 op->tmp4()->as_register() == O1 &&
2289 op->klass()->as_register() == G5, "must be");
2290
2291 __ signx(op->len()->as_register());
2292 if (UseSlowPath ||
2293 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2294 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2295 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2296 __ delayed()->nop();
2297 } else {
2298 __ allocate_array(op->obj()->as_register(),
2299 op->len()->as_register(),
2300 op->tmp1()->as_register(),
2301 op->tmp2()->as_register(),
2302 op->tmp3()->as_register(),
2303 arrayOopDesc::header_size(op->type()),
2304 type2aelembytes(op->type()),
2305 op->klass()->as_register(),
2306 *op->stub()->entry());
2307 }
2308 __ bind(*op->stub()->continuation());
2309 }
2310
2311
2312 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2313 ciMethodData *md, ciProfileData *data,
2314 Register recv, Register tmp1, Label* update_done) {
2315 uint i;
2316 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2317 Label next_test;
2318 // See if the receiver is receiver[n].
2319 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2320 mdo_offset_bias);
2321 __ ld_ptr(receiver_addr, tmp1);
2322 __ verify_klass_ptr(tmp1);
2323 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2324 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2325 mdo_offset_bias);
2326 __ ld_ptr(data_addr, tmp1);
2327 __ add(tmp1, DataLayout::counter_increment, tmp1);
2328 __ st_ptr(tmp1, data_addr);
2329 __ ba(*update_done);
2330 __ delayed()->nop();
2331 __ bind(next_test);
2332 }
2333
2334 // Didn't find receiver; find next empty slot and fill it in
2335 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2336 Label next_test;
2337 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2338 mdo_offset_bias);
2339 __ ld_ptr(recv_addr, tmp1);
2340 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2341 __ st_ptr(recv, recv_addr);
2342 __ set(DataLayout::counter_increment, tmp1);
2343 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2344 mdo_offset_bias);
2345 __ ba(*update_done);
2346 __ delayed()->nop();
2347 __ bind(next_test);
2348 }
2349 }
2350
2351
2352 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2353 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2354 md = method->method_data_or_null();
2355 assert(md != NULL, "Sanity");
2356 data = md->bci_to_data(bci);
2357 assert(data != NULL, "need data for checkcast");
2358 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2359 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2360 // The offset is large so bias the mdo by the base of the slot so
2361 // that the ld can use simm13s to reference the slots of the data
2362 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2363 }
2364 }
2365
2366 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2367 // we always need a stub for the failure case.
2368 CodeStub* stub = op->stub();
2369 Register obj = op->object()->as_register();
2370 Register k_RInfo = op->tmp1()->as_register();
2371 Register klass_RInfo = op->tmp2()->as_register();
2372 Register dst = op->result_opr()->as_register();
2373 Register Rtmp1 = op->tmp3()->as_register();
2374 ciKlass* k = op->klass();
2375
2376
2377 if (obj == k_RInfo) {
2378 k_RInfo = klass_RInfo;
2379 klass_RInfo = obj;
2380 }
2381
2382 ciMethodData* md;
2383 ciProfileData* data;
2384 int mdo_offset_bias = 0;
2385 if (op->should_profile()) {
2386 ciMethod* method = op->profiled_method();
2387 assert(method != NULL, "Should have method");
2388 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2389
2390 Label not_null;
2391 __ br_notnull_short(obj, Assembler::pn, not_null);
2392 Register mdo = k_RInfo;
2393 Register data_val = Rtmp1;
2394 metadata2reg(md->constant_encoding(), mdo);
2395 if (mdo_offset_bias > 0) {
2396 __ set(mdo_offset_bias, data_val);
2397 __ add(mdo, data_val, mdo);
2398 }
2399 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2400 __ ldub(flags_addr, data_val);
2401 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2402 __ stb(data_val, flags_addr);
2403 __ ba(*obj_is_null);
2404 __ delayed()->nop();
2405 __ bind(not_null);
2406 } else {
2407 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2408 __ delayed()->nop();
2409 }
2410
2411 Label profile_cast_failure, profile_cast_success;
2412 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2413 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2414
2415 // patching may screw with our temporaries on sparc,
2416 // so let's do it before loading the class
2417 if (k->is_loaded()) {
2418 metadata2reg(k->constant_encoding(), k_RInfo);
2419 } else {
2420 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2421 }
2422 assert(obj != k_RInfo, "must be different");
2423
2424 // get object class
2425 // not a safepoint as obj null check happens earlier
2426 __ load_klass(obj, klass_RInfo);
2427 if (op->fast_check()) {
2428 assert_different_registers(klass_RInfo, k_RInfo);
2429 __ cmp(k_RInfo, klass_RInfo);
2430 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2431 __ delayed()->nop();
2432 } else {
2433 bool need_slow_path = true;
2434 if (k->is_loaded()) {
2435 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2436 need_slow_path = false;
2437 // perform the fast part of the checking logic
2438 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2439 (need_slow_path ? success_target : NULL),
2440 failure_target, NULL,
2441 RegisterOrConstant(k->super_check_offset()));
2442 } else {
2443 // perform the fast part of the checking logic
2444 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2445 failure_target, NULL);
2446 }
2447 if (need_slow_path) {
2448 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2449 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2450 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2451 __ delayed()->nop();
2452 __ cmp(G3, 0);
2453 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2454 __ delayed()->nop();
2455 // Fall through to success case
2456 }
2457 }
2458
2459 if (op->should_profile()) {
2460 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2461 assert_different_registers(obj, mdo, recv, tmp1);
2462 __ bind(profile_cast_success);
2463 metadata2reg(md->constant_encoding(), mdo);
2464 if (mdo_offset_bias > 0) {
2465 __ set(mdo_offset_bias, tmp1);
2466 __ add(mdo, tmp1, mdo);
2467 }
2468 __ load_klass(obj, recv);
2469 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2470 // Jump over the failure case
2471 __ ba(*success);
2472 __ delayed()->nop();
2473 // Cast failure case
2474 __ bind(profile_cast_failure);
2475 metadata2reg(md->constant_encoding(), mdo);
2476 if (mdo_offset_bias > 0) {
2477 __ set(mdo_offset_bias, tmp1);
2478 __ add(mdo, tmp1, mdo);
2479 }
2480 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2481 __ ld_ptr(data_addr, tmp1);
2482 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2483 __ st_ptr(tmp1, data_addr);
2484 __ ba(*failure);
2485 __ delayed()->nop();
2486 }
2487 __ ba(*success);
2488 __ delayed()->nop();
2489 }
2490
2491 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2492 LIR_Code code = op->code();
2493 if (code == lir_store_check) {
2494 Register value = op->object()->as_register();
2495 Register array = op->array()->as_register();
2496 Register k_RInfo = op->tmp1()->as_register();
2497 Register klass_RInfo = op->tmp2()->as_register();
2498 Register Rtmp1 = op->tmp3()->as_register();
2499
2500 __ verify_oop(value);
2501 CodeStub* stub = op->stub();
2502 // check if it needs to be profiled
2503 ciMethodData* md;
2504 ciProfileData* data;
2505 int mdo_offset_bias = 0;
2506 if (op->should_profile()) {
2507 ciMethod* method = op->profiled_method();
2508 assert(method != NULL, "Should have method");
2509 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2510 }
2511 Label profile_cast_success, profile_cast_failure, done;
2512 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2513 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2514
2515 if (op->should_profile()) {
2516 Label not_null;
2517 __ br_notnull_short(value, Assembler::pn, not_null);
2518 Register mdo = k_RInfo;
2519 Register data_val = Rtmp1;
2520 metadata2reg(md->constant_encoding(), mdo);
2521 if (mdo_offset_bias > 0) {
2522 __ set(mdo_offset_bias, data_val);
2523 __ add(mdo, data_val, mdo);
2524 }
2525 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2526 __ ldub(flags_addr, data_val);
2527 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2528 __ stb(data_val, flags_addr);
2529 __ ba_short(done);
2530 __ bind(not_null);
2531 } else {
2532 __ br_null_short(value, Assembler::pn, done);
2533 }
2534 add_debug_info_for_null_check_here(op->info_for_exception());
2535 __ load_klass(array, k_RInfo);
2536 __ load_klass(value, klass_RInfo);
2537
2538 // get instance klass
2539 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2540 // perform the fast part of the checking logic
2541 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2542
2543 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2544 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2545 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2546 __ delayed()->nop();
2547 __ cmp(G3, 0);
2548 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2549 __ delayed()->nop();
2550 // fall through to the success case
2551
2552 if (op->should_profile()) {
2553 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2554 assert_different_registers(value, mdo, recv, tmp1);
2555 __ bind(profile_cast_success);
2556 metadata2reg(md->constant_encoding(), mdo);
2557 if (mdo_offset_bias > 0) {
2558 __ set(mdo_offset_bias, tmp1);
2559 __ add(mdo, tmp1, mdo);
2560 }
2561 __ load_klass(value, recv);
2562 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2563 __ ba_short(done);
2564 // Cast failure case
2565 __ bind(profile_cast_failure);
2566 metadata2reg(md->constant_encoding(), mdo);
2567 if (mdo_offset_bias > 0) {
2568 __ set(mdo_offset_bias, tmp1);
2569 __ add(mdo, tmp1, mdo);
2570 }
2571 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2572 __ ld_ptr(data_addr, tmp1);
2573 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2574 __ st_ptr(tmp1, data_addr);
2575 __ ba(*stub->entry());
2576 __ delayed()->nop();
2577 }
2578 __ bind(done);
2579 } else if (code == lir_checkcast) {
2580 Register obj = op->object()->as_register();
2581 Register dst = op->result_opr()->as_register();
2582 Label success;
2583 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2584 __ bind(success);
2585 __ mov(obj, dst);
2586 } else if (code == lir_instanceof) {
2587 Register obj = op->object()->as_register();
2588 Register dst = op->result_opr()->as_register();
2589 Label success, failure, done;
2590 emit_typecheck_helper(op, &success, &failure, &failure);
2591 __ bind(failure);
2592 __ set(0, dst);
2593 __ ba_short(done);
2594 __ bind(success);
2595 __ set(1, dst);
2596 __ bind(done);
2597 } else {
2598 ShouldNotReachHere();
2599 }
2600
2601 }
2602
2603
2604 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2605 if (op->code() == lir_cas_long) {
2606 assert(VM_Version::supports_cx8(), "wrong machine");
2607 Register addr = op->addr()->as_pointer_register();
2608 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2609 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2610 Register new_value_lo = op->new_value()->as_register_lo();
2611 Register new_value_hi = op->new_value()->as_register_hi();
2612 Register t1 = op->tmp1()->as_register();
2613 Register t2 = op->tmp2()->as_register();
2614 __ mov(cmp_value_lo, t1);
2615 __ mov(new_value_lo, t2);
2616 // perform the compare and swap operation
2617 __ casx(addr, t1, t2);
2618 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2619 // overwritten with the original value in "addr" and will be equal to t1.
2620 __ cmp(t1, t2);
2621 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2622 Register addr = op->addr()->as_pointer_register();
2623 Register cmp_value = op->cmp_value()->as_register();
2624 Register new_value = op->new_value()->as_register();
2625 Register t1 = op->tmp1()->as_register();
2626 Register t2 = op->tmp2()->as_register();
2627 __ mov(cmp_value, t1);
2628 __ mov(new_value, t2);
2629 if (op->code() == lir_cas_obj) {
2630 if (UseCompressedOops) {
2631 __ encode_heap_oop(t1);
2632 __ encode_heap_oop(t2);
2633 __ cas(addr, t1, t2);
2634 } else {
2635 __ cas_ptr(addr, t1, t2);
2636 }
2637 } else {
2638 __ cas(addr, t1, t2);
2639 }
2640 __ cmp(t1, t2);
2641 } else {
2642 Unimplemented();
2643 }
2644 }
2645
2646 void LIR_Assembler::set_24bit_FPU() {
2647 Unimplemented();
2648 }
2649
2650
2651 void LIR_Assembler::reset_FPU() {
2652 Unimplemented();
2653 }
2654
2655
2656 void LIR_Assembler::breakpoint() {
2657 __ breakpoint_trap();
2658 }
2659
2660
2661 void LIR_Assembler::push(LIR_Opr opr) {
2662 Unimplemented();
2663 }
2664
2665
2666 void LIR_Assembler::pop(LIR_Opr opr) {
2667 Unimplemented();
2668 }
2669
2670
2671 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2672 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2673 Register dst = dst_opr->as_register();
2674 Register reg = mon_addr.base();
2675 int offset = mon_addr.disp();
2676 // compute pointer to BasicLock
2677 if (mon_addr.is_simm13()) {
2678 __ add(reg, offset, dst);
2679 } else {
2680 __ set(offset, dst);
2681 __ add(dst, reg, dst);
2682 }
2683 }
2684
2685 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2686 assert(op->crc()->is_single_cpu(), "crc must be register");
2687 assert(op->val()->is_single_cpu(), "byte value must be register");
2688 assert(op->result_opr()->is_single_cpu(), "result must be register");
2689 Register crc = op->crc()->as_register();
2690 Register val = op->val()->as_register();
2691 Register table = op->result_opr()->as_register();
2692 Register res = op->result_opr()->as_register();
2693
2694 assert_different_registers(val, crc, table);
2695
2696 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table);
2697 __ not1(crc);
2698 __ clruwu(crc);
2699 __ update_byte_crc32(crc, val, table);
2700 __ not1(crc);
2701
2702 __ mov(crc, res);
2703 }
2704
2705 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2706 Register obj = op->obj_opr()->as_register();
2707 Register hdr = op->hdr_opr()->as_register();
2708 Register lock = op->lock_opr()->as_register();
2709
2710 // obj may not be an oop
2711 if (op->code() == lir_lock) {
2712 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2713 if (UseFastLocking) {
2714 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2715 // add debug info for NullPointerException only if one is possible
2716 if (op->info() != NULL) {
2717 add_debug_info_for_null_check_here(op->info());
2718 }
2719 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2720 } else {
2721 // always do slow locking
2722 // note: the slow locking code could be inlined here, however if we use
2723 // slow locking, speed doesn't matter anyway and this solution is
2724 // simpler and requires less duplicated code - additionally, the
2725 // slow locking code is the same in either case which simplifies
2726 // debugging
2727 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2728 __ delayed()->nop();
2729 }
2730 } else {
2731 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2732 if (UseFastLocking) {
2733 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2734 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2735 } else {
2736 // always do slow unlocking
2737 // note: the slow unlocking code could be inlined here, however if we use
2738 // slow unlocking, speed doesn't matter anyway and this solution is
2739 // simpler and requires less duplicated code - additionally, the
2740 // slow unlocking code is the same in either case which simplifies
2741 // debugging
2742 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2743 __ delayed()->nop();
2744 }
2745 }
2746 __ bind(*op->stub()->continuation());
2747 }
2748
2749
2750 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2751 ciMethod* method = op->profiled_method();
2752 int bci = op->profiled_bci();
2753 ciMethod* callee = op->profiled_callee();
2754
2755 // Update counter for all call types
2756 ciMethodData* md = method->method_data_or_null();
2757 assert(md != NULL, "Sanity");
2758 ciProfileData* data = md->bci_to_data(bci);
2759 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2760 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2761 Register mdo = op->mdo()->as_register();
2762 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2763 Register tmp1 = op->tmp1()->as_register_lo();
2764 metadata2reg(md->constant_encoding(), mdo);
2765 int mdo_offset_bias = 0;
2766 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2767 data->size_in_bytes())) {
2768 // The offset is large so bias the mdo by the base of the slot so
2769 // that the ld can use simm13s to reference the slots of the data
2770 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2771 __ set(mdo_offset_bias, O7);
2772 __ add(mdo, O7, mdo);
2773 }
2774
2775 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2776 // Perform additional virtual call profiling for invokevirtual and
2777 // invokeinterface bytecodes
2778 if (op->should_profile_receiver_type()) {
2779 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2780 Register recv = op->recv()->as_register();
2781 assert_different_registers(mdo, tmp1, recv);
2782 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2783 ciKlass* known_klass = op->known_holder();
2784 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2785 // We know the type that will be seen at this call site; we can
2786 // statically update the MethodData* rather than needing to do
2787 // dynamic tests on the receiver type
2788
2789 // NOTE: we should probably put a lock around this search to
2790 // avoid collisions by concurrent compilations
2791 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2792 uint i;
2793 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2794 ciKlass* receiver = vc_data->receiver(i);
2795 if (known_klass->equals(receiver)) {
2796 Address data_addr(mdo, md->byte_offset_of_slot(data,
2797 VirtualCallData::receiver_count_offset(i)) -
2798 mdo_offset_bias);
2799 __ ld_ptr(data_addr, tmp1);
2800 __ add(tmp1, DataLayout::counter_increment, tmp1);
2801 __ st_ptr(tmp1, data_addr);
2802 return;
2803 }
2804 }
2805
2806 // Receiver type not found in profile data; select an empty slot
2807
2808 // Note that this is less efficient than it should be because it
2809 // always does a write to the receiver part of the
2810 // VirtualCallData rather than just the first time
2811 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2812 ciKlass* receiver = vc_data->receiver(i);
2813 if (receiver == NULL) {
2814 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2815 mdo_offset_bias);
2816 metadata2reg(known_klass->constant_encoding(), tmp1);
2817 __ st_ptr(tmp1, recv_addr);
2818 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2819 mdo_offset_bias);
2820 __ ld_ptr(data_addr, tmp1);
2821 __ add(tmp1, DataLayout::counter_increment, tmp1);
2822 __ st_ptr(tmp1, data_addr);
2823 return;
2824 }
2825 }
2826 } else {
2827 __ load_klass(recv, recv);
2828 Label update_done;
2829 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2830 // Receiver did not match any saved receiver and there is no empty row for it.
2831 // Increment total counter to indicate polymorphic case.
2832 __ ld_ptr(counter_addr, tmp1);
2833 __ add(tmp1, DataLayout::counter_increment, tmp1);
2834 __ st_ptr(tmp1, counter_addr);
2835
2836 __ bind(update_done);
2837 }
2838 } else {
2839 // Static call
2840 __ ld_ptr(counter_addr, tmp1);
2841 __ add(tmp1, DataLayout::counter_increment, tmp1);
2842 __ st_ptr(tmp1, counter_addr);
2843 }
2844 }
2845
2846 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2847 Register obj = op->obj()->as_register();
2848 Register tmp1 = op->tmp()->as_pointer_register();
2849 Register tmp2 = G1;
2850 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2851 ciKlass* exact_klass = op->exact_klass();
2852 intptr_t current_klass = op->current_klass();
2853 bool not_null = op->not_null();
2854 bool no_conflict = op->no_conflict();
2855
2856 Label update, next, none;
2857
2858 bool do_null = !not_null;
2859 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2860 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2861
2862 assert(do_null || do_update, "why are we here?");
2863 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2864
2865 __ verify_oop(obj);
2866
2867 if (tmp1 != obj) {
2868 __ mov(obj, tmp1);
2869 }
2870 if (do_null) {
2871 __ br_notnull_short(tmp1, Assembler::pt, update);
2872 if (!TypeEntries::was_null_seen(current_klass)) {
2873 __ ld_ptr(mdo_addr, tmp1);
2874 __ or3(tmp1, TypeEntries::null_seen, tmp1);
2875 __ st_ptr(tmp1, mdo_addr);
2876 }
2877 if (do_update) {
2878 __ ba(next);
2879 __ delayed()->nop();
2880 }
2881 #ifdef ASSERT
2882 } else {
2883 __ br_notnull_short(tmp1, Assembler::pt, update);
2884 __ stop("unexpect null obj");
2885 #endif
2886 }
2887
2888 __ bind(update);
2889
2890 if (do_update) {
2891 #ifdef ASSERT
2892 if (exact_klass != NULL) {
2893 Label ok;
2894 __ load_klass(tmp1, tmp1);
2895 metadata2reg(exact_klass->constant_encoding(), tmp2);
2896 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
2897 __ stop("exact klass and actual klass differ");
2898 __ bind(ok);
2899 }
2900 #endif
2901
2902 Label do_update;
2903 __ ld_ptr(mdo_addr, tmp2);
2904
2905 if (!no_conflict) {
2906 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2907 if (exact_klass != NULL) {
2908 metadata2reg(exact_klass->constant_encoding(), tmp1);
2909 } else {
2910 __ load_klass(tmp1, tmp1);
2911 }
2912
2913 __ xor3(tmp1, tmp2, tmp1);
2914 __ btst(TypeEntries::type_klass_mask, tmp1);
2915 // klass seen before, nothing to do. The unknown bit may have been
2916 // set already but no need to check.
2917 __ brx(Assembler::zero, false, Assembler::pt, next);
2918 __ delayed()->
2919
2920 btst(TypeEntries::type_unknown, tmp1);
2921 // already unknown. Nothing to do anymore.
2922 __ brx(Assembler::notZero, false, Assembler::pt, next);
2923
2924 if (TypeEntries::is_type_none(current_klass)) {
2925 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2926 __ brx(Assembler::zero, true, Assembler::pt, do_update);
2927 // first time here. Set profile type.
2928 __ delayed()->or3(tmp2, tmp1, tmp2);
2929 } else {
2930 __ delayed()->nop();
2931 }
2932 } else {
2933 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2934 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2935
2936 __ btst(TypeEntries::type_unknown, tmp2);
2937 // already unknown. Nothing to do anymore.
2938 __ brx(Assembler::notZero, false, Assembler::pt, next);
2939 __ delayed()->nop();
2940 }
2941
2942 // different than before. Cannot keep accurate profile.
2943 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
2944 } else {
2945 // There's a single possible klass at this profile point
2946 assert(exact_klass != NULL, "should be");
2947 if (TypeEntries::is_type_none(current_klass)) {
2948 metadata2reg(exact_klass->constant_encoding(), tmp1);
2949 __ xor3(tmp1, tmp2, tmp1);
2950 __ btst(TypeEntries::type_klass_mask, tmp1);
2951 __ brx(Assembler::zero, false, Assembler::pt, next);
2952 #ifdef ASSERT
2953
2954 {
2955 Label ok;
2956 __ delayed()->btst(TypeEntries::type_mask, tmp2);
2957 __ brx(Assembler::zero, true, Assembler::pt, ok);
2958 __ delayed()->nop();
2959
2960 __ stop("unexpected profiling mismatch");
2961 __ bind(ok);
2962 }
2963 // first time here. Set profile type.
2964 __ or3(tmp2, tmp1, tmp2);
2965 #else
2966 // first time here. Set profile type.
2967 __ delayed()->or3(tmp2, tmp1, tmp2);
2968 #endif
2969
2970 } else {
2971 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2972 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2973
2974 // already unknown. Nothing to do anymore.
2975 __ btst(TypeEntries::type_unknown, tmp2);
2976 __ brx(Assembler::notZero, false, Assembler::pt, next);
2977 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
2978 }
2979 }
2980
2981 __ bind(do_update);
2982 __ st_ptr(tmp2, mdo_addr);
2983
2984 __ bind(next);
2985 }
2986 }
2987
2988 void LIR_Assembler::align_backward_branch_target() {
2989 __ align(OptoLoopAlignment);
2990 }
2991
2992
2993 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2994 // make sure we are expecting a delay
2995 // this has the side effect of clearing the delay state
2996 // so we can use _masm instead of _masm->delayed() to do the
2997 // code generation.
2998 __ delayed();
2999
3000 // make sure we only emit one instruction
3001 int offset = code_offset();
3002 op->delay_op()->emit_code(this);
3003 #ifdef ASSERT
3004 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3005 op->delay_op()->print();
3006 }
3007 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3008 "only one instruction can go in a delay slot");
3009 #endif
3010
3011 // we may also be emitting the call info for the instruction
3012 // which we are the delay slot of.
3013 CodeEmitInfo* call_info = op->call_info();
3014 if (call_info) {
3015 add_call_info(code_offset(), call_info);
3016 }
3017
3018 if (VerifyStackAtCalls) {
3019 _masm->sub(FP, SP, O7);
3020 _masm->cmp(O7, initial_frame_size_in_bytes());
3021 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3022 }
3023 }
3024
3025
3026 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3027 assert(left->is_register(), "can only handle registers");
3028
3029 if (left->is_single_cpu()) {
3030 __ neg(left->as_register(), dest->as_register());
3031 } else if (left->is_single_fpu()) {
3032 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3033 } else if (left->is_double_fpu()) {
3034 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3035 } else {
3036 assert (left->is_double_cpu(), "Must be a long");
3037 Register Rlow = left->as_register_lo();
3038 Register Rhi = left->as_register_hi();
3039 __ sub(G0, Rlow, dest->as_register_lo());
3040 }
3041 }
3042
3043
3044 void LIR_Assembler::fxch(int i) {
3045 Unimplemented();
3046 }
3047
3048 void LIR_Assembler::fld(int i) {
3049 Unimplemented();
3050 }
3051
3052 void LIR_Assembler::ffree(int i) {
3053 Unimplemented();
3054 }
3055
3056 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3057 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3058
3059 // if tmp is invalid, then the function being called doesn't destroy the thread
3060 if (tmp->is_valid()) {
3061 __ save_thread(tmp->as_pointer_register());
3062 }
3063 __ call(dest, relocInfo::runtime_call_type);
3064 __ delayed()->nop();
3065 if (info != NULL) {
3066 add_call_info_here(info);
3067 }
3068 if (tmp->is_valid()) {
3069 __ restore_thread(tmp->as_pointer_register());
3070 }
3071
3072 #ifdef ASSERT
3073 __ verify_thread();
3074 #endif // ASSERT
3075 }
3076
3077
3078 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3079 ShouldNotReachHere();
3080
3081 NEEDS_CLEANUP;
3082 if (type == T_LONG) {
3083 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3084
3085 // (extended to allow indexed as well as constant displaced for JSR-166)
3086 Register idx = noreg; // contains either constant offset or index
3087
3088 int disp = mem_addr->disp();
3089 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3090 if (!Assembler::is_simm13(disp)) {
3091 idx = O7;
3092 __ set(disp, idx);
3093 }
3094 } else {
3095 assert(disp == 0, "not both indexed and disp");
3096 idx = mem_addr->index()->as_register();
3097 }
3098
3099 int null_check_offset = -1;
3100
3101 Register base = mem_addr->base()->as_register();
3102 if (src->is_register() && dest->is_address()) {
3103 // G4 is high half, G5 is low half
3104 // clear the top bits of G5, and scale up G4
3105 __ srl (src->as_register_lo(), 0, G5);
3106 __ sllx(src->as_register_hi(), 32, G4);
3107 // combine the two halves into the 64 bits of G4
3108 __ or3(G4, G5, G4);
3109 null_check_offset = __ offset();
3110 if (idx == noreg) {
3111 __ stx(G4, base, disp);
3112 } else {
3113 __ stx(G4, base, idx);
3114 }
3115 } else if (src->is_address() && dest->is_register()) {
3116 null_check_offset = __ offset();
3117 if (idx == noreg) {
3118 __ ldx(base, disp, G5);
3119 } else {
3120 __ ldx(base, idx, G5);
3121 }
3122 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3123 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3124 } else {
3125 Unimplemented();
3126 }
3127 if (info != NULL) {
3128 add_debug_info_for_null_check(null_check_offset, info);
3129 }
3130
3131 } else {
3132 // use normal move for all other volatiles since they don't need
3133 // special handling to remain atomic.
3134 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3135 }
3136 }
3137
3138 void LIR_Assembler::membar() {
3139 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3140 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3141 }
3142
3143 void LIR_Assembler::membar_acquire() {
3144 // no-op on TSO
3145 }
3146
3147 void LIR_Assembler::membar_release() {
3148 // no-op on TSO
3149 }
3150
3151 void LIR_Assembler::membar_loadload() {
3152 // no-op
3153 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3154 }
3155
3156 void LIR_Assembler::membar_storestore() {
3157 // no-op
3158 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3159 }
3160
3161 void LIR_Assembler::membar_loadstore() {
3162 // no-op
3163 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3164 }
3165
3166 void LIR_Assembler::membar_storeload() {
3167 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3168 }
3169
3170 void LIR_Assembler::on_spin_wait() {
3171 Unimplemented();
3172 }
3173
3174 // Pack two sequential registers containing 32 bit values
3175 // into a single 64 bit register.
3176 // src and src->successor() are packed into dst
3177 // src and dst may be the same register.
3178 // Note: src is destroyed
3179 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3180 Register rs = src->as_register();
3181 Register rd = dst->as_register_lo();
3182 __ sllx(rs, 32, rs);
3183 __ srl(rs->successor(), 0, rs->successor());
3184 __ or3(rs, rs->successor(), rd);
3185 }
3186
3187 // Unpack a 64 bit value in a register into
3188 // two sequential registers.
3189 // src is unpacked into dst and dst->successor()
3190 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3191 Register rs = src->as_register_lo();
3192 Register rd = dst->as_register_hi();
3193 assert_different_registers(rs, rd, rd->successor());
3194 __ srlx(rs, 32, rd);
3195 __ srl (rs, 0, rd->successor());
3196 }
3197
3198 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3199 const LIR_Address* addr = addr_opr->as_address_ptr();
3200 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3201 const Register dest_reg = dest->as_pointer_register();
3202 const Register base_reg = addr->base()->as_pointer_register();
3203
3204 if (patch_code != lir_patch_none) {
3205 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3206 assert(addr->disp() != 0, "must have");
3207 assert(base_reg != G3_scratch, "invariant");
3208 __ patchable_set(0, G3_scratch);
3209 patching_epilog(patch, patch_code, base_reg, info);
3210 assert(dest_reg != G3_scratch, "invariant");
3211 if (addr->index()->is_valid()) {
3212 const Register index_reg = addr->index()->as_pointer_register();
3213 assert(index_reg != G3_scratch, "invariant");
3214 __ add(index_reg, G3_scratch, G3_scratch);
3215 }
3216 __ add(base_reg, G3_scratch, dest_reg);
3217 } else {
3218 if (Assembler::is_simm13(addr->disp())) {
3219 if (addr->index()->is_valid()) {
3220 const Register index_reg = addr->index()->as_pointer_register();
3221 assert(index_reg != G3_scratch, "invariant");
3222 __ add(base_reg, addr->disp(), G3_scratch);
3223 __ add(index_reg, G3_scratch, dest_reg);
3224 } else {
3225 __ add(base_reg, addr->disp(), dest_reg);
3226 }
3227 } else {
3228 __ set(addr->disp(), G3_scratch);
3229 if (addr->index()->is_valid()) {
3230 const Register index_reg = addr->index()->as_pointer_register();
3231 assert(index_reg != G3_scratch, "invariant");
3232 __ add(index_reg, G3_scratch, G3_scratch);
3233 }
3234 __ add(base_reg, G3_scratch, dest_reg);
3235 }
3236 }
3237 }
3238
3239
3240 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3241 assert(result_reg->is_register(), "check");
3242 __ mov(G2_thread, result_reg->as_register());
3243 }
3244
3245 #ifdef ASSERT
3246 // emit run-time assertion
3247 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3248 assert(op->code() == lir_assert, "must be");
3249
3250 if (op->in_opr1()->is_valid()) {
3251 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3252 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3253 } else {
3254 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3255 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3256 }
3257
3258 Label ok;
3259 if (op->condition() != lir_cond_always) {
3260 Assembler::Condition acond;
3261 switch (op->condition()) {
3262 case lir_cond_equal: acond = Assembler::equal; break;
3263 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3264 case lir_cond_less: acond = Assembler::less; break;
3265 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3266 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3267 case lir_cond_greater: acond = Assembler::greater; break;
3268 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3269 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3270 default: ShouldNotReachHere();
3271 };
3272 __ br(acond, false, Assembler::pt, ok);
3273 __ delayed()->nop();
3274 }
3275 if (op->halt()) {
3276 const char* str = __ code_string(op->msg());
3277 __ stop(str);
3278 } else {
3279 breakpoint();
3280 }
3281 __ bind(ok);
3282 }
3283 #endif
3284
3285 void LIR_Assembler::peephole(LIR_List* lir) {
3286 LIR_OpList* inst = lir->instructions_list();
3287 for (int i = 0; i < inst->length(); i++) {
3288 LIR_Op* op = inst->at(i);
3289 switch (op->code()) {
3290 case lir_cond_float_branch:
3291 case lir_branch: {
3292 LIR_OpBranch* branch = op->as_OpBranch();
3293 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3294 LIR_Op* delay_op = NULL;
3295 // we'd like to be able to pull following instructions into
3296 // this slot but we don't know enough to do it safely yet so
3297 // only optimize block to block control flow.
3298 if (LIRFillDelaySlots && branch->block()) {
3299 LIR_Op* prev = inst->at(i - 1);
3300 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3301 // swap previous instruction into delay slot
3302 inst->at_put(i - 1, op);
3303 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3304 #ifndef PRODUCT
3305 if (LIRTracePeephole) {
3306 tty->print_cr("delayed");
3307 inst->at(i - 1)->print();
3308 inst->at(i)->print();
3309 tty->cr();
3310 }
3311 #endif
3312 continue;
3313 }
3314 }
3315
3316 if (!delay_op) {
3317 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3318 }
3319 inst->insert_before(i + 1, delay_op);
3320 break;
3321 }
3322 case lir_static_call:
3323 case lir_virtual_call:
3324 case lir_icvirtual_call:
3325 case lir_optvirtual_call:
3326 case lir_dynamic_call: {
3327 LIR_Op* prev = inst->at(i - 1);
3328 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3329 (op->code() != lir_virtual_call ||
3330 !prev->result_opr()->is_single_cpu() ||
3331 prev->result_opr()->as_register() != O0) &&
3332 LIR_Assembler::is_single_instruction(prev)) {
3333 // Only moves without info can be put into the delay slot.
3334 // Also don't allow the setup of the receiver in the delay
3335 // slot for vtable calls.
3336 inst->at_put(i - 1, op);
3337 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3338 #ifndef PRODUCT
3339 if (LIRTracePeephole) {
3340 tty->print_cr("delayed");
3341 inst->at(i - 1)->print();
3342 inst->at(i)->print();
3343 tty->cr();
3344 }
3345 #endif
3346 } else {
3347 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3348 inst->insert_before(i + 1, delay_op);
3349 i++;
3350 }
3351 break;
3352 }
3353 }
3354 }
3355 }
3356
3357 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3358 LIR_Address* addr = src->as_address_ptr();
3359
3360 assert(data == dest, "swap uses only 2 operands");
3361 assert (code == lir_xchg, "no xadd on sparc");
3362
3363 if (data->type() == T_INT) {
3364 __ swap(as_Address(addr), data->as_register());
3365 } else if (data->is_oop()) {
3366 Register obj = data->as_register();
3367 Register narrow = tmp->as_register();
3368 assert(UseCompressedOops, "swap is 32bit only");
3369 __ encode_heap_oop(obj, narrow);
3370 __ swap(as_Address(addr), narrow);
3371 __ decode_heap_oop(narrow, obj);
3372 } else {
3373 ShouldNotReachHere();
3374 }
3375 }
3376
3377 #undef __