1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && is_evex_instruction) {
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x6E: // movd
774 case 0x7E: // movd
775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
776 debug_only(has_disp32 = true);
777 break;
778
779 case 0xAD: // shrd r, a, %cl
780 case 0xAF: // imul r, a
781 case 0xBE: // movsbl r, a (movsxb)
782 case 0xBF: // movswl r, a (movsxw)
783 case 0xB6: // movzbl r, a (movzxb)
784 case 0xB7: // movzwl r, a (movzxw)
785 case REP16(0x40): // cmovl cc, r, a
786 case 0xB0: // cmpxchgb
787 case 0xB1: // cmpxchg
788 case 0xC1: // xaddl
789 case 0xC7: // cmpxchg8
790 case REP16(0x90): // setcc a
791 debug_only(has_disp32 = true);
792 // fall out of the switch to decode the address
793 break;
794
795 case 0xC4: // pinsrw r, a, #8
796 debug_only(has_disp32 = true);
797 case 0xC5: // pextrw r, r, #8
798 tail_size = 1; // the imm8
799 break;
800
801 case 0xAC: // shrd r, a, #8
802 debug_only(has_disp32 = true);
803 tail_size = 1; // the imm8
804 break;
805
806 case REP16(0x80): // jcc rdisp32
807 if (which == end_pc_operand) return ip + 4;
808 assert(which == call32_operand, "jcc has no disp32 or imm");
809 return ip;
810 default:
811 ShouldNotReachHere();
812 }
813 break;
814
815 case 0x81: // addl a, #32; addl r, #32
816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
817 // on 32bit in the case of cmpl, the imm might be an oop
818 tail_size = 4;
819 debug_only(has_disp32 = true); // has both kinds of operands!
820 break;
821
822 case 0x83: // addl a, #8; addl r, #8
823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 tail_size = 1;
826 break;
827
828 case 0x9B:
829 switch (0xFF & *ip++) {
830 case 0xD9: // fnstcw a
831 debug_only(has_disp32 = true);
832 break;
833 default:
834 ShouldNotReachHere();
835 }
836 break;
837
838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
839 case REP4(0x10): // adc...
840 case REP4(0x20): // and...
841 case REP4(0x30): // xor...
842 case REP4(0x08): // or...
843 case REP4(0x18): // sbb...
844 case REP4(0x28): // sub...
845 case 0xF7: // mull a
846 case 0x8D: // lea r, a
847 case 0x87: // xchg r, a
848 case REP4(0x38): // cmp...
849 case 0x85: // test r, a
850 debug_only(has_disp32 = true); // has both kinds of operands!
851 break;
852
853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
854 case 0xC6: // movb a, #8
855 case 0x80: // cmpb a, #8
856 case 0x6B: // imul r, a, #8
857 debug_only(has_disp32 = true); // has both kinds of operands!
858 tail_size = 1; // the imm8
859 break;
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 // First byte
881 if ((0xFF & *inst) == VEX_3bytes) {
882 ip++; // third byte
883 is_64bit = ((VEX_W & *ip) == VEX_W);
884 }
885 ip++; // opcode
886 // To find the end of instruction (which == end_pc_operand).
887 switch (0xFF & *ip) {
888 case 0x61: // pcmpestri r, r/a, #8
889 case 0x70: // pshufd r, r/a, #8
890 case 0x73: // psrldq r, #8
891 tail_size = 1; // the imm8
892 break;
893 default:
894 break;
895 }
896 ip++; // skip opcode
897 debug_only(has_disp32 = true); // has both kinds of operands!
898 break;
899
900 case 0x62: // EVEX_4bytes
901 assert((UseAVX > 0), "shouldn't have EVEX prefix");
902 assert(ip == inst+1, "no prefixes allowed");
903 // no EVEX collisions, all instructions that have 0x62 opcodes
904 // have EVEX versions and are subopcodes of 0x66
905 ip++; // skip P0 and exmaine W in P1
906 is_64bit = ((VEX_W & *ip) == VEX_W);
907 ip++; // move to P2
908 ip++; // skip P2, move to opcode
909 // To find the end of instruction (which == end_pc_operand).
910 switch (0xFF & *ip) {
911 case 0x61: // pcmpestri r, r/a, #8
912 case 0x70: // pshufd r, r/a, #8
913 case 0x73: // psrldq r, #8
914 tail_size = 1; // the imm8
915 break;
916 default:
917 break;
918 }
919 ip++; // skip opcode
920 debug_only(has_disp32 = true); // has both kinds of operands!
921 break;
922
923 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
924 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
925 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
926 case 0xDD: // fld_d a; fst_d a; fstp_d a
927 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
928 case 0xDF: // fild_d a; fistp_d a
929 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
930 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
931 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
932 debug_only(has_disp32 = true);
933 break;
934
935 case 0xE8: // call rdisp32
936 case 0xE9: // jmp rdisp32
937 if (which == end_pc_operand) return ip + 4;
938 assert(which == call32_operand, "call has no disp32 or imm");
939 return ip;
940
941 case 0xF0: // Lock
942 assert(os::is_MP(), "only on MP");
943 goto again_after_prefix;
944
945 case 0xF3: // For SSE
946 case 0xF2: // For SSE2
947 switch (0xFF & *ip++) {
948 case REX:
949 case REX_B:
950 case REX_X:
951 case REX_XB:
952 case REX_R:
953 case REX_RB:
954 case REX_RX:
955 case REX_RXB:
956 case REX_W:
957 case REX_WB:
958 case REX_WX:
959 case REX_WXB:
960 case REX_WR:
961 case REX_WRB:
962 case REX_WRX:
963 case REX_WRXB:
964 NOT_LP64(assert(false, "found 64bit prefix"));
965 ip++;
966 default:
967 ip++;
968 }
969 debug_only(has_disp32 = true); // has both kinds of operands!
970 break;
971
972 default:
973 ShouldNotReachHere();
974
975 #undef REP8
976 #undef REP16
977 }
978
979 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
980 #ifdef _LP64
981 assert(which != imm_operand, "instruction is not a movq reg, imm64");
982 #else
983 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
984 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
985 #endif // LP64
986 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
987
988 // parse the output of emit_operand
989 int op2 = 0xFF & *ip++;
990 int base = op2 & 0x07;
991 int op3 = -1;
992 const int b100 = 4;
993 const int b101 = 5;
994 if (base == b100 && (op2 >> 6) != 3) {
995 op3 = 0xFF & *ip++;
996 base = op3 & 0x07; // refetch the base
997 }
998 // now ip points at the disp (if any)
999
1000 switch (op2 >> 6) {
1001 case 0:
1002 // [00 reg 100][ss index base]
1003 // [00 reg 100][00 100 esp]
1004 // [00 reg base]
1005 // [00 reg 100][ss index 101][disp32]
1006 // [00 reg 101] [disp32]
1007
1008 if (base == b101) {
1009 if (which == disp32_operand)
1010 return ip; // caller wants the disp32
1011 ip += 4; // skip the disp32
1012 }
1013 break;
1014
1015 case 1:
1016 // [01 reg 100][ss index base][disp8]
1017 // [01 reg 100][00 100 esp][disp8]
1018 // [01 reg base] [disp8]
1019 ip += 1; // skip the disp8
1020 break;
1021
1022 case 2:
1023 // [10 reg 100][ss index base][disp32]
1024 // [10 reg 100][00 100 esp][disp32]
1025 // [10 reg base] [disp32]
1026 if (which == disp32_operand)
1027 return ip; // caller wants the disp32
1028 ip += 4; // skip the disp32
1029 break;
1030
1031 case 3:
1032 // [11 reg base] (not a memory addressing mode)
1033 break;
1034 }
1035
1036 if (which == end_pc_operand) {
1037 return ip + tail_size;
1038 }
1039
1040 #ifdef _LP64
1041 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1042 #else
1043 assert(which == imm_operand, "instruction has only an imm field");
1044 #endif // LP64
1045 return ip;
1046 }
1047
1048 address Assembler::locate_next_instruction(address inst) {
1049 // Secretly share code with locate_operand:
1050 return locate_operand(inst, end_pc_operand);
1051 }
1052
1053
1054 #ifdef ASSERT
1055 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1056 address inst = inst_mark();
1057 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1058 address opnd;
1059
1060 Relocation* r = rspec.reloc();
1061 if (r->type() == relocInfo::none) {
1062 return;
1063 } else if (r->is_call() || format == call32_operand) {
1064 // assert(format == imm32_operand, "cannot specify a nonzero format");
1065 opnd = locate_operand(inst, call32_operand);
1066 } else if (r->is_data()) {
1067 assert(format == imm_operand || format == disp32_operand
1068 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1069 opnd = locate_operand(inst, (WhichOperand)format);
1070 } else {
1071 assert(format == imm_operand, "cannot specify a format");
1072 return;
1073 }
1074 assert(opnd == pc(), "must put operand where relocs can find it");
1075 }
1076 #endif // ASSERT
1077
1078 void Assembler::emit_operand32(Register reg, Address adr) {
1079 assert(reg->encoding() < 8, "no extended registers");
1080 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1081 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1082 adr._rspec);
1083 }
1084
1085 void Assembler::emit_operand(Register reg, Address adr,
1086 int rip_relative_correction) {
1087 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1088 adr._rspec,
1089 rip_relative_correction);
1090 }
1091
1092 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1093 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1094 adr._rspec);
1095 }
1096
1097 // MMX operations
1098 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1101 }
1102
1103 // work around gcc (3.2.1-7a) bug
1104 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1105 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1106 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1107 }
1108
1109
1110 void Assembler::emit_farith(int b1, int b2, int i) {
1111 assert(isByte(b1) && isByte(b2), "wrong opcode");
1112 assert(0 <= i && i < 8, "illegal stack offset");
1113 emit_int8(b1);
1114 emit_int8(b2 + i);
1115 }
1116
1117
1118 // Now the Assembler instructions (identical for 32/64 bits)
1119
1120 void Assembler::adcl(Address dst, int32_t imm32) {
1121 InstructionMark im(this);
1122 prefix(dst);
1123 emit_arith_operand(0x81, rdx, dst, imm32);
1124 }
1125
1126 void Assembler::adcl(Address dst, Register src) {
1127 InstructionMark im(this);
1128 prefix(dst, src);
1129 emit_int8(0x11);
1130 emit_operand(src, dst);
1131 }
1132
1133 void Assembler::adcl(Register dst, int32_t imm32) {
1134 prefix(dst);
1135 emit_arith(0x81, 0xD0, dst, imm32);
1136 }
1137
1138 void Assembler::adcl(Register dst, Address src) {
1139 InstructionMark im(this);
1140 prefix(src, dst);
1141 emit_int8(0x13);
1142 emit_operand(dst, src);
1143 }
1144
1145 void Assembler::adcl(Register dst, Register src) {
1146 (void) prefix_and_encode(dst->encoding(), src->encoding());
1147 emit_arith(0x13, 0xC0, dst, src);
1148 }
1149
1150 void Assembler::addl(Address dst, int32_t imm32) {
1151 InstructionMark im(this);
1152 prefix(dst);
1153 emit_arith_operand(0x81, rax, dst, imm32);
1154 }
1155
1156 void Assembler::addl(Address dst, Register src) {
1157 InstructionMark im(this);
1158 prefix(dst, src);
1159 emit_int8(0x01);
1160 emit_operand(src, dst);
1161 }
1162
1163 void Assembler::addl(Register dst, int32_t imm32) {
1164 prefix(dst);
1165 emit_arith(0x81, 0xC0, dst, imm32);
1166 }
1167
1168 void Assembler::addl(Register dst, Address src) {
1169 InstructionMark im(this);
1170 prefix(src, dst);
1171 emit_int8(0x03);
1172 emit_operand(dst, src);
1173 }
1174
1175 void Assembler::addl(Register dst, Register src) {
1176 (void) prefix_and_encode(dst->encoding(), src->encoding());
1177 emit_arith(0x03, 0xC0, dst, src);
1178 }
1179
1180 void Assembler::addr_nop_4() {
1181 assert(UseAddressNop, "no CPU support");
1182 // 4 bytes: NOP DWORD PTR [EAX+0]
1183 emit_int8(0x0F);
1184 emit_int8(0x1F);
1185 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1186 emit_int8(0); // 8-bits offset (1 byte)
1187 }
1188
1189 void Assembler::addr_nop_5() {
1190 assert(UseAddressNop, "no CPU support");
1191 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1192 emit_int8(0x0F);
1193 emit_int8(0x1F);
1194 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1195 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1196 emit_int8(0); // 8-bits offset (1 byte)
1197 }
1198
1199 void Assembler::addr_nop_7() {
1200 assert(UseAddressNop, "no CPU support");
1201 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1202 emit_int8(0x0F);
1203 emit_int8(0x1F);
1204 emit_int8((unsigned char)0x80);
1205 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1206 emit_int32(0); // 32-bits offset (4 bytes)
1207 }
1208
1209 void Assembler::addr_nop_8() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8((unsigned char)0x84);
1215 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1216 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1217 emit_int32(0); // 32-bits offset (4 bytes)
1218 }
1219
1220 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1221 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1222 if (VM_Version::supports_evex()) {
1223 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1224 } else {
1225 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1226 }
1227 }
1228
1229 void Assembler::addsd(XMMRegister dst, Address src) {
1230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1231 if (VM_Version::supports_evex()) {
1232 tuple_type = EVEX_T1S;
1233 input_size_in_bits = EVEX_64bit;
1234 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1235 } else {
1236 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1237 }
1238 }
1239
1240 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1242 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1243 }
1244
1245 void Assembler::addss(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1247 if (VM_Version::supports_evex()) {
1248 tuple_type = EVEX_T1S;
1249 input_size_in_bits = EVEX_32bit;
1250 }
1251 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1252 }
1253
1254 void Assembler::aesdec(XMMRegister dst, Address src) {
1255 assert(VM_Version::supports_aes(), "");
1256 InstructionMark im(this);
1257 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1258 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1259 emit_int8((unsigned char)0xDE);
1260 emit_operand(dst, src);
1261 }
1262
1263 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1264 assert(VM_Version::supports_aes(), "");
1265 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1266 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1267 emit_int8((unsigned char)0xDE);
1268 emit_int8(0xC0 | encode);
1269 }
1270
1271 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1272 assert(VM_Version::supports_aes(), "");
1273 InstructionMark im(this);
1274 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1275 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1276 emit_int8((unsigned char)0xDF);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1281 assert(VM_Version::supports_aes(), "");
1282 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1283 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1284 emit_int8((unsigned char)0xDF);
1285 emit_int8((unsigned char)(0xC0 | encode));
1286 }
1287
1288 void Assembler::aesenc(XMMRegister dst, Address src) {
1289 assert(VM_Version::supports_aes(), "");
1290 InstructionMark im(this);
1291 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1292 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1293 emit_int8((unsigned char)0xDC);
1294 emit_operand(dst, src);
1295 }
1296
1297 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1298 assert(VM_Version::supports_aes(), "");
1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1300 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1301 emit_int8((unsigned char)0xDC);
1302 emit_int8(0xC0 | encode);
1303 }
1304
1305 void Assembler::aesenclast(XMMRegister dst, Address src) {
1306 assert(VM_Version::supports_aes(), "");
1307 InstructionMark im(this);
1308 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1309 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1310 emit_int8((unsigned char)0xDD);
1311 emit_operand(dst, src);
1312 }
1313
1314 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1315 assert(VM_Version::supports_aes(), "");
1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1317 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1318 emit_int8((unsigned char)0xDD);
1319 emit_int8((unsigned char)(0xC0 | encode));
1320 }
1321
1322
1323 void Assembler::andl(Address dst, int32_t imm32) {
1324 InstructionMark im(this);
1325 prefix(dst);
1326 emit_int8((unsigned char)0x81);
1327 emit_operand(rsp, dst, 4);
1328 emit_int32(imm32);
1329 }
1330
1331 void Assembler::andl(Register dst, int32_t imm32) {
1332 prefix(dst);
1333 emit_arith(0x81, 0xE0, dst, imm32);
1334 }
1335
1336 void Assembler::andl(Register dst, Address src) {
1337 InstructionMark im(this);
1338 prefix(src, dst);
1339 emit_int8(0x23);
1340 emit_operand(dst, src);
1341 }
1342
1343 void Assembler::andl(Register dst, Register src) {
1344 (void) prefix_and_encode(dst->encoding(), src->encoding());
1345 emit_arith(0x23, 0xC0, dst, src);
1346 }
1347
1348 void Assembler::andnl(Register dst, Register src1, Register src2) {
1349 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1350 int encode = vex_prefix_0F38_and_encode_legacy(dst, src1, src2, false);
1351 emit_int8((unsigned char)0xF2);
1352 emit_int8((unsigned char)(0xC0 | encode));
1353 }
1354
1355 void Assembler::andnl(Register dst, Register src1, Address src2) {
1356 InstructionMark im(this);
1357 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1358 vex_prefix_0F38_legacy(dst, src1, src2, false);
1359 emit_int8((unsigned char)0xF2);
1360 emit_operand(dst, src2);
1361 }
1362
1363 void Assembler::bsfl(Register dst, Register src) {
1364 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1365 emit_int8(0x0F);
1366 emit_int8((unsigned char)0xBC);
1367 emit_int8((unsigned char)(0xC0 | encode));
1368 }
1369
1370 void Assembler::bsrl(Register dst, Register src) {
1371 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1372 emit_int8(0x0F);
1373 emit_int8((unsigned char)0xBD);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::bswapl(Register reg) { // bswap
1378 int encode = prefix_and_encode(reg->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)(0xC8 | encode));
1381 }
1382
1383 void Assembler::blsil(Register dst, Register src) {
1384 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1385 int encode = vex_prefix_0F38_and_encode_legacy(rbx, dst, src, false);
1386 emit_int8((unsigned char)0xF3);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::blsil(Register dst, Address src) {
1391 InstructionMark im(this);
1392 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1393 vex_prefix_0F38_legacy(rbx, dst, src, false);
1394 emit_int8((unsigned char)0xF3);
1395 emit_operand(rbx, src);
1396 }
1397
1398 void Assembler::blsmskl(Register dst, Register src) {
1399 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1400 int encode = vex_prefix_0F38_and_encode_legacy(rdx, dst, src, false);
1401 emit_int8((unsigned char)0xF3);
1402 emit_int8((unsigned char)(0xC0 | encode));
1403 }
1404
1405 void Assembler::blsmskl(Register dst, Address src) {
1406 InstructionMark im(this);
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 vex_prefix_0F38(rdx, dst, src, false);
1409 emit_int8((unsigned char)0xF3);
1410 emit_operand(rdx, src);
1411 }
1412
1413 void Assembler::blsrl(Register dst, Register src) {
1414 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1415 int encode = vex_prefix_0F38_and_encode_legacy(rcx, dst, src, false);
1416 emit_int8((unsigned char)0xF3);
1417 emit_int8((unsigned char)(0xC0 | encode));
1418 }
1419
1420 void Assembler::blsrl(Register dst, Address src) {
1421 InstructionMark im(this);
1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1423 vex_prefix_0F38_legacy(rcx, dst, src, false);
1424 emit_int8((unsigned char)0xF3);
1425 emit_operand(rcx, src);
1426 }
1427
1428 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1429 // suspect disp32 is always good
1430 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1431
1432 if (L.is_bound()) {
1433 const int long_size = 5;
1434 int offs = (int)( target(L) - pc() );
1435 assert(offs <= 0, "assembler error");
1436 InstructionMark im(this);
1437 // 1110 1000 #32-bit disp
1438 emit_int8((unsigned char)0xE8);
1439 emit_data(offs - long_size, rtype, operand);
1440 } else {
1441 InstructionMark im(this);
1442 // 1110 1000 #32-bit disp
1443 L.add_patch_at(code(), locator());
1444
1445 emit_int8((unsigned char)0xE8);
1446 emit_data(int(0), rtype, operand);
1447 }
1448 }
1449
1450 void Assembler::call(Register dst) {
1451 int encode = prefix_and_encode(dst->encoding());
1452 emit_int8((unsigned char)0xFF);
1453 emit_int8((unsigned char)(0xD0 | encode));
1454 }
1455
1456
1457 void Assembler::call(Address adr) {
1458 InstructionMark im(this);
1459 prefix(adr);
1460 emit_int8((unsigned char)0xFF);
1461 emit_operand(rdx, adr);
1462 }
1463
1464 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1465 assert(entry != NULL, "call most probably wrong");
1466 InstructionMark im(this);
1467 emit_int8((unsigned char)0xE8);
1468 intptr_t disp = entry - (pc() + sizeof(int32_t));
1469 assert(is_simm32(disp), "must be 32bit offset (call2)");
1470 // Technically, should use call32_operand, but this format is
1471 // implied by the fact that we're emitting a call instruction.
1472
1473 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1474 emit_data((int) disp, rspec, operand);
1475 }
1476
1477 void Assembler::cdql() {
1478 emit_int8((unsigned char)0x99);
1479 }
1480
1481 void Assembler::cld() {
1482 emit_int8((unsigned char)0xFC);
1483 }
1484
1485 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1486 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1487 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1488 emit_int8(0x0F);
1489 emit_int8(0x40 | cc);
1490 emit_int8((unsigned char)(0xC0 | encode));
1491 }
1492
1493
1494 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1495 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1496 prefix(src, dst);
1497 emit_int8(0x0F);
1498 emit_int8(0x40 | cc);
1499 emit_operand(dst, src);
1500 }
1501
1502 void Assembler::cmpb(Address dst, int imm8) {
1503 InstructionMark im(this);
1504 prefix(dst);
1505 emit_int8((unsigned char)0x80);
1506 emit_operand(rdi, dst, 1);
1507 emit_int8(imm8);
1508 }
1509
1510 void Assembler::cmpl(Address dst, int32_t imm32) {
1511 InstructionMark im(this);
1512 prefix(dst);
1513 emit_int8((unsigned char)0x81);
1514 emit_operand(rdi, dst, 4);
1515 emit_int32(imm32);
1516 }
1517
1518 void Assembler::cmpl(Register dst, int32_t imm32) {
1519 prefix(dst);
1520 emit_arith(0x81, 0xF8, dst, imm32);
1521 }
1522
1523 void Assembler::cmpl(Register dst, Register src) {
1524 (void) prefix_and_encode(dst->encoding(), src->encoding());
1525 emit_arith(0x3B, 0xC0, dst, src);
1526 }
1527
1528
1529 void Assembler::cmpl(Register dst, Address src) {
1530 InstructionMark im(this);
1531 prefix(src, dst);
1532 emit_int8((unsigned char)0x3B);
1533 emit_operand(dst, src);
1534 }
1535
1536 void Assembler::cmpw(Address dst, int imm16) {
1537 InstructionMark im(this);
1538 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1539 emit_int8(0x66);
1540 emit_int8((unsigned char)0x81);
1541 emit_operand(rdi, dst, 2);
1542 emit_int16(imm16);
1543 }
1544
1545 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1546 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1547 // The ZF is set if the compared values were equal, and cleared otherwise.
1548 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1549 InstructionMark im(this);
1550 prefix(adr, reg);
1551 emit_int8(0x0F);
1552 emit_int8((unsigned char)0xB1);
1553 emit_operand(reg, adr);
1554 }
1555
1556 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1557 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1558 // The ZF is set if the compared values were equal, and cleared otherwise.
1559 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1560 InstructionMark im(this);
1561 prefix(adr, reg, true);
1562 emit_int8(0x0F);
1563 emit_int8((unsigned char)0xB0);
1564 emit_operand(reg, adr);
1565 }
1566
1567 void Assembler::comisd(XMMRegister dst, Address src) {
1568 // NOTE: dbx seems to decode this as comiss even though the
1569 // 0x66 is there. Strangly ucomisd comes out correct
1570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1571 if (VM_Version::supports_evex()) {
1572 tuple_type = EVEX_T1S;
1573 input_size_in_bits = EVEX_64bit;
1574 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1575 } else {
1576 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1577 }
1578 }
1579
1580 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1581 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1582 if (VM_Version::supports_evex()) {
1583 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1584 } else {
1585 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1586 }
1587 }
1588
1589 void Assembler::comiss(XMMRegister dst, Address src) {
1590 if (VM_Version::supports_evex()) {
1591 tuple_type = EVEX_T1S;
1592 input_size_in_bits = EVEX_32bit;
1593 }
1594 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1595 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1596 }
1597
1598 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1599 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1600 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1601 }
1602
1603 void Assembler::cpuid() {
1604 emit_int8(0x0F);
1605 emit_int8((unsigned char)0xA2);
1606 }
1607
1608 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1610 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1611 }
1612
1613 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1614 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1615 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1616 }
1617
1618 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1620 if (VM_Version::supports_evex()) {
1621 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1622 } else {
1623 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1624 }
1625 }
1626
1627 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1629 if (VM_Version::supports_evex()) {
1630 tuple_type = EVEX_T1F;
1631 input_size_in_bits = EVEX_64bit;
1632 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1633 } else {
1634 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1635 }
1636 }
1637
1638 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1639 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1640 int encode = 0;
1641 if (VM_Version::supports_evex()) {
1642 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
1643 } else {
1644 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false);
1645 }
1646 emit_int8(0x2A);
1647 emit_int8((unsigned char)(0xC0 | encode));
1648 }
1649
1650 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1651 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1652 if (VM_Version::supports_evex()) {
1653 tuple_type = EVEX_T1S;
1654 input_size_in_bits = EVEX_32bit;
1655 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true);
1656 } else {
1657 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1658 }
1659 }
1660
1661 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1662 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1664 emit_int8(0x2A);
1665 emit_int8((unsigned char)(0xC0 | encode));
1666 }
1667
1668 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1669 if (VM_Version::supports_evex()) {
1670 tuple_type = EVEX_T1S;
1671 input_size_in_bits = EVEX_32bit;
1672 }
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1675 }
1676
1677 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1679 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1680 }
1681
1682 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1683 if (VM_Version::supports_evex()) {
1684 tuple_type = EVEX_T1S;
1685 input_size_in_bits = EVEX_32bit;
1686 }
1687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1688 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1689 }
1690
1691
1692 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1694 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1695 emit_int8(0x2C);
1696 emit_int8((unsigned char)(0xC0 | encode));
1697 }
1698
1699 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1700 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1701 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
1702 emit_int8(0x2C);
1703 emit_int8((unsigned char)(0xC0 | encode));
1704 }
1705
1706 void Assembler::decl(Address dst) {
1707 // Don't use it directly. Use MacroAssembler::decrement() instead.
1708 InstructionMark im(this);
1709 prefix(dst);
1710 emit_int8((unsigned char)0xFF);
1711 emit_operand(rcx, dst);
1712 }
1713
1714 void Assembler::divsd(XMMRegister dst, Address src) {
1715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1716 if (VM_Version::supports_evex()) {
1717 tuple_type = EVEX_T1S;
1718 input_size_in_bits = EVEX_64bit;
1719 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1720 } else {
1721 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1722 }
1723 }
1724
1725 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 if (VM_Version::supports_evex()) {
1728 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1729 } else {
1730 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1731 }
1732 }
1733
1734 void Assembler::divss(XMMRegister dst, Address src) {
1735 if (VM_Version::supports_evex()) {
1736 tuple_type = EVEX_T1S;
1737 input_size_in_bits = EVEX_32bit;
1738 }
1739 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1740 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1741 }
1742
1743 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1744 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1745 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1746 }
1747
1748 void Assembler::emms() {
1749 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1750 emit_int8(0x0F);
1751 emit_int8(0x77);
1752 }
1753
1754 void Assembler::hlt() {
1755 emit_int8((unsigned char)0xF4);
1756 }
1757
1758 void Assembler::idivl(Register src) {
1759 int encode = prefix_and_encode(src->encoding());
1760 emit_int8((unsigned char)0xF7);
1761 emit_int8((unsigned char)(0xF8 | encode));
1762 }
1763
1764 void Assembler::divl(Register src) { // Unsigned
1765 int encode = prefix_and_encode(src->encoding());
1766 emit_int8((unsigned char)0xF7);
1767 emit_int8((unsigned char)(0xF0 | encode));
1768 }
1769
1770 void Assembler::imull(Register dst, Register src) {
1771 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1772 emit_int8(0x0F);
1773 emit_int8((unsigned char)0xAF);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777
1778 void Assembler::imull(Register dst, Register src, int value) {
1779 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1780 if (is8bit(value)) {
1781 emit_int8(0x6B);
1782 emit_int8((unsigned char)(0xC0 | encode));
1783 emit_int8(value & 0xFF);
1784 } else {
1785 emit_int8(0x69);
1786 emit_int8((unsigned char)(0xC0 | encode));
1787 emit_int32(value);
1788 }
1789 }
1790
1791 void Assembler::imull(Register dst, Address src) {
1792 InstructionMark im(this);
1793 prefix(src, dst);
1794 emit_int8(0x0F);
1795 emit_int8((unsigned char) 0xAF);
1796 emit_operand(dst, src);
1797 }
1798
1799
1800 void Assembler::incl(Address dst) {
1801 // Don't use it directly. Use MacroAssembler::increment() instead.
1802 InstructionMark im(this);
1803 prefix(dst);
1804 emit_int8((unsigned char)0xFF);
1805 emit_operand(rax, dst);
1806 }
1807
1808 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1809 InstructionMark im(this);
1810 assert((0 <= cc) && (cc < 16), "illegal cc");
1811 if (L.is_bound()) {
1812 address dst = target(L);
1813 assert(dst != NULL, "jcc most probably wrong");
1814
1815 const int short_size = 2;
1816 const int long_size = 6;
1817 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1818 if (maybe_short && is8bit(offs - short_size)) {
1819 // 0111 tttn #8-bit disp
1820 emit_int8(0x70 | cc);
1821 emit_int8((offs - short_size) & 0xFF);
1822 } else {
1823 // 0000 1111 1000 tttn #32-bit disp
1824 assert(is_simm32(offs - long_size),
1825 "must be 32bit offset (call4)");
1826 emit_int8(0x0F);
1827 emit_int8((unsigned char)(0x80 | cc));
1828 emit_int32(offs - long_size);
1829 }
1830 } else {
1831 // Note: could eliminate cond. jumps to this jump if condition
1832 // is the same however, seems to be rather unlikely case.
1833 // Note: use jccb() if label to be bound is very close to get
1834 // an 8-bit displacement
1835 L.add_patch_at(code(), locator());
1836 emit_int8(0x0F);
1837 emit_int8((unsigned char)(0x80 | cc));
1838 emit_int32(0);
1839 }
1840 }
1841
1842 void Assembler::jccb(Condition cc, Label& L) {
1843 if (L.is_bound()) {
1844 const int short_size = 2;
1845 address entry = target(L);
1846 #ifdef ASSERT
1847 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1848 intptr_t delta = short_branch_delta();
1849 if (delta != 0) {
1850 dist += (dist < 0 ? (-delta) :delta);
1851 }
1852 assert(is8bit(dist), "Dispacement too large for a short jmp");
1853 #endif
1854 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1855 // 0111 tttn #8-bit disp
1856 emit_int8(0x70 | cc);
1857 emit_int8((offs - short_size) & 0xFF);
1858 } else {
1859 InstructionMark im(this);
1860 L.add_patch_at(code(), locator());
1861 emit_int8(0x70 | cc);
1862 emit_int8(0);
1863 }
1864 }
1865
1866 void Assembler::jmp(Address adr) {
1867 InstructionMark im(this);
1868 prefix(adr);
1869 emit_int8((unsigned char)0xFF);
1870 emit_operand(rsp, adr);
1871 }
1872
1873 void Assembler::jmp(Label& L, bool maybe_short) {
1874 if (L.is_bound()) {
1875 address entry = target(L);
1876 assert(entry != NULL, "jmp most probably wrong");
1877 InstructionMark im(this);
1878 const int short_size = 2;
1879 const int long_size = 5;
1880 intptr_t offs = entry - pc();
1881 if (maybe_short && is8bit(offs - short_size)) {
1882 emit_int8((unsigned char)0xEB);
1883 emit_int8((offs - short_size) & 0xFF);
1884 } else {
1885 emit_int8((unsigned char)0xE9);
1886 emit_int32(offs - long_size);
1887 }
1888 } else {
1889 // By default, forward jumps are always 32-bit displacements, since
1890 // we can't yet know where the label will be bound. If you're sure that
1891 // the forward jump will not run beyond 256 bytes, use jmpb to
1892 // force an 8-bit displacement.
1893 InstructionMark im(this);
1894 L.add_patch_at(code(), locator());
1895 emit_int8((unsigned char)0xE9);
1896 emit_int32(0);
1897 }
1898 }
1899
1900 void Assembler::jmp(Register entry) {
1901 int encode = prefix_and_encode(entry->encoding());
1902 emit_int8((unsigned char)0xFF);
1903 emit_int8((unsigned char)(0xE0 | encode));
1904 }
1905
1906 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1907 InstructionMark im(this);
1908 emit_int8((unsigned char)0xE9);
1909 assert(dest != NULL, "must have a target");
1910 intptr_t disp = dest - (pc() + sizeof(int32_t));
1911 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1912 emit_data(disp, rspec.reloc(), call32_operand);
1913 }
1914
1915 void Assembler::jmpb(Label& L) {
1916 if (L.is_bound()) {
1917 const int short_size = 2;
1918 address entry = target(L);
1919 assert(entry != NULL, "jmp most probably wrong");
1920 #ifdef ASSERT
1921 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1922 intptr_t delta = short_branch_delta();
1923 if (delta != 0) {
1924 dist += (dist < 0 ? (-delta) :delta);
1925 }
1926 assert(is8bit(dist), "Dispacement too large for a short jmp");
1927 #endif
1928 intptr_t offs = entry - pc();
1929 emit_int8((unsigned char)0xEB);
1930 emit_int8((offs - short_size) & 0xFF);
1931 } else {
1932 InstructionMark im(this);
1933 L.add_patch_at(code(), locator());
1934 emit_int8((unsigned char)0xEB);
1935 emit_int8(0);
1936 }
1937 }
1938
1939 void Assembler::ldmxcsr( Address src) {
1940 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1941 InstructionMark im(this);
1942 prefix(src);
1943 emit_int8(0x0F);
1944 emit_int8((unsigned char)0xAE);
1945 emit_operand(as_Register(2), src);
1946 }
1947
1948 void Assembler::leal(Register dst, Address src) {
1949 InstructionMark im(this);
1950 #ifdef _LP64
1951 emit_int8(0x67); // addr32
1952 prefix(src, dst);
1953 #endif // LP64
1954 emit_int8((unsigned char)0x8D);
1955 emit_operand(dst, src);
1956 }
1957
1958 void Assembler::lfence() {
1959 emit_int8(0x0F);
1960 emit_int8((unsigned char)0xAE);
1961 emit_int8((unsigned char)0xE8);
1962 }
1963
1964 void Assembler::lock() {
1965 emit_int8((unsigned char)0xF0);
1966 }
1967
1968 void Assembler::lzcntl(Register dst, Register src) {
1969 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1970 emit_int8((unsigned char)0xF3);
1971 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1972 emit_int8(0x0F);
1973 emit_int8((unsigned char)0xBD);
1974 emit_int8((unsigned char)(0xC0 | encode));
1975 }
1976
1977 // Emit mfence instruction
1978 void Assembler::mfence() {
1979 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xAE);
1982 emit_int8((unsigned char)0xF0);
1983 }
1984
1985 void Assembler::mov(Register dst, Register src) {
1986 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1987 }
1988
1989 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1991 if (VM_Version::supports_evex()) {
1992 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true);
1993 } else {
1994 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1995 }
1996 }
1997
1998 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1999 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2000 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2001 }
2002
2003 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2005 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F,
2006 false, AVX_128bit);
2007 emit_int8(0x16);
2008 emit_int8((unsigned char)(0xC0 | encode));
2009 }
2010
2011 void Assembler::movb(Register dst, Address src) {
2012 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2013 InstructionMark im(this);
2014 prefix(src, dst, true);
2015 emit_int8((unsigned char)0x8A);
2016 emit_operand(dst, src);
2017 }
2018
2019 void Assembler::kmovq(KRegister dst, KRegister src) {
2020 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2021 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2022 true, VEX_OPCODE_0F, true);
2023 emit_int8((unsigned char)0x90);
2024 emit_int8((unsigned char)(0xC0 | encode));
2025 }
2026
2027 void Assembler::kmovq(KRegister dst, Address src) {
2028 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2029 int dst_enc = dst->encoding();
2030 int nds_enc = 0;
2031 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2032 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2033 emit_int8((unsigned char)0x90);
2034 emit_operand((Register)dst, src);
2035 }
2036
2037 void Assembler::kmovq(Address dst, KRegister src) {
2038 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2039 int src_enc = src->encoding();
2040 int nds_enc = 0;
2041 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2042 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2043 emit_int8((unsigned char)0x90);
2044 emit_operand((Register)src, dst);
2045 }
2046
2047 void Assembler::kmovql(KRegister dst, Register src) {
2048 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2049 bool supports_bw = VM_Version::supports_avx512bw();
2050 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2051 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true,
2052 VEX_OPCODE_0F, supports_bw);
2053 emit_int8((unsigned char)0x92);
2054 emit_int8((unsigned char)(0xC0 | encode));
2055 }
2056
2057 void Assembler::kmovdl(KRegister dst, Register src) {
2058 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2059 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2060 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false);
2061 emit_int8((unsigned char)0x92);
2062 emit_int8((unsigned char)(0xC0 | encode));
2063 }
2064
2065 void Assembler::movb(Address dst, int imm8) {
2066 InstructionMark im(this);
2067 prefix(dst);
2068 emit_int8((unsigned char)0xC6);
2069 emit_operand(rax, dst, 1);
2070 emit_int8(imm8);
2071 }
2072
2073
2074 void Assembler::movb(Address dst, Register src) {
2075 assert(src->has_byte_register(), "must have byte register");
2076 InstructionMark im(this);
2077 prefix(dst, src, true);
2078 emit_int8((unsigned char)0x88);
2079 emit_operand(src, dst);
2080 }
2081
2082 void Assembler::movdl(XMMRegister dst, Register src) {
2083 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2084 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true);
2085 emit_int8(0x6E);
2086 emit_int8((unsigned char)(0xC0 | encode));
2087 }
2088
2089 void Assembler::movdl(Register dst, XMMRegister src) {
2090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2091 // swap src/dst to get correct prefix
2092 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true);
2093 emit_int8(0x7E);
2094 emit_int8((unsigned char)(0xC0 | encode));
2095 }
2096
2097 void Assembler::movdl(XMMRegister dst, Address src) {
2098 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2099 if (VM_Version::supports_evex()) {
2100 tuple_type = EVEX_T1S;
2101 input_size_in_bits = EVEX_32bit;
2102 }
2103 InstructionMark im(this);
2104 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F);
2105 emit_int8(0x6E);
2106 emit_operand(dst, src);
2107 }
2108
2109 void Assembler::movdl(Address dst, XMMRegister src) {
2110 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2111 if (VM_Version::supports_evex()) {
2112 tuple_type = EVEX_T1S;
2113 input_size_in_bits = EVEX_32bit;
2114 }
2115 InstructionMark im(this);
2116 simd_prefix(dst, src, VEX_SIMD_66, true);
2117 emit_int8(0x7E);
2118 emit_operand(src, dst);
2119 }
2120
2121 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2123 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2124 }
2125
2126 void Assembler::movdqa(XMMRegister dst, Address src) {
2127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2128 if (VM_Version::supports_evex()) {
2129 tuple_type = EVEX_FVM;
2130 }
2131 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2132 }
2133
2134 void Assembler::movdqu(XMMRegister dst, Address src) {
2135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2136 if (VM_Version::supports_evex()) {
2137 tuple_type = EVEX_FVM;
2138 }
2139 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2140 }
2141
2142 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2144 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2145 }
2146
2147 void Assembler::movdqu(Address dst, XMMRegister src) {
2148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2149 if (VM_Version::supports_evex()) {
2150 tuple_type = EVEX_FVM;
2151 }
2152 InstructionMark im(this);
2153 simd_prefix(dst, src, VEX_SIMD_F3, false);
2154 emit_int8(0x7F);
2155 emit_operand(src, dst);
2156 }
2157
2158 // Move Unaligned 256bit Vector
2159 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2160 assert(UseAVX > 0, "");
2161 if (VM_Version::supports_evex()) {
2162 tuple_type = EVEX_FVM;
2163 }
2164 int vector_len = AVX_256bit;
2165 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2166 emit_int8(0x6F);
2167 emit_int8((unsigned char)(0xC0 | encode));
2168 }
2169
2170 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2171 assert(UseAVX > 0, "");
2172 if (VM_Version::supports_evex()) {
2173 tuple_type = EVEX_FVM;
2174 }
2175 InstructionMark im(this);
2176 int vector_len = AVX_256bit;
2177 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2178 emit_int8(0x6F);
2179 emit_operand(dst, src);
2180 }
2181
2182 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2183 assert(UseAVX > 0, "");
2184 if (VM_Version::supports_evex()) {
2185 tuple_type = EVEX_FVM;
2186 }
2187 InstructionMark im(this);
2188 int vector_len = AVX_256bit;
2189 // swap src<->dst for encoding
2190 assert(src != xnoreg, "sanity");
2191 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2192 emit_int8(0x7F);
2193 emit_operand(src, dst);
2194 }
2195
2196 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2197 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2198 assert(UseAVX > 0, "");
2199 int src_enc = src->encoding();
2200 int dst_enc = dst->encoding();
2201 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2202 true, vector_len, false, false);
2203 emit_int8(0x6F);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) {
2208 assert(UseAVX > 0, "");
2209 InstructionMark im(this);
2210 if (VM_Version::supports_evex()) {
2211 tuple_type = EVEX_FVM;
2212 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2213 } else {
2214 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2215 }
2216 emit_int8(0x6F);
2217 emit_operand(dst, src);
2218 }
2219
2220 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) {
2221 assert(UseAVX > 0, "");
2222 InstructionMark im(this);
2223 assert(src != xnoreg, "sanity");
2224 if (VM_Version::supports_evex()) {
2225 tuple_type = EVEX_FVM;
2226 // swap src<->dst for encoding
2227 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2228 } else {
2229 // swap src<->dst for encoding
2230 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2231 }
2232 emit_int8(0x7F);
2233 emit_operand(src, dst);
2234 }
2235
2236 // Uses zero extension on 64bit
2237
2238 void Assembler::movl(Register dst, int32_t imm32) {
2239 int encode = prefix_and_encode(dst->encoding());
2240 emit_int8((unsigned char)(0xB8 | encode));
2241 emit_int32(imm32);
2242 }
2243
2244 void Assembler::movl(Register dst, Register src) {
2245 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2246 emit_int8((unsigned char)0x8B);
2247 emit_int8((unsigned char)(0xC0 | encode));
2248 }
2249
2250 void Assembler::movl(Register dst, Address src) {
2251 InstructionMark im(this);
2252 prefix(src, dst);
2253 emit_int8((unsigned char)0x8B);
2254 emit_operand(dst, src);
2255 }
2256
2257 void Assembler::movl(Address dst, int32_t imm32) {
2258 InstructionMark im(this);
2259 prefix(dst);
2260 emit_int8((unsigned char)0xC7);
2261 emit_operand(rax, dst, 4);
2262 emit_int32(imm32);
2263 }
2264
2265 void Assembler::movl(Address dst, Register src) {
2266 InstructionMark im(this);
2267 prefix(dst, src);
2268 emit_int8((unsigned char)0x89);
2269 emit_operand(src, dst);
2270 }
2271
2272 // New cpus require to use movsd and movss to avoid partial register stall
2273 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2274 // The selection is done in MacroAssembler::movdbl() and movflt().
2275 void Assembler::movlpd(XMMRegister dst, Address src) {
2276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2277 if (VM_Version::supports_evex()) {
2278 tuple_type = EVEX_T1S;
2279 input_size_in_bits = EVEX_32bit;
2280 }
2281 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true);
2282 }
2283
2284 void Assembler::movq( MMXRegister dst, Address src ) {
2285 assert( VM_Version::supports_mmx(), "" );
2286 emit_int8(0x0F);
2287 emit_int8(0x6F);
2288 emit_operand(dst, src);
2289 }
2290
2291 void Assembler::movq( Address dst, MMXRegister src ) {
2292 assert( VM_Version::supports_mmx(), "" );
2293 emit_int8(0x0F);
2294 emit_int8(0x7F);
2295 // workaround gcc (3.2.1-7a) bug
2296 // In that version of gcc with only an emit_operand(MMX, Address)
2297 // gcc will tail jump and try and reverse the parameters completely
2298 // obliterating dst in the process. By having a version available
2299 // that doesn't need to swap the args at the tail jump the bug is
2300 // avoided.
2301 emit_operand(dst, src);
2302 }
2303
2304 void Assembler::movq(XMMRegister dst, Address src) {
2305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2306 InstructionMark im(this);
2307 if (VM_Version::supports_evex()) {
2308 tuple_type = EVEX_T1S;
2309 input_size_in_bits = EVEX_64bit;
2310 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true);
2311 } else {
2312 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F);
2313 }
2314 emit_int8(0x7E);
2315 emit_operand(dst, src);
2316 }
2317
2318 void Assembler::movq(Address dst, XMMRegister src) {
2319 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2320 InstructionMark im(this);
2321 if (VM_Version::supports_evex()) {
2322 tuple_type = EVEX_T1S;
2323 input_size_in_bits = EVEX_64bit;
2324 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true,
2325 VEX_OPCODE_0F, true, AVX_128bit);
2326 } else {
2327 simd_prefix(dst, src, VEX_SIMD_66, true);
2328 }
2329 emit_int8((unsigned char)0xD6);
2330 emit_operand(src, dst);
2331 }
2332
2333 void Assembler::movsbl(Register dst, Address src) { // movsxb
2334 InstructionMark im(this);
2335 prefix(src, dst);
2336 emit_int8(0x0F);
2337 emit_int8((unsigned char)0xBE);
2338 emit_operand(dst, src);
2339 }
2340
2341 void Assembler::movsbl(Register dst, Register src) { // movsxb
2342 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2343 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2344 emit_int8(0x0F);
2345 emit_int8((unsigned char)0xBE);
2346 emit_int8((unsigned char)(0xC0 | encode));
2347 }
2348
2349 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2350 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2351 if (VM_Version::supports_evex()) {
2352 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true);
2353 } else {
2354 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2355 }
2356 }
2357
2358 void Assembler::movsd(XMMRegister dst, Address src) {
2359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2360 if (VM_Version::supports_evex()) {
2361 tuple_type = EVEX_T1S;
2362 input_size_in_bits = EVEX_64bit;
2363 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true);
2364 } else {
2365 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2366 }
2367 }
2368
2369 void Assembler::movsd(Address dst, XMMRegister src) {
2370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2371 InstructionMark im(this);
2372 if (VM_Version::supports_evex()) {
2373 tuple_type = EVEX_T1S;
2374 input_size_in_bits = EVEX_64bit;
2375 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2376 } else {
2377 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false);
2378 }
2379 emit_int8(0x11);
2380 emit_operand(src, dst);
2381 }
2382
2383 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2384 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2385 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true);
2386 }
2387
2388 void Assembler::movss(XMMRegister dst, Address src) {
2389 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2390 if (VM_Version::supports_evex()) {
2391 tuple_type = EVEX_T1S;
2392 input_size_in_bits = EVEX_32bit;
2393 }
2394 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true);
2395 }
2396
2397 void Assembler::movss(Address dst, XMMRegister src) {
2398 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2399 if (VM_Version::supports_evex()) {
2400 tuple_type = EVEX_T1S;
2401 input_size_in_bits = EVEX_32bit;
2402 }
2403 InstructionMark im(this);
2404 simd_prefix(dst, src, VEX_SIMD_F3, false);
2405 emit_int8(0x11);
2406 emit_operand(src, dst);
2407 }
2408
2409 void Assembler::movswl(Register dst, Address src) { // movsxw
2410 InstructionMark im(this);
2411 prefix(src, dst);
2412 emit_int8(0x0F);
2413 emit_int8((unsigned char)0xBF);
2414 emit_operand(dst, src);
2415 }
2416
2417 void Assembler::movswl(Register dst, Register src) { // movsxw
2418 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2419 emit_int8(0x0F);
2420 emit_int8((unsigned char)0xBF);
2421 emit_int8((unsigned char)(0xC0 | encode));
2422 }
2423
2424 void Assembler::movw(Address dst, int imm16) {
2425 InstructionMark im(this);
2426
2427 emit_int8(0x66); // switch to 16-bit mode
2428 prefix(dst);
2429 emit_int8((unsigned char)0xC7);
2430 emit_operand(rax, dst, 2);
2431 emit_int16(imm16);
2432 }
2433
2434 void Assembler::movw(Register dst, Address src) {
2435 InstructionMark im(this);
2436 emit_int8(0x66);
2437 prefix(src, dst);
2438 emit_int8((unsigned char)0x8B);
2439 emit_operand(dst, src);
2440 }
2441
2442 void Assembler::movw(Address dst, Register src) {
2443 InstructionMark im(this);
2444 emit_int8(0x66);
2445 prefix(dst, src);
2446 emit_int8((unsigned char)0x89);
2447 emit_operand(src, dst);
2448 }
2449
2450 void Assembler::movzbl(Register dst, Address src) { // movzxb
2451 InstructionMark im(this);
2452 prefix(src, dst);
2453 emit_int8(0x0F);
2454 emit_int8((unsigned char)0xB6);
2455 emit_operand(dst, src);
2456 }
2457
2458 void Assembler::movzbl(Register dst, Register src) { // movzxb
2459 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2460 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
2461 emit_int8(0x0F);
2462 emit_int8((unsigned char)0xB6);
2463 emit_int8(0xC0 | encode);
2464 }
2465
2466 void Assembler::movzwl(Register dst, Address src) { // movzxw
2467 InstructionMark im(this);
2468 prefix(src, dst);
2469 emit_int8(0x0F);
2470 emit_int8((unsigned char)0xB7);
2471 emit_operand(dst, src);
2472 }
2473
2474 void Assembler::movzwl(Register dst, Register src) { // movzxw
2475 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2476 emit_int8(0x0F);
2477 emit_int8((unsigned char)0xB7);
2478 emit_int8(0xC0 | encode);
2479 }
2480
2481 void Assembler::mull(Address src) {
2482 InstructionMark im(this);
2483 prefix(src);
2484 emit_int8((unsigned char)0xF7);
2485 emit_operand(rsp, src);
2486 }
2487
2488 void Assembler::mull(Register src) {
2489 int encode = prefix_and_encode(src->encoding());
2490 emit_int8((unsigned char)0xF7);
2491 emit_int8((unsigned char)(0xE0 | encode));
2492 }
2493
2494 void Assembler::mulsd(XMMRegister dst, Address src) {
2495 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2496 if (VM_Version::supports_evex()) {
2497 tuple_type = EVEX_T1S;
2498 input_size_in_bits = EVEX_64bit;
2499 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2500 } else {
2501 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2502 }
2503 }
2504
2505 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2507 if (VM_Version::supports_evex()) {
2508 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2509 } else {
2510 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2511 }
2512 }
2513
2514 void Assembler::mulss(XMMRegister dst, Address src) {
2515 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2516 if (VM_Version::supports_evex()) {
2517 tuple_type = EVEX_T1S;
2518 input_size_in_bits = EVEX_32bit;
2519 }
2520 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2521 }
2522
2523 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2524 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2525 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2526 }
2527
2528 void Assembler::negl(Register dst) {
2529 int encode = prefix_and_encode(dst->encoding());
2530 emit_int8((unsigned char)0xF7);
2531 emit_int8((unsigned char)(0xD8 | encode));
2532 }
2533
2534 void Assembler::nop(int i) {
2535 #ifdef ASSERT
2536 assert(i > 0, " ");
2537 // The fancy nops aren't currently recognized by debuggers making it a
2538 // pain to disassemble code while debugging. If asserts are on clearly
2539 // speed is not an issue so simply use the single byte traditional nop
2540 // to do alignment.
2541
2542 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2543 return;
2544
2545 #endif // ASSERT
2546
2547 if (UseAddressNop && VM_Version::is_intel()) {
2548 //
2549 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2550 // 1: 0x90
2551 // 2: 0x66 0x90
2552 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2553 // 4: 0x0F 0x1F 0x40 0x00
2554 // 5: 0x0F 0x1F 0x44 0x00 0x00
2555 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2556 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2557 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2558 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2559 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2560 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2561
2562 // The rest coding is Intel specific - don't use consecutive address nops
2563
2564 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2565 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2566 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2567 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2568
2569 while(i >= 15) {
2570 // For Intel don't generate consecutive addess nops (mix with regular nops)
2571 i -= 15;
2572 emit_int8(0x66); // size prefix
2573 emit_int8(0x66); // size prefix
2574 emit_int8(0x66); // size prefix
2575 addr_nop_8();
2576 emit_int8(0x66); // size prefix
2577 emit_int8(0x66); // size prefix
2578 emit_int8(0x66); // size prefix
2579 emit_int8((unsigned char)0x90);
2580 // nop
2581 }
2582 switch (i) {
2583 case 14:
2584 emit_int8(0x66); // size prefix
2585 case 13:
2586 emit_int8(0x66); // size prefix
2587 case 12:
2588 addr_nop_8();
2589 emit_int8(0x66); // size prefix
2590 emit_int8(0x66); // size prefix
2591 emit_int8(0x66); // size prefix
2592 emit_int8((unsigned char)0x90);
2593 // nop
2594 break;
2595 case 11:
2596 emit_int8(0x66); // size prefix
2597 case 10:
2598 emit_int8(0x66); // size prefix
2599 case 9:
2600 emit_int8(0x66); // size prefix
2601 case 8:
2602 addr_nop_8();
2603 break;
2604 case 7:
2605 addr_nop_7();
2606 break;
2607 case 6:
2608 emit_int8(0x66); // size prefix
2609 case 5:
2610 addr_nop_5();
2611 break;
2612 case 4:
2613 addr_nop_4();
2614 break;
2615 case 3:
2616 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2617 emit_int8(0x66); // size prefix
2618 case 2:
2619 emit_int8(0x66); // size prefix
2620 case 1:
2621 emit_int8((unsigned char)0x90);
2622 // nop
2623 break;
2624 default:
2625 assert(i == 0, " ");
2626 }
2627 return;
2628 }
2629 if (UseAddressNop && VM_Version::is_amd()) {
2630 //
2631 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2632 // 1: 0x90
2633 // 2: 0x66 0x90
2634 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2635 // 4: 0x0F 0x1F 0x40 0x00
2636 // 5: 0x0F 0x1F 0x44 0x00 0x00
2637 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2638 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2639 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2640 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2641 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2642 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2643
2644 // The rest coding is AMD specific - use consecutive address nops
2645
2646 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2647 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2648 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2649 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2650 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2651 // Size prefixes (0x66) are added for larger sizes
2652
2653 while(i >= 22) {
2654 i -= 11;
2655 emit_int8(0x66); // size prefix
2656 emit_int8(0x66); // size prefix
2657 emit_int8(0x66); // size prefix
2658 addr_nop_8();
2659 }
2660 // Generate first nop for size between 21-12
2661 switch (i) {
2662 case 21:
2663 i -= 1;
2664 emit_int8(0x66); // size prefix
2665 case 20:
2666 case 19:
2667 i -= 1;
2668 emit_int8(0x66); // size prefix
2669 case 18:
2670 case 17:
2671 i -= 1;
2672 emit_int8(0x66); // size prefix
2673 case 16:
2674 case 15:
2675 i -= 8;
2676 addr_nop_8();
2677 break;
2678 case 14:
2679 case 13:
2680 i -= 7;
2681 addr_nop_7();
2682 break;
2683 case 12:
2684 i -= 6;
2685 emit_int8(0x66); // size prefix
2686 addr_nop_5();
2687 break;
2688 default:
2689 assert(i < 12, " ");
2690 }
2691
2692 // Generate second nop for size between 11-1
2693 switch (i) {
2694 case 11:
2695 emit_int8(0x66); // size prefix
2696 case 10:
2697 emit_int8(0x66); // size prefix
2698 case 9:
2699 emit_int8(0x66); // size prefix
2700 case 8:
2701 addr_nop_8();
2702 break;
2703 case 7:
2704 addr_nop_7();
2705 break;
2706 case 6:
2707 emit_int8(0x66); // size prefix
2708 case 5:
2709 addr_nop_5();
2710 break;
2711 case 4:
2712 addr_nop_4();
2713 break;
2714 case 3:
2715 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2716 emit_int8(0x66); // size prefix
2717 case 2:
2718 emit_int8(0x66); // size prefix
2719 case 1:
2720 emit_int8((unsigned char)0x90);
2721 // nop
2722 break;
2723 default:
2724 assert(i == 0, " ");
2725 }
2726 return;
2727 }
2728
2729 // Using nops with size prefixes "0x66 0x90".
2730 // From AMD Optimization Guide:
2731 // 1: 0x90
2732 // 2: 0x66 0x90
2733 // 3: 0x66 0x66 0x90
2734 // 4: 0x66 0x66 0x66 0x90
2735 // 5: 0x66 0x66 0x90 0x66 0x90
2736 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2737 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2738 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2739 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2740 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2741 //
2742 while(i > 12) {
2743 i -= 4;
2744 emit_int8(0x66); // size prefix
2745 emit_int8(0x66);
2746 emit_int8(0x66);
2747 emit_int8((unsigned char)0x90);
2748 // nop
2749 }
2750 // 1 - 12 nops
2751 if(i > 8) {
2752 if(i > 9) {
2753 i -= 1;
2754 emit_int8(0x66);
2755 }
2756 i -= 3;
2757 emit_int8(0x66);
2758 emit_int8(0x66);
2759 emit_int8((unsigned char)0x90);
2760 }
2761 // 1 - 8 nops
2762 if(i > 4) {
2763 if(i > 6) {
2764 i -= 1;
2765 emit_int8(0x66);
2766 }
2767 i -= 3;
2768 emit_int8(0x66);
2769 emit_int8(0x66);
2770 emit_int8((unsigned char)0x90);
2771 }
2772 switch (i) {
2773 case 4:
2774 emit_int8(0x66);
2775 case 3:
2776 emit_int8(0x66);
2777 case 2:
2778 emit_int8(0x66);
2779 case 1:
2780 emit_int8((unsigned char)0x90);
2781 break;
2782 default:
2783 assert(i == 0, " ");
2784 }
2785 }
2786
2787 void Assembler::notl(Register dst) {
2788 int encode = prefix_and_encode(dst->encoding());
2789 emit_int8((unsigned char)0xF7);
2790 emit_int8((unsigned char)(0xD0 | encode));
2791 }
2792
2793 void Assembler::orl(Address dst, int32_t imm32) {
2794 InstructionMark im(this);
2795 prefix(dst);
2796 emit_arith_operand(0x81, rcx, dst, imm32);
2797 }
2798
2799 void Assembler::orl(Register dst, int32_t imm32) {
2800 prefix(dst);
2801 emit_arith(0x81, 0xC8, dst, imm32);
2802 }
2803
2804 void Assembler::orl(Register dst, Address src) {
2805 InstructionMark im(this);
2806 prefix(src, dst);
2807 emit_int8(0x0B);
2808 emit_operand(dst, src);
2809 }
2810
2811 void Assembler::orl(Register dst, Register src) {
2812 (void) prefix_and_encode(dst->encoding(), src->encoding());
2813 emit_arith(0x0B, 0xC0, dst, src);
2814 }
2815
2816 void Assembler::orl(Address dst, Register src) {
2817 InstructionMark im(this);
2818 prefix(dst, src);
2819 emit_int8(0x09);
2820 emit_operand(src, dst);
2821 }
2822
2823 void Assembler::packuswb(XMMRegister dst, Address src) {
2824 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2825 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2826 if (VM_Version::supports_evex()) {
2827 tuple_type = EVEX_FV;
2828 input_size_in_bits = EVEX_32bit;
2829 }
2830 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2831 false, (VM_Version::supports_avx512dq() == false));
2832 }
2833
2834 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2836 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2837 false, (VM_Version::supports_avx512dq() == false));
2838 }
2839
2840 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2841 assert(UseAVX > 0, "some form of AVX must be enabled");
2842 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len,
2843 false, (VM_Version::supports_avx512dq() == false));
2844 }
2845
2846 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
2847 assert(VM_Version::supports_avx2(), "");
2848 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2849 VEX_OPCODE_0F_3A, true, vector_len);
2850 emit_int8(0x00);
2851 emit_int8(0xC0 | encode);
2852 emit_int8(imm8);
2853 }
2854
2855 void Assembler::pause() {
2856 emit_int8((unsigned char)0xF3);
2857 emit_int8((unsigned char)0x90);
2858 }
2859
2860 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2861 assert(VM_Version::supports_sse4_2(), "");
2862 InstructionMark im(this);
2863 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A,
2864 false, AVX_128bit, true);
2865 emit_int8(0x61);
2866 emit_operand(dst, src);
2867 emit_int8(imm8);
2868 }
2869
2870 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2871 assert(VM_Version::supports_sse4_2(), "");
2872 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2873 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
2874 emit_int8(0x61);
2875 emit_int8((unsigned char)(0xC0 | encode));
2876 emit_int8(imm8);
2877 }
2878
2879 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2880 assert(VM_Version::supports_sse4_1(), "");
2881 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2882 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2883 emit_int8(0x16);
2884 emit_int8((unsigned char)(0xC0 | encode));
2885 emit_int8(imm8);
2886 }
2887
2888 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2889 assert(VM_Version::supports_sse4_1(), "");
2890 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2891 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2892 emit_int8(0x16);
2893 emit_int8((unsigned char)(0xC0 | encode));
2894 emit_int8(imm8);
2895 }
2896
2897 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2898 assert(VM_Version::supports_sse4_1(), "");
2899 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2900 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2901 emit_int8(0x22);
2902 emit_int8((unsigned char)(0xC0 | encode));
2903 emit_int8(imm8);
2904 }
2905
2906 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2907 assert(VM_Version::supports_sse4_1(), "");
2908 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2909 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2910 emit_int8(0x22);
2911 emit_int8((unsigned char)(0xC0 | encode));
2912 emit_int8(imm8);
2913 }
2914
2915 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2916 assert(VM_Version::supports_sse4_1(), "");
2917 if (VM_Version::supports_evex()) {
2918 tuple_type = EVEX_HVM;
2919 }
2920 InstructionMark im(this);
2921 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2922 emit_int8(0x30);
2923 emit_operand(dst, src);
2924 }
2925
2926 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2927 assert(VM_Version::supports_sse4_1(), "");
2928 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2929 emit_int8(0x30);
2930 emit_int8((unsigned char)(0xC0 | encode));
2931 }
2932
2933 // generic
2934 void Assembler::pop(Register dst) {
2935 int encode = prefix_and_encode(dst->encoding());
2936 emit_int8(0x58 | encode);
2937 }
2938
2939 void Assembler::popcntl(Register dst, Address src) {
2940 assert(VM_Version::supports_popcnt(), "must support");
2941 InstructionMark im(this);
2942 emit_int8((unsigned char)0xF3);
2943 prefix(src, dst);
2944 emit_int8(0x0F);
2945 emit_int8((unsigned char)0xB8);
2946 emit_operand(dst, src);
2947 }
2948
2949 void Assembler::popcntl(Register dst, Register src) {
2950 assert(VM_Version::supports_popcnt(), "must support");
2951 emit_int8((unsigned char)0xF3);
2952 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2953 emit_int8(0x0F);
2954 emit_int8((unsigned char)0xB8);
2955 emit_int8((unsigned char)(0xC0 | encode));
2956 }
2957
2958 void Assembler::popf() {
2959 emit_int8((unsigned char)0x9D);
2960 }
2961
2962 #ifndef _LP64 // no 32bit push/pop on amd64
2963 void Assembler::popl(Address dst) {
2964 // NOTE: this will adjust stack by 8byte on 64bits
2965 InstructionMark im(this);
2966 prefix(dst);
2967 emit_int8((unsigned char)0x8F);
2968 emit_operand(rax, dst);
2969 }
2970 #endif
2971
2972 void Assembler::prefetch_prefix(Address src) {
2973 prefix(src);
2974 emit_int8(0x0F);
2975 }
2976
2977 void Assembler::prefetchnta(Address src) {
2978 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2979 InstructionMark im(this);
2980 prefetch_prefix(src);
2981 emit_int8(0x18);
2982 emit_operand(rax, src); // 0, src
2983 }
2984
2985 void Assembler::prefetchr(Address src) {
2986 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2987 InstructionMark im(this);
2988 prefetch_prefix(src);
2989 emit_int8(0x0D);
2990 emit_operand(rax, src); // 0, src
2991 }
2992
2993 void Assembler::prefetcht0(Address src) {
2994 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2995 InstructionMark im(this);
2996 prefetch_prefix(src);
2997 emit_int8(0x18);
2998 emit_operand(rcx, src); // 1, src
2999 }
3000
3001 void Assembler::prefetcht1(Address src) {
3002 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3003 InstructionMark im(this);
3004 prefetch_prefix(src);
3005 emit_int8(0x18);
3006 emit_operand(rdx, src); // 2, src
3007 }
3008
3009 void Assembler::prefetcht2(Address src) {
3010 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3011 InstructionMark im(this);
3012 prefetch_prefix(src);
3013 emit_int8(0x18);
3014 emit_operand(rbx, src); // 3, src
3015 }
3016
3017 void Assembler::prefetchw(Address src) {
3018 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3019 InstructionMark im(this);
3020 prefetch_prefix(src);
3021 emit_int8(0x0D);
3022 emit_operand(rcx, src); // 1, src
3023 }
3024
3025 void Assembler::prefix(Prefix p) {
3026 emit_int8(p);
3027 }
3028
3029 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3030 assert(VM_Version::supports_ssse3(), "");
3031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3032 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3033 emit_int8(0x00);
3034 emit_int8((unsigned char)(0xC0 | encode));
3035 }
3036
3037 void Assembler::pshufb(XMMRegister dst, Address src) {
3038 assert(VM_Version::supports_ssse3(), "");
3039 if (VM_Version::supports_evex()) {
3040 tuple_type = EVEX_FVM;
3041 }
3042 InstructionMark im(this);
3043 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3044 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3045 emit_int8(0x00);
3046 emit_operand(dst, src);
3047 }
3048
3049 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3050 assert(isByte(mode), "invalid value");
3051 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3052 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3053 emit_int8(mode & 0xFF);
3054
3055 }
3056
3057 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3058 assert(isByte(mode), "invalid value");
3059 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3060 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3061 if (VM_Version::supports_evex()) {
3062 tuple_type = EVEX_FV;
3063 input_size_in_bits = EVEX_32bit;
3064 }
3065 InstructionMark im(this);
3066 simd_prefix(dst, src, VEX_SIMD_66, false);
3067 emit_int8(0x70);
3068 emit_operand(dst, src);
3069 emit_int8(mode & 0xFF);
3070 }
3071
3072 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3073 assert(isByte(mode), "invalid value");
3074 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3075 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false,
3076 (VM_Version::supports_avx512bw() == false));
3077 emit_int8(mode & 0xFF);
3078 }
3079
3080 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3081 assert(isByte(mode), "invalid value");
3082 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3083 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3084 if (VM_Version::supports_evex()) {
3085 tuple_type = EVEX_FVM;
3086 }
3087 InstructionMark im(this);
3088 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3089 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3090 emit_int8(0x70);
3091 emit_operand(dst, src);
3092 emit_int8(mode & 0xFF);
3093 }
3094
3095 void Assembler::psrldq(XMMRegister dst, int shift) {
3096 // Shift 128 bit value in xmm register by number of bytes.
3097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3098 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3099 emit_int8(0x73);
3100 emit_int8((unsigned char)(0xC0 | encode));
3101 emit_int8(shift);
3102 }
3103
3104 void Assembler::pslldq(XMMRegister dst, int shift) {
3105 // Shift left 128 bit value in xmm register by number of bytes.
3106 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3107 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3108 emit_int8(0x73);
3109 emit_int8((unsigned char)(0xC0 | encode));
3110 emit_int8(shift);
3111 }
3112
3113 void Assembler::ptest(XMMRegister dst, Address src) {
3114 assert(VM_Version::supports_sse4_1(), "");
3115 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3116 InstructionMark im(this);
3117 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false,
3118 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3119 emit_int8(0x17);
3120 emit_operand(dst, src);
3121 }
3122
3123 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3124 assert(VM_Version::supports_sse4_1(), "");
3125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
3126 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3127 emit_int8(0x17);
3128 emit_int8((unsigned char)(0xC0 | encode));
3129 }
3130
3131 void Assembler::vptest(XMMRegister dst, Address src) {
3132 assert(VM_Version::supports_avx(), "");
3133 InstructionMark im(this);
3134 int vector_len = AVX_256bit;
3135 assert(dst != xnoreg, "sanity");
3136 int dst_enc = dst->encoding();
3137 // swap src<->dst for encoding
3138 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len, true, false);
3139 emit_int8(0x17);
3140 emit_operand(dst, src);
3141 }
3142
3143 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3144 assert(VM_Version::supports_avx(), "");
3145 int vector_len = AVX_256bit;
3146 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3147 vector_len, VEX_OPCODE_0F_38, true, false);
3148 emit_int8(0x17);
3149 emit_int8((unsigned char)(0xC0 | encode));
3150 }
3151
3152 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3154 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3155 if (VM_Version::supports_evex()) {
3156 tuple_type = EVEX_FVM;
3157 }
3158 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, false, (VM_Version::supports_avx512vlbw() == false));
3159 }
3160
3161 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3162 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3163 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, false, (VM_Version::supports_avx512vlbw() == false));
3164 }
3165
3166 void Assembler::punpckldq(XMMRegister dst, Address src) {
3167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3168 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3169 if (VM_Version::supports_evex()) {
3170 tuple_type = EVEX_FV;
3171 input_size_in_bits = EVEX_32bit;
3172 }
3173 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3174 }
3175
3176 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3178 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3179 }
3180
3181 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3182 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3183 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3184 }
3185
3186 void Assembler::push(int32_t imm32) {
3187 // in 64bits we push 64bits onto the stack but only
3188 // take a 32bit immediate
3189 emit_int8(0x68);
3190 emit_int32(imm32);
3191 }
3192
3193 void Assembler::push(Register src) {
3194 int encode = prefix_and_encode(src->encoding());
3195
3196 emit_int8(0x50 | encode);
3197 }
3198
3199 void Assembler::pushf() {
3200 emit_int8((unsigned char)0x9C);
3201 }
3202
3203 #ifndef _LP64 // no 32bit push/pop on amd64
3204 void Assembler::pushl(Address src) {
3205 // Note this will push 64bit on 64bit
3206 InstructionMark im(this);
3207 prefix(src);
3208 emit_int8((unsigned char)0xFF);
3209 emit_operand(rsi, src);
3210 }
3211 #endif
3212
3213 void Assembler::rcll(Register dst, int imm8) {
3214 assert(isShiftCount(imm8), "illegal shift count");
3215 int encode = prefix_and_encode(dst->encoding());
3216 if (imm8 == 1) {
3217 emit_int8((unsigned char)0xD1);
3218 emit_int8((unsigned char)(0xD0 | encode));
3219 } else {
3220 emit_int8((unsigned char)0xC1);
3221 emit_int8((unsigned char)0xD0 | encode);
3222 emit_int8(imm8);
3223 }
3224 }
3225
3226 void Assembler::rdtsc() {
3227 emit_int8((unsigned char)0x0F);
3228 emit_int8((unsigned char)0x31);
3229 }
3230
3231 // copies data from [esi] to [edi] using rcx pointer sized words
3232 // generic
3233 void Assembler::rep_mov() {
3234 emit_int8((unsigned char)0xF3);
3235 // MOVSQ
3236 LP64_ONLY(prefix(REX_W));
3237 emit_int8((unsigned char)0xA5);
3238 }
3239
3240 // sets rcx bytes with rax, value at [edi]
3241 void Assembler::rep_stosb() {
3242 emit_int8((unsigned char)0xF3); // REP
3243 LP64_ONLY(prefix(REX_W));
3244 emit_int8((unsigned char)0xAA); // STOSB
3245 }
3246
3247 // sets rcx pointer sized words with rax, value at [edi]
3248 // generic
3249 void Assembler::rep_stos() {
3250 emit_int8((unsigned char)0xF3); // REP
3251 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3252 emit_int8((unsigned char)0xAB);
3253 }
3254
3255 // scans rcx pointer sized words at [edi] for occurance of rax,
3256 // generic
3257 void Assembler::repne_scan() { // repne_scan
3258 emit_int8((unsigned char)0xF2);
3259 // SCASQ
3260 LP64_ONLY(prefix(REX_W));
3261 emit_int8((unsigned char)0xAF);
3262 }
3263
3264 #ifdef _LP64
3265 // scans rcx 4 byte words at [edi] for occurance of rax,
3266 // generic
3267 void Assembler::repne_scanl() { // repne_scan
3268 emit_int8((unsigned char)0xF2);
3269 // SCASL
3270 emit_int8((unsigned char)0xAF);
3271 }
3272 #endif
3273
3274 void Assembler::ret(int imm16) {
3275 if (imm16 == 0) {
3276 emit_int8((unsigned char)0xC3);
3277 } else {
3278 emit_int8((unsigned char)0xC2);
3279 emit_int16(imm16);
3280 }
3281 }
3282
3283 void Assembler::sahf() {
3284 #ifdef _LP64
3285 // Not supported in 64bit mode
3286 ShouldNotReachHere();
3287 #endif
3288 emit_int8((unsigned char)0x9E);
3289 }
3290
3291 void Assembler::sarl(Register dst, int imm8) {
3292 int encode = prefix_and_encode(dst->encoding());
3293 assert(isShiftCount(imm8), "illegal shift count");
3294 if (imm8 == 1) {
3295 emit_int8((unsigned char)0xD1);
3296 emit_int8((unsigned char)(0xF8 | encode));
3297 } else {
3298 emit_int8((unsigned char)0xC1);
3299 emit_int8((unsigned char)(0xF8 | encode));
3300 emit_int8(imm8);
3301 }
3302 }
3303
3304 void Assembler::sarl(Register dst) {
3305 int encode = prefix_and_encode(dst->encoding());
3306 emit_int8((unsigned char)0xD3);
3307 emit_int8((unsigned char)(0xF8 | encode));
3308 }
3309
3310 void Assembler::sbbl(Address dst, int32_t imm32) {
3311 InstructionMark im(this);
3312 prefix(dst);
3313 emit_arith_operand(0x81, rbx, dst, imm32);
3314 }
3315
3316 void Assembler::sbbl(Register dst, int32_t imm32) {
3317 prefix(dst);
3318 emit_arith(0x81, 0xD8, dst, imm32);
3319 }
3320
3321
3322 void Assembler::sbbl(Register dst, Address src) {
3323 InstructionMark im(this);
3324 prefix(src, dst);
3325 emit_int8(0x1B);
3326 emit_operand(dst, src);
3327 }
3328
3329 void Assembler::sbbl(Register dst, Register src) {
3330 (void) prefix_and_encode(dst->encoding(), src->encoding());
3331 emit_arith(0x1B, 0xC0, dst, src);
3332 }
3333
3334 void Assembler::setb(Condition cc, Register dst) {
3335 assert(0 <= cc && cc < 16, "illegal cc");
3336 int encode = prefix_and_encode(dst->encoding(), true);
3337 emit_int8(0x0F);
3338 emit_int8((unsigned char)0x90 | cc);
3339 emit_int8((unsigned char)(0xC0 | encode));
3340 }
3341
3342 void Assembler::shll(Register dst, int imm8) {
3343 assert(isShiftCount(imm8), "illegal shift count");
3344 int encode = prefix_and_encode(dst->encoding());
3345 if (imm8 == 1 ) {
3346 emit_int8((unsigned char)0xD1);
3347 emit_int8((unsigned char)(0xE0 | encode));
3348 } else {
3349 emit_int8((unsigned char)0xC1);
3350 emit_int8((unsigned char)(0xE0 | encode));
3351 emit_int8(imm8);
3352 }
3353 }
3354
3355 void Assembler::shll(Register dst) {
3356 int encode = prefix_and_encode(dst->encoding());
3357 emit_int8((unsigned char)0xD3);
3358 emit_int8((unsigned char)(0xE0 | encode));
3359 }
3360
3361 void Assembler::shrl(Register dst, int imm8) {
3362 assert(isShiftCount(imm8), "illegal shift count");
3363 int encode = prefix_and_encode(dst->encoding());
3364 emit_int8((unsigned char)0xC1);
3365 emit_int8((unsigned char)(0xE8 | encode));
3366 emit_int8(imm8);
3367 }
3368
3369 void Assembler::shrl(Register dst) {
3370 int encode = prefix_and_encode(dst->encoding());
3371 emit_int8((unsigned char)0xD3);
3372 emit_int8((unsigned char)(0xE8 | encode));
3373 }
3374
3375 // copies a single word from [esi] to [edi]
3376 void Assembler::smovl() {
3377 emit_int8((unsigned char)0xA5);
3378 }
3379
3380 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3382 if (VM_Version::supports_evex()) {
3383 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3384 } else {
3385 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3386 }
3387 }
3388
3389 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3391 if (VM_Version::supports_evex()) {
3392 tuple_type = EVEX_T1S;
3393 input_size_in_bits = EVEX_64bit;
3394 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3395 } else {
3396 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3397 }
3398 }
3399
3400 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3401 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3402 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3403 }
3404
3405 void Assembler::std() {
3406 emit_int8((unsigned char)0xFD);
3407 }
3408
3409 void Assembler::sqrtss(XMMRegister dst, Address src) {
3410 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3411 if (VM_Version::supports_evex()) {
3412 tuple_type = EVEX_T1S;
3413 input_size_in_bits = EVEX_32bit;
3414 }
3415 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3416 }
3417
3418 void Assembler::stmxcsr( Address dst) {
3419 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3420 InstructionMark im(this);
3421 prefix(dst);
3422 emit_int8(0x0F);
3423 emit_int8((unsigned char)0xAE);
3424 emit_operand(as_Register(3), dst);
3425 }
3426
3427 void Assembler::subl(Address dst, int32_t imm32) {
3428 InstructionMark im(this);
3429 prefix(dst);
3430 emit_arith_operand(0x81, rbp, dst, imm32);
3431 }
3432
3433 void Assembler::subl(Address dst, Register src) {
3434 InstructionMark im(this);
3435 prefix(dst, src);
3436 emit_int8(0x29);
3437 emit_operand(src, dst);
3438 }
3439
3440 void Assembler::subl(Register dst, int32_t imm32) {
3441 prefix(dst);
3442 emit_arith(0x81, 0xE8, dst, imm32);
3443 }
3444
3445 // Force generation of a 4 byte immediate value even if it fits into 8bit
3446 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3447 prefix(dst);
3448 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3449 }
3450
3451 void Assembler::subl(Register dst, Address src) {
3452 InstructionMark im(this);
3453 prefix(src, dst);
3454 emit_int8(0x2B);
3455 emit_operand(dst, src);
3456 }
3457
3458 void Assembler::subl(Register dst, Register src) {
3459 (void) prefix_and_encode(dst->encoding(), src->encoding());
3460 emit_arith(0x2B, 0xC0, dst, src);
3461 }
3462
3463 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3464 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3465 if (VM_Version::supports_evex()) {
3466 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3467 } else {
3468 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3469 }
3470 }
3471
3472 void Assembler::subsd(XMMRegister dst, Address src) {
3473 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3474 if (VM_Version::supports_evex()) {
3475 tuple_type = EVEX_T1S;
3476 input_size_in_bits = EVEX_64bit;
3477 }
3478 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3479 }
3480
3481 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3482 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3483 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3484 }
3485
3486 void Assembler::subss(XMMRegister dst, Address src) {
3487 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3488 if (VM_Version::supports_evex()) {
3489 tuple_type = EVEX_T1S;
3490 input_size_in_bits = EVEX_32bit;
3491 }
3492 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3493 }
3494
3495 void Assembler::testb(Register dst, int imm8) {
3496 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3497 (void) prefix_and_encode(dst->encoding(), true);
3498 emit_arith_b(0xF6, 0xC0, dst, imm8);
3499 }
3500
3501 void Assembler::testl(Register dst, int32_t imm32) {
3502 // not using emit_arith because test
3503 // doesn't support sign-extension of
3504 // 8bit operands
3505 int encode = dst->encoding();
3506 if (encode == 0) {
3507 emit_int8((unsigned char)0xA9);
3508 } else {
3509 encode = prefix_and_encode(encode);
3510 emit_int8((unsigned char)0xF7);
3511 emit_int8((unsigned char)(0xC0 | encode));
3512 }
3513 emit_int32(imm32);
3514 }
3515
3516 void Assembler::testl(Register dst, Register src) {
3517 (void) prefix_and_encode(dst->encoding(), src->encoding());
3518 emit_arith(0x85, 0xC0, dst, src);
3519 }
3520
3521 void Assembler::testl(Register dst, Address src) {
3522 InstructionMark im(this);
3523 prefix(src, dst);
3524 emit_int8((unsigned char)0x85);
3525 emit_operand(dst, src);
3526 }
3527
3528 void Assembler::tzcntl(Register dst, Register src) {
3529 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3530 emit_int8((unsigned char)0xF3);
3531 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3532 emit_int8(0x0F);
3533 emit_int8((unsigned char)0xBC);
3534 emit_int8((unsigned char)0xC0 | encode);
3535 }
3536
3537 void Assembler::tzcntq(Register dst, Register src) {
3538 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3539 emit_int8((unsigned char)0xF3);
3540 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3541 emit_int8(0x0F);
3542 emit_int8((unsigned char)0xBC);
3543 emit_int8((unsigned char)(0xC0 | encode));
3544 }
3545
3546 void Assembler::ucomisd(XMMRegister dst, Address src) {
3547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3548 if (VM_Version::supports_evex()) {
3549 tuple_type = EVEX_T1S;
3550 input_size_in_bits = EVEX_64bit;
3551 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3552 } else {
3553 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3554 }
3555 }
3556
3557 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3558 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3559 if (VM_Version::supports_evex()) {
3560 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3561 } else {
3562 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3563 }
3564 }
3565
3566 void Assembler::ucomiss(XMMRegister dst, Address src) {
3567 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3568 if (VM_Version::supports_evex()) {
3569 tuple_type = EVEX_T1S;
3570 input_size_in_bits = EVEX_32bit;
3571 }
3572 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3573 }
3574
3575 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3576 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3577 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3578 }
3579
3580 void Assembler::xabort(int8_t imm8) {
3581 emit_int8((unsigned char)0xC6);
3582 emit_int8((unsigned char)0xF8);
3583 emit_int8((unsigned char)(imm8 & 0xFF));
3584 }
3585
3586 void Assembler::xaddl(Address dst, Register src) {
3587 InstructionMark im(this);
3588 prefix(dst, src);
3589 emit_int8(0x0F);
3590 emit_int8((unsigned char)0xC1);
3591 emit_operand(src, dst);
3592 }
3593
3594 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3595 InstructionMark im(this);
3596 relocate(rtype);
3597 if (abort.is_bound()) {
3598 address entry = target(abort);
3599 assert(entry != NULL, "abort entry NULL");
3600 intptr_t offset = entry - pc();
3601 emit_int8((unsigned char)0xC7);
3602 emit_int8((unsigned char)0xF8);
3603 emit_int32(offset - 6); // 2 opcode + 4 address
3604 } else {
3605 abort.add_patch_at(code(), locator());
3606 emit_int8((unsigned char)0xC7);
3607 emit_int8((unsigned char)0xF8);
3608 emit_int32(0);
3609 }
3610 }
3611
3612 void Assembler::xchgl(Register dst, Address src) { // xchg
3613 InstructionMark im(this);
3614 prefix(src, dst);
3615 emit_int8((unsigned char)0x87);
3616 emit_operand(dst, src);
3617 }
3618
3619 void Assembler::xchgl(Register dst, Register src) {
3620 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3621 emit_int8((unsigned char)0x87);
3622 emit_int8((unsigned char)(0xC0 | encode));
3623 }
3624
3625 void Assembler::xend() {
3626 emit_int8((unsigned char)0x0F);
3627 emit_int8((unsigned char)0x01);
3628 emit_int8((unsigned char)0xD5);
3629 }
3630
3631 void Assembler::xgetbv() {
3632 emit_int8(0x0F);
3633 emit_int8(0x01);
3634 emit_int8((unsigned char)0xD0);
3635 }
3636
3637 void Assembler::xorl(Register dst, int32_t imm32) {
3638 prefix(dst);
3639 emit_arith(0x81, 0xF0, dst, imm32);
3640 }
3641
3642 void Assembler::xorl(Register dst, Address src) {
3643 InstructionMark im(this);
3644 prefix(src, dst);
3645 emit_int8(0x33);
3646 emit_operand(dst, src);
3647 }
3648
3649 void Assembler::xorl(Register dst, Register src) {
3650 (void) prefix_and_encode(dst->encoding(), src->encoding());
3651 emit_arith(0x33, 0xC0, dst, src);
3652 }
3653
3654
3655 // AVX 3-operands scalar float-point arithmetic instructions
3656
3657 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3658 assert(VM_Version::supports_avx(), "");
3659 if (VM_Version::supports_evex()) {
3660 tuple_type = EVEX_T1S;
3661 input_size_in_bits = EVEX_64bit;
3662 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3663 } else {
3664 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3665 }
3666 }
3667
3668 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3669 assert(VM_Version::supports_avx(), "");
3670 if (VM_Version::supports_evex()) {
3671 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3672 } else {
3673 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3674 }
3675 }
3676
3677 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3678 assert(VM_Version::supports_avx(), "");
3679 if (VM_Version::supports_evex()) {
3680 tuple_type = EVEX_T1S;
3681 input_size_in_bits = EVEX_32bit;
3682 }
3683 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3684 }
3685
3686 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3687 assert(VM_Version::supports_avx(), "");
3688 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3689 }
3690
3691 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3692 assert(VM_Version::supports_avx(), "");
3693 if (VM_Version::supports_evex()) {
3694 tuple_type = EVEX_T1S;
3695 input_size_in_bits = EVEX_64bit;
3696 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3697 } else {
3698 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3699 }
3700 }
3701
3702 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3703 assert(VM_Version::supports_avx(), "");
3704 if (VM_Version::supports_evex()) {
3705 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3706 } else {
3707 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3708 }
3709 }
3710
3711 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3712 assert(VM_Version::supports_avx(), "");
3713 if (VM_Version::supports_evex()) {
3714 tuple_type = EVEX_T1S;
3715 input_size_in_bits = EVEX_32bit;
3716 }
3717 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3718 }
3719
3720 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3721 assert(VM_Version::supports_avx(), "");
3722 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3723 }
3724
3725 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3726 assert(VM_Version::supports_avx(), "");
3727 if (VM_Version::supports_evex()) {
3728 tuple_type = EVEX_T1S;
3729 input_size_in_bits = EVEX_64bit;
3730 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3731 } else {
3732 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3733 }
3734 }
3735
3736 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3737 assert(VM_Version::supports_avx(), "");
3738 if (VM_Version::supports_evex()) {
3739 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3740 } else {
3741 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3742 }
3743 }
3744
3745 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3746 assert(VM_Version::supports_avx(), "");
3747 if (VM_Version::supports_evex()) {
3748 tuple_type = EVEX_T1S;
3749 input_size_in_bits = EVEX_32bit;
3750 }
3751 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3752 }
3753
3754 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3755 assert(VM_Version::supports_avx(), "");
3756 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3757 }
3758
3759 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3760 assert(VM_Version::supports_avx(), "");
3761 if (VM_Version::supports_evex()) {
3762 tuple_type = EVEX_T1S;
3763 input_size_in_bits = EVEX_64bit;
3764 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3765 } else {
3766 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3767 }
3768 }
3769
3770 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3771 assert(VM_Version::supports_avx(), "");
3772 if (VM_Version::supports_evex()) {
3773 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3774 } else {
3775 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3776 }
3777 }
3778
3779 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3780 assert(VM_Version::supports_avx(), "");
3781 if (VM_Version::supports_evex()) {
3782 tuple_type = EVEX_T1S;
3783 input_size_in_bits = EVEX_32bit;
3784 }
3785 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3786 }
3787
3788 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3789 assert(VM_Version::supports_avx(), "");
3790 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3791 }
3792
3793 //====================VECTOR ARITHMETIC=====================================
3794
3795 // Float-point vector arithmetic
3796
3797 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3798 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3799 if (VM_Version::supports_evex()) {
3800 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
3801 } else {
3802 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3803 }
3804 }
3805
3806 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3807 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3808 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3809 }
3810
3811 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3812 assert(VM_Version::supports_avx(), "");
3813 if (VM_Version::supports_evex()) {
3814 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3815 } else {
3816 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3817 }
3818 }
3819
3820 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3821 assert(VM_Version::supports_avx(), "");
3822 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3823 }
3824
3825 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3826 assert(VM_Version::supports_avx(), "");
3827 if (VM_Version::supports_evex()) {
3828 tuple_type = EVEX_FV;
3829 input_size_in_bits = EVEX_64bit;
3830 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3831 } else {
3832 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3833 }
3834 }
3835
3836 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3837 assert(VM_Version::supports_avx(), "");
3838 if (VM_Version::supports_evex()) {
3839 tuple_type = EVEX_FV;
3840 input_size_in_bits = EVEX_32bit;
3841 }
3842 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3843 }
3844
3845 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3847 if (VM_Version::supports_evex()) {
3848 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
3849 } else {
3850 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3851 }
3852 }
3853
3854 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3855 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3856 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3857 }
3858
3859 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3860 assert(VM_Version::supports_avx(), "");
3861 if (VM_Version::supports_evex()) {
3862 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3863 } else {
3864 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3865 }
3866 }
3867
3868 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3869 assert(VM_Version::supports_avx(), "");
3870 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3871 }
3872
3873 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3874 assert(VM_Version::supports_avx(), "");
3875 if (VM_Version::supports_evex()) {
3876 tuple_type = EVEX_FV;
3877 input_size_in_bits = EVEX_64bit;
3878 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3879 } else {
3880 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3881 }
3882 }
3883
3884 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3885 assert(VM_Version::supports_avx(), "");
3886 if (VM_Version::supports_evex()) {
3887 tuple_type = EVEX_FV;
3888 input_size_in_bits = EVEX_32bit;
3889 }
3890 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3891 }
3892
3893 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3894 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3895 if (VM_Version::supports_evex()) {
3896 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
3897 } else {
3898 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3899 }
3900 }
3901
3902 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3904 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3905 }
3906
3907 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3908 assert(VM_Version::supports_avx(), "");
3909 if (VM_Version::supports_evex()) {
3910 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3911 } else {
3912 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3913 }
3914 }
3915
3916 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3917 assert(VM_Version::supports_avx(), "");
3918 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3919 }
3920
3921 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3922 assert(VM_Version::supports_avx(), "");
3923 if (VM_Version::supports_evex()) {
3924 tuple_type = EVEX_FV;
3925 input_size_in_bits = EVEX_64bit;
3926 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3927 } else {
3928 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3929 }
3930 }
3931
3932 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3933 assert(VM_Version::supports_avx(), "");
3934 if (VM_Version::supports_evex()) {
3935 tuple_type = EVEX_FV;
3936 input_size_in_bits = EVEX_32bit;
3937 }
3938 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3939 }
3940
3941 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3942 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3943 if (VM_Version::supports_evex()) {
3944 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
3945 } else {
3946 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3947 }
3948 }
3949
3950 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3951 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3952 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3953 }
3954
3955 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3956 assert(VM_Version::supports_avx(), "");
3957 if (VM_Version::supports_evex()) {
3958 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3959 } else {
3960 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3961 }
3962 }
3963
3964 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3965 assert(VM_Version::supports_avx(), "");
3966 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3967 }
3968
3969 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3970 assert(VM_Version::supports_avx(), "");
3971 if (VM_Version::supports_evex()) {
3972 tuple_type = EVEX_FV;
3973 input_size_in_bits = EVEX_64bit;
3974 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3975 } else {
3976 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3977 }
3978 }
3979
3980 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3981 assert(VM_Version::supports_avx(), "");
3982 if (VM_Version::supports_evex()) {
3983 tuple_type = EVEX_FV;
3984 input_size_in_bits = EVEX_32bit;
3985 }
3986 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3987 }
3988
3989 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3991 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
3992 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
3993 } else {
3994 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
3995 }
3996 }
3997
3998 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3999 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4000 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false,
4001 (VM_Version::supports_avx512dq() == false));
4002 }
4003
4004 void Assembler::andps(XMMRegister dst, Address src) {
4005 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4006 if (VM_Version::supports_evex()) {
4007 tuple_type = EVEX_FV;
4008 input_size_in_bits = EVEX_32bit;
4009 }
4010 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE,
4011 false, (VM_Version::supports_avx512dq() == false));
4012 }
4013
4014 void Assembler::andpd(XMMRegister dst, Address src) {
4015 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4016 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4017 tuple_type = EVEX_FV;
4018 input_size_in_bits = EVEX_64bit;
4019 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4020 } else {
4021 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4022 }
4023 }
4024
4025 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4026 assert(VM_Version::supports_avx(), "");
4027 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4028 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4029 } else {
4030 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4031 }
4032 }
4033
4034 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4035 assert(VM_Version::supports_avx(), "");
4036 bool legacy_mode = (VM_Version::supports_avx512dq() == false);
4037 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode);
4038 }
4039
4040 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4041 assert(VM_Version::supports_avx(), "");
4042 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4043 tuple_type = EVEX_FV;
4044 input_size_in_bits = EVEX_64bit;
4045 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4046 } else {
4047 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4048 }
4049 }
4050
4051 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4052 assert(VM_Version::supports_avx(), "");
4053 if (VM_Version::supports_evex()) {
4054 tuple_type = EVEX_FV;
4055 input_size_in_bits = EVEX_32bit;
4056 }
4057 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
4058 (VM_Version::supports_avx512dq() == false));
4059 }
4060
4061 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4062 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4063 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4064 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4065 } else {
4066 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4067 }
4068 }
4069
4070 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4071 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4072 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE,
4073 false, (VM_Version::supports_avx512dq() == false));
4074 }
4075
4076 void Assembler::xorpd(XMMRegister dst, Address src) {
4077 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4078 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4079 tuple_type = EVEX_FV;
4080 input_size_in_bits = EVEX_64bit;
4081 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4082 } else {
4083 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4084 }
4085 }
4086
4087 void Assembler::xorps(XMMRegister dst, Address src) {
4088 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4089 if (VM_Version::supports_evex()) {
4090 tuple_type = EVEX_FV;
4091 input_size_in_bits = EVEX_32bit;
4092 }
4093 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false,
4094 (VM_Version::supports_avx512dq() == false));
4095 }
4096
4097 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4098 assert(VM_Version::supports_avx(), "");
4099 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4100 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4101 } else {
4102 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4103 }
4104 }
4105
4106 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4107 assert(VM_Version::supports_avx(), "");
4108 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4109 (VM_Version::supports_avx512dq() == false));
4110 }
4111
4112 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4113 assert(VM_Version::supports_avx(), "");
4114 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4115 tuple_type = EVEX_FV;
4116 input_size_in_bits = EVEX_64bit;
4117 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4118 } else {
4119 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4120 }
4121 }
4122
4123 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4124 assert(VM_Version::supports_avx(), "");
4125 if (VM_Version::supports_evex()) {
4126 tuple_type = EVEX_FV;
4127 input_size_in_bits = EVEX_32bit;
4128 }
4129 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4130 (VM_Version::supports_avx512dq() == false));
4131 }
4132
4133 // Integer vector arithmetic
4134 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4135 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4136 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4137 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4138 VEX_OPCODE_0F_38, true, false);
4139 emit_int8(0x01);
4140 emit_int8((unsigned char)(0xC0 | encode));
4141 }
4142
4143 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4144 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4145 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4146 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4147 VEX_OPCODE_0F_38, true, false);
4148 emit_int8(0x02);
4149 emit_int8((unsigned char)(0xC0 | encode));
4150 }
4151
4152 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4154 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
4155 }
4156
4157 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4158 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4159 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
4160 }
4161
4162 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4164 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4165 }
4166
4167 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4168 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4169 if (VM_Version::supports_evex()) {
4170 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4171 } else {
4172 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4173 }
4174 }
4175
4176 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4177 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4178 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4179 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4180 emit_int8(0x01);
4181 emit_int8((unsigned char)(0xC0 | encode));
4182 }
4183
4184 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4185 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4186 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4187 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4188 emit_int8(0x02);
4189 emit_int8((unsigned char)(0xC0 | encode));
4190 }
4191
4192 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4193 assert(UseAVX > 0, "requires some form of AVX");
4194 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len,
4195 (VM_Version::supports_avx512bw() == false));
4196 }
4197
4198 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4199 assert(UseAVX > 0, "requires some form of AVX");
4200 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len,
4201 (VM_Version::supports_avx512bw() == false));
4202 }
4203
4204 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4205 assert(UseAVX > 0, "requires some form of AVX");
4206 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4207 }
4208
4209 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4210 assert(UseAVX > 0, "requires some form of AVX");
4211 if (VM_Version::supports_evex()) {
4212 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4213 } else {
4214 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4215 }
4216 }
4217
4218 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4219 assert(UseAVX > 0, "requires some form of AVX");
4220 if (VM_Version::supports_evex()) {
4221 tuple_type = EVEX_FVM;
4222 }
4223 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len);
4224 }
4225
4226 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4227 assert(UseAVX > 0, "requires some form of AVX");
4228 if (VM_Version::supports_evex()) {
4229 tuple_type = EVEX_FVM;
4230 }
4231 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len);
4232 }
4233
4234 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4235 assert(UseAVX > 0, "requires some form of AVX");
4236 if (VM_Version::supports_evex()) {
4237 tuple_type = EVEX_FV;
4238 input_size_in_bits = EVEX_32bit;
4239 }
4240 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4241 }
4242
4243 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4244 assert(UseAVX > 0, "requires some form of AVX");
4245 if (VM_Version::supports_evex()) {
4246 tuple_type = EVEX_FV;
4247 input_size_in_bits = EVEX_64bit;
4248 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4249 } else {
4250 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4251 }
4252 }
4253
4254 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4255 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4256 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
4257 }
4258
4259 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4261 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
4262 }
4263
4264 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4265 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4266 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4267 }
4268
4269 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4270 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4271 if (VM_Version::supports_evex()) {
4272 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4273 } else {
4274 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4275 }
4276 }
4277
4278 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4279 assert(UseAVX > 0, "requires some form of AVX");
4280 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4281 (VM_Version::supports_avx512bw() == false));
4282 }
4283
4284 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4285 assert(UseAVX > 0, "requires some form of AVX");
4286 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4287 (VM_Version::supports_avx512bw() == false));
4288 }
4289
4290 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4291 assert(UseAVX > 0, "requires some form of AVX");
4292 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4293 }
4294
4295 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4296 assert(UseAVX > 0, "requires some form of AVX");
4297 if (VM_Version::supports_evex()) {
4298 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4299 } else {
4300 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4301 }
4302 }
4303
4304 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4305 assert(UseAVX > 0, "requires some form of AVX");
4306 if (VM_Version::supports_evex()) {
4307 tuple_type = EVEX_FVM;
4308 }
4309 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4310 (VM_Version::supports_avx512bw() == false));
4311 }
4312
4313 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4314 assert(UseAVX > 0, "requires some form of AVX");
4315 if (VM_Version::supports_evex()) {
4316 tuple_type = EVEX_FVM;
4317 }
4318 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4319 (VM_Version::supports_avx512bw() == false));
4320 }
4321
4322 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4323 assert(UseAVX > 0, "requires some form of AVX");
4324 if (VM_Version::supports_evex()) {
4325 tuple_type = EVEX_FV;
4326 input_size_in_bits = EVEX_32bit;
4327 }
4328 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4329 }
4330
4331 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4332 assert(UseAVX > 0, "requires some form of AVX");
4333 if (VM_Version::supports_evex()) {
4334 tuple_type = EVEX_FV;
4335 input_size_in_bits = EVEX_64bit;
4336 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4337 } else {
4338 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4339 }
4340 }
4341
4342 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4344 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66,
4345 (VM_Version::supports_avx512bw() == false));
4346 }
4347
4348 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4349 assert(VM_Version::supports_sse4_1(), "");
4350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4351 false, VEX_OPCODE_0F_38);
4352 emit_int8(0x40);
4353 emit_int8((unsigned char)(0xC0 | encode));
4354 }
4355
4356 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4357 assert(UseAVX > 0, "requires some form of AVX");
4358 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len,
4359 (VM_Version::supports_avx512bw() == false));
4360 }
4361
4362 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4363 assert(UseAVX > 0, "requires some form of AVX");
4364 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4365 vector_len, VEX_OPCODE_0F_38);
4366 emit_int8(0x40);
4367 emit_int8((unsigned char)(0xC0 | encode));
4368 }
4369
4370 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4371 assert(UseAVX > 2, "requires some form of AVX");
4372 int src_enc = src->encoding();
4373 int dst_enc = dst->encoding();
4374 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4375 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4376 VEX_OPCODE_0F_38, true, vector_len, false, false);
4377 emit_int8(0x40);
4378 emit_int8((unsigned char)(0xC0 | encode));
4379 }
4380
4381 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4382 assert(UseAVX > 0, "requires some form of AVX");
4383 if (VM_Version::supports_evex()) {
4384 tuple_type = EVEX_FVM;
4385 }
4386 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len);
4387 }
4388
4389 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4390 assert(UseAVX > 0, "requires some form of AVX");
4391 if (VM_Version::supports_evex()) {
4392 tuple_type = EVEX_FV;
4393 input_size_in_bits = EVEX_32bit;
4394 }
4395 InstructionMark im(this);
4396 int dst_enc = dst->encoding();
4397 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4398 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4399 VEX_OPCODE_0F_38, false, vector_len);
4400 emit_int8(0x40);
4401 emit_operand(dst, src);
4402 }
4403
4404 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4405 assert(UseAVX > 0, "requires some form of AVX");
4406 if (VM_Version::supports_evex()) {
4407 tuple_type = EVEX_FV;
4408 input_size_in_bits = EVEX_64bit;
4409 }
4410 InstructionMark im(this);
4411 int dst_enc = dst->encoding();
4412 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4413 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
4414 emit_int8(0x40);
4415 emit_operand(dst, src);
4416 }
4417
4418 // Shift packed integers left by specified number of bits.
4419 void Assembler::psllw(XMMRegister dst, int shift) {
4420 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4421 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4422 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4423 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
4424 emit_int8(0x71);
4425 emit_int8((unsigned char)(0xC0 | encode));
4426 emit_int8(shift & 0xFF);
4427 }
4428
4429 void Assembler::pslld(XMMRegister dst, int shift) {
4430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4431 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4432 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false);
4433 emit_int8(0x72);
4434 emit_int8((unsigned char)(0xC0 | encode));
4435 emit_int8(shift & 0xFF);
4436 }
4437
4438 void Assembler::psllq(XMMRegister dst, int shift) {
4439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4440 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4441 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4442 emit_int8(0x73);
4443 emit_int8((unsigned char)(0xC0 | encode));
4444 emit_int8(shift & 0xFF);
4445 }
4446
4447 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4448 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4449 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false,
4450 (VM_Version::supports_avx512bw() == false));
4451 }
4452
4453 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4454 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4455 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4456 }
4457
4458 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4459 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4460 if (VM_Version::supports_evex()) {
4461 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4462 } else {
4463 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4464 }
4465 }
4466
4467 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4468 assert(UseAVX > 0, "requires some form of AVX");
4469 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4470 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len,
4471 (VM_Version::supports_avx512bw() == false));
4472 emit_int8(shift & 0xFF);
4473 }
4474
4475 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4476 assert(UseAVX > 0, "requires some form of AVX");
4477 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4478 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4479 emit_int8(shift & 0xFF);
4480 }
4481
4482 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4483 assert(UseAVX > 0, "requires some form of AVX");
4484 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4485 if (VM_Version::supports_evex()) {
4486 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4487 } else {
4488 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4489 }
4490 emit_int8(shift & 0xFF);
4491 }
4492
4493 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4494 assert(UseAVX > 0, "requires some form of AVX");
4495 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len,
4496 (VM_Version::supports_avx512bw() == false));
4497 }
4498
4499 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4500 assert(UseAVX > 0, "requires some form of AVX");
4501 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4502 }
4503
4504 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4505 assert(UseAVX > 0, "requires some form of AVX");
4506 if (VM_Version::supports_evex()) {
4507 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4508 } else {
4509 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4510 }
4511 }
4512
4513 // Shift packed integers logically right by specified number of bits.
4514 void Assembler::psrlw(XMMRegister dst, int shift) {
4515 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4516 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4517 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4518 (VM_Version::supports_avx512bw() == false));
4519 emit_int8(0x71);
4520 emit_int8((unsigned char)(0xC0 | encode));
4521 emit_int8(shift & 0xFF);
4522 }
4523
4524 void Assembler::psrld(XMMRegister dst, int shift) {
4525 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4526 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4527 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false);
4528 emit_int8(0x72);
4529 emit_int8((unsigned char)(0xC0 | encode));
4530 emit_int8(shift & 0xFF);
4531 }
4532
4533 void Assembler::psrlq(XMMRegister dst, int shift) {
4534 // Do not confuse it with psrldq SSE2 instruction which
4535 // shifts 128 bit value in xmm register by number of bytes.
4536 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4537 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4538 int encode = 0;
4539 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) {
4540 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false);
4541 } else {
4542 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4543 }
4544 emit_int8(0x73);
4545 emit_int8((unsigned char)(0xC0 | encode));
4546 emit_int8(shift & 0xFF);
4547 }
4548
4549 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4550 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4551 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false,
4552 (VM_Version::supports_avx512bw() == false));
4553 }
4554
4555 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4556 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4557 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4558 }
4559
4560 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4561 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4562 if (VM_Version::supports_evex()) {
4563 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4564 } else {
4565 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4566 }
4567 }
4568
4569 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4570 assert(UseAVX > 0, "requires some form of AVX");
4571 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4572 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len,
4573 (VM_Version::supports_avx512bw() == false));
4574 emit_int8(shift & 0xFF);
4575 }
4576
4577 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4578 assert(UseAVX > 0, "requires some form of AVX");
4579 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4580 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4581 emit_int8(shift & 0xFF);
4582 }
4583
4584 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4585 assert(UseAVX > 0, "requires some form of AVX");
4586 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4587 if (VM_Version::supports_evex()) {
4588 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4589 } else {
4590 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4591 }
4592 emit_int8(shift & 0xFF);
4593 }
4594
4595 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4596 assert(UseAVX > 0, "requires some form of AVX");
4597 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len,
4598 (VM_Version::supports_avx512bw() == false));
4599 }
4600
4601 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4602 assert(UseAVX > 0, "requires some form of AVX");
4603 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4604 }
4605
4606 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4607 assert(UseAVX > 0, "requires some form of AVX");
4608 if (VM_Version::supports_evex()) {
4609 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4610 } else {
4611 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4612 }
4613 }
4614
4615 // Shift packed integers arithmetically right by specified number of bits.
4616 void Assembler::psraw(XMMRegister dst, int shift) {
4617 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4618 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4619 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4620 (VM_Version::supports_avx512bw() == false));
4621 emit_int8(0x71);
4622 emit_int8((unsigned char)(0xC0 | encode));
4623 emit_int8(shift & 0xFF);
4624 }
4625
4626 void Assembler::psrad(XMMRegister dst, int shift) {
4627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4628 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4629 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false);
4630 emit_int8(0x72);
4631 emit_int8((unsigned char)(0xC0 | encode));
4632 emit_int8(shift & 0xFF);
4633 }
4634
4635 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4637 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66,
4638 (VM_Version::supports_avx512bw() == false));
4639 }
4640
4641 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4643 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4644 }
4645
4646 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4647 assert(UseAVX > 0, "requires some form of AVX");
4648 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4649 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len,
4650 (VM_Version::supports_avx512bw() == false));
4651 emit_int8(shift & 0xFF);
4652 }
4653
4654 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4655 assert(UseAVX > 0, "requires some form of AVX");
4656 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4657 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4658 emit_int8(shift & 0xFF);
4659 }
4660
4661 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4662 assert(UseAVX > 0, "requires some form of AVX");
4663 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len,
4664 (VM_Version::supports_avx512bw() == false));
4665 }
4666
4667 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4668 assert(UseAVX > 0, "requires some form of AVX");
4669 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4670 }
4671
4672
4673 // AND packed integers
4674 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4676 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4677 }
4678
4679 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4680 assert(UseAVX > 0, "requires some form of AVX");
4681 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4682 }
4683
4684 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4685 assert(UseAVX > 0, "requires some form of AVX");
4686 if (VM_Version::supports_evex()) {
4687 tuple_type = EVEX_FV;
4688 input_size_in_bits = EVEX_32bit;
4689 }
4690 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4691 }
4692
4693 void Assembler::por(XMMRegister dst, XMMRegister src) {
4694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4695 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4696 }
4697
4698 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4699 assert(UseAVX > 0, "requires some form of AVX");
4700 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4701 }
4702
4703 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4704 assert(UseAVX > 0, "requires some form of AVX");
4705 if (VM_Version::supports_evex()) {
4706 tuple_type = EVEX_FV;
4707 input_size_in_bits = EVEX_32bit;
4708 }
4709 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4710 }
4711
4712 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
4713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4714 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
4715 }
4716
4717 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4718 assert(UseAVX > 0, "requires some form of AVX");
4719 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4720 }
4721
4722 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4723 assert(UseAVX > 0, "requires some form of AVX");
4724 if (VM_Version::supports_evex()) {
4725 tuple_type = EVEX_FV;
4726 input_size_in_bits = EVEX_32bit;
4727 }
4728 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4729 }
4730
4731
4732 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4733 assert(VM_Version::supports_avx(), "");
4734 int vector_len = AVX_256bit;
4735 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4736 emit_int8(0x18);
4737 emit_int8((unsigned char)(0xC0 | encode));
4738 // 0x00 - insert into lower 128 bits
4739 // 0x01 - insert into upper 128 bits
4740 emit_int8(0x01);
4741 }
4742
4743 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4744 assert(VM_Version::supports_evex(), "");
4745 int vector_len = AVX_512bit;
4746 int src_enc = src->encoding();
4747 int dst_enc = dst->encoding();
4748 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4749 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4750 VEX_OPCODE_0F_3A, true, vector_len, false, false);
4751 emit_int8(0x1A);
4752 emit_int8((unsigned char)(0xC0 | encode));
4753 // 0x00 - insert into lower 256 bits
4754 // 0x01 - insert into upper 256 bits
4755 emit_int8(0x01);
4756 }
4757
4758 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
4759 assert(VM_Version::supports_avx(), "");
4760 if (VM_Version::supports_evex()) {
4761 tuple_type = EVEX_T4;
4762 input_size_in_bits = EVEX_64bit;
4763 }
4764 InstructionMark im(this);
4765 int vector_len = AVX_512bit;
4766 assert(dst != xnoreg, "sanity");
4767 int dst_enc = dst->encoding();
4768 // swap src<->dst for encoding
4769 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len);
4770 emit_int8(0x1A);
4771 emit_operand(dst, src);
4772 // 0x01 - insert into upper 128 bits
4773 emit_int8(0x01);
4774 }
4775
4776 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
4777 assert(VM_Version::supports_avx(), "");
4778 if (VM_Version::supports_evex()) {
4779 tuple_type = EVEX_T4;
4780 input_size_in_bits = EVEX_32bit;
4781 }
4782 InstructionMark im(this);
4783 int vector_len = AVX_256bit;
4784 assert(dst != xnoreg, "sanity");
4785 int dst_enc = dst->encoding();
4786 // swap src<->dst for encoding
4787 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4788 emit_int8(0x18);
4789 emit_operand(dst, src);
4790 // 0x01 - insert into upper 128 bits
4791 emit_int8(0x01);
4792 }
4793
4794 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
4795 assert(VM_Version::supports_avx(), "");
4796 int vector_len = AVX_256bit;
4797 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4798 emit_int8(0x19);
4799 emit_int8((unsigned char)(0xC0 | encode));
4800 // 0x00 - insert into lower 128 bits
4801 // 0x01 - insert into upper 128 bits
4802 emit_int8(0x01);
4803 }
4804
4805 void Assembler::vextractf128h(Address dst, XMMRegister src) {
4806 assert(VM_Version::supports_avx(), "");
4807 if (VM_Version::supports_evex()) {
4808 tuple_type = EVEX_T4;
4809 input_size_in_bits = EVEX_32bit;
4810 }
4811 InstructionMark im(this);
4812 int vector_len = AVX_256bit;
4813 assert(src != xnoreg, "sanity");
4814 int src_enc = src->encoding();
4815 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4816 emit_int8(0x19);
4817 emit_operand(src, dst);
4818 // 0x01 - extract from upper 128 bits
4819 emit_int8(0x01);
4820 }
4821
4822 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4823 assert(VM_Version::supports_avx2(), "");
4824 int vector_len = AVX_256bit;
4825 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4826 emit_int8(0x38);
4827 emit_int8((unsigned char)(0xC0 | encode));
4828 // 0x00 - insert into lower 128 bits
4829 // 0x01 - insert into upper 128 bits
4830 emit_int8(0x01);
4831 }
4832
4833 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4834 assert(VM_Version::supports_evex(), "");
4835 int vector_len = AVX_512bit;
4836 int src_enc = src->encoding();
4837 int dst_enc = dst->encoding();
4838 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4839 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4840 VM_Version::supports_avx512dq(), vector_len, false, false);
4841 emit_int8(0x38);
4842 emit_int8((unsigned char)(0xC0 | encode));
4843 // 0x00 - insert into lower 256 bits
4844 // 0x01 - insert into upper 256 bits
4845 emit_int8(0x01);
4846 }
4847
4848 void Assembler::vinserti128h(XMMRegister dst, Address src) {
4849 assert(VM_Version::supports_avx2(), "");
4850 if (VM_Version::supports_evex()) {
4851 tuple_type = EVEX_T4;
4852 input_size_in_bits = EVEX_32bit;
4853 }
4854 InstructionMark im(this);
4855 int vector_len = AVX_256bit;
4856 assert(dst != xnoreg, "sanity");
4857 int dst_enc = dst->encoding();
4858 // swap src<->dst for encoding
4859 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4860 emit_int8(0x38);
4861 emit_operand(dst, src);
4862 // 0x01 - insert into upper 128 bits
4863 emit_int8(0x01);
4864 }
4865
4866 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
4867 assert(VM_Version::supports_avx(), "");
4868 int vector_len = AVX_256bit;
4869 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4870 emit_int8(0x39);
4871 emit_int8((unsigned char)(0xC0 | encode));
4872 // 0x00 - insert into lower 128 bits
4873 // 0x01 - insert into upper 128 bits
4874 emit_int8(0x01);
4875 }
4876
4877 void Assembler::vextracti128h(Address dst, XMMRegister src) {
4878 assert(VM_Version::supports_avx2(), "");
4879 if (VM_Version::supports_evex()) {
4880 tuple_type = EVEX_T4;
4881 input_size_in_bits = EVEX_32bit;
4882 }
4883 InstructionMark im(this);
4884 int vector_len = AVX_256bit;
4885 assert(src != xnoreg, "sanity");
4886 int src_enc = src->encoding();
4887 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4888 emit_int8(0x39);
4889 emit_operand(src, dst);
4890 // 0x01 - extract from upper 128 bits
4891 emit_int8(0x01);
4892 }
4893
4894 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
4895 assert(VM_Version::supports_evex(), "");
4896 int vector_len = AVX_512bit;
4897 int src_enc = src->encoding();
4898 int dst_enc = dst->encoding();
4899 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4900 true, vector_len, false, false);
4901 emit_int8(0x3B);
4902 emit_int8((unsigned char)(0xC0 | encode));
4903 // 0x01 - extract from upper 256 bits
4904 emit_int8(0x01);
4905 }
4906
4907 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
4908 assert(VM_Version::supports_evex(), "");
4909 int vector_len = AVX_512bit;
4910 int src_enc = src->encoding();
4911 int dst_enc = dst->encoding();
4912 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4913 VM_Version::supports_avx512dq(), vector_len, false, false);
4914 emit_int8(0x39);
4915 emit_int8((unsigned char)(0xC0 | encode));
4916 // 0x01 - extract from bits 255:128
4917 // 0x02 - extract from bits 383:256
4918 // 0x03 - extract from bits 511:384
4919 emit_int8(value & 0x3);
4920 }
4921
4922 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
4923 assert(VM_Version::supports_evex(), "");
4924 int vector_len = AVX_512bit;
4925 int src_enc = src->encoding();
4926 int dst_enc = dst->encoding();
4927 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4928 VM_Version::supports_avx512dq(), vector_len, false, false);
4929 emit_int8(0x1B);
4930 emit_int8((unsigned char)(0xC0 | encode));
4931 // 0x01 - extract from upper 256 bits
4932 emit_int8(0x01);
4933 }
4934
4935 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
4936 assert(VM_Version::supports_avx2(), "");
4937 tuple_type = EVEX_T4;
4938 input_size_in_bits = EVEX_64bit;
4939 InstructionMark im(this);
4940 int vector_len = AVX_512bit;
4941 assert(src != xnoreg, "sanity");
4942 int src_enc = src->encoding();
4943 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4944 VM_Version::supports_avx512dq(), vector_len);
4945 emit_int8(0x1B);
4946 emit_operand(src, dst);
4947 // 0x01 - extract from upper 128 bits
4948 emit_int8(0x01);
4949 }
4950
4951 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
4952 assert(VM_Version::supports_evex(), "");
4953 int vector_len = AVX_512bit;
4954 int src_enc = src->encoding();
4955 int dst_enc = dst->encoding();
4956 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66,
4957 VEX_OPCODE_0F_3A, false, vector_len, false, false);
4958 emit_int8(0x19);
4959 emit_int8((unsigned char)(0xC0 | encode));
4960 // 0x01 - extract from bits 255:128
4961 // 0x02 - extract from bits 383:256
4962 // 0x03 - extract from bits 511:384
4963 emit_int8(value & 0x3);
4964 }
4965
4966 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
4967 assert(VM_Version::supports_evex(), "");
4968 int vector_len = AVX_512bit;
4969 int src_enc = src->encoding();
4970 int dst_enc = dst->encoding();
4971 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4972 VM_Version::supports_avx512dq(), vector_len, false, false);
4973 emit_int8(0x19);
4974 emit_int8((unsigned char)(0xC0 | encode));
4975 // 0x01 - extract from bits 255:128
4976 // 0x02 - extract from bits 383:256
4977 // 0x03 - extract from bits 511:384
4978 emit_int8(value & 0x3);
4979 }
4980
4981 // duplicate 4-bytes integer data from src into 8 locations in dest
4982 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
4983 assert(VM_Version::supports_avx2(), "");
4984 int vector_len = AVX_256bit;
4985 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4986 vector_len, VEX_OPCODE_0F_38, false);
4987 emit_int8(0x58);
4988 emit_int8((unsigned char)(0xC0 | encode));
4989 }
4990
4991 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
4992 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
4993 assert(VM_Version::supports_evex(), "");
4994 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
4995 vector_len, VEX_OPCODE_0F_38, false);
4996 emit_int8(0x78);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 }
4999
5000 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5001 assert(VM_Version::supports_evex(), "");
5002 tuple_type = EVEX_T1S;
5003 input_size_in_bits = EVEX_8bit;
5004 InstructionMark im(this);
5005 assert(dst != xnoreg, "sanity");
5006 int dst_enc = dst->encoding();
5007 // swap src<->dst for encoding
5008 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5009 emit_int8(0x78);
5010 emit_operand(dst, src);
5011 }
5012
5013 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5014 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5015 assert(VM_Version::supports_evex(), "");
5016 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5017 vector_len, VEX_OPCODE_0F_38, false);
5018 emit_int8(0x79);
5019 emit_int8((unsigned char)(0xC0 | encode));
5020 }
5021
5022 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5023 assert(VM_Version::supports_evex(), "");
5024 tuple_type = EVEX_T1S;
5025 input_size_in_bits = EVEX_16bit;
5026 InstructionMark im(this);
5027 assert(dst != xnoreg, "sanity");
5028 int dst_enc = dst->encoding();
5029 // swap src<->dst for encoding
5030 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5031 emit_int8(0x79);
5032 emit_operand(dst, src);
5033 }
5034
5035 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5036 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5037 assert(VM_Version::supports_evex(), "");
5038 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5039 vector_len, VEX_OPCODE_0F_38, false);
5040 emit_int8(0x58);
5041 emit_int8((unsigned char)(0xC0 | encode));
5042 }
5043
5044 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5045 assert(VM_Version::supports_evex(), "");
5046 tuple_type = EVEX_T1S;
5047 input_size_in_bits = EVEX_32bit;
5048 InstructionMark im(this);
5049 assert(dst != xnoreg, "sanity");
5050 int dst_enc = dst->encoding();
5051 // swap src<->dst for encoding
5052 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5053 emit_int8(0x58);
5054 emit_operand(dst, src);
5055 }
5056
5057 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5058 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5059 assert(VM_Version::supports_evex(), "");
5060 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5061 VEX_OPCODE_0F_38, true, vector_len, false, false);
5062 emit_int8(0x59);
5063 emit_int8((unsigned char)(0xC0 | encode));
5064 }
5065
5066 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5067 assert(VM_Version::supports_evex(), "");
5068 tuple_type = EVEX_T1S;
5069 input_size_in_bits = EVEX_64bit;
5070 InstructionMark im(this);
5071 assert(dst != xnoreg, "sanity");
5072 int dst_enc = dst->encoding();
5073 // swap src<->dst for encoding
5074 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5075 emit_int8(0x59);
5076 emit_operand(dst, src);
5077 }
5078
5079 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5080 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5081 assert(VM_Version::supports_evex(), "");
5082 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5083 VEX_OPCODE_0F_38, false, vector_len, false, false);
5084 emit_int8(0x18);
5085 emit_int8((unsigned char)(0xC0 | encode));
5086 }
5087
5088 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5089 assert(VM_Version::supports_evex(), "");
5090 tuple_type = EVEX_T1S;
5091 input_size_in_bits = EVEX_32bit;
5092 InstructionMark im(this);
5093 assert(dst != xnoreg, "sanity");
5094 int dst_enc = dst->encoding();
5095 // swap src<->dst for encoding
5096 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5097 emit_int8(0x18);
5098 emit_operand(dst, src);
5099 }
5100
5101 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5102 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5103 assert(VM_Version::supports_evex(), "");
5104 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5105 VEX_OPCODE_0F_38, true, vector_len, false, false);
5106 emit_int8(0x19);
5107 emit_int8((unsigned char)(0xC0 | encode));
5108 }
5109
5110 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5111 assert(VM_Version::supports_evex(), "");
5112 tuple_type = EVEX_T1S;
5113 input_size_in_bits = EVEX_64bit;
5114 InstructionMark im(this);
5115 assert(dst != xnoreg, "sanity");
5116 int dst_enc = dst->encoding();
5117 // swap src<->dst for encoding
5118 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5119 emit_int8(0x19);
5120 emit_operand(dst, src);
5121 }
5122
5123 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5124 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5125 assert(VM_Version::supports_evex(), "");
5126 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5127 VEX_OPCODE_0F_38, false, vector_len, false, false);
5128 emit_int8(0x7A);
5129 emit_int8((unsigned char)(0xC0 | encode));
5130 }
5131
5132 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5133 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5134 assert(VM_Version::supports_evex(), "");
5135 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5136 VEX_OPCODE_0F_38, false, vector_len, false, false);
5137 emit_int8(0x7B);
5138 emit_int8((unsigned char)(0xC0 | encode));
5139 }
5140
5141 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5142 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5143 assert(VM_Version::supports_evex(), "");
5144 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5145 VEX_OPCODE_0F_38, false, vector_len, false, false);
5146 emit_int8(0x7C);
5147 emit_int8((unsigned char)(0xC0 | encode));
5148 }
5149
5150 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5151 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5152 assert(VM_Version::supports_evex(), "");
5153 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5154 VEX_OPCODE_0F_38, true, vector_len, false, false);
5155 emit_int8(0x7C);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 }
5158
5159 // Carry-Less Multiplication Quadword
5160 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5161 assert(VM_Version::supports_clmul(), "");
5162 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
5163 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
5164 emit_int8(0x44);
5165 emit_int8((unsigned char)(0xC0 | encode));
5166 emit_int8((unsigned char)mask);
5167 }
5168
5169 // Carry-Less Multiplication Quadword
5170 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5171 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5172 int vector_len = AVX_128bit;
5173 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
5174 vector_len, VEX_OPCODE_0F_3A, true);
5175 emit_int8(0x44);
5176 emit_int8((unsigned char)(0xC0 | encode));
5177 emit_int8((unsigned char)mask);
5178 }
5179
5180 void Assembler::vzeroupper() {
5181 assert(VM_Version::supports_avx(), "");
5182 if (UseAVX < 3)
5183 {
5184 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5185 emit_int8(0x77);
5186 }
5187 }
5188
5189
5190 #ifndef _LP64
5191 // 32bit only pieces of the assembler
5192
5193 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5194 // NO PREFIX AS NEVER 64BIT
5195 InstructionMark im(this);
5196 emit_int8((unsigned char)0x81);
5197 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5198 emit_data(imm32, rspec, 0);
5199 }
5200
5201 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5202 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5203 InstructionMark im(this);
5204 emit_int8((unsigned char)0x81);
5205 emit_operand(rdi, src1);
5206 emit_data(imm32, rspec, 0);
5207 }
5208
5209 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5210 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5211 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5212 void Assembler::cmpxchg8(Address adr) {
5213 InstructionMark im(this);
5214 emit_int8(0x0F);
5215 emit_int8((unsigned char)0xC7);
5216 emit_operand(rcx, adr);
5217 }
5218
5219 void Assembler::decl(Register dst) {
5220 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5221 emit_int8(0x48 | dst->encoding());
5222 }
5223
5224 #endif // _LP64
5225
5226 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5227
5228 void Assembler::fabs() {
5229 emit_int8((unsigned char)0xD9);
5230 emit_int8((unsigned char)0xE1);
5231 }
5232
5233 void Assembler::fadd(int i) {
5234 emit_farith(0xD8, 0xC0, i);
5235 }
5236
5237 void Assembler::fadd_d(Address src) {
5238 InstructionMark im(this);
5239 emit_int8((unsigned char)0xDC);
5240 emit_operand32(rax, src);
5241 }
5242
5243 void Assembler::fadd_s(Address src) {
5244 InstructionMark im(this);
5245 emit_int8((unsigned char)0xD8);
5246 emit_operand32(rax, src);
5247 }
5248
5249 void Assembler::fadda(int i) {
5250 emit_farith(0xDC, 0xC0, i);
5251 }
5252
5253 void Assembler::faddp(int i) {
5254 emit_farith(0xDE, 0xC0, i);
5255 }
5256
5257 void Assembler::fchs() {
5258 emit_int8((unsigned char)0xD9);
5259 emit_int8((unsigned char)0xE0);
5260 }
5261
5262 void Assembler::fcom(int i) {
5263 emit_farith(0xD8, 0xD0, i);
5264 }
5265
5266 void Assembler::fcomp(int i) {
5267 emit_farith(0xD8, 0xD8, i);
5268 }
5269
5270 void Assembler::fcomp_d(Address src) {
5271 InstructionMark im(this);
5272 emit_int8((unsigned char)0xDC);
5273 emit_operand32(rbx, src);
5274 }
5275
5276 void Assembler::fcomp_s(Address src) {
5277 InstructionMark im(this);
5278 emit_int8((unsigned char)0xD8);
5279 emit_operand32(rbx, src);
5280 }
5281
5282 void Assembler::fcompp() {
5283 emit_int8((unsigned char)0xDE);
5284 emit_int8((unsigned char)0xD9);
5285 }
5286
5287 void Assembler::fcos() {
5288 emit_int8((unsigned char)0xD9);
5289 emit_int8((unsigned char)0xFF);
5290 }
5291
5292 void Assembler::fdecstp() {
5293 emit_int8((unsigned char)0xD9);
5294 emit_int8((unsigned char)0xF6);
5295 }
5296
5297 void Assembler::fdiv(int i) {
5298 emit_farith(0xD8, 0xF0, i);
5299 }
5300
5301 void Assembler::fdiv_d(Address src) {
5302 InstructionMark im(this);
5303 emit_int8((unsigned char)0xDC);
5304 emit_operand32(rsi, src);
5305 }
5306
5307 void Assembler::fdiv_s(Address src) {
5308 InstructionMark im(this);
5309 emit_int8((unsigned char)0xD8);
5310 emit_operand32(rsi, src);
5311 }
5312
5313 void Assembler::fdiva(int i) {
5314 emit_farith(0xDC, 0xF8, i);
5315 }
5316
5317 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5318 // is erroneous for some of the floating-point instructions below.
5319
5320 void Assembler::fdivp(int i) {
5321 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5322 }
5323
5324 void Assembler::fdivr(int i) {
5325 emit_farith(0xD8, 0xF8, i);
5326 }
5327
5328 void Assembler::fdivr_d(Address src) {
5329 InstructionMark im(this);
5330 emit_int8((unsigned char)0xDC);
5331 emit_operand32(rdi, src);
5332 }
5333
5334 void Assembler::fdivr_s(Address src) {
5335 InstructionMark im(this);
5336 emit_int8((unsigned char)0xD8);
5337 emit_operand32(rdi, src);
5338 }
5339
5340 void Assembler::fdivra(int i) {
5341 emit_farith(0xDC, 0xF0, i);
5342 }
5343
5344 void Assembler::fdivrp(int i) {
5345 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5346 }
5347
5348 void Assembler::ffree(int i) {
5349 emit_farith(0xDD, 0xC0, i);
5350 }
5351
5352 void Assembler::fild_d(Address adr) {
5353 InstructionMark im(this);
5354 emit_int8((unsigned char)0xDF);
5355 emit_operand32(rbp, adr);
5356 }
5357
5358 void Assembler::fild_s(Address adr) {
5359 InstructionMark im(this);
5360 emit_int8((unsigned char)0xDB);
5361 emit_operand32(rax, adr);
5362 }
5363
5364 void Assembler::fincstp() {
5365 emit_int8((unsigned char)0xD9);
5366 emit_int8((unsigned char)0xF7);
5367 }
5368
5369 void Assembler::finit() {
5370 emit_int8((unsigned char)0x9B);
5371 emit_int8((unsigned char)0xDB);
5372 emit_int8((unsigned char)0xE3);
5373 }
5374
5375 void Assembler::fist_s(Address adr) {
5376 InstructionMark im(this);
5377 emit_int8((unsigned char)0xDB);
5378 emit_operand32(rdx, adr);
5379 }
5380
5381 void Assembler::fistp_d(Address adr) {
5382 InstructionMark im(this);
5383 emit_int8((unsigned char)0xDF);
5384 emit_operand32(rdi, adr);
5385 }
5386
5387 void Assembler::fistp_s(Address adr) {
5388 InstructionMark im(this);
5389 emit_int8((unsigned char)0xDB);
5390 emit_operand32(rbx, adr);
5391 }
5392
5393 void Assembler::fld1() {
5394 emit_int8((unsigned char)0xD9);
5395 emit_int8((unsigned char)0xE8);
5396 }
5397
5398 void Assembler::fld_d(Address adr) {
5399 InstructionMark im(this);
5400 emit_int8((unsigned char)0xDD);
5401 emit_operand32(rax, adr);
5402 }
5403
5404 void Assembler::fld_s(Address adr) {
5405 InstructionMark im(this);
5406 emit_int8((unsigned char)0xD9);
5407 emit_operand32(rax, adr);
5408 }
5409
5410
5411 void Assembler::fld_s(int index) {
5412 emit_farith(0xD9, 0xC0, index);
5413 }
5414
5415 void Assembler::fld_x(Address adr) {
5416 InstructionMark im(this);
5417 emit_int8((unsigned char)0xDB);
5418 emit_operand32(rbp, adr);
5419 }
5420
5421 void Assembler::fldcw(Address src) {
5422 InstructionMark im(this);
5423 emit_int8((unsigned char)0xD9);
5424 emit_operand32(rbp, src);
5425 }
5426
5427 void Assembler::fldenv(Address src) {
5428 InstructionMark im(this);
5429 emit_int8((unsigned char)0xD9);
5430 emit_operand32(rsp, src);
5431 }
5432
5433 void Assembler::fldlg2() {
5434 emit_int8((unsigned char)0xD9);
5435 emit_int8((unsigned char)0xEC);
5436 }
5437
5438 void Assembler::fldln2() {
5439 emit_int8((unsigned char)0xD9);
5440 emit_int8((unsigned char)0xED);
5441 }
5442
5443 void Assembler::fldz() {
5444 emit_int8((unsigned char)0xD9);
5445 emit_int8((unsigned char)0xEE);
5446 }
5447
5448 void Assembler::flog() {
5449 fldln2();
5450 fxch();
5451 fyl2x();
5452 }
5453
5454 void Assembler::flog10() {
5455 fldlg2();
5456 fxch();
5457 fyl2x();
5458 }
5459
5460 void Assembler::fmul(int i) {
5461 emit_farith(0xD8, 0xC8, i);
5462 }
5463
5464 void Assembler::fmul_d(Address src) {
5465 InstructionMark im(this);
5466 emit_int8((unsigned char)0xDC);
5467 emit_operand32(rcx, src);
5468 }
5469
5470 void Assembler::fmul_s(Address src) {
5471 InstructionMark im(this);
5472 emit_int8((unsigned char)0xD8);
5473 emit_operand32(rcx, src);
5474 }
5475
5476 void Assembler::fmula(int i) {
5477 emit_farith(0xDC, 0xC8, i);
5478 }
5479
5480 void Assembler::fmulp(int i) {
5481 emit_farith(0xDE, 0xC8, i);
5482 }
5483
5484 void Assembler::fnsave(Address dst) {
5485 InstructionMark im(this);
5486 emit_int8((unsigned char)0xDD);
5487 emit_operand32(rsi, dst);
5488 }
5489
5490 void Assembler::fnstcw(Address src) {
5491 InstructionMark im(this);
5492 emit_int8((unsigned char)0x9B);
5493 emit_int8((unsigned char)0xD9);
5494 emit_operand32(rdi, src);
5495 }
5496
5497 void Assembler::fnstsw_ax() {
5498 emit_int8((unsigned char)0xDF);
5499 emit_int8((unsigned char)0xE0);
5500 }
5501
5502 void Assembler::fprem() {
5503 emit_int8((unsigned char)0xD9);
5504 emit_int8((unsigned char)0xF8);
5505 }
5506
5507 void Assembler::fprem1() {
5508 emit_int8((unsigned char)0xD9);
5509 emit_int8((unsigned char)0xF5);
5510 }
5511
5512 void Assembler::frstor(Address src) {
5513 InstructionMark im(this);
5514 emit_int8((unsigned char)0xDD);
5515 emit_operand32(rsp, src);
5516 }
5517
5518 void Assembler::fsin() {
5519 emit_int8((unsigned char)0xD9);
5520 emit_int8((unsigned char)0xFE);
5521 }
5522
5523 void Assembler::fsqrt() {
5524 emit_int8((unsigned char)0xD9);
5525 emit_int8((unsigned char)0xFA);
5526 }
5527
5528 void Assembler::fst_d(Address adr) {
5529 InstructionMark im(this);
5530 emit_int8((unsigned char)0xDD);
5531 emit_operand32(rdx, adr);
5532 }
5533
5534 void Assembler::fst_s(Address adr) {
5535 InstructionMark im(this);
5536 emit_int8((unsigned char)0xD9);
5537 emit_operand32(rdx, adr);
5538 }
5539
5540 void Assembler::fstp_d(Address adr) {
5541 InstructionMark im(this);
5542 emit_int8((unsigned char)0xDD);
5543 emit_operand32(rbx, adr);
5544 }
5545
5546 void Assembler::fstp_d(int index) {
5547 emit_farith(0xDD, 0xD8, index);
5548 }
5549
5550 void Assembler::fstp_s(Address adr) {
5551 InstructionMark im(this);
5552 emit_int8((unsigned char)0xD9);
5553 emit_operand32(rbx, adr);
5554 }
5555
5556 void Assembler::fstp_x(Address adr) {
5557 InstructionMark im(this);
5558 emit_int8((unsigned char)0xDB);
5559 emit_operand32(rdi, adr);
5560 }
5561
5562 void Assembler::fsub(int i) {
5563 emit_farith(0xD8, 0xE0, i);
5564 }
5565
5566 void Assembler::fsub_d(Address src) {
5567 InstructionMark im(this);
5568 emit_int8((unsigned char)0xDC);
5569 emit_operand32(rsp, src);
5570 }
5571
5572 void Assembler::fsub_s(Address src) {
5573 InstructionMark im(this);
5574 emit_int8((unsigned char)0xD8);
5575 emit_operand32(rsp, src);
5576 }
5577
5578 void Assembler::fsuba(int i) {
5579 emit_farith(0xDC, 0xE8, i);
5580 }
5581
5582 void Assembler::fsubp(int i) {
5583 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5584 }
5585
5586 void Assembler::fsubr(int i) {
5587 emit_farith(0xD8, 0xE8, i);
5588 }
5589
5590 void Assembler::fsubr_d(Address src) {
5591 InstructionMark im(this);
5592 emit_int8((unsigned char)0xDC);
5593 emit_operand32(rbp, src);
5594 }
5595
5596 void Assembler::fsubr_s(Address src) {
5597 InstructionMark im(this);
5598 emit_int8((unsigned char)0xD8);
5599 emit_operand32(rbp, src);
5600 }
5601
5602 void Assembler::fsubra(int i) {
5603 emit_farith(0xDC, 0xE0, i);
5604 }
5605
5606 void Assembler::fsubrp(int i) {
5607 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
5608 }
5609
5610 void Assembler::ftan() {
5611 emit_int8((unsigned char)0xD9);
5612 emit_int8((unsigned char)0xF2);
5613 emit_int8((unsigned char)0xDD);
5614 emit_int8((unsigned char)0xD8);
5615 }
5616
5617 void Assembler::ftst() {
5618 emit_int8((unsigned char)0xD9);
5619 emit_int8((unsigned char)0xE4);
5620 }
5621
5622 void Assembler::fucomi(int i) {
5623 // make sure the instruction is supported (introduced for P6, together with cmov)
5624 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5625 emit_farith(0xDB, 0xE8, i);
5626 }
5627
5628 void Assembler::fucomip(int i) {
5629 // make sure the instruction is supported (introduced for P6, together with cmov)
5630 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5631 emit_farith(0xDF, 0xE8, i);
5632 }
5633
5634 void Assembler::fwait() {
5635 emit_int8((unsigned char)0x9B);
5636 }
5637
5638 void Assembler::fxch(int i) {
5639 emit_farith(0xD9, 0xC8, i);
5640 }
5641
5642 void Assembler::fyl2x() {
5643 emit_int8((unsigned char)0xD9);
5644 emit_int8((unsigned char)0xF1);
5645 }
5646
5647 void Assembler::frndint() {
5648 emit_int8((unsigned char)0xD9);
5649 emit_int8((unsigned char)0xFC);
5650 }
5651
5652 void Assembler::f2xm1() {
5653 emit_int8((unsigned char)0xD9);
5654 emit_int8((unsigned char)0xF0);
5655 }
5656
5657 void Assembler::fldl2e() {
5658 emit_int8((unsigned char)0xD9);
5659 emit_int8((unsigned char)0xEA);
5660 }
5661
5662 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
5663 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
5664 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
5665 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
5666
5667 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
5668 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5669 if (pre > 0) {
5670 emit_int8(simd_pre[pre]);
5671 }
5672 if (rex_w) {
5673 prefixq(adr, xreg);
5674 } else {
5675 prefix(adr, xreg);
5676 }
5677 if (opc > 0) {
5678 emit_int8(0x0F);
5679 int opc2 = simd_opc[opc];
5680 if (opc2 > 0) {
5681 emit_int8(opc2);
5682 }
5683 }
5684 }
5685
5686 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5687 if (pre > 0) {
5688 emit_int8(simd_pre[pre]);
5689 }
5690 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
5691 prefix_and_encode(dst_enc, src_enc);
5692 if (opc > 0) {
5693 emit_int8(0x0F);
5694 int opc2 = simd_opc[opc];
5695 if (opc2 > 0) {
5696 emit_int8(opc2);
5697 }
5698 }
5699 return encode;
5700 }
5701
5702
5703 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
5704 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
5705 prefix(VEX_3bytes);
5706
5707 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
5708 byte1 = (~byte1) & 0xE0;
5709 byte1 |= opc;
5710 emit_int8(byte1);
5711
5712 int byte2 = ((~nds_enc) & 0xf) << 3;
5713 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
5714 emit_int8(byte2);
5715 } else {
5716 prefix(VEX_2bytes);
5717
5718 int byte1 = vex_r ? VEX_R : 0;
5719 byte1 = (~byte1) & 0x80;
5720 byte1 |= ((~nds_enc) & 0xf) << 3;
5721 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
5722 emit_int8(byte1);
5723 }
5724 }
5725
5726 // This is a 4 byte encoding
5727 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
5728 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
5729 bool is_extended_context, bool is_merge_context,
5730 int vector_len, bool no_mask_reg ){
5731 // EVEX 0x62 prefix
5732 prefix(EVEX_4bytes);
5733 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
5734
5735 // P0: byte 2, initialized to RXBR`00mm
5736 // instead of not'd
5737 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
5738 byte2 = (~byte2) & 0xF0;
5739 // confine opc opcode extensions in mm bits to lower two bits
5740 // of form {0F, 0F_38, 0F_3A}
5741 byte2 |= opc;
5742 emit_int8(byte2);
5743
5744 // P1: byte 3 as Wvvvv1pp
5745 int byte3 = ((~nds_enc) & 0xf) << 3;
5746 // p[10] is always 1
5747 byte3 |= EVEX_F;
5748 byte3 |= (vex_w & 1) << 7;
5749 // confine pre opcode extensions in pp bits to lower two bits
5750 // of form {66, F3, F2}
5751 byte3 |= pre;
5752 emit_int8(byte3);
5753
5754 // P2: byte 4 as zL'Lbv'aaa
5755 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
5756 // EVEX.v` for extending EVEX.vvvv or VIDX
5757 byte4 |= (evex_v ? 0: EVEX_V);
5758 // third EXEC.b for broadcast actions
5759 byte4 |= (is_extended_context ? EVEX_Rb : 0);
5760 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
5761 byte4 |= ((vector_len) & 0x3) << 5;
5762 // last is EVEX.z for zero/merge actions
5763 byte4 |= (is_merge_context ? EVEX_Z : 0);
5764 emit_int8(byte4);
5765 }
5766
5767 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
5768 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
5769 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
5770 bool vex_b = adr.base_needs_rex();
5771 bool vex_x = adr.index_needs_rex();
5772 avx_vector_len = vector_len;
5773
5774 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5775 if (VM_Version::supports_avx512vl() == false) {
5776 switch (vector_len) {
5777 case AVX_128bit:
5778 case AVX_256bit:
5779 legacy_mode = true;
5780 break;
5781 }
5782 }
5783
5784 if ((UseAVX > 2) && (legacy_mode == false))
5785 {
5786 bool evex_r = (xreg_enc >= 16);
5787 bool evex_v = (nds_enc >= 16);
5788 is_evex_instruction = true;
5789 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5790 } else {
5791 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5792 }
5793 }
5794
5795 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
5796 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
5797 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
5798 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
5799 bool vex_x = false;
5800 avx_vector_len = vector_len;
5801
5802 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5803 if (VM_Version::supports_avx512vl() == false) {
5804 switch (vector_len) {
5805 case AVX_128bit:
5806 case AVX_256bit:
5807 legacy_mode = true;
5808 break;
5809 }
5810 }
5811
5812 if ((UseAVX > 2) && (legacy_mode == false))
5813 {
5814 bool evex_r = (dst_enc >= 16);
5815 bool evex_v = (nds_enc >= 16);
5816 // can use vex_x as bank extender on rm encoding
5817 vex_x = (src_enc >= 16);
5818 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5819 } else {
5820 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5821 }
5822
5823 // return modrm byte components for operands
5824 return (((dst_enc & 7) << 3) | (src_enc & 7));
5825 }
5826
5827
5828 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
5829 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5830 if (UseAVX > 0) {
5831 int xreg_enc = xreg->encoding();
5832 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5833 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5834 } else {
5835 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
5836 rex_prefix(adr, xreg, pre, opc, rex_w);
5837 }
5838 }
5839
5840 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
5841 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5842 int dst_enc = dst->encoding();
5843 int src_enc = src->encoding();
5844 if (UseAVX > 0) {
5845 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5846 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5847 } else {
5848 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
5849 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
5850 }
5851 }
5852
5853 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
5854 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5855 int dst_enc = dst->encoding();
5856 int src_enc = src->encoding();
5857 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5858 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5859 }
5860
5861 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
5862 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5863 int dst_enc = dst->encoding();
5864 int src_enc = src->encoding();
5865 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5866 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5867 }
5868
5869 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5870 InstructionMark im(this);
5871 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5872 emit_int8(opcode);
5873 emit_operand(dst, src);
5874 }
5875
5876 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
5877 InstructionMark im(this);
5878 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
5879 emit_int8(opcode);
5880 emit_operand(dst, src);
5881 }
5882
5883 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5884 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5885 emit_int8(opcode);
5886 emit_int8((unsigned char)(0xC0 | encode));
5887 }
5888
5889 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5890 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5891 emit_int8(opcode);
5892 emit_int8((unsigned char)(0xC0 | encode));
5893 }
5894
5895 // Versions with no second source register (non-destructive source).
5896 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5897 InstructionMark im(this);
5898 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
5899 emit_int8(opcode);
5900 emit_operand(dst, src);
5901 }
5902
5903 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5904 InstructionMark im(this);
5905 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
5906 emit_int8(opcode);
5907 emit_operand(dst, src);
5908 }
5909
5910 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5911 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit);
5912 emit_int8(opcode);
5913 emit_int8((unsigned char)(0xC0 | encode));
5914 }
5915
5916 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5917 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5918 emit_int8(opcode);
5919 emit_int8((unsigned char)(0xC0 | encode));
5920 }
5921
5922 // 3-operands AVX instructions
5923 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
5924 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5925 InstructionMark im(this);
5926 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
5927 emit_int8(opcode);
5928 emit_operand(dst, src);
5929 }
5930
5931 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
5932 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5933 InstructionMark im(this);
5934 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
5935 emit_int8(opcode);
5936 emit_operand(dst, src);
5937 }
5938
5939 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5940 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5941 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg);
5942 emit_int8(opcode);
5943 emit_int8((unsigned char)(0xC0 | encode));
5944 }
5945
5946 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5947 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5948 int src_enc = src->encoding();
5949 int dst_enc = dst->encoding();
5950 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5951 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
5952 emit_int8(opcode);
5953 emit_int8((unsigned char)(0xC0 | encode));
5954 }
5955
5956 #ifndef _LP64
5957
5958 void Assembler::incl(Register dst) {
5959 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5960 emit_int8(0x40 | dst->encoding());
5961 }
5962
5963 void Assembler::lea(Register dst, Address src) {
5964 leal(dst, src);
5965 }
5966
5967 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5968 InstructionMark im(this);
5969 emit_int8((unsigned char)0xC7);
5970 emit_operand(rax, dst);
5971 emit_data((int)imm32, rspec, 0);
5972 }
5973
5974 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5975 InstructionMark im(this);
5976 int encode = prefix_and_encode(dst->encoding());
5977 emit_int8((unsigned char)(0xB8 | encode));
5978 emit_data((int)imm32, rspec, 0);
5979 }
5980
5981 void Assembler::popa() { // 32bit
5982 emit_int8(0x61);
5983 }
5984
5985 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
5986 InstructionMark im(this);
5987 emit_int8(0x68);
5988 emit_data(imm32, rspec, 0);
5989 }
5990
5991 void Assembler::pusha() { // 32bit
5992 emit_int8(0x60);
5993 }
5994
5995 void Assembler::set_byte_if_not_zero(Register dst) {
5996 emit_int8(0x0F);
5997 emit_int8((unsigned char)0x95);
5998 emit_int8((unsigned char)(0xE0 | dst->encoding()));
5999 }
6000
6001 void Assembler::shldl(Register dst, Register src) {
6002 emit_int8(0x0F);
6003 emit_int8((unsigned char)0xA5);
6004 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6005 }
6006
6007 void Assembler::shrdl(Register dst, Register src) {
6008 emit_int8(0x0F);
6009 emit_int8((unsigned char)0xAD);
6010 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6011 }
6012
6013 #else // LP64
6014
6015 void Assembler::set_byte_if_not_zero(Register dst) {
6016 int enc = prefix_and_encode(dst->encoding(), true);
6017 emit_int8(0x0F);
6018 emit_int8((unsigned char)0x95);
6019 emit_int8((unsigned char)(0xE0 | enc));
6020 }
6021
6022 // 64bit only pieces of the assembler
6023 // This should only be used by 64bit instructions that can use rip-relative
6024 // it cannot be used by instructions that want an immediate value.
6025
6026 bool Assembler::reachable(AddressLiteral adr) {
6027 int64_t disp;
6028 // None will force a 64bit literal to the code stream. Likely a placeholder
6029 // for something that will be patched later and we need to certain it will
6030 // always be reachable.
6031 if (adr.reloc() == relocInfo::none) {
6032 return false;
6033 }
6034 if (adr.reloc() == relocInfo::internal_word_type) {
6035 // This should be rip relative and easily reachable.
6036 return true;
6037 }
6038 if (adr.reloc() == relocInfo::virtual_call_type ||
6039 adr.reloc() == relocInfo::opt_virtual_call_type ||
6040 adr.reloc() == relocInfo::static_call_type ||
6041 adr.reloc() == relocInfo::static_stub_type ) {
6042 // This should be rip relative within the code cache and easily
6043 // reachable until we get huge code caches. (At which point
6044 // ic code is going to have issues).
6045 return true;
6046 }
6047 if (adr.reloc() != relocInfo::external_word_type &&
6048 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6049 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6050 adr.reloc() != relocInfo::runtime_call_type ) {
6051 return false;
6052 }
6053
6054 // Stress the correction code
6055 if (ForceUnreachable) {
6056 // Must be runtimecall reloc, see if it is in the codecache
6057 // Flipping stuff in the codecache to be unreachable causes issues
6058 // with things like inline caches where the additional instructions
6059 // are not handled.
6060 if (CodeCache::find_blob(adr._target) == NULL) {
6061 return false;
6062 }
6063 }
6064 // For external_word_type/runtime_call_type if it is reachable from where we
6065 // are now (possibly a temp buffer) and where we might end up
6066 // anywhere in the codeCache then we are always reachable.
6067 // This would have to change if we ever save/restore shared code
6068 // to be more pessimistic.
6069 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6070 if (!is_simm32(disp)) return false;
6071 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6072 if (!is_simm32(disp)) return false;
6073
6074 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6075
6076 // Because rip relative is a disp + address_of_next_instruction and we
6077 // don't know the value of address_of_next_instruction we apply a fudge factor
6078 // to make sure we will be ok no matter the size of the instruction we get placed into.
6079 // We don't have to fudge the checks above here because they are already worst case.
6080
6081 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6082 // + 4 because better safe than sorry.
6083 const int fudge = 12 + 4;
6084 if (disp < 0) {
6085 disp -= fudge;
6086 } else {
6087 disp += fudge;
6088 }
6089 return is_simm32(disp);
6090 }
6091
6092 // Check if the polling page is not reachable from the code cache using rip-relative
6093 // addressing.
6094 bool Assembler::is_polling_page_far() {
6095 intptr_t addr = (intptr_t)os::get_polling_page();
6096 return ForceUnreachable ||
6097 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6098 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6099 }
6100
6101 void Assembler::emit_data64(jlong data,
6102 relocInfo::relocType rtype,
6103 int format) {
6104 if (rtype == relocInfo::none) {
6105 emit_int64(data);
6106 } else {
6107 emit_data64(data, Relocation::spec_simple(rtype), format);
6108 }
6109 }
6110
6111 void Assembler::emit_data64(jlong data,
6112 RelocationHolder const& rspec,
6113 int format) {
6114 assert(imm_operand == 0, "default format must be immediate in this file");
6115 assert(imm_operand == format, "must be immediate");
6116 assert(inst_mark() != NULL, "must be inside InstructionMark");
6117 // Do not use AbstractAssembler::relocate, which is not intended for
6118 // embedded words. Instead, relocate to the enclosing instruction.
6119 code_section()->relocate(inst_mark(), rspec, format);
6120 #ifdef ASSERT
6121 check_relocation(rspec, format);
6122 #endif
6123 emit_int64(data);
6124 }
6125
6126 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6127 if (reg_enc >= 8) {
6128 prefix(REX_B);
6129 reg_enc -= 8;
6130 } else if (byteinst && reg_enc >= 4) {
6131 prefix(REX);
6132 }
6133 return reg_enc;
6134 }
6135
6136 int Assembler::prefixq_and_encode(int reg_enc) {
6137 if (reg_enc < 8) {
6138 prefix(REX_W);
6139 } else {
6140 prefix(REX_WB);
6141 reg_enc -= 8;
6142 }
6143 return reg_enc;
6144 }
6145
6146 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
6147 if (dst_enc < 8) {
6148 if (src_enc >= 8) {
6149 prefix(REX_B);
6150 src_enc -= 8;
6151 } else if (byteinst && src_enc >= 4) {
6152 prefix(REX);
6153 }
6154 } else {
6155 if (src_enc < 8) {
6156 prefix(REX_R);
6157 } else {
6158 prefix(REX_RB);
6159 src_enc -= 8;
6160 }
6161 dst_enc -= 8;
6162 }
6163 return dst_enc << 3 | src_enc;
6164 }
6165
6166 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6167 if (dst_enc < 8) {
6168 if (src_enc < 8) {
6169 prefix(REX_W);
6170 } else {
6171 prefix(REX_WB);
6172 src_enc -= 8;
6173 }
6174 } else {
6175 if (src_enc < 8) {
6176 prefix(REX_WR);
6177 } else {
6178 prefix(REX_WRB);
6179 src_enc -= 8;
6180 }
6181 dst_enc -= 8;
6182 }
6183 return dst_enc << 3 | src_enc;
6184 }
6185
6186 void Assembler::prefix(Register reg) {
6187 if (reg->encoding() >= 8) {
6188 prefix(REX_B);
6189 }
6190 }
6191
6192 void Assembler::prefix(Address adr) {
6193 if (adr.base_needs_rex()) {
6194 if (adr.index_needs_rex()) {
6195 prefix(REX_XB);
6196 } else {
6197 prefix(REX_B);
6198 }
6199 } else {
6200 if (adr.index_needs_rex()) {
6201 prefix(REX_X);
6202 }
6203 }
6204 }
6205
6206 void Assembler::prefixq(Address adr) {
6207 if (adr.base_needs_rex()) {
6208 if (adr.index_needs_rex()) {
6209 prefix(REX_WXB);
6210 } else {
6211 prefix(REX_WB);
6212 }
6213 } else {
6214 if (adr.index_needs_rex()) {
6215 prefix(REX_WX);
6216 } else {
6217 prefix(REX_W);
6218 }
6219 }
6220 }
6221
6222
6223 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6224 if (reg->encoding() < 8) {
6225 if (adr.base_needs_rex()) {
6226 if (adr.index_needs_rex()) {
6227 prefix(REX_XB);
6228 } else {
6229 prefix(REX_B);
6230 }
6231 } else {
6232 if (adr.index_needs_rex()) {
6233 prefix(REX_X);
6234 } else if (byteinst && reg->encoding() >= 4 ) {
6235 prefix(REX);
6236 }
6237 }
6238 } else {
6239 if (adr.base_needs_rex()) {
6240 if (adr.index_needs_rex()) {
6241 prefix(REX_RXB);
6242 } else {
6243 prefix(REX_RB);
6244 }
6245 } else {
6246 if (adr.index_needs_rex()) {
6247 prefix(REX_RX);
6248 } else {
6249 prefix(REX_R);
6250 }
6251 }
6252 }
6253 }
6254
6255 void Assembler::prefixq(Address adr, Register src) {
6256 if (src->encoding() < 8) {
6257 if (adr.base_needs_rex()) {
6258 if (adr.index_needs_rex()) {
6259 prefix(REX_WXB);
6260 } else {
6261 prefix(REX_WB);
6262 }
6263 } else {
6264 if (adr.index_needs_rex()) {
6265 prefix(REX_WX);
6266 } else {
6267 prefix(REX_W);
6268 }
6269 }
6270 } else {
6271 if (adr.base_needs_rex()) {
6272 if (adr.index_needs_rex()) {
6273 prefix(REX_WRXB);
6274 } else {
6275 prefix(REX_WRB);
6276 }
6277 } else {
6278 if (adr.index_needs_rex()) {
6279 prefix(REX_WRX);
6280 } else {
6281 prefix(REX_WR);
6282 }
6283 }
6284 }
6285 }
6286
6287 void Assembler::prefix(Address adr, XMMRegister reg) {
6288 if (reg->encoding() < 8) {
6289 if (adr.base_needs_rex()) {
6290 if (adr.index_needs_rex()) {
6291 prefix(REX_XB);
6292 } else {
6293 prefix(REX_B);
6294 }
6295 } else {
6296 if (adr.index_needs_rex()) {
6297 prefix(REX_X);
6298 }
6299 }
6300 } else {
6301 if (adr.base_needs_rex()) {
6302 if (adr.index_needs_rex()) {
6303 prefix(REX_RXB);
6304 } else {
6305 prefix(REX_RB);
6306 }
6307 } else {
6308 if (adr.index_needs_rex()) {
6309 prefix(REX_RX);
6310 } else {
6311 prefix(REX_R);
6312 }
6313 }
6314 }
6315 }
6316
6317 void Assembler::prefixq(Address adr, XMMRegister src) {
6318 if (src->encoding() < 8) {
6319 if (adr.base_needs_rex()) {
6320 if (adr.index_needs_rex()) {
6321 prefix(REX_WXB);
6322 } else {
6323 prefix(REX_WB);
6324 }
6325 } else {
6326 if (adr.index_needs_rex()) {
6327 prefix(REX_WX);
6328 } else {
6329 prefix(REX_W);
6330 }
6331 }
6332 } else {
6333 if (adr.base_needs_rex()) {
6334 if (adr.index_needs_rex()) {
6335 prefix(REX_WRXB);
6336 } else {
6337 prefix(REX_WRB);
6338 }
6339 } else {
6340 if (adr.index_needs_rex()) {
6341 prefix(REX_WRX);
6342 } else {
6343 prefix(REX_WR);
6344 }
6345 }
6346 }
6347 }
6348
6349 void Assembler::adcq(Register dst, int32_t imm32) {
6350 (void) prefixq_and_encode(dst->encoding());
6351 emit_arith(0x81, 0xD0, dst, imm32);
6352 }
6353
6354 void Assembler::adcq(Register dst, Address src) {
6355 InstructionMark im(this);
6356 prefixq(src, dst);
6357 emit_int8(0x13);
6358 emit_operand(dst, src);
6359 }
6360
6361 void Assembler::adcq(Register dst, Register src) {
6362 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6363 emit_arith(0x13, 0xC0, dst, src);
6364 }
6365
6366 void Assembler::addq(Address dst, int32_t imm32) {
6367 InstructionMark im(this);
6368 prefixq(dst);
6369 emit_arith_operand(0x81, rax, dst,imm32);
6370 }
6371
6372 void Assembler::addq(Address dst, Register src) {
6373 InstructionMark im(this);
6374 prefixq(dst, src);
6375 emit_int8(0x01);
6376 emit_operand(src, dst);
6377 }
6378
6379 void Assembler::addq(Register dst, int32_t imm32) {
6380 (void) prefixq_and_encode(dst->encoding());
6381 emit_arith(0x81, 0xC0, dst, imm32);
6382 }
6383
6384 void Assembler::addq(Register dst, Address src) {
6385 InstructionMark im(this);
6386 prefixq(src, dst);
6387 emit_int8(0x03);
6388 emit_operand(dst, src);
6389 }
6390
6391 void Assembler::addq(Register dst, Register src) {
6392 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6393 emit_arith(0x03, 0xC0, dst, src);
6394 }
6395
6396 void Assembler::adcxq(Register dst, Register src) {
6397 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6398 emit_int8((unsigned char)0x66);
6399 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6400 emit_int8(0x0F);
6401 emit_int8(0x38);
6402 emit_int8((unsigned char)0xF6);
6403 emit_int8((unsigned char)(0xC0 | encode));
6404 }
6405
6406 void Assembler::adoxq(Register dst, Register src) {
6407 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6408 emit_int8((unsigned char)0xF3);
6409 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6410 emit_int8(0x0F);
6411 emit_int8(0x38);
6412 emit_int8((unsigned char)0xF6);
6413 emit_int8((unsigned char)(0xC0 | encode));
6414 }
6415
6416 void Assembler::andq(Address dst, int32_t imm32) {
6417 InstructionMark im(this);
6418 prefixq(dst);
6419 emit_int8((unsigned char)0x81);
6420 emit_operand(rsp, dst, 4);
6421 emit_int32(imm32);
6422 }
6423
6424 void Assembler::andq(Register dst, int32_t imm32) {
6425 (void) prefixq_and_encode(dst->encoding());
6426 emit_arith(0x81, 0xE0, dst, imm32);
6427 }
6428
6429 void Assembler::andq(Register dst, Address src) {
6430 InstructionMark im(this);
6431 prefixq(src, dst);
6432 emit_int8(0x23);
6433 emit_operand(dst, src);
6434 }
6435
6436 void Assembler::andq(Register dst, Register src) {
6437 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6438 emit_arith(0x23, 0xC0, dst, src);
6439 }
6440
6441 void Assembler::andnq(Register dst, Register src1, Register src2) {
6442 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6443 int encode = vex_prefix_0F38_and_encode_q_legacy(dst, src1, src2);
6444 emit_int8((unsigned char)0xF2);
6445 emit_int8((unsigned char)(0xC0 | encode));
6446 }
6447
6448 void Assembler::andnq(Register dst, Register src1, Address src2) {
6449 InstructionMark im(this);
6450 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6451 vex_prefix_0F38_q_legacy(dst, src1, src2);
6452 emit_int8((unsigned char)0xF2);
6453 emit_operand(dst, src2);
6454 }
6455
6456 void Assembler::bsfq(Register dst, Register src) {
6457 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6458 emit_int8(0x0F);
6459 emit_int8((unsigned char)0xBC);
6460 emit_int8((unsigned char)(0xC0 | encode));
6461 }
6462
6463 void Assembler::bsrq(Register dst, Register src) {
6464 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6465 emit_int8(0x0F);
6466 emit_int8((unsigned char)0xBD);
6467 emit_int8((unsigned char)(0xC0 | encode));
6468 }
6469
6470 void Assembler::bswapq(Register reg) {
6471 int encode = prefixq_and_encode(reg->encoding());
6472 emit_int8(0x0F);
6473 emit_int8((unsigned char)(0xC8 | encode));
6474 }
6475
6476 void Assembler::blsiq(Register dst, Register src) {
6477 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6478 int encode = vex_prefix_0F38_and_encode_q_legacy(rbx, dst, src);
6479 emit_int8((unsigned char)0xF3);
6480 emit_int8((unsigned char)(0xC0 | encode));
6481 }
6482
6483 void Assembler::blsiq(Register dst, Address src) {
6484 InstructionMark im(this);
6485 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6486 vex_prefix_0F38_q_legacy(rbx, dst, src);
6487 emit_int8((unsigned char)0xF3);
6488 emit_operand(rbx, src);
6489 }
6490
6491 void Assembler::blsmskq(Register dst, Register src) {
6492 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6493 int encode = vex_prefix_0F38_and_encode_q_legacy(rdx, dst, src);
6494 emit_int8((unsigned char)0xF3);
6495 emit_int8((unsigned char)(0xC0 | encode));
6496 }
6497
6498 void Assembler::blsmskq(Register dst, Address src) {
6499 InstructionMark im(this);
6500 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6501 vex_prefix_0F38_q_legacy(rdx, dst, src);
6502 emit_int8((unsigned char)0xF3);
6503 emit_operand(rdx, src);
6504 }
6505
6506 void Assembler::blsrq(Register dst, Register src) {
6507 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6508 int encode = vex_prefix_0F38_and_encode_q_legacy(rcx, dst, src);
6509 emit_int8((unsigned char)0xF3);
6510 emit_int8((unsigned char)(0xC0 | encode));
6511 }
6512
6513 void Assembler::blsrq(Register dst, Address src) {
6514 InstructionMark im(this);
6515 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6516 vex_prefix_0F38_q_legacy(rcx, dst, src);
6517 emit_int8((unsigned char)0xF3);
6518 emit_operand(rcx, src);
6519 }
6520
6521 void Assembler::cdqq() {
6522 prefix(REX_W);
6523 emit_int8((unsigned char)0x99);
6524 }
6525
6526 void Assembler::clflush(Address adr) {
6527 prefix(adr);
6528 emit_int8(0x0F);
6529 emit_int8((unsigned char)0xAE);
6530 emit_operand(rdi, adr);
6531 }
6532
6533 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6534 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6535 emit_int8(0x0F);
6536 emit_int8(0x40 | cc);
6537 emit_int8((unsigned char)(0xC0 | encode));
6538 }
6539
6540 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6541 InstructionMark im(this);
6542 prefixq(src, dst);
6543 emit_int8(0x0F);
6544 emit_int8(0x40 | cc);
6545 emit_operand(dst, src);
6546 }
6547
6548 void Assembler::cmpq(Address dst, int32_t imm32) {
6549 InstructionMark im(this);
6550 prefixq(dst);
6551 emit_int8((unsigned char)0x81);
6552 emit_operand(rdi, dst, 4);
6553 emit_int32(imm32);
6554 }
6555
6556 void Assembler::cmpq(Register dst, int32_t imm32) {
6557 (void) prefixq_and_encode(dst->encoding());
6558 emit_arith(0x81, 0xF8, dst, imm32);
6559 }
6560
6561 void Assembler::cmpq(Address dst, Register src) {
6562 InstructionMark im(this);
6563 prefixq(dst, src);
6564 emit_int8(0x3B);
6565 emit_operand(src, dst);
6566 }
6567
6568 void Assembler::cmpq(Register dst, Register src) {
6569 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6570 emit_arith(0x3B, 0xC0, dst, src);
6571 }
6572
6573 void Assembler::cmpq(Register dst, Address src) {
6574 InstructionMark im(this);
6575 prefixq(src, dst);
6576 emit_int8(0x3B);
6577 emit_operand(dst, src);
6578 }
6579
6580 void Assembler::cmpxchgq(Register reg, Address adr) {
6581 InstructionMark im(this);
6582 prefixq(adr, reg);
6583 emit_int8(0x0F);
6584 emit_int8((unsigned char)0xB1);
6585 emit_operand(reg, adr);
6586 }
6587
6588 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6590 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6591 emit_int8(0x2A);
6592 emit_int8((unsigned char)(0xC0 | encode));
6593 }
6594
6595 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6597 if (VM_Version::supports_evex()) {
6598 tuple_type = EVEX_T1S;
6599 input_size_in_bits = EVEX_32bit;
6600 }
6601 InstructionMark im(this);
6602 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6603 emit_int8(0x2A);
6604 emit_operand(dst, src);
6605 }
6606
6607 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
6608 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6609 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
6610 emit_int8(0x2A);
6611 emit_int8((unsigned char)(0xC0 | encode));
6612 }
6613
6614 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6615 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6616 if (VM_Version::supports_evex()) {
6617 tuple_type = EVEX_T1S;
6618 input_size_in_bits = EVEX_32bit;
6619 }
6620 InstructionMark im(this);
6621 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6622 emit_int8(0x2A);
6623 emit_operand(dst, src);
6624 }
6625
6626 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6628 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6629 emit_int8(0x2C);
6630 emit_int8((unsigned char)(0xC0 | encode));
6631 }
6632
6633 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
6634 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6635 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
6636 emit_int8(0x2C);
6637 emit_int8((unsigned char)(0xC0 | encode));
6638 }
6639
6640 void Assembler::decl(Register dst) {
6641 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6642 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
6643 int encode = prefix_and_encode(dst->encoding());
6644 emit_int8((unsigned char)0xFF);
6645 emit_int8((unsigned char)(0xC8 | encode));
6646 }
6647
6648 void Assembler::decq(Register dst) {
6649 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6650 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6651 int encode = prefixq_and_encode(dst->encoding());
6652 emit_int8((unsigned char)0xFF);
6653 emit_int8(0xC8 | encode);
6654 }
6655
6656 void Assembler::decq(Address dst) {
6657 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6658 InstructionMark im(this);
6659 prefixq(dst);
6660 emit_int8((unsigned char)0xFF);
6661 emit_operand(rcx, dst);
6662 }
6663
6664 void Assembler::fxrstor(Address src) {
6665 prefixq(src);
6666 emit_int8(0x0F);
6667 emit_int8((unsigned char)0xAE);
6668 emit_operand(as_Register(1), src);
6669 }
6670
6671 void Assembler::fxsave(Address dst) {
6672 prefixq(dst);
6673 emit_int8(0x0F);
6674 emit_int8((unsigned char)0xAE);
6675 emit_operand(as_Register(0), dst);
6676 }
6677
6678 void Assembler::idivq(Register src) {
6679 int encode = prefixq_and_encode(src->encoding());
6680 emit_int8((unsigned char)0xF7);
6681 emit_int8((unsigned char)(0xF8 | encode));
6682 }
6683
6684 void Assembler::imulq(Register dst, Register src) {
6685 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6686 emit_int8(0x0F);
6687 emit_int8((unsigned char)0xAF);
6688 emit_int8((unsigned char)(0xC0 | encode));
6689 }
6690
6691 void Assembler::imulq(Register dst, Register src, int value) {
6692 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6693 if (is8bit(value)) {
6694 emit_int8(0x6B);
6695 emit_int8((unsigned char)(0xC0 | encode));
6696 emit_int8(value & 0xFF);
6697 } else {
6698 emit_int8(0x69);
6699 emit_int8((unsigned char)(0xC0 | encode));
6700 emit_int32(value);
6701 }
6702 }
6703
6704 void Assembler::imulq(Register dst, Address src) {
6705 InstructionMark im(this);
6706 prefixq(src, dst);
6707 emit_int8(0x0F);
6708 emit_int8((unsigned char) 0xAF);
6709 emit_operand(dst, src);
6710 }
6711
6712 void Assembler::incl(Register dst) {
6713 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6714 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6715 int encode = prefix_and_encode(dst->encoding());
6716 emit_int8((unsigned char)0xFF);
6717 emit_int8((unsigned char)(0xC0 | encode));
6718 }
6719
6720 void Assembler::incq(Register dst) {
6721 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6722 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6723 int encode = prefixq_and_encode(dst->encoding());
6724 emit_int8((unsigned char)0xFF);
6725 emit_int8((unsigned char)(0xC0 | encode));
6726 }
6727
6728 void Assembler::incq(Address dst) {
6729 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6730 InstructionMark im(this);
6731 prefixq(dst);
6732 emit_int8((unsigned char)0xFF);
6733 emit_operand(rax, dst);
6734 }
6735
6736 void Assembler::lea(Register dst, Address src) {
6737 leaq(dst, src);
6738 }
6739
6740 void Assembler::leaq(Register dst, Address src) {
6741 InstructionMark im(this);
6742 prefixq(src, dst);
6743 emit_int8((unsigned char)0x8D);
6744 emit_operand(dst, src);
6745 }
6746
6747 void Assembler::mov64(Register dst, int64_t imm64) {
6748 InstructionMark im(this);
6749 int encode = prefixq_and_encode(dst->encoding());
6750 emit_int8((unsigned char)(0xB8 | encode));
6751 emit_int64(imm64);
6752 }
6753
6754 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
6755 InstructionMark im(this);
6756 int encode = prefixq_and_encode(dst->encoding());
6757 emit_int8(0xB8 | encode);
6758 emit_data64(imm64, rspec);
6759 }
6760
6761 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6762 InstructionMark im(this);
6763 int encode = prefix_and_encode(dst->encoding());
6764 emit_int8((unsigned char)(0xB8 | encode));
6765 emit_data((int)imm32, rspec, narrow_oop_operand);
6766 }
6767
6768 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6769 InstructionMark im(this);
6770 prefix(dst);
6771 emit_int8((unsigned char)0xC7);
6772 emit_operand(rax, dst, 4);
6773 emit_data((int)imm32, rspec, narrow_oop_operand);
6774 }
6775
6776 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6777 InstructionMark im(this);
6778 int encode = prefix_and_encode(src1->encoding());
6779 emit_int8((unsigned char)0x81);
6780 emit_int8((unsigned char)(0xF8 | encode));
6781 emit_data((int)imm32, rspec, narrow_oop_operand);
6782 }
6783
6784 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6785 InstructionMark im(this);
6786 prefix(src1);
6787 emit_int8((unsigned char)0x81);
6788 emit_operand(rax, src1, 4);
6789 emit_data((int)imm32, rspec, narrow_oop_operand);
6790 }
6791
6792 void Assembler::lzcntq(Register dst, Register src) {
6793 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
6794 emit_int8((unsigned char)0xF3);
6795 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6796 emit_int8(0x0F);
6797 emit_int8((unsigned char)0xBD);
6798 emit_int8((unsigned char)(0xC0 | encode));
6799 }
6800
6801 void Assembler::movdq(XMMRegister dst, Register src) {
6802 // table D-1 says MMX/SSE2
6803 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6804 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true);
6805 emit_int8(0x6E);
6806 emit_int8((unsigned char)(0xC0 | encode));
6807 }
6808
6809 void Assembler::movdq(Register dst, XMMRegister src) {
6810 // table D-1 says MMX/SSE2
6811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6812 // swap src/dst to get correct prefix
6813 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true);
6814 emit_int8(0x7E);
6815 emit_int8((unsigned char)(0xC0 | encode));
6816 }
6817
6818 void Assembler::movq(Register dst, Register src) {
6819 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6820 emit_int8((unsigned char)0x8B);
6821 emit_int8((unsigned char)(0xC0 | encode));
6822 }
6823
6824 void Assembler::movq(Register dst, Address src) {
6825 InstructionMark im(this);
6826 prefixq(src, dst);
6827 emit_int8((unsigned char)0x8B);
6828 emit_operand(dst, src);
6829 }
6830
6831 void Assembler::movq(Address dst, Register src) {
6832 InstructionMark im(this);
6833 prefixq(dst, src);
6834 emit_int8((unsigned char)0x89);
6835 emit_operand(src, dst);
6836 }
6837
6838 void Assembler::movsbq(Register dst, Address src) {
6839 InstructionMark im(this);
6840 prefixq(src, dst);
6841 emit_int8(0x0F);
6842 emit_int8((unsigned char)0xBE);
6843 emit_operand(dst, src);
6844 }
6845
6846 void Assembler::movsbq(Register dst, Register src) {
6847 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6848 emit_int8(0x0F);
6849 emit_int8((unsigned char)0xBE);
6850 emit_int8((unsigned char)(0xC0 | encode));
6851 }
6852
6853 void Assembler::movslq(Register dst, int32_t imm32) {
6854 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
6855 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
6856 // as a result we shouldn't use until tested at runtime...
6857 ShouldNotReachHere();
6858 InstructionMark im(this);
6859 int encode = prefixq_and_encode(dst->encoding());
6860 emit_int8((unsigned char)(0xC7 | encode));
6861 emit_int32(imm32);
6862 }
6863
6864 void Assembler::movslq(Address dst, int32_t imm32) {
6865 assert(is_simm32(imm32), "lost bits");
6866 InstructionMark im(this);
6867 prefixq(dst);
6868 emit_int8((unsigned char)0xC7);
6869 emit_operand(rax, dst, 4);
6870 emit_int32(imm32);
6871 }
6872
6873 void Assembler::movslq(Register dst, Address src) {
6874 InstructionMark im(this);
6875 prefixq(src, dst);
6876 emit_int8(0x63);
6877 emit_operand(dst, src);
6878 }
6879
6880 void Assembler::movslq(Register dst, Register src) {
6881 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6882 emit_int8(0x63);
6883 emit_int8((unsigned char)(0xC0 | encode));
6884 }
6885
6886 void Assembler::movswq(Register dst, Address src) {
6887 InstructionMark im(this);
6888 prefixq(src, dst);
6889 emit_int8(0x0F);
6890 emit_int8((unsigned char)0xBF);
6891 emit_operand(dst, src);
6892 }
6893
6894 void Assembler::movswq(Register dst, Register src) {
6895 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6896 emit_int8((unsigned char)0x0F);
6897 emit_int8((unsigned char)0xBF);
6898 emit_int8((unsigned char)(0xC0 | encode));
6899 }
6900
6901 void Assembler::movzbq(Register dst, Address src) {
6902 InstructionMark im(this);
6903 prefixq(src, dst);
6904 emit_int8((unsigned char)0x0F);
6905 emit_int8((unsigned char)0xB6);
6906 emit_operand(dst, src);
6907 }
6908
6909 void Assembler::movzbq(Register dst, Register src) {
6910 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6911 emit_int8(0x0F);
6912 emit_int8((unsigned char)0xB6);
6913 emit_int8(0xC0 | encode);
6914 }
6915
6916 void Assembler::movzwq(Register dst, Address src) {
6917 InstructionMark im(this);
6918 prefixq(src, dst);
6919 emit_int8((unsigned char)0x0F);
6920 emit_int8((unsigned char)0xB7);
6921 emit_operand(dst, src);
6922 }
6923
6924 void Assembler::movzwq(Register dst, Register src) {
6925 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6926 emit_int8((unsigned char)0x0F);
6927 emit_int8((unsigned char)0xB7);
6928 emit_int8((unsigned char)(0xC0 | encode));
6929 }
6930
6931 void Assembler::mulq(Address src) {
6932 InstructionMark im(this);
6933 prefixq(src);
6934 emit_int8((unsigned char)0xF7);
6935 emit_operand(rsp, src);
6936 }
6937
6938 void Assembler::mulq(Register src) {
6939 int encode = prefixq_and_encode(src->encoding());
6940 emit_int8((unsigned char)0xF7);
6941 emit_int8((unsigned char)(0xE0 | encode));
6942 }
6943
6944 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
6945 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6946 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(),
6947 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false);
6948 emit_int8((unsigned char)0xF6);
6949 emit_int8((unsigned char)(0xC0 | encode));
6950 }
6951
6952 void Assembler::negq(Register dst) {
6953 int encode = prefixq_and_encode(dst->encoding());
6954 emit_int8((unsigned char)0xF7);
6955 emit_int8((unsigned char)(0xD8 | encode));
6956 }
6957
6958 void Assembler::notq(Register dst) {
6959 int encode = prefixq_and_encode(dst->encoding());
6960 emit_int8((unsigned char)0xF7);
6961 emit_int8((unsigned char)(0xD0 | encode));
6962 }
6963
6964 void Assembler::orq(Address dst, int32_t imm32) {
6965 InstructionMark im(this);
6966 prefixq(dst);
6967 emit_int8((unsigned char)0x81);
6968 emit_operand(rcx, dst, 4);
6969 emit_int32(imm32);
6970 }
6971
6972 void Assembler::orq(Register dst, int32_t imm32) {
6973 (void) prefixq_and_encode(dst->encoding());
6974 emit_arith(0x81, 0xC8, dst, imm32);
6975 }
6976
6977 void Assembler::orq(Register dst, Address src) {
6978 InstructionMark im(this);
6979 prefixq(src, dst);
6980 emit_int8(0x0B);
6981 emit_operand(dst, src);
6982 }
6983
6984 void Assembler::orq(Register dst, Register src) {
6985 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6986 emit_arith(0x0B, 0xC0, dst, src);
6987 }
6988
6989 void Assembler::popa() { // 64bit
6990 movq(r15, Address(rsp, 0));
6991 movq(r14, Address(rsp, wordSize));
6992 movq(r13, Address(rsp, 2 * wordSize));
6993 movq(r12, Address(rsp, 3 * wordSize));
6994 movq(r11, Address(rsp, 4 * wordSize));
6995 movq(r10, Address(rsp, 5 * wordSize));
6996 movq(r9, Address(rsp, 6 * wordSize));
6997 movq(r8, Address(rsp, 7 * wordSize));
6998 movq(rdi, Address(rsp, 8 * wordSize));
6999 movq(rsi, Address(rsp, 9 * wordSize));
7000 movq(rbp, Address(rsp, 10 * wordSize));
7001 // skip rsp
7002 movq(rbx, Address(rsp, 12 * wordSize));
7003 movq(rdx, Address(rsp, 13 * wordSize));
7004 movq(rcx, Address(rsp, 14 * wordSize));
7005 movq(rax, Address(rsp, 15 * wordSize));
7006
7007 addq(rsp, 16 * wordSize);
7008 }
7009
7010 void Assembler::popcntq(Register dst, Address src) {
7011 assert(VM_Version::supports_popcnt(), "must support");
7012 InstructionMark im(this);
7013 emit_int8((unsigned char)0xF3);
7014 prefixq(src, dst);
7015 emit_int8((unsigned char)0x0F);
7016 emit_int8((unsigned char)0xB8);
7017 emit_operand(dst, src);
7018 }
7019
7020 void Assembler::popcntq(Register dst, Register src) {
7021 assert(VM_Version::supports_popcnt(), "must support");
7022 emit_int8((unsigned char)0xF3);
7023 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7024 emit_int8((unsigned char)0x0F);
7025 emit_int8((unsigned char)0xB8);
7026 emit_int8((unsigned char)(0xC0 | encode));
7027 }
7028
7029 void Assembler::popq(Address dst) {
7030 InstructionMark im(this);
7031 prefixq(dst);
7032 emit_int8((unsigned char)0x8F);
7033 emit_operand(rax, dst);
7034 }
7035
7036 void Assembler::pusha() { // 64bit
7037 // we have to store original rsp. ABI says that 128 bytes
7038 // below rsp are local scratch.
7039 movq(Address(rsp, -5 * wordSize), rsp);
7040
7041 subq(rsp, 16 * wordSize);
7042
7043 movq(Address(rsp, 15 * wordSize), rax);
7044 movq(Address(rsp, 14 * wordSize), rcx);
7045 movq(Address(rsp, 13 * wordSize), rdx);
7046 movq(Address(rsp, 12 * wordSize), rbx);
7047 // skip rsp
7048 movq(Address(rsp, 10 * wordSize), rbp);
7049 movq(Address(rsp, 9 * wordSize), rsi);
7050 movq(Address(rsp, 8 * wordSize), rdi);
7051 movq(Address(rsp, 7 * wordSize), r8);
7052 movq(Address(rsp, 6 * wordSize), r9);
7053 movq(Address(rsp, 5 * wordSize), r10);
7054 movq(Address(rsp, 4 * wordSize), r11);
7055 movq(Address(rsp, 3 * wordSize), r12);
7056 movq(Address(rsp, 2 * wordSize), r13);
7057 movq(Address(rsp, wordSize), r14);
7058 movq(Address(rsp, 0), r15);
7059 }
7060
7061 void Assembler::pushq(Address src) {
7062 InstructionMark im(this);
7063 prefixq(src);
7064 emit_int8((unsigned char)0xFF);
7065 emit_operand(rsi, src);
7066 }
7067
7068 void Assembler::rclq(Register dst, int imm8) {
7069 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7070 int encode = prefixq_and_encode(dst->encoding());
7071 if (imm8 == 1) {
7072 emit_int8((unsigned char)0xD1);
7073 emit_int8((unsigned char)(0xD0 | encode));
7074 } else {
7075 emit_int8((unsigned char)0xC1);
7076 emit_int8((unsigned char)(0xD0 | encode));
7077 emit_int8(imm8);
7078 }
7079 }
7080
7081 void Assembler::rcrq(Register dst, int imm8) {
7082 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7083 int encode = prefixq_and_encode(dst->encoding());
7084 if (imm8 == 1) {
7085 emit_int8((unsigned char)0xD1);
7086 emit_int8((unsigned char)(0xD8 | encode));
7087 } else {
7088 emit_int8((unsigned char)0xC1);
7089 emit_int8((unsigned char)(0xD8 | encode));
7090 emit_int8(imm8);
7091 }
7092 }
7093
7094 void Assembler::rorq(Register dst, int imm8) {
7095 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7096 int encode = prefixq_and_encode(dst->encoding());
7097 if (imm8 == 1) {
7098 emit_int8((unsigned char)0xD1);
7099 emit_int8((unsigned char)(0xC8 | encode));
7100 } else {
7101 emit_int8((unsigned char)0xC1);
7102 emit_int8((unsigned char)(0xc8 | encode));
7103 emit_int8(imm8);
7104 }
7105 }
7106
7107 void Assembler::rorxq(Register dst, Register src, int imm8) {
7108 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7109 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2,
7110 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false);
7111 emit_int8((unsigned char)0xF0);
7112 emit_int8((unsigned char)(0xC0 | encode));
7113 emit_int8(imm8);
7114 }
7115
7116 void Assembler::sarq(Register dst, int imm8) {
7117 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7118 int encode = prefixq_and_encode(dst->encoding());
7119 if (imm8 == 1) {
7120 emit_int8((unsigned char)0xD1);
7121 emit_int8((unsigned char)(0xF8 | encode));
7122 } else {
7123 emit_int8((unsigned char)0xC1);
7124 emit_int8((unsigned char)(0xF8 | encode));
7125 emit_int8(imm8);
7126 }
7127 }
7128
7129 void Assembler::sarq(Register dst) {
7130 int encode = prefixq_and_encode(dst->encoding());
7131 emit_int8((unsigned char)0xD3);
7132 emit_int8((unsigned char)(0xF8 | encode));
7133 }
7134
7135 void Assembler::sbbq(Address dst, int32_t imm32) {
7136 InstructionMark im(this);
7137 prefixq(dst);
7138 emit_arith_operand(0x81, rbx, dst, imm32);
7139 }
7140
7141 void Assembler::sbbq(Register dst, int32_t imm32) {
7142 (void) prefixq_and_encode(dst->encoding());
7143 emit_arith(0x81, 0xD8, dst, imm32);
7144 }
7145
7146 void Assembler::sbbq(Register dst, Address src) {
7147 InstructionMark im(this);
7148 prefixq(src, dst);
7149 emit_int8(0x1B);
7150 emit_operand(dst, src);
7151 }
7152
7153 void Assembler::sbbq(Register dst, Register src) {
7154 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7155 emit_arith(0x1B, 0xC0, dst, src);
7156 }
7157
7158 void Assembler::shlq(Register dst, int imm8) {
7159 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7160 int encode = prefixq_and_encode(dst->encoding());
7161 if (imm8 == 1) {
7162 emit_int8((unsigned char)0xD1);
7163 emit_int8((unsigned char)(0xE0 | encode));
7164 } else {
7165 emit_int8((unsigned char)0xC1);
7166 emit_int8((unsigned char)(0xE0 | encode));
7167 emit_int8(imm8);
7168 }
7169 }
7170
7171 void Assembler::shlq(Register dst) {
7172 int encode = prefixq_and_encode(dst->encoding());
7173 emit_int8((unsigned char)0xD3);
7174 emit_int8((unsigned char)(0xE0 | encode));
7175 }
7176
7177 void Assembler::shrq(Register dst, int imm8) {
7178 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7179 int encode = prefixq_and_encode(dst->encoding());
7180 emit_int8((unsigned char)0xC1);
7181 emit_int8((unsigned char)(0xE8 | encode));
7182 emit_int8(imm8);
7183 }
7184
7185 void Assembler::shrq(Register dst) {
7186 int encode = prefixq_and_encode(dst->encoding());
7187 emit_int8((unsigned char)0xD3);
7188 emit_int8(0xE8 | encode);
7189 }
7190
7191 void Assembler::subq(Address dst, int32_t imm32) {
7192 InstructionMark im(this);
7193 prefixq(dst);
7194 emit_arith_operand(0x81, rbp, dst, imm32);
7195 }
7196
7197 void Assembler::subq(Address dst, Register src) {
7198 InstructionMark im(this);
7199 prefixq(dst, src);
7200 emit_int8(0x29);
7201 emit_operand(src, dst);
7202 }
7203
7204 void Assembler::subq(Register dst, int32_t imm32) {
7205 (void) prefixq_and_encode(dst->encoding());
7206 emit_arith(0x81, 0xE8, dst, imm32);
7207 }
7208
7209 // Force generation of a 4 byte immediate value even if it fits into 8bit
7210 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7211 (void) prefixq_and_encode(dst->encoding());
7212 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7213 }
7214
7215 void Assembler::subq(Register dst, Address src) {
7216 InstructionMark im(this);
7217 prefixq(src, dst);
7218 emit_int8(0x2B);
7219 emit_operand(dst, src);
7220 }
7221
7222 void Assembler::subq(Register dst, Register src) {
7223 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7224 emit_arith(0x2B, 0xC0, dst, src);
7225 }
7226
7227 void Assembler::testq(Register dst, int32_t imm32) {
7228 // not using emit_arith because test
7229 // doesn't support sign-extension of
7230 // 8bit operands
7231 int encode = dst->encoding();
7232 if (encode == 0) {
7233 prefix(REX_W);
7234 emit_int8((unsigned char)0xA9);
7235 } else {
7236 encode = prefixq_and_encode(encode);
7237 emit_int8((unsigned char)0xF7);
7238 emit_int8((unsigned char)(0xC0 | encode));
7239 }
7240 emit_int32(imm32);
7241 }
7242
7243 void Assembler::testq(Register dst, Register src) {
7244 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7245 emit_arith(0x85, 0xC0, dst, src);
7246 }
7247
7248 void Assembler::xaddq(Address dst, Register src) {
7249 InstructionMark im(this);
7250 prefixq(dst, src);
7251 emit_int8(0x0F);
7252 emit_int8((unsigned char)0xC1);
7253 emit_operand(src, dst);
7254 }
7255
7256 void Assembler::xchgq(Register dst, Address src) {
7257 InstructionMark im(this);
7258 prefixq(src, dst);
7259 emit_int8((unsigned char)0x87);
7260 emit_operand(dst, src);
7261 }
7262
7263 void Assembler::xchgq(Register dst, Register src) {
7264 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7265 emit_int8((unsigned char)0x87);
7266 emit_int8((unsigned char)(0xc0 | encode));
7267 }
7268
7269 void Assembler::xorq(Register dst, Register src) {
7270 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7271 emit_arith(0x33, 0xC0, dst, src);
7272 }
7273
7274 void Assembler::xorq(Register dst, Address src) {
7275 InstructionMark im(this);
7276 prefixq(src, dst);
7277 emit_int8(0x33);
7278 emit_operand(dst, src);
7279 }
7280
7281 #endif // !LP64