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src/cpu/x86/vm/assembler_x86.cpp

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rev 8802 : G1 performance improvements: card batching, joining, sorting, prefetching and write barrier fence elision and simplification based on a global syncrhonization using handshakes piggybacking on thread-local safepoints.


3481 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3482   NOT_LP64(assert(VM_Version::supports_sse(), ""));
3483   emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3484 }
3485 
3486 void Assembler::subss(XMMRegister dst, Address src) {
3487   NOT_LP64(assert(VM_Version::supports_sse(), ""));
3488   if (VM_Version::supports_evex()) {
3489     tuple_type = EVEX_T1S;
3490     input_size_in_bits = EVEX_32bit;
3491   }
3492   emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3493 }
3494 
3495 void Assembler::testb(Register dst, int imm8) {
3496   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3497   (void) prefix_and_encode(dst->encoding(), true);
3498   emit_arith_b(0xF6, 0xC0, dst, imm8);
3499 }
3500 








3501 void Assembler::testl(Register dst, int32_t imm32) {
3502   // not using emit_arith because test
3503   // doesn't support sign-extension of
3504   // 8bit operands
3505   int encode = dst->encoding();
3506   if (encode == 0) {
3507     emit_int8((unsigned char)0xA9);
3508   } else {
3509     encode = prefix_and_encode(encode);
3510     emit_int8((unsigned char)0xF7);
3511     emit_int8((unsigned char)(0xC0 | encode));
3512   }
3513   emit_int32(imm32);
3514 }
3515 
3516 void Assembler::testl(Register dst, Register src) {
3517   (void) prefix_and_encode(dst->encoding(), src->encoding());
3518   emit_arith(0x85, 0xC0, dst, src);
3519 }
3520 




3481 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3482   NOT_LP64(assert(VM_Version::supports_sse(), ""));
3483   emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3484 }
3485 
3486 void Assembler::subss(XMMRegister dst, Address src) {
3487   NOT_LP64(assert(VM_Version::supports_sse(), ""));
3488   if (VM_Version::supports_evex()) {
3489     tuple_type = EVEX_T1S;
3490     input_size_in_bits = EVEX_32bit;
3491   }
3492   emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3493 }
3494 
3495 void Assembler::testb(Register dst, int imm8) {
3496   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3497   (void) prefix_and_encode(dst->encoding(), true);
3498   emit_arith_b(0xF6, 0xC0, dst, imm8);
3499 }
3500 
3501 void Assembler::testb(Address dst, int8_t imm8) {
3502   InstructionMark im(this);
3503   prefix(dst);
3504   emit_int8((unsigned char)0xF6);
3505   emit_operand(rax, dst, 1);
3506   emit_int8((unsigned char)imm8);
3507 }
3508 
3509 void Assembler::testl(Register dst, int32_t imm32) {
3510   // not using emit_arith because test
3511   // doesn't support sign-extension of
3512   // 8bit operands
3513   int encode = dst->encoding();
3514   if (encode == 0) {
3515     emit_int8((unsigned char)0xA9);
3516   } else {
3517     encode = prefix_and_encode(encode);
3518     emit_int8((unsigned char)0xF7);
3519     emit_int8((unsigned char)(0xC0 | encode));
3520   }
3521   emit_int32(imm32);
3522 }
3523 
3524 void Assembler::testl(Register dst, Register src) {
3525   (void) prefix_and_encode(dst->encoding(), src->encoding());
3526   emit_arith(0x85, 0xC0, dst, src);
3527 }
3528
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