2550 __ mov(obj, dst);
2551 } else if (code == lir_instanceof) {
2552 Register obj = op->object()->as_register();
2553 Register dst = op->result_opr()->as_register();
2554 Label success, failure, done;
2555 emit_typecheck_helper(op, &success, &failure, &failure);
2556 __ bind(failure);
2557 __ set(0, dst);
2558 __ ba_short(done);
2559 __ bind(success);
2560 __ set(1, dst);
2561 __ bind(done);
2562 } else {
2563 ShouldNotReachHere();
2564 }
2565
2566 }
2567
2568
2569 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2570 if (op->code() == lir_cas_long) {
2571 assert(VM_Version::supports_cx8(), "wrong machine");
2572 Register addr = op->addr()->as_pointer_register();
2573 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2574 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2575 Register new_value_lo = op->new_value()->as_register_lo();
2576 Register new_value_hi = op->new_value()->as_register_hi();
2577 Register t1 = op->tmp1()->as_register();
2578 Register t2 = op->tmp2()->as_register();
2579 __ mov(cmp_value_lo, t1);
2580 __ mov(new_value_lo, t2);
2581 // perform the compare and swap operation
2582 __ casx(addr, t1, t2);
2583 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2584 // overwritten with the original value in "addr" and will be equal to t1.
2585 __ cmp(t1, t2);
2586 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2587 Register addr = op->addr()->as_pointer_register();
2588 Register cmp_value = op->cmp_value()->as_register();
2589 Register new_value = op->new_value()->as_register();
2590 Register t1 = op->tmp1()->as_register();
2591 Register t2 = op->tmp2()->as_register();
2592 __ mov(cmp_value, t1);
2593 __ mov(new_value, t2);
2594 if (op->code() == lir_cas_obj) {
2595 if (UseCompressedOops) {
2596 __ encode_heap_oop(t1);
2597 __ encode_heap_oop(t2);
2598 __ cas(addr, t1, t2);
2599 } else {
2600 __ cas_ptr(addr, t1, t2);
2601 }
2602 } else {
2603 __ cas(addr, t1, t2);
2604 }
2605 __ cmp(t1, t2);
2606 } else {
2607 Unimplemented();
3147 // Note: src is destroyed
3148 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3149 Register rs = src->as_register();
3150 Register rd = dst->as_register_lo();
3151 __ sllx(rs, 32, rs);
3152 __ srl(rs->successor(), 0, rs->successor());
3153 __ or3(rs, rs->successor(), rd);
3154 }
3155
3156 // Unpack a 64 bit value in a register into
3157 // two sequential registers.
3158 // src is unpacked into dst and dst->successor()
3159 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3160 Register rs = src->as_register_lo();
3161 Register rd = dst->as_register_hi();
3162 assert_different_registers(rs, rd, rd->successor());
3163 __ srlx(rs, 32, rd);
3164 __ srl (rs, 0, rd->successor());
3165 }
3166
3167
3168 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3169 LIR_Address* addr = addr_opr->as_address_ptr();
3170 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3171
3172 if (Assembler::is_simm13(addr->disp())) {
3173 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3174 } else {
3175 __ set(addr->disp(), G3_scratch);
3176 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3177 }
3178 }
3179
3180
3181 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3182 assert(result_reg->is_register(), "check");
3183 __ mov(G2_thread, result_reg->as_register());
3184 }
3185
3186 #ifdef ASSERT
3187 // emit run-time assertion
3188 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3189 assert(op->code() == lir_assert, "must be");
3190
3191 if (op->in_opr1()->is_valid()) {
3192 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3193 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3194 } else {
3195 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3196 assert(op->condition() == lir_cond_always, "no other conditions allowed");
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2550 __ mov(obj, dst);
2551 } else if (code == lir_instanceof) {
2552 Register obj = op->object()->as_register();
2553 Register dst = op->result_opr()->as_register();
2554 Label success, failure, done;
2555 emit_typecheck_helper(op, &success, &failure, &failure);
2556 __ bind(failure);
2557 __ set(0, dst);
2558 __ ba_short(done);
2559 __ bind(success);
2560 __ set(1, dst);
2561 __ bind(done);
2562 } else {
2563 ShouldNotReachHere();
2564 }
2565
2566 }
2567
2568
2569 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2570 LIR_Address* address = op->addr()->as_address_ptr();
2571 if (op->code() == lir_cas_long) {
2572 assert(VM_Version::supports_cx8(), "wrong machine");
2573 Register addr = address->base()->as_pointer_register();
2574 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2575 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2576 Register new_value_lo = op->new_value()->as_register_lo();
2577 Register new_value_hi = op->new_value()->as_register_hi();
2578 Register t1 = op->tmp1()->as_register();
2579 Register t2 = op->tmp2()->as_register();
2580 __ mov(cmp_value_lo, t1);
2581 __ mov(new_value_lo, t2);
2582 // perform the compare and swap operation
2583 __ casx(addr, t1, t2);
2584 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2585 // overwritten with the original value in "addr" and will be equal to t1.
2586 __ cmp(t1, t2);
2587 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2588 Register addr = address->base()->as_pointer_register();
2589 Register cmp_value = op->cmp_value()->as_register();
2590 Register new_value = op->new_value()->as_register();
2591 Register t1 = op->tmp1()->as_register();
2592 Register t2 = op->tmp2()->as_register();
2593 __ mov(cmp_value, t1);
2594 __ mov(new_value, t2);
2595 if (op->code() == lir_cas_obj) {
2596 if (UseCompressedOops) {
2597 __ encode_heap_oop(t1);
2598 __ encode_heap_oop(t2);
2599 __ cas(addr, t1, t2);
2600 } else {
2601 __ cas_ptr(addr, t1, t2);
2602 }
2603 } else {
2604 __ cas(addr, t1, t2);
2605 }
2606 __ cmp(t1, t2);
2607 } else {
2608 Unimplemented();
3148 // Note: src is destroyed
3149 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3150 Register rs = src->as_register();
3151 Register rd = dst->as_register_lo();
3152 __ sllx(rs, 32, rs);
3153 __ srl(rs->successor(), 0, rs->successor());
3154 __ or3(rs, rs->successor(), rd);
3155 }
3156
3157 // Unpack a 64 bit value in a register into
3158 // two sequential registers.
3159 // src is unpacked into dst and dst->successor()
3160 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3161 Register rs = src->as_register_lo();
3162 Register rd = dst->as_register_hi();
3163 assert_different_registers(rs, rd, rd->successor());
3164 __ srlx(rs, 32, rd);
3165 __ srl (rs, 0, rd->successor());
3166 }
3167
3168 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3169 const LIR_Address* addr = addr_opr->as_address_ptr();
3170 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3171 const Register dest_reg = dest->as_pointer_register();
3172 const Register base_reg = addr->base()->as_pointer_register();
3173
3174 if (Assembler::is_simm13(addr->disp())) {
3175 if (addr->index()->is_valid()) {
3176 const Register index_reg = addr->index()->as_pointer_register();
3177 assert(index_reg != G3_scratch, "invariant");
3178 __ add(base_reg, addr->disp(), G3_scratch);
3179 __ add(index_reg, G3_scratch, dest_reg);
3180
3181 } else {
3182 __ add(base_reg, addr->disp(), dest_reg);
3183 }
3184 } else {
3185 __ set(addr->disp(), G3_scratch);
3186 if (addr->index()->is_valid()) {
3187 const Register index_reg = addr->index()->as_pointer_register();
3188 assert(index_reg != G3_scratch, "invariant");
3189 __ add(index_reg, G3_scratch, G3_scratch);
3190
3191 }
3192 __ add(base_reg, G3_scratch, dest_reg);
3193 }
3194 }
3195
3196
3197 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3198 assert(result_reg->is_register(), "check");
3199 __ mov(G2_thread, result_reg->as_register());
3200 }
3201
3202 #ifdef ASSERT
3203 // emit run-time assertion
3204 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3205 assert(op->code() == lir_assert, "must be");
3206
3207 if (op->in_opr1()->is_valid()) {
3208 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3209 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3210 } else {
3211 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3212 assert(op->condition() == lir_cond_always, "no other conditions allowed");
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