1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30
31 // <sys/trap.h> promises that the system will not use traps 16-31
32 #define ST_RESERVED_FOR_USER_0 0x10
33
34 class BiasedLockingCounters;
35
36
37 // Register aliases for parts of the system:
38
39 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
40 // across context switches in V8+ ABI. Of course, there are no 64 bit regs
41 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
42
43 // g2-g4 are scratch registers called "application globals". Their
44 // meaning is reserved to the "compilation system"--which means us!
45 // They are are not supposed to be touched by ordinary C code, although
46 // highly-optimized C code might steal them for temps. They are safe
47 // across thread switches, and the ABI requires that they be safe
48 // across function calls.
49 //
50 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
51 // across func calls, and V8+ also allows g5 to be clobbered across
52 // func calls. Also, g1 and g5 can get touched while doing shared
53 // library loading.
54 //
55 // We must not touch g7 (it is the thread-self register) and g6 is
56 // reserved for certain tools. g0, of course, is always zero.
57 //
58 // (Sources: SunSoft Compilers Group, thread library engineers.)
59
60 // %%%% The interpreter should be revisited to reduce global scratch regs.
61
62 // This global always holds the current JavaThread pointer:
63
64 REGISTER_DECLARATION(Register, G2_thread , G2);
65 REGISTER_DECLARATION(Register, G6_heapbase , G6);
66
67 // The following globals are part of the Java calling convention:
68
69 REGISTER_DECLARATION(Register, G5_method , G5);
70 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
71 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
72
73 // The following globals are used for the new C1 & interpreter calling convention:
74 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
75
76 // This local is used to preserve G2_thread in the interpreter and in stubs:
77 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
78
79 // These globals are used as scratch registers in the interpreter:
80
81 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
82 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
83 REGISTER_DECLARATION(Register, G3_scratch , G3);
84 REGISTER_DECLARATION(Register, G4_scratch , G4);
85
86 // These globals are used as short-lived scratch registers in the compiler:
87
88 REGISTER_DECLARATION(Register, Gtemp , G5);
89
90 // JSR 292 fixed register usages:
91 REGISTER_DECLARATION(Register, G5_method_type , G5);
92 REGISTER_DECLARATION(Register, G3_method_handle , G3);
93 REGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
94
95 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
96 // because a single patchable "set" instruction (NativeMovConstReg,
97 // or NativeMovConstPatching for compiler1) instruction
98 // serves to set up either quantity, depending on whether the compiled
99 // call site is an inline cache or is megamorphic. See the function
100 // CompiledIC::set_to_megamorphic.
101 //
102 // If a inline cache targets an interpreted method, then the
103 // G5 register will be used twice during the call. First,
104 // the call site will be patched to load a compiledICHolder
105 // into G5. (This is an ordered pair of ic_klass, method.)
106 // The c2i adapter will first check the ic_klass, then load
107 // G5_method with the method part of the pair just before
108 // jumping into the interpreter.
109 //
110 // Note that G5_method is only the method-self for the interpreter,
111 // and is logically unrelated to G5_megamorphic_method.
112 //
113 // Invariants on G2_thread (the JavaThread pointer):
114 // - it should not be used for any other purpose anywhere
115 // - it must be re-initialized by StubRoutines::call_stub()
116 // - it must be preserved around every use of call_VM
117
118 // We can consider using g2/g3/g4 to cache more values than the
119 // JavaThread, such as the card-marking base or perhaps pointers into
120 // Eden. It's something of a waste to use them as scratch temporaries,
121 // since they are not supposed to be volatile. (Of course, if we find
122 // that Java doesn't benefit from application globals, then we can just
123 // use them as ordinary temporaries.)
124 //
125 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
126 // it makes sense to use them routinely for procedure linkage,
127 // whenever the On registers are not applicable. Examples: G5_method,
128 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
129 // stubs. This means that compiler stubs, etc., should be kept to a
130 // maximum of two or three G-register arguments.
131
132
133 // stub frames
134
135 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
136
137 // Interpreter frames
138
139 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
140 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
141 REGISTER_DECLARATION(Register, Lmethod , L2);
142 REGISTER_DECLARATION(Register, Llocals , L3);
143 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
144 // must match Llocals in asm interpreter
145 REGISTER_DECLARATION(Register, Lmonitors , L4);
146 REGISTER_DECLARATION(Register, Lbyte_code , L5);
147 // When calling out from the interpreter we record SP so that we can remove any extra stack
148 // space allocated during adapter transitions. This register is only live from the point
149 // of the call until we return.
150 REGISTER_DECLARATION(Register, Llast_SP , L5);
151 REGISTER_DECLARATION(Register, Lscratch , L5);
152 REGISTER_DECLARATION(Register, Lscratch2 , L6);
153 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
154
155 REGISTER_DECLARATION(Register, O5_savedSP , O5);
156 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
157 // a copy SP, so in 64-bit it's a biased value. The bias
158 // is added and removed as needed in the frame code.
159 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
160 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
161 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
162
163 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
164 // the interpreter code. If Lscratch2 needs to be used for some
165 // purpose than LcpoolCache should be restore after that for
166 // the interpreter to work right
167 // (These assignments must be compatible with L7_thread_cache; see above.)
168
169 // Lbcp points into the middle of the method object.
170
171 // Exception processing
172 // These registers are passed into exception handlers.
173 // All exception handlers require the exception object being thrown.
174 // In addition, an nmethod's exception handler must be passed
175 // the address of the call site within the nmethod, to allow
176 // proper selection of the applicable catch block.
177 // (Interpreter frames use their own bcp() for this purpose.)
178 //
179 // The Oissuing_pc value is not always needed. When jumping to a
180 // handler that is known to be interpreted, the Oissuing_pc value can be
181 // omitted. An actual catch block in compiled code receives (from its
182 // nmethod's exception handler) the thrown exception in the Oexception,
183 // but it doesn't need the Oissuing_pc.
184 //
185 // If an exception handler (either interpreted or compiled)
186 // discovers there is no applicable catch block, it updates
187 // the Oissuing_pc to the continuation PC of its own caller,
188 // pops back to that caller's stack frame, and executes that
189 // caller's exception handler. Obviously, this process will
190 // iterate until the control stack is popped back to a method
191 // containing an applicable catch block. A key invariant is
192 // that the Oissuing_pc value is always a value local to
193 // the method whose exception handler is currently executing.
194 //
195 // Note: The issuing PC value is __not__ a raw return address (I7 value).
196 // It is a "return pc", the address __following__ the call.
197 // Raw return addresses are converted to issuing PCs by frame::pc(),
198 // or by stubs. Issuing PCs can be used directly with PC range tables.
199 //
200 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
201 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
202
203
204 // These must occur after the declarations above
205 #ifndef DONT_USE_REGISTER_DEFINES
206
207 #define Gthread AS_REGISTER(Register, Gthread)
208 #define Gmethod AS_REGISTER(Register, Gmethod)
209 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
210 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
211 #define Gargs AS_REGISTER(Register, Gargs)
212 #define Lthread_cache AS_REGISTER(Register, Lthread_cache)
213 #define Gframe_size AS_REGISTER(Register, Gframe_size)
214 #define Gtemp AS_REGISTER(Register, Gtemp)
215
216 #define Lesp AS_REGISTER(Register, Lesp)
217 #define Lbcp AS_REGISTER(Register, Lbcp)
218 #define Lmethod AS_REGISTER(Register, Lmethod)
219 #define Llocals AS_REGISTER(Register, Llocals)
220 #define Lmonitors AS_REGISTER(Register, Lmonitors)
221 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
222 #define Lscratch AS_REGISTER(Register, Lscratch)
223 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
224 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
225
226 #define Lentry_args AS_REGISTER(Register, Lentry_args)
227 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
228 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
229 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
230 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
231 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
232
233 #define Oexception AS_REGISTER(Register, Oexception)
234 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
235
236 #endif
237
238
239 // Address is an abstraction used to represent a memory location.
240 //
241 // Note: A register location is represented via a Register, not
242 // via an address for efficiency & simplicity reasons.
243
244 class Address VALUE_OBJ_CLASS_SPEC {
245 private:
246 Register _base; // Base register.
247 RegisterOrConstant _index_or_disp; // Index register or constant displacement.
248 RelocationHolder _rspec;
249
250 public:
251 Address() : _base(noreg), _index_or_disp(noreg) {}
252
253 Address(Register base, RegisterOrConstant index_or_disp)
254 : _base(base),
255 _index_or_disp(index_or_disp) {
256 }
257
258 Address(Register base, Register index)
259 : _base(base),
260 _index_or_disp(index) {
261 }
262
263 Address(Register base, int disp)
264 : _base(base),
265 _index_or_disp(disp) {
266 }
267
268 #ifdef ASSERT
269 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
270 Address(Register base, ByteSize disp)
271 : _base(base),
272 _index_or_disp(in_bytes(disp)) {
273 }
274 #endif
275
276 // accessors
277 Register base() const { return _base; }
278 Register index() const { return _index_or_disp.as_register(); }
279 int disp() const { return _index_or_disp.as_constant(); }
280
281 bool has_index() const { return _index_or_disp.is_register(); }
282 bool has_disp() const { return _index_or_disp.is_constant(); }
283
284 bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
285
286 const relocInfo::relocType rtype() { return _rspec.type(); }
287 const RelocationHolder& rspec() { return _rspec; }
288
289 RelocationHolder rspec(int offset) const {
290 return offset == 0 ? _rspec : _rspec.plus(offset);
291 }
292
293 inline bool is_simm13(int offset = 0); // check disp+offset for overflow
294
295 Address plus_disp(int plusdisp) const { // bump disp by a small amount
296 assert(_index_or_disp.is_constant(), "must have a displacement");
297 Address a(base(), disp() + plusdisp);
298 return a;
299 }
300 bool is_same_address(Address a) const {
301 // disregard _rspec
302 return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
303 }
304
305 Address after_save() const {
306 Address a = (*this);
307 a._base = a._base->after_save();
308 return a;
309 }
310
311 Address after_restore() const {
312 Address a = (*this);
313 a._base = a._base->after_restore();
314 return a;
315 }
316
317 // Convert the raw encoding form into the form expected by the
318 // constructor for Address.
319 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
320
321 friend class Assembler;
322 };
323
324
325 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
326 private:
327 address _address;
328 RelocationHolder _rspec;
329
330 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
331 switch (rtype) {
332 case relocInfo::external_word_type:
333 return external_word_Relocation::spec(addr);
334 case relocInfo::internal_word_type:
335 return internal_word_Relocation::spec(addr);
336 case relocInfo::opt_virtual_call_type:
337 return opt_virtual_call_Relocation::spec();
338 case relocInfo::static_call_type:
339 return static_call_Relocation::spec();
340 case relocInfo::runtime_call_type:
341 return runtime_call_Relocation::spec();
342 case relocInfo::none:
343 return RelocationHolder();
344 default:
345 ShouldNotReachHere();
346 return RelocationHolder();
347 }
348 }
349
350 protected:
351 // creation
352 AddressLiteral() : _address(NULL), _rspec(NULL) {}
353
354 public:
355 AddressLiteral(address addr, RelocationHolder const& rspec)
356 : _address(addr),
357 _rspec(rspec) {}
358
359 // Some constructors to avoid casting at the call site.
360 AddressLiteral(jobject obj, RelocationHolder const& rspec)
361 : _address((address) obj),
362 _rspec(rspec) {}
363
364 AddressLiteral(intptr_t value, RelocationHolder const& rspec)
365 : _address((address) value),
366 _rspec(rspec) {}
367
368 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
369 : _address((address) addr),
370 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
371
372 // Some constructors to avoid casting at the call site.
373 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
374 : _address((address) addr),
375 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
376
377 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
378 : _address((address) addr),
379 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
380
381 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
382 : _address((address) addr),
383 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
384
385 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
386 : _address((address) addr),
387 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
388
389 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
390 : _address((address) addr),
391 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
392
393 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
394 : _address((address) addr),
395 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
396
397 // 32-bit complains about a multiple declaration for int*.
398 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
399 : _address((address) addr),
400 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
401
402 AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none)
403 : _address((address) addr),
404 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
405
406 AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none)
407 : _address((address) addr),
408 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
409
410 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
411 : _address((address) addr),
412 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
413
414 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
415 : _address((address) addr),
416 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
417
418 intptr_t value() const { return (intptr_t) _address; }
419 int low10() const;
420
421 const relocInfo::relocType rtype() const { return _rspec.type(); }
422 const RelocationHolder& rspec() const { return _rspec; }
423
424 RelocationHolder rspec(int offset) const {
425 return offset == 0 ? _rspec : _rspec.plus(offset);
426 }
427 };
428
429 // Convenience classes
430 class ExternalAddress: public AddressLiteral {
431 private:
432 static relocInfo::relocType reloc_for_target(address target) {
433 // Sometimes ExternalAddress is used for values which aren't
434 // exactly addresses, like the card table base.
435 // external_word_type can't be used for values in the first page
436 // so just skip the reloc in that case.
437 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
438 }
439
440 public:
441 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {}
442 ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {}
443 };
444
445 inline Address RegisterImpl::address_in_saved_window() const {
446 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
447 }
448
449
450
451 // Argument is an abstraction used to represent an outgoing
452 // actual argument or an incoming formal parameter, whether
453 // it resides in memory or in a register, in a manner consistent
454 // with the SPARC Application Binary Interface, or ABI. This is
455 // often referred to as the native or C calling convention.
456
457 class Argument VALUE_OBJ_CLASS_SPEC {
458 private:
459 int _number;
460 bool _is_in;
461
462 public:
463 enum {
464 n_register_parameters = 6, // only 6 registers may contain integer parameters
465 n_float_register_parameters = 16 // Can have up to 16 floating registers
466 };
467
468 // creation
469 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
470
471 int number() const { return _number; }
472 bool is_in() const { return _is_in; }
473 bool is_out() const { return !is_in(); }
474
475 Argument successor() const { return Argument(number() + 1, is_in()); }
476 Argument as_in() const { return Argument(number(), true ); }
477 Argument as_out() const { return Argument(number(), false); }
478
479 // locating register-based arguments:
480 bool is_register() const { return _number < n_register_parameters; }
481
482 // locating Floating Point register-based arguments:
483 bool is_float_register() const { return _number < n_float_register_parameters; }
484
485 FloatRegister as_float_register() const {
486 assert(is_float_register(), "must be a register argument");
487 return as_FloatRegister(( number() *2 ) + 1);
488 }
489 FloatRegister as_double_register() const {
490 assert(is_float_register(), "must be a register argument");
491 return as_FloatRegister(( number() *2 ));
492 }
493
494 Register as_register() const {
495 assert(is_register(), "must be a register argument");
496 return is_in() ? as_iRegister(number()) : as_oRegister(number());
497 }
498
499 // locating memory-based arguments
500 Address as_address() const {
501 assert(!is_register(), "must be a memory argument");
502 return address_in_frame();
503 }
504
505 // When applied to a register-based argument, give the corresponding address
506 // into the 6-word area "into which callee may store register arguments"
507 // (This is a different place than the corresponding register-save area location.)
508 Address address_in_frame() const;
509
510 // debugging
511 const char* name() const;
512
513 friend class Assembler;
514 };
515
516
517 class RegistersForDebugging : public StackObj {
518 public:
519 intptr_t i[8], l[8], o[8], g[8];
520 float f[32];
521 double d[32];
522
523 void print(outputStream* s);
524
525 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
526 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
527 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
528 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
529 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
530 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
531
532 // gen asm code to save regs
533 static void save_registers(MacroAssembler* a);
534
535 // restore global registers in case C code disturbed them
536 static void restore_registers(MacroAssembler* a, Register r);
537 };
538
539
540 // MacroAssembler extends Assembler by a few frequently used macros.
541 //
542 // Most of the standard SPARC synthetic ops are defined here.
543 // Instructions for which a 'better' code sequence exists depending
544 // on arguments should also go in here.
545
546 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
547 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
548 #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__)
549 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
550
551
552 class MacroAssembler : public Assembler {
553 // code patchers need various routines like inv_wdisp()
554 friend class NativeInstruction;
555 friend class NativeGeneralJump;
556 friend class Relocation;
557 friend class Label;
558
559 protected:
560 static int patched_branch(int dest_pos, int inst, int inst_pos);
561 static int branch_destination(int inst, int pos);
562
563 // Support for VM calls
564 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
565 // may customize this version by overriding it for its purposes (e.g., to save/restore
566 // additional registers when doing a VM call).
567 virtual void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
568
569 //
570 // It is imperative that all calls into the VM are handled via the call_VM macros.
571 // They make sure that the stack linkage is setup correctly. call_VM's correspond
572 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
573 //
574 // This is the base routine called by the different versions of call_VM. The interpreter
575 // may customize this version by overriding it for its purposes (e.g., to save/restore
576 // additional registers when doing a VM call).
577 //
578 // A non-volatile java_thread_cache register should be specified so
579 // that the G2_thread value can be preserved across the call.
580 // (If java_thread_cache is noreg, then a slow get_thread call
581 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
582 // thread.
583 //
584 // If no last_java_sp is specified (noreg) than SP will be used instead.
585
586 virtual void call_VM_base(
587 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
588 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
589 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
590 address entry_point, // the entry point
591 int number_of_arguments, // the number of arguments (w/o thread) to pop after call
592 bool check_exception=true // flag which indicates if exception should be checked
593 );
594
595 public:
596 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
597
598 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
599 // The implementation is only non-empty for the InterpreterMacroAssembler,
600 // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
601 virtual void check_and_handle_popframe(Register scratch_reg);
602 virtual void check_and_handle_earlyret(Register scratch_reg);
603
604 // Support for NULL-checks
605 //
606 // Generates code that causes a NULL OS exception if the content of reg is NULL.
607 // If the accessed location is M[reg + offset] and the offset is known, provide the
608 // offset. No explicit code generation is needed if the offset is within a certain
609 // range (0 <= offset <= page_size).
610 //
611 // %%%%%% Currently not done for SPARC
612
613 void null_check(Register reg, int offset = -1);
614 static bool needs_explicit_null_check(intptr_t offset);
615
616 // support for delayed instructions
617 MacroAssembler* delayed() { Assembler::delayed(); return this; }
618
619 // branches that use right instruction for v8 vs. v9
620 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
621 inline void br( Condition c, bool a, Predict p, Label& L );
622
623 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
624 inline void fb( Condition c, bool a, Predict p, Label& L );
625
626 // compares register with zero (32 bit) and branches (V9 and V8 instructions)
627 void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
628 // Compares a pointer register with zero and branches on (not)null.
629 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
630 void br_null ( Register s1, bool a, Predict p, Label& L );
631 void br_notnull( Register s1, bool a, Predict p, Label& L );
632
633 //
634 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
635 //
636 // ATTENTION: use these instructions with caution because cbcond instruction
637 // has very short distance: 512 instructions (2Kbyte).
638
639 // Compare integer (32 bit) values (icc only).
640 void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
641 void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
642 // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
643 void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
644 void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
645
646 // Short branch version for compares a pointer pwith zero.
647 void br_null_short ( Register s1, Predict p, Label& L );
648 void br_notnull_short( Register s1, Predict p, Label& L );
649
650 // unconditional short branch
651 void ba_short(Label& L);
652
653 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
654 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
655
656 // Branch that tests xcc in LP64 and icc in !LP64
657 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
658 inline void brx( Condition c, bool a, Predict p, Label& L );
659
660 // unconditional branch
661 inline void ba( Label& L );
662
663 // Branch that tests fp condition codes
664 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
665 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
666
667 // get PC the best way
668 inline int get_pc( Register d );
669
670 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
671 inline void cmp( Register s1, Register s2 );
672 inline void cmp( Register s1, int simm13a );
673
674 inline void jmp( Register s1, Register s2 );
675 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
676
677 // Check if the call target is out of wdisp30 range (relative to the code cache)
678 static inline bool is_far_target(address d);
679 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
680 inline void call( address d, RelocationHolder const& rspec);
681
682 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
683 inline void call( Label& L, RelocationHolder const& rspec);
684
685 inline void callr( Register s1, Register s2 );
686 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
687
688 // Emits nothing on V8
689 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
690 inline void iprefetch( Label& L);
691
692 inline void tst( Register s );
693
694 inline void ret( bool trace = false );
695 inline void retl( bool trace = false );
696
697 // Required platform-specific helpers for Label::patch_instructions.
698 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
699 void pd_patch_instruction(address branch, address target);
700
701 // sethi Macro handles optimizations and relocations
702 private:
703 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
704 public:
705 void sethi(const AddressLiteral& addrlit, Register d);
706 void patchable_sethi(const AddressLiteral& addrlit, Register d);
707
708 // compute the number of instructions for a sethi/set
709 static int insts_for_sethi( address a, bool worst_case = false );
710 static int worst_case_insts_for_set();
711
712 // set may be either setsw or setuw (high 32 bits may be zero or sign)
713 private:
714 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
715 static int insts_for_internal_set(intptr_t value);
716 public:
717 void set(const AddressLiteral& addrlit, Register d);
718 void set(intptr_t value, Register d);
719 void set(address addr, Register d, RelocationHolder const& rspec);
720 static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
721
722 void patchable_set(const AddressLiteral& addrlit, Register d);
723 void patchable_set(intptr_t value, Register d);
724 void set64(jlong value, Register d, Register tmp);
725 static int insts_for_set64(jlong value);
726
727 // sign-extend 32 to 64
728 inline void signx( Register s, Register d );
729 inline void signx( Register d );
730
731 inline void not1( Register s, Register d );
732 inline void not1( Register d );
733
734 inline void neg( Register s, Register d );
735 inline void neg( Register d );
736
737 inline void cas( Register s1, Register s2, Register d);
738 inline void casx( Register s1, Register s2, Register d);
739 // Functions for isolating 64 bit atomic swaps for LP64
740 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
741 inline void cas_ptr( Register s1, Register s2, Register d);
742
743 // Resolve a jobject or jweak
744 void resolve_jobject(Register value, Register tmp);
745
746 // Functions for isolating 64 bit shifts for LP64
747 inline void sll_ptr( Register s1, Register s2, Register d );
748 inline void sll_ptr( Register s1, int imm6a, Register d );
749 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
750 inline void srl_ptr( Register s1, Register s2, Register d );
751 inline void srl_ptr( Register s1, int imm6a, Register d );
752
753 // little-endian
754 inline void casl( Register s1, Register s2, Register d);
755 inline void casxl( Register s1, Register s2, Register d);
756
757 inline void inc( Register d, int const13 = 1 );
758 inline void inccc( Register d, int const13 = 1 );
759
760 inline void dec( Register d, int const13 = 1 );
761 inline void deccc( Register d, int const13 = 1 );
762
763 using Assembler::add;
764 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype);
765 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
766 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
767 inline void add(const Address& a, Register d, int offset = 0);
768
769 using Assembler::andn;
770 inline void andn( Register s1, RegisterOrConstant s2, Register d);
771
772 inline void btst( Register s1, Register s2 );
773 inline void btst( int simm13a, Register s );
774
775 inline void bset( Register s1, Register s2 );
776 inline void bset( int simm13a, Register s );
777
778 inline void bclr( Register s1, Register s2 );
779 inline void bclr( int simm13a, Register s );
780
781 inline void btog( Register s1, Register s2 );
782 inline void btog( int simm13a, Register s );
783
784 inline void clr( Register d );
785
786 inline void clrb( Register s1, Register s2);
787 inline void clrh( Register s1, Register s2);
788 inline void clr( Register s1, Register s2);
789 inline void clrx( Register s1, Register s2);
790
791 inline void clrb( Register s1, int simm13a);
792 inline void clrh( Register s1, int simm13a);
793 inline void clr( Register s1, int simm13a);
794 inline void clrx( Register s1, int simm13a);
795
796 // copy & clear upper word
797 inline void clruw( Register s, Register d );
798 // clear upper word
799 inline void clruwu( Register d );
800
801 using Assembler::ldsb;
802 using Assembler::ldsh;
803 using Assembler::ldsw;
804 using Assembler::ldub;
805 using Assembler::lduh;
806 using Assembler::lduw;
807 using Assembler::ldx;
808 using Assembler::ldd;
809
810 #ifdef ASSERT
811 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
812 inline void ld(Register s1, ByteSize simm13a, Register d);
813 #endif
814
815 inline void ld(Register s1, Register s2, Register d);
816 inline void ld(Register s1, int simm13a, Register d);
817
818 inline void ldsb(const Address& a, Register d, int offset = 0);
819 inline void ldsh(const Address& a, Register d, int offset = 0);
820 inline void ldsw(const Address& a, Register d, int offset = 0);
821 inline void ldub(const Address& a, Register d, int offset = 0);
822 inline void lduh(const Address& a, Register d, int offset = 0);
823 inline void lduw(const Address& a, Register d, int offset = 0);
824 inline void ldx( const Address& a, Register d, int offset = 0);
825 inline void ld( const Address& a, Register d, int offset = 0);
826 inline void ldd( const Address& a, Register d, int offset = 0);
827
828 inline void ldub(Register s1, RegisterOrConstant s2, Register d );
829 inline void ldsb(Register s1, RegisterOrConstant s2, Register d );
830 inline void lduh(Register s1, RegisterOrConstant s2, Register d );
831 inline void ldsh(Register s1, RegisterOrConstant s2, Register d );
832 inline void lduw(Register s1, RegisterOrConstant s2, Register d );
833 inline void ldsw(Register s1, RegisterOrConstant s2, Register d );
834 inline void ldx( Register s1, RegisterOrConstant s2, Register d );
835 inline void ld( Register s1, RegisterOrConstant s2, Register d );
836 inline void ldd( Register s1, RegisterOrConstant s2, Register d );
837
838 using Assembler::ldf;
839 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
840 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
841
842 // little-endian
843 inline void lduwl(Register s1, Register s2, Register d);
844 inline void ldswl(Register s1, Register s2, Register d);
845 inline void ldxl( Register s1, Register s2, Register d);
846 inline void ldfl(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
847
848 // membar psuedo instruction. takes into account target memory model.
849 inline void membar( Assembler::Membar_mask_bits const7a );
850
851 // returns if membar generates anything.
852 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
853
854 // mov pseudo instructions
855 inline void mov( Register s, Register d);
856
857 inline void mov_or_nop( Register s, Register d);
858
859 inline void mov( int simm13a, Register d);
860
861 using Assembler::prefetch;
862 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
863
864 using Assembler::stb;
865 using Assembler::sth;
866 using Assembler::stw;
867 using Assembler::stx;
868 using Assembler::std;
869
870 #ifdef ASSERT
871 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
872 inline void st(Register d, Register s1, ByteSize simm13a);
873 #endif
874
875 inline void st(Register d, Register s1, Register s2);
876 inline void st(Register d, Register s1, int simm13a);
877
878 inline void stb(Register d, const Address& a, int offset = 0 );
879 inline void sth(Register d, const Address& a, int offset = 0 );
880 inline void stw(Register d, const Address& a, int offset = 0 );
881 inline void stx(Register d, const Address& a, int offset = 0 );
882 inline void st( Register d, const Address& a, int offset = 0 );
883 inline void std(Register d, const Address& a, int offset = 0 );
884
885 inline void stb(Register d, Register s1, RegisterOrConstant s2 );
886 inline void sth(Register d, Register s1, RegisterOrConstant s2 );
887 inline void stw(Register d, Register s1, RegisterOrConstant s2 );
888 inline void stx(Register d, Register s1, RegisterOrConstant s2 );
889 inline void std(Register d, Register s1, RegisterOrConstant s2 );
890 inline void st( Register d, Register s1, RegisterOrConstant s2 );
891
892 using Assembler::stf;
893 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
894 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
895
896 // Note: offset is added to s2.
897 using Assembler::sub;
898 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
899
900 using Assembler::swap;
901 inline void swap(const Address& a, Register d, int offset = 0);
902
903 // address pseudos: make these names unlike instruction names to avoid confusion
904 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
905 inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
906 inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
907 inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
908 inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
909 inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
910 inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
911 inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
912 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
913
914 // ring buffer traceable jumps
915
916 void jmp2( Register r1, Register r2, const char* file, int line );
917 void jmp ( Register r1, int offset, const char* file, int line );
918
919 void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
920 void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
921
922
923 // argument pseudos:
924
925 inline void load_argument( Argument& a, Register d );
926 inline void store_argument( Register s, Argument& a );
927 inline void store_ptr_argument( Register s, Argument& a );
928 inline void store_float_argument( FloatRegister s, Argument& a );
929 inline void store_double_argument( FloatRegister s, Argument& a );
930 inline void store_long_argument( Register s, Argument& a );
931
932 // handy macros:
933
934 inline void round_to( Register r, int modulus );
935
936 // --------------------------------------------------
937
938 // Functions for isolating 64 bit loads for LP64
939 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
940 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
941 inline void ld_ptr(Register s1, Register s2, Register d);
942 inline void ld_ptr(Register s1, int simm13a, Register d);
943 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
944 inline void ld_ptr(const Address& a, Register d, int offset = 0);
945 inline void st_ptr(Register d, Register s1, Register s2);
946 inline void st_ptr(Register d, Register s1, int simm13a);
947 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
948 inline void st_ptr(Register d, const Address& a, int offset = 0);
949
950 #ifdef ASSERT
951 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
952 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
953 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
954 #endif
955
956 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
957 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
958 inline void ld_long(Register s1, Register s2, Register d);
959 inline void ld_long(Register s1, int simm13a, Register d);
960 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
961 inline void ld_long(const Address& a, Register d, int offset = 0);
962 inline void st_long(Register d, Register s1, Register s2);
963 inline void st_long(Register d, Register s1, int simm13a);
964 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
965 inline void st_long(Register d, const Address& a, int offset = 0);
966
967 // Helpers for address formation.
968 // - They emit only a move if s2 is a constant zero.
969 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
970 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
971 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
972 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
973 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
974
975 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
976 if (is_simm13(src.constant_or_zero()))
977 return src; // register or short constant
978 guarantee(temp != noreg, "constant offset overflow");
979 set(src.as_constant(), temp);
980 return temp;
981 }
982
983 // --------------------------------------------------
984
985 public:
986 // traps as per trap.h (SPARC ABI?)
987
988 void breakpoint_trap();
989 void breakpoint_trap(Condition c, CC cc);
990
991 // Support for serializing memory accesses between threads
992 void serialize_memory(Register thread, Register tmp1, Register tmp2);
993
994 // Stack frame creation/removal
995 void enter();
996 void leave();
997
998 // Manipulation of C++ bools
999 // These are idioms to flag the need for care with accessing bools but on
1000 // this platform we assume byte size
1001
1002 inline void stbool(Register d, const Address& a);
1003 inline void ldbool(const Address& a, Register d);
1004 inline void movbool( bool boolconst, Register d);
1005
1006 void load_mirror(Register mirror, Register method);
1007
1008 // klass oop manipulations if compressed
1009 void load_klass(Register src_oop, Register klass);
1010 void store_klass(Register klass, Register dst_oop);
1011 void store_klass_gap(Register s, Register dst_oop);
1012
1013 // oop manipulations
1014 void load_heap_oop(const Address& s, Register d);
1015 void load_heap_oop(Register s1, Register s2, Register d);
1016 void load_heap_oop(Register s1, int simm13a, Register d);
1017 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
1018 void store_heap_oop(Register d, Register s1, Register s2);
1019 void store_heap_oop(Register d, Register s1, int simm13a);
1020 void store_heap_oop(Register d, const Address& a, int offset = 0);
1021
1022 void encode_heap_oop(Register src, Register dst);
1023 void encode_heap_oop(Register r) {
1024 encode_heap_oop(r, r);
1025 }
1026 void decode_heap_oop(Register src, Register dst);
1027 void decode_heap_oop(Register r) {
1028 decode_heap_oop(r, r);
1029 }
1030 void encode_heap_oop_not_null(Register r);
1031 void decode_heap_oop_not_null(Register r);
1032 void encode_heap_oop_not_null(Register src, Register dst);
1033 void decode_heap_oop_not_null(Register src, Register dst);
1034
1035 void encode_klass_not_null(Register r);
1036 void decode_klass_not_null(Register r);
1037 void encode_klass_not_null(Register src, Register dst);
1038 void decode_klass_not_null(Register src, Register dst);
1039
1040 // Support for managing the JavaThread pointer (i.e.; the reference to
1041 // thread-local information).
1042 void get_thread(); // load G2_thread
1043 void verify_thread(); // verify G2_thread contents
1044 void save_thread (const Register threache); // save to cache
1045 void restore_thread(const Register thread_cache); // restore from cache
1046
1047 // Support for last Java frame (but use call_VM instead where possible)
1048 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
1049 void reset_last_Java_frame(void);
1050
1051 // Call into the VM.
1052 // Passes the thread pointer (in O0) as a prepended argument.
1053 // Makes sure oop return values are visible to the GC.
1054 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1055 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1056 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1057 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1058
1059 // these overloadings are not presently used on SPARC:
1060 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1061 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1062 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1063 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1064
1065 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
1066 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
1067 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
1068 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
1069
1070 void get_vm_result (Register oop_result);
1071 void get_vm_result_2(Register metadata_result);
1072
1073 // vm result is currently getting hijacked to for oop preservation
1074 void set_vm_result(Register oop_result);
1075
1076 // Emit the CompiledIC call idiom
1077 void ic_call(address entry, bool emit_delay = true, jint method_index = 0);
1078
1079 // if call_VM_base was called with check_exceptions=false, then call
1080 // check_and_forward_exception to handle exceptions when it is safe
1081 void check_and_forward_exception(Register scratch_reg);
1082
1083 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1084 void push_fTOS();
1085
1086 // pops double TOS element from CPU stack and pushes on FPU stack
1087 void pop_fTOS();
1088
1089 void empty_FPU_stack();
1090
1091 void push_IU_state();
1092 void pop_IU_state();
1093
1094 void push_FPU_state();
1095 void pop_FPU_state();
1096
1097 void push_CPU_state();
1098 void pop_CPU_state();
1099
1100 // Returns the byte size of the instructions generated by decode_klass_not_null().
1101 static int instr_size_for_decode_klass_not_null();
1102
1103 // if heap base register is used - reinit it with the correct value
1104 void reinit_heapbase();
1105
1106 // Debugging
1107 void _verify_oop(Register reg, const char * msg, const char * file, int line);
1108 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
1109
1110 // TODO: verify_method and klass metadata (compare against vptr?)
1111 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1112 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1113
1114 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
1115 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
1116 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1117 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1118
1119 // only if +VerifyOops
1120 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1121 // only if +VerifyFPU
1122 void stop(const char* msg); // prints msg, dumps registers and stops execution
1123 void warn(const char* msg); // prints msg, but don't stop
1124 void untested(const char* what = "");
1125 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1126 void should_not_reach_here() { stop("should not reach here"); }
1127 void print_CPU_state();
1128
1129 // oops in code
1130 AddressLiteral allocate_oop_address(jobject obj); // allocate_index
1131 AddressLiteral constant_oop_address(jobject obj); // find_index
1132 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
1133 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
1134 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address
1135
1136 // metadata in code that we have to keep track of
1137 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
1138 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
1139 inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address
1140 inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address
1141 inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address
1142
1143 void set_narrow_oop( jobject obj, Register d );
1144 void set_narrow_klass( Klass* k, Register d );
1145
1146 // nop padding
1147 void align(int modulus);
1148
1149 // declare a safepoint
1150 void safepoint();
1151
1152 // factor out part of stop into subroutine to save space
1153 void stop_subroutine();
1154 // factor out part of verify_oop into subroutine to save space
1155 void verify_oop_subroutine();
1156
1157 // side-door communication with signalHandler in os_solaris.cpp
1158 static address _verify_oop_implicit_branch[3];
1159
1160 int total_frame_size_in_bytes(int extraWords);
1161
1162 // used when extraWords known statically
1163 void save_frame(int extraWords = 0);
1164 void save_frame_c1(int size_in_bytes);
1165 // make a frame, and simultaneously pass up one or two register value
1166 // into the new register window
1167 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
1168
1169 // give no. (outgoing) params, calc # of words will need on frame
1170 void calc_mem_param_words(Register Rparam_words, Register Rresult);
1171
1172 // used to calculate frame size dynamically
1173 // result is in bytes and must be negated for save inst
1174 void calc_frame_size(Register extraWords, Register resultReg);
1175
1176 // calc and also save
1177 void calc_frame_size_and_save(Register extraWords, Register resultReg);
1178
1179 static void debug(char* msg, RegistersForDebugging* outWindow);
1180
1181 // implementations of bytecodes used by both interpreter and compiler
1182
1183 void lcmp( Register Ra_hi, Register Ra_low,
1184 Register Rb_hi, Register Rb_low,
1185 Register Rresult);
1186
1187 void lneg( Register Rhi, Register Rlow );
1188
1189 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
1190 Register Rout_high, Register Rout_low, Register Rtemp );
1191
1192 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
1193 Register Rout_high, Register Rout_low, Register Rtemp );
1194
1195 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
1196 Register Rout_high, Register Rout_low, Register Rtemp );
1197
1198 void lcmp( Register Ra, Register Rb, Register Rresult);
1199
1200 // Load and store values by size and signed-ness
1201 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
1202 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
1203
1204 void float_cmp( bool is_float, int unordered_result,
1205 FloatRegister Fa, FloatRegister Fb,
1206 Register Rresult);
1207
1208 void save_all_globals_into_locals();
1209 void restore_globals_from_locals();
1210
1211 // These set the icc condition code to equal if the lock succeeded
1212 // and notEqual if it failed and requires a slow case
1213 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
1214 Register Rscratch,
1215 BiasedLockingCounters* counters = NULL,
1216 bool try_bias = UseBiasedLocking);
1217 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
1218 Register Rscratch,
1219 bool try_bias = UseBiasedLocking);
1220
1221 // Biased locking support
1222 // Upon entry, lock_reg must point to the lock record on the stack,
1223 // obj_reg must contain the target object, and mark_reg must contain
1224 // the target object's header.
1225 // Destroys mark_reg if an attempt is made to bias an anonymously
1226 // biased lock. In this case a failure will go either to the slow
1227 // case or fall through with the notEqual condition code set with
1228 // the expectation that the slow case in the runtime will be called.
1229 // In the fall-through case where the CAS-based lock is done,
1230 // mark_reg is not destroyed.
1231 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
1232 Label& done, Label* slow_case = NULL,
1233 BiasedLockingCounters* counters = NULL);
1234 // Upon entry, the base register of mark_addr must contain the oop.
1235 // Destroys temp_reg.
1236
1237 // If allow_delay_slot_filling is set to true, the next instruction
1238 // emitted after this one will go in an annulled delay slot if the
1239 // biased locking exit case failed.
1240 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
1241
1242 // allocation
1243 void eden_allocate(
1244 Register obj, // result: pointer to object after successful allocation
1245 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1246 int con_size_in_bytes, // object size in bytes if known at compile time
1247 Register t1, // temp register
1248 Register t2, // temp register
1249 Label& slow_case // continuation point if fast allocation fails
1250 );
1251 void tlab_allocate(
1252 Register obj, // result: pointer to object after successful allocation
1253 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1254 int con_size_in_bytes, // object size in bytes if known at compile time
1255 Register t1, // temp register
1256 Label& slow_case // continuation point if fast allocation fails
1257 );
1258 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1259 void zero_memory(Register base, Register index);
1260 void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
1261 Register t1, Register t2);
1262
1263 // interface method calling
1264 void lookup_interface_method(Register recv_klass,
1265 Register intf_klass,
1266 RegisterOrConstant itable_index,
1267 Register method_result,
1268 Register temp_reg, Register temp2_reg,
1269 Label& no_such_interface);
1270
1271 // virtual method calling
1272 void lookup_virtual_method(Register recv_klass,
1273 RegisterOrConstant vtable_index,
1274 Register method_result);
1275
1276 // Test sub_klass against super_klass, with fast and slow paths.
1277
1278 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1279 // One of the three labels can be NULL, meaning take the fall-through.
1280 // If super_check_offset is -1, the value is loaded up from super_klass.
1281 // No registers are killed, except temp_reg and temp2_reg.
1282 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
1283 void check_klass_subtype_fast_path(Register sub_klass,
1284 Register super_klass,
1285 Register temp_reg,
1286 Register temp2_reg,
1287 Label* L_success,
1288 Label* L_failure,
1289 Label* L_slow_path,
1290 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1291
1292 // The rest of the type check; must be wired to a corresponding fast path.
1293 // It does not repeat the fast path logic, so don't use it standalone.
1294 // The temp_reg can be noreg, if no temps are available.
1295 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
1296 // Updates the sub's secondary super cache as necessary.
1297 void check_klass_subtype_slow_path(Register sub_klass,
1298 Register super_klass,
1299 Register temp_reg,
1300 Register temp2_reg,
1301 Register temp3_reg,
1302 Register temp4_reg,
1303 Label* L_success,
1304 Label* L_failure);
1305
1306 // Simplified, combined version, good for typical uses.
1307 // Falls through on failure.
1308 void check_klass_subtype(Register sub_klass,
1309 Register super_klass,
1310 Register temp_reg,
1311 Register temp2_reg,
1312 Label& L_success);
1313
1314 // method handles (JSR 292)
1315 // offset relative to Gargs of argument at tos[arg_slot].
1316 // (arg_slot == 0 means the last argument, not the first).
1317 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
1318 Register temp_reg,
1319 int extra_slot_offset = 0);
1320 // Address of Gargs and argument_offset.
1321 Address argument_address(RegisterOrConstant arg_slot,
1322 Register temp_reg = noreg,
1323 int extra_slot_offset = 0);
1324
1325 // Stack overflow checking
1326
1327 // Note: this clobbers G3_scratch
1328 inline void bang_stack_with_offset(int offset);
1329
1330 // Writes to stack successive pages until offset reached to check for
1331 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
1332 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
1333
1334 // Check for reserved stack access in method being exited (for JIT)
1335 void reserved_stack_check();
1336
1337 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
1338
1339 void verify_tlab();
1340
1341 Condition negate_condition(Condition cond);
1342
1343 // Helper functions for statistics gathering.
1344 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
1345 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
1346 // Unconditional increment.
1347 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
1348 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
1349
1350 #ifdef COMPILER2
1351 // Compress char[] to byte[] by compressing 16 bytes at once. Return 0 on failure.
1352 void string_compress_16(Register src, Register dst, Register cnt, Register result,
1353 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
1354 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, Label& Ldone);
1355
1356 // Compress char[] to byte[]. Return 0 on failure.
1357 void string_compress(Register src, Register dst, Register cnt, Register tmp, Register result, Label& Ldone);
1358
1359 // Inflate byte[] to char[] by inflating 16 bytes at once.
1360 void string_inflate_16(Register src, Register dst, Register cnt, Register tmp,
1361 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, FloatRegister ftmp4, Label& Ldone);
1362
1363 // Inflate byte[] to char[].
1364 void string_inflate(Register src, Register dst, Register cnt, Register tmp, Label& Ldone);
1365
1366 void string_compare(Register str1, Register str2,
1367 Register cnt1, Register cnt2,
1368 Register tmp1, Register tmp2,
1369 Register result, int ae);
1370
1371 void array_equals(bool is_array_equ, Register ary1, Register ary2,
1372 Register limit, Register tmp, Register result, bool is_byte);
1373 // test for negative bytes in input string of a given size, result 0 if none
1374 void has_negatives(Register inp, Register size, Register result,
1375 Register t2, Register t3, Register t4,
1376 Register t5);
1377
1378 #endif
1379
1380 // Use BIS for zeroing
1381 void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
1382
1383 // Update CRC-32[C] with a byte value according to constants in table
1384 void update_byte_crc32(Register crc, Register val, Register table);
1385
1386 // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
1387 void reverse_bytes_32(Register src, Register dst, Register tmp);
1388 void movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2);
1389 void movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2);
1390
1391 // CRC32 code for java.util.zip.CRC32::updateBytes0() instrinsic.
1392 void kernel_crc32(Register crc, Register buf, Register len, Register table);
1393 // Fold 128-bit data chunk
1394 void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset);
1395 void fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo);
1396 // Fold 8-bit data
1397 void fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp);
1398 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1399 // CRC32C code for java.util.zip.CRC32C::updateBytes/updateDirectByteBuffer instrinsic.
1400 void kernel_crc32c(Register crc, Register buf, Register len, Register table);
1401
1402 };
1403
1404 /**
1405 * class SkipIfEqual:
1406 *
1407 * Instantiating this class will result in assembly code being output that will
1408 * jump around any code emitted between the creation of the instance and it's
1409 * automatic destruction at the end of a scope block, depending on the value of
1410 * the flag passed to the constructor, which will be checked at run-time.
1411 */
1412 class SkipIfEqual : public StackObj {
1413 private:
1414 MacroAssembler* _masm;
1415 Label _label;
1416
1417 public:
1418 // 'temp' is a temp register that this object can use (and trash)
1419 SkipIfEqual(MacroAssembler*, Register temp,
1420 const bool* flag_addr, Assembler::Condition condition);
1421 ~SkipIfEqual();
1422 };
1423
1424 #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP