1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_LIRAssembler.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "c1/c1_ValueStack.hpp"
31 #include "ci/ciArrayKlass.hpp"
32 #include "ci/ciInstance.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/cardTableModRefBS.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "nativeInst_sparc.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 #define __ _masm->
41
42
43 //------------------------------------------------------------
44
45
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
47 if (opr->is_constant()) {
48 LIR_Const* constant = opr->as_constant_ptr();
49 switch (constant->type()) {
50 case T_INT: {
51 jint value = constant->as_jint();
52 return Assembler::is_simm13(value);
53 }
54
55 default:
56 return false;
57 }
58 }
59 return false;
60 }
61
62
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
64 switch (op->code()) {
65 case lir_null_check:
66 return true;
67
68
69 case lir_add:
70 case lir_ushr:
71 case lir_shr:
72 case lir_shl:
73 // integer shifts and adds are always one instruction
74 return op->result_opr()->is_single_cpu();
75
76
77 case lir_move: {
78 LIR_Op1* op1 = op->as_Op1();
79 LIR_Opr src = op1->in_opr();
80 LIR_Opr dst = op1->result_opr();
81
82 if (src == dst) {
83 NEEDS_CLEANUP;
84 // this works around a problem where moves with the same src and dst
85 // end up in the delay slot and then the assembler swallows the mov
86 // since it has no effect and then it complains because the delay slot
87 // is empty. returning false stops the optimizer from putting this in
88 // the delay slot
89 return false;
90 }
91
92 // don't put moves involving oops into the delay slot since the VerifyOops code
93 // will make it much larger than a single instruction.
94 if (VerifyOops) {
95 return false;
96 }
97
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
100 return false;
101 }
102
103 if (UseCompressedOops) {
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
106 }
107
108 if (UseCompressedClassPointers) {
109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&
110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;
111 }
112
113 if (dst->is_register()) {
114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
115 return !PatchALot;
116 } else if (src->is_single_stack()) {
117 return true;
118 }
119 }
120
121 if (src->is_register()) {
122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
123 return !PatchALot;
124 } else if (dst->is_single_stack()) {
125 return true;
126 }
127 }
128
129 if (dst->is_register() &&
130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
132 return true;
133 }
134
135 return false;
136 }
137
138 default:
139 return false;
140 }
141 ShouldNotReachHere();
142 }
143
144
145 LIR_Opr LIR_Assembler::receiverOpr() {
146 return FrameMap::O0_oop_opr;
147 }
148
149
150 LIR_Opr LIR_Assembler::osrBufferPointer() {
151 return FrameMap::I0_opr;
152 }
153
154
155 int LIR_Assembler::initial_frame_size_in_bytes() const {
156 return in_bytes(frame_map()->framesize_in_bytes());
157 }
158
159
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
161 // we fetch the class of the receiver (O0) and compare it with the cached class.
162 // If they do not match we jump to slow case.
163 int LIR_Assembler::check_icache() {
164 int offset = __ offset();
165 __ inline_cache_check(O0, G5_inline_cache_reg);
166 return offset;
167 }
168
169
170 void LIR_Assembler::osr_entry() {
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
172 //
173 // 1. Create a new compiled activation.
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
175 // at the osr_bci; it is not initialized.
176 // 3. Jump to the continuation address in compiled code to resume execution.
177
178 // OSR entry point
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
181 ValueStack* entry_state = osr_entry->end()->state();
182 int number_of_locks = entry_state->locks_size();
183
184 // Create a frame for the compiled activation.
185 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
186
187 // OSR buffer is
188 //
189 // locals[nlocals-1..0]
190 // monitors[number_of_locks-1..0]
191 //
192 // locals is a direct copy of the interpreter frame so in the osr buffer
193 // so first slot in the local array is the last local from the interpreter
194 // and last slot is local[0] (receiver) from the interpreter
195 //
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
198 // in the interpreter frame (the method lock if a sync method)
199
200 // Initialize monitors in the compiled activation.
201 // I0: pointer to osr buffer
202 //
203 // All other registers are dead at this point and the locals will be
204 // copied into place by code emitted in the IR.
205
206 Register OSR_buf = osrBufferPointer()->as_register();
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
208 int monitor_offset = BytesPerWord * method()->max_locals() +
209 (2 * BytesPerWord) * (number_of_locks - 1);
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
211 // the OSR buffer using 2 word entries: first the lock and then
212 // the oop.
213 for (int i = 0; i < number_of_locks; i++) {
214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
215 #ifdef ASSERT
216 // verify the interpreter's monitor has a non-null object
217 {
218 Label L;
219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);
221 __ stop("locked object is NULL");
222 __ bind(L);
223 }
224 #endif // ASSERT
225 // Copy the lock field into the compiled activation.
226 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
230 }
231 }
232 }
233
234
235 // Optimized Library calls
236 // This is the fast version of java.lang.String.compare; it has not
237 // OSR-entry and therefore, we generate a slow version for OSR's
238 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
239 Register str0 = left->as_register();
240 Register str1 = right->as_register();
241
242 Label Ldone;
243
244 Register result = dst->as_register();
245 {
246 // Get a pointer to the first character of string0 in tmp0
247 // and get string0.length() in str0
248 // Get a pointer to the first character of string1 in tmp1
249 // and get string1.length() in str1
250 // Also, get string0.length()-string1.length() in
251 // o7 and get the condition code set
252 // Note: some instructions have been hoisted for better instruction scheduling
253
254 Register tmp0 = L0;
255 Register tmp1 = L1;
256 Register tmp2 = L2;
257
258 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
259 if (java_lang_String::has_offset_field()) {
260 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
261 int count_offset = java_lang_String:: count_offset_in_bytes();
262 __ load_heap_oop(str0, value_offset, tmp0);
263 __ ld(str0, offset_offset, tmp2);
264 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
265 __ ld(str0, count_offset, str0);
266 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
267 } else {
268 __ load_heap_oop(str0, value_offset, tmp1);
269 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
270 __ ld(tmp1, arrayOopDesc::length_offset_in_bytes(), str0);
271 }
272
273 // str1 may be null
274 add_debug_info_for_null_check_here(info);
275
276 if (java_lang_String::has_offset_field()) {
277 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
278 int count_offset = java_lang_String:: count_offset_in_bytes();
279 __ load_heap_oop(str1, value_offset, tmp1);
280 __ add(tmp0, tmp2, tmp0);
281
282 __ ld(str1, offset_offset, tmp2);
283 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
284 __ ld(str1, count_offset, str1);
285 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
286 __ add(tmp1, tmp2, tmp1);
287 } else {
288 __ load_heap_oop(str1, value_offset, tmp2);
289 __ add(tmp2, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
290 __ ld(tmp2, arrayOopDesc::length_offset_in_bytes(), str1);
291 }
292 __ subcc(str0, str1, O7);
293 }
294
295 {
296 // Compute the minimum of the string lengths, scale it and store it in limit
297 Register count0 = I0;
298 Register count1 = I1;
299 Register limit = L3;
300
301 Label Lskip;
302 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
303 __ br(Assembler::greater, true, Assembler::pt, Lskip);
304 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
305 __ bind(Lskip);
306
307 // If either string is empty (or both of them) the result is the difference in lengths
308 __ cmp(limit, 0);
309 __ br(Assembler::equal, true, Assembler::pn, Ldone);
310 __ delayed()->mov(O7, result); // result is difference in lengths
311 }
312
313 {
314 // Neither string is empty
315 Label Lloop;
316
317 Register base0 = L0;
318 Register base1 = L1;
319 Register chr0 = I0;
320 Register chr1 = I1;
321 Register limit = L3;
322
323 // Shift base0 and base1 to the end of the arrays, negate limit
324 __ add(base0, limit, base0);
325 __ add(base1, limit, base1);
326 __ neg(limit); // limit = -min{string0.length(), string1.length()}
327
328 __ lduh(base0, limit, chr0);
329 __ bind(Lloop);
330 __ lduh(base1, limit, chr1);
331 __ subcc(chr0, chr1, chr0);
332 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
333 assert(chr0 == result, "result must be pre-placed");
334 __ delayed()->inccc(limit, sizeof(jchar));
335 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
336 __ delayed()->lduh(base0, limit, chr0);
337 }
338
339 // If strings are equal up to min length, return the length difference.
340 __ mov(O7, result);
341
342 // Otherwise, return the difference between the first mismatched chars.
343 __ bind(Ldone);
344 }
345
346
347 // --------------------------------------------------------------------------------------------
348
349 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
350 if (!GenerateSynchronizationCode) return;
351
352 Register obj_reg = obj_opr->as_register();
353 Register lock_reg = lock_opr->as_register();
354
355 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
356 Register reg = mon_addr.base();
357 int offset = mon_addr.disp();
358 // compute pointer to BasicLock
359 if (mon_addr.is_simm13()) {
360 __ add(reg, offset, lock_reg);
361 }
362 else {
363 __ set(offset, lock_reg);
364 __ add(reg, lock_reg, lock_reg);
365 }
366 // unlock object
367 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
368 // _slow_case_stubs->append(slow_case);
369 // temporary fix: must be created after exceptionhandler, therefore as call stub
370 _slow_case_stubs->append(slow_case);
371 if (UseFastLocking) {
372 // try inlined fast unlocking first, revert to slow locking if it fails
373 // note: lock_reg points to the displaced header since the displaced header offset is 0!
374 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
375 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
376 } else {
377 // always do slow unlocking
378 // note: the slow unlocking code could be inlined here, however if we use
379 // slow unlocking, speed doesn't matter anyway and this solution is
380 // simpler and requires less duplicated code - additionally, the
381 // slow unlocking code is the same in either case which simplifies
382 // debugging
383 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
384 __ delayed()->nop();
385 }
386 // done
387 __ bind(*slow_case->continuation());
388 }
389
390
391 int LIR_Assembler::emit_exception_handler() {
392 // if the last instruction is a call (typically to do a throw which
393 // is coming at the end after block reordering) the return address
394 // must still point into the code area in order to avoid assertion
395 // failures when searching for the corresponding bci => add a nop
396 // (was bug 5/14/1999 - gri)
397 __ nop();
398
399 // generate code for exception handler
400 ciMethod* method = compilation()->method();
401
402 address handler_base = __ start_a_stub(exception_handler_size);
403
404 if (handler_base == NULL) {
405 // not enough space left for the handler
406 bailout("exception handler overflow");
407 return -1;
408 }
409
410 int offset = code_offset();
411
412 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
413 __ delayed()->nop();
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
416 __ end_a_stub();
417
418 return offset;
419 }
420
421
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
430
431 int offset = code_offset();
432
433 // Fetch the exception from TLS and clear out exception related thread state
434 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);
435 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
436 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));
437
438 __ bind(_unwind_handler_entry);
439 __ verify_not_null_oop(O0);
440 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
441 __ mov(O0, I0); // Preserve the exception
442 }
443
444 // Preform needed unlocking
445 MonitorExitStub* stub = NULL;
446 if (method()->is_synchronized()) {
447 monitor_address(0, FrameMap::I1_opr);
448 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);
449 __ unlock_object(I3, I2, I1, *stub->entry());
450 __ bind(*stub->continuation());
451 }
452
453 if (compilation()->env()->dtrace_method_probes()) {
454 __ mov(G2_thread, O0);
455 __ save_thread(I1); // need to preserve thread in G2 across
456 // runtime call
457 metadata2reg(method()->constant_encoding(), O1);
458 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);
459 __ delayed()->nop();
460 __ restore_thread(I1);
461 }
462
463 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
464 __ mov(I0, O0); // Restore the exception
465 }
466
467 // dispatch to the unwind logic
468 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
469 __ delayed()->nop();
470
471 // Emit the slow path assembly
472 if (stub != NULL) {
473 stub->emit_code(this);
474 }
475
476 return offset;
477 }
478
479
480 int LIR_Assembler::emit_deopt_handler() {
481 // if the last instruction is a call (typically to do a throw which
482 // is coming at the end after block reordering) the return address
483 // must still point into the code area in order to avoid assertion
484 // failures when searching for the corresponding bci => add a nop
485 // (was bug 5/14/1999 - gri)
486 __ nop();
487
488 // generate code for deopt handler
489 ciMethod* method = compilation()->method();
490 address handler_base = __ start_a_stub(deopt_handler_size);
491 if (handler_base == NULL) {
492 // not enough space left for the handler
493 bailout("deopt handler overflow");
494 return -1;
495 }
496
497 int offset = code_offset();
498 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
499 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
500 __ delayed()->nop();
501 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
502 __ end_a_stub();
503
504 return offset;
505 }
506
507
508 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
509 if (o == NULL) {
510 __ set(NULL_WORD, reg);
511 } else {
512 int oop_index = __ oop_recorder()->find_index(o);
513 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");
514 RelocationHolder rspec = oop_Relocation::spec(oop_index);
515 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
516 }
517 }
518
519
520 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
521 // Allocate a new index in table to hold the object once it's been patched
522 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
523 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
524
525 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
526 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
527 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
528 // NULL will be dynamically patched later and the patched value may be large. We must
529 // therefore generate the sethi/add as a placeholders
530 __ patchable_set(addrlit, reg);
531
532 patching_epilog(patch, lir_patch_normal, reg, info);
533 }
534
535
536 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
537 __ set_metadata_constant(o, reg);
538 }
539
540 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
541 // Allocate a new index in table to hold the klass once it's been patched
542 int index = __ oop_recorder()->allocate_metadata_index(NULL);
543 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
544 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));
545 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
546 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
547 // NULL will be dynamically patched later and the patched value may be large. We must
548 // therefore generate the sethi/add as a placeholders
549 __ patchable_set(addrlit, reg);
550
551 patching_epilog(patch, lir_patch_normal, reg, info);
552 }
553
554 void LIR_Assembler::emit_op3(LIR_Op3* op) {
555 Register Rdividend = op->in_opr1()->as_register();
556 Register Rdivisor = noreg;
557 Register Rscratch = op->in_opr3()->as_register();
558 Register Rresult = op->result_opr()->as_register();
559 int divisor = -1;
560
561 if (op->in_opr2()->is_register()) {
562 Rdivisor = op->in_opr2()->as_register();
563 } else {
564 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
565 assert(Assembler::is_simm13(divisor), "can only handle simm13");
566 }
567
568 assert(Rdividend != Rscratch, "");
569 assert(Rdivisor != Rscratch, "");
570 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
571
572 if (Rdivisor == noreg && is_power_of_2(divisor)) {
573 // convert division by a power of two into some shifts and logical operations
574 if (op->code() == lir_idiv) {
575 if (divisor == 2) {
576 __ srl(Rdividend, 31, Rscratch);
577 } else {
578 __ sra(Rdividend, 31, Rscratch);
579 __ and3(Rscratch, divisor - 1, Rscratch);
580 }
581 __ add(Rdividend, Rscratch, Rscratch);
582 __ sra(Rscratch, log2_intptr(divisor), Rresult);
583 return;
584 } else {
585 if (divisor == 2) {
586 __ srl(Rdividend, 31, Rscratch);
587 } else {
588 __ sra(Rdividend, 31, Rscratch);
589 __ and3(Rscratch, divisor - 1,Rscratch);
590 }
591 __ add(Rdividend, Rscratch, Rscratch);
592 __ andn(Rscratch, divisor - 1,Rscratch);
593 __ sub(Rdividend, Rscratch, Rresult);
594 return;
595 }
596 }
597
598 __ sra(Rdividend, 31, Rscratch);
599 __ wry(Rscratch);
600
601 add_debug_info_for_div0_here(op->info());
602
603 if (Rdivisor != noreg) {
604 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
605 } else {
606 assert(Assembler::is_simm13(divisor), "can only handle simm13");
607 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
608 }
609
610 Label skip;
611 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
612 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
613 __ bind(skip);
614
615 if (op->code() == lir_irem) {
616 if (Rdivisor != noreg) {
617 __ smul(Rscratch, Rdivisor, Rscratch);
618 } else {
619 __ smul(Rscratch, divisor, Rscratch);
620 }
621 __ sub(Rdividend, Rscratch, Rresult);
622 }
623 }
624
625
626 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
627 #ifdef ASSERT
628 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
629 if (op->block() != NULL) _branch_target_blocks.append(op->block());
630 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
631 #endif
632 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
633
634 if (op->cond() == lir_cond_always) {
635 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
636 } else if (op->code() == lir_cond_float_branch) {
637 assert(op->ublock() != NULL, "must have unordered successor");
638 bool is_unordered = (op->ublock() == op->block());
639 Assembler::Condition acond;
640 switch (op->cond()) {
641 case lir_cond_equal: acond = Assembler::f_equal; break;
642 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
643 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
644 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
645 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
646 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
647 default : ShouldNotReachHere();
648 }
649 __ fb( acond, false, Assembler::pn, *(op->label()));
650 } else {
651 assert (op->code() == lir_branch, "just checking");
652
653 Assembler::Condition acond;
654 switch (op->cond()) {
655 case lir_cond_equal: acond = Assembler::equal; break;
656 case lir_cond_notEqual: acond = Assembler::notEqual; break;
657 case lir_cond_less: acond = Assembler::less; break;
658 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
659 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
660 case lir_cond_greater: acond = Assembler::greater; break;
661 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
662 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
663 default: ShouldNotReachHere();
664 };
665
666 // sparc has different condition codes for testing 32-bit
667 // vs. 64-bit values. We could always test xcc is we could
668 // guarantee that 32-bit loads always sign extended but that isn't
669 // true and since sign extension isn't free, it would impose a
670 // slight cost.
671 #ifdef _LP64
672 if (op->type() == T_INT) {
673 __ br(acond, false, Assembler::pn, *(op->label()));
674 } else
675 #endif
676 __ brx(acond, false, Assembler::pn, *(op->label()));
677 }
678 // The peephole pass fills the delay slot
679 }
680
681
682 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
683 Bytecodes::Code code = op->bytecode();
684 LIR_Opr dst = op->result_opr();
685
686 switch(code) {
687 case Bytecodes::_i2l: {
688 Register rlo = dst->as_register_lo();
689 Register rhi = dst->as_register_hi();
690 Register rval = op->in_opr()->as_register();
691 #ifdef _LP64
692 __ sra(rval, 0, rlo);
693 #else
694 __ mov(rval, rlo);
695 __ sra(rval, BitsPerInt-1, rhi);
696 #endif
697 break;
698 }
699 case Bytecodes::_i2d:
700 case Bytecodes::_i2f: {
701 bool is_double = (code == Bytecodes::_i2d);
702 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
703 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
704 FloatRegister rsrc = op->in_opr()->as_float_reg();
705 if (rsrc != rdst) {
706 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
707 }
708 __ fitof(w, rdst, rdst);
709 break;
710 }
711 case Bytecodes::_f2i:{
712 FloatRegister rsrc = op->in_opr()->as_float_reg();
713 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
714 Label L;
715 // result must be 0 if value is NaN; test by comparing value to itself
716 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
717 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
718 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
719 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
720 // move integer result from float register to int register
721 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
722 __ bind (L);
723 break;
724 }
725 case Bytecodes::_l2i: {
726 Register rlo = op->in_opr()->as_register_lo();
727 Register rhi = op->in_opr()->as_register_hi();
728 Register rdst = dst->as_register();
729 #ifdef _LP64
730 __ sra(rlo, 0, rdst);
731 #else
732 __ mov(rlo, rdst);
733 #endif
734 break;
735 }
736 case Bytecodes::_d2f:
737 case Bytecodes::_f2d: {
738 bool is_double = (code == Bytecodes::_f2d);
739 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
740 LIR_Opr val = op->in_opr();
741 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
742 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
743 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
744 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
745 __ ftof(vw, dw, rval, rdst);
746 break;
747 }
748 case Bytecodes::_i2s:
749 case Bytecodes::_i2b: {
750 Register rval = op->in_opr()->as_register();
751 Register rdst = dst->as_register();
752 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
753 __ sll (rval, shift, rdst);
754 __ sra (rdst, shift, rdst);
755 break;
756 }
757 case Bytecodes::_i2c: {
758 Register rval = op->in_opr()->as_register();
759 Register rdst = dst->as_register();
760 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
761 __ sll (rval, shift, rdst);
762 __ srl (rdst, shift, rdst);
763 break;
764 }
765
766 default: ShouldNotReachHere();
767 }
768 }
769
770
771 void LIR_Assembler::align_call(LIR_Code) {
772 // do nothing since all instructions are word aligned on sparc
773 }
774
775
776 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
777 __ call(op->addr(), rtype);
778 // The peephole pass fills the delay slot, add_call_info is done in
779 // LIR_Assembler::emit_delay.
780 }
781
782
783 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
784 __ ic_call(op->addr(), false);
785 // The peephole pass fills the delay slot, add_call_info is done in
786 // LIR_Assembler::emit_delay.
787 }
788
789
790 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
791 add_debug_info_for_null_check_here(op->info());
792 __ load_klass(O0, G3_scratch);
793 if (Assembler::is_simm13(op->vtable_offset())) {
794 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
795 } else {
796 // This will generate 2 instructions
797 __ set(op->vtable_offset(), G5_method);
798 // ld_ptr, set_hi, set
799 __ ld_ptr(G3_scratch, G5_method, G5_method);
800 }
801 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch);
802 __ callr(G3_scratch, G0);
803 // the peephole pass fills the delay slot
804 }
805
806 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
807 int store_offset;
808 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
809 assert(!unaligned, "can't handle this");
810 // for offsets larger than a simm13 we setup the offset in O7
811 __ set(offset, O7);
812 store_offset = store(from_reg, base, O7, type, wide);
813 } else {
814 if (type == T_ARRAY || type == T_OBJECT) {
815 __ verify_oop(from_reg->as_register());
816 }
817 store_offset = code_offset();
818 switch (type) {
819 case T_BOOLEAN: // fall through
820 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
821 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
822 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
823 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
824 case T_LONG :
825 #ifdef _LP64
826 if (unaligned || PatchALot) {
827 __ srax(from_reg->as_register_lo(), 32, O7);
828 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
829 __ stw(O7, base, offset + hi_word_offset_in_bytes);
830 } else {
831 __ stx(from_reg->as_register_lo(), base, offset);
832 }
833 #else
834 assert(Assembler::is_simm13(offset + 4), "must be");
835 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
836 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
837 #endif
838 break;
839 case T_ADDRESS:
840 case T_METADATA:
841 __ st_ptr(from_reg->as_register(), base, offset);
842 break;
843 case T_ARRAY : // fall through
844 case T_OBJECT:
845 {
846 if (UseCompressedOops && !wide) {
847 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
848 store_offset = code_offset();
849 __ stw(G3_scratch, base, offset);
850 } else {
851 __ st_ptr(from_reg->as_register(), base, offset);
852 }
853 break;
854 }
855
856 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
857 case T_DOUBLE:
858 {
859 FloatRegister reg = from_reg->as_double_reg();
860 // split unaligned stores
861 if (unaligned || PatchALot) {
862 assert(Assembler::is_simm13(offset + 4), "must be");
863 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
864 __ stf(FloatRegisterImpl::S, reg, base, offset);
865 } else {
866 __ stf(FloatRegisterImpl::D, reg, base, offset);
867 }
868 break;
869 }
870 default : ShouldNotReachHere();
871 }
872 }
873 return store_offset;
874 }
875
876
877 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
878 if (type == T_ARRAY || type == T_OBJECT) {
879 __ verify_oop(from_reg->as_register());
880 }
881 int store_offset = code_offset();
882 switch (type) {
883 case T_BOOLEAN: // fall through
884 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
885 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
886 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
887 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
888 case T_LONG :
889 #ifdef _LP64
890 __ stx(from_reg->as_register_lo(), base, disp);
891 #else
892 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
893 __ std(from_reg->as_register_hi(), base, disp);
894 #endif
895 break;
896 case T_ADDRESS:
897 __ st_ptr(from_reg->as_register(), base, disp);
898 break;
899 case T_ARRAY : // fall through
900 case T_OBJECT:
901 {
902 if (UseCompressedOops && !wide) {
903 __ encode_heap_oop(from_reg->as_register(), G3_scratch);
904 store_offset = code_offset();
905 __ stw(G3_scratch, base, disp);
906 } else {
907 __ st_ptr(from_reg->as_register(), base, disp);
908 }
909 break;
910 }
911 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
912 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
913 default : ShouldNotReachHere();
914 }
915 return store_offset;
916 }
917
918
919 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
920 int load_offset;
921 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
922 assert(base != O7, "destroying register");
923 assert(!unaligned, "can't handle this");
924 // for offsets larger than a simm13 we setup the offset in O7
925 __ set(offset, O7);
926 load_offset = load(base, O7, to_reg, type, wide);
927 } else {
928 load_offset = code_offset();
929 switch(type) {
930 case T_BOOLEAN: // fall through
931 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
932 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
933 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
934 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
935 case T_LONG :
936 if (!unaligned) {
937 #ifdef _LP64
938 __ ldx(base, offset, to_reg->as_register_lo());
939 #else
940 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
941 "must be sequential");
942 __ ldd(base, offset, to_reg->as_register_hi());
943 #endif
944 } else {
945 #ifdef _LP64
946 assert(base != to_reg->as_register_lo(), "can't handle this");
947 assert(O7 != to_reg->as_register_lo(), "can't handle this");
948 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
949 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
950 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
951 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
952 #else
953 if (base == to_reg->as_register_lo()) {
954 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
955 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
956 } else {
957 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
958 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
959 }
960 #endif
961 }
962 break;
963 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break;
964 case T_ADDRESS:
965 #ifdef _LP64
966 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
967 __ lduw(base, offset, to_reg->as_register());
968 __ decode_klass_not_null(to_reg->as_register());
969 } else
970 #endif
971 {
972 __ ld_ptr(base, offset, to_reg->as_register());
973 }
974 break;
975 case T_ARRAY : // fall through
976 case T_OBJECT:
977 {
978 if (UseCompressedOops && !wide) {
979 __ lduw(base, offset, to_reg->as_register());
980 __ decode_heap_oop(to_reg->as_register());
981 } else {
982 __ ld_ptr(base, offset, to_reg->as_register());
983 }
984 break;
985 }
986 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
987 case T_DOUBLE:
988 {
989 FloatRegister reg = to_reg->as_double_reg();
990 // split unaligned loads
991 if (unaligned || PatchALot) {
992 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
993 __ ldf(FloatRegisterImpl::S, base, offset, reg);
994 } else {
995 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
996 }
997 break;
998 }
999 default : ShouldNotReachHere();
1000 }
1001 if (type == T_ARRAY || type == T_OBJECT) {
1002 __ verify_oop(to_reg->as_register());
1003 }
1004 }
1005 return load_offset;
1006 }
1007
1008
1009 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
1010 int load_offset = code_offset();
1011 switch(type) {
1012 case T_BOOLEAN: // fall through
1013 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
1014 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
1015 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1016 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1017 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
1018 case T_ARRAY : // fall through
1019 case T_OBJECT:
1020 {
1021 if (UseCompressedOops && !wide) {
1022 __ lduw(base, disp, to_reg->as_register());
1023 __ decode_heap_oop(to_reg->as_register());
1024 } else {
1025 __ ld_ptr(base, disp, to_reg->as_register());
1026 }
1027 break;
1028 }
1029 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1030 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1031 case T_LONG :
1032 #ifdef _LP64
1033 __ ldx(base, disp, to_reg->as_register_lo());
1034 #else
1035 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1036 "must be sequential");
1037 __ ldd(base, disp, to_reg->as_register_hi());
1038 #endif
1039 break;
1040 default : ShouldNotReachHere();
1041 }
1042 if (type == T_ARRAY || type == T_OBJECT) {
1043 __ verify_oop(to_reg->as_register());
1044 }
1045 return load_offset;
1046 }
1047
1048 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1049 LIR_Const* c = src->as_constant_ptr();
1050 switch (c->type()) {
1051 case T_INT:
1052 case T_FLOAT: {
1053 Register src_reg = O7;
1054 int value = c->as_jint_bits();
1055 if (value == 0) {
1056 src_reg = G0;
1057 } else {
1058 __ set(value, O7);
1059 }
1060 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1061 __ stw(src_reg, addr.base(), addr.disp());
1062 break;
1063 }
1064 case T_ADDRESS: {
1065 Register src_reg = O7;
1066 int value = c->as_jint_bits();
1067 if (value == 0) {
1068 src_reg = G0;
1069 } else {
1070 __ set(value, O7);
1071 }
1072 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1073 __ st_ptr(src_reg, addr.base(), addr.disp());
1074 break;
1075 }
1076 case T_OBJECT: {
1077 Register src_reg = O7;
1078 jobject2reg(c->as_jobject(), src_reg);
1079 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1080 __ st_ptr(src_reg, addr.base(), addr.disp());
1081 break;
1082 }
1083 case T_LONG:
1084 case T_DOUBLE: {
1085 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1086
1087 Register tmp = O7;
1088 int value_lo = c->as_jint_lo_bits();
1089 if (value_lo == 0) {
1090 tmp = G0;
1091 } else {
1092 __ set(value_lo, O7);
1093 }
1094 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1095 int value_hi = c->as_jint_hi_bits();
1096 if (value_hi == 0) {
1097 tmp = G0;
1098 } else {
1099 __ set(value_hi, O7);
1100 }
1101 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1102 break;
1103 }
1104 default:
1105 Unimplemented();
1106 }
1107 }
1108
1109
1110 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
1111 LIR_Const* c = src->as_constant_ptr();
1112 LIR_Address* addr = dest->as_address_ptr();
1113 Register base = addr->base()->as_pointer_register();
1114 int offset = -1;
1115
1116 switch (c->type()) {
1117 case T_INT:
1118 case T_FLOAT:
1119 case T_ADDRESS: {
1120 LIR_Opr tmp = FrameMap::O7_opr;
1121 int value = c->as_jint_bits();
1122 if (value == 0) {
1123 tmp = FrameMap::G0_opr;
1124 } else if (Assembler::is_simm13(value)) {
1125 __ set(value, O7);
1126 }
1127 if (addr->index()->is_valid()) {
1128 assert(addr->disp() == 0, "must be zero");
1129 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1130 } else {
1131 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1132 offset = store(tmp, base, addr->disp(), type, wide, false);
1133 }
1134 break;
1135 }
1136 case T_LONG:
1137 case T_DOUBLE: {
1138 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1139 assert(Assembler::is_simm13(addr->disp()) &&
1140 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1141
1142 LIR_Opr tmp = FrameMap::O7_opr;
1143 int value_lo = c->as_jint_lo_bits();
1144 if (value_lo == 0) {
1145 tmp = FrameMap::G0_opr;
1146 } else {
1147 __ set(value_lo, O7);
1148 }
1149 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
1150 int value_hi = c->as_jint_hi_bits();
1151 if (value_hi == 0) {
1152 tmp = FrameMap::G0_opr;
1153 } else {
1154 __ set(value_hi, O7);
1155 }
1156 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
1157 break;
1158 }
1159 case T_OBJECT: {
1160 jobject obj = c->as_jobject();
1161 LIR_Opr tmp;
1162 if (obj == NULL) {
1163 tmp = FrameMap::G0_opr;
1164 } else {
1165 tmp = FrameMap::O7_opr;
1166 jobject2reg(c->as_jobject(), O7);
1167 }
1168 // handle either reg+reg or reg+disp address
1169 if (addr->index()->is_valid()) {
1170 assert(addr->disp() == 0, "must be zero");
1171 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
1172 } else {
1173 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1174 offset = store(tmp, base, addr->disp(), type, wide, false);
1175 }
1176
1177 break;
1178 }
1179 default:
1180 Unimplemented();
1181 }
1182 if (info != NULL) {
1183 assert(offset != -1, "offset should've been set");
1184 add_debug_info_for_null_check(offset, info);
1185 }
1186 }
1187
1188
1189 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1190 LIR_Const* c = src->as_constant_ptr();
1191 LIR_Opr to_reg = dest;
1192
1193 switch (c->type()) {
1194 case T_INT:
1195 case T_ADDRESS:
1196 {
1197 jint con = c->as_jint();
1198 if (to_reg->is_single_cpu()) {
1199 assert(patch_code == lir_patch_none, "no patching handled here");
1200 __ set(con, to_reg->as_register());
1201 } else {
1202 ShouldNotReachHere();
1203 assert(to_reg->is_single_fpu(), "wrong register kind");
1204
1205 __ set(con, O7);
1206 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1207 __ st(O7, temp_slot);
1208 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1209 }
1210 }
1211 break;
1212
1213 case T_LONG:
1214 {
1215 jlong con = c->as_jlong();
1216
1217 if (to_reg->is_double_cpu()) {
1218 #ifdef _LP64
1219 __ set(con, to_reg->as_register_lo());
1220 #else
1221 __ set(low(con), to_reg->as_register_lo());
1222 __ set(high(con), to_reg->as_register_hi());
1223 #endif
1224 #ifdef _LP64
1225 } else if (to_reg->is_single_cpu()) {
1226 __ set(con, to_reg->as_register());
1227 #endif
1228 } else {
1229 ShouldNotReachHere();
1230 assert(to_reg->is_double_fpu(), "wrong register kind");
1231 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1232 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1233 __ set(low(con), O7);
1234 __ st(O7, temp_slot_lo);
1235 __ set(high(con), O7);
1236 __ st(O7, temp_slot_hi);
1237 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1238 }
1239 }
1240 break;
1241
1242 case T_OBJECT:
1243 {
1244 if (patch_code == lir_patch_none) {
1245 jobject2reg(c->as_jobject(), to_reg->as_register());
1246 } else {
1247 jobject2reg_with_patching(to_reg->as_register(), info);
1248 }
1249 }
1250 break;
1251
1252 case T_METADATA:
1253 {
1254 if (patch_code == lir_patch_none) {
1255 metadata2reg(c->as_metadata(), to_reg->as_register());
1256 } else {
1257 klass2reg_with_patching(to_reg->as_register(), info);
1258 }
1259 }
1260 break;
1261
1262 case T_FLOAT:
1263 {
1264 address const_addr = __ float_constant(c->as_jfloat());
1265 if (const_addr == NULL) {
1266 bailout("const section overflow");
1267 break;
1268 }
1269 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1270 AddressLiteral const_addrlit(const_addr, rspec);
1271 if (to_reg->is_single_fpu()) {
1272 __ patchable_sethi(const_addrlit, O7);
1273 __ relocate(rspec);
1274 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1275
1276 } else {
1277 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1278
1279 __ set(const_addrlit, O7);
1280 __ ld(O7, 0, to_reg->as_register());
1281 }
1282 }
1283 break;
1284
1285 case T_DOUBLE:
1286 {
1287 address const_addr = __ double_constant(c->as_jdouble());
1288 if (const_addr == NULL) {
1289 bailout("const section overflow");
1290 break;
1291 }
1292 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1293
1294 if (to_reg->is_double_fpu()) {
1295 AddressLiteral const_addrlit(const_addr, rspec);
1296 __ patchable_sethi(const_addrlit, O7);
1297 __ relocate(rspec);
1298 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1299 } else {
1300 assert(to_reg->is_double_cpu(), "Must be a long register.");
1301 #ifdef _LP64
1302 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1303 #else
1304 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1305 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1306 #endif
1307 }
1308
1309 }
1310 break;
1311
1312 default:
1313 ShouldNotReachHere();
1314 }
1315 }
1316
1317 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1318 Register reg = addr->base()->as_pointer_register();
1319 LIR_Opr index = addr->index();
1320 if (index->is_illegal()) {
1321 return Address(reg, addr->disp());
1322 } else {
1323 assert (addr->disp() == 0, "unsupported address mode");
1324 return Address(reg, index->as_pointer_register());
1325 }
1326 }
1327
1328
1329 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1330 switch (type) {
1331 case T_INT:
1332 case T_FLOAT: {
1333 Register tmp = O7;
1334 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1335 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1336 __ lduw(from.base(), from.disp(), tmp);
1337 __ stw(tmp, to.base(), to.disp());
1338 break;
1339 }
1340 case T_OBJECT: {
1341 Register tmp = O7;
1342 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1343 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1344 __ ld_ptr(from.base(), from.disp(), tmp);
1345 __ st_ptr(tmp, to.base(), to.disp());
1346 break;
1347 }
1348 case T_LONG:
1349 case T_DOUBLE: {
1350 Register tmp = O7;
1351 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1352 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1353 __ lduw(from.base(), from.disp(), tmp);
1354 __ stw(tmp, to.base(), to.disp());
1355 __ lduw(from.base(), from.disp() + 4, tmp);
1356 __ stw(tmp, to.base(), to.disp() + 4);
1357 break;
1358 }
1359
1360 default:
1361 ShouldNotReachHere();
1362 }
1363 }
1364
1365
1366 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1367 Address base = as_Address(addr);
1368 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1369 }
1370
1371
1372 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1373 Address base = as_Address(addr);
1374 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1375 }
1376
1377
1378 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1379 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1380
1381 assert(type != T_METADATA, "load of metadata ptr not supported");
1382 LIR_Address* addr = src_opr->as_address_ptr();
1383 LIR_Opr to_reg = dest;
1384
1385 Register src = addr->base()->as_pointer_register();
1386 Register disp_reg = noreg;
1387 int disp_value = addr->disp();
1388 bool needs_patching = (patch_code != lir_patch_none);
1389
1390 if (addr->base()->type() == T_OBJECT) {
1391 __ verify_oop(src);
1392 }
1393
1394 PatchingStub* patch = NULL;
1395 if (needs_patching) {
1396 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1397 assert(!to_reg->is_double_cpu() ||
1398 patch_code == lir_patch_none ||
1399 patch_code == lir_patch_normal, "patching doesn't match register");
1400 }
1401
1402 if (addr->index()->is_illegal()) {
1403 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1404 if (needs_patching) {
1405 __ patchable_set(0, O7);
1406 } else {
1407 __ set(disp_value, O7);
1408 }
1409 disp_reg = O7;
1410 }
1411 } else if (unaligned || PatchALot) {
1412 __ add(src, addr->index()->as_register(), O7);
1413 src = O7;
1414 } else {
1415 disp_reg = addr->index()->as_pointer_register();
1416 assert(disp_value == 0, "can't handle 3 operand addresses");
1417 }
1418
1419 // remember the offset of the load. The patching_epilog must be done
1420 // before the call to add_debug_info, otherwise the PcDescs don't get
1421 // entered in increasing order.
1422 int offset = code_offset();
1423
1424 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1425 if (disp_reg == noreg) {
1426 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1427 } else {
1428 assert(!unaligned, "can't handle this");
1429 offset = load(src, disp_reg, to_reg, type, wide);
1430 }
1431
1432 if (patch != NULL) {
1433 patching_epilog(patch, patch_code, src, info);
1434 }
1435 if (info != NULL) add_debug_info_for_null_check(offset, info);
1436 }
1437
1438
1439 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1440 Address addr;
1441 if (src->is_single_word()) {
1442 addr = frame_map()->address_for_slot(src->single_stack_ix());
1443 } else if (src->is_double_word()) {
1444 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1445 }
1446
1447 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1448 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1449 }
1450
1451
1452 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1453 Address addr;
1454 if (dest->is_single_word()) {
1455 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1456 } else if (dest->is_double_word()) {
1457 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1458 }
1459 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1460 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1461 }
1462
1463
1464 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1465 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1466 if (from_reg->is_double_fpu()) {
1467 // double to double moves
1468 assert(to_reg->is_double_fpu(), "should match");
1469 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1470 } else {
1471 // float to float moves
1472 assert(to_reg->is_single_fpu(), "should match");
1473 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1474 }
1475 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1476 if (from_reg->is_double_cpu()) {
1477 #ifdef _LP64
1478 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1479 #else
1480 assert(to_reg->is_double_cpu() &&
1481 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1482 from_reg->as_register_lo() != to_reg->as_register_hi(),
1483 "should both be long and not overlap");
1484 // long to long moves
1485 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1486 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1487 #endif
1488 #ifdef _LP64
1489 } else if (to_reg->is_double_cpu()) {
1490 // int to int moves
1491 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1492 #endif
1493 } else {
1494 // int to int moves
1495 __ mov(from_reg->as_register(), to_reg->as_register());
1496 }
1497 } else {
1498 ShouldNotReachHere();
1499 }
1500 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1501 __ verify_oop(to_reg->as_register());
1502 }
1503 }
1504
1505
1506 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1507 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1508 bool wide, bool unaligned) {
1509 assert(type != T_METADATA, "store of metadata ptr not supported");
1510 LIR_Address* addr = dest->as_address_ptr();
1511
1512 Register src = addr->base()->as_pointer_register();
1513 Register disp_reg = noreg;
1514 int disp_value = addr->disp();
1515 bool needs_patching = (patch_code != lir_patch_none);
1516
1517 if (addr->base()->is_oop_register()) {
1518 __ verify_oop(src);
1519 }
1520
1521 PatchingStub* patch = NULL;
1522 if (needs_patching) {
1523 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1524 assert(!from_reg->is_double_cpu() ||
1525 patch_code == lir_patch_none ||
1526 patch_code == lir_patch_normal, "patching doesn't match register");
1527 }
1528
1529 if (addr->index()->is_illegal()) {
1530 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1531 if (needs_patching) {
1532 __ patchable_set(0, O7);
1533 } else {
1534 __ set(disp_value, O7);
1535 }
1536 disp_reg = O7;
1537 }
1538 } else if (unaligned || PatchALot) {
1539 __ add(src, addr->index()->as_register(), O7);
1540 src = O7;
1541 } else {
1542 disp_reg = addr->index()->as_pointer_register();
1543 assert(disp_value == 0, "can't handle 3 operand addresses");
1544 }
1545
1546 // remember the offset of the store. The patching_epilog must be done
1547 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1548 // entered in increasing order.
1549 int offset;
1550
1551 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1552 if (disp_reg == noreg) {
1553 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1554 } else {
1555 assert(!unaligned, "can't handle this");
1556 offset = store(from_reg, src, disp_reg, type, wide);
1557 }
1558
1559 if (patch != NULL) {
1560 patching_epilog(patch, patch_code, src, info);
1561 }
1562
1563 if (info != NULL) add_debug_info_for_null_check(offset, info);
1564 }
1565
1566
1567 void LIR_Assembler::return_op(LIR_Opr result) {
1568 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1569 __ reserved_stack_check();
1570 }
1571 // the poll may need a register so just pick one that isn't the return register
1572 #if defined(TIERED) && !defined(_LP64)
1573 if (result->type_field() == LIR_OprDesc::long_type) {
1574 // Must move the result to G1
1575 // Must leave proper result in O0,O1 and G1 (TIERED only)
1576 __ sllx(I0, 32, G1); // Shift bits into high G1
1577 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1578 __ or3 (I1, G1, G1); // OR 64 bits into G1
1579 #ifdef ASSERT
1580 // mangle it so any problems will show up
1581 __ set(0xdeadbeef, I0);
1582 __ set(0xdeadbeef, I1);
1583 #endif
1584 }
1585 #endif // TIERED
1586 __ set((intptr_t)os::get_polling_page(), L0);
1587 __ relocate(relocInfo::poll_return_type);
1588 __ ld_ptr(L0, 0, G0);
1589 __ ret();
1590 __ delayed()->restore();
1591 }
1592
1593
1594 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1595 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1596 if (info != NULL) {
1597 add_debug_info_for_branch(info);
1598 }
1599 int offset = __ offset();
1600 __ relocate(relocInfo::poll_type);
1601 __ ld_ptr(tmp->as_register(), 0, G0);
1602 return offset;
1603 }
1604
1605
1606 void LIR_Assembler::emit_static_call_stub() {
1607 address call_pc = __ pc();
1608 address stub = __ start_a_stub(call_stub_size);
1609 if (stub == NULL) {
1610 bailout("static call stub overflow");
1611 return;
1612 }
1613
1614 int start = __ offset();
1615 __ relocate(static_stub_Relocation::spec(call_pc));
1616
1617 __ set_metadata(NULL, G5);
1618 // must be set to -1 at code generation time
1619 AddressLiteral addrlit(-1);
1620 __ jump_to(addrlit, G3);
1621 __ delayed()->nop();
1622
1623 assert(__ offset() - start <= call_stub_size, "stub too big");
1624 __ end_a_stub();
1625 }
1626
1627
1628 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1629 if (opr1->is_single_fpu()) {
1630 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1631 } else if (opr1->is_double_fpu()) {
1632 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1633 } else if (opr1->is_single_cpu()) {
1634 if (opr2->is_constant()) {
1635 switch (opr2->as_constant_ptr()->type()) {
1636 case T_INT:
1637 { jint con = opr2->as_constant_ptr()->as_jint();
1638 if (Assembler::is_simm13(con)) {
1639 __ cmp(opr1->as_register(), con);
1640 } else {
1641 __ set(con, O7);
1642 __ cmp(opr1->as_register(), O7);
1643 }
1644 }
1645 break;
1646
1647 case T_OBJECT:
1648 // there are only equal/notequal comparisions on objects
1649 { jobject con = opr2->as_constant_ptr()->as_jobject();
1650 if (con == NULL) {
1651 __ cmp(opr1->as_register(), 0);
1652 } else {
1653 jobject2reg(con, O7);
1654 __ cmp(opr1->as_register(), O7);
1655 }
1656 }
1657 break;
1658
1659 default:
1660 ShouldNotReachHere();
1661 break;
1662 }
1663 } else {
1664 if (opr2->is_address()) {
1665 LIR_Address * addr = opr2->as_address_ptr();
1666 BasicType type = addr->type();
1667 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1668 else __ ld(as_Address(addr), O7);
1669 __ cmp(opr1->as_register(), O7);
1670 } else {
1671 __ cmp(opr1->as_register(), opr2->as_register());
1672 }
1673 }
1674 } else if (opr1->is_double_cpu()) {
1675 Register xlo = opr1->as_register_lo();
1676 Register xhi = opr1->as_register_hi();
1677 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1678 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1679 #ifdef _LP64
1680 __ orcc(xhi, G0, G0);
1681 #else
1682 __ orcc(xhi, xlo, G0);
1683 #endif
1684 } else if (opr2->is_register()) {
1685 Register ylo = opr2->as_register_lo();
1686 Register yhi = opr2->as_register_hi();
1687 #ifdef _LP64
1688 __ cmp(xlo, ylo);
1689 #else
1690 __ subcc(xlo, ylo, xlo);
1691 __ subccc(xhi, yhi, xhi);
1692 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1693 __ orcc(xhi, xlo, G0);
1694 }
1695 #endif
1696 } else {
1697 ShouldNotReachHere();
1698 }
1699 } else if (opr1->is_address()) {
1700 LIR_Address * addr = opr1->as_address_ptr();
1701 BasicType type = addr->type();
1702 assert (opr2->is_constant(), "Checking");
1703 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1704 else __ ld(as_Address(addr), O7);
1705 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1706 } else {
1707 ShouldNotReachHere();
1708 }
1709 }
1710
1711
1712 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1713 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1714 bool is_unordered_less = (code == lir_ucmp_fd2i);
1715 if (left->is_single_fpu()) {
1716 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1717 } else if (left->is_double_fpu()) {
1718 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1719 } else {
1720 ShouldNotReachHere();
1721 }
1722 } else if (code == lir_cmp_l2i) {
1723 #ifdef _LP64
1724 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register());
1725 #else
1726 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1727 right->as_register_hi(), right->as_register_lo(),
1728 dst->as_register());
1729 #endif
1730 } else {
1731 ShouldNotReachHere();
1732 }
1733 }
1734
1735
1736 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1737 Assembler::Condition acond;
1738 switch (condition) {
1739 case lir_cond_equal: acond = Assembler::equal; break;
1740 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1741 case lir_cond_less: acond = Assembler::less; break;
1742 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1743 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1744 case lir_cond_greater: acond = Assembler::greater; break;
1745 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1746 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1747 default: ShouldNotReachHere();
1748 };
1749
1750 if (opr1->is_constant() && opr1->type() == T_INT) {
1751 Register dest = result->as_register();
1752 // load up first part of constant before branch
1753 // and do the rest in the delay slot.
1754 if (!Assembler::is_simm13(opr1->as_jint())) {
1755 __ sethi(opr1->as_jint(), dest);
1756 }
1757 } else if (opr1->is_constant()) {
1758 const2reg(opr1, result, lir_patch_none, NULL);
1759 } else if (opr1->is_register()) {
1760 reg2reg(opr1, result);
1761 } else if (opr1->is_stack()) {
1762 stack2reg(opr1, result, result->type());
1763 } else {
1764 ShouldNotReachHere();
1765 }
1766 Label skip;
1767 #ifdef _LP64
1768 if (type == T_INT) {
1769 __ br(acond, false, Assembler::pt, skip);
1770 } else
1771 #endif
1772 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit
1773 if (opr1->is_constant() && opr1->type() == T_INT) {
1774 Register dest = result->as_register();
1775 if (Assembler::is_simm13(opr1->as_jint())) {
1776 __ delayed()->or3(G0, opr1->as_jint(), dest);
1777 } else {
1778 // the sethi has been done above, so just put in the low 10 bits
1779 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1780 }
1781 } else {
1782 // can't do anything useful in the delay slot
1783 __ delayed()->nop();
1784 }
1785 if (opr2->is_constant()) {
1786 const2reg(opr2, result, lir_patch_none, NULL);
1787 } else if (opr2->is_register()) {
1788 reg2reg(opr2, result);
1789 } else if (opr2->is_stack()) {
1790 stack2reg(opr2, result, result->type());
1791 } else {
1792 ShouldNotReachHere();
1793 }
1794 __ bind(skip);
1795 }
1796
1797
1798 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1799 assert(info == NULL, "unused on this code path");
1800 assert(left->is_register(), "wrong items state");
1801 assert(dest->is_register(), "wrong items state");
1802
1803 if (right->is_register()) {
1804 if (dest->is_float_kind()) {
1805
1806 FloatRegister lreg, rreg, res;
1807 FloatRegisterImpl::Width w;
1808 if (right->is_single_fpu()) {
1809 w = FloatRegisterImpl::S;
1810 lreg = left->as_float_reg();
1811 rreg = right->as_float_reg();
1812 res = dest->as_float_reg();
1813 } else {
1814 w = FloatRegisterImpl::D;
1815 lreg = left->as_double_reg();
1816 rreg = right->as_double_reg();
1817 res = dest->as_double_reg();
1818 }
1819
1820 switch (code) {
1821 case lir_add: __ fadd(w, lreg, rreg, res); break;
1822 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1823 case lir_mul: // fall through
1824 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1825 case lir_div: // fall through
1826 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1827 default: ShouldNotReachHere();
1828 }
1829
1830 } else if (dest->is_double_cpu()) {
1831 #ifdef _LP64
1832 Register dst_lo = dest->as_register_lo();
1833 Register op1_lo = left->as_pointer_register();
1834 Register op2_lo = right->as_pointer_register();
1835
1836 switch (code) {
1837 case lir_add:
1838 __ add(op1_lo, op2_lo, dst_lo);
1839 break;
1840
1841 case lir_sub:
1842 __ sub(op1_lo, op2_lo, dst_lo);
1843 break;
1844
1845 default: ShouldNotReachHere();
1846 }
1847 #else
1848 Register op1_lo = left->as_register_lo();
1849 Register op1_hi = left->as_register_hi();
1850 Register op2_lo = right->as_register_lo();
1851 Register op2_hi = right->as_register_hi();
1852 Register dst_lo = dest->as_register_lo();
1853 Register dst_hi = dest->as_register_hi();
1854
1855 switch (code) {
1856 case lir_add:
1857 __ addcc(op1_lo, op2_lo, dst_lo);
1858 __ addc (op1_hi, op2_hi, dst_hi);
1859 break;
1860
1861 case lir_sub:
1862 __ subcc(op1_lo, op2_lo, dst_lo);
1863 __ subc (op1_hi, op2_hi, dst_hi);
1864 break;
1865
1866 default: ShouldNotReachHere();
1867 }
1868 #endif
1869 } else {
1870 assert (right->is_single_cpu(), "Just Checking");
1871
1872 Register lreg = left->as_register();
1873 Register res = dest->as_register();
1874 Register rreg = right->as_register();
1875 switch (code) {
1876 case lir_add: __ add (lreg, rreg, res); break;
1877 case lir_sub: __ sub (lreg, rreg, res); break;
1878 case lir_mul: __ mulx (lreg, rreg, res); break;
1879 default: ShouldNotReachHere();
1880 }
1881 }
1882 } else {
1883 assert (right->is_constant(), "must be constant");
1884
1885 if (dest->is_single_cpu()) {
1886 Register lreg = left->as_register();
1887 Register res = dest->as_register();
1888 int simm13 = right->as_constant_ptr()->as_jint();
1889
1890 switch (code) {
1891 case lir_add: __ add (lreg, simm13, res); break;
1892 case lir_sub: __ sub (lreg, simm13, res); break;
1893 case lir_mul: __ mulx (lreg, simm13, res); break;
1894 default: ShouldNotReachHere();
1895 }
1896 } else {
1897 Register lreg = left->as_pointer_register();
1898 Register res = dest->as_register_lo();
1899 long con = right->as_constant_ptr()->as_jlong();
1900 assert(Assembler::is_simm13(con), "must be simm13");
1901
1902 switch (code) {
1903 case lir_add: __ add (lreg, (int)con, res); break;
1904 case lir_sub: __ sub (lreg, (int)con, res); break;
1905 case lir_mul: __ mulx (lreg, (int)con, res); break;
1906 default: ShouldNotReachHere();
1907 }
1908 }
1909 }
1910 }
1911
1912
1913 void LIR_Assembler::fpop() {
1914 // do nothing
1915 }
1916
1917
1918 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1919 switch (code) {
1920 case lir_sin:
1921 case lir_tan:
1922 case lir_cos: {
1923 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1924 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1925 break;
1926 }
1927 case lir_sqrt: {
1928 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1929 FloatRegister src_reg = value->as_double_reg();
1930 FloatRegister dst_reg = dest->as_double_reg();
1931 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1932 break;
1933 }
1934 case lir_abs: {
1935 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1936 FloatRegister src_reg = value->as_double_reg();
1937 FloatRegister dst_reg = dest->as_double_reg();
1938 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1939 break;
1940 }
1941 default: {
1942 ShouldNotReachHere();
1943 break;
1944 }
1945 }
1946 }
1947
1948
1949 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1950 if (right->is_constant()) {
1951 if (dest->is_single_cpu()) {
1952 int simm13 = right->as_constant_ptr()->as_jint();
1953 switch (code) {
1954 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1955 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1956 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1957 default: ShouldNotReachHere();
1958 }
1959 } else {
1960 long c = right->as_constant_ptr()->as_jlong();
1961 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1962 int simm13 = (int)c;
1963 switch (code) {
1964 case lir_logic_and:
1965 #ifndef _LP64
1966 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1967 #endif
1968 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1969 break;
1970
1971 case lir_logic_or:
1972 #ifndef _LP64
1973 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1974 #endif
1975 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1976 break;
1977
1978 case lir_logic_xor:
1979 #ifndef _LP64
1980 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1981 #endif
1982 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1983 break;
1984
1985 default: ShouldNotReachHere();
1986 }
1987 }
1988 } else {
1989 assert(right->is_register(), "right should be in register");
1990
1991 if (dest->is_single_cpu()) {
1992 switch (code) {
1993 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1994 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1995 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1996 default: ShouldNotReachHere();
1997 }
1998 } else {
1999 #ifdef _LP64
2000 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
2001 left->as_register_lo();
2002 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
2003 right->as_register_lo();
2004
2005 switch (code) {
2006 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
2007 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2008 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2009 default: ShouldNotReachHere();
2010 }
2011 #else
2012 switch (code) {
2013 case lir_logic_and:
2014 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2015 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2016 break;
2017
2018 case lir_logic_or:
2019 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2020 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2021 break;
2022
2023 case lir_logic_xor:
2024 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2025 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2026 break;
2027
2028 default: ShouldNotReachHere();
2029 }
2030 #endif
2031 }
2032 }
2033 }
2034
2035
2036 int LIR_Assembler::shift_amount(BasicType t) {
2037 int elem_size = type2aelembytes(t);
2038 switch (elem_size) {
2039 case 1 : return 0;
2040 case 2 : return 1;
2041 case 4 : return 2;
2042 case 8 : return 3;
2043 }
2044 ShouldNotReachHere();
2045 return -1;
2046 }
2047
2048
2049 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2050 assert(exceptionOop->as_register() == Oexception, "should match");
2051 assert(exceptionPC->as_register() == Oissuing_pc, "should match");
2052
2053 info->add_register_oop(exceptionOop);
2054
2055 // reuse the debug info from the safepoint poll for the throw op itself
2056 address pc_for_athrow = __ pc();
2057 int pc_for_athrow_offset = __ offset();
2058 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2059 __ set(pc_for_athrow, Oissuing_pc, rspec);
2060 add_call_info(pc_for_athrow_offset, info); // for exception handler
2061
2062 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2063 __ delayed()->nop();
2064 }
2065
2066
2067 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2068 assert(exceptionOop->as_register() == Oexception, "should match");
2069
2070 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry);
2071 __ delayed()->nop();
2072 }
2073
2074 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2075 Register src = op->src()->as_register();
2076 Register dst = op->dst()->as_register();
2077 Register src_pos = op->src_pos()->as_register();
2078 Register dst_pos = op->dst_pos()->as_register();
2079 Register length = op->length()->as_register();
2080 Register tmp = op->tmp()->as_register();
2081 Register tmp2 = O7;
2082
2083 int flags = op->flags();
2084 ciArrayKlass* default_type = op->expected_type();
2085 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2086 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2087
2088 #ifdef _LP64
2089 // higher 32bits must be null
2090 __ sra(dst_pos, 0, dst_pos);
2091 __ sra(src_pos, 0, src_pos);
2092 __ sra(length, 0, length);
2093 #endif
2094
2095 // set up the arraycopy stub information
2096 ArrayCopyStub* stub = op->stub();
2097
2098 // always do stub if no type information is available. it's ok if
2099 // the known type isn't loaded since the code sanity checks
2100 // in debug mode and the type isn't required when we know the exact type
2101 // also check that the type is an array type.
2102 if (op->expected_type() == NULL) {
2103 __ mov(src, O0);
2104 __ mov(src_pos, O1);
2105 __ mov(dst, O2);
2106 __ mov(dst_pos, O3);
2107 __ mov(length, O4);
2108 address copyfunc_addr = StubRoutines::generic_arraycopy();
2109
2110 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
2111 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2112 } else {
2113 #ifndef PRODUCT
2114 if (PrintC1Statistics) {
2115 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
2116 __ inc_counter(counter, G1, G3);
2117 }
2118 #endif
2119 __ call_VM_leaf(tmp, copyfunc_addr);
2120 }
2121
2122 if (copyfunc_addr != NULL) {
2123 __ xor3(O0, -1, tmp);
2124 __ sub(length, tmp, length);
2125 __ add(src_pos, tmp, src_pos);
2126 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2127 __ delayed()->add(dst_pos, tmp, dst_pos);
2128 } else {
2129 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry());
2130 __ delayed()->nop();
2131 }
2132 __ bind(*stub->continuation());
2133 return;
2134 }
2135
2136 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2137
2138 // make sure src and dst are non-null and load array length
2139 if (flags & LIR_OpArrayCopy::src_null_check) {
2140 __ tst(src);
2141 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2142 __ delayed()->nop();
2143 }
2144
2145 if (flags & LIR_OpArrayCopy::dst_null_check) {
2146 __ tst(dst);
2147 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
2148 __ delayed()->nop();
2149 }
2150
2151 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2152 // test src_pos register
2153 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry());
2154 __ delayed()->nop();
2155 }
2156
2157 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2158 // test dst_pos register
2159 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry());
2160 __ delayed()->nop();
2161 }
2162
2163 if (flags & LIR_OpArrayCopy::length_positive_check) {
2164 // make sure length isn't negative
2165 __ cmp_zero_and_br(Assembler::less, length, *stub->entry());
2166 __ delayed()->nop();
2167 }
2168
2169 if (flags & LIR_OpArrayCopy::src_range_check) {
2170 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2171 __ add(length, src_pos, tmp);
2172 __ cmp(tmp2, tmp);
2173 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2174 __ delayed()->nop();
2175 }
2176
2177 if (flags & LIR_OpArrayCopy::dst_range_check) {
2178 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2179 __ add(length, dst_pos, tmp);
2180 __ cmp(tmp2, tmp);
2181 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2182 __ delayed()->nop();
2183 }
2184
2185 int shift = shift_amount(basic_type);
2186
2187 if (flags & LIR_OpArrayCopy::type_check) {
2188 // We don't know the array types are compatible
2189 if (basic_type != T_OBJECT) {
2190 // Simple test for basic type arrays
2191 if (UseCompressedClassPointers) {
2192 // We don't need decode because we just need to compare
2193 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
2194 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2195 __ cmp(tmp, tmp2);
2196 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2197 } else {
2198 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2199 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2200 __ cmp(tmp, tmp2);
2201 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2202 }
2203 __ delayed()->nop();
2204 } else {
2205 // For object arrays, if src is a sub class of dst then we can
2206 // safely do the copy.
2207 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2208
2209 Label cont, slow;
2210 assert_different_registers(tmp, tmp2, G3, G1);
2211
2212 __ load_klass(src, G3);
2213 __ load_klass(dst, G1);
2214
2215 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2216
2217 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2218 __ delayed()->nop();
2219
2220 __ cmp(G3, 0);
2221 if (copyfunc_addr != NULL) { // use stub if available
2222 // src is not a sub class of dst so we have to do a
2223 // per-element check.
2224 __ br(Assembler::notEqual, false, Assembler::pt, cont);
2225 __ delayed()->nop();
2226
2227 __ bind(slow);
2228
2229 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2230 if ((flags & mask) != mask) {
2231 // Check that at least both of them object arrays.
2232 assert(flags & mask, "one of the two should be known to be an object array");
2233
2234 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2235 __ load_klass(src, tmp);
2236 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2237 __ load_klass(dst, tmp);
2238 }
2239 int lh_offset = in_bytes(Klass::layout_helper_offset());
2240
2241 __ lduw(tmp, lh_offset, tmp2);
2242
2243 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2244 __ set(objArray_lh, tmp);
2245 __ cmp(tmp, tmp2);
2246 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2247 __ delayed()->nop();
2248 }
2249
2250 Register src_ptr = O0;
2251 Register dst_ptr = O1;
2252 Register len = O2;
2253 Register chk_off = O3;
2254 Register super_k = O4;
2255
2256 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2257 if (shift == 0) {
2258 __ add(src_ptr, src_pos, src_ptr);
2259 } else {
2260 __ sll(src_pos, shift, tmp);
2261 __ add(src_ptr, tmp, src_ptr);
2262 }
2263
2264 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2265 if (shift == 0) {
2266 __ add(dst_ptr, dst_pos, dst_ptr);
2267 } else {
2268 __ sll(dst_pos, shift, tmp);
2269 __ add(dst_ptr, tmp, dst_ptr);
2270 }
2271 __ mov(length, len);
2272 __ load_klass(dst, tmp);
2273
2274 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2275 __ ld_ptr(tmp, ek_offset, super_k);
2276
2277 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2278 __ lduw(super_k, sco_offset, chk_off);
2279
2280 __ call_VM_leaf(tmp, copyfunc_addr);
2281
2282 #ifndef PRODUCT
2283 if (PrintC1Statistics) {
2284 Label failed;
2285 __ br_notnull_short(O0, Assembler::pn, failed);
2286 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3);
2287 __ bind(failed);
2288 }
2289 #endif
2290
2291 __ br_null(O0, false, Assembler::pt, *stub->continuation());
2292 __ delayed()->xor3(O0, -1, tmp);
2293
2294 #ifndef PRODUCT
2295 if (PrintC1Statistics) {
2296 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3);
2297 }
2298 #endif
2299
2300 __ sub(length, tmp, length);
2301 __ add(src_pos, tmp, src_pos);
2302 __ br(Assembler::always, false, Assembler::pt, *stub->entry());
2303 __ delayed()->add(dst_pos, tmp, dst_pos);
2304
2305 __ bind(cont);
2306 } else {
2307 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2308 __ delayed()->nop();
2309 __ bind(cont);
2310 }
2311 }
2312 }
2313
2314 #ifdef ASSERT
2315 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2316 // Sanity check the known type with the incoming class. For the
2317 // primitive case the types must match exactly with src.klass and
2318 // dst.klass each exactly matching the default type. For the
2319 // object array case, if no type check is needed then either the
2320 // dst type is exactly the expected type and the src type is a
2321 // subtype which we can't check or src is the same array as dst
2322 // but not necessarily exactly of type default_type.
2323 Label known_ok, halt;
2324 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2325 if (UseCompressedClassPointers) {
2326 // tmp holds the default type. It currently comes uncompressed after the
2327 // load of a constant, so encode it.
2328 __ encode_klass_not_null(tmp);
2329 // load the raw value of the dst klass, since we will be comparing
2330 // uncompressed values directly.
2331 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2332 if (basic_type != T_OBJECT) {
2333 __ cmp(tmp, tmp2);
2334 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2335 // load the raw value of the src klass.
2336 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
2337 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2338 } else {
2339 __ cmp(tmp, tmp2);
2340 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2341 __ delayed()->cmp(src, dst);
2342 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2343 __ delayed()->nop();
2344 }
2345 } else {
2346 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2347 if (basic_type != T_OBJECT) {
2348 __ cmp(tmp, tmp2);
2349 __ brx(Assembler::notEqual, false, Assembler::pn, halt);
2350 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2351 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok);
2352 } else {
2353 __ cmp(tmp, tmp2);
2354 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2355 __ delayed()->cmp(src, dst);
2356 __ brx(Assembler::equal, false, Assembler::pn, known_ok);
2357 __ delayed()->nop();
2358 }
2359 }
2360 __ bind(halt);
2361 __ stop("incorrect type information in arraycopy");
2362 __ bind(known_ok);
2363 }
2364 #endif
2365
2366 #ifndef PRODUCT
2367 if (PrintC1Statistics) {
2368 address counter = Runtime1::arraycopy_count_address(basic_type);
2369 __ inc_counter(counter, G1, G3);
2370 }
2371 #endif
2372
2373 Register src_ptr = O0;
2374 Register dst_ptr = O1;
2375 Register len = O2;
2376
2377 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2378 if (shift == 0) {
2379 __ add(src_ptr, src_pos, src_ptr);
2380 } else {
2381 __ sll(src_pos, shift, tmp);
2382 __ add(src_ptr, tmp, src_ptr);
2383 }
2384
2385 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2386 if (shift == 0) {
2387 __ add(dst_ptr, dst_pos, dst_ptr);
2388 } else {
2389 __ sll(dst_pos, shift, tmp);
2390 __ add(dst_ptr, tmp, dst_ptr);
2391 }
2392
2393 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2394 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2395 const char *name;
2396 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2397
2398 // arraycopy stubs takes a length in number of elements, so don't scale it.
2399 __ mov(length, len);
2400 __ call_VM_leaf(tmp, entry);
2401
2402 __ bind(*stub->continuation());
2403 }
2404
2405
2406 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2407 if (dest->is_single_cpu()) {
2408 #ifdef _LP64
2409 if (left->type() == T_OBJECT) {
2410 switch (code) {
2411 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2412 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2413 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2414 default: ShouldNotReachHere();
2415 }
2416 } else
2417 #endif
2418 switch (code) {
2419 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2420 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2421 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2422 default: ShouldNotReachHere();
2423 }
2424 } else {
2425 #ifdef _LP64
2426 switch (code) {
2427 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2428 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2429 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2430 default: ShouldNotReachHere();
2431 }
2432 #else
2433 switch (code) {
2434 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2435 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2436 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2437 default: ShouldNotReachHere();
2438 }
2439 #endif
2440 }
2441 }
2442
2443
2444 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2445 #ifdef _LP64
2446 if (left->type() == T_OBJECT) {
2447 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2448 Register l = left->as_register();
2449 Register d = dest->as_register_lo();
2450 switch (code) {
2451 case lir_shl: __ sllx (l, count, d); break;
2452 case lir_shr: __ srax (l, count, d); break;
2453 case lir_ushr: __ srlx (l, count, d); break;
2454 default: ShouldNotReachHere();
2455 }
2456 return;
2457 }
2458 #endif
2459
2460 if (dest->is_single_cpu()) {
2461 count = count & 0x1F; // Java spec
2462 switch (code) {
2463 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2464 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2465 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2466 default: ShouldNotReachHere();
2467 }
2468 } else if (dest->is_double_cpu()) {
2469 count = count & 63; // Java spec
2470 switch (code) {
2471 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2472 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2473 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2474 default: ShouldNotReachHere();
2475 }
2476 } else {
2477 ShouldNotReachHere();
2478 }
2479 }
2480
2481
2482 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2483 assert(op->tmp1()->as_register() == G1 &&
2484 op->tmp2()->as_register() == G3 &&
2485 op->tmp3()->as_register() == G4 &&
2486 op->obj()->as_register() == O0 &&
2487 op->klass()->as_register() == G5, "must be");
2488 if (op->init_check()) {
2489 __ ldub(op->klass()->as_register(),
2490 in_bytes(InstanceKlass::init_state_offset()),
2491 op->tmp1()->as_register());
2492 add_debug_info_for_null_check_here(op->stub()->info());
2493 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2494 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2495 __ delayed()->nop();
2496 }
2497 __ allocate_object(op->obj()->as_register(),
2498 op->tmp1()->as_register(),
2499 op->tmp2()->as_register(),
2500 op->tmp3()->as_register(),
2501 op->header_size(),
2502 op->object_size(),
2503 op->klass()->as_register(),
2504 *op->stub()->entry());
2505 __ bind(*op->stub()->continuation());
2506 __ verify_oop(op->obj()->as_register());
2507 }
2508
2509
2510 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2511 assert(op->tmp1()->as_register() == G1 &&
2512 op->tmp2()->as_register() == G3 &&
2513 op->tmp3()->as_register() == G4 &&
2514 op->tmp4()->as_register() == O1 &&
2515 op->klass()->as_register() == G5, "must be");
2516
2517 LP64_ONLY( __ signx(op->len()->as_register()); )
2518 if (UseSlowPath ||
2519 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2520 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2521 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2522 __ delayed()->nop();
2523 } else {
2524 __ allocate_array(op->obj()->as_register(),
2525 op->len()->as_register(),
2526 op->tmp1()->as_register(),
2527 op->tmp2()->as_register(),
2528 op->tmp3()->as_register(),
2529 arrayOopDesc::header_size(op->type()),
2530 type2aelembytes(op->type()),
2531 op->klass()->as_register(),
2532 *op->stub()->entry());
2533 }
2534 __ bind(*op->stub()->continuation());
2535 }
2536
2537
2538 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2539 ciMethodData *md, ciProfileData *data,
2540 Register recv, Register tmp1, Label* update_done) {
2541 uint i;
2542 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2543 Label next_test;
2544 // See if the receiver is receiver[n].
2545 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2546 mdo_offset_bias);
2547 __ ld_ptr(receiver_addr, tmp1);
2548 __ verify_klass_ptr(tmp1);
2549 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test);
2550 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2551 mdo_offset_bias);
2552 __ ld_ptr(data_addr, tmp1);
2553 __ add(tmp1, DataLayout::counter_increment, tmp1);
2554 __ st_ptr(tmp1, data_addr);
2555 __ ba(*update_done);
2556 __ delayed()->nop();
2557 __ bind(next_test);
2558 }
2559
2560 // Didn't find receiver; find next empty slot and fill it in
2561 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2562 Label next_test;
2563 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
2564 mdo_offset_bias);
2565 __ ld_ptr(recv_addr, tmp1);
2566 __ br_notnull_short(tmp1, Assembler::pt, next_test);
2567 __ st_ptr(recv, recv_addr);
2568 __ set(DataLayout::counter_increment, tmp1);
2569 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
2570 mdo_offset_bias);
2571 __ ba(*update_done);
2572 __ delayed()->nop();
2573 __ bind(next_test);
2574 }
2575 }
2576
2577
2578 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2579 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2580 md = method->method_data_or_null();
2581 assert(md != NULL, "Sanity");
2582 data = md->bci_to_data(bci);
2583 assert(data != NULL, "need data for checkcast");
2584 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2585 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2586 // The offset is large so bias the mdo by the base of the slot so
2587 // that the ld can use simm13s to reference the slots of the data
2588 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2589 }
2590 }
2591
2592 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2593 // we always need a stub for the failure case.
2594 CodeStub* stub = op->stub();
2595 Register obj = op->object()->as_register();
2596 Register k_RInfo = op->tmp1()->as_register();
2597 Register klass_RInfo = op->tmp2()->as_register();
2598 Register dst = op->result_opr()->as_register();
2599 Register Rtmp1 = op->tmp3()->as_register();
2600 ciKlass* k = op->klass();
2601
2602
2603 if (obj == k_RInfo) {
2604 k_RInfo = klass_RInfo;
2605 klass_RInfo = obj;
2606 }
2607
2608 ciMethodData* md;
2609 ciProfileData* data;
2610 int mdo_offset_bias = 0;
2611 if (op->should_profile()) {
2612 ciMethod* method = op->profiled_method();
2613 assert(method != NULL, "Should have method");
2614 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2615
2616 Label not_null;
2617 __ br_notnull_short(obj, Assembler::pn, not_null);
2618 Register mdo = k_RInfo;
2619 Register data_val = Rtmp1;
2620 metadata2reg(md->constant_encoding(), mdo);
2621 if (mdo_offset_bias > 0) {
2622 __ set(mdo_offset_bias, data_val);
2623 __ add(mdo, data_val, mdo);
2624 }
2625 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2626 __ ldub(flags_addr, data_val);
2627 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2628 __ stb(data_val, flags_addr);
2629 __ ba(*obj_is_null);
2630 __ delayed()->nop();
2631 __ bind(not_null);
2632 } else {
2633 __ br_null(obj, false, Assembler::pn, *obj_is_null);
2634 __ delayed()->nop();
2635 }
2636
2637 Label profile_cast_failure, profile_cast_success;
2638 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2639 Label *success_target = op->should_profile() ? &profile_cast_success : success;
2640
2641 // patching may screw with our temporaries on sparc,
2642 // so let's do it before loading the class
2643 if (k->is_loaded()) {
2644 metadata2reg(k->constant_encoding(), k_RInfo);
2645 } else {
2646 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2647 }
2648 assert(obj != k_RInfo, "must be different");
2649
2650 // get object class
2651 // not a safepoint as obj null check happens earlier
2652 __ load_klass(obj, klass_RInfo);
2653 if (op->fast_check()) {
2654 assert_different_registers(klass_RInfo, k_RInfo);
2655 __ cmp(k_RInfo, klass_RInfo);
2656 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target);
2657 __ delayed()->nop();
2658 } else {
2659 bool need_slow_path = true;
2660 if (k->is_loaded()) {
2661 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset()))
2662 need_slow_path = false;
2663 // perform the fast part of the checking logic
2664 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2665 (need_slow_path ? success_target : NULL),
2666 failure_target, NULL,
2667 RegisterOrConstant(k->super_check_offset()));
2668 } else {
2669 // perform the fast part of the checking logic
2670 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target,
2671 failure_target, NULL);
2672 }
2673 if (need_slow_path) {
2674 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2675 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2676 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2677 __ delayed()->nop();
2678 __ cmp(G3, 0);
2679 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2680 __ delayed()->nop();
2681 // Fall through to success case
2682 }
2683 }
2684
2685 if (op->should_profile()) {
2686 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2687 assert_different_registers(obj, mdo, recv, tmp1);
2688 __ bind(profile_cast_success);
2689 metadata2reg(md->constant_encoding(), mdo);
2690 if (mdo_offset_bias > 0) {
2691 __ set(mdo_offset_bias, tmp1);
2692 __ add(mdo, tmp1, mdo);
2693 }
2694 __ load_klass(obj, recv);
2695 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
2696 // Jump over the failure case
2697 __ ba(*success);
2698 __ delayed()->nop();
2699 // Cast failure case
2700 __ bind(profile_cast_failure);
2701 metadata2reg(md->constant_encoding(), mdo);
2702 if (mdo_offset_bias > 0) {
2703 __ set(mdo_offset_bias, tmp1);
2704 __ add(mdo, tmp1, mdo);
2705 }
2706 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2707 __ ld_ptr(data_addr, tmp1);
2708 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2709 __ st_ptr(tmp1, data_addr);
2710 __ ba(*failure);
2711 __ delayed()->nop();
2712 }
2713 __ ba(*success);
2714 __ delayed()->nop();
2715 }
2716
2717 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2718 LIR_Code code = op->code();
2719 if (code == lir_store_check) {
2720 Register value = op->object()->as_register();
2721 Register array = op->array()->as_register();
2722 Register k_RInfo = op->tmp1()->as_register();
2723 Register klass_RInfo = op->tmp2()->as_register();
2724 Register Rtmp1 = op->tmp3()->as_register();
2725
2726 __ verify_oop(value);
2727 CodeStub* stub = op->stub();
2728 // check if it needs to be profiled
2729 ciMethodData* md;
2730 ciProfileData* data;
2731 int mdo_offset_bias = 0;
2732 if (op->should_profile()) {
2733 ciMethod* method = op->profiled_method();
2734 assert(method != NULL, "Should have method");
2735 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2736 }
2737 Label profile_cast_success, profile_cast_failure, done;
2738 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2739 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2740
2741 if (op->should_profile()) {
2742 Label not_null;
2743 __ br_notnull_short(value, Assembler::pn, not_null);
2744 Register mdo = k_RInfo;
2745 Register data_val = Rtmp1;
2746 metadata2reg(md->constant_encoding(), mdo);
2747 if (mdo_offset_bias > 0) {
2748 __ set(mdo_offset_bias, data_val);
2749 __ add(mdo, data_val, mdo);
2750 }
2751 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2752 __ ldub(flags_addr, data_val);
2753 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2754 __ stb(data_val, flags_addr);
2755 __ ba_short(done);
2756 __ bind(not_null);
2757 } else {
2758 __ br_null_short(value, Assembler::pn, done);
2759 }
2760 add_debug_info_for_null_check_here(op->info_for_exception());
2761 __ load_klass(array, k_RInfo);
2762 __ load_klass(value, klass_RInfo);
2763
2764 // get instance klass
2765 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo);
2766 // perform the fast part of the checking logic
2767 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
2768
2769 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2770 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2771 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2772 __ delayed()->nop();
2773 __ cmp(G3, 0);
2774 __ br(Assembler::equal, false, Assembler::pn, *failure_target);
2775 __ delayed()->nop();
2776 // fall through to the success case
2777
2778 if (op->should_profile()) {
2779 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2780 assert_different_registers(value, mdo, recv, tmp1);
2781 __ bind(profile_cast_success);
2782 metadata2reg(md->constant_encoding(), mdo);
2783 if (mdo_offset_bias > 0) {
2784 __ set(mdo_offset_bias, tmp1);
2785 __ add(mdo, tmp1, mdo);
2786 }
2787 __ load_klass(value, recv);
2788 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2789 __ ba_short(done);
2790 // Cast failure case
2791 __ bind(profile_cast_failure);
2792 metadata2reg(md->constant_encoding(), mdo);
2793 if (mdo_offset_bias > 0) {
2794 __ set(mdo_offset_bias, tmp1);
2795 __ add(mdo, tmp1, mdo);
2796 }
2797 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2798 __ ld_ptr(data_addr, tmp1);
2799 __ sub(tmp1, DataLayout::counter_increment, tmp1);
2800 __ st_ptr(tmp1, data_addr);
2801 __ ba(*stub->entry());
2802 __ delayed()->nop();
2803 }
2804 __ bind(done);
2805 } else if (code == lir_checkcast) {
2806 Register obj = op->object()->as_register();
2807 Register dst = op->result_opr()->as_register();
2808 Label success;
2809 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2810 __ bind(success);
2811 __ mov(obj, dst);
2812 } else if (code == lir_instanceof) {
2813 Register obj = op->object()->as_register();
2814 Register dst = op->result_opr()->as_register();
2815 Label success, failure, done;
2816 emit_typecheck_helper(op, &success, &failure, &failure);
2817 __ bind(failure);
2818 __ set(0, dst);
2819 __ ba_short(done);
2820 __ bind(success);
2821 __ set(1, dst);
2822 __ bind(done);
2823 } else {
2824 ShouldNotReachHere();
2825 }
2826
2827 }
2828
2829
2830 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2831 if (op->code() == lir_cas_long) {
2832 assert(VM_Version::supports_cx8(), "wrong machine");
2833 Register addr = op->addr()->as_pointer_register();
2834 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2835 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2836 Register new_value_lo = op->new_value()->as_register_lo();
2837 Register new_value_hi = op->new_value()->as_register_hi();
2838 Register t1 = op->tmp1()->as_register();
2839 Register t2 = op->tmp2()->as_register();
2840 #ifdef _LP64
2841 __ mov(cmp_value_lo, t1);
2842 __ mov(new_value_lo, t2);
2843 // perform the compare and swap operation
2844 __ casx(addr, t1, t2);
2845 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2846 // overwritten with the original value in "addr" and will be equal to t1.
2847 __ cmp(t1, t2);
2848 #else
2849 // move high and low halves of long values into single registers
2850 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2851 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2852 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2853 __ sllx(new_value_hi, 32, t2);
2854 __ srl(new_value_lo, 0, new_value_lo);
2855 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2856 // perform the compare and swap operation
2857 __ casx(addr, t1, t2);
2858 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2859 // overwritten with the original value in "addr" and will be equal to t1.
2860 // Produce icc flag for 32bit.
2861 __ sub(t1, t2, t2);
2862 __ srlx(t2, 32, t1);
2863 __ orcc(t2, t1, G0);
2864 #endif
2865 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2866 Register addr = op->addr()->as_pointer_register();
2867 Register cmp_value = op->cmp_value()->as_register();
2868 Register new_value = op->new_value()->as_register();
2869 Register t1 = op->tmp1()->as_register();
2870 Register t2 = op->tmp2()->as_register();
2871 __ mov(cmp_value, t1);
2872 __ mov(new_value, t2);
2873 if (op->code() == lir_cas_obj) {
2874 if (UseCompressedOops) {
2875 __ encode_heap_oop(t1);
2876 __ encode_heap_oop(t2);
2877 __ cas(addr, t1, t2);
2878 } else {
2879 __ cas_ptr(addr, t1, t2);
2880 }
2881 } else {
2882 __ cas(addr, t1, t2);
2883 }
2884 __ cmp(t1, t2);
2885 } else {
2886 Unimplemented();
2887 }
2888 }
2889
2890 void LIR_Assembler::set_24bit_FPU() {
2891 Unimplemented();
2892 }
2893
2894
2895 void LIR_Assembler::reset_FPU() {
2896 Unimplemented();
2897 }
2898
2899
2900 void LIR_Assembler::breakpoint() {
2901 __ breakpoint_trap();
2902 }
2903
2904
2905 void LIR_Assembler::push(LIR_Opr opr) {
2906 Unimplemented();
2907 }
2908
2909
2910 void LIR_Assembler::pop(LIR_Opr opr) {
2911 Unimplemented();
2912 }
2913
2914
2915 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2916 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2917 Register dst = dst_opr->as_register();
2918 Register reg = mon_addr.base();
2919 int offset = mon_addr.disp();
2920 // compute pointer to BasicLock
2921 if (mon_addr.is_simm13()) {
2922 __ add(reg, offset, dst);
2923 } else {
2924 __ set(offset, dst);
2925 __ add(dst, reg, dst);
2926 }
2927 }
2928
2929 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2930 fatal("CRC32 intrinsic is not implemented on this platform");
2931 }
2932
2933 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2934 Register obj = op->obj_opr()->as_register();
2935 Register hdr = op->hdr_opr()->as_register();
2936 Register lock = op->lock_opr()->as_register();
2937
2938 // obj may not be an oop
2939 if (op->code() == lir_lock) {
2940 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2941 if (UseFastLocking) {
2942 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2943 // add debug info for NullPointerException only if one is possible
2944 if (op->info() != NULL) {
2945 add_debug_info_for_null_check_here(op->info());
2946 }
2947 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2948 } else {
2949 // always do slow locking
2950 // note: the slow locking code could be inlined here, however if we use
2951 // slow locking, speed doesn't matter anyway and this solution is
2952 // simpler and requires less duplicated code - additionally, the
2953 // slow locking code is the same in either case which simplifies
2954 // debugging
2955 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2956 __ delayed()->nop();
2957 }
2958 } else {
2959 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2960 if (UseFastLocking) {
2961 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2962 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2963 } else {
2964 // always do slow unlocking
2965 // note: the slow unlocking code could be inlined here, however if we use
2966 // slow unlocking, speed doesn't matter anyway and this solution is
2967 // simpler and requires less duplicated code - additionally, the
2968 // slow unlocking code is the same in either case which simplifies
2969 // debugging
2970 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2971 __ delayed()->nop();
2972 }
2973 }
2974 __ bind(*op->stub()->continuation());
2975 }
2976
2977
2978 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2979 ciMethod* method = op->profiled_method();
2980 int bci = op->profiled_bci();
2981 ciMethod* callee = op->profiled_callee();
2982
2983 // Update counter for all call types
2984 ciMethodData* md = method->method_data_or_null();
2985 assert(md != NULL, "Sanity");
2986 ciProfileData* data = md->bci_to_data(bci);
2987 assert(data->is_CounterData(), "need CounterData for calls");
2988 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2989 Register mdo = op->mdo()->as_register();
2990 #ifdef _LP64
2991 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2992 Register tmp1 = op->tmp1()->as_register_lo();
2993 #else
2994 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2995 Register tmp1 = op->tmp1()->as_register();
2996 #endif
2997 metadata2reg(md->constant_encoding(), mdo);
2998 int mdo_offset_bias = 0;
2999 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
3000 data->size_in_bytes())) {
3001 // The offset is large so bias the mdo by the base of the slot so
3002 // that the ld can use simm13s to reference the slots of the data
3003 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
3004 __ set(mdo_offset_bias, O7);
3005 __ add(mdo, O7, mdo);
3006 }
3007
3008 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
3009 Bytecodes::Code bc = method->java_code_at_bci(bci);
3010 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3011 // Perform additional virtual call profiling for invokevirtual and
3012 // invokeinterface bytecodes
3013 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3014 !callee_is_static && // required for optimized MH invokes
3015 C1ProfileVirtualCalls) {
3016 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3017 Register recv = op->recv()->as_register();
3018 assert_different_registers(mdo, tmp1, recv);
3019 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3020 ciKlass* known_klass = op->known_holder();
3021 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3022 // We know the type that will be seen at this call site; we can
3023 // statically update the MethodData* rather than needing to do
3024 // dynamic tests on the receiver type
3025
3026 // NOTE: we should probably put a lock around this search to
3027 // avoid collisions by concurrent compilations
3028 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3029 uint i;
3030 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3031 ciKlass* receiver = vc_data->receiver(i);
3032 if (known_klass->equals(receiver)) {
3033 Address data_addr(mdo, md->byte_offset_of_slot(data,
3034 VirtualCallData::receiver_count_offset(i)) -
3035 mdo_offset_bias);
3036 __ ld_ptr(data_addr, tmp1);
3037 __ add(tmp1, DataLayout::counter_increment, tmp1);
3038 __ st_ptr(tmp1, data_addr);
3039 return;
3040 }
3041 }
3042
3043 // Receiver type not found in profile data; select an empty slot
3044
3045 // Note that this is less efficient than it should be because it
3046 // always does a write to the receiver part of the
3047 // VirtualCallData rather than just the first time
3048 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3049 ciKlass* receiver = vc_data->receiver(i);
3050 if (receiver == NULL) {
3051 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
3052 mdo_offset_bias);
3053 metadata2reg(known_klass->constant_encoding(), tmp1);
3054 __ st_ptr(tmp1, recv_addr);
3055 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
3056 mdo_offset_bias);
3057 __ ld_ptr(data_addr, tmp1);
3058 __ add(tmp1, DataLayout::counter_increment, tmp1);
3059 __ st_ptr(tmp1, data_addr);
3060 return;
3061 }
3062 }
3063 } else {
3064 __ load_klass(recv, recv);
3065 Label update_done;
3066 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
3067 // Receiver did not match any saved receiver and there is no empty row for it.
3068 // Increment total counter to indicate polymorphic case.
3069 __ ld_ptr(counter_addr, tmp1);
3070 __ add(tmp1, DataLayout::counter_increment, tmp1);
3071 __ st_ptr(tmp1, counter_addr);
3072
3073 __ bind(update_done);
3074 }
3075 } else {
3076 // Static call
3077 __ ld_ptr(counter_addr, tmp1);
3078 __ add(tmp1, DataLayout::counter_increment, tmp1);
3079 __ st_ptr(tmp1, counter_addr);
3080 }
3081 }
3082
3083 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3084 Register obj = op->obj()->as_register();
3085 Register tmp1 = op->tmp()->as_pointer_register();
3086 Register tmp2 = G1;
3087 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3088 ciKlass* exact_klass = op->exact_klass();
3089 intptr_t current_klass = op->current_klass();
3090 bool not_null = op->not_null();
3091 bool no_conflict = op->no_conflict();
3092
3093 Label update, next, none;
3094
3095 bool do_null = !not_null;
3096 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3097 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3098
3099 assert(do_null || do_update, "why are we here?");
3100 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3101
3102 __ verify_oop(obj);
3103
3104 if (tmp1 != obj) {
3105 __ mov(obj, tmp1);
3106 }
3107 if (do_null) {
3108 __ br_notnull_short(tmp1, Assembler::pt, update);
3109 if (!TypeEntries::was_null_seen(current_klass)) {
3110 __ ld_ptr(mdo_addr, tmp1);
3111 __ or3(tmp1, TypeEntries::null_seen, tmp1);
3112 __ st_ptr(tmp1, mdo_addr);
3113 }
3114 if (do_update) {
3115 __ ba(next);
3116 __ delayed()->nop();
3117 }
3118 #ifdef ASSERT
3119 } else {
3120 __ br_notnull_short(tmp1, Assembler::pt, update);
3121 __ stop("unexpect null obj");
3122 #endif
3123 }
3124
3125 __ bind(update);
3126
3127 if (do_update) {
3128 #ifdef ASSERT
3129 if (exact_klass != NULL) {
3130 Label ok;
3131 __ load_klass(tmp1, tmp1);
3132 metadata2reg(exact_klass->constant_encoding(), tmp2);
3133 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok);
3134 __ stop("exact klass and actual klass differ");
3135 __ bind(ok);
3136 }
3137 #endif
3138
3139 Label do_update;
3140 __ ld_ptr(mdo_addr, tmp2);
3141
3142 if (!no_conflict) {
3143 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3144 if (exact_klass != NULL) {
3145 metadata2reg(exact_klass->constant_encoding(), tmp1);
3146 } else {
3147 __ load_klass(tmp1, tmp1);
3148 }
3149
3150 __ xor3(tmp1, tmp2, tmp1);
3151 __ btst(TypeEntries::type_klass_mask, tmp1);
3152 // klass seen before, nothing to do. The unknown bit may have been
3153 // set already but no need to check.
3154 __ brx(Assembler::zero, false, Assembler::pt, next);
3155 __ delayed()->
3156
3157 btst(TypeEntries::type_unknown, tmp1);
3158 // already unknown. Nothing to do anymore.
3159 __ brx(Assembler::notZero, false, Assembler::pt, next);
3160
3161 if (TypeEntries::is_type_none(current_klass)) {
3162 __ delayed()->btst(TypeEntries::type_mask, tmp2);
3163 __ brx(Assembler::zero, true, Assembler::pt, do_update);
3164 // first time here. Set profile type.
3165 __ delayed()->or3(tmp2, tmp1, tmp2);
3166 } else {
3167 __ delayed()->nop();
3168 }
3169 } else {
3170 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3171 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3172
3173 __ btst(TypeEntries::type_unknown, tmp2);
3174 // already unknown. Nothing to do anymore.
3175 __ brx(Assembler::notZero, false, Assembler::pt, next);
3176 __ delayed()->nop();
3177 }
3178
3179 // different than before. Cannot keep accurate profile.
3180 __ or3(tmp2, TypeEntries::type_unknown, tmp2);
3181 } else {
3182 // There's a single possible klass at this profile point
3183 assert(exact_klass != NULL, "should be");
3184 if (TypeEntries::is_type_none(current_klass)) {
3185 metadata2reg(exact_klass->constant_encoding(), tmp1);
3186 __ xor3(tmp1, tmp2, tmp1);
3187 __ btst(TypeEntries::type_klass_mask, tmp1);
3188 __ brx(Assembler::zero, false, Assembler::pt, next);
3189 #ifdef ASSERT
3190
3191 {
3192 Label ok;
3193 __ delayed()->btst(TypeEntries::type_mask, tmp2);
3194 __ brx(Assembler::zero, true, Assembler::pt, ok);
3195 __ delayed()->nop();
3196
3197 __ stop("unexpected profiling mismatch");
3198 __ bind(ok);
3199 }
3200 // first time here. Set profile type.
3201 __ or3(tmp2, tmp1, tmp2);
3202 #else
3203 // first time here. Set profile type.
3204 __ delayed()->or3(tmp2, tmp1, tmp2);
3205 #endif
3206
3207 } else {
3208 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3209 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3210
3211 // already unknown. Nothing to do anymore.
3212 __ btst(TypeEntries::type_unknown, tmp2);
3213 __ brx(Assembler::notZero, false, Assembler::pt, next);
3214 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2);
3215 }
3216 }
3217
3218 __ bind(do_update);
3219 __ st_ptr(tmp2, mdo_addr);
3220
3221 __ bind(next);
3222 }
3223 }
3224
3225 void LIR_Assembler::align_backward_branch_target() {
3226 __ align(OptoLoopAlignment);
3227 }
3228
3229
3230 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3231 // make sure we are expecting a delay
3232 // this has the side effect of clearing the delay state
3233 // so we can use _masm instead of _masm->delayed() to do the
3234 // code generation.
3235 __ delayed();
3236
3237 // make sure we only emit one instruction
3238 int offset = code_offset();
3239 op->delay_op()->emit_code(this);
3240 #ifdef ASSERT
3241 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3242 op->delay_op()->print();
3243 }
3244 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
3245 "only one instruction can go in a delay slot");
3246 #endif
3247
3248 // we may also be emitting the call info for the instruction
3249 // which we are the delay slot of.
3250 CodeEmitInfo* call_info = op->call_info();
3251 if (call_info) {
3252 add_call_info(code_offset(), call_info);
3253 }
3254
3255 if (VerifyStackAtCalls) {
3256 _masm->sub(FP, SP, O7);
3257 _masm->cmp(O7, initial_frame_size_in_bytes());
3258 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
3259 }
3260 }
3261
3262
3263 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3264 assert(left->is_register(), "can only handle registers");
3265
3266 if (left->is_single_cpu()) {
3267 __ neg(left->as_register(), dest->as_register());
3268 } else if (left->is_single_fpu()) {
3269 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
3270 } else if (left->is_double_fpu()) {
3271 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
3272 } else {
3273 assert (left->is_double_cpu(), "Must be a long");
3274 Register Rlow = left->as_register_lo();
3275 Register Rhi = left->as_register_hi();
3276 #ifdef _LP64
3277 __ sub(G0, Rlow, dest->as_register_lo());
3278 #else
3279 __ subcc(G0, Rlow, dest->as_register_lo());
3280 __ subc (G0, Rhi, dest->as_register_hi());
3281 #endif
3282 }
3283 }
3284
3285
3286 void LIR_Assembler::fxch(int i) {
3287 Unimplemented();
3288 }
3289
3290 void LIR_Assembler::fld(int i) {
3291 Unimplemented();
3292 }
3293
3294 void LIR_Assembler::ffree(int i) {
3295 Unimplemented();
3296 }
3297
3298 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
3299 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3300
3301 // if tmp is invalid, then the function being called doesn't destroy the thread
3302 if (tmp->is_valid()) {
3303 __ save_thread(tmp->as_pointer_register());
3304 }
3305 __ call(dest, relocInfo::runtime_call_type);
3306 __ delayed()->nop();
3307 if (info != NULL) {
3308 add_call_info_here(info);
3309 }
3310 if (tmp->is_valid()) {
3311 __ restore_thread(tmp->as_pointer_register());
3312 }
3313
3314 #ifdef ASSERT
3315 __ verify_thread();
3316 #endif // ASSERT
3317 }
3318
3319
3320 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3321 #ifdef _LP64
3322 ShouldNotReachHere();
3323 #endif
3324
3325 NEEDS_CLEANUP;
3326 if (type == T_LONG) {
3327 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
3328
3329 // (extended to allow indexed as well as constant displaced for JSR-166)
3330 Register idx = noreg; // contains either constant offset or index
3331
3332 int disp = mem_addr->disp();
3333 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
3334 if (!Assembler::is_simm13(disp)) {
3335 idx = O7;
3336 __ set(disp, idx);
3337 }
3338 } else {
3339 assert(disp == 0, "not both indexed and disp");
3340 idx = mem_addr->index()->as_register();
3341 }
3342
3343 int null_check_offset = -1;
3344
3345 Register base = mem_addr->base()->as_register();
3346 if (src->is_register() && dest->is_address()) {
3347 // G4 is high half, G5 is low half
3348 // clear the top bits of G5, and scale up G4
3349 __ srl (src->as_register_lo(), 0, G5);
3350 __ sllx(src->as_register_hi(), 32, G4);
3351 // combine the two halves into the 64 bits of G4
3352 __ or3(G4, G5, G4);
3353 null_check_offset = __ offset();
3354 if (idx == noreg) {
3355 __ stx(G4, base, disp);
3356 } else {
3357 __ stx(G4, base, idx);
3358 }
3359 } else if (src->is_address() && dest->is_register()) {
3360 null_check_offset = __ offset();
3361 if (idx == noreg) {
3362 __ ldx(base, disp, G5);
3363 } else {
3364 __ ldx(base, idx, G5);
3365 }
3366 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
3367 __ mov (G5, dest->as_register_lo()); // copy low half into lo
3368 } else {
3369 Unimplemented();
3370 }
3371 if (info != NULL) {
3372 add_debug_info_for_null_check(null_check_offset, info);
3373 }
3374
3375 } else {
3376 // use normal move for all other volatiles since they don't need
3377 // special handling to remain atomic.
3378 move_op(src, dest, type, lir_patch_none, info, false, false, false);
3379 }
3380 }
3381
3382 void LIR_Assembler::membar() {
3383 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3384 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3385 }
3386
3387 void LIR_Assembler::membar_acquire() {
3388 // no-op on TSO
3389 }
3390
3391 void LIR_Assembler::membar_release() {
3392 // no-op on TSO
3393 }
3394
3395 void LIR_Assembler::membar_loadload() {
3396 // no-op
3397 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3398 }
3399
3400 void LIR_Assembler::membar_storestore() {
3401 // no-op
3402 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3403 }
3404
3405 void LIR_Assembler::membar_loadstore() {
3406 // no-op
3407 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3408 }
3409
3410 void LIR_Assembler::membar_storeload() {
3411 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3412 }
3413
3414
3415 // Pack two sequential registers containing 32 bit values
3416 // into a single 64 bit register.
3417 // src and src->successor() are packed into dst
3418 // src and dst may be the same register.
3419 // Note: src is destroyed
3420 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3421 Register rs = src->as_register();
3422 Register rd = dst->as_register_lo();
3423 __ sllx(rs, 32, rs);
3424 __ srl(rs->successor(), 0, rs->successor());
3425 __ or3(rs, rs->successor(), rd);
3426 }
3427
3428 // Unpack a 64 bit value in a register into
3429 // two sequential registers.
3430 // src is unpacked into dst and dst->successor()
3431 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3432 Register rs = src->as_register_lo();
3433 Register rd = dst->as_register_hi();
3434 assert_different_registers(rs, rd, rd->successor());
3435 __ srlx(rs, 32, rd);
3436 __ srl (rs, 0, rd->successor());
3437 }
3438
3439
3440 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3441 LIR_Address* addr = addr_opr->as_address_ptr();
3442 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3443
3444 if (Assembler::is_simm13(addr->disp())) {
3445 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3446 } else {
3447 __ set(addr->disp(), G3_scratch);
3448 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3449 }
3450 }
3451
3452
3453 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3454 assert(result_reg->is_register(), "check");
3455 __ mov(G2_thread, result_reg->as_register());
3456 }
3457
3458 #ifdef ASSERT
3459 // emit run-time assertion
3460 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3461 assert(op->code() == lir_assert, "must be");
3462
3463 if (op->in_opr1()->is_valid()) {
3464 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3465 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3466 } else {
3467 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3468 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3469 }
3470
3471 Label ok;
3472 if (op->condition() != lir_cond_always) {
3473 Assembler::Condition acond;
3474 switch (op->condition()) {
3475 case lir_cond_equal: acond = Assembler::equal; break;
3476 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3477 case lir_cond_less: acond = Assembler::less; break;
3478 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3479 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
3480 case lir_cond_greater: acond = Assembler::greater; break;
3481 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
3482 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
3483 default: ShouldNotReachHere();
3484 };
3485 __ br(acond, false, Assembler::pt, ok);
3486 __ delayed()->nop();
3487 }
3488 if (op->halt()) {
3489 const char* str = __ code_string(op->msg());
3490 __ stop(str);
3491 } else {
3492 breakpoint();
3493 }
3494 __ bind(ok);
3495 }
3496 #endif
3497
3498 void LIR_Assembler::peephole(LIR_List* lir) {
3499 LIR_OpList* inst = lir->instructions_list();
3500 for (int i = 0; i < inst->length(); i++) {
3501 LIR_Op* op = inst->at(i);
3502 switch (op->code()) {
3503 case lir_cond_float_branch:
3504 case lir_branch: {
3505 LIR_OpBranch* branch = op->as_OpBranch();
3506 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3507 LIR_Op* delay_op = NULL;
3508 // we'd like to be able to pull following instructions into
3509 // this slot but we don't know enough to do it safely yet so
3510 // only optimize block to block control flow.
3511 if (LIRFillDelaySlots && branch->block()) {
3512 LIR_Op* prev = inst->at(i - 1);
3513 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3514 // swap previous instruction into delay slot
3515 inst->at_put(i - 1, op);
3516 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3517 #ifndef PRODUCT
3518 if (LIRTracePeephole) {
3519 tty->print_cr("delayed");
3520 inst->at(i - 1)->print();
3521 inst->at(i)->print();
3522 tty->cr();
3523 }
3524 #endif
3525 continue;
3526 }
3527 }
3528
3529 if (!delay_op) {
3530 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3531 }
3532 inst->insert_before(i + 1, delay_op);
3533 break;
3534 }
3535 case lir_static_call:
3536 case lir_virtual_call:
3537 case lir_icvirtual_call:
3538 case lir_optvirtual_call:
3539 case lir_dynamic_call: {
3540 LIR_Op* prev = inst->at(i - 1);
3541 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3542 (op->code() != lir_virtual_call ||
3543 !prev->result_opr()->is_single_cpu() ||
3544 prev->result_opr()->as_register() != O0) &&
3545 LIR_Assembler::is_single_instruction(prev)) {
3546 // Only moves without info can be put into the delay slot.
3547 // Also don't allow the setup of the receiver in the delay
3548 // slot for vtable calls.
3549 inst->at_put(i - 1, op);
3550 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3551 #ifndef PRODUCT
3552 if (LIRTracePeephole) {
3553 tty->print_cr("delayed");
3554 inst->at(i - 1)->print();
3555 inst->at(i)->print();
3556 tty->cr();
3557 }
3558 #endif
3559 } else {
3560 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3561 inst->insert_before(i + 1, delay_op);
3562 i++;
3563 }
3564
3565 #if defined(TIERED) && !defined(_LP64)
3566 // fixup the return value from G1 to O0/O1 for long returns.
3567 // It's done here instead of in LIRGenerator because there's
3568 // such a mismatch between the single reg and double reg
3569 // calling convention.
3570 LIR_OpJavaCall* callop = op->as_OpJavaCall();
3571 if (callop->result_opr() == FrameMap::out_long_opr) {
3572 LIR_OpJavaCall* call;
3573 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length());
3574 for (int a = 0; a < arguments->length(); a++) {
3575 arguments[a] = callop->arguments()[a];
3576 }
3577 if (op->code() == lir_virtual_call) {
3578 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3579 callop->vtable_offset(), arguments, callop->info());
3580 } else {
3581 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3582 callop->addr(), arguments, callop->info());
3583 }
3584 inst->at_put(i - 1, call);
3585 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3586 T_LONG, lir_patch_none, NULL));
3587 }
3588 #endif
3589 break;
3590 }
3591 }
3592 }
3593 }
3594
3595 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3596 LIR_Address* addr = src->as_address_ptr();
3597
3598 assert(data == dest, "swap uses only 2 operands");
3599 assert (code == lir_xchg, "no xadd on sparc");
3600
3601 if (data->type() == T_INT) {
3602 __ swap(as_Address(addr), data->as_register());
3603 } else if (data->is_oop()) {
3604 Register obj = data->as_register();
3605 Register narrow = tmp->as_register();
3606 #ifdef _LP64
3607 assert(UseCompressedOops, "swap is 32bit only");
3608 __ encode_heap_oop(obj, narrow);
3609 __ swap(as_Address(addr), narrow);
3610 __ decode_heap_oop(narrow, obj);
3611 #else
3612 __ swap(as_Address(addr), obj);
3613 #endif
3614 } else {
3615 ShouldNotReachHere();
3616 }
3617 }
3618
3619 #undef __