1 // 2 // Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Header information of the source block. 461 // Method declarations/definitions which are used outside 462 // the ad-scope can conveniently be defined here. 463 // 464 // To keep related declarations/definitions/uses close together, 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 466 467 // Must be visible to the DFA in dfa_sparc.cpp 468 extern bool can_branch_register( Node *bol, Node *cmp ); 469 470 extern bool use_block_zeroing(Node* count); 471 472 // Macros to extract hi & lo halves from a long pair. 473 // G0 is not part of any long pair, so assert on that. 474 // Prevents accidentally using G1 instead of G0. 475 #define LONG_HI_REG(x) (x) 476 #define LONG_LO_REG(x) (x) 477 478 class CallStubImpl { 479 480 //-------------------------------------------------------------- 481 //---< Used for optimization in Compile::Shorten_branches >--- 482 //-------------------------------------------------------------- 483 484 public: 485 // Size of call trampoline stub. 486 static uint size_call_trampoline() { 487 return 0; // no call trampolines on this platform 488 } 489 490 // number of relocations needed by a call trampoline stub 491 static uint reloc_call_trampoline() { 492 return 0; // no call trampolines on this platform 493 } 494 }; 495 496 class HandlerImpl { 497 498 public: 499 500 static int emit_exception_handler(CodeBuffer &cbuf); 501 static int emit_deopt_handler(CodeBuffer& cbuf); 502 503 static uint size_exception_handler() { 504 if (TraceJumps) { 505 return (400); // just a guess 506 } 507 return ( NativeJump::instruction_size ); // sethi;jmp;nop 508 } 509 510 static uint size_deopt_handler() { 511 if (TraceJumps) { 512 return (400); // just a guess 513 } 514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 515 } 516 }; 517 518 %} 519 520 source %{ 521 #define __ _masm. 522 523 // tertiary op of a LoadP or StoreP encoding 524 #define REGP_OP true 525 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 528 static Register reg_to_register_object(int register_encoding); 529 530 // Used by the DFA in dfa_sparc.cpp. 531 // Check for being able to use a V9 branch-on-register. Requires a 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 533 // extended. Doesn't work following an integer ADD, for example, because of 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 536 // replace them with zero, which could become sign-extension in a different OS 537 // release. There's no obvious reason why an interrupt will ever fill these 538 // bits with non-zero junk (the registers are reloaded with standard LD 539 // instructions which either zero-fill or sign-fill). 540 bool can_branch_register( Node *bol, Node *cmp ) { 541 if( !BranchOnRegister ) return false; 542 #ifdef _LP64 543 if( cmp->Opcode() == Op_CmpP ) 544 return true; // No problems with pointer compares 545 #endif 546 if( cmp->Opcode() == Op_CmpL ) 547 return true; // No problems with long compares 548 549 if( !SparcV9RegsHiBitsZero ) return false; 550 if( bol->as_Bool()->_test._test != BoolTest::ne && 551 bol->as_Bool()->_test._test != BoolTest::eq ) 552 return false; 553 554 // Check for comparing against a 'safe' value. Any operation which 555 // clears out the high word is safe. Thus, loads and certain shifts 556 // are safe, as are non-negative constants. Any operation which 557 // preserves zero bits in the high word is safe as long as each of its 558 // inputs are safe. Thus, phis and bitwise booleans are safe if their 559 // inputs are safe. At present, the only important case to recognize 560 // seems to be loads. Constants should fold away, and shifts & 561 // logicals can use the 'cc' forms. 562 Node *x = cmp->in(1); 563 if( x->is_Load() ) return true; 564 if( x->is_Phi() ) { 565 for( uint i = 1; i < x->req(); i++ ) 566 if( !x->in(i)->is_Load() ) 567 return false; 568 return true; 569 } 570 return false; 571 } 572 573 bool use_block_zeroing(Node* count) { 574 // Use BIS for zeroing if count is not constant 575 // or it is >= BlockZeroingLowLimit. 576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 577 } 578 579 // **************************************************************************** 580 581 // REQUIRED FUNCTIONALITY 582 583 // !!!!! Special hack to get all type of calls to specify the byte offset 584 // from the start of the call to the point where the return address 585 // will point. 586 // The "return address" is the address of the call instruction, plus 8. 587 588 int MachCallStaticJavaNode::ret_addr_offset() { 589 int offset = NativeCall::instruction_size; // call; delay slot 590 if (_method_handle_invoke) 591 offset += 4; // restore SP 592 return offset; 593 } 594 595 int MachCallDynamicJavaNode::ret_addr_offset() { 596 int vtable_index = this->_vtable_index; 597 if (vtable_index < 0) { 598 // must be invalid_vtable_index, not nonvirtual_vtable_index 599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 600 return (NativeMovConstReg::instruction_size + 601 NativeCall::instruction_size); // sethi; setlo; call; delay slot 602 } else { 603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 606 int klass_load_size; 607 if (UseCompressedClassPointers) { 608 assert(Universe::heap() != NULL, "java heap should be initialized"); 609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 610 } else { 611 klass_load_size = 1*BytesPerInstWord; 612 } 613 if (Assembler::is_simm13(v_off)) { 614 return klass_load_size + 615 (2*BytesPerInstWord + // ld_ptr, ld_ptr 616 NativeCall::instruction_size); // call; delay slot 617 } else { 618 return klass_load_size + 619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 620 NativeCall::instruction_size); // call; delay slot 621 } 622 } 623 } 624 625 int MachCallRuntimeNode::ret_addr_offset() { 626 #ifdef _LP64 627 if (MacroAssembler::is_far_target(entry_point())) { 628 return NativeFarCall::instruction_size; 629 } else { 630 return NativeCall::instruction_size; 631 } 632 #else 633 return NativeCall::instruction_size; // call; delay slot 634 #endif 635 } 636 637 // Indicate if the safepoint node needs the polling page as an input. 638 // Since Sparc does not have absolute addressing, it does. 639 bool SafePointNode::needs_polling_address_input() { 640 return true; 641 } 642 643 // emit an interrupt that is caught by the debugger (for debugging compiler) 644 void emit_break(CodeBuffer &cbuf) { 645 MacroAssembler _masm(&cbuf); 646 __ breakpoint_trap(); 647 } 648 649 #ifndef PRODUCT 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 651 st->print("TA"); 652 } 653 #endif 654 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 656 emit_break(cbuf); 657 } 658 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 660 return MachNode::size(ra_); 661 } 662 663 // Traceable jump 664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 665 MacroAssembler _masm(&cbuf); 666 Register rdest = reg_to_register_object(jump_target); 667 __ JMP(rdest, 0); 668 __ delayed()->nop(); 669 } 670 671 // Traceable jump and set exception pc 672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 673 MacroAssembler _masm(&cbuf); 674 Register rdest = reg_to_register_object(jump_target); 675 __ JMP(rdest, 0); 676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 677 } 678 679 void emit_nop(CodeBuffer &cbuf) { 680 MacroAssembler _masm(&cbuf); 681 __ nop(); 682 } 683 684 void emit_illtrap(CodeBuffer &cbuf) { 685 MacroAssembler _masm(&cbuf); 686 __ illtrap(0); 687 } 688 689 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 691 assert(n->rule() != loadUB_rule, ""); 692 693 intptr_t offset = 0; 694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 695 const Node* addr = n->get_base_and_disp(offset, adr_type); 696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 697 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 698 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 699 atype = atype->add_offset(offset); 700 assert(disp32 == offset, "wrong disp32"); 701 return atype->_offset; 702 } 703 704 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 706 assert(n->rule() != loadUB_rule, ""); 707 708 intptr_t offset = 0; 709 Node* addr = n->in(2); 710 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 712 Node* a = addr->in(2/*AddPNode::Address*/); 713 Node* o = addr->in(3/*AddPNode::Offset*/); 714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 715 atype = a->bottom_type()->is_ptr()->add_offset(offset); 716 assert(atype->isa_oop_ptr(), "still an oop"); 717 } 718 offset = atype->is_ptr()->_offset; 719 if (offset != Type::OffsetBot) offset += disp32; 720 return offset; 721 } 722 723 static inline jdouble replicate_immI(int con, int count, int width) { 724 // Load a constant replicated "count" times with width "width" 725 assert(count*width == 8 && width <= 4, "sanity"); 726 int bit_width = width * 8; 727 jlong val = con; 728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 729 for (int i = 0; i < count - 1; i++) { 730 val |= (val << bit_width); 731 } 732 jdouble dval = *((jdouble*) &val); // coerce to double type 733 return dval; 734 } 735 736 static inline jdouble replicate_immF(float con) { 737 // Replicate float con 2 times and pack into vector. 738 int val = *((int*)&con); 739 jlong lval = val; 740 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 741 jdouble dval = *((jdouble*) &lval); // coerce to double type 742 return dval; 743 } 744 745 // Standard Sparc opcode form2 field breakdown 746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 747 f0 &= (1<<19)-1; // Mask displacement to 19 bits 748 int op = (f30 << 30) | 749 (f29 << 29) | 750 (f25 << 25) | 751 (f22 << 22) | 752 (f20 << 20) | 753 (f19 << 19) | 754 (f0 << 0); 755 cbuf.insts()->emit_int32(op); 756 } 757 758 // Standard Sparc opcode form2 field breakdown 759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 760 f0 >>= 10; // Drop 10 bits 761 f0 &= (1<<22)-1; // Mask displacement to 22 bits 762 int op = (f30 << 30) | 763 (f25 << 25) | 764 (f22 << 22) | 765 (f0 << 0); 766 cbuf.insts()->emit_int32(op); 767 } 768 769 // Standard Sparc opcode form3 field breakdown 770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 771 int op = (f30 << 30) | 772 (f25 << 25) | 773 (f19 << 19) | 774 (f14 << 14) | 775 (f5 << 5) | 776 (f0 << 0); 777 cbuf.insts()->emit_int32(op); 778 } 779 780 // Standard Sparc opcode form3 field breakdown 781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 782 simm13 &= (1<<13)-1; // Mask to 13 bits 783 int op = (f30 << 30) | 784 (f25 << 25) | 785 (f19 << 19) | 786 (f14 << 14) | 787 (1 << 13) | // bit to indicate immediate-mode 788 (simm13<<0); 789 cbuf.insts()->emit_int32(op); 790 } 791 792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 793 simm10 &= (1<<10)-1; // Mask to 10 bits 794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 795 } 796 797 #ifdef ASSERT 798 // Helper function for VerifyOops in emit_form3_mem_reg 799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 800 warning("VerifyOops encountered unexpected instruction:"); 801 n->dump(2); 802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 803 } 804 #endif 805 806 807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 808 int src1_enc, int disp32, int src2_enc, int dst_enc) { 809 810 #ifdef ASSERT 811 // The following code implements the +VerifyOops feature. 812 // It verifies oop values which are loaded into or stored out of 813 // the current method activation. +VerifyOops complements techniques 814 // like ScavengeALot, because it eagerly inspects oops in transit, 815 // as they enter or leave the stack, as opposed to ScavengeALot, 816 // which inspects oops "at rest", in the stack or heap, at safepoints. 817 // For this reason, +VerifyOops can sometimes detect bugs very close 818 // to their point of creation. It can also serve as a cross-check 819 // on the validity of oop maps, when used toegether with ScavengeALot. 820 821 // It would be good to verify oops at other points, especially 822 // when an oop is used as a base pointer for a load or store. 823 // This is presently difficult, because it is hard to know when 824 // a base address is biased or not. (If we had such information, 825 // it would be easy and useful to make a two-argument version of 826 // verify_oop which unbiases the base, and performs verification.) 827 828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 829 bool is_verified_oop_base = false; 830 bool is_verified_oop_load = false; 831 bool is_verified_oop_store = false; 832 int tmp_enc = -1; 833 if (VerifyOops && src1_enc != R_SP_enc) { 834 // classify the op, mainly for an assert check 835 int st_op = 0, ld_op = 0; 836 switch (primary) { 837 case Assembler::stb_op3: st_op = Op_StoreB; break; 838 case Assembler::sth_op3: st_op = Op_StoreC; break; 839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 840 case Assembler::stw_op3: st_op = Op_StoreI; break; 841 case Assembler::std_op3: st_op = Op_StoreL; break; 842 case Assembler::stf_op3: st_op = Op_StoreF; break; 843 case Assembler::stdf_op3: st_op = Op_StoreD; break; 844 845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 849 case Assembler::ldx_op3: // may become LoadP or stay LoadI 850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 851 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 852 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 853 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 854 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 856 857 default: ShouldNotReachHere(); 858 } 859 if (tertiary == REGP_OP) { 860 if (st_op == Op_StoreI) st_op = Op_StoreP; 861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 862 else ShouldNotReachHere(); 863 if (st_op) { 864 // a store 865 // inputs are (0:control, 1:memory, 2:address, 3:value) 866 Node* n2 = n->in(3); 867 if (n2 != NULL) { 868 const Type* t = n2->bottom_type(); 869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 870 } 871 } else { 872 // a load 873 const Type* t = n->bottom_type(); 874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 875 } 876 } 877 878 if (ld_op) { 879 // a Load 880 // inputs are (0:control, 1:memory, 2:address) 881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 894 !(n->rule() == loadUB_rule)) { 895 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 896 } 897 } else if (st_op) { 898 // a Store 899 // inputs are (0:control, 1:memory, 2:address, 3:value) 900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 907 verify_oops_warning(n, n->ideal_Opcode(), st_op); 908 } 909 } 910 911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 912 Node* addr = n->in(2); 913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 915 if (atype != NULL) { 916 intptr_t offset = get_offset_from_base(n, atype, disp32); 917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 918 if (offset != offset_2) { 919 get_offset_from_base(n, atype, disp32); 920 get_offset_from_base_2(n, atype, disp32); 921 } 922 assert(offset == offset_2, "different offsets"); 923 if (offset == disp32) { 924 // we now know that src1 is a true oop pointer 925 is_verified_oop_base = true; 926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 927 if( primary == Assembler::ldd_op3 ) { 928 is_verified_oop_base = false; // Cannot 'ldd' into O7 929 } else { 930 tmp_enc = dst_enc; 931 dst_enc = R_O7_enc; // Load into O7; preserve source oop 932 assert(src1_enc != dst_enc, ""); 933 } 934 } 935 } 936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 937 || offset == oopDesc::mark_offset_in_bytes())) { 938 // loading the mark should not be allowed either, but 939 // we don't check this since it conflicts with InlineObjectHash 940 // usage of LoadINode to get the mark. We could keep the 941 // check if we create a new LoadMarkNode 942 // but do not verify the object before its header is initialized 943 ShouldNotReachHere(); 944 } 945 } 946 } 947 } 948 } 949 #endif 950 951 uint instr; 952 instr = (Assembler::ldst_op << 30) 953 | (dst_enc << 25) 954 | (primary << 19) 955 | (src1_enc << 14); 956 957 uint index = src2_enc; 958 int disp = disp32; 959 960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 961 disp += STACK_BIAS; 962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not 963 if (!Assembler::is_simm13(disp)) { 964 ra->C->record_method_not_compilable("unable to handle large constant offsets"); 965 return; 966 } 967 } 968 969 // We should have a compiler bailout here rather than a guarantee. 970 // Better yet would be some mechanism to handle variable-size matches correctly. 971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 972 973 if( disp == 0 ) { 974 // use reg-reg form 975 // bit 13 is already zero 976 instr |= index; 977 } else { 978 // use reg-imm form 979 instr |= 0x00002000; // set bit 13 to one 980 instr |= disp & 0x1FFF; 981 } 982 983 cbuf.insts()->emit_int32(instr); 984 985 #ifdef ASSERT 986 { 987 MacroAssembler _masm(&cbuf); 988 if (is_verified_oop_base) { 989 __ verify_oop(reg_to_register_object(src1_enc)); 990 } 991 if (is_verified_oop_store) { 992 __ verify_oop(reg_to_register_object(dst_enc)); 993 } 994 if (tmp_enc != -1) { 995 __ mov(O7, reg_to_register_object(tmp_enc)); 996 } 997 if (is_verified_oop_load) { 998 __ verify_oop(reg_to_register_object(dst_enc)); 999 } 1000 } 1001 #endif 1002 } 1003 1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { 1005 // The method which records debug information at every safepoint 1006 // expects the call to be the first instruction in the snippet as 1007 // it creates a PcDesc structure which tracks the offset of a call 1008 // from the start of the codeBlob. This offset is computed as 1009 // code_end() - code_begin() of the code which has been emitted 1010 // so far. 1011 // In this particular case we have skirted around the problem by 1012 // putting the "mov" instruction in the delay slot but the problem 1013 // may bite us again at some other point and a cleaner/generic 1014 // solution using relocations would be needed. 1015 MacroAssembler _masm(&cbuf); 1016 __ set_inst_mark(); 1017 1018 // We flush the current window just so that there is a valid stack copy 1019 // the fact that the current window becomes active again instantly is 1020 // not a problem there is nothing live in it. 1021 1022 #ifdef ASSERT 1023 int startpos = __ offset(); 1024 #endif /* ASSERT */ 1025 1026 __ call((address)entry_point, rtype); 1027 1028 if (preserve_g2) __ delayed()->mov(G2, L7); 1029 else __ delayed()->nop(); 1030 1031 if (preserve_g2) __ mov(L7, G2); 1032 1033 #ifdef ASSERT 1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 1035 #ifdef _LP64 1036 // Trash argument dump slots. 1037 __ set(0xb0b8ac0db0b8ac0d, G1); 1038 __ mov(G1, G5); 1039 __ stx(G1, SP, STACK_BIAS + 0x80); 1040 __ stx(G1, SP, STACK_BIAS + 0x88); 1041 __ stx(G1, SP, STACK_BIAS + 0x90); 1042 __ stx(G1, SP, STACK_BIAS + 0x98); 1043 __ stx(G1, SP, STACK_BIAS + 0xA0); 1044 __ stx(G1, SP, STACK_BIAS + 0xA8); 1045 #else // _LP64 1046 // this is also a native call, so smash the first 7 stack locations, 1047 // and the various registers 1048 1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1050 // while [SP+0x44..0x58] are the argument dump slots. 1051 __ set((intptr_t)0xbaadf00d, G1); 1052 __ mov(G1, G5); 1053 __ sllx(G1, 32, G1); 1054 __ or3(G1, G5, G1); 1055 __ mov(G1, G5); 1056 __ stx(G1, SP, 0x40); 1057 __ stx(G1, SP, 0x48); 1058 __ stx(G1, SP, 0x50); 1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1060 #endif // _LP64 1061 } 1062 #endif /*ASSERT*/ 1063 } 1064 1065 //============================================================================= 1066 // REQUIRED FUNCTIONALITY for encoding 1067 void emit_lo(CodeBuffer &cbuf, int val) { } 1068 void emit_hi(CodeBuffer &cbuf, int val) { } 1069 1070 1071 //============================================================================= 1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1073 1074 int Compile::ConstantTable::calculate_table_base_offset() const { 1075 if (UseRDPCForConstantTableBase) { 1076 // The table base offset might be less but then it fits into 1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1078 return Assembler::min_simm13(); 1079 } else { 1080 int offset = -(size() / 2); 1081 if (!Assembler::is_simm13(offset)) { 1082 offset = Assembler::min_simm13(); 1083 } 1084 return offset; 1085 } 1086 } 1087 1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1090 ShouldNotReachHere(); 1091 } 1092 1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1094 Compile* C = ra_->C; 1095 Compile::ConstantTable& constant_table = C->constant_table(); 1096 MacroAssembler _masm(&cbuf); 1097 1098 Register r = as_Register(ra_->get_encode(this)); 1099 CodeSection* consts_section = __ code()->consts(); 1100 int consts_size = consts_section->align_at_start(consts_section->size()); 1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size); 1102 1103 if (UseRDPCForConstantTableBase) { 1104 // For the following RDPC logic to work correctly the consts 1105 // section must be allocated right before the insts section. This 1106 // assert checks for that. The layout and the SECT_* constants 1107 // are defined in src/share/vm/asm/codeBuffer.hpp. 1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1109 int insts_offset = __ offset(); 1110 1111 // Layout: 1112 // 1113 // |----------- consts section ------------|----------- insts section -----------... 1114 // |------ constant table -----|- padding -|------------------x---- 1115 // \ current PC (RDPC instruction) 1116 // |<------------- consts_size ----------->|<- insts_offset ->| 1117 // \ table base 1118 // The table base offset is later added to the load displacement 1119 // so it has to be negative. 1120 int table_base_offset = -(consts_size + insts_offset); 1121 int disp; 1122 1123 // If the displacement from the current PC to the constant table 1124 // base fits into simm13 we set the constant table base to the 1125 // current PC. 1126 if (Assembler::is_simm13(table_base_offset)) { 1127 constant_table.set_table_base_offset(table_base_offset); 1128 disp = 0; 1129 } else { 1130 // Otherwise we set the constant table base offset to the 1131 // maximum negative displacement of load instructions to keep 1132 // the disp as small as possible: 1133 // 1134 // |<------------- consts_size ----------->|<- insts_offset ->| 1135 // |<--------- min_simm13 --------->|<-------- disp --------->| 1136 // \ table base 1137 table_base_offset = Assembler::min_simm13(); 1138 constant_table.set_table_base_offset(table_base_offset); 1139 disp = (consts_size + insts_offset) + table_base_offset; 1140 } 1141 1142 __ rdpc(r); 1143 1144 if (disp != 0) { 1145 assert(r != O7, "need temporary"); 1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1147 } 1148 } 1149 else { 1150 // Materialize the constant table base. 1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1153 AddressLiteral base(baseaddr, rspec); 1154 __ set(base, r); 1155 } 1156 } 1157 1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1159 if (UseRDPCForConstantTableBase) { 1160 // This is really the worst case but generally it's only 1 instruction. 1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1162 } else { 1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1164 } 1165 } 1166 1167 #ifndef PRODUCT 1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1169 char reg[128]; 1170 ra_->dump_register(this, reg); 1171 if (UseRDPCForConstantTableBase) { 1172 st->print("RDPC %s\t! constant table base", reg); 1173 } else { 1174 st->print("SET &constanttable,%s\t! constant table base", reg); 1175 } 1176 } 1177 #endif 1178 1179 1180 //============================================================================= 1181 1182 #ifndef PRODUCT 1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1184 Compile* C = ra_->C; 1185 1186 for (int i = 0; i < OptoPrologueNops; i++) { 1187 st->print_cr("NOP"); st->print("\t"); 1188 } 1189 1190 if( VerifyThread ) { 1191 st->print_cr("Verify_Thread"); st->print("\t"); 1192 } 1193 1194 size_t framesize = C->frame_size_in_bytes(); 1195 int bangsize = C->bang_size_in_bytes(); 1196 1197 // Calls to C2R adapters often do not accept exceptional returns. 1198 // We require that their callers must bang for them. But be careful, because 1199 // some VM calls (such as call site linkage) can use several kilobytes of 1200 // stack. But the stack safety zone should account for that. 1201 // See bugs 4446381, 4468289, 4497237. 1202 if (C->need_stack_bang(bangsize)) { 1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1204 } 1205 1206 if (Assembler::is_simm13(-framesize)) { 1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1208 } else { 1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1211 st->print ("SAVE R_SP,R_G3,R_SP"); 1212 } 1213 1214 } 1215 #endif 1216 1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1218 Compile* C = ra_->C; 1219 MacroAssembler _masm(&cbuf); 1220 1221 for (int i = 0; i < OptoPrologueNops; i++) { 1222 __ nop(); 1223 } 1224 1225 __ verify_thread(); 1226 1227 size_t framesize = C->frame_size_in_bytes(); 1228 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1230 int bangsize = C->bang_size_in_bytes(); 1231 1232 // Calls to C2R adapters often do not accept exceptional returns. 1233 // We require that their callers must bang for them. But be careful, because 1234 // some VM calls (such as call site linkage) can use several kilobytes of 1235 // stack. But the stack safety zone should account for that. 1236 // See bugs 4446381, 4468289, 4497237. 1237 if (C->need_stack_bang(bangsize)) { 1238 __ generate_stack_overflow_check(bangsize); 1239 } 1240 1241 if (Assembler::is_simm13(-framesize)) { 1242 __ save(SP, -framesize, SP); 1243 } else { 1244 __ sethi(-framesize & ~0x3ff, G3); 1245 __ add(G3, -framesize & 0x3ff, G3); 1246 __ save(SP, G3, SP); 1247 } 1248 C->set_frame_complete( __ offset() ); 1249 1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1251 // NOTE: We set the table base offset here because users might be 1252 // emitted before MachConstantBaseNode. 1253 Compile::ConstantTable& constant_table = C->constant_table(); 1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1255 } 1256 } 1257 1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1259 return MachNode::size(ra_); 1260 } 1261 1262 int MachPrologNode::reloc() const { 1263 return 10; // a large enough number 1264 } 1265 1266 //============================================================================= 1267 #ifndef PRODUCT 1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1269 Compile* C = ra_->C; 1270 1271 if(do_polling() && ra_->C->is_method_compilation()) { 1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1273 #ifdef _LP64 1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1275 #else 1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1277 #endif 1278 } 1279 1280 if(do_polling()) { 1281 if (UseCBCond && !ra_->C->is_method_compilation()) { 1282 st->print("NOP\n\t"); 1283 } 1284 st->print("RET\n\t"); 1285 } 1286 1287 st->print("RESTORE"); 1288 } 1289 #endif 1290 1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1292 MacroAssembler _masm(&cbuf); 1293 Compile* C = ra_->C; 1294 1295 __ verify_thread(); 1296 1297 // If this does safepoint polling, then do it here 1298 if(do_polling() && ra_->C->is_method_compilation()) { 1299 AddressLiteral polling_page(os::get_polling_page()); 1300 __ sethi(polling_page, L0); 1301 __ relocate(relocInfo::poll_return_type); 1302 __ ld_ptr(L0, 0, G0); 1303 } 1304 1305 // If this is a return, then stuff the restore in the delay slot 1306 if(do_polling()) { 1307 if (UseCBCond && !ra_->C->is_method_compilation()) { 1308 // Insert extra padding for the case when the epilogue is preceded by 1309 // a cbcond jump, which can't be followed by a CTI instruction 1310 __ nop(); 1311 } 1312 __ ret(); 1313 __ delayed()->restore(); 1314 } else { 1315 __ restore(); 1316 } 1317 } 1318 1319 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1320 return MachNode::size(ra_); 1321 } 1322 1323 int MachEpilogNode::reloc() const { 1324 return 16; // a large enough number 1325 } 1326 1327 const Pipeline * MachEpilogNode::pipeline() const { 1328 return MachNode::pipeline_class(); 1329 } 1330 1331 int MachEpilogNode::safepoint_offset() const { 1332 assert( do_polling(), "no return for this epilog node"); 1333 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1334 } 1335 1336 //============================================================================= 1337 1338 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1339 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1340 static enum RC rc_class( OptoReg::Name reg ) { 1341 if( !OptoReg::is_valid(reg) ) return rc_bad; 1342 if (OptoReg::is_stack(reg)) return rc_stack; 1343 VMReg r = OptoReg::as_VMReg(reg); 1344 if (r->is_Register()) return rc_int; 1345 assert(r->is_FloatRegister(), "must be"); 1346 return rc_float; 1347 } 1348 1349 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1350 if (cbuf) { 1351 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1352 } 1353 #ifndef PRODUCT 1354 else if (!do_size) { 1355 if (size != 0) st->print("\n\t"); 1356 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1357 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1358 } 1359 #endif 1360 return size+4; 1361 } 1362 1363 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1364 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1365 #ifndef PRODUCT 1366 else if( !do_size ) { 1367 if( size != 0 ) st->print("\n\t"); 1368 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1369 } 1370 #endif 1371 return size+4; 1372 } 1373 1374 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1375 PhaseRegAlloc *ra_, 1376 bool do_size, 1377 outputStream* st ) const { 1378 // Get registers to move 1379 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1380 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1381 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1382 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1383 1384 enum RC src_second_rc = rc_class(src_second); 1385 enum RC src_first_rc = rc_class(src_first); 1386 enum RC dst_second_rc = rc_class(dst_second); 1387 enum RC dst_first_rc = rc_class(dst_first); 1388 1389 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1390 1391 // Generate spill code! 1392 int size = 0; 1393 1394 if( src_first == dst_first && src_second == dst_second ) 1395 return size; // Self copy, no move 1396 1397 // -------------------------------------- 1398 // Check for mem-mem move. Load into unused float registers and fall into 1399 // the float-store case. 1400 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1401 int offset = ra_->reg2offset(src_first); 1402 // Further check for aligned-adjacent pair, so we can use a double load 1403 if( (src_first&1)==0 && src_first+1 == src_second ) { 1404 src_second = OptoReg::Name(R_F31_num); 1405 src_second_rc = rc_float; 1406 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1407 } else { 1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1409 } 1410 src_first = OptoReg::Name(R_F30_num); 1411 src_first_rc = rc_float; 1412 } 1413 1414 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1415 int offset = ra_->reg2offset(src_second); 1416 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1417 src_second = OptoReg::Name(R_F31_num); 1418 src_second_rc = rc_float; 1419 } 1420 1421 // -------------------------------------- 1422 // Check for float->int copy; requires a trip through memory 1423 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1424 int offset = frame::register_save_words*wordSize; 1425 if (cbuf) { 1426 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1427 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1428 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1429 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1430 } 1431 #ifndef PRODUCT 1432 else if (!do_size) { 1433 if (size != 0) st->print("\n\t"); 1434 st->print( "SUB R_SP,16,R_SP\n"); 1435 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1436 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1437 st->print("\tADD R_SP,16,R_SP\n"); 1438 } 1439 #endif 1440 size += 16; 1441 } 1442 1443 // Check for float->int copy on T4 1444 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1445 // Further check for aligned-adjacent pair, so we can use a double move 1446 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1447 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); 1448 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); 1449 } 1450 // Check for int->float copy on T4 1451 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1452 // Further check for aligned-adjacent pair, so we can use a double move 1453 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1454 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); 1455 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); 1456 } 1457 1458 // -------------------------------------- 1459 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1460 // In such cases, I have to do the big-endian swap. For aligned targets, the 1461 // hardware does the flop for me. Doubles are always aligned, so no problem 1462 // there. Misaligned sources only come from native-long-returns (handled 1463 // special below). 1464 #ifndef _LP64 1465 if( src_first_rc == rc_int && // source is already big-endian 1466 src_second_rc != rc_bad && // 64-bit move 1467 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1468 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1469 // Do the big-endian flop. 1470 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1471 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1472 } 1473 #endif 1474 1475 // -------------------------------------- 1476 // Check for integer reg-reg copy 1477 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1478 #ifndef _LP64 1479 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1480 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1481 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1482 // operand contains the least significant word of the 64-bit value and vice versa. 1483 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1484 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1485 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1486 if( cbuf ) { 1487 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1488 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1489 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1490 #ifndef PRODUCT 1491 } else if( !do_size ) { 1492 if( size != 0 ) st->print("\n\t"); 1493 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1494 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1495 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1496 #endif 1497 } 1498 return size+12; 1499 } 1500 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1501 // returning a long value in I0/I1 1502 // a SpillCopy must be able to target a return instruction's reg_class 1503 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1504 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1505 // operand contains the least significant word of the 64-bit value and vice versa. 1506 OptoReg::Name tdest = dst_first; 1507 1508 if (src_first == dst_first) { 1509 tdest = OptoReg::Name(R_O7_num); 1510 size += 4; 1511 } 1512 1513 if( cbuf ) { 1514 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1515 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1516 // ShrL_reg_imm6 1517 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1518 // ShrR_reg_imm6 src, 0, dst 1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1520 if (tdest != dst_first) { 1521 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1522 } 1523 } 1524 #ifndef PRODUCT 1525 else if( !do_size ) { 1526 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1527 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1528 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1529 if (tdest != dst_first) { 1530 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1531 } 1532 } 1533 #endif // PRODUCT 1534 return size+8; 1535 } 1536 #endif // !_LP64 1537 // Else normal reg-reg copy 1538 assert( src_second != dst_first, "smashed second before evacuating it" ); 1539 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1540 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1541 // This moves an aligned adjacent pair. 1542 // See if we are done. 1543 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1544 return size; 1545 } 1546 1547 // Check for integer store 1548 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1549 int offset = ra_->reg2offset(dst_first); 1550 // Further check for aligned-adjacent pair, so we can use a double store 1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1552 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1553 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1554 } 1555 1556 // Check for integer load 1557 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1558 int offset = ra_->reg2offset(src_first); 1559 // Further check for aligned-adjacent pair, so we can use a double load 1560 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1561 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1562 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1563 } 1564 1565 // Check for float reg-reg copy 1566 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1567 // Further check for aligned-adjacent pair, so we can use a double move 1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1569 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1570 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1571 } 1572 1573 // Check for float store 1574 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1575 int offset = ra_->reg2offset(dst_first); 1576 // Further check for aligned-adjacent pair, so we can use a double store 1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1578 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1579 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1580 } 1581 1582 // Check for float load 1583 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1584 int offset = ra_->reg2offset(src_first); 1585 // Further check for aligned-adjacent pair, so we can use a double load 1586 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1587 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1588 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1589 } 1590 1591 // -------------------------------------------------------------------- 1592 // Check for hi bits still needing moving. Only happens for misaligned 1593 // arguments to native calls. 1594 if( src_second == dst_second ) 1595 return size; // Self copy; no move 1596 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1597 1598 #ifndef _LP64 1599 // In the LP64 build, all registers can be moved as aligned/adjacent 1600 // pairs, so there's never any need to move the high bits separately. 1601 // The 32-bit builds have to deal with the 32-bit ABI which can force 1602 // all sorts of silly alignment problems. 1603 1604 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1605 // 32-bits of a 64-bit register, but are needed in low bits of another 1606 // register (else it's a hi-bits-to-hi-bits copy which should have 1607 // happened already as part of a 64-bit move) 1608 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1609 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1610 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1611 // Shift src_second down to dst_second's low bits. 1612 if( cbuf ) { 1613 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1614 #ifndef PRODUCT 1615 } else if( !do_size ) { 1616 if( size != 0 ) st->print("\n\t"); 1617 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1618 #endif 1619 } 1620 return size+4; 1621 } 1622 1623 // Check for high word integer store. Must down-shift the hi bits 1624 // into a temp register, then fall into the case of storing int bits. 1625 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1626 // Shift src_second down to dst_second's low bits. 1627 if( cbuf ) { 1628 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1629 #ifndef PRODUCT 1630 } else if( !do_size ) { 1631 if( size != 0 ) st->print("\n\t"); 1632 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1633 #endif 1634 } 1635 size+=4; 1636 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1637 } 1638 1639 // Check for high word integer load 1640 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1641 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1642 1643 // Check for high word integer store 1644 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1645 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1646 1647 // Check for high word float store 1648 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1650 1651 #endif // !_LP64 1652 1653 Unimplemented(); 1654 } 1655 1656 #ifndef PRODUCT 1657 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1658 implementation( NULL, ra_, false, st ); 1659 } 1660 #endif 1661 1662 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1663 implementation( &cbuf, ra_, false, NULL ); 1664 } 1665 1666 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1667 return implementation( NULL, ra_, true, NULL ); 1668 } 1669 1670 //============================================================================= 1671 #ifndef PRODUCT 1672 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1673 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1674 } 1675 #endif 1676 1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1678 MacroAssembler _masm(&cbuf); 1679 for(int i = 0; i < _count; i += 1) { 1680 __ nop(); 1681 } 1682 } 1683 1684 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1685 return 4 * _count; 1686 } 1687 1688 1689 //============================================================================= 1690 #ifndef PRODUCT 1691 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1692 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1693 int reg = ra_->get_reg_first(this); 1694 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1695 } 1696 #endif 1697 1698 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1699 MacroAssembler _masm(&cbuf); 1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1701 int reg = ra_->get_encode(this); 1702 1703 if (Assembler::is_simm13(offset)) { 1704 __ add(SP, offset, reg_to_register_object(reg)); 1705 } else { 1706 __ set(offset, O7); 1707 __ add(SP, O7, reg_to_register_object(reg)); 1708 } 1709 } 1710 1711 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1712 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1713 assert(ra_ == ra_->C->regalloc(), "sanity"); 1714 return ra_->C->scratch_emit_size(this); 1715 } 1716 1717 //============================================================================= 1718 #ifndef PRODUCT 1719 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1720 st->print_cr("\nUEP:"); 1721 #ifdef _LP64 1722 if (UseCompressedClassPointers) { 1723 assert(Universe::heap() != NULL, "java heap should be initialized"); 1724 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1725 if (Universe::narrow_klass_base() != 0) { 1726 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1727 if (Universe::narrow_klass_shift() != 0) { 1728 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1729 } 1730 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1731 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1732 } else { 1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1734 } 1735 } else { 1736 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1737 } 1738 st->print_cr("\tCMP R_G5,R_G3" ); 1739 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1740 #else // _LP64 1741 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1742 st->print_cr("\tCMP R_G5,R_G3" ); 1743 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1744 #endif // _LP64 1745 } 1746 #endif 1747 1748 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1749 MacroAssembler _masm(&cbuf); 1750 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1751 Register temp_reg = G3; 1752 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1753 1754 // Load klass from receiver 1755 __ load_klass(O0, temp_reg); 1756 // Compare against expected klass 1757 __ cmp(temp_reg, G5_ic_reg); 1758 // Branch to miss code, checks xcc or icc depending 1759 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1760 } 1761 1762 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1763 return MachNode::size(ra_); 1764 } 1765 1766 1767 //============================================================================= 1768 1769 1770 // Emit exception handler code. 1771 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1772 Register temp_reg = G3; 1773 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1774 MacroAssembler _masm(&cbuf); 1775 1776 address base = __ start_a_stub(size_exception_handler()); 1777 if (base == NULL) { 1778 ciEnv::current()->record_failure("CodeCache is full"); 1779 return 0; // CodeBuffer::expand failed 1780 } 1781 1782 int offset = __ offset(); 1783 1784 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1785 __ delayed()->nop(); 1786 1787 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1788 1789 __ end_a_stub(); 1790 1791 return offset; 1792 } 1793 1794 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1795 // Can't use any of the current frame's registers as we may have deopted 1796 // at a poll and everything (including G3) can be live. 1797 Register temp_reg = L0; 1798 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1799 MacroAssembler _masm(&cbuf); 1800 1801 address base = __ start_a_stub(size_deopt_handler()); 1802 if (base == NULL) { 1803 ciEnv::current()->record_failure("CodeCache is full"); 1804 return 0; // CodeBuffer::expand failed 1805 } 1806 1807 int offset = __ offset(); 1808 __ save_frame(0); 1809 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1810 __ delayed()->restore(); 1811 1812 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1813 1814 __ end_a_stub(); 1815 return offset; 1816 1817 } 1818 1819 // Given a register encoding, produce a Integer Register object 1820 static Register reg_to_register_object(int register_encoding) { 1821 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1822 return as_Register(register_encoding); 1823 } 1824 1825 // Given a register encoding, produce a single-precision Float Register object 1826 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1827 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1828 return as_SingleFloatRegister(register_encoding); 1829 } 1830 1831 // Given a register encoding, produce a double-precision Float Register object 1832 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1833 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1834 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1835 return as_DoubleFloatRegister(register_encoding); 1836 } 1837 1838 const bool Matcher::match_rule_supported(int opcode) { 1839 if (!has_match_rule(opcode)) 1840 return false; 1841 1842 switch (opcode) { 1843 case Op_CountLeadingZerosI: 1844 case Op_CountLeadingZerosL: 1845 case Op_CountTrailingZerosI: 1846 case Op_CountTrailingZerosL: 1847 case Op_PopCountI: 1848 case Op_PopCountL: 1849 if (!UsePopCountInstruction) 1850 return false; 1851 case Op_CompareAndSwapL: 1852 #ifdef _LP64 1853 case Op_CompareAndSwapP: 1854 #endif 1855 if (!VM_Version::supports_cx8()) 1856 return false; 1857 break; 1858 } 1859 1860 return true; // Per default match rules are supported. 1861 } 1862 1863 const int Matcher::float_pressure(int default_pressure_threshold) { 1864 return default_pressure_threshold; 1865 } 1866 1867 int Matcher::regnum_to_fpu_offset(int regnum) { 1868 return regnum - 32; // The FP registers are in the second chunk 1869 } 1870 1871 #ifdef ASSERT 1872 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1873 #endif 1874 1875 // Vector width in bytes 1876 const int Matcher::vector_width_in_bytes(BasicType bt) { 1877 assert(MaxVectorSize == 8, ""); 1878 return 8; 1879 } 1880 1881 // Vector ideal reg 1882 const int Matcher::vector_ideal_reg(int size) { 1883 assert(MaxVectorSize == 8, ""); 1884 return Op_RegD; 1885 } 1886 1887 const int Matcher::vector_shift_count_ideal_reg(int size) { 1888 fatal("vector shift is not supported"); 1889 return Node::NotAMachineReg; 1890 } 1891 1892 // Limits on vector size (number of elements) loaded into vector. 1893 const int Matcher::max_vector_size(const BasicType bt) { 1894 assert(is_java_primitive(bt), "only primitive type vectors"); 1895 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1896 } 1897 1898 const int Matcher::min_vector_size(const BasicType bt) { 1899 return max_vector_size(bt); // Same as max. 1900 } 1901 1902 // SPARC doesn't support misaligned vectors store/load. 1903 const bool Matcher::misaligned_vectors_ok() { 1904 return false; 1905 } 1906 1907 // Current (2013) SPARC platforms need to read original key 1908 // to construct decryption expanded key 1909 const bool Matcher::pass_original_key_for_aes() { 1910 return true; 1911 } 1912 1913 // USII supports fxtof through the whole range of number, USIII doesn't 1914 const bool Matcher::convL2FSupported(void) { 1915 return VM_Version::has_fast_fxtof(); 1916 } 1917 1918 // Is this branch offset short enough that a short branch can be used? 1919 // 1920 // NOTE: If the platform does not provide any short branch variants, then 1921 // this method should return false for offset 0. 1922 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1923 // The passed offset is relative to address of the branch. 1924 // Don't need to adjust the offset. 1925 return UseCBCond && Assembler::is_simm12(offset); 1926 } 1927 1928 const bool Matcher::isSimpleConstant64(jlong value) { 1929 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1930 // Depends on optimizations in MacroAssembler::setx. 1931 int hi = (int)(value >> 32); 1932 int lo = (int)(value & ~0); 1933 return (hi == 0) || (hi == -1) || (lo == 0); 1934 } 1935 1936 // No scaling for the parameter the ClearArray node. 1937 const bool Matcher::init_array_count_is_in_bytes = true; 1938 1939 // Threshold size for cleararray. 1940 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1941 1942 // No additional cost for CMOVL. 1943 const int Matcher::long_cmove_cost() { return 0; } 1944 1945 // CMOVF/CMOVD are expensive on T4 and on SPARC64. 1946 const int Matcher::float_cmove_cost() { 1947 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; 1948 } 1949 1950 // Does the CPU require late expand (see block.cpp for description of late expand)? 1951 const bool Matcher::require_postalloc_expand = false; 1952 1953 // Should the Matcher clone shifts on addressing modes, expecting them to 1954 // be subsumed into complex addressing expressions or compute them into 1955 // registers? True for Intel but false for most RISCs 1956 const bool Matcher::clone_shift_expressions = false; 1957 1958 // Do we need to mask the count passed to shift instructions or does 1959 // the cpu only look at the lower 5/6 bits anyway? 1960 const bool Matcher::need_masked_shift_count = false; 1961 1962 bool Matcher::narrow_oop_use_complex_address() { 1963 NOT_LP64(ShouldNotCallThis()); 1964 assert(UseCompressedOops, "only for compressed oops code"); 1965 return false; 1966 } 1967 1968 bool Matcher::narrow_klass_use_complex_address() { 1969 NOT_LP64(ShouldNotCallThis()); 1970 assert(UseCompressedClassPointers, "only for compressed klass code"); 1971 return false; 1972 } 1973 1974 // Is it better to copy float constants, or load them directly from memory? 1975 // Intel can load a float constant from a direct address, requiring no 1976 // extra registers. Most RISCs will have to materialize an address into a 1977 // register first, so they would do better to copy the constant from stack. 1978 const bool Matcher::rematerialize_float_constants = false; 1979 1980 // If CPU can load and store mis-aligned doubles directly then no fixup is 1981 // needed. Else we split the double into 2 integer pieces and move it 1982 // piece-by-piece. Only happens when passing doubles into C code as the 1983 // Java calling convention forces doubles to be aligned. 1984 #ifdef _LP64 1985 const bool Matcher::misaligned_doubles_ok = true; 1986 #else 1987 const bool Matcher::misaligned_doubles_ok = false; 1988 #endif 1989 1990 // No-op on SPARC. 1991 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1992 } 1993 1994 // Advertise here if the CPU requires explicit rounding operations 1995 // to implement the UseStrictFP mode. 1996 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1997 1998 // Are floats converted to double when stored to stack during deoptimization? 1999 // Sparc does not handle callee-save floats. 2000 bool Matcher::float_in_double() { return false; } 2001 2002 // Do ints take an entire long register or just half? 2003 // Note that we if-def off of _LP64. 2004 // The relevant question is how the int is callee-saved. In _LP64 2005 // the whole long is written but de-opt'ing will have to extract 2006 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 2007 #ifdef _LP64 2008 const bool Matcher::int_in_long = true; 2009 #else 2010 const bool Matcher::int_in_long = false; 2011 #endif 2012 2013 // Return whether or not this register is ever used as an argument. This 2014 // function is used on startup to build the trampoline stubs in generateOptoStub. 2015 // Registers not mentioned will be killed by the VM call in the trampoline, and 2016 // arguments in those registers not be available to the callee. 2017 bool Matcher::can_be_java_arg( int reg ) { 2018 // Standard sparc 6 args in registers 2019 if( reg == R_I0_num || 2020 reg == R_I1_num || 2021 reg == R_I2_num || 2022 reg == R_I3_num || 2023 reg == R_I4_num || 2024 reg == R_I5_num ) return true; 2025 #ifdef _LP64 2026 // 64-bit builds can pass 64-bit pointers and longs in 2027 // the high I registers 2028 if( reg == R_I0H_num || 2029 reg == R_I1H_num || 2030 reg == R_I2H_num || 2031 reg == R_I3H_num || 2032 reg == R_I4H_num || 2033 reg == R_I5H_num ) return true; 2034 2035 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 2036 return true; 2037 } 2038 2039 #else 2040 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 2041 // Longs cannot be passed in O regs, because O regs become I regs 2042 // after a 'save' and I regs get their high bits chopped off on 2043 // interrupt. 2044 if( reg == R_G1H_num || reg == R_G1_num ) return true; 2045 if( reg == R_G4H_num || reg == R_G4_num ) return true; 2046 #endif 2047 // A few float args in registers 2048 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 2049 2050 return false; 2051 } 2052 2053 bool Matcher::is_spillable_arg( int reg ) { 2054 return can_be_java_arg(reg); 2055 } 2056 2057 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 2058 // Use hardware SDIVX instruction when it is 2059 // faster than a code which use multiply. 2060 return VM_Version::has_fast_idiv(); 2061 } 2062 2063 // Register for DIVI projection of divmodI 2064 RegMask Matcher::divI_proj_mask() { 2065 ShouldNotReachHere(); 2066 return RegMask(); 2067 } 2068 2069 // Register for MODI projection of divmodI 2070 RegMask Matcher::modI_proj_mask() { 2071 ShouldNotReachHere(); 2072 return RegMask(); 2073 } 2074 2075 // Register for DIVL projection of divmodL 2076 RegMask Matcher::divL_proj_mask() { 2077 ShouldNotReachHere(); 2078 return RegMask(); 2079 } 2080 2081 // Register for MODL projection of divmodL 2082 RegMask Matcher::modL_proj_mask() { 2083 ShouldNotReachHere(); 2084 return RegMask(); 2085 } 2086 2087 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2088 return L7_REGP_mask(); 2089 } 2090 2091 %} 2092 2093 2094 // The intptr_t operand types, defined by textual substitution. 2095 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 2096 #ifdef _LP64 2097 #define immX immL 2098 #define immX13 immL13 2099 #define immX13m7 immL13m7 2100 #define iRegX iRegL 2101 #define g1RegX g1RegL 2102 #else 2103 #define immX immI 2104 #define immX13 immI13 2105 #define immX13m7 immI13m7 2106 #define iRegX iRegI 2107 #define g1RegX g1RegI 2108 #endif 2109 2110 //----------ENCODING BLOCK----------------------------------------------------- 2111 // This block specifies the encoding classes used by the compiler to output 2112 // byte streams. Encoding classes are parameterized macros used by 2113 // Machine Instruction Nodes in order to generate the bit encoding of the 2114 // instruction. Operands specify their base encoding interface with the 2115 // interface keyword. There are currently supported four interfaces, 2116 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2117 // operand to generate a function which returns its register number when 2118 // queried. CONST_INTER causes an operand to generate a function which 2119 // returns the value of the constant when queried. MEMORY_INTER causes an 2120 // operand to generate four functions which return the Base Register, the 2121 // Index Register, the Scale Value, and the Offset Value of the operand when 2122 // queried. COND_INTER causes an operand to generate six functions which 2123 // return the encoding code (ie - encoding bits for the instruction) 2124 // associated with each basic boolean condition for a conditional instruction. 2125 // 2126 // Instructions specify two basic values for encoding. Again, a function 2127 // is available to check if the constant displacement is an oop. They use the 2128 // ins_encode keyword to specify their encoding classes (which must be 2129 // a sequence of enc_class names, and their parameters, specified in 2130 // the encoding block), and they use the 2131 // opcode keyword to specify, in order, their primary, secondary, and 2132 // tertiary opcode. Only the opcode sections which a particular instruction 2133 // needs for encoding need to be specified. 2134 encode %{ 2135 enc_class enc_untested %{ 2136 #ifdef ASSERT 2137 MacroAssembler _masm(&cbuf); 2138 __ untested("encoding"); 2139 #endif 2140 %} 2141 2142 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2143 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 2144 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2145 %} 2146 2147 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2148 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2149 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2150 %} 2151 2152 enc_class form3_mem_prefetch_read( memory mem ) %{ 2153 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2154 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2155 %} 2156 2157 enc_class form3_mem_prefetch_write( memory mem ) %{ 2158 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2159 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2160 %} 2161 2162 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2163 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2164 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2165 guarantee($mem$$index == R_G0_enc, "double index?"); 2166 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2167 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2168 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2169 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2170 %} 2171 2172 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2173 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2174 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2175 guarantee($mem$$index == R_G0_enc, "double index?"); 2176 // Load long with 2 instructions 2177 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2178 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2179 %} 2180 2181 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2182 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2183 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2184 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2185 %} 2186 2187 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2188 // Encode a reg-reg copy. If it is useless, then empty encoding. 2189 if( $rs2$$reg != $rd$$reg ) 2190 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2191 %} 2192 2193 // Target lo half of long 2194 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2195 // Encode a reg-reg copy. If it is useless, then empty encoding. 2196 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2197 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2198 %} 2199 2200 // Source lo half of long 2201 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2202 // Encode a reg-reg copy. If it is useless, then empty encoding. 2203 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2204 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2205 %} 2206 2207 // Target hi half of long 2208 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2209 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2210 %} 2211 2212 // Source lo half of long, and leave it sign extended. 2213 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2214 // Sign extend low half 2215 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2216 %} 2217 2218 // Source hi half of long, and leave it sign extended. 2219 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2220 // Shift high half to low half 2221 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2222 %} 2223 2224 // Source hi half of long 2225 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2226 // Encode a reg-reg copy. If it is useless, then empty encoding. 2227 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2228 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2229 %} 2230 2231 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2232 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2233 %} 2234 2235 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2236 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2237 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2238 %} 2239 2240 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2241 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2242 // clear if nothing else is happening 2243 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2244 // blt,a,pn done 2245 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2246 // mov dst,-1 in delay slot 2247 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2248 %} 2249 2250 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2251 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2252 %} 2253 2254 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2255 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2256 %} 2257 2258 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2259 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2260 %} 2261 2262 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2263 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2264 %} 2265 2266 enc_class move_return_pc_to_o1() %{ 2267 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2268 %} 2269 2270 #ifdef _LP64 2271 /* %%% merge with enc_to_bool */ 2272 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2273 MacroAssembler _masm(&cbuf); 2274 2275 Register src_reg = reg_to_register_object($src$$reg); 2276 Register dst_reg = reg_to_register_object($dst$$reg); 2277 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2278 %} 2279 #endif 2280 2281 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2282 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2283 MacroAssembler _masm(&cbuf); 2284 2285 Register p_reg = reg_to_register_object($p$$reg); 2286 Register q_reg = reg_to_register_object($q$$reg); 2287 Register y_reg = reg_to_register_object($y$$reg); 2288 Register tmp_reg = reg_to_register_object($tmp$$reg); 2289 2290 __ subcc( p_reg, q_reg, p_reg ); 2291 __ add ( p_reg, y_reg, tmp_reg ); 2292 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2293 %} 2294 2295 enc_class form_d2i_helper(regD src, regF dst) %{ 2296 // fcmp %fcc0,$src,$src 2297 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2298 // branch %fcc0 not-nan, predict taken 2299 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2300 // fdtoi $src,$dst 2301 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2302 // fitos $dst,$dst (if nan) 2303 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2304 // clear $dst (if nan) 2305 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2306 // carry on here... 2307 %} 2308 2309 enc_class form_d2l_helper(regD src, regD dst) %{ 2310 // fcmp %fcc0,$src,$src check for NAN 2311 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2312 // branch %fcc0 not-nan, predict taken 2313 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2314 // fdtox $src,$dst convert in delay slot 2315 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2316 // fxtod $dst,$dst (if nan) 2317 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2318 // clear $dst (if nan) 2319 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2320 // carry on here... 2321 %} 2322 2323 enc_class form_f2i_helper(regF src, regF dst) %{ 2324 // fcmps %fcc0,$src,$src 2325 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2326 // branch %fcc0 not-nan, predict taken 2327 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2328 // fstoi $src,$dst 2329 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2330 // fitos $dst,$dst (if nan) 2331 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2332 // clear $dst (if nan) 2333 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2334 // carry on here... 2335 %} 2336 2337 enc_class form_f2l_helper(regF src, regD dst) %{ 2338 // fcmps %fcc0,$src,$src 2339 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2340 // branch %fcc0 not-nan, predict taken 2341 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2342 // fstox $src,$dst 2343 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2344 // fxtod $dst,$dst (if nan) 2345 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2346 // clear $dst (if nan) 2347 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2348 // carry on here... 2349 %} 2350 2351 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2352 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2353 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2354 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2355 2356 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2357 2358 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2359 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2360 2361 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2362 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2363 %} 2364 2365 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2366 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2367 %} 2368 2369 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2370 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2371 %} 2372 2373 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2374 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2375 %} 2376 2377 enc_class form3_convI2F(regF rs2, regF rd) %{ 2378 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2379 %} 2380 2381 // Encloding class for traceable jumps 2382 enc_class form_jmpl(g3RegP dest) %{ 2383 emit_jmpl(cbuf, $dest$$reg); 2384 %} 2385 2386 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2387 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2388 %} 2389 2390 enc_class form2_nop() %{ 2391 emit_nop(cbuf); 2392 %} 2393 2394 enc_class form2_illtrap() %{ 2395 emit_illtrap(cbuf); 2396 %} 2397 2398 2399 // Compare longs and convert into -1, 0, 1. 2400 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2401 // CMP $src1,$src2 2402 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2403 // blt,a,pn done 2404 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2405 // mov dst,-1 in delay slot 2406 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2407 // bgt,a,pn done 2408 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2409 // mov dst,1 in delay slot 2410 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2411 // CLR $dst 2412 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2413 %} 2414 2415 enc_class enc_PartialSubtypeCheck() %{ 2416 MacroAssembler _masm(&cbuf); 2417 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2418 __ delayed()->nop(); 2419 %} 2420 2421 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2422 MacroAssembler _masm(&cbuf); 2423 Label* L = $labl$$label; 2424 Assembler::Predict predict_taken = 2425 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2426 2427 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2428 __ delayed()->nop(); 2429 %} 2430 2431 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2432 MacroAssembler _masm(&cbuf); 2433 Label* L = $labl$$label; 2434 Assembler::Predict predict_taken = 2435 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2436 2437 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2438 __ delayed()->nop(); 2439 %} 2440 2441 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2442 int op = (Assembler::arith_op << 30) | 2443 ($dst$$reg << 25) | 2444 (Assembler::movcc_op3 << 19) | 2445 (1 << 18) | // cc2 bit for 'icc' 2446 ($cmp$$cmpcode << 14) | 2447 (0 << 13) | // select register move 2448 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2449 ($src$$reg << 0); 2450 cbuf.insts()->emit_int32(op); 2451 %} 2452 2453 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2454 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2455 int op = (Assembler::arith_op << 30) | 2456 ($dst$$reg << 25) | 2457 (Assembler::movcc_op3 << 19) | 2458 (1 << 18) | // cc2 bit for 'icc' 2459 ($cmp$$cmpcode << 14) | 2460 (1 << 13) | // select immediate move 2461 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2462 (simm11 << 0); 2463 cbuf.insts()->emit_int32(op); 2464 %} 2465 2466 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2467 int op = (Assembler::arith_op << 30) | 2468 ($dst$$reg << 25) | 2469 (Assembler::movcc_op3 << 19) | 2470 (0 << 18) | // cc2 bit for 'fccX' 2471 ($cmp$$cmpcode << 14) | 2472 (0 << 13) | // select register move 2473 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2474 ($src$$reg << 0); 2475 cbuf.insts()->emit_int32(op); 2476 %} 2477 2478 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2479 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2480 int op = (Assembler::arith_op << 30) | 2481 ($dst$$reg << 25) | 2482 (Assembler::movcc_op3 << 19) | 2483 (0 << 18) | // cc2 bit for 'fccX' 2484 ($cmp$$cmpcode << 14) | 2485 (1 << 13) | // select immediate move 2486 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2487 (simm11 << 0); 2488 cbuf.insts()->emit_int32(op); 2489 %} 2490 2491 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2492 int op = (Assembler::arith_op << 30) | 2493 ($dst$$reg << 25) | 2494 (Assembler::fpop2_op3 << 19) | 2495 (0 << 18) | 2496 ($cmp$$cmpcode << 14) | 2497 (1 << 13) | // select register move 2498 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2499 ($primary << 5) | // select single, double or quad 2500 ($src$$reg << 0); 2501 cbuf.insts()->emit_int32(op); 2502 %} 2503 2504 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2505 int op = (Assembler::arith_op << 30) | 2506 ($dst$$reg << 25) | 2507 (Assembler::fpop2_op3 << 19) | 2508 (0 << 18) | 2509 ($cmp$$cmpcode << 14) | 2510 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2511 ($primary << 5) | // select single, double or quad 2512 ($src$$reg << 0); 2513 cbuf.insts()->emit_int32(op); 2514 %} 2515 2516 // Used by the MIN/MAX encodings. Same as a CMOV, but 2517 // the condition comes from opcode-field instead of an argument. 2518 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2519 int op = (Assembler::arith_op << 30) | 2520 ($dst$$reg << 25) | 2521 (Assembler::movcc_op3 << 19) | 2522 (1 << 18) | // cc2 bit for 'icc' 2523 ($primary << 14) | 2524 (0 << 13) | // select register move 2525 (0 << 11) | // cc1, cc0 bits for 'icc' 2526 ($src$$reg << 0); 2527 cbuf.insts()->emit_int32(op); 2528 %} 2529 2530 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2531 int op = (Assembler::arith_op << 30) | 2532 ($dst$$reg << 25) | 2533 (Assembler::movcc_op3 << 19) | 2534 (6 << 16) | // cc2 bit for 'xcc' 2535 ($primary << 14) | 2536 (0 << 13) | // select register move 2537 (0 << 11) | // cc1, cc0 bits for 'icc' 2538 ($src$$reg << 0); 2539 cbuf.insts()->emit_int32(op); 2540 %} 2541 2542 enc_class Set13( immI13 src, iRegI rd ) %{ 2543 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2544 %} 2545 2546 enc_class SetHi22( immI src, iRegI rd ) %{ 2547 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2548 %} 2549 2550 enc_class Set32( immI src, iRegI rd ) %{ 2551 MacroAssembler _masm(&cbuf); 2552 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2553 %} 2554 2555 enc_class call_epilog %{ 2556 if( VerifyStackAtCalls ) { 2557 MacroAssembler _masm(&cbuf); 2558 int framesize = ra_->C->frame_size_in_bytes(); 2559 Register temp_reg = G3; 2560 __ add(SP, framesize, temp_reg); 2561 __ cmp(temp_reg, FP); 2562 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2563 } 2564 %} 2565 2566 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2567 // to G1 so the register allocator will not have to deal with the misaligned register 2568 // pair. 2569 enc_class adjust_long_from_native_call %{ 2570 #ifndef _LP64 2571 if (returns_long()) { 2572 // sllx O0,32,O0 2573 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2574 // srl O1,0,O1 2575 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2576 // or O0,O1,G1 2577 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2578 } 2579 #endif 2580 %} 2581 2582 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2583 // CALL directly to the runtime 2584 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2585 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2586 /*preserve_g2=*/true); 2587 %} 2588 2589 enc_class preserve_SP %{ 2590 MacroAssembler _masm(&cbuf); 2591 __ mov(SP, L7_mh_SP_save); 2592 %} 2593 2594 enc_class restore_SP %{ 2595 MacroAssembler _masm(&cbuf); 2596 __ mov(L7_mh_SP_save, SP); 2597 %} 2598 2599 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2600 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2601 // who we intended to call. 2602 if (!_method) { 2603 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2604 } else if (_optimized_virtual) { 2605 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2606 } else { 2607 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2608 } 2609 if (_method) { // Emit stub for static call. 2610 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2611 // Stub does not fit into scratch buffer if TraceJumps is enabled 2612 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) { 2613 ciEnv::current()->record_failure("CodeCache is full"); 2614 return; 2615 } 2616 } 2617 %} 2618 2619 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2620 MacroAssembler _masm(&cbuf); 2621 __ set_inst_mark(); 2622 int vtable_index = this->_vtable_index; 2623 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2624 if (vtable_index < 0) { 2625 // must be invalid_vtable_index, not nonvirtual_vtable_index 2626 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2627 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2628 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2629 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2630 __ ic_call((address)$meth$$method); 2631 } else { 2632 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2633 // Just go thru the vtable 2634 // get receiver klass (receiver already checked for non-null) 2635 // If we end up going thru a c2i adapter interpreter expects method in G5 2636 int off = __ offset(); 2637 __ load_klass(O0, G3_scratch); 2638 int klass_load_size; 2639 if (UseCompressedClassPointers) { 2640 assert(Universe::heap() != NULL, "java heap should be initialized"); 2641 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2642 } else { 2643 klass_load_size = 1*BytesPerInstWord; 2644 } 2645 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2646 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2647 if (Assembler::is_simm13(v_off)) { 2648 __ ld_ptr(G3, v_off, G5_method); 2649 } else { 2650 // Generate 2 instructions 2651 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2652 __ or3(G5_method, v_off & 0x3ff, G5_method); 2653 // ld_ptr, set_hi, set 2654 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2655 "Unexpected instruction size(s)"); 2656 __ ld_ptr(G3, G5_method, G5_method); 2657 } 2658 // NOTE: for vtable dispatches, the vtable entry will never be null. 2659 // However it may very well end up in handle_wrong_method if the 2660 // method is abstract for the particular class. 2661 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2662 // jump to target (either compiled code or c2iadapter) 2663 __ jmpl(G3_scratch, G0, O7); 2664 __ delayed()->nop(); 2665 } 2666 %} 2667 2668 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2669 MacroAssembler _masm(&cbuf); 2670 2671 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2672 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2673 // we might be calling a C2I adapter which needs it. 2674 2675 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2676 // Load nmethod 2677 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2678 2679 // CALL to compiled java, indirect the contents of G3 2680 __ set_inst_mark(); 2681 __ callr(temp_reg, G0); 2682 __ delayed()->nop(); 2683 %} 2684 2685 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2686 MacroAssembler _masm(&cbuf); 2687 Register Rdividend = reg_to_register_object($src1$$reg); 2688 Register Rdivisor = reg_to_register_object($src2$$reg); 2689 Register Rresult = reg_to_register_object($dst$$reg); 2690 2691 __ sra(Rdivisor, 0, Rdivisor); 2692 __ sra(Rdividend, 0, Rdividend); 2693 __ sdivx(Rdividend, Rdivisor, Rresult); 2694 %} 2695 2696 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2697 MacroAssembler _masm(&cbuf); 2698 2699 Register Rdividend = reg_to_register_object($src1$$reg); 2700 int divisor = $imm$$constant; 2701 Register Rresult = reg_to_register_object($dst$$reg); 2702 2703 __ sra(Rdividend, 0, Rdividend); 2704 __ sdivx(Rdividend, divisor, Rresult); 2705 %} 2706 2707 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2708 MacroAssembler _masm(&cbuf); 2709 Register Rsrc1 = reg_to_register_object($src1$$reg); 2710 Register Rsrc2 = reg_to_register_object($src2$$reg); 2711 Register Rdst = reg_to_register_object($dst$$reg); 2712 2713 __ sra( Rsrc1, 0, Rsrc1 ); 2714 __ sra( Rsrc2, 0, Rsrc2 ); 2715 __ mulx( Rsrc1, Rsrc2, Rdst ); 2716 __ srlx( Rdst, 32, Rdst ); 2717 %} 2718 2719 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2720 MacroAssembler _masm(&cbuf); 2721 Register Rdividend = reg_to_register_object($src1$$reg); 2722 Register Rdivisor = reg_to_register_object($src2$$reg); 2723 Register Rresult = reg_to_register_object($dst$$reg); 2724 Register Rscratch = reg_to_register_object($scratch$$reg); 2725 2726 assert(Rdividend != Rscratch, ""); 2727 assert(Rdivisor != Rscratch, ""); 2728 2729 __ sra(Rdividend, 0, Rdividend); 2730 __ sra(Rdivisor, 0, Rdivisor); 2731 __ sdivx(Rdividend, Rdivisor, Rscratch); 2732 __ mulx(Rscratch, Rdivisor, Rscratch); 2733 __ sub(Rdividend, Rscratch, Rresult); 2734 %} 2735 2736 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2737 MacroAssembler _masm(&cbuf); 2738 2739 Register Rdividend = reg_to_register_object($src1$$reg); 2740 int divisor = $imm$$constant; 2741 Register Rresult = reg_to_register_object($dst$$reg); 2742 Register Rscratch = reg_to_register_object($scratch$$reg); 2743 2744 assert(Rdividend != Rscratch, ""); 2745 2746 __ sra(Rdividend, 0, Rdividend); 2747 __ sdivx(Rdividend, divisor, Rscratch); 2748 __ mulx(Rscratch, divisor, Rscratch); 2749 __ sub(Rdividend, Rscratch, Rresult); 2750 %} 2751 2752 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2753 MacroAssembler _masm(&cbuf); 2754 2755 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2756 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2757 2758 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2759 %} 2760 2761 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2762 MacroAssembler _masm(&cbuf); 2763 2764 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2765 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2766 2767 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2768 %} 2769 2770 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2771 MacroAssembler _masm(&cbuf); 2772 2773 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2774 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2775 2776 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2777 %} 2778 2779 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2780 MacroAssembler _masm(&cbuf); 2781 2782 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2783 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2784 2785 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2786 %} 2787 2788 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2789 MacroAssembler _masm(&cbuf); 2790 2791 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2792 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2793 2794 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2795 %} 2796 2797 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2798 MacroAssembler _masm(&cbuf); 2799 2800 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2801 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2802 2803 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2804 %} 2805 2806 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2807 MacroAssembler _masm(&cbuf); 2808 2809 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2810 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2811 2812 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2813 %} 2814 2815 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2816 MacroAssembler _masm(&cbuf); 2817 2818 Register Roop = reg_to_register_object($oop$$reg); 2819 Register Rbox = reg_to_register_object($box$$reg); 2820 Register Rscratch = reg_to_register_object($scratch$$reg); 2821 Register Rmark = reg_to_register_object($scratch2$$reg); 2822 2823 assert(Roop != Rscratch, ""); 2824 assert(Roop != Rmark, ""); 2825 assert(Rbox != Rscratch, ""); 2826 assert(Rbox != Rmark, ""); 2827 2828 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2829 %} 2830 2831 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2832 MacroAssembler _masm(&cbuf); 2833 2834 Register Roop = reg_to_register_object($oop$$reg); 2835 Register Rbox = reg_to_register_object($box$$reg); 2836 Register Rscratch = reg_to_register_object($scratch$$reg); 2837 Register Rmark = reg_to_register_object($scratch2$$reg); 2838 2839 assert(Roop != Rscratch, ""); 2840 assert(Roop != Rmark, ""); 2841 assert(Rbox != Rscratch, ""); 2842 assert(Rbox != Rmark, ""); 2843 2844 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2845 %} 2846 2847 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2848 MacroAssembler _masm(&cbuf); 2849 Register Rmem = reg_to_register_object($mem$$reg); 2850 Register Rold = reg_to_register_object($old$$reg); 2851 Register Rnew = reg_to_register_object($new$$reg); 2852 2853 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2854 __ cmp( Rold, Rnew ); 2855 %} 2856 2857 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2858 Register Rmem = reg_to_register_object($mem$$reg); 2859 Register Rold = reg_to_register_object($old$$reg); 2860 Register Rnew = reg_to_register_object($new$$reg); 2861 2862 MacroAssembler _masm(&cbuf); 2863 __ mov(Rnew, O7); 2864 __ casx(Rmem, Rold, O7); 2865 __ cmp( Rold, O7 ); 2866 %} 2867 2868 // raw int cas, used for compareAndSwap 2869 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2870 Register Rmem = reg_to_register_object($mem$$reg); 2871 Register Rold = reg_to_register_object($old$$reg); 2872 Register Rnew = reg_to_register_object($new$$reg); 2873 2874 MacroAssembler _masm(&cbuf); 2875 __ mov(Rnew, O7); 2876 __ cas(Rmem, Rold, O7); 2877 __ cmp( Rold, O7 ); 2878 %} 2879 2880 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2881 Register Rres = reg_to_register_object($res$$reg); 2882 2883 MacroAssembler _masm(&cbuf); 2884 __ mov(1, Rres); 2885 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2886 %} 2887 2888 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2889 Register Rres = reg_to_register_object($res$$reg); 2890 2891 MacroAssembler _masm(&cbuf); 2892 __ mov(1, Rres); 2893 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2894 %} 2895 2896 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2897 MacroAssembler _masm(&cbuf); 2898 Register Rdst = reg_to_register_object($dst$$reg); 2899 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2900 : reg_to_DoubleFloatRegister_object($src1$$reg); 2901 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2902 : reg_to_DoubleFloatRegister_object($src2$$reg); 2903 2904 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2905 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2906 %} 2907 2908 2909 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2910 Label Ldone, Lloop; 2911 MacroAssembler _masm(&cbuf); 2912 2913 Register str1_reg = reg_to_register_object($str1$$reg); 2914 Register str2_reg = reg_to_register_object($str2$$reg); 2915 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2916 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2917 Register result_reg = reg_to_register_object($result$$reg); 2918 2919 assert(result_reg != str1_reg && 2920 result_reg != str2_reg && 2921 result_reg != cnt1_reg && 2922 result_reg != cnt2_reg , 2923 "need different registers"); 2924 2925 // Compute the minimum of the string lengths(str1_reg) and the 2926 // difference of the string lengths (stack) 2927 2928 // See if the lengths are different, and calculate min in str1_reg. 2929 // Stash diff in O7 in case we need it for a tie-breaker. 2930 Label Lskip; 2931 __ subcc(cnt1_reg, cnt2_reg, O7); 2932 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2933 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2934 // cnt2 is shorter, so use its count: 2935 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2936 __ bind(Lskip); 2937 2938 // reallocate cnt1_reg, cnt2_reg, result_reg 2939 // Note: limit_reg holds the string length pre-scaled by 2 2940 Register limit_reg = cnt1_reg; 2941 Register chr2_reg = cnt2_reg; 2942 Register chr1_reg = result_reg; 2943 // str{12} are the base pointers 2944 2945 // Is the minimum length zero? 2946 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2947 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2948 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2949 2950 // Load first characters 2951 __ lduh(str1_reg, 0, chr1_reg); 2952 __ lduh(str2_reg, 0, chr2_reg); 2953 2954 // Compare first characters 2955 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2956 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2957 assert(chr1_reg == result_reg, "result must be pre-placed"); 2958 __ delayed()->nop(); 2959 2960 { 2961 // Check after comparing first character to see if strings are equivalent 2962 Label LSkip2; 2963 // Check if the strings start at same location 2964 __ cmp(str1_reg, str2_reg); 2965 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2966 __ delayed()->nop(); 2967 2968 // Check if the length difference is zero (in O7) 2969 __ cmp(G0, O7); 2970 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2971 __ delayed()->mov(G0, result_reg); // result is zero 2972 2973 // Strings might not be equal 2974 __ bind(LSkip2); 2975 } 2976 2977 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 2978 __ signx(limit_reg); 2979 2980 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2981 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2982 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2983 2984 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2985 __ add(str1_reg, limit_reg, str1_reg); 2986 __ add(str2_reg, limit_reg, str2_reg); 2987 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2988 2989 // Compare the rest of the characters 2990 __ lduh(str1_reg, limit_reg, chr1_reg); 2991 __ bind(Lloop); 2992 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2993 __ lduh(str2_reg, limit_reg, chr2_reg); 2994 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2995 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2996 assert(chr1_reg == result_reg, "result must be pre-placed"); 2997 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2998 // annul LDUH if branch is not taken to prevent access past end of string 2999 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 3000 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 3001 3002 // If strings are equal up to min length, return the length difference. 3003 __ mov(O7, result_reg); 3004 3005 // Otherwise, return the difference between the first mismatched chars. 3006 __ bind(Ldone); 3007 %} 3008 3009 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 3010 Label Lchar, Lchar_loop, Ldone; 3011 MacroAssembler _masm(&cbuf); 3012 3013 Register str1_reg = reg_to_register_object($str1$$reg); 3014 Register str2_reg = reg_to_register_object($str2$$reg); 3015 Register cnt_reg = reg_to_register_object($cnt$$reg); 3016 Register tmp1_reg = O7; 3017 Register result_reg = reg_to_register_object($result$$reg); 3018 3019 assert(result_reg != str1_reg && 3020 result_reg != str2_reg && 3021 result_reg != cnt_reg && 3022 result_reg != tmp1_reg , 3023 "need different registers"); 3024 3025 __ cmp(str1_reg, str2_reg); //same char[] ? 3026 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3027 __ delayed()->add(G0, 1, result_reg); 3028 3029 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); 3030 __ delayed()->add(G0, 1, result_reg); // count == 0 3031 3032 //rename registers 3033 Register limit_reg = cnt_reg; 3034 Register chr1_reg = result_reg; 3035 Register chr2_reg = tmp1_reg; 3036 3037 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 3038 __ signx(limit_reg); 3039 3040 //check for alignment and position the pointers to the ends 3041 __ or3(str1_reg, str2_reg, chr1_reg); 3042 __ andcc(chr1_reg, 0x3, chr1_reg); 3043 // notZero means at least one not 4-byte aligned. 3044 // We could optimize the case when both arrays are not aligned 3045 // but it is not frequent case and it requires additional checks. 3046 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 3047 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 3048 3049 // Compare char[] arrays aligned to 4 bytes. 3050 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 3051 chr1_reg, chr2_reg, Ldone); 3052 __ ba(Ldone); 3053 __ delayed()->add(G0, 1, result_reg); 3054 3055 // char by char compare 3056 __ bind(Lchar); 3057 __ add(str1_reg, limit_reg, str1_reg); 3058 __ add(str2_reg, limit_reg, str2_reg); 3059 __ neg(limit_reg); //negate count 3060 3061 __ lduh(str1_reg, limit_reg, chr1_reg); 3062 // Lchar_loop 3063 __ bind(Lchar_loop); 3064 __ lduh(str2_reg, limit_reg, chr2_reg); 3065 __ cmp(chr1_reg, chr2_reg); 3066 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3067 __ delayed()->mov(G0, result_reg); //not equal 3068 __ inccc(limit_reg, sizeof(jchar)); 3069 // annul LDUH if branch is not taken to prevent access past end of string 3070 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 3071 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 3072 3073 __ add(G0, 1, result_reg); //equal 3074 3075 __ bind(Ldone); 3076 %} 3077 3078 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 3079 Label Lvector, Ldone, Lloop; 3080 MacroAssembler _masm(&cbuf); 3081 3082 Register ary1_reg = reg_to_register_object($ary1$$reg); 3083 Register ary2_reg = reg_to_register_object($ary2$$reg); 3084 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3085 Register tmp2_reg = O7; 3086 Register result_reg = reg_to_register_object($result$$reg); 3087 3088 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3089 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3090 3091 // return true if the same array 3092 __ cmp(ary1_reg, ary2_reg); 3093 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3094 __ delayed()->add(G0, 1, result_reg); // equal 3095 3096 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3097 __ delayed()->mov(G0, result_reg); // not equal 3098 3099 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3100 __ delayed()->mov(G0, result_reg); // not equal 3101 3102 //load the lengths of arrays 3103 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3104 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3105 3106 // return false if the two arrays are not equal length 3107 __ cmp(tmp1_reg, tmp2_reg); 3108 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3109 __ delayed()->mov(G0, result_reg); // not equal 3110 3111 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); 3112 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3113 3114 // load array addresses 3115 __ add(ary1_reg, base_offset, ary1_reg); 3116 __ add(ary2_reg, base_offset, ary2_reg); 3117 3118 // renaming registers 3119 Register chr1_reg = result_reg; // for characters in ary1 3120 Register chr2_reg = tmp2_reg; // for characters in ary2 3121 Register limit_reg = tmp1_reg; // length 3122 3123 // set byte count 3124 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3125 3126 // Compare char[] arrays aligned to 4 bytes. 3127 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3128 chr1_reg, chr2_reg, Ldone); 3129 __ add(G0, 1, result_reg); // equals 3130 3131 __ bind(Ldone); 3132 %} 3133 3134 enc_class enc_rethrow() %{ 3135 cbuf.set_insts_mark(); 3136 Register temp_reg = G3; 3137 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3138 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3139 MacroAssembler _masm(&cbuf); 3140 #ifdef ASSERT 3141 __ save_frame(0); 3142 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3143 __ sethi(last_rethrow_addrlit, L1); 3144 Address addr(L1, last_rethrow_addrlit.low10()); 3145 __ rdpc(L2); 3146 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3147 __ st_ptr(L2, addr); 3148 __ restore(); 3149 #endif 3150 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3151 __ delayed()->nop(); 3152 %} 3153 3154 enc_class emit_mem_nop() %{ 3155 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3156 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3157 %} 3158 3159 enc_class emit_fadd_nop() %{ 3160 // Generates the instruction FMOVS f31,f31 3161 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3162 %} 3163 3164 enc_class emit_br_nop() %{ 3165 // Generates the instruction BPN,PN . 3166 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3167 %} 3168 3169 enc_class enc_membar_acquire %{ 3170 MacroAssembler _masm(&cbuf); 3171 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3172 %} 3173 3174 enc_class enc_membar_release %{ 3175 MacroAssembler _masm(&cbuf); 3176 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3177 %} 3178 3179 enc_class enc_membar_volatile %{ 3180 MacroAssembler _masm(&cbuf); 3181 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3182 %} 3183 3184 %} 3185 3186 //----------FRAME-------------------------------------------------------------- 3187 // Definition of frame structure and management information. 3188 // 3189 // S T A C K L A Y O U T Allocators stack-slot number 3190 // | (to get allocators register number 3191 // G Owned by | | v add VMRegImpl::stack0) 3192 // r CALLER | | 3193 // o | +--------+ pad to even-align allocators stack-slot 3194 // w V | pad0 | numbers; owned by CALLER 3195 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3196 // h ^ | in | 5 3197 // | | args | 4 Holes in incoming args owned by SELF 3198 // | | | | 3 3199 // | | +--------+ 3200 // V | | old out| Empty on Intel, window on Sparc 3201 // | old |preserve| Must be even aligned. 3202 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3203 // | | in | 3 area for Intel ret address 3204 // Owned by |preserve| Empty on Sparc. 3205 // SELF +--------+ 3206 // | | pad2 | 2 pad to align old SP 3207 // | +--------+ 1 3208 // | | locks | 0 3209 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3210 // | | pad1 | 11 pad to align new SP 3211 // | +--------+ 3212 // | | | 10 3213 // | | spills | 9 spills 3214 // V | | 8 (pad0 slot for callee) 3215 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3216 // ^ | out | 7 3217 // | | args | 6 Holes in outgoing args owned by CALLEE 3218 // Owned by +--------+ 3219 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3220 // | new |preserve| Must be even-aligned. 3221 // | SP-+--------+----> Matcher::_new_SP, even aligned 3222 // | | | 3223 // 3224 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3225 // known from SELF's arguments and the Java calling convention. 3226 // Region 6-7 is determined per call site. 3227 // Note 2: If the calling convention leaves holes in the incoming argument 3228 // area, those holes are owned by SELF. Holes in the outgoing area 3229 // are owned by the CALLEE. Holes should not be nessecary in the 3230 // incoming area, as the Java calling convention is completely under 3231 // the control of the AD file. Doubles can be sorted and packed to 3232 // avoid holes. Holes in the outgoing arguments may be necessary for 3233 // varargs C calling conventions. 3234 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3235 // even aligned with pad0 as needed. 3236 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3237 // region 6-11 is even aligned; it may be padded out more so that 3238 // the region from SP to FP meets the minimum stack alignment. 3239 3240 frame %{ 3241 // What direction does stack grow in (assumed to be same for native & Java) 3242 stack_direction(TOWARDS_LOW); 3243 3244 // These two registers define part of the calling convention 3245 // between compiled code and the interpreter. 3246 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 3247 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3248 3249 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3250 cisc_spilling_operand_name(indOffset); 3251 3252 // Number of stack slots consumed by a Monitor enter 3253 #ifdef _LP64 3254 sync_stack_slots(2); 3255 #else 3256 sync_stack_slots(1); 3257 #endif 3258 3259 // Compiled code's Frame Pointer 3260 frame_pointer(R_SP); 3261 3262 // Stack alignment requirement 3263 stack_alignment(StackAlignmentInBytes); 3264 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3265 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3266 3267 // Number of stack slots between incoming argument block and the start of 3268 // a new frame. The PROLOG must add this many slots to the stack. The 3269 // EPILOG must remove this many slots. 3270 in_preserve_stack_slots(0); 3271 3272 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3273 // for calls to C. Supports the var-args backing area for register parms. 3274 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3275 #ifdef _LP64 3276 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3277 varargs_C_out_slots_killed(12); 3278 #else 3279 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3280 varargs_C_out_slots_killed( 7); 3281 #endif 3282 3283 // The after-PROLOG location of the return address. Location of 3284 // return address specifies a type (REG or STACK) and a number 3285 // representing the register number (i.e. - use a register name) or 3286 // stack slot. 3287 return_addr(REG R_I7); // Ret Addr is in register I7 3288 3289 // Body of function which returns an OptoRegs array locating 3290 // arguments either in registers or in stack slots for calling 3291 // java 3292 calling_convention %{ 3293 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3294 3295 %} 3296 3297 // Body of function which returns an OptoRegs array locating 3298 // arguments either in registers or in stack slots for calling 3299 // C. 3300 c_calling_convention %{ 3301 // This is obviously always outgoing 3302 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3303 %} 3304 3305 // Location of native (C/C++) and interpreter return values. This is specified to 3306 // be the same as Java. In the 32-bit VM, long values are actually returned from 3307 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3308 // to and from the register pairs is done by the appropriate call and epilog 3309 // opcodes. This simplifies the register allocator. 3310 c_return_value %{ 3311 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3312 #ifdef _LP64 3313 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3314 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3315 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3316 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3317 #else // !_LP64 3318 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3319 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3320 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3321 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3322 #endif 3323 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3324 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3325 %} 3326 3327 // Location of compiled Java return values. Same as C 3328 return_value %{ 3329 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3330 #ifdef _LP64 3331 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3332 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3333 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3334 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3335 #else // !_LP64 3336 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3337 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3338 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3339 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3340 #endif 3341 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3342 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3343 %} 3344 3345 %} 3346 3347 3348 //----------ATTRIBUTES--------------------------------------------------------- 3349 //----------Operand Attributes------------------------------------------------- 3350 op_attrib op_cost(1); // Required cost attribute 3351 3352 //----------Instruction Attributes--------------------------------------------- 3353 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3354 ins_attrib ins_size(32); // Required size attribute (in bits) 3355 3356 // avoid_back_to_back attribute is an expression that must return 3357 // one of the following values defined in MachNode: 3358 // AVOID_NONE - instruction can be placed anywhere 3359 // AVOID_BEFORE - instruction cannot be placed after an 3360 // instruction with MachNode::AVOID_AFTER 3361 // AVOID_AFTER - the next instruction cannot be the one 3362 // with MachNode::AVOID_BEFORE 3363 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 3364 // the same time 3365 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 3366 3367 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3368 // non-matching short branch variant of some 3369 // long branch? 3370 3371 //----------OPERANDS----------------------------------------------------------- 3372 // Operand definitions must precede instruction definitions for correct parsing 3373 // in the ADLC because operands constitute user defined types which are used in 3374 // instruction definitions. 3375 3376 //----------Simple Operands---------------------------------------------------- 3377 // Immediate Operands 3378 // Integer Immediate: 32-bit 3379 operand immI() %{ 3380 match(ConI); 3381 3382 op_cost(0); 3383 // formats are generated automatically for constants and base registers 3384 format %{ %} 3385 interface(CONST_INTER); 3386 %} 3387 3388 // Integer Immediate: 0-bit 3389 operand immI0() %{ 3390 predicate(n->get_int() == 0); 3391 match(ConI); 3392 op_cost(0); 3393 3394 format %{ %} 3395 interface(CONST_INTER); 3396 %} 3397 3398 // Integer Immediate: 5-bit 3399 operand immI5() %{ 3400 predicate(Assembler::is_simm5(n->get_int())); 3401 match(ConI); 3402 op_cost(0); 3403 format %{ %} 3404 interface(CONST_INTER); 3405 %} 3406 3407 // Integer Immediate: 8-bit 3408 operand immI8() %{ 3409 predicate(Assembler::is_simm8(n->get_int())); 3410 match(ConI); 3411 op_cost(0); 3412 format %{ %} 3413 interface(CONST_INTER); 3414 %} 3415 3416 // Integer Immediate: the value 10 3417 operand immI10() %{ 3418 predicate(n->get_int() == 10); 3419 match(ConI); 3420 op_cost(0); 3421 3422 format %{ %} 3423 interface(CONST_INTER); 3424 %} 3425 3426 // Integer Immediate: 11-bit 3427 operand immI11() %{ 3428 predicate(Assembler::is_simm11(n->get_int())); 3429 match(ConI); 3430 op_cost(0); 3431 format %{ %} 3432 interface(CONST_INTER); 3433 %} 3434 3435 // Integer Immediate: 13-bit 3436 operand immI13() %{ 3437 predicate(Assembler::is_simm13(n->get_int())); 3438 match(ConI); 3439 op_cost(0); 3440 3441 format %{ %} 3442 interface(CONST_INTER); 3443 %} 3444 3445 // Integer Immediate: 13-bit minus 7 3446 operand immI13m7() %{ 3447 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3448 match(ConI); 3449 op_cost(0); 3450 3451 format %{ %} 3452 interface(CONST_INTER); 3453 %} 3454 3455 // Integer Immediate: 16-bit 3456 operand immI16() %{ 3457 predicate(Assembler::is_simm16(n->get_int())); 3458 match(ConI); 3459 op_cost(0); 3460 format %{ %} 3461 interface(CONST_INTER); 3462 %} 3463 3464 // Integer Immediate: the values 1-31 3465 operand immI_1_31() %{ 3466 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3467 match(ConI); 3468 op_cost(0); 3469 3470 format %{ %} 3471 interface(CONST_INTER); 3472 %} 3473 3474 // Integer Immediate: the values 32-63 3475 operand immI_32_63() %{ 3476 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3477 match(ConI); 3478 op_cost(0); 3479 3480 format %{ %} 3481 interface(CONST_INTER); 3482 %} 3483 3484 // Immediates for special shifts (sign extend) 3485 3486 // Integer Immediate: the value 16 3487 operand immI_16() %{ 3488 predicate(n->get_int() == 16); 3489 match(ConI); 3490 op_cost(0); 3491 3492 format %{ %} 3493 interface(CONST_INTER); 3494 %} 3495 3496 // Integer Immediate: the value 24 3497 operand immI_24() %{ 3498 predicate(n->get_int() == 24); 3499 match(ConI); 3500 op_cost(0); 3501 3502 format %{ %} 3503 interface(CONST_INTER); 3504 %} 3505 // Integer Immediate: the value 255 3506 operand immI_255() %{ 3507 predicate( n->get_int() == 255 ); 3508 match(ConI); 3509 op_cost(0); 3510 3511 format %{ %} 3512 interface(CONST_INTER); 3513 %} 3514 3515 // Integer Immediate: the value 65535 3516 operand immI_65535() %{ 3517 predicate(n->get_int() == 65535); 3518 match(ConI); 3519 op_cost(0); 3520 3521 format %{ %} 3522 interface(CONST_INTER); 3523 %} 3524 3525 // Integer Immediate: the values 0-31 3526 operand immU5() %{ 3527 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3528 match(ConI); 3529 op_cost(0); 3530 3531 format %{ %} 3532 interface(CONST_INTER); 3533 %} 3534 3535 // Integer Immediate: 6-bit 3536 operand immU6() %{ 3537 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3538 match(ConI); 3539 op_cost(0); 3540 format %{ %} 3541 interface(CONST_INTER); 3542 %} 3543 3544 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3545 operand immU12() %{ 3546 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3547 match(ConI); 3548 op_cost(0); 3549 3550 format %{ %} 3551 interface(CONST_INTER); 3552 %} 3553 3554 // Integer Immediate non-negative 3555 operand immU31() 3556 %{ 3557 predicate(n->get_int() >= 0); 3558 match(ConI); 3559 3560 op_cost(0); 3561 format %{ %} 3562 interface(CONST_INTER); 3563 %} 3564 3565 // Long Immediate: the value FF 3566 operand immL_FF() %{ 3567 predicate( n->get_long() == 0xFFL ); 3568 match(ConL); 3569 op_cost(0); 3570 3571 format %{ %} 3572 interface(CONST_INTER); 3573 %} 3574 3575 // Long Immediate: the value FFFF 3576 operand immL_FFFF() %{ 3577 predicate( n->get_long() == 0xFFFFL ); 3578 match(ConL); 3579 op_cost(0); 3580 3581 format %{ %} 3582 interface(CONST_INTER); 3583 %} 3584 3585 // Pointer Immediate: 32 or 64-bit 3586 operand immP() %{ 3587 match(ConP); 3588 3589 op_cost(5); 3590 // formats are generated automatically for constants and base registers 3591 format %{ %} 3592 interface(CONST_INTER); 3593 %} 3594 3595 #ifdef _LP64 3596 // Pointer Immediate: 64-bit 3597 operand immP_set() %{ 3598 predicate(!VM_Version::is_niagara_plus()); 3599 match(ConP); 3600 3601 op_cost(5); 3602 // formats are generated automatically for constants and base registers 3603 format %{ %} 3604 interface(CONST_INTER); 3605 %} 3606 3607 // Pointer Immediate: 64-bit 3608 // From Niagara2 processors on a load should be better than materializing. 3609 operand immP_load() %{ 3610 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3611 match(ConP); 3612 3613 op_cost(5); 3614 // formats are generated automatically for constants and base registers 3615 format %{ %} 3616 interface(CONST_INTER); 3617 %} 3618 3619 // Pointer Immediate: 64-bit 3620 operand immP_no_oop_cheap() %{ 3621 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3622 match(ConP); 3623 3624 op_cost(5); 3625 // formats are generated automatically for constants and base registers 3626 format %{ %} 3627 interface(CONST_INTER); 3628 %} 3629 #endif 3630 3631 operand immP13() %{ 3632 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3633 match(ConP); 3634 op_cost(0); 3635 3636 format %{ %} 3637 interface(CONST_INTER); 3638 %} 3639 3640 operand immP0() %{ 3641 predicate(n->get_ptr() == 0); 3642 match(ConP); 3643 op_cost(0); 3644 3645 format %{ %} 3646 interface(CONST_INTER); 3647 %} 3648 3649 operand immP_poll() %{ 3650 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3651 match(ConP); 3652 3653 // formats are generated automatically for constants and base registers 3654 format %{ %} 3655 interface(CONST_INTER); 3656 %} 3657 3658 // Pointer Immediate 3659 operand immN() 3660 %{ 3661 match(ConN); 3662 3663 op_cost(10); 3664 format %{ %} 3665 interface(CONST_INTER); 3666 %} 3667 3668 operand immNKlass() 3669 %{ 3670 match(ConNKlass); 3671 3672 op_cost(10); 3673 format %{ %} 3674 interface(CONST_INTER); 3675 %} 3676 3677 // NULL Pointer Immediate 3678 operand immN0() 3679 %{ 3680 predicate(n->get_narrowcon() == 0); 3681 match(ConN); 3682 3683 op_cost(0); 3684 format %{ %} 3685 interface(CONST_INTER); 3686 %} 3687 3688 operand immL() %{ 3689 match(ConL); 3690 op_cost(40); 3691 // formats are generated automatically for constants and base registers 3692 format %{ %} 3693 interface(CONST_INTER); 3694 %} 3695 3696 operand immL0() %{ 3697 predicate(n->get_long() == 0L); 3698 match(ConL); 3699 op_cost(0); 3700 // formats are generated automatically for constants and base registers 3701 format %{ %} 3702 interface(CONST_INTER); 3703 %} 3704 3705 // Integer Immediate: 5-bit 3706 operand immL5() %{ 3707 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3708 match(ConL); 3709 op_cost(0); 3710 format %{ %} 3711 interface(CONST_INTER); 3712 %} 3713 3714 // Long Immediate: 13-bit 3715 operand immL13() %{ 3716 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3717 match(ConL); 3718 op_cost(0); 3719 3720 format %{ %} 3721 interface(CONST_INTER); 3722 %} 3723 3724 // Long Immediate: 13-bit minus 7 3725 operand immL13m7() %{ 3726 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3727 match(ConL); 3728 op_cost(0); 3729 3730 format %{ %} 3731 interface(CONST_INTER); 3732 %} 3733 3734 // Long Immediate: low 32-bit mask 3735 operand immL_32bits() %{ 3736 predicate(n->get_long() == 0xFFFFFFFFL); 3737 match(ConL); 3738 op_cost(0); 3739 3740 format %{ %} 3741 interface(CONST_INTER); 3742 %} 3743 3744 // Long Immediate: cheap (materialize in <= 3 instructions) 3745 operand immL_cheap() %{ 3746 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3747 match(ConL); 3748 op_cost(0); 3749 3750 format %{ %} 3751 interface(CONST_INTER); 3752 %} 3753 3754 // Long Immediate: expensive (materialize in > 3 instructions) 3755 operand immL_expensive() %{ 3756 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3757 match(ConL); 3758 op_cost(0); 3759 3760 format %{ %} 3761 interface(CONST_INTER); 3762 %} 3763 3764 // Double Immediate 3765 operand immD() %{ 3766 match(ConD); 3767 3768 op_cost(40); 3769 format %{ %} 3770 interface(CONST_INTER); 3771 %} 3772 3773 // Double Immediate: +0.0d 3774 operand immD0() %{ 3775 predicate(jlong_cast(n->getd()) == 0); 3776 match(ConD); 3777 3778 op_cost(0); 3779 format %{ %} 3780 interface(CONST_INTER); 3781 %} 3782 3783 // Float Immediate 3784 operand immF() %{ 3785 match(ConF); 3786 3787 op_cost(20); 3788 format %{ %} 3789 interface(CONST_INTER); 3790 %} 3791 3792 // Float Immediate: +0.0f 3793 operand immF0() %{ 3794 predicate(jint_cast(n->getf()) == 0); 3795 match(ConF); 3796 3797 op_cost(0); 3798 format %{ %} 3799 interface(CONST_INTER); 3800 %} 3801 3802 // Integer Register Operands 3803 // Integer Register 3804 operand iRegI() %{ 3805 constraint(ALLOC_IN_RC(int_reg)); 3806 match(RegI); 3807 3808 match(notemp_iRegI); 3809 match(g1RegI); 3810 match(o0RegI); 3811 match(iRegIsafe); 3812 3813 format %{ %} 3814 interface(REG_INTER); 3815 %} 3816 3817 operand notemp_iRegI() %{ 3818 constraint(ALLOC_IN_RC(notemp_int_reg)); 3819 match(RegI); 3820 3821 match(o0RegI); 3822 3823 format %{ %} 3824 interface(REG_INTER); 3825 %} 3826 3827 operand o0RegI() %{ 3828 constraint(ALLOC_IN_RC(o0_regI)); 3829 match(iRegI); 3830 3831 format %{ %} 3832 interface(REG_INTER); 3833 %} 3834 3835 // Pointer Register 3836 operand iRegP() %{ 3837 constraint(ALLOC_IN_RC(ptr_reg)); 3838 match(RegP); 3839 3840 match(lock_ptr_RegP); 3841 match(g1RegP); 3842 match(g2RegP); 3843 match(g3RegP); 3844 match(g4RegP); 3845 match(i0RegP); 3846 match(o0RegP); 3847 match(o1RegP); 3848 match(l7RegP); 3849 3850 format %{ %} 3851 interface(REG_INTER); 3852 %} 3853 3854 operand sp_ptr_RegP() %{ 3855 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3856 match(RegP); 3857 match(iRegP); 3858 3859 format %{ %} 3860 interface(REG_INTER); 3861 %} 3862 3863 operand lock_ptr_RegP() %{ 3864 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3865 match(RegP); 3866 match(i0RegP); 3867 match(o0RegP); 3868 match(o1RegP); 3869 match(l7RegP); 3870 3871 format %{ %} 3872 interface(REG_INTER); 3873 %} 3874 3875 operand g1RegP() %{ 3876 constraint(ALLOC_IN_RC(g1_regP)); 3877 match(iRegP); 3878 3879 format %{ %} 3880 interface(REG_INTER); 3881 %} 3882 3883 operand g2RegP() %{ 3884 constraint(ALLOC_IN_RC(g2_regP)); 3885 match(iRegP); 3886 3887 format %{ %} 3888 interface(REG_INTER); 3889 %} 3890 3891 operand g3RegP() %{ 3892 constraint(ALLOC_IN_RC(g3_regP)); 3893 match(iRegP); 3894 3895 format %{ %} 3896 interface(REG_INTER); 3897 %} 3898 3899 operand g1RegI() %{ 3900 constraint(ALLOC_IN_RC(g1_regI)); 3901 match(iRegI); 3902 3903 format %{ %} 3904 interface(REG_INTER); 3905 %} 3906 3907 operand g3RegI() %{ 3908 constraint(ALLOC_IN_RC(g3_regI)); 3909 match(iRegI); 3910 3911 format %{ %} 3912 interface(REG_INTER); 3913 %} 3914 3915 operand g4RegI() %{ 3916 constraint(ALLOC_IN_RC(g4_regI)); 3917 match(iRegI); 3918 3919 format %{ %} 3920 interface(REG_INTER); 3921 %} 3922 3923 operand g4RegP() %{ 3924 constraint(ALLOC_IN_RC(g4_regP)); 3925 match(iRegP); 3926 3927 format %{ %} 3928 interface(REG_INTER); 3929 %} 3930 3931 operand i0RegP() %{ 3932 constraint(ALLOC_IN_RC(i0_regP)); 3933 match(iRegP); 3934 3935 format %{ %} 3936 interface(REG_INTER); 3937 %} 3938 3939 operand o0RegP() %{ 3940 constraint(ALLOC_IN_RC(o0_regP)); 3941 match(iRegP); 3942 3943 format %{ %} 3944 interface(REG_INTER); 3945 %} 3946 3947 operand o1RegP() %{ 3948 constraint(ALLOC_IN_RC(o1_regP)); 3949 match(iRegP); 3950 3951 format %{ %} 3952 interface(REG_INTER); 3953 %} 3954 3955 operand o2RegP() %{ 3956 constraint(ALLOC_IN_RC(o2_regP)); 3957 match(iRegP); 3958 3959 format %{ %} 3960 interface(REG_INTER); 3961 %} 3962 3963 operand o7RegP() %{ 3964 constraint(ALLOC_IN_RC(o7_regP)); 3965 match(iRegP); 3966 3967 format %{ %} 3968 interface(REG_INTER); 3969 %} 3970 3971 operand l7RegP() %{ 3972 constraint(ALLOC_IN_RC(l7_regP)); 3973 match(iRegP); 3974 3975 format %{ %} 3976 interface(REG_INTER); 3977 %} 3978 3979 operand o7RegI() %{ 3980 constraint(ALLOC_IN_RC(o7_regI)); 3981 match(iRegI); 3982 3983 format %{ %} 3984 interface(REG_INTER); 3985 %} 3986 3987 operand iRegN() %{ 3988 constraint(ALLOC_IN_RC(int_reg)); 3989 match(RegN); 3990 3991 format %{ %} 3992 interface(REG_INTER); 3993 %} 3994 3995 // Long Register 3996 operand iRegL() %{ 3997 constraint(ALLOC_IN_RC(long_reg)); 3998 match(RegL); 3999 4000 format %{ %} 4001 interface(REG_INTER); 4002 %} 4003 4004 operand o2RegL() %{ 4005 constraint(ALLOC_IN_RC(o2_regL)); 4006 match(iRegL); 4007 4008 format %{ %} 4009 interface(REG_INTER); 4010 %} 4011 4012 operand o7RegL() %{ 4013 constraint(ALLOC_IN_RC(o7_regL)); 4014 match(iRegL); 4015 4016 format %{ %} 4017 interface(REG_INTER); 4018 %} 4019 4020 operand g1RegL() %{ 4021 constraint(ALLOC_IN_RC(g1_regL)); 4022 match(iRegL); 4023 4024 format %{ %} 4025 interface(REG_INTER); 4026 %} 4027 4028 operand g3RegL() %{ 4029 constraint(ALLOC_IN_RC(g3_regL)); 4030 match(iRegL); 4031 4032 format %{ %} 4033 interface(REG_INTER); 4034 %} 4035 4036 // Int Register safe 4037 // This is 64bit safe 4038 operand iRegIsafe() %{ 4039 constraint(ALLOC_IN_RC(long_reg)); 4040 4041 match(iRegI); 4042 4043 format %{ %} 4044 interface(REG_INTER); 4045 %} 4046 4047 // Condition Code Flag Register 4048 operand flagsReg() %{ 4049 constraint(ALLOC_IN_RC(int_flags)); 4050 match(RegFlags); 4051 4052 format %{ "ccr" %} // both ICC and XCC 4053 interface(REG_INTER); 4054 %} 4055 4056 // Condition Code Register, unsigned comparisons. 4057 operand flagsRegU() %{ 4058 constraint(ALLOC_IN_RC(int_flags)); 4059 match(RegFlags); 4060 4061 format %{ "icc_U" %} 4062 interface(REG_INTER); 4063 %} 4064 4065 // Condition Code Register, pointer comparisons. 4066 operand flagsRegP() %{ 4067 constraint(ALLOC_IN_RC(int_flags)); 4068 match(RegFlags); 4069 4070 #ifdef _LP64 4071 format %{ "xcc_P" %} 4072 #else 4073 format %{ "icc_P" %} 4074 #endif 4075 interface(REG_INTER); 4076 %} 4077 4078 // Condition Code Register, long comparisons. 4079 operand flagsRegL() %{ 4080 constraint(ALLOC_IN_RC(int_flags)); 4081 match(RegFlags); 4082 4083 format %{ "xcc_L" %} 4084 interface(REG_INTER); 4085 %} 4086 4087 // Condition Code Register, floating comparisons, unordered same as "less". 4088 operand flagsRegF() %{ 4089 constraint(ALLOC_IN_RC(float_flags)); 4090 match(RegFlags); 4091 match(flagsRegF0); 4092 4093 format %{ %} 4094 interface(REG_INTER); 4095 %} 4096 4097 operand flagsRegF0() %{ 4098 constraint(ALLOC_IN_RC(float_flag0)); 4099 match(RegFlags); 4100 4101 format %{ %} 4102 interface(REG_INTER); 4103 %} 4104 4105 4106 // Condition Code Flag Register used by long compare 4107 operand flagsReg_long_LTGE() %{ 4108 constraint(ALLOC_IN_RC(int_flags)); 4109 match(RegFlags); 4110 format %{ "icc_LTGE" %} 4111 interface(REG_INTER); 4112 %} 4113 operand flagsReg_long_EQNE() %{ 4114 constraint(ALLOC_IN_RC(int_flags)); 4115 match(RegFlags); 4116 format %{ "icc_EQNE" %} 4117 interface(REG_INTER); 4118 %} 4119 operand flagsReg_long_LEGT() %{ 4120 constraint(ALLOC_IN_RC(int_flags)); 4121 match(RegFlags); 4122 format %{ "icc_LEGT" %} 4123 interface(REG_INTER); 4124 %} 4125 4126 4127 operand regD() %{ 4128 constraint(ALLOC_IN_RC(dflt_reg)); 4129 match(RegD); 4130 4131 match(regD_low); 4132 4133 format %{ %} 4134 interface(REG_INTER); 4135 %} 4136 4137 operand regF() %{ 4138 constraint(ALLOC_IN_RC(sflt_reg)); 4139 match(RegF); 4140 4141 format %{ %} 4142 interface(REG_INTER); 4143 %} 4144 4145 operand regD_low() %{ 4146 constraint(ALLOC_IN_RC(dflt_low_reg)); 4147 match(regD); 4148 4149 format %{ %} 4150 interface(REG_INTER); 4151 %} 4152 4153 // Special Registers 4154 4155 // Method Register 4156 operand inline_cache_regP(iRegP reg) %{ 4157 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4158 match(reg); 4159 format %{ %} 4160 interface(REG_INTER); 4161 %} 4162 4163 operand interpreter_method_oop_regP(iRegP reg) %{ 4164 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4165 match(reg); 4166 format %{ %} 4167 interface(REG_INTER); 4168 %} 4169 4170 4171 //----------Complex Operands--------------------------------------------------- 4172 // Indirect Memory Reference 4173 operand indirect(sp_ptr_RegP reg) %{ 4174 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4175 match(reg); 4176 4177 op_cost(100); 4178 format %{ "[$reg]" %} 4179 interface(MEMORY_INTER) %{ 4180 base($reg); 4181 index(0x0); 4182 scale(0x0); 4183 disp(0x0); 4184 %} 4185 %} 4186 4187 // Indirect with simm13 Offset 4188 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4189 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4190 match(AddP reg offset); 4191 4192 op_cost(100); 4193 format %{ "[$reg + $offset]" %} 4194 interface(MEMORY_INTER) %{ 4195 base($reg); 4196 index(0x0); 4197 scale(0x0); 4198 disp($offset); 4199 %} 4200 %} 4201 4202 // Indirect with simm13 Offset minus 7 4203 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4204 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4205 match(AddP reg offset); 4206 4207 op_cost(100); 4208 format %{ "[$reg + $offset]" %} 4209 interface(MEMORY_INTER) %{ 4210 base($reg); 4211 index(0x0); 4212 scale(0x0); 4213 disp($offset); 4214 %} 4215 %} 4216 4217 // Note: Intel has a swapped version also, like this: 4218 //operand indOffsetX(iRegI reg, immP offset) %{ 4219 // constraint(ALLOC_IN_RC(int_reg)); 4220 // match(AddP offset reg); 4221 // 4222 // op_cost(100); 4223 // format %{ "[$reg + $offset]" %} 4224 // interface(MEMORY_INTER) %{ 4225 // base($reg); 4226 // index(0x0); 4227 // scale(0x0); 4228 // disp($offset); 4229 // %} 4230 //%} 4231 //// However, it doesn't make sense for SPARC, since 4232 // we have no particularly good way to embed oops in 4233 // single instructions. 4234 4235 // Indirect with Register Index 4236 operand indIndex(iRegP addr, iRegX index) %{ 4237 constraint(ALLOC_IN_RC(ptr_reg)); 4238 match(AddP addr index); 4239 4240 op_cost(100); 4241 format %{ "[$addr + $index]" %} 4242 interface(MEMORY_INTER) %{ 4243 base($addr); 4244 index($index); 4245 scale(0x0); 4246 disp(0x0); 4247 %} 4248 %} 4249 4250 //----------Special Memory Operands-------------------------------------------- 4251 // Stack Slot Operand - This operand is used for loading and storing temporary 4252 // values on the stack where a match requires a value to 4253 // flow through memory. 4254 operand stackSlotI(sRegI reg) %{ 4255 constraint(ALLOC_IN_RC(stack_slots)); 4256 op_cost(100); 4257 //match(RegI); 4258 format %{ "[$reg]" %} 4259 interface(MEMORY_INTER) %{ 4260 base(0xE); // R_SP 4261 index(0x0); 4262 scale(0x0); 4263 disp($reg); // Stack Offset 4264 %} 4265 %} 4266 4267 operand stackSlotP(sRegP reg) %{ 4268 constraint(ALLOC_IN_RC(stack_slots)); 4269 op_cost(100); 4270 //match(RegP); 4271 format %{ "[$reg]" %} 4272 interface(MEMORY_INTER) %{ 4273 base(0xE); // R_SP 4274 index(0x0); 4275 scale(0x0); 4276 disp($reg); // Stack Offset 4277 %} 4278 %} 4279 4280 operand stackSlotF(sRegF reg) %{ 4281 constraint(ALLOC_IN_RC(stack_slots)); 4282 op_cost(100); 4283 //match(RegF); 4284 format %{ "[$reg]" %} 4285 interface(MEMORY_INTER) %{ 4286 base(0xE); // R_SP 4287 index(0x0); 4288 scale(0x0); 4289 disp($reg); // Stack Offset 4290 %} 4291 %} 4292 operand stackSlotD(sRegD reg) %{ 4293 constraint(ALLOC_IN_RC(stack_slots)); 4294 op_cost(100); 4295 //match(RegD); 4296 format %{ "[$reg]" %} 4297 interface(MEMORY_INTER) %{ 4298 base(0xE); // R_SP 4299 index(0x0); 4300 scale(0x0); 4301 disp($reg); // Stack Offset 4302 %} 4303 %} 4304 operand stackSlotL(sRegL reg) %{ 4305 constraint(ALLOC_IN_RC(stack_slots)); 4306 op_cost(100); 4307 //match(RegL); 4308 format %{ "[$reg]" %} 4309 interface(MEMORY_INTER) %{ 4310 base(0xE); // R_SP 4311 index(0x0); 4312 scale(0x0); 4313 disp($reg); // Stack Offset 4314 %} 4315 %} 4316 4317 // Operands for expressing Control Flow 4318 // NOTE: Label is a predefined operand which should not be redefined in 4319 // the AD file. It is generically handled within the ADLC. 4320 4321 //----------Conditional Branch Operands---------------------------------------- 4322 // Comparison Op - This is the operation of the comparison, and is limited to 4323 // the following set of codes: 4324 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4325 // 4326 // Other attributes of the comparison, such as unsignedness, are specified 4327 // by the comparison instruction that sets a condition code flags register. 4328 // That result is represented by a flags operand whose subtype is appropriate 4329 // to the unsignedness (etc.) of the comparison. 4330 // 4331 // Later, the instruction which matches both the Comparison Op (a Bool) and 4332 // the flags (produced by the Cmp) specifies the coding of the comparison op 4333 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4334 4335 operand cmpOp() %{ 4336 match(Bool); 4337 4338 format %{ "" %} 4339 interface(COND_INTER) %{ 4340 equal(0x1); 4341 not_equal(0x9); 4342 less(0x3); 4343 greater_equal(0xB); 4344 less_equal(0x2); 4345 greater(0xA); 4346 overflow(0x7); 4347 no_overflow(0xF); 4348 %} 4349 %} 4350 4351 // Comparison Op, unsigned 4352 operand cmpOpU() %{ 4353 match(Bool); 4354 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4355 n->as_Bool()->_test._test != BoolTest::no_overflow); 4356 4357 format %{ "u" %} 4358 interface(COND_INTER) %{ 4359 equal(0x1); 4360 not_equal(0x9); 4361 less(0x5); 4362 greater_equal(0xD); 4363 less_equal(0x4); 4364 greater(0xC); 4365 overflow(0x7); 4366 no_overflow(0xF); 4367 %} 4368 %} 4369 4370 // Comparison Op, pointer (same as unsigned) 4371 operand cmpOpP() %{ 4372 match(Bool); 4373 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4374 n->as_Bool()->_test._test != BoolTest::no_overflow); 4375 4376 format %{ "p" %} 4377 interface(COND_INTER) %{ 4378 equal(0x1); 4379 not_equal(0x9); 4380 less(0x5); 4381 greater_equal(0xD); 4382 less_equal(0x4); 4383 greater(0xC); 4384 overflow(0x7); 4385 no_overflow(0xF); 4386 %} 4387 %} 4388 4389 // Comparison Op, branch-register encoding 4390 operand cmpOp_reg() %{ 4391 match(Bool); 4392 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4393 n->as_Bool()->_test._test != BoolTest::no_overflow); 4394 4395 format %{ "" %} 4396 interface(COND_INTER) %{ 4397 equal (0x1); 4398 not_equal (0x5); 4399 less (0x3); 4400 greater_equal(0x7); 4401 less_equal (0x2); 4402 greater (0x6); 4403 overflow(0x7); // not supported 4404 no_overflow(0xF); // not supported 4405 %} 4406 %} 4407 4408 // Comparison Code, floating, unordered same as less 4409 operand cmpOpF() %{ 4410 match(Bool); 4411 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4412 n->as_Bool()->_test._test != BoolTest::no_overflow); 4413 4414 format %{ "fl" %} 4415 interface(COND_INTER) %{ 4416 equal(0x9); 4417 not_equal(0x1); 4418 less(0x3); 4419 greater_equal(0xB); 4420 less_equal(0xE); 4421 greater(0x6); 4422 4423 overflow(0x7); // not supported 4424 no_overflow(0xF); // not supported 4425 %} 4426 %} 4427 4428 // Used by long compare 4429 operand cmpOp_commute() %{ 4430 match(Bool); 4431 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4432 n->as_Bool()->_test._test != BoolTest::no_overflow); 4433 4434 format %{ "" %} 4435 interface(COND_INTER) %{ 4436 equal(0x1); 4437 not_equal(0x9); 4438 less(0xA); 4439 greater_equal(0x2); 4440 less_equal(0xB); 4441 greater(0x3); 4442 overflow(0x7); 4443 no_overflow(0xF); 4444 %} 4445 %} 4446 4447 //----------OPERAND CLASSES---------------------------------------------------- 4448 // Operand Classes are groups of operands that are used to simplify 4449 // instruction definitions by not requiring the AD writer to specify separate 4450 // instructions for every form of operand when the instruction accepts 4451 // multiple operand types with the same basic encoding and format. The classic 4452 // case of this is memory operands. 4453 opclass memory( indirect, indOffset13, indIndex ); 4454 opclass indIndexMemory( indIndex ); 4455 4456 //----------PIPELINE----------------------------------------------------------- 4457 pipeline %{ 4458 4459 //----------ATTRIBUTES--------------------------------------------------------- 4460 attributes %{ 4461 fixed_size_instructions; // Fixed size instructions 4462 branch_has_delay_slot; // Branch has delay slot following 4463 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4464 instruction_unit_size = 4; // An instruction is 4 bytes long 4465 instruction_fetch_unit_size = 16; // The processor fetches one line 4466 instruction_fetch_units = 1; // of 16 bytes 4467 4468 // List of nop instructions 4469 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4470 %} 4471 4472 //----------RESOURCES---------------------------------------------------------- 4473 // Resources are the functional units available to the machine 4474 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4475 4476 //----------PIPELINE DESCRIPTION----------------------------------------------- 4477 // Pipeline Description specifies the stages in the machine's pipeline 4478 4479 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4480 4481 //----------PIPELINE CLASSES--------------------------------------------------- 4482 // Pipeline Classes describe the stages in which input and output are 4483 // referenced by the hardware pipeline. 4484 4485 // Integer ALU reg-reg operation 4486 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4487 single_instruction; 4488 dst : E(write); 4489 src1 : R(read); 4490 src2 : R(read); 4491 IALU : R; 4492 %} 4493 4494 // Integer ALU reg-reg long operation 4495 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4496 instruction_count(2); 4497 dst : E(write); 4498 src1 : R(read); 4499 src2 : R(read); 4500 IALU : R; 4501 IALU : R; 4502 %} 4503 4504 // Integer ALU reg-reg long dependent operation 4505 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4506 instruction_count(1); multiple_bundles; 4507 dst : E(write); 4508 src1 : R(read); 4509 src2 : R(read); 4510 cr : E(write); 4511 IALU : R(2); 4512 %} 4513 4514 // Integer ALU reg-imm operaion 4515 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4516 single_instruction; 4517 dst : E(write); 4518 src1 : R(read); 4519 IALU : R; 4520 %} 4521 4522 // Integer ALU reg-reg operation with condition code 4523 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4524 single_instruction; 4525 dst : E(write); 4526 cr : E(write); 4527 src1 : R(read); 4528 src2 : R(read); 4529 IALU : R; 4530 %} 4531 4532 // Integer ALU reg-imm operation with condition code 4533 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4534 single_instruction; 4535 dst : E(write); 4536 cr : E(write); 4537 src1 : R(read); 4538 IALU : R; 4539 %} 4540 4541 // Integer ALU zero-reg operation 4542 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4543 single_instruction; 4544 dst : E(write); 4545 src2 : R(read); 4546 IALU : R; 4547 %} 4548 4549 // Integer ALU zero-reg operation with condition code only 4550 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4551 single_instruction; 4552 cr : E(write); 4553 src : R(read); 4554 IALU : R; 4555 %} 4556 4557 // Integer ALU reg-reg operation with condition code only 4558 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4559 single_instruction; 4560 cr : E(write); 4561 src1 : R(read); 4562 src2 : R(read); 4563 IALU : R; 4564 %} 4565 4566 // Integer ALU reg-imm operation with condition code only 4567 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4568 single_instruction; 4569 cr : E(write); 4570 src1 : R(read); 4571 IALU : R; 4572 %} 4573 4574 // Integer ALU reg-reg-zero operation with condition code only 4575 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4576 single_instruction; 4577 cr : E(write); 4578 src1 : R(read); 4579 src2 : R(read); 4580 IALU : R; 4581 %} 4582 4583 // Integer ALU reg-imm-zero operation with condition code only 4584 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4585 single_instruction; 4586 cr : E(write); 4587 src1 : R(read); 4588 IALU : R; 4589 %} 4590 4591 // Integer ALU reg-reg operation with condition code, src1 modified 4592 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4593 single_instruction; 4594 cr : E(write); 4595 src1 : E(write); 4596 src1 : R(read); 4597 src2 : R(read); 4598 IALU : R; 4599 %} 4600 4601 // Integer ALU reg-imm operation with condition code, src1 modified 4602 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4603 single_instruction; 4604 cr : E(write); 4605 src1 : E(write); 4606 src1 : R(read); 4607 IALU : R; 4608 %} 4609 4610 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4611 multiple_bundles; 4612 dst : E(write)+4; 4613 cr : E(write); 4614 src1 : R(read); 4615 src2 : R(read); 4616 IALU : R(3); 4617 BR : R(2); 4618 %} 4619 4620 // Integer ALU operation 4621 pipe_class ialu_none(iRegI dst) %{ 4622 single_instruction; 4623 dst : E(write); 4624 IALU : R; 4625 %} 4626 4627 // Integer ALU reg operation 4628 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4629 single_instruction; may_have_no_code; 4630 dst : E(write); 4631 src : R(read); 4632 IALU : R; 4633 %} 4634 4635 // Integer ALU reg conditional operation 4636 // This instruction has a 1 cycle stall, and cannot execute 4637 // in the same cycle as the instruction setting the condition 4638 // code. We kludge this by pretending to read the condition code 4639 // 1 cycle earlier, and by marking the functional units as busy 4640 // for 2 cycles with the result available 1 cycle later than 4641 // is really the case. 4642 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4643 single_instruction; 4644 op2_out : C(write); 4645 op1 : R(read); 4646 cr : R(read); // This is really E, with a 1 cycle stall 4647 BR : R(2); 4648 MS : R(2); 4649 %} 4650 4651 #ifdef _LP64 4652 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4653 instruction_count(1); multiple_bundles; 4654 dst : C(write)+1; 4655 src : R(read)+1; 4656 IALU : R(1); 4657 BR : E(2); 4658 MS : E(2); 4659 %} 4660 #endif 4661 4662 // Integer ALU reg operation 4663 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4664 single_instruction; may_have_no_code; 4665 dst : E(write); 4666 src : R(read); 4667 IALU : R; 4668 %} 4669 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4670 single_instruction; may_have_no_code; 4671 dst : E(write); 4672 src : R(read); 4673 IALU : R; 4674 %} 4675 4676 // Two integer ALU reg operations 4677 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4678 instruction_count(2); 4679 dst : E(write); 4680 src : R(read); 4681 A0 : R; 4682 A1 : R; 4683 %} 4684 4685 // Two integer ALU reg operations 4686 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4687 instruction_count(2); may_have_no_code; 4688 dst : E(write); 4689 src : R(read); 4690 A0 : R; 4691 A1 : R; 4692 %} 4693 4694 // Integer ALU imm operation 4695 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4696 single_instruction; 4697 dst : E(write); 4698 IALU : R; 4699 %} 4700 4701 // Integer ALU reg-reg with carry operation 4702 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4703 single_instruction; 4704 dst : E(write); 4705 src1 : R(read); 4706 src2 : R(read); 4707 IALU : R; 4708 %} 4709 4710 // Integer ALU cc operation 4711 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4712 single_instruction; 4713 dst : E(write); 4714 cc : R(read); 4715 IALU : R; 4716 %} 4717 4718 // Integer ALU cc / second IALU operation 4719 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4720 instruction_count(1); multiple_bundles; 4721 dst : E(write)+1; 4722 src : R(read); 4723 IALU : R; 4724 %} 4725 4726 // Integer ALU cc / second IALU operation 4727 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4728 instruction_count(1); multiple_bundles; 4729 dst : E(write)+1; 4730 p : R(read); 4731 q : R(read); 4732 IALU : R; 4733 %} 4734 4735 // Integer ALU hi-lo-reg operation 4736 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4737 instruction_count(1); multiple_bundles; 4738 dst : E(write)+1; 4739 IALU : R(2); 4740 %} 4741 4742 // Float ALU hi-lo-reg operation (with temp) 4743 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4744 instruction_count(1); multiple_bundles; 4745 dst : E(write)+1; 4746 IALU : R(2); 4747 %} 4748 4749 // Long Constant 4750 pipe_class loadConL( iRegL dst, immL src ) %{ 4751 instruction_count(2); multiple_bundles; 4752 dst : E(write)+1; 4753 IALU : R(2); 4754 IALU : R(2); 4755 %} 4756 4757 // Pointer Constant 4758 pipe_class loadConP( iRegP dst, immP src ) %{ 4759 instruction_count(0); multiple_bundles; 4760 fixed_latency(6); 4761 %} 4762 4763 // Polling Address 4764 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4765 #ifdef _LP64 4766 instruction_count(0); multiple_bundles; 4767 fixed_latency(6); 4768 #else 4769 dst : E(write); 4770 IALU : R; 4771 #endif 4772 %} 4773 4774 // Long Constant small 4775 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4776 instruction_count(2); 4777 dst : E(write); 4778 IALU : R; 4779 IALU : R; 4780 %} 4781 4782 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4783 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4784 instruction_count(1); multiple_bundles; 4785 src : R(read); 4786 dst : M(write)+1; 4787 IALU : R; 4788 MS : E; 4789 %} 4790 4791 // Integer ALU nop operation 4792 pipe_class ialu_nop() %{ 4793 single_instruction; 4794 IALU : R; 4795 %} 4796 4797 // Integer ALU nop operation 4798 pipe_class ialu_nop_A0() %{ 4799 single_instruction; 4800 A0 : R; 4801 %} 4802 4803 // Integer ALU nop operation 4804 pipe_class ialu_nop_A1() %{ 4805 single_instruction; 4806 A1 : R; 4807 %} 4808 4809 // Integer Multiply reg-reg operation 4810 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4811 single_instruction; 4812 dst : E(write); 4813 src1 : R(read); 4814 src2 : R(read); 4815 MS : R(5); 4816 %} 4817 4818 // Integer Multiply reg-imm operation 4819 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4820 single_instruction; 4821 dst : E(write); 4822 src1 : R(read); 4823 MS : R(5); 4824 %} 4825 4826 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4827 single_instruction; 4828 dst : E(write)+4; 4829 src1 : R(read); 4830 src2 : R(read); 4831 MS : R(6); 4832 %} 4833 4834 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4835 single_instruction; 4836 dst : E(write)+4; 4837 src1 : R(read); 4838 MS : R(6); 4839 %} 4840 4841 // Integer Divide reg-reg 4842 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4843 instruction_count(1); multiple_bundles; 4844 dst : E(write); 4845 temp : E(write); 4846 src1 : R(read); 4847 src2 : R(read); 4848 temp : R(read); 4849 MS : R(38); 4850 %} 4851 4852 // Integer Divide reg-imm 4853 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4854 instruction_count(1); multiple_bundles; 4855 dst : E(write); 4856 temp : E(write); 4857 src1 : R(read); 4858 temp : R(read); 4859 MS : R(38); 4860 %} 4861 4862 // Long Divide 4863 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4864 dst : E(write)+71; 4865 src1 : R(read); 4866 src2 : R(read)+1; 4867 MS : R(70); 4868 %} 4869 4870 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4871 dst : E(write)+71; 4872 src1 : R(read); 4873 MS : R(70); 4874 %} 4875 4876 // Floating Point Add Float 4877 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4878 single_instruction; 4879 dst : X(write); 4880 src1 : E(read); 4881 src2 : E(read); 4882 FA : R; 4883 %} 4884 4885 // Floating Point Add Double 4886 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4887 single_instruction; 4888 dst : X(write); 4889 src1 : E(read); 4890 src2 : E(read); 4891 FA : R; 4892 %} 4893 4894 // Floating Point Conditional Move based on integer flags 4895 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4896 single_instruction; 4897 dst : X(write); 4898 src : E(read); 4899 cr : R(read); 4900 FA : R(2); 4901 BR : R(2); 4902 %} 4903 4904 // Floating Point Conditional Move based on integer flags 4905 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4906 single_instruction; 4907 dst : X(write); 4908 src : E(read); 4909 cr : R(read); 4910 FA : R(2); 4911 BR : R(2); 4912 %} 4913 4914 // Floating Point Multiply Float 4915 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4916 single_instruction; 4917 dst : X(write); 4918 src1 : E(read); 4919 src2 : E(read); 4920 FM : R; 4921 %} 4922 4923 // Floating Point Multiply Double 4924 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4925 single_instruction; 4926 dst : X(write); 4927 src1 : E(read); 4928 src2 : E(read); 4929 FM : R; 4930 %} 4931 4932 // Floating Point Divide Float 4933 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4934 single_instruction; 4935 dst : X(write); 4936 src1 : E(read); 4937 src2 : E(read); 4938 FM : R; 4939 FDIV : C(14); 4940 %} 4941 4942 // Floating Point Divide Double 4943 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4944 single_instruction; 4945 dst : X(write); 4946 src1 : E(read); 4947 src2 : E(read); 4948 FM : R; 4949 FDIV : C(17); 4950 %} 4951 4952 // Floating Point Move/Negate/Abs Float 4953 pipe_class faddF_reg(regF dst, regF src) %{ 4954 single_instruction; 4955 dst : W(write); 4956 src : E(read); 4957 FA : R(1); 4958 %} 4959 4960 // Floating Point Move/Negate/Abs Double 4961 pipe_class faddD_reg(regD dst, regD src) %{ 4962 single_instruction; 4963 dst : W(write); 4964 src : E(read); 4965 FA : R; 4966 %} 4967 4968 // Floating Point Convert F->D 4969 pipe_class fcvtF2D(regD dst, regF src) %{ 4970 single_instruction; 4971 dst : X(write); 4972 src : E(read); 4973 FA : R; 4974 %} 4975 4976 // Floating Point Convert I->D 4977 pipe_class fcvtI2D(regD dst, regF src) %{ 4978 single_instruction; 4979 dst : X(write); 4980 src : E(read); 4981 FA : R; 4982 %} 4983 4984 // Floating Point Convert LHi->D 4985 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4986 single_instruction; 4987 dst : X(write); 4988 src : E(read); 4989 FA : R; 4990 %} 4991 4992 // Floating Point Convert L->D 4993 pipe_class fcvtL2D(regD dst, regF src) %{ 4994 single_instruction; 4995 dst : X(write); 4996 src : E(read); 4997 FA : R; 4998 %} 4999 5000 // Floating Point Convert L->F 5001 pipe_class fcvtL2F(regD dst, regF src) %{ 5002 single_instruction; 5003 dst : X(write); 5004 src : E(read); 5005 FA : R; 5006 %} 5007 5008 // Floating Point Convert D->F 5009 pipe_class fcvtD2F(regD dst, regF src) %{ 5010 single_instruction; 5011 dst : X(write); 5012 src : E(read); 5013 FA : R; 5014 %} 5015 5016 // Floating Point Convert I->L 5017 pipe_class fcvtI2L(regD dst, regF src) %{ 5018 single_instruction; 5019 dst : X(write); 5020 src : E(read); 5021 FA : R; 5022 %} 5023 5024 // Floating Point Convert D->F 5025 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 5026 instruction_count(1); multiple_bundles; 5027 dst : X(write)+6; 5028 src : E(read); 5029 FA : R; 5030 %} 5031 5032 // Floating Point Convert D->L 5033 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 5034 instruction_count(1); multiple_bundles; 5035 dst : X(write)+6; 5036 src : E(read); 5037 FA : R; 5038 %} 5039 5040 // Floating Point Convert F->I 5041 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 5042 instruction_count(1); multiple_bundles; 5043 dst : X(write)+6; 5044 src : E(read); 5045 FA : R; 5046 %} 5047 5048 // Floating Point Convert F->L 5049 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 5050 instruction_count(1); multiple_bundles; 5051 dst : X(write)+6; 5052 src : E(read); 5053 FA : R; 5054 %} 5055 5056 // Floating Point Convert I->F 5057 pipe_class fcvtI2F(regF dst, regF src) %{ 5058 single_instruction; 5059 dst : X(write); 5060 src : E(read); 5061 FA : R; 5062 %} 5063 5064 // Floating Point Compare 5065 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 5066 single_instruction; 5067 cr : X(write); 5068 src1 : E(read); 5069 src2 : E(read); 5070 FA : R; 5071 %} 5072 5073 // Floating Point Compare 5074 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 5075 single_instruction; 5076 cr : X(write); 5077 src1 : E(read); 5078 src2 : E(read); 5079 FA : R; 5080 %} 5081 5082 // Floating Add Nop 5083 pipe_class fadd_nop() %{ 5084 single_instruction; 5085 FA : R; 5086 %} 5087 5088 // Integer Store to Memory 5089 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 5090 single_instruction; 5091 mem : R(read); 5092 src : C(read); 5093 MS : R; 5094 %} 5095 5096 // Integer Store to Memory 5097 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 5098 single_instruction; 5099 mem : R(read); 5100 src : C(read); 5101 MS : R; 5102 %} 5103 5104 // Integer Store Zero to Memory 5105 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 5106 single_instruction; 5107 mem : R(read); 5108 MS : R; 5109 %} 5110 5111 // Special Stack Slot Store 5112 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 5113 single_instruction; 5114 stkSlot : R(read); 5115 src : C(read); 5116 MS : R; 5117 %} 5118 5119 // Special Stack Slot Store 5120 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 5121 instruction_count(2); multiple_bundles; 5122 stkSlot : R(read); 5123 src : C(read); 5124 MS : R(2); 5125 %} 5126 5127 // Float Store 5128 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 5129 single_instruction; 5130 mem : R(read); 5131 src : C(read); 5132 MS : R; 5133 %} 5134 5135 // Float Store 5136 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 5137 single_instruction; 5138 mem : R(read); 5139 MS : R; 5140 %} 5141 5142 // Double Store 5143 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 5144 instruction_count(1); 5145 mem : R(read); 5146 src : C(read); 5147 MS : R; 5148 %} 5149 5150 // Double Store 5151 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5152 single_instruction; 5153 mem : R(read); 5154 MS : R; 5155 %} 5156 5157 // Special Stack Slot Float Store 5158 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5159 single_instruction; 5160 stkSlot : R(read); 5161 src : C(read); 5162 MS : R; 5163 %} 5164 5165 // Special Stack Slot Double Store 5166 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5167 single_instruction; 5168 stkSlot : R(read); 5169 src : C(read); 5170 MS : R; 5171 %} 5172 5173 // Integer Load (when sign bit propagation not needed) 5174 pipe_class iload_mem(iRegI dst, memory mem) %{ 5175 single_instruction; 5176 mem : R(read); 5177 dst : C(write); 5178 MS : R; 5179 %} 5180 5181 // Integer Load from stack operand 5182 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5183 single_instruction; 5184 mem : R(read); 5185 dst : C(write); 5186 MS : R; 5187 %} 5188 5189 // Integer Load (when sign bit propagation or masking is needed) 5190 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5191 single_instruction; 5192 mem : R(read); 5193 dst : M(write); 5194 MS : R; 5195 %} 5196 5197 // Float Load 5198 pipe_class floadF_mem(regF dst, memory mem) %{ 5199 single_instruction; 5200 mem : R(read); 5201 dst : M(write); 5202 MS : R; 5203 %} 5204 5205 // Float Load 5206 pipe_class floadD_mem(regD dst, memory mem) %{ 5207 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5208 mem : R(read); 5209 dst : M(write); 5210 MS : R; 5211 %} 5212 5213 // Float Load 5214 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5215 single_instruction; 5216 stkSlot : R(read); 5217 dst : M(write); 5218 MS : R; 5219 %} 5220 5221 // Float Load 5222 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5223 single_instruction; 5224 stkSlot : R(read); 5225 dst : M(write); 5226 MS : R; 5227 %} 5228 5229 // Memory Nop 5230 pipe_class mem_nop() %{ 5231 single_instruction; 5232 MS : R; 5233 %} 5234 5235 pipe_class sethi(iRegP dst, immI src) %{ 5236 single_instruction; 5237 dst : E(write); 5238 IALU : R; 5239 %} 5240 5241 pipe_class loadPollP(iRegP poll) %{ 5242 single_instruction; 5243 poll : R(read); 5244 MS : R; 5245 %} 5246 5247 pipe_class br(Universe br, label labl) %{ 5248 single_instruction_with_delay_slot; 5249 BR : R; 5250 %} 5251 5252 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5253 single_instruction_with_delay_slot; 5254 cr : E(read); 5255 BR : R; 5256 %} 5257 5258 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5259 single_instruction_with_delay_slot; 5260 op1 : E(read); 5261 BR : R; 5262 MS : R; 5263 %} 5264 5265 // Compare and branch 5266 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 5267 instruction_count(2); has_delay_slot; 5268 cr : E(write); 5269 src1 : R(read); 5270 src2 : R(read); 5271 IALU : R; 5272 BR : R; 5273 %} 5274 5275 // Compare and branch 5276 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 5277 instruction_count(2); has_delay_slot; 5278 cr : E(write); 5279 src1 : R(read); 5280 IALU : R; 5281 BR : R; 5282 %} 5283 5284 // Compare and branch using cbcond 5285 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 5286 single_instruction; 5287 src1 : E(read); 5288 src2 : E(read); 5289 IALU : R; 5290 BR : R; 5291 %} 5292 5293 // Compare and branch using cbcond 5294 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 5295 single_instruction; 5296 src1 : E(read); 5297 IALU : R; 5298 BR : R; 5299 %} 5300 5301 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5302 single_instruction_with_delay_slot; 5303 cr : E(read); 5304 BR : R; 5305 %} 5306 5307 pipe_class br_nop() %{ 5308 single_instruction; 5309 BR : R; 5310 %} 5311 5312 pipe_class simple_call(method meth) %{ 5313 instruction_count(2); multiple_bundles; force_serialization; 5314 fixed_latency(100); 5315 BR : R(1); 5316 MS : R(1); 5317 A0 : R(1); 5318 %} 5319 5320 pipe_class compiled_call(method meth) %{ 5321 instruction_count(1); multiple_bundles; force_serialization; 5322 fixed_latency(100); 5323 MS : R(1); 5324 %} 5325 5326 pipe_class call(method meth) %{ 5327 instruction_count(0); multiple_bundles; force_serialization; 5328 fixed_latency(100); 5329 %} 5330 5331 pipe_class tail_call(Universe ignore, label labl) %{ 5332 single_instruction; has_delay_slot; 5333 fixed_latency(100); 5334 BR : R(1); 5335 MS : R(1); 5336 %} 5337 5338 pipe_class ret(Universe ignore) %{ 5339 single_instruction; has_delay_slot; 5340 BR : R(1); 5341 MS : R(1); 5342 %} 5343 5344 pipe_class ret_poll(g3RegP poll) %{ 5345 instruction_count(3); has_delay_slot; 5346 poll : E(read); 5347 MS : R; 5348 %} 5349 5350 // The real do-nothing guy 5351 pipe_class empty( ) %{ 5352 instruction_count(0); 5353 %} 5354 5355 pipe_class long_memory_op() %{ 5356 instruction_count(0); multiple_bundles; force_serialization; 5357 fixed_latency(25); 5358 MS : R(1); 5359 %} 5360 5361 // Check-cast 5362 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5363 array : R(read); 5364 match : R(read); 5365 IALU : R(2); 5366 BR : R(2); 5367 MS : R; 5368 %} 5369 5370 // Convert FPU flags into +1,0,-1 5371 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5372 src1 : E(read); 5373 src2 : E(read); 5374 dst : E(write); 5375 FA : R; 5376 MS : R(2); 5377 BR : R(2); 5378 %} 5379 5380 // Compare for p < q, and conditionally add y 5381 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5382 p : E(read); 5383 q : E(read); 5384 y : E(read); 5385 IALU : R(3) 5386 %} 5387 5388 // Perform a compare, then move conditionally in a branch delay slot. 5389 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5390 src2 : E(read); 5391 srcdst : E(read); 5392 IALU : R; 5393 BR : R; 5394 %} 5395 5396 // Define the class for the Nop node 5397 define %{ 5398 MachNop = ialu_nop; 5399 %} 5400 5401 %} 5402 5403 //----------INSTRUCTIONS------------------------------------------------------- 5404 5405 //------------Special Stack Slot instructions - no match rules----------------- 5406 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5407 // No match rule to avoid chain rule match. 5408 effect(DEF dst, USE src); 5409 ins_cost(MEMORY_REF_COST); 5410 size(4); 5411 format %{ "LDF $src,$dst\t! stkI to regF" %} 5412 opcode(Assembler::ldf_op3); 5413 ins_encode(simple_form3_mem_reg(src, dst)); 5414 ins_pipe(floadF_stk); 5415 %} 5416 5417 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5418 // No match rule to avoid chain rule match. 5419 effect(DEF dst, USE src); 5420 ins_cost(MEMORY_REF_COST); 5421 size(4); 5422 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5423 opcode(Assembler::lddf_op3); 5424 ins_encode(simple_form3_mem_reg(src, dst)); 5425 ins_pipe(floadD_stk); 5426 %} 5427 5428 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5429 // No match rule to avoid chain rule match. 5430 effect(DEF dst, USE src); 5431 ins_cost(MEMORY_REF_COST); 5432 size(4); 5433 format %{ "STF $src,$dst\t! regF to stkI" %} 5434 opcode(Assembler::stf_op3); 5435 ins_encode(simple_form3_mem_reg(dst, src)); 5436 ins_pipe(fstoreF_stk_reg); 5437 %} 5438 5439 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5440 // No match rule to avoid chain rule match. 5441 effect(DEF dst, USE src); 5442 ins_cost(MEMORY_REF_COST); 5443 size(4); 5444 format %{ "STDF $src,$dst\t! regD to stkL" %} 5445 opcode(Assembler::stdf_op3); 5446 ins_encode(simple_form3_mem_reg(dst, src)); 5447 ins_pipe(fstoreD_stk_reg); 5448 %} 5449 5450 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5451 effect(DEF dst, USE src); 5452 ins_cost(MEMORY_REF_COST*2); 5453 size(8); 5454 format %{ "STW $src,$dst.hi\t! long\n\t" 5455 "STW R_G0,$dst.lo" %} 5456 opcode(Assembler::stw_op3); 5457 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5458 ins_pipe(lstoreI_stk_reg); 5459 %} 5460 5461 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5462 // No match rule to avoid chain rule match. 5463 effect(DEF dst, USE src); 5464 ins_cost(MEMORY_REF_COST); 5465 size(4); 5466 format %{ "STX $src,$dst\t! regL to stkD" %} 5467 opcode(Assembler::stx_op3); 5468 ins_encode(simple_form3_mem_reg( dst, src ) ); 5469 ins_pipe(istore_stk_reg); 5470 %} 5471 5472 //---------- Chain stack slots between similar types -------- 5473 5474 // Load integer from stack slot 5475 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5476 match(Set dst src); 5477 ins_cost(MEMORY_REF_COST); 5478 5479 size(4); 5480 format %{ "LDUW $src,$dst\t!stk" %} 5481 opcode(Assembler::lduw_op3); 5482 ins_encode(simple_form3_mem_reg( src, dst ) ); 5483 ins_pipe(iload_mem); 5484 %} 5485 5486 // Store integer to stack slot 5487 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5488 match(Set dst src); 5489 ins_cost(MEMORY_REF_COST); 5490 5491 size(4); 5492 format %{ "STW $src,$dst\t!stk" %} 5493 opcode(Assembler::stw_op3); 5494 ins_encode(simple_form3_mem_reg( dst, src ) ); 5495 ins_pipe(istore_mem_reg); 5496 %} 5497 5498 // Load long from stack slot 5499 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5500 match(Set dst src); 5501 5502 ins_cost(MEMORY_REF_COST); 5503 size(4); 5504 format %{ "LDX $src,$dst\t! long" %} 5505 opcode(Assembler::ldx_op3); 5506 ins_encode(simple_form3_mem_reg( src, dst ) ); 5507 ins_pipe(iload_mem); 5508 %} 5509 5510 // Store long to stack slot 5511 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5512 match(Set dst src); 5513 5514 ins_cost(MEMORY_REF_COST); 5515 size(4); 5516 format %{ "STX $src,$dst\t! long" %} 5517 opcode(Assembler::stx_op3); 5518 ins_encode(simple_form3_mem_reg( dst, src ) ); 5519 ins_pipe(istore_mem_reg); 5520 %} 5521 5522 #ifdef _LP64 5523 // Load pointer from stack slot, 64-bit encoding 5524 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5525 match(Set dst src); 5526 ins_cost(MEMORY_REF_COST); 5527 size(4); 5528 format %{ "LDX $src,$dst\t!ptr" %} 5529 opcode(Assembler::ldx_op3); 5530 ins_encode(simple_form3_mem_reg( src, dst ) ); 5531 ins_pipe(iload_mem); 5532 %} 5533 5534 // Store pointer to stack slot 5535 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5536 match(Set dst src); 5537 ins_cost(MEMORY_REF_COST); 5538 size(4); 5539 format %{ "STX $src,$dst\t!ptr" %} 5540 opcode(Assembler::stx_op3); 5541 ins_encode(simple_form3_mem_reg( dst, src ) ); 5542 ins_pipe(istore_mem_reg); 5543 %} 5544 #else // _LP64 5545 // Load pointer from stack slot, 32-bit encoding 5546 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5547 match(Set dst src); 5548 ins_cost(MEMORY_REF_COST); 5549 format %{ "LDUW $src,$dst\t!ptr" %} 5550 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5551 ins_encode(simple_form3_mem_reg( src, dst ) ); 5552 ins_pipe(iload_mem); 5553 %} 5554 5555 // Store pointer to stack slot 5556 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5557 match(Set dst src); 5558 ins_cost(MEMORY_REF_COST); 5559 format %{ "STW $src,$dst\t!ptr" %} 5560 opcode(Assembler::stw_op3, Assembler::ldst_op); 5561 ins_encode(simple_form3_mem_reg( dst, src ) ); 5562 ins_pipe(istore_mem_reg); 5563 %} 5564 #endif // _LP64 5565 5566 //------------Special Nop instructions for bundling - no match rules----------- 5567 // Nop using the A0 functional unit 5568 instruct Nop_A0() %{ 5569 ins_cost(0); 5570 5571 format %{ "NOP ! Alu Pipeline" %} 5572 opcode(Assembler::or_op3, Assembler::arith_op); 5573 ins_encode( form2_nop() ); 5574 ins_pipe(ialu_nop_A0); 5575 %} 5576 5577 // Nop using the A1 functional unit 5578 instruct Nop_A1( ) %{ 5579 ins_cost(0); 5580 5581 format %{ "NOP ! Alu Pipeline" %} 5582 opcode(Assembler::or_op3, Assembler::arith_op); 5583 ins_encode( form2_nop() ); 5584 ins_pipe(ialu_nop_A1); 5585 %} 5586 5587 // Nop using the memory functional unit 5588 instruct Nop_MS( ) %{ 5589 ins_cost(0); 5590 5591 format %{ "NOP ! Memory Pipeline" %} 5592 ins_encode( emit_mem_nop ); 5593 ins_pipe(mem_nop); 5594 %} 5595 5596 // Nop using the floating add functional unit 5597 instruct Nop_FA( ) %{ 5598 ins_cost(0); 5599 5600 format %{ "NOP ! Floating Add Pipeline" %} 5601 ins_encode( emit_fadd_nop ); 5602 ins_pipe(fadd_nop); 5603 %} 5604 5605 // Nop using the branch functional unit 5606 instruct Nop_BR( ) %{ 5607 ins_cost(0); 5608 5609 format %{ "NOP ! Branch Pipeline" %} 5610 ins_encode( emit_br_nop ); 5611 ins_pipe(br_nop); 5612 %} 5613 5614 //----------Load/Store/Move Instructions--------------------------------------- 5615 //----------Load Instructions-------------------------------------------------- 5616 // Load Byte (8bit signed) 5617 instruct loadB(iRegI dst, memory mem) %{ 5618 match(Set dst (LoadB mem)); 5619 ins_cost(MEMORY_REF_COST); 5620 5621 size(4); 5622 format %{ "LDSB $mem,$dst\t! byte" %} 5623 ins_encode %{ 5624 __ ldsb($mem$$Address, $dst$$Register); 5625 %} 5626 ins_pipe(iload_mask_mem); 5627 %} 5628 5629 // Load Byte (8bit signed) into a Long Register 5630 instruct loadB2L(iRegL dst, memory mem) %{ 5631 match(Set dst (ConvI2L (LoadB mem))); 5632 ins_cost(MEMORY_REF_COST); 5633 5634 size(4); 5635 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5636 ins_encode %{ 5637 __ ldsb($mem$$Address, $dst$$Register); 5638 %} 5639 ins_pipe(iload_mask_mem); 5640 %} 5641 5642 // Load Unsigned Byte (8bit UNsigned) into an int reg 5643 instruct loadUB(iRegI dst, memory mem) %{ 5644 match(Set dst (LoadUB mem)); 5645 ins_cost(MEMORY_REF_COST); 5646 5647 size(4); 5648 format %{ "LDUB $mem,$dst\t! ubyte" %} 5649 ins_encode %{ 5650 __ ldub($mem$$Address, $dst$$Register); 5651 %} 5652 ins_pipe(iload_mem); 5653 %} 5654 5655 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5656 instruct loadUB2L(iRegL dst, memory mem) %{ 5657 match(Set dst (ConvI2L (LoadUB mem))); 5658 ins_cost(MEMORY_REF_COST); 5659 5660 size(4); 5661 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5662 ins_encode %{ 5663 __ ldub($mem$$Address, $dst$$Register); 5664 %} 5665 ins_pipe(iload_mem); 5666 %} 5667 5668 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5669 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5670 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5671 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5672 5673 size(2*4); 5674 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5675 "AND $dst,right_n_bits($mask, 8),$dst" %} 5676 ins_encode %{ 5677 __ ldub($mem$$Address, $dst$$Register); 5678 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5679 %} 5680 ins_pipe(iload_mem); 5681 %} 5682 5683 // Load Short (16bit signed) 5684 instruct loadS(iRegI dst, memory mem) %{ 5685 match(Set dst (LoadS mem)); 5686 ins_cost(MEMORY_REF_COST); 5687 5688 size(4); 5689 format %{ "LDSH $mem,$dst\t! short" %} 5690 ins_encode %{ 5691 __ ldsh($mem$$Address, $dst$$Register); 5692 %} 5693 ins_pipe(iload_mask_mem); 5694 %} 5695 5696 // Load Short (16 bit signed) to Byte (8 bit signed) 5697 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5698 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5699 ins_cost(MEMORY_REF_COST); 5700 5701 size(4); 5702 5703 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5704 ins_encode %{ 5705 __ ldsb($mem$$Address, $dst$$Register, 1); 5706 %} 5707 ins_pipe(iload_mask_mem); 5708 %} 5709 5710 // Load Short (16bit signed) into a Long Register 5711 instruct loadS2L(iRegL dst, memory mem) %{ 5712 match(Set dst (ConvI2L (LoadS mem))); 5713 ins_cost(MEMORY_REF_COST); 5714 5715 size(4); 5716 format %{ "LDSH $mem,$dst\t! short -> long" %} 5717 ins_encode %{ 5718 __ ldsh($mem$$Address, $dst$$Register); 5719 %} 5720 ins_pipe(iload_mask_mem); 5721 %} 5722 5723 // Load Unsigned Short/Char (16bit UNsigned) 5724 instruct loadUS(iRegI dst, memory mem) %{ 5725 match(Set dst (LoadUS mem)); 5726 ins_cost(MEMORY_REF_COST); 5727 5728 size(4); 5729 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5730 ins_encode %{ 5731 __ lduh($mem$$Address, $dst$$Register); 5732 %} 5733 ins_pipe(iload_mem); 5734 %} 5735 5736 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5737 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5738 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5739 ins_cost(MEMORY_REF_COST); 5740 5741 size(4); 5742 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5743 ins_encode %{ 5744 __ ldsb($mem$$Address, $dst$$Register, 1); 5745 %} 5746 ins_pipe(iload_mask_mem); 5747 %} 5748 5749 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5750 instruct loadUS2L(iRegL dst, memory mem) %{ 5751 match(Set dst (ConvI2L (LoadUS mem))); 5752 ins_cost(MEMORY_REF_COST); 5753 5754 size(4); 5755 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5756 ins_encode %{ 5757 __ lduh($mem$$Address, $dst$$Register); 5758 %} 5759 ins_pipe(iload_mem); 5760 %} 5761 5762 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5763 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5764 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5765 ins_cost(MEMORY_REF_COST); 5766 5767 size(4); 5768 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5769 ins_encode %{ 5770 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5771 %} 5772 ins_pipe(iload_mem); 5773 %} 5774 5775 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5776 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5777 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5778 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5779 5780 size(2*4); 5781 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5782 "AND $dst,$mask,$dst" %} 5783 ins_encode %{ 5784 Register Rdst = $dst$$Register; 5785 __ lduh($mem$$Address, Rdst); 5786 __ and3(Rdst, $mask$$constant, Rdst); 5787 %} 5788 ins_pipe(iload_mem); 5789 %} 5790 5791 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5792 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5793 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5794 effect(TEMP dst, TEMP tmp); 5795 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5796 5797 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5798 "SET right_n_bits($mask, 16),$tmp\n\t" 5799 "AND $dst,$tmp,$dst" %} 5800 ins_encode %{ 5801 Register Rdst = $dst$$Register; 5802 Register Rtmp = $tmp$$Register; 5803 __ lduh($mem$$Address, Rdst); 5804 __ set($mask$$constant & right_n_bits(16), Rtmp); 5805 __ and3(Rdst, Rtmp, Rdst); 5806 %} 5807 ins_pipe(iload_mem); 5808 %} 5809 5810 // Load Integer 5811 instruct loadI(iRegI dst, memory mem) %{ 5812 match(Set dst (LoadI mem)); 5813 ins_cost(MEMORY_REF_COST); 5814 5815 size(4); 5816 format %{ "LDUW $mem,$dst\t! int" %} 5817 ins_encode %{ 5818 __ lduw($mem$$Address, $dst$$Register); 5819 %} 5820 ins_pipe(iload_mem); 5821 %} 5822 5823 // Load Integer to Byte (8 bit signed) 5824 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5825 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5826 ins_cost(MEMORY_REF_COST); 5827 5828 size(4); 5829 5830 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5831 ins_encode %{ 5832 __ ldsb($mem$$Address, $dst$$Register, 3); 5833 %} 5834 ins_pipe(iload_mask_mem); 5835 %} 5836 5837 // Load Integer to Unsigned Byte (8 bit UNsigned) 5838 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5839 match(Set dst (AndI (LoadI mem) mask)); 5840 ins_cost(MEMORY_REF_COST); 5841 5842 size(4); 5843 5844 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5845 ins_encode %{ 5846 __ ldub($mem$$Address, $dst$$Register, 3); 5847 %} 5848 ins_pipe(iload_mask_mem); 5849 %} 5850 5851 // Load Integer to Short (16 bit signed) 5852 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5853 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5854 ins_cost(MEMORY_REF_COST); 5855 5856 size(4); 5857 5858 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5859 ins_encode %{ 5860 __ ldsh($mem$$Address, $dst$$Register, 2); 5861 %} 5862 ins_pipe(iload_mask_mem); 5863 %} 5864 5865 // Load Integer to Unsigned Short (16 bit UNsigned) 5866 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5867 match(Set dst (AndI (LoadI mem) mask)); 5868 ins_cost(MEMORY_REF_COST); 5869 5870 size(4); 5871 5872 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5873 ins_encode %{ 5874 __ lduh($mem$$Address, $dst$$Register, 2); 5875 %} 5876 ins_pipe(iload_mask_mem); 5877 %} 5878 5879 // Load Integer into a Long Register 5880 instruct loadI2L(iRegL dst, memory mem) %{ 5881 match(Set dst (ConvI2L (LoadI mem))); 5882 ins_cost(MEMORY_REF_COST); 5883 5884 size(4); 5885 format %{ "LDSW $mem,$dst\t! int -> long" %} 5886 ins_encode %{ 5887 __ ldsw($mem$$Address, $dst$$Register); 5888 %} 5889 ins_pipe(iload_mask_mem); 5890 %} 5891 5892 // Load Integer with mask 0xFF into a Long Register 5893 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5894 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5895 ins_cost(MEMORY_REF_COST); 5896 5897 size(4); 5898 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5899 ins_encode %{ 5900 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5901 %} 5902 ins_pipe(iload_mem); 5903 %} 5904 5905 // Load Integer with mask 0xFFFF into a Long Register 5906 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5907 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5908 ins_cost(MEMORY_REF_COST); 5909 5910 size(4); 5911 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5912 ins_encode %{ 5913 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5914 %} 5915 ins_pipe(iload_mem); 5916 %} 5917 5918 // Load Integer with a 12-bit mask into a Long Register 5919 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5920 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5921 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5922 5923 size(2*4); 5924 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5925 "AND $dst,$mask,$dst" %} 5926 ins_encode %{ 5927 Register Rdst = $dst$$Register; 5928 __ lduw($mem$$Address, Rdst); 5929 __ and3(Rdst, $mask$$constant, Rdst); 5930 %} 5931 ins_pipe(iload_mem); 5932 %} 5933 5934 // Load Integer with a 31-bit mask into a Long Register 5935 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5936 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5937 effect(TEMP dst, TEMP tmp); 5938 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5939 5940 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5941 "SET $mask,$tmp\n\t" 5942 "AND $dst,$tmp,$dst" %} 5943 ins_encode %{ 5944 Register Rdst = $dst$$Register; 5945 Register Rtmp = $tmp$$Register; 5946 __ lduw($mem$$Address, Rdst); 5947 __ set($mask$$constant, Rtmp); 5948 __ and3(Rdst, Rtmp, Rdst); 5949 %} 5950 ins_pipe(iload_mem); 5951 %} 5952 5953 // Load Unsigned Integer into a Long Register 5954 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5955 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5956 ins_cost(MEMORY_REF_COST); 5957 5958 size(4); 5959 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5960 ins_encode %{ 5961 __ lduw($mem$$Address, $dst$$Register); 5962 %} 5963 ins_pipe(iload_mem); 5964 %} 5965 5966 // Load Long - aligned 5967 instruct loadL(iRegL dst, memory mem ) %{ 5968 match(Set dst (LoadL mem)); 5969 ins_cost(MEMORY_REF_COST); 5970 5971 size(4); 5972 format %{ "LDX $mem,$dst\t! long" %} 5973 ins_encode %{ 5974 __ ldx($mem$$Address, $dst$$Register); 5975 %} 5976 ins_pipe(iload_mem); 5977 %} 5978 5979 // Load Long - UNaligned 5980 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5981 match(Set dst (LoadL_unaligned mem)); 5982 effect(KILL tmp); 5983 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5984 size(16); 5985 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5986 "\tLDUW $mem ,$dst\n" 5987 "\tSLLX #32, $dst, $dst\n" 5988 "\tOR $dst, R_O7, $dst" %} 5989 opcode(Assembler::lduw_op3); 5990 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5991 ins_pipe(iload_mem); 5992 %} 5993 5994 // Load Range 5995 instruct loadRange(iRegI dst, memory mem) %{ 5996 match(Set dst (LoadRange mem)); 5997 ins_cost(MEMORY_REF_COST); 5998 5999 size(4); 6000 format %{ "LDUW $mem,$dst\t! range" %} 6001 opcode(Assembler::lduw_op3); 6002 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6003 ins_pipe(iload_mem); 6004 %} 6005 6006 // Load Integer into %f register (for fitos/fitod) 6007 instruct loadI_freg(regF dst, memory mem) %{ 6008 match(Set dst (LoadI mem)); 6009 ins_cost(MEMORY_REF_COST); 6010 size(4); 6011 6012 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 6013 opcode(Assembler::ldf_op3); 6014 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6015 ins_pipe(floadF_mem); 6016 %} 6017 6018 // Load Pointer 6019 instruct loadP(iRegP dst, memory mem) %{ 6020 match(Set dst (LoadP mem)); 6021 ins_cost(MEMORY_REF_COST); 6022 size(4); 6023 6024 #ifndef _LP64 6025 format %{ "LDUW $mem,$dst\t! ptr" %} 6026 ins_encode %{ 6027 __ lduw($mem$$Address, $dst$$Register); 6028 %} 6029 #else 6030 format %{ "LDX $mem,$dst\t! ptr" %} 6031 ins_encode %{ 6032 __ ldx($mem$$Address, $dst$$Register); 6033 %} 6034 #endif 6035 ins_pipe(iload_mem); 6036 %} 6037 6038 // Load Compressed Pointer 6039 instruct loadN(iRegN dst, memory mem) %{ 6040 match(Set dst (LoadN mem)); 6041 ins_cost(MEMORY_REF_COST); 6042 size(4); 6043 6044 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 6045 ins_encode %{ 6046 __ lduw($mem$$Address, $dst$$Register); 6047 %} 6048 ins_pipe(iload_mem); 6049 %} 6050 6051 // Load Klass Pointer 6052 instruct loadKlass(iRegP dst, memory mem) %{ 6053 match(Set dst (LoadKlass mem)); 6054 ins_cost(MEMORY_REF_COST); 6055 size(4); 6056 6057 #ifndef _LP64 6058 format %{ "LDUW $mem,$dst\t! klass ptr" %} 6059 ins_encode %{ 6060 __ lduw($mem$$Address, $dst$$Register); 6061 %} 6062 #else 6063 format %{ "LDX $mem,$dst\t! klass ptr" %} 6064 ins_encode %{ 6065 __ ldx($mem$$Address, $dst$$Register); 6066 %} 6067 #endif 6068 ins_pipe(iload_mem); 6069 %} 6070 6071 // Load narrow Klass Pointer 6072 instruct loadNKlass(iRegN dst, memory mem) %{ 6073 match(Set dst (LoadNKlass mem)); 6074 ins_cost(MEMORY_REF_COST); 6075 size(4); 6076 6077 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 6078 ins_encode %{ 6079 __ lduw($mem$$Address, $dst$$Register); 6080 %} 6081 ins_pipe(iload_mem); 6082 %} 6083 6084 // Load Double 6085 instruct loadD(regD dst, memory mem) %{ 6086 match(Set dst (LoadD mem)); 6087 ins_cost(MEMORY_REF_COST); 6088 6089 size(4); 6090 format %{ "LDDF $mem,$dst" %} 6091 opcode(Assembler::lddf_op3); 6092 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6093 ins_pipe(floadD_mem); 6094 %} 6095 6096 // Load Double - UNaligned 6097 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 6098 match(Set dst (LoadD_unaligned mem)); 6099 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 6100 size(8); 6101 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 6102 "\tLDF $mem+4,$dst.lo\t!" %} 6103 opcode(Assembler::ldf_op3); 6104 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 6105 ins_pipe(iload_mem); 6106 %} 6107 6108 // Load Float 6109 instruct loadF(regF dst, memory mem) %{ 6110 match(Set dst (LoadF mem)); 6111 ins_cost(MEMORY_REF_COST); 6112 6113 size(4); 6114 format %{ "LDF $mem,$dst" %} 6115 opcode(Assembler::ldf_op3); 6116 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6117 ins_pipe(floadF_mem); 6118 %} 6119 6120 // Load Constant 6121 instruct loadConI( iRegI dst, immI src ) %{ 6122 match(Set dst src); 6123 ins_cost(DEFAULT_COST * 3/2); 6124 format %{ "SET $src,$dst" %} 6125 ins_encode( Set32(src, dst) ); 6126 ins_pipe(ialu_hi_lo_reg); 6127 %} 6128 6129 instruct loadConI13( iRegI dst, immI13 src ) %{ 6130 match(Set dst src); 6131 6132 size(4); 6133 format %{ "MOV $src,$dst" %} 6134 ins_encode( Set13( src, dst ) ); 6135 ins_pipe(ialu_imm); 6136 %} 6137 6138 #ifndef _LP64 6139 instruct loadConP(iRegP dst, immP con) %{ 6140 match(Set dst con); 6141 ins_cost(DEFAULT_COST * 3/2); 6142 format %{ "SET $con,$dst\t!ptr" %} 6143 ins_encode %{ 6144 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 6145 intptr_t val = $con$$constant; 6146 if (constant_reloc == relocInfo::oop_type) { 6147 __ set_oop_constant((jobject) val, $dst$$Register); 6148 } else if (constant_reloc == relocInfo::metadata_type) { 6149 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6150 } else { // non-oop pointers, e.g. card mark base, heap top 6151 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6152 __ set(val, $dst$$Register); 6153 } 6154 %} 6155 ins_pipe(loadConP); 6156 %} 6157 #else 6158 instruct loadConP_set(iRegP dst, immP_set con) %{ 6159 match(Set dst con); 6160 ins_cost(DEFAULT_COST * 3/2); 6161 format %{ "SET $con,$dst\t! ptr" %} 6162 ins_encode %{ 6163 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 6164 intptr_t val = $con$$constant; 6165 if (constant_reloc == relocInfo::oop_type) { 6166 __ set_oop_constant((jobject) val, $dst$$Register); 6167 } else if (constant_reloc == relocInfo::metadata_type) { 6168 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6169 } else { // non-oop pointers, e.g. card mark base, heap top 6170 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6171 __ set(val, $dst$$Register); 6172 } 6173 %} 6174 ins_pipe(loadConP); 6175 %} 6176 6177 instruct loadConP_load(iRegP dst, immP_load con) %{ 6178 match(Set dst con); 6179 ins_cost(MEMORY_REF_COST); 6180 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 6181 ins_encode %{ 6182 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6183 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 6184 %} 6185 ins_pipe(loadConP); 6186 %} 6187 6188 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 6189 match(Set dst con); 6190 ins_cost(DEFAULT_COST * 3/2); 6191 format %{ "SET $con,$dst\t! non-oop ptr" %} 6192 ins_encode %{ 6193 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 6194 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 6195 } else { 6196 __ set($con$$constant, $dst$$Register); 6197 } 6198 %} 6199 ins_pipe(loadConP); 6200 %} 6201 #endif // _LP64 6202 6203 instruct loadConP0(iRegP dst, immP0 src) %{ 6204 match(Set dst src); 6205 6206 size(4); 6207 format %{ "CLR $dst\t!ptr" %} 6208 ins_encode %{ 6209 __ clr($dst$$Register); 6210 %} 6211 ins_pipe(ialu_imm); 6212 %} 6213 6214 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6215 match(Set dst src); 6216 ins_cost(DEFAULT_COST); 6217 format %{ "SET $src,$dst\t!ptr" %} 6218 ins_encode %{ 6219 AddressLiteral polling_page(os::get_polling_page()); 6220 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6221 %} 6222 ins_pipe(loadConP_poll); 6223 %} 6224 6225 instruct loadConN0(iRegN dst, immN0 src) %{ 6226 match(Set dst src); 6227 6228 size(4); 6229 format %{ "CLR $dst\t! compressed NULL ptr" %} 6230 ins_encode %{ 6231 __ clr($dst$$Register); 6232 %} 6233 ins_pipe(ialu_imm); 6234 %} 6235 6236 instruct loadConN(iRegN dst, immN src) %{ 6237 match(Set dst src); 6238 ins_cost(DEFAULT_COST * 3/2); 6239 format %{ "SET $src,$dst\t! compressed ptr" %} 6240 ins_encode %{ 6241 Register dst = $dst$$Register; 6242 __ set_narrow_oop((jobject)$src$$constant, dst); 6243 %} 6244 ins_pipe(ialu_hi_lo_reg); 6245 %} 6246 6247 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 6248 match(Set dst src); 6249 ins_cost(DEFAULT_COST * 3/2); 6250 format %{ "SET $src,$dst\t! compressed klass ptr" %} 6251 ins_encode %{ 6252 Register dst = $dst$$Register; 6253 __ set_narrow_klass((Klass*)$src$$constant, dst); 6254 %} 6255 ins_pipe(ialu_hi_lo_reg); 6256 %} 6257 6258 // Materialize long value (predicated by immL_cheap). 6259 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 6260 match(Set dst con); 6261 effect(KILL tmp); 6262 ins_cost(DEFAULT_COST * 3); 6263 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 6264 ins_encode %{ 6265 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 6266 %} 6267 ins_pipe(loadConL); 6268 %} 6269 6270 // Load long value from constant table (predicated by immL_expensive). 6271 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 6272 match(Set dst con); 6273 ins_cost(MEMORY_REF_COST); 6274 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 6275 ins_encode %{ 6276 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6277 __ ldx($constanttablebase, con_offset, $dst$$Register); 6278 %} 6279 ins_pipe(loadConL); 6280 %} 6281 6282 instruct loadConL0( iRegL dst, immL0 src ) %{ 6283 match(Set dst src); 6284 ins_cost(DEFAULT_COST); 6285 size(4); 6286 format %{ "CLR $dst\t! long" %} 6287 ins_encode( Set13( src, dst ) ); 6288 ins_pipe(ialu_imm); 6289 %} 6290 6291 instruct loadConL13( iRegL dst, immL13 src ) %{ 6292 match(Set dst src); 6293 ins_cost(DEFAULT_COST * 2); 6294 6295 size(4); 6296 format %{ "MOV $src,$dst\t! long" %} 6297 ins_encode( Set13( src, dst ) ); 6298 ins_pipe(ialu_imm); 6299 %} 6300 6301 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 6302 match(Set dst con); 6303 effect(KILL tmp); 6304 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 6305 ins_encode %{ 6306 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6307 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 6308 %} 6309 ins_pipe(loadConFD); 6310 %} 6311 6312 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 6313 match(Set dst con); 6314 effect(KILL tmp); 6315 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 6316 ins_encode %{ 6317 // XXX This is a quick fix for 6833573. 6318 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6319 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6320 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 6321 %} 6322 ins_pipe(loadConFD); 6323 %} 6324 6325 // Prefetch instructions for allocation. 6326 // Must be safe to execute with invalid address (cannot fault). 6327 6328 instruct prefetchAlloc( memory mem ) %{ 6329 predicate(AllocatePrefetchInstr == 0); 6330 match( PrefetchAllocation mem ); 6331 ins_cost(MEMORY_REF_COST); 6332 size(4); 6333 6334 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 6335 opcode(Assembler::prefetch_op3); 6336 ins_encode( form3_mem_prefetch_write( mem ) ); 6337 ins_pipe(iload_mem); 6338 %} 6339 6340 // Use BIS instruction to prefetch for allocation. 6341 // Could fault, need space at the end of TLAB. 6342 instruct prefetchAlloc_bis( iRegP dst ) %{ 6343 predicate(AllocatePrefetchInstr == 1); 6344 match( PrefetchAllocation dst ); 6345 ins_cost(MEMORY_REF_COST); 6346 size(4); 6347 6348 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 6349 ins_encode %{ 6350 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 6351 %} 6352 ins_pipe(istore_mem_reg); 6353 %} 6354 6355 // Next code is used for finding next cache line address to prefetch. 6356 #ifndef _LP64 6357 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ 6358 match(Set dst (CastX2P (AndI (CastP2X src) mask))); 6359 ins_cost(DEFAULT_COST); 6360 size(4); 6361 6362 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6363 ins_encode %{ 6364 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6365 %} 6366 ins_pipe(ialu_reg_imm); 6367 %} 6368 #else 6369 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 6370 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 6371 ins_cost(DEFAULT_COST); 6372 size(4); 6373 6374 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6375 ins_encode %{ 6376 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6377 %} 6378 ins_pipe(ialu_reg_imm); 6379 %} 6380 #endif 6381 6382 //----------Store Instructions------------------------------------------------- 6383 // Store Byte 6384 instruct storeB(memory mem, iRegI src) %{ 6385 match(Set mem (StoreB mem src)); 6386 ins_cost(MEMORY_REF_COST); 6387 6388 size(4); 6389 format %{ "STB $src,$mem\t! byte" %} 6390 opcode(Assembler::stb_op3); 6391 ins_encode(simple_form3_mem_reg( mem, src ) ); 6392 ins_pipe(istore_mem_reg); 6393 %} 6394 6395 instruct storeB0(memory mem, immI0 src) %{ 6396 match(Set mem (StoreB mem src)); 6397 ins_cost(MEMORY_REF_COST); 6398 6399 size(4); 6400 format %{ "STB $src,$mem\t! byte" %} 6401 opcode(Assembler::stb_op3); 6402 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6403 ins_pipe(istore_mem_zero); 6404 %} 6405 6406 instruct storeCM0(memory mem, immI0 src) %{ 6407 match(Set mem (StoreCM mem src)); 6408 ins_cost(MEMORY_REF_COST); 6409 6410 size(4); 6411 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6412 opcode(Assembler::stb_op3); 6413 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6414 ins_pipe(istore_mem_zero); 6415 %} 6416 6417 // Store Char/Short 6418 instruct storeC(memory mem, iRegI src) %{ 6419 match(Set mem (StoreC mem src)); 6420 ins_cost(MEMORY_REF_COST); 6421 6422 size(4); 6423 format %{ "STH $src,$mem\t! short" %} 6424 opcode(Assembler::sth_op3); 6425 ins_encode(simple_form3_mem_reg( mem, src ) ); 6426 ins_pipe(istore_mem_reg); 6427 %} 6428 6429 instruct storeC0(memory mem, immI0 src) %{ 6430 match(Set mem (StoreC mem src)); 6431 ins_cost(MEMORY_REF_COST); 6432 6433 size(4); 6434 format %{ "STH $src,$mem\t! short" %} 6435 opcode(Assembler::sth_op3); 6436 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6437 ins_pipe(istore_mem_zero); 6438 %} 6439 6440 // Store Integer 6441 instruct storeI(memory mem, iRegI src) %{ 6442 match(Set mem (StoreI mem src)); 6443 ins_cost(MEMORY_REF_COST); 6444 6445 size(4); 6446 format %{ "STW $src,$mem" %} 6447 opcode(Assembler::stw_op3); 6448 ins_encode(simple_form3_mem_reg( mem, src ) ); 6449 ins_pipe(istore_mem_reg); 6450 %} 6451 6452 // Store Long 6453 instruct storeL(memory mem, iRegL src) %{ 6454 match(Set mem (StoreL mem src)); 6455 ins_cost(MEMORY_REF_COST); 6456 size(4); 6457 format %{ "STX $src,$mem\t! long" %} 6458 opcode(Assembler::stx_op3); 6459 ins_encode(simple_form3_mem_reg( mem, src ) ); 6460 ins_pipe(istore_mem_reg); 6461 %} 6462 6463 instruct storeI0(memory mem, immI0 src) %{ 6464 match(Set mem (StoreI mem src)); 6465 ins_cost(MEMORY_REF_COST); 6466 6467 size(4); 6468 format %{ "STW $src,$mem" %} 6469 opcode(Assembler::stw_op3); 6470 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6471 ins_pipe(istore_mem_zero); 6472 %} 6473 6474 instruct storeL0(memory mem, immL0 src) %{ 6475 match(Set mem (StoreL mem src)); 6476 ins_cost(MEMORY_REF_COST); 6477 6478 size(4); 6479 format %{ "STX $src,$mem" %} 6480 opcode(Assembler::stx_op3); 6481 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6482 ins_pipe(istore_mem_zero); 6483 %} 6484 6485 // Store Integer from float register (used after fstoi) 6486 instruct storeI_Freg(memory mem, regF src) %{ 6487 match(Set mem (StoreI mem src)); 6488 ins_cost(MEMORY_REF_COST); 6489 6490 size(4); 6491 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6492 opcode(Assembler::stf_op3); 6493 ins_encode(simple_form3_mem_reg( mem, src ) ); 6494 ins_pipe(fstoreF_mem_reg); 6495 %} 6496 6497 // Store Pointer 6498 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6499 match(Set dst (StoreP dst src)); 6500 ins_cost(MEMORY_REF_COST); 6501 size(4); 6502 6503 #ifndef _LP64 6504 format %{ "STW $src,$dst\t! ptr" %} 6505 opcode(Assembler::stw_op3, 0, REGP_OP); 6506 #else 6507 format %{ "STX $src,$dst\t! ptr" %} 6508 opcode(Assembler::stx_op3, 0, REGP_OP); 6509 #endif 6510 ins_encode( form3_mem_reg( dst, src ) ); 6511 ins_pipe(istore_mem_spORreg); 6512 %} 6513 6514 instruct storeP0(memory dst, immP0 src) %{ 6515 match(Set dst (StoreP dst src)); 6516 ins_cost(MEMORY_REF_COST); 6517 size(4); 6518 6519 #ifndef _LP64 6520 format %{ "STW $src,$dst\t! ptr" %} 6521 opcode(Assembler::stw_op3, 0, REGP_OP); 6522 #else 6523 format %{ "STX $src,$dst\t! ptr" %} 6524 opcode(Assembler::stx_op3, 0, REGP_OP); 6525 #endif 6526 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6527 ins_pipe(istore_mem_zero); 6528 %} 6529 6530 // Store Compressed Pointer 6531 instruct storeN(memory dst, iRegN src) %{ 6532 match(Set dst (StoreN dst src)); 6533 ins_cost(MEMORY_REF_COST); 6534 size(4); 6535 6536 format %{ "STW $src,$dst\t! compressed ptr" %} 6537 ins_encode %{ 6538 Register base = as_Register($dst$$base); 6539 Register index = as_Register($dst$$index); 6540 Register src = $src$$Register; 6541 if (index != G0) { 6542 __ stw(src, base, index); 6543 } else { 6544 __ stw(src, base, $dst$$disp); 6545 } 6546 %} 6547 ins_pipe(istore_mem_spORreg); 6548 %} 6549 6550 instruct storeNKlass(memory dst, iRegN src) %{ 6551 match(Set dst (StoreNKlass dst src)); 6552 ins_cost(MEMORY_REF_COST); 6553 size(4); 6554 6555 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6556 ins_encode %{ 6557 Register base = as_Register($dst$$base); 6558 Register index = as_Register($dst$$index); 6559 Register src = $src$$Register; 6560 if (index != G0) { 6561 __ stw(src, base, index); 6562 } else { 6563 __ stw(src, base, $dst$$disp); 6564 } 6565 %} 6566 ins_pipe(istore_mem_spORreg); 6567 %} 6568 6569 instruct storeN0(memory dst, immN0 src) %{ 6570 match(Set dst (StoreN dst src)); 6571 ins_cost(MEMORY_REF_COST); 6572 size(4); 6573 6574 format %{ "STW $src,$dst\t! compressed ptr" %} 6575 ins_encode %{ 6576 Register base = as_Register($dst$$base); 6577 Register index = as_Register($dst$$index); 6578 if (index != G0) { 6579 __ stw(0, base, index); 6580 } else { 6581 __ stw(0, base, $dst$$disp); 6582 } 6583 %} 6584 ins_pipe(istore_mem_zero); 6585 %} 6586 6587 // Store Double 6588 instruct storeD( memory mem, regD src) %{ 6589 match(Set mem (StoreD mem src)); 6590 ins_cost(MEMORY_REF_COST); 6591 6592 size(4); 6593 format %{ "STDF $src,$mem" %} 6594 opcode(Assembler::stdf_op3); 6595 ins_encode(simple_form3_mem_reg( mem, src ) ); 6596 ins_pipe(fstoreD_mem_reg); 6597 %} 6598 6599 instruct storeD0( memory mem, immD0 src) %{ 6600 match(Set mem (StoreD mem src)); 6601 ins_cost(MEMORY_REF_COST); 6602 6603 size(4); 6604 format %{ "STX $src,$mem" %} 6605 opcode(Assembler::stx_op3); 6606 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6607 ins_pipe(fstoreD_mem_zero); 6608 %} 6609 6610 // Store Float 6611 instruct storeF( memory mem, regF src) %{ 6612 match(Set mem (StoreF mem src)); 6613 ins_cost(MEMORY_REF_COST); 6614 6615 size(4); 6616 format %{ "STF $src,$mem" %} 6617 opcode(Assembler::stf_op3); 6618 ins_encode(simple_form3_mem_reg( mem, src ) ); 6619 ins_pipe(fstoreF_mem_reg); 6620 %} 6621 6622 instruct storeF0( memory mem, immF0 src) %{ 6623 match(Set mem (StoreF mem src)); 6624 ins_cost(MEMORY_REF_COST); 6625 6626 size(4); 6627 format %{ "STW $src,$mem\t! storeF0" %} 6628 opcode(Assembler::stw_op3); 6629 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6630 ins_pipe(fstoreF_mem_zero); 6631 %} 6632 6633 // Convert oop pointer into compressed form 6634 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6635 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6636 match(Set dst (EncodeP src)); 6637 format %{ "encode_heap_oop $src, $dst" %} 6638 ins_encode %{ 6639 __ encode_heap_oop($src$$Register, $dst$$Register); 6640 %} 6641 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6642 ins_pipe(ialu_reg); 6643 %} 6644 6645 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6646 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6647 match(Set dst (EncodeP src)); 6648 format %{ "encode_heap_oop_not_null $src, $dst" %} 6649 ins_encode %{ 6650 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6651 %} 6652 ins_pipe(ialu_reg); 6653 %} 6654 6655 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6656 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6657 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6658 match(Set dst (DecodeN src)); 6659 format %{ "decode_heap_oop $src, $dst" %} 6660 ins_encode %{ 6661 __ decode_heap_oop($src$$Register, $dst$$Register); 6662 %} 6663 ins_pipe(ialu_reg); 6664 %} 6665 6666 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6667 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6668 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6669 match(Set dst (DecodeN src)); 6670 format %{ "decode_heap_oop_not_null $src, $dst" %} 6671 ins_encode %{ 6672 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6673 %} 6674 ins_pipe(ialu_reg); 6675 %} 6676 6677 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6678 match(Set dst (EncodePKlass src)); 6679 format %{ "encode_klass_not_null $src, $dst" %} 6680 ins_encode %{ 6681 __ encode_klass_not_null($src$$Register, $dst$$Register); 6682 %} 6683 ins_pipe(ialu_reg); 6684 %} 6685 6686 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6687 match(Set dst (DecodeNKlass src)); 6688 format %{ "decode_klass_not_null $src, $dst" %} 6689 ins_encode %{ 6690 __ decode_klass_not_null($src$$Register, $dst$$Register); 6691 %} 6692 ins_pipe(ialu_reg); 6693 %} 6694 6695 //----------MemBar Instructions----------------------------------------------- 6696 // Memory barrier flavors 6697 6698 instruct membar_acquire() %{ 6699 match(MemBarAcquire); 6700 match(LoadFence); 6701 ins_cost(4*MEMORY_REF_COST); 6702 6703 size(0); 6704 format %{ "MEMBAR-acquire" %} 6705 ins_encode( enc_membar_acquire ); 6706 ins_pipe(long_memory_op); 6707 %} 6708 6709 instruct membar_acquire_lock() %{ 6710 match(MemBarAcquireLock); 6711 ins_cost(0); 6712 6713 size(0); 6714 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6715 ins_encode( ); 6716 ins_pipe(empty); 6717 %} 6718 6719 instruct membar_release() %{ 6720 match(MemBarRelease); 6721 match(StoreFence); 6722 ins_cost(4*MEMORY_REF_COST); 6723 6724 size(0); 6725 format %{ "MEMBAR-release" %} 6726 ins_encode( enc_membar_release ); 6727 ins_pipe(long_memory_op); 6728 %} 6729 6730 instruct membar_release_lock() %{ 6731 match(MemBarReleaseLock); 6732 ins_cost(0); 6733 6734 size(0); 6735 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6736 ins_encode( ); 6737 ins_pipe(empty); 6738 %} 6739 6740 instruct membar_volatile() %{ 6741 match(MemBarVolatile); 6742 ins_cost(4*MEMORY_REF_COST); 6743 6744 size(4); 6745 format %{ "MEMBAR-volatile" %} 6746 ins_encode( enc_membar_volatile ); 6747 ins_pipe(long_memory_op); 6748 %} 6749 6750 instruct unnecessary_membar_volatile() %{ 6751 match(MemBarVolatile); 6752 predicate(Matcher::post_store_load_barrier(n)); 6753 ins_cost(0); 6754 6755 size(0); 6756 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6757 ins_encode( ); 6758 ins_pipe(empty); 6759 %} 6760 6761 instruct membar_storestore() %{ 6762 match(MemBarStoreStore); 6763 ins_cost(0); 6764 6765 size(0); 6766 format %{ "!MEMBAR-storestore (empty encoding)" %} 6767 ins_encode( ); 6768 ins_pipe(empty); 6769 %} 6770 6771 //----------Register Move Instructions----------------------------------------- 6772 instruct roundDouble_nop(regD dst) %{ 6773 match(Set dst (RoundDouble dst)); 6774 ins_cost(0); 6775 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6776 ins_encode( ); 6777 ins_pipe(empty); 6778 %} 6779 6780 6781 instruct roundFloat_nop(regF dst) %{ 6782 match(Set dst (RoundFloat dst)); 6783 ins_cost(0); 6784 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6785 ins_encode( ); 6786 ins_pipe(empty); 6787 %} 6788 6789 6790 // Cast Index to Pointer for unsafe natives 6791 instruct castX2P(iRegX src, iRegP dst) %{ 6792 match(Set dst (CastX2P src)); 6793 6794 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6795 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6796 ins_pipe(ialu_reg); 6797 %} 6798 6799 // Cast Pointer to Index for unsafe natives 6800 instruct castP2X(iRegP src, iRegX dst) %{ 6801 match(Set dst (CastP2X src)); 6802 6803 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6804 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6805 ins_pipe(ialu_reg); 6806 %} 6807 6808 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6809 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6810 match(Set stkSlot src); // chain rule 6811 ins_cost(MEMORY_REF_COST); 6812 format %{ "STDF $src,$stkSlot\t!stk" %} 6813 opcode(Assembler::stdf_op3); 6814 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6815 ins_pipe(fstoreD_stk_reg); 6816 %} 6817 6818 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6819 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6820 match(Set dst stkSlot); // chain rule 6821 ins_cost(MEMORY_REF_COST); 6822 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6823 opcode(Assembler::lddf_op3); 6824 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6825 ins_pipe(floadD_stk); 6826 %} 6827 6828 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6829 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6830 match(Set stkSlot src); // chain rule 6831 ins_cost(MEMORY_REF_COST); 6832 format %{ "STF $src,$stkSlot\t!stk" %} 6833 opcode(Assembler::stf_op3); 6834 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6835 ins_pipe(fstoreF_stk_reg); 6836 %} 6837 6838 //----------Conditional Move--------------------------------------------------- 6839 // Conditional move 6840 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6841 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6842 ins_cost(150); 6843 format %{ "MOV$cmp $pcc,$src,$dst" %} 6844 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6845 ins_pipe(ialu_reg); 6846 %} 6847 6848 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6849 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6850 ins_cost(140); 6851 format %{ "MOV$cmp $pcc,$src,$dst" %} 6852 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6853 ins_pipe(ialu_imm); 6854 %} 6855 6856 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6857 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6858 ins_cost(150); 6859 size(4); 6860 format %{ "MOV$cmp $icc,$src,$dst" %} 6861 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6862 ins_pipe(ialu_reg); 6863 %} 6864 6865 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6866 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6867 ins_cost(140); 6868 size(4); 6869 format %{ "MOV$cmp $icc,$src,$dst" %} 6870 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6871 ins_pipe(ialu_imm); 6872 %} 6873 6874 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6875 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6876 ins_cost(150); 6877 size(4); 6878 format %{ "MOV$cmp $icc,$src,$dst" %} 6879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6880 ins_pipe(ialu_reg); 6881 %} 6882 6883 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6884 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6885 ins_cost(140); 6886 size(4); 6887 format %{ "MOV$cmp $icc,$src,$dst" %} 6888 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6889 ins_pipe(ialu_imm); 6890 %} 6891 6892 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6893 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6894 ins_cost(150); 6895 size(4); 6896 format %{ "MOV$cmp $fcc,$src,$dst" %} 6897 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6898 ins_pipe(ialu_reg); 6899 %} 6900 6901 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6902 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6903 ins_cost(140); 6904 size(4); 6905 format %{ "MOV$cmp $fcc,$src,$dst" %} 6906 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6907 ins_pipe(ialu_imm); 6908 %} 6909 6910 // Conditional move for RegN. Only cmov(reg,reg). 6911 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6912 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6913 ins_cost(150); 6914 format %{ "MOV$cmp $pcc,$src,$dst" %} 6915 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6916 ins_pipe(ialu_reg); 6917 %} 6918 6919 // This instruction also works with CmpN so we don't need cmovNN_reg. 6920 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6921 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6922 ins_cost(150); 6923 size(4); 6924 format %{ "MOV$cmp $icc,$src,$dst" %} 6925 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6926 ins_pipe(ialu_reg); 6927 %} 6928 6929 // This instruction also works with CmpN so we don't need cmovNN_reg. 6930 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6931 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6932 ins_cost(150); 6933 size(4); 6934 format %{ "MOV$cmp $icc,$src,$dst" %} 6935 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6936 ins_pipe(ialu_reg); 6937 %} 6938 6939 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6940 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6941 ins_cost(150); 6942 size(4); 6943 format %{ "MOV$cmp $fcc,$src,$dst" %} 6944 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6945 ins_pipe(ialu_reg); 6946 %} 6947 6948 // Conditional move 6949 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6950 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6951 ins_cost(150); 6952 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6953 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6954 ins_pipe(ialu_reg); 6955 %} 6956 6957 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6958 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6959 ins_cost(140); 6960 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6961 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6962 ins_pipe(ialu_imm); 6963 %} 6964 6965 // This instruction also works with CmpN so we don't need cmovPN_reg. 6966 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6967 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6968 ins_cost(150); 6969 6970 size(4); 6971 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6972 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6973 ins_pipe(ialu_reg); 6974 %} 6975 6976 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6977 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6978 ins_cost(150); 6979 6980 size(4); 6981 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6982 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6983 ins_pipe(ialu_reg); 6984 %} 6985 6986 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6987 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6988 ins_cost(140); 6989 6990 size(4); 6991 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6992 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6993 ins_pipe(ialu_imm); 6994 %} 6995 6996 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6997 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6998 ins_cost(140); 6999 7000 size(4); 7001 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 7002 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 7003 ins_pipe(ialu_imm); 7004 %} 7005 7006 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 7007 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 7008 ins_cost(150); 7009 size(4); 7010 format %{ "MOV$cmp $fcc,$src,$dst" %} 7011 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7012 ins_pipe(ialu_imm); 7013 %} 7014 7015 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 7016 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 7017 ins_cost(140); 7018 size(4); 7019 format %{ "MOV$cmp $fcc,$src,$dst" %} 7020 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 7021 ins_pipe(ialu_imm); 7022 %} 7023 7024 // Conditional move 7025 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 7026 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 7027 ins_cost(150); 7028 opcode(0x101); 7029 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 7030 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7031 ins_pipe(int_conditional_float_move); 7032 %} 7033 7034 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 7035 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 7036 ins_cost(150); 7037 7038 size(4); 7039 format %{ "FMOVS$cmp $icc,$src,$dst" %} 7040 opcode(0x101); 7041 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7042 ins_pipe(int_conditional_float_move); 7043 %} 7044 7045 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 7046 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 7047 ins_cost(150); 7048 7049 size(4); 7050 format %{ "FMOVS$cmp $icc,$src,$dst" %} 7051 opcode(0x101); 7052 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7053 ins_pipe(int_conditional_float_move); 7054 %} 7055 7056 // Conditional move, 7057 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 7058 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 7059 ins_cost(150); 7060 size(4); 7061 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 7062 opcode(0x1); 7063 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7064 ins_pipe(int_conditional_double_move); 7065 %} 7066 7067 // Conditional move 7068 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 7069 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 7070 ins_cost(150); 7071 size(4); 7072 opcode(0x102); 7073 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 7074 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7075 ins_pipe(int_conditional_double_move); 7076 %} 7077 7078 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 7079 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7080 ins_cost(150); 7081 7082 size(4); 7083 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7084 opcode(0x102); 7085 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7086 ins_pipe(int_conditional_double_move); 7087 %} 7088 7089 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 7090 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7091 ins_cost(150); 7092 7093 size(4); 7094 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7095 opcode(0x102); 7096 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7097 ins_pipe(int_conditional_double_move); 7098 %} 7099 7100 // Conditional move, 7101 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 7102 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 7103 ins_cost(150); 7104 size(4); 7105 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 7106 opcode(0x2); 7107 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7108 ins_pipe(int_conditional_double_move); 7109 %} 7110 7111 // Conditional move 7112 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 7113 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7114 ins_cost(150); 7115 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7116 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7117 ins_pipe(ialu_reg); 7118 %} 7119 7120 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 7121 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7122 ins_cost(140); 7123 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7124 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 7125 ins_pipe(ialu_imm); 7126 %} 7127 7128 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 7129 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7130 ins_cost(150); 7131 7132 size(4); 7133 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7134 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7135 ins_pipe(ialu_reg); 7136 %} 7137 7138 7139 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 7140 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7141 ins_cost(150); 7142 7143 size(4); 7144 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7145 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7146 ins_pipe(ialu_reg); 7147 %} 7148 7149 7150 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 7151 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 7152 ins_cost(150); 7153 7154 size(4); 7155 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 7156 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7157 ins_pipe(ialu_reg); 7158 %} 7159 7160 7161 7162 //----------OS and Locking Instructions---------------------------------------- 7163 7164 // This name is KNOWN by the ADLC and cannot be changed. 7165 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 7166 // for this guy. 7167 instruct tlsLoadP(g2RegP dst) %{ 7168 match(Set dst (ThreadLocal)); 7169 7170 size(0); 7171 ins_cost(0); 7172 format %{ "# TLS is in G2" %} 7173 ins_encode( /*empty encoding*/ ); 7174 ins_pipe(ialu_none); 7175 %} 7176 7177 instruct checkCastPP( iRegP dst ) %{ 7178 match(Set dst (CheckCastPP dst)); 7179 7180 size(0); 7181 format %{ "# checkcastPP of $dst" %} 7182 ins_encode( /*empty encoding*/ ); 7183 ins_pipe(empty); 7184 %} 7185 7186 7187 instruct castPP( iRegP dst ) %{ 7188 match(Set dst (CastPP dst)); 7189 format %{ "# castPP of $dst" %} 7190 ins_encode( /*empty encoding*/ ); 7191 ins_pipe(empty); 7192 %} 7193 7194 instruct castII( iRegI dst ) %{ 7195 match(Set dst (CastII dst)); 7196 format %{ "# castII of $dst" %} 7197 ins_encode( /*empty encoding*/ ); 7198 ins_cost(0); 7199 ins_pipe(empty); 7200 %} 7201 7202 //----------Arithmetic Instructions-------------------------------------------- 7203 // Addition Instructions 7204 // Register Addition 7205 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7206 match(Set dst (AddI src1 src2)); 7207 7208 size(4); 7209 format %{ "ADD $src1,$src2,$dst" %} 7210 ins_encode %{ 7211 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7212 %} 7213 ins_pipe(ialu_reg_reg); 7214 %} 7215 7216 // Immediate Addition 7217 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7218 match(Set dst (AddI src1 src2)); 7219 7220 size(4); 7221 format %{ "ADD $src1,$src2,$dst" %} 7222 opcode(Assembler::add_op3, Assembler::arith_op); 7223 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7224 ins_pipe(ialu_reg_imm); 7225 %} 7226 7227 // Pointer Register Addition 7228 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7229 match(Set dst (AddP src1 src2)); 7230 7231 size(4); 7232 format %{ "ADD $src1,$src2,$dst" %} 7233 opcode(Assembler::add_op3, Assembler::arith_op); 7234 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7235 ins_pipe(ialu_reg_reg); 7236 %} 7237 7238 // Pointer Immediate Addition 7239 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7240 match(Set dst (AddP src1 src2)); 7241 7242 size(4); 7243 format %{ "ADD $src1,$src2,$dst" %} 7244 opcode(Assembler::add_op3, Assembler::arith_op); 7245 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7246 ins_pipe(ialu_reg_imm); 7247 %} 7248 7249 // Long Addition 7250 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7251 match(Set dst (AddL src1 src2)); 7252 7253 size(4); 7254 format %{ "ADD $src1,$src2,$dst\t! long" %} 7255 opcode(Assembler::add_op3, Assembler::arith_op); 7256 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7257 ins_pipe(ialu_reg_reg); 7258 %} 7259 7260 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7261 match(Set dst (AddL src1 con)); 7262 7263 size(4); 7264 format %{ "ADD $src1,$con,$dst" %} 7265 opcode(Assembler::add_op3, Assembler::arith_op); 7266 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7267 ins_pipe(ialu_reg_imm); 7268 %} 7269 7270 //----------Conditional_store-------------------------------------------------- 7271 // Conditional-store of the updated heap-top. 7272 // Used during allocation of the shared heap. 7273 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7274 7275 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7276 instruct loadPLocked(iRegP dst, memory mem) %{ 7277 match(Set dst (LoadPLocked mem)); 7278 ins_cost(MEMORY_REF_COST); 7279 7280 #ifndef _LP64 7281 size(4); 7282 format %{ "LDUW $mem,$dst\t! ptr" %} 7283 opcode(Assembler::lduw_op3, 0, REGP_OP); 7284 #else 7285 format %{ "LDX $mem,$dst\t! ptr" %} 7286 opcode(Assembler::ldx_op3, 0, REGP_OP); 7287 #endif 7288 ins_encode( form3_mem_reg( mem, dst ) ); 7289 ins_pipe(iload_mem); 7290 %} 7291 7292 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7293 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7294 effect( KILL newval ); 7295 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7296 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7297 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7298 ins_pipe( long_memory_op ); 7299 %} 7300 7301 // Conditional-store of an int value. 7302 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7303 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7304 effect( KILL newval ); 7305 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7306 "CMP $oldval,$newval\t\t! See if we made progress" %} 7307 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7308 ins_pipe( long_memory_op ); 7309 %} 7310 7311 // Conditional-store of a long value. 7312 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7313 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7314 effect( KILL newval ); 7315 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7316 "CMP $oldval,$newval\t\t! See if we made progress" %} 7317 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7318 ins_pipe( long_memory_op ); 7319 %} 7320 7321 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7322 7323 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7324 predicate(VM_Version::supports_cx8()); 7325 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7326 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7327 format %{ 7328 "MOV $newval,O7\n\t" 7329 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7330 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7331 "MOV 1,$res\n\t" 7332 "MOVne xcc,R_G0,$res" 7333 %} 7334 ins_encode( enc_casx(mem_ptr, oldval, newval), 7335 enc_lflags_ne_to_boolean(res) ); 7336 ins_pipe( long_memory_op ); 7337 %} 7338 7339 7340 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7341 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7342 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7343 format %{ 7344 "MOV $newval,O7\n\t" 7345 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7346 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7347 "MOV 1,$res\n\t" 7348 "MOVne icc,R_G0,$res" 7349 %} 7350 ins_encode( enc_casi(mem_ptr, oldval, newval), 7351 enc_iflags_ne_to_boolean(res) ); 7352 ins_pipe( long_memory_op ); 7353 %} 7354 7355 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7356 #ifdef _LP64 7357 predicate(VM_Version::supports_cx8()); 7358 #endif 7359 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7360 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7361 format %{ 7362 "MOV $newval,O7\n\t" 7363 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7364 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7365 "MOV 1,$res\n\t" 7366 "MOVne xcc,R_G0,$res" 7367 %} 7368 #ifdef _LP64 7369 ins_encode( enc_casx(mem_ptr, oldval, newval), 7370 enc_lflags_ne_to_boolean(res) ); 7371 #else 7372 ins_encode( enc_casi(mem_ptr, oldval, newval), 7373 enc_iflags_ne_to_boolean(res) ); 7374 #endif 7375 ins_pipe( long_memory_op ); 7376 %} 7377 7378 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7379 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7380 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7381 format %{ 7382 "MOV $newval,O7\n\t" 7383 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7384 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7385 "MOV 1,$res\n\t" 7386 "MOVne icc,R_G0,$res" 7387 %} 7388 ins_encode( enc_casi(mem_ptr, oldval, newval), 7389 enc_iflags_ne_to_boolean(res) ); 7390 ins_pipe( long_memory_op ); 7391 %} 7392 7393 instruct xchgI( memory mem, iRegI newval) %{ 7394 match(Set newval (GetAndSetI mem newval)); 7395 format %{ "SWAP [$mem],$newval" %} 7396 size(4); 7397 ins_encode %{ 7398 __ swap($mem$$Address, $newval$$Register); 7399 %} 7400 ins_pipe( long_memory_op ); 7401 %} 7402 7403 #ifndef _LP64 7404 instruct xchgP( memory mem, iRegP newval) %{ 7405 match(Set newval (GetAndSetP mem newval)); 7406 format %{ "SWAP [$mem],$newval" %} 7407 size(4); 7408 ins_encode %{ 7409 __ swap($mem$$Address, $newval$$Register); 7410 %} 7411 ins_pipe( long_memory_op ); 7412 %} 7413 #endif 7414 7415 instruct xchgN( memory mem, iRegN newval) %{ 7416 match(Set newval (GetAndSetN mem newval)); 7417 format %{ "SWAP [$mem],$newval" %} 7418 size(4); 7419 ins_encode %{ 7420 __ swap($mem$$Address, $newval$$Register); 7421 %} 7422 ins_pipe( long_memory_op ); 7423 %} 7424 7425 //--------------------- 7426 // Subtraction Instructions 7427 // Register Subtraction 7428 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7429 match(Set dst (SubI src1 src2)); 7430 7431 size(4); 7432 format %{ "SUB $src1,$src2,$dst" %} 7433 opcode(Assembler::sub_op3, Assembler::arith_op); 7434 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7435 ins_pipe(ialu_reg_reg); 7436 %} 7437 7438 // Immediate Subtraction 7439 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7440 match(Set dst (SubI src1 src2)); 7441 7442 size(4); 7443 format %{ "SUB $src1,$src2,$dst" %} 7444 opcode(Assembler::sub_op3, Assembler::arith_op); 7445 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7446 ins_pipe(ialu_reg_imm); 7447 %} 7448 7449 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7450 match(Set dst (SubI zero src2)); 7451 7452 size(4); 7453 format %{ "NEG $src2,$dst" %} 7454 opcode(Assembler::sub_op3, Assembler::arith_op); 7455 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7456 ins_pipe(ialu_zero_reg); 7457 %} 7458 7459 // Long subtraction 7460 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7461 match(Set dst (SubL src1 src2)); 7462 7463 size(4); 7464 format %{ "SUB $src1,$src2,$dst\t! long" %} 7465 opcode(Assembler::sub_op3, Assembler::arith_op); 7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7467 ins_pipe(ialu_reg_reg); 7468 %} 7469 7470 // Immediate Subtraction 7471 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7472 match(Set dst (SubL src1 con)); 7473 7474 size(4); 7475 format %{ "SUB $src1,$con,$dst\t! long" %} 7476 opcode(Assembler::sub_op3, Assembler::arith_op); 7477 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7478 ins_pipe(ialu_reg_imm); 7479 %} 7480 7481 // Long negation 7482 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7483 match(Set dst (SubL zero src2)); 7484 7485 size(4); 7486 format %{ "NEG $src2,$dst\t! long" %} 7487 opcode(Assembler::sub_op3, Assembler::arith_op); 7488 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7489 ins_pipe(ialu_zero_reg); 7490 %} 7491 7492 // Multiplication Instructions 7493 // Integer Multiplication 7494 // Register Multiplication 7495 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7496 match(Set dst (MulI src1 src2)); 7497 7498 size(4); 7499 format %{ "MULX $src1,$src2,$dst" %} 7500 opcode(Assembler::mulx_op3, Assembler::arith_op); 7501 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7502 ins_pipe(imul_reg_reg); 7503 %} 7504 7505 // Immediate Multiplication 7506 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7507 match(Set dst (MulI src1 src2)); 7508 7509 size(4); 7510 format %{ "MULX $src1,$src2,$dst" %} 7511 opcode(Assembler::mulx_op3, Assembler::arith_op); 7512 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7513 ins_pipe(imul_reg_imm); 7514 %} 7515 7516 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7517 match(Set dst (MulL src1 src2)); 7518 ins_cost(DEFAULT_COST * 5); 7519 size(4); 7520 format %{ "MULX $src1,$src2,$dst\t! long" %} 7521 opcode(Assembler::mulx_op3, Assembler::arith_op); 7522 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7523 ins_pipe(mulL_reg_reg); 7524 %} 7525 7526 // Immediate Multiplication 7527 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7528 match(Set dst (MulL src1 src2)); 7529 ins_cost(DEFAULT_COST * 5); 7530 size(4); 7531 format %{ "MULX $src1,$src2,$dst" %} 7532 opcode(Assembler::mulx_op3, Assembler::arith_op); 7533 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7534 ins_pipe(mulL_reg_imm); 7535 %} 7536 7537 // Integer Division 7538 // Register Division 7539 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7540 match(Set dst (DivI src1 src2)); 7541 ins_cost((2+71)*DEFAULT_COST); 7542 7543 format %{ "SRA $src2,0,$src2\n\t" 7544 "SRA $src1,0,$src1\n\t" 7545 "SDIVX $src1,$src2,$dst" %} 7546 ins_encode( idiv_reg( src1, src2, dst ) ); 7547 ins_pipe(sdiv_reg_reg); 7548 %} 7549 7550 // Immediate Division 7551 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7552 match(Set dst (DivI src1 src2)); 7553 ins_cost((2+71)*DEFAULT_COST); 7554 7555 format %{ "SRA $src1,0,$src1\n\t" 7556 "SDIVX $src1,$src2,$dst" %} 7557 ins_encode( idiv_imm( src1, src2, dst ) ); 7558 ins_pipe(sdiv_reg_imm); 7559 %} 7560 7561 //----------Div-By-10-Expansion------------------------------------------------ 7562 // Extract hi bits of a 32x32->64 bit multiply. 7563 // Expand rule only, not matched 7564 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7565 effect( DEF dst, USE src1, USE src2 ); 7566 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7567 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7568 ins_encode( enc_mul_hi(dst,src1,src2)); 7569 ins_pipe(sdiv_reg_reg); 7570 %} 7571 7572 // Magic constant, reciprocal of 10 7573 instruct loadConI_x66666667(iRegIsafe dst) %{ 7574 effect( DEF dst ); 7575 7576 size(8); 7577 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7578 ins_encode( Set32(0x66666667, dst) ); 7579 ins_pipe(ialu_hi_lo_reg); 7580 %} 7581 7582 // Register Shift Right Arithmetic Long by 32-63 7583 instruct sra_31( iRegI dst, iRegI src ) %{ 7584 effect( DEF dst, USE src ); 7585 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7586 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7587 ins_pipe(ialu_reg_reg); 7588 %} 7589 7590 // Arithmetic Shift Right by 8-bit immediate 7591 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7592 effect( DEF dst, USE src ); 7593 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7594 opcode(Assembler::sra_op3, Assembler::arith_op); 7595 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7596 ins_pipe(ialu_reg_imm); 7597 %} 7598 7599 // Integer DIV with 10 7600 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7601 match(Set dst (DivI src div)); 7602 ins_cost((6+6)*DEFAULT_COST); 7603 expand %{ 7604 iRegIsafe tmp1; // Killed temps; 7605 iRegIsafe tmp2; // Killed temps; 7606 iRegI tmp3; // Killed temps; 7607 iRegI tmp4; // Killed temps; 7608 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7609 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7610 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7611 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7612 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7613 %} 7614 %} 7615 7616 // Register Long Division 7617 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7618 match(Set dst (DivL src1 src2)); 7619 ins_cost(DEFAULT_COST*71); 7620 size(4); 7621 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7622 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7623 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7624 ins_pipe(divL_reg_reg); 7625 %} 7626 7627 // Register Long Division 7628 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7629 match(Set dst (DivL src1 src2)); 7630 ins_cost(DEFAULT_COST*71); 7631 size(4); 7632 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7633 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7634 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7635 ins_pipe(divL_reg_imm); 7636 %} 7637 7638 // Integer Remainder 7639 // Register Remainder 7640 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7641 match(Set dst (ModI src1 src2)); 7642 effect( KILL ccr, KILL temp); 7643 7644 format %{ "SREM $src1,$src2,$dst" %} 7645 ins_encode( irem_reg(src1, src2, dst, temp) ); 7646 ins_pipe(sdiv_reg_reg); 7647 %} 7648 7649 // Immediate Remainder 7650 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7651 match(Set dst (ModI src1 src2)); 7652 effect( KILL ccr, KILL temp); 7653 7654 format %{ "SREM $src1,$src2,$dst" %} 7655 ins_encode( irem_imm(src1, src2, dst, temp) ); 7656 ins_pipe(sdiv_reg_imm); 7657 %} 7658 7659 // Register Long Remainder 7660 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7661 effect(DEF dst, USE src1, USE src2); 7662 size(4); 7663 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7664 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7665 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7666 ins_pipe(divL_reg_reg); 7667 %} 7668 7669 // Register Long Division 7670 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7671 effect(DEF dst, USE src1, USE src2); 7672 size(4); 7673 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7674 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7675 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7676 ins_pipe(divL_reg_imm); 7677 %} 7678 7679 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7680 effect(DEF dst, USE src1, USE src2); 7681 size(4); 7682 format %{ "MULX $src1,$src2,$dst\t! long" %} 7683 opcode(Assembler::mulx_op3, Assembler::arith_op); 7684 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7685 ins_pipe(mulL_reg_reg); 7686 %} 7687 7688 // Immediate Multiplication 7689 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7690 effect(DEF dst, USE src1, USE src2); 7691 size(4); 7692 format %{ "MULX $src1,$src2,$dst" %} 7693 opcode(Assembler::mulx_op3, Assembler::arith_op); 7694 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7695 ins_pipe(mulL_reg_imm); 7696 %} 7697 7698 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7699 effect(DEF dst, USE src1, USE src2); 7700 size(4); 7701 format %{ "SUB $src1,$src2,$dst\t! long" %} 7702 opcode(Assembler::sub_op3, Assembler::arith_op); 7703 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7704 ins_pipe(ialu_reg_reg); 7705 %} 7706 7707 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7708 effect(DEF dst, USE src1, USE src2); 7709 size(4); 7710 format %{ "SUB $src1,$src2,$dst\t! long" %} 7711 opcode(Assembler::sub_op3, Assembler::arith_op); 7712 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7713 ins_pipe(ialu_reg_reg); 7714 %} 7715 7716 // Register Long Remainder 7717 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7718 match(Set dst (ModL src1 src2)); 7719 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7720 expand %{ 7721 iRegL tmp1; 7722 iRegL tmp2; 7723 divL_reg_reg_1(tmp1, src1, src2); 7724 mulL_reg_reg_1(tmp2, tmp1, src2); 7725 subL_reg_reg_1(dst, src1, tmp2); 7726 %} 7727 %} 7728 7729 // Register Long Remainder 7730 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7731 match(Set dst (ModL src1 src2)); 7732 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7733 expand %{ 7734 iRegL tmp1; 7735 iRegL tmp2; 7736 divL_reg_imm13_1(tmp1, src1, src2); 7737 mulL_reg_imm13_1(tmp2, tmp1, src2); 7738 subL_reg_reg_2 (dst, src1, tmp2); 7739 %} 7740 %} 7741 7742 // Integer Shift Instructions 7743 // Register Shift Left 7744 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7745 match(Set dst (LShiftI src1 src2)); 7746 7747 size(4); 7748 format %{ "SLL $src1,$src2,$dst" %} 7749 opcode(Assembler::sll_op3, Assembler::arith_op); 7750 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7751 ins_pipe(ialu_reg_reg); 7752 %} 7753 7754 // Register Shift Left Immediate 7755 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7756 match(Set dst (LShiftI src1 src2)); 7757 7758 size(4); 7759 format %{ "SLL $src1,$src2,$dst" %} 7760 opcode(Assembler::sll_op3, Assembler::arith_op); 7761 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7762 ins_pipe(ialu_reg_imm); 7763 %} 7764 7765 // Register Shift Left 7766 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7767 match(Set dst (LShiftL src1 src2)); 7768 7769 size(4); 7770 format %{ "SLLX $src1,$src2,$dst" %} 7771 opcode(Assembler::sllx_op3, Assembler::arith_op); 7772 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7773 ins_pipe(ialu_reg_reg); 7774 %} 7775 7776 // Register Shift Left Immediate 7777 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7778 match(Set dst (LShiftL src1 src2)); 7779 7780 size(4); 7781 format %{ "SLLX $src1,$src2,$dst" %} 7782 opcode(Assembler::sllx_op3, Assembler::arith_op); 7783 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7784 ins_pipe(ialu_reg_imm); 7785 %} 7786 7787 // Register Arithmetic Shift Right 7788 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7789 match(Set dst (RShiftI src1 src2)); 7790 size(4); 7791 format %{ "SRA $src1,$src2,$dst" %} 7792 opcode(Assembler::sra_op3, Assembler::arith_op); 7793 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7794 ins_pipe(ialu_reg_reg); 7795 %} 7796 7797 // Register Arithmetic Shift Right Immediate 7798 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7799 match(Set dst (RShiftI src1 src2)); 7800 7801 size(4); 7802 format %{ "SRA $src1,$src2,$dst" %} 7803 opcode(Assembler::sra_op3, Assembler::arith_op); 7804 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7805 ins_pipe(ialu_reg_imm); 7806 %} 7807 7808 // Register Shift Right Arithmatic Long 7809 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7810 match(Set dst (RShiftL src1 src2)); 7811 7812 size(4); 7813 format %{ "SRAX $src1,$src2,$dst" %} 7814 opcode(Assembler::srax_op3, Assembler::arith_op); 7815 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7816 ins_pipe(ialu_reg_reg); 7817 %} 7818 7819 // Register Shift Left Immediate 7820 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7821 match(Set dst (RShiftL src1 src2)); 7822 7823 size(4); 7824 format %{ "SRAX $src1,$src2,$dst" %} 7825 opcode(Assembler::srax_op3, Assembler::arith_op); 7826 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7827 ins_pipe(ialu_reg_imm); 7828 %} 7829 7830 // Register Shift Right 7831 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7832 match(Set dst (URShiftI src1 src2)); 7833 7834 size(4); 7835 format %{ "SRL $src1,$src2,$dst" %} 7836 opcode(Assembler::srl_op3, Assembler::arith_op); 7837 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7838 ins_pipe(ialu_reg_reg); 7839 %} 7840 7841 // Register Shift Right Immediate 7842 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7843 match(Set dst (URShiftI src1 src2)); 7844 7845 size(4); 7846 format %{ "SRL $src1,$src2,$dst" %} 7847 opcode(Assembler::srl_op3, Assembler::arith_op); 7848 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7849 ins_pipe(ialu_reg_imm); 7850 %} 7851 7852 // Register Shift Right 7853 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7854 match(Set dst (URShiftL src1 src2)); 7855 7856 size(4); 7857 format %{ "SRLX $src1,$src2,$dst" %} 7858 opcode(Assembler::srlx_op3, Assembler::arith_op); 7859 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7860 ins_pipe(ialu_reg_reg); 7861 %} 7862 7863 // Register Shift Right Immediate 7864 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7865 match(Set dst (URShiftL src1 src2)); 7866 7867 size(4); 7868 format %{ "SRLX $src1,$src2,$dst" %} 7869 opcode(Assembler::srlx_op3, Assembler::arith_op); 7870 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7871 ins_pipe(ialu_reg_imm); 7872 %} 7873 7874 // Register Shift Right Immediate with a CastP2X 7875 #ifdef _LP64 7876 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7877 match(Set dst (URShiftL (CastP2X src1) src2)); 7878 size(4); 7879 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7880 opcode(Assembler::srlx_op3, Assembler::arith_op); 7881 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7882 ins_pipe(ialu_reg_imm); 7883 %} 7884 #else 7885 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7886 match(Set dst (URShiftI (CastP2X src1) src2)); 7887 size(4); 7888 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7889 opcode(Assembler::srl_op3, Assembler::arith_op); 7890 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7891 ins_pipe(ialu_reg_imm); 7892 %} 7893 #endif 7894 7895 7896 //----------Floating Point Arithmetic Instructions----------------------------- 7897 7898 // Add float single precision 7899 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7900 match(Set dst (AddF src1 src2)); 7901 7902 size(4); 7903 format %{ "FADDS $src1,$src2,$dst" %} 7904 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7905 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7906 ins_pipe(faddF_reg_reg); 7907 %} 7908 7909 // Add float double precision 7910 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7911 match(Set dst (AddD src1 src2)); 7912 7913 size(4); 7914 format %{ "FADDD $src1,$src2,$dst" %} 7915 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7916 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7917 ins_pipe(faddD_reg_reg); 7918 %} 7919 7920 // Sub float single precision 7921 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7922 match(Set dst (SubF src1 src2)); 7923 7924 size(4); 7925 format %{ "FSUBS $src1,$src2,$dst" %} 7926 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7927 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7928 ins_pipe(faddF_reg_reg); 7929 %} 7930 7931 // Sub float double precision 7932 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7933 match(Set dst (SubD src1 src2)); 7934 7935 size(4); 7936 format %{ "FSUBD $src1,$src2,$dst" %} 7937 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7938 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7939 ins_pipe(faddD_reg_reg); 7940 %} 7941 7942 // Mul float single precision 7943 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7944 match(Set dst (MulF src1 src2)); 7945 7946 size(4); 7947 format %{ "FMULS $src1,$src2,$dst" %} 7948 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7949 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7950 ins_pipe(fmulF_reg_reg); 7951 %} 7952 7953 // Mul float double precision 7954 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7955 match(Set dst (MulD src1 src2)); 7956 7957 size(4); 7958 format %{ "FMULD $src1,$src2,$dst" %} 7959 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7960 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7961 ins_pipe(fmulD_reg_reg); 7962 %} 7963 7964 // Div float single precision 7965 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7966 match(Set dst (DivF src1 src2)); 7967 7968 size(4); 7969 format %{ "FDIVS $src1,$src2,$dst" %} 7970 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7971 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7972 ins_pipe(fdivF_reg_reg); 7973 %} 7974 7975 // Div float double precision 7976 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7977 match(Set dst (DivD src1 src2)); 7978 7979 size(4); 7980 format %{ "FDIVD $src1,$src2,$dst" %} 7981 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7982 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7983 ins_pipe(fdivD_reg_reg); 7984 %} 7985 7986 // Absolute float double precision 7987 instruct absD_reg(regD dst, regD src) %{ 7988 match(Set dst (AbsD src)); 7989 7990 format %{ "FABSd $src,$dst" %} 7991 ins_encode(fabsd(dst, src)); 7992 ins_pipe(faddD_reg); 7993 %} 7994 7995 // Absolute float single precision 7996 instruct absF_reg(regF dst, regF src) %{ 7997 match(Set dst (AbsF src)); 7998 7999 format %{ "FABSs $src,$dst" %} 8000 ins_encode(fabss(dst, src)); 8001 ins_pipe(faddF_reg); 8002 %} 8003 8004 instruct negF_reg(regF dst, regF src) %{ 8005 match(Set dst (NegF src)); 8006 8007 size(4); 8008 format %{ "FNEGs $src,$dst" %} 8009 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 8010 ins_encode(form3_opf_rs2F_rdF(src, dst)); 8011 ins_pipe(faddF_reg); 8012 %} 8013 8014 instruct negD_reg(regD dst, regD src) %{ 8015 match(Set dst (NegD src)); 8016 8017 format %{ "FNEGd $src,$dst" %} 8018 ins_encode(fnegd(dst, src)); 8019 ins_pipe(faddD_reg); 8020 %} 8021 8022 // Sqrt float double precision 8023 instruct sqrtF_reg_reg(regF dst, regF src) %{ 8024 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8025 8026 size(4); 8027 format %{ "FSQRTS $src,$dst" %} 8028 ins_encode(fsqrts(dst, src)); 8029 ins_pipe(fdivF_reg_reg); 8030 %} 8031 8032 // Sqrt float double precision 8033 instruct sqrtD_reg_reg(regD dst, regD src) %{ 8034 match(Set dst (SqrtD src)); 8035 8036 size(4); 8037 format %{ "FSQRTD $src,$dst" %} 8038 ins_encode(fsqrtd(dst, src)); 8039 ins_pipe(fdivD_reg_reg); 8040 %} 8041 8042 //----------Logical Instructions----------------------------------------------- 8043 // And Instructions 8044 // Register And 8045 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8046 match(Set dst (AndI src1 src2)); 8047 8048 size(4); 8049 format %{ "AND $src1,$src2,$dst" %} 8050 opcode(Assembler::and_op3, Assembler::arith_op); 8051 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8052 ins_pipe(ialu_reg_reg); 8053 %} 8054 8055 // Immediate And 8056 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8057 match(Set dst (AndI src1 src2)); 8058 8059 size(4); 8060 format %{ "AND $src1,$src2,$dst" %} 8061 opcode(Assembler::and_op3, Assembler::arith_op); 8062 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8063 ins_pipe(ialu_reg_imm); 8064 %} 8065 8066 // Register And Long 8067 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8068 match(Set dst (AndL src1 src2)); 8069 8070 ins_cost(DEFAULT_COST); 8071 size(4); 8072 format %{ "AND $src1,$src2,$dst\t! long" %} 8073 opcode(Assembler::and_op3, Assembler::arith_op); 8074 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8075 ins_pipe(ialu_reg_reg); 8076 %} 8077 8078 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8079 match(Set dst (AndL src1 con)); 8080 8081 ins_cost(DEFAULT_COST); 8082 size(4); 8083 format %{ "AND $src1,$con,$dst\t! long" %} 8084 opcode(Assembler::and_op3, Assembler::arith_op); 8085 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8086 ins_pipe(ialu_reg_imm); 8087 %} 8088 8089 // Or Instructions 8090 // Register Or 8091 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8092 match(Set dst (OrI src1 src2)); 8093 8094 size(4); 8095 format %{ "OR $src1,$src2,$dst" %} 8096 opcode(Assembler::or_op3, Assembler::arith_op); 8097 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8098 ins_pipe(ialu_reg_reg); 8099 %} 8100 8101 // Immediate Or 8102 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8103 match(Set dst (OrI src1 src2)); 8104 8105 size(4); 8106 format %{ "OR $src1,$src2,$dst" %} 8107 opcode(Assembler::or_op3, Assembler::arith_op); 8108 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8109 ins_pipe(ialu_reg_imm); 8110 %} 8111 8112 // Register Or Long 8113 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8114 match(Set dst (OrL src1 src2)); 8115 8116 ins_cost(DEFAULT_COST); 8117 size(4); 8118 format %{ "OR $src1,$src2,$dst\t! long" %} 8119 opcode(Assembler::or_op3, Assembler::arith_op); 8120 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8121 ins_pipe(ialu_reg_reg); 8122 %} 8123 8124 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8125 match(Set dst (OrL src1 con)); 8126 ins_cost(DEFAULT_COST*2); 8127 8128 ins_cost(DEFAULT_COST); 8129 size(4); 8130 format %{ "OR $src1,$con,$dst\t! long" %} 8131 opcode(Assembler::or_op3, Assembler::arith_op); 8132 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8133 ins_pipe(ialu_reg_imm); 8134 %} 8135 8136 #ifndef _LP64 8137 8138 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 8139 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 8140 match(Set dst (OrI src1 (CastP2X src2))); 8141 8142 size(4); 8143 format %{ "OR $src1,$src2,$dst" %} 8144 opcode(Assembler::or_op3, Assembler::arith_op); 8145 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8146 ins_pipe(ialu_reg_reg); 8147 %} 8148 8149 #else 8150 8151 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 8152 match(Set dst (OrL src1 (CastP2X src2))); 8153 8154 ins_cost(DEFAULT_COST); 8155 size(4); 8156 format %{ "OR $src1,$src2,$dst\t! long" %} 8157 opcode(Assembler::or_op3, Assembler::arith_op); 8158 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8159 ins_pipe(ialu_reg_reg); 8160 %} 8161 8162 #endif 8163 8164 // Xor Instructions 8165 // Register Xor 8166 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8167 match(Set dst (XorI src1 src2)); 8168 8169 size(4); 8170 format %{ "XOR $src1,$src2,$dst" %} 8171 opcode(Assembler::xor_op3, Assembler::arith_op); 8172 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8173 ins_pipe(ialu_reg_reg); 8174 %} 8175 8176 // Immediate Xor 8177 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8178 match(Set dst (XorI src1 src2)); 8179 8180 size(4); 8181 format %{ "XOR $src1,$src2,$dst" %} 8182 opcode(Assembler::xor_op3, Assembler::arith_op); 8183 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8184 ins_pipe(ialu_reg_imm); 8185 %} 8186 8187 // Register Xor Long 8188 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8189 match(Set dst (XorL src1 src2)); 8190 8191 ins_cost(DEFAULT_COST); 8192 size(4); 8193 format %{ "XOR $src1,$src2,$dst\t! long" %} 8194 opcode(Assembler::xor_op3, Assembler::arith_op); 8195 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8196 ins_pipe(ialu_reg_reg); 8197 %} 8198 8199 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8200 match(Set dst (XorL src1 con)); 8201 8202 ins_cost(DEFAULT_COST); 8203 size(4); 8204 format %{ "XOR $src1,$con,$dst\t! long" %} 8205 opcode(Assembler::xor_op3, Assembler::arith_op); 8206 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8207 ins_pipe(ialu_reg_imm); 8208 %} 8209 8210 //----------Convert to Boolean------------------------------------------------- 8211 // Nice hack for 32-bit tests but doesn't work for 8212 // 64-bit pointers. 8213 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8214 match(Set dst (Conv2B src)); 8215 effect( KILL ccr ); 8216 ins_cost(DEFAULT_COST*2); 8217 format %{ "CMP R_G0,$src\n\t" 8218 "ADDX R_G0,0,$dst" %} 8219 ins_encode( enc_to_bool( src, dst ) ); 8220 ins_pipe(ialu_reg_ialu); 8221 %} 8222 8223 #ifndef _LP64 8224 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8225 match(Set dst (Conv2B src)); 8226 effect( KILL ccr ); 8227 ins_cost(DEFAULT_COST*2); 8228 format %{ "CMP R_G0,$src\n\t" 8229 "ADDX R_G0,0,$dst" %} 8230 ins_encode( enc_to_bool( src, dst ) ); 8231 ins_pipe(ialu_reg_ialu); 8232 %} 8233 #else 8234 instruct convP2B( iRegI dst, iRegP src ) %{ 8235 match(Set dst (Conv2B src)); 8236 ins_cost(DEFAULT_COST*2); 8237 format %{ "MOV $src,$dst\n\t" 8238 "MOVRNZ $src,1,$dst" %} 8239 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8240 ins_pipe(ialu_clr_and_mover); 8241 %} 8242 #endif 8243 8244 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 8245 match(Set dst (CmpLTMask src zero)); 8246 effect(KILL ccr); 8247 size(4); 8248 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 8249 ins_encode %{ 8250 __ sra($src$$Register, 31, $dst$$Register); 8251 %} 8252 ins_pipe(ialu_reg_imm); 8253 %} 8254 8255 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8256 match(Set dst (CmpLTMask p q)); 8257 effect( KILL ccr ); 8258 ins_cost(DEFAULT_COST*4); 8259 format %{ "CMP $p,$q\n\t" 8260 "MOV #0,$dst\n\t" 8261 "BLT,a .+8\n\t" 8262 "MOV #-1,$dst" %} 8263 ins_encode( enc_ltmask(p,q,dst) ); 8264 ins_pipe(ialu_reg_reg_ialu); 8265 %} 8266 8267 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8268 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8269 effect(KILL ccr, TEMP tmp); 8270 ins_cost(DEFAULT_COST*3); 8271 8272 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8273 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8274 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8275 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 8276 ins_pipe(cadd_cmpltmask); 8277 %} 8278 8279 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 8280 match(Set p (AndI (CmpLTMask p q) y)); 8281 effect(KILL ccr); 8282 ins_cost(DEFAULT_COST*3); 8283 8284 format %{ "CMP $p,$q\n\t" 8285 "MOV $y,$p\n\t" 8286 "MOVge G0,$p" %} 8287 ins_encode %{ 8288 __ cmp($p$$Register, $q$$Register); 8289 __ mov($y$$Register, $p$$Register); 8290 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 8291 %} 8292 ins_pipe(ialu_reg_reg_ialu); 8293 %} 8294 8295 //----------------------------------------------------------------- 8296 // Direct raw moves between float and general registers using VIS3. 8297 8298 // ins_pipe(faddF_reg); 8299 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 8300 predicate(UseVIS >= 3); 8301 match(Set dst (MoveF2I src)); 8302 8303 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 8304 ins_encode %{ 8305 __ movstouw($src$$FloatRegister, $dst$$Register); 8306 %} 8307 ins_pipe(ialu_reg_reg); 8308 %} 8309 8310 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 8311 predicate(UseVIS >= 3); 8312 match(Set dst (MoveI2F src)); 8313 8314 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 8315 ins_encode %{ 8316 __ movwtos($src$$Register, $dst$$FloatRegister); 8317 %} 8318 ins_pipe(ialu_reg_reg); 8319 %} 8320 8321 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 8322 predicate(UseVIS >= 3); 8323 match(Set dst (MoveD2L src)); 8324 8325 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 8326 ins_encode %{ 8327 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 8328 %} 8329 ins_pipe(ialu_reg_reg); 8330 %} 8331 8332 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 8333 predicate(UseVIS >= 3); 8334 match(Set dst (MoveL2D src)); 8335 8336 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 8337 ins_encode %{ 8338 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 8339 %} 8340 ins_pipe(ialu_reg_reg); 8341 %} 8342 8343 8344 // Raw moves between float and general registers using stack. 8345 8346 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8347 match(Set dst (MoveF2I src)); 8348 effect(DEF dst, USE src); 8349 ins_cost(MEMORY_REF_COST); 8350 8351 size(4); 8352 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8353 opcode(Assembler::lduw_op3); 8354 ins_encode(simple_form3_mem_reg( src, dst ) ); 8355 ins_pipe(iload_mem); 8356 %} 8357 8358 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8359 match(Set dst (MoveI2F src)); 8360 effect(DEF dst, USE src); 8361 ins_cost(MEMORY_REF_COST); 8362 8363 size(4); 8364 format %{ "LDF $src,$dst\t! MoveI2F" %} 8365 opcode(Assembler::ldf_op3); 8366 ins_encode(simple_form3_mem_reg(src, dst)); 8367 ins_pipe(floadF_stk); 8368 %} 8369 8370 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8371 match(Set dst (MoveD2L src)); 8372 effect(DEF dst, USE src); 8373 ins_cost(MEMORY_REF_COST); 8374 8375 size(4); 8376 format %{ "LDX $src,$dst\t! MoveD2L" %} 8377 opcode(Assembler::ldx_op3); 8378 ins_encode(simple_form3_mem_reg( src, dst ) ); 8379 ins_pipe(iload_mem); 8380 %} 8381 8382 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8383 match(Set dst (MoveL2D src)); 8384 effect(DEF dst, USE src); 8385 ins_cost(MEMORY_REF_COST); 8386 8387 size(4); 8388 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8389 opcode(Assembler::lddf_op3); 8390 ins_encode(simple_form3_mem_reg(src, dst)); 8391 ins_pipe(floadD_stk); 8392 %} 8393 8394 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8395 match(Set dst (MoveF2I src)); 8396 effect(DEF dst, USE src); 8397 ins_cost(MEMORY_REF_COST); 8398 8399 size(4); 8400 format %{ "STF $src,$dst\t! MoveF2I" %} 8401 opcode(Assembler::stf_op3); 8402 ins_encode(simple_form3_mem_reg(dst, src)); 8403 ins_pipe(fstoreF_stk_reg); 8404 %} 8405 8406 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8407 match(Set dst (MoveI2F src)); 8408 effect(DEF dst, USE src); 8409 ins_cost(MEMORY_REF_COST); 8410 8411 size(4); 8412 format %{ "STW $src,$dst\t! MoveI2F" %} 8413 opcode(Assembler::stw_op3); 8414 ins_encode(simple_form3_mem_reg( dst, src ) ); 8415 ins_pipe(istore_mem_reg); 8416 %} 8417 8418 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8419 match(Set dst (MoveD2L src)); 8420 effect(DEF dst, USE src); 8421 ins_cost(MEMORY_REF_COST); 8422 8423 size(4); 8424 format %{ "STDF $src,$dst\t! MoveD2L" %} 8425 opcode(Assembler::stdf_op3); 8426 ins_encode(simple_form3_mem_reg(dst, src)); 8427 ins_pipe(fstoreD_stk_reg); 8428 %} 8429 8430 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8431 match(Set dst (MoveL2D src)); 8432 effect(DEF dst, USE src); 8433 ins_cost(MEMORY_REF_COST); 8434 8435 size(4); 8436 format %{ "STX $src,$dst\t! MoveL2D" %} 8437 opcode(Assembler::stx_op3); 8438 ins_encode(simple_form3_mem_reg( dst, src ) ); 8439 ins_pipe(istore_mem_reg); 8440 %} 8441 8442 8443 //----------Arithmetic Conversion Instructions--------------------------------- 8444 // The conversions operations are all Alpha sorted. Please keep it that way! 8445 8446 instruct convD2F_reg(regF dst, regD src) %{ 8447 match(Set dst (ConvD2F src)); 8448 size(4); 8449 format %{ "FDTOS $src,$dst" %} 8450 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8451 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8452 ins_pipe(fcvtD2F); 8453 %} 8454 8455 8456 // Convert a double to an int in a float register. 8457 // If the double is a NAN, stuff a zero in instead. 8458 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8459 effect(DEF dst, USE src, KILL fcc0); 8460 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8461 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8462 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8463 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8464 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8465 "skip:" %} 8466 ins_encode(form_d2i_helper(src,dst)); 8467 ins_pipe(fcvtD2I); 8468 %} 8469 8470 instruct convD2I_stk(stackSlotI dst, regD src) %{ 8471 match(Set dst (ConvD2I src)); 8472 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8473 expand %{ 8474 regF tmp; 8475 convD2I_helper(tmp, src); 8476 regF_to_stkI(dst, tmp); 8477 %} 8478 %} 8479 8480 instruct convD2I_reg(iRegI dst, regD src) %{ 8481 predicate(UseVIS >= 3); 8482 match(Set dst (ConvD2I src)); 8483 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8484 expand %{ 8485 regF tmp; 8486 convD2I_helper(tmp, src); 8487 MoveF2I_reg_reg(dst, tmp); 8488 %} 8489 %} 8490 8491 8492 // Convert a double to a long in a double register. 8493 // If the double is a NAN, stuff a zero in instead. 8494 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8495 effect(DEF dst, USE src, KILL fcc0); 8496 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8497 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8498 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8499 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8500 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8501 "skip:" %} 8502 ins_encode(form_d2l_helper(src,dst)); 8503 ins_pipe(fcvtD2L); 8504 %} 8505 8506 instruct convD2L_stk(stackSlotL dst, regD src) %{ 8507 match(Set dst (ConvD2L src)); 8508 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8509 expand %{ 8510 regD tmp; 8511 convD2L_helper(tmp, src); 8512 regD_to_stkL(dst, tmp); 8513 %} 8514 %} 8515 8516 instruct convD2L_reg(iRegL dst, regD src) %{ 8517 predicate(UseVIS >= 3); 8518 match(Set dst (ConvD2L src)); 8519 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8520 expand %{ 8521 regD tmp; 8522 convD2L_helper(tmp, src); 8523 MoveD2L_reg_reg(dst, tmp); 8524 %} 8525 %} 8526 8527 8528 instruct convF2D_reg(regD dst, regF src) %{ 8529 match(Set dst (ConvF2D src)); 8530 format %{ "FSTOD $src,$dst" %} 8531 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8532 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8533 ins_pipe(fcvtF2D); 8534 %} 8535 8536 8537 // Convert a float to an int in a float register. 8538 // If the float is a NAN, stuff a zero in instead. 8539 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8540 effect(DEF dst, USE src, KILL fcc0); 8541 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8542 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8543 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8544 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8545 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8546 "skip:" %} 8547 ins_encode(form_f2i_helper(src,dst)); 8548 ins_pipe(fcvtF2I); 8549 %} 8550 8551 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8552 match(Set dst (ConvF2I src)); 8553 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8554 expand %{ 8555 regF tmp; 8556 convF2I_helper(tmp, src); 8557 regF_to_stkI(dst, tmp); 8558 %} 8559 %} 8560 8561 instruct convF2I_reg(iRegI dst, regF src) %{ 8562 predicate(UseVIS >= 3); 8563 match(Set dst (ConvF2I src)); 8564 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8565 expand %{ 8566 regF tmp; 8567 convF2I_helper(tmp, src); 8568 MoveF2I_reg_reg(dst, tmp); 8569 %} 8570 %} 8571 8572 8573 // Convert a float to a long in a float register. 8574 // If the float is a NAN, stuff a zero in instead. 8575 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8576 effect(DEF dst, USE src, KILL fcc0); 8577 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8578 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8579 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8580 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8581 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8582 "skip:" %} 8583 ins_encode(form_f2l_helper(src,dst)); 8584 ins_pipe(fcvtF2L); 8585 %} 8586 8587 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8588 match(Set dst (ConvF2L src)); 8589 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8590 expand %{ 8591 regD tmp; 8592 convF2L_helper(tmp, src); 8593 regD_to_stkL(dst, tmp); 8594 %} 8595 %} 8596 8597 instruct convF2L_reg(iRegL dst, regF src) %{ 8598 predicate(UseVIS >= 3); 8599 match(Set dst (ConvF2L src)); 8600 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8601 expand %{ 8602 regD tmp; 8603 convF2L_helper(tmp, src); 8604 MoveD2L_reg_reg(dst, tmp); 8605 %} 8606 %} 8607 8608 8609 instruct convI2D_helper(regD dst, regF tmp) %{ 8610 effect(USE tmp, DEF dst); 8611 format %{ "FITOD $tmp,$dst" %} 8612 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8613 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8614 ins_pipe(fcvtI2D); 8615 %} 8616 8617 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8618 match(Set dst (ConvI2D src)); 8619 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8620 expand %{ 8621 regF tmp; 8622 stkI_to_regF(tmp, src); 8623 convI2D_helper(dst, tmp); 8624 %} 8625 %} 8626 8627 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8628 predicate(UseVIS >= 3); 8629 match(Set dst (ConvI2D src)); 8630 expand %{ 8631 regF tmp; 8632 MoveI2F_reg_reg(tmp, src); 8633 convI2D_helper(dst, tmp); 8634 %} 8635 %} 8636 8637 instruct convI2D_mem(regD_low dst, memory mem) %{ 8638 match(Set dst (ConvI2D (LoadI mem))); 8639 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8640 size(8); 8641 format %{ "LDF $mem,$dst\n\t" 8642 "FITOD $dst,$dst" %} 8643 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8644 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8645 ins_pipe(floadF_mem); 8646 %} 8647 8648 8649 instruct convI2F_helper(regF dst, regF tmp) %{ 8650 effect(DEF dst, USE tmp); 8651 format %{ "FITOS $tmp,$dst" %} 8652 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8653 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8654 ins_pipe(fcvtI2F); 8655 %} 8656 8657 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8658 match(Set dst (ConvI2F src)); 8659 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8660 expand %{ 8661 regF tmp; 8662 stkI_to_regF(tmp,src); 8663 convI2F_helper(dst, tmp); 8664 %} 8665 %} 8666 8667 instruct convI2F_reg(regF dst, iRegI src) %{ 8668 predicate(UseVIS >= 3); 8669 match(Set dst (ConvI2F src)); 8670 ins_cost(DEFAULT_COST); 8671 expand %{ 8672 regF tmp; 8673 MoveI2F_reg_reg(tmp, src); 8674 convI2F_helper(dst, tmp); 8675 %} 8676 %} 8677 8678 instruct convI2F_mem( regF dst, memory mem ) %{ 8679 match(Set dst (ConvI2F (LoadI mem))); 8680 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8681 size(8); 8682 format %{ "LDF $mem,$dst\n\t" 8683 "FITOS $dst,$dst" %} 8684 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8685 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8686 ins_pipe(floadF_mem); 8687 %} 8688 8689 8690 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8691 match(Set dst (ConvI2L src)); 8692 size(4); 8693 format %{ "SRA $src,0,$dst\t! int->long" %} 8694 opcode(Assembler::sra_op3, Assembler::arith_op); 8695 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8696 ins_pipe(ialu_reg_reg); 8697 %} 8698 8699 // Zero-extend convert int to long 8700 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8701 match(Set dst (AndL (ConvI2L src) mask) ); 8702 size(4); 8703 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8704 opcode(Assembler::srl_op3, Assembler::arith_op); 8705 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8706 ins_pipe(ialu_reg_reg); 8707 %} 8708 8709 // Zero-extend long 8710 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8711 match(Set dst (AndL src mask) ); 8712 size(4); 8713 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8714 opcode(Assembler::srl_op3, Assembler::arith_op); 8715 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8716 ins_pipe(ialu_reg_reg); 8717 %} 8718 8719 8720 //----------- 8721 // Long to Double conversion using V8 opcodes. 8722 // Still useful because cheetah traps and becomes 8723 // amazingly slow for some common numbers. 8724 8725 // Magic constant, 0x43300000 8726 instruct loadConI_x43300000(iRegI dst) %{ 8727 effect(DEF dst); 8728 size(4); 8729 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8730 ins_encode(SetHi22(0x43300000, dst)); 8731 ins_pipe(ialu_none); 8732 %} 8733 8734 // Magic constant, 0x41f00000 8735 instruct loadConI_x41f00000(iRegI dst) %{ 8736 effect(DEF dst); 8737 size(4); 8738 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8739 ins_encode(SetHi22(0x41f00000, dst)); 8740 ins_pipe(ialu_none); 8741 %} 8742 8743 // Construct a double from two float halves 8744 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8745 effect(DEF dst, USE src1, USE src2); 8746 size(8); 8747 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8748 "FMOVS $src2.lo,$dst.lo" %} 8749 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8750 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8751 ins_pipe(faddD_reg_reg); 8752 %} 8753 8754 // Convert integer in high half of a double register (in the lower half of 8755 // the double register file) to double 8756 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8757 effect(DEF dst, USE src); 8758 size(4); 8759 format %{ "FITOD $src,$dst" %} 8760 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8761 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8762 ins_pipe(fcvtLHi2D); 8763 %} 8764 8765 // Add float double precision 8766 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8767 effect(DEF dst, USE src1, USE src2); 8768 size(4); 8769 format %{ "FADDD $src1,$src2,$dst" %} 8770 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8771 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8772 ins_pipe(faddD_reg_reg); 8773 %} 8774 8775 // Sub float double precision 8776 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8777 effect(DEF dst, USE src1, USE src2); 8778 size(4); 8779 format %{ "FSUBD $src1,$src2,$dst" %} 8780 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8781 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8782 ins_pipe(faddD_reg_reg); 8783 %} 8784 8785 // Mul float double precision 8786 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8787 effect(DEF dst, USE src1, USE src2); 8788 size(4); 8789 format %{ "FMULD $src1,$src2,$dst" %} 8790 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8791 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8792 ins_pipe(fmulD_reg_reg); 8793 %} 8794 8795 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8796 match(Set dst (ConvL2D src)); 8797 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8798 8799 expand %{ 8800 regD_low tmpsrc; 8801 iRegI ix43300000; 8802 iRegI ix41f00000; 8803 stackSlotL lx43300000; 8804 stackSlotL lx41f00000; 8805 regD_low dx43300000; 8806 regD dx41f00000; 8807 regD tmp1; 8808 regD_low tmp2; 8809 regD tmp3; 8810 regD tmp4; 8811 8812 stkL_to_regD(tmpsrc, src); 8813 8814 loadConI_x43300000(ix43300000); 8815 loadConI_x41f00000(ix41f00000); 8816 regI_to_stkLHi(lx43300000, ix43300000); 8817 regI_to_stkLHi(lx41f00000, ix41f00000); 8818 stkL_to_regD(dx43300000, lx43300000); 8819 stkL_to_regD(dx41f00000, lx41f00000); 8820 8821 convI2D_regDHi_regD(tmp1, tmpsrc); 8822 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8823 subD_regD_regD(tmp3, tmp2, dx43300000); 8824 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8825 addD_regD_regD(dst, tmp3, tmp4); 8826 %} 8827 %} 8828 8829 // Long to Double conversion using fast fxtof 8830 instruct convL2D_helper(regD dst, regD tmp) %{ 8831 effect(DEF dst, USE tmp); 8832 size(4); 8833 format %{ "FXTOD $tmp,$dst" %} 8834 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8835 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8836 ins_pipe(fcvtL2D); 8837 %} 8838 8839 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8840 predicate(VM_Version::has_fast_fxtof()); 8841 match(Set dst (ConvL2D src)); 8842 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8843 expand %{ 8844 regD tmp; 8845 stkL_to_regD(tmp, src); 8846 convL2D_helper(dst, tmp); 8847 %} 8848 %} 8849 8850 instruct convL2D_reg(regD dst, iRegL src) %{ 8851 predicate(UseVIS >= 3); 8852 match(Set dst (ConvL2D src)); 8853 expand %{ 8854 regD tmp; 8855 MoveL2D_reg_reg(tmp, src); 8856 convL2D_helper(dst, tmp); 8857 %} 8858 %} 8859 8860 // Long to Float conversion using fast fxtof 8861 instruct convL2F_helper(regF dst, regD tmp) %{ 8862 effect(DEF dst, USE tmp); 8863 size(4); 8864 format %{ "FXTOS $tmp,$dst" %} 8865 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8866 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8867 ins_pipe(fcvtL2F); 8868 %} 8869 8870 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8871 match(Set dst (ConvL2F src)); 8872 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8873 expand %{ 8874 regD tmp; 8875 stkL_to_regD(tmp, src); 8876 convL2F_helper(dst, tmp); 8877 %} 8878 %} 8879 8880 instruct convL2F_reg(regF dst, iRegL src) %{ 8881 predicate(UseVIS >= 3); 8882 match(Set dst (ConvL2F src)); 8883 ins_cost(DEFAULT_COST); 8884 expand %{ 8885 regD tmp; 8886 MoveL2D_reg_reg(tmp, src); 8887 convL2F_helper(dst, tmp); 8888 %} 8889 %} 8890 8891 //----------- 8892 8893 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8894 match(Set dst (ConvL2I src)); 8895 #ifndef _LP64 8896 format %{ "MOV $src.lo,$dst\t! long->int" %} 8897 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8898 ins_pipe(ialu_move_reg_I_to_L); 8899 #else 8900 size(4); 8901 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8902 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8903 ins_pipe(ialu_reg); 8904 #endif 8905 %} 8906 8907 // Register Shift Right Immediate 8908 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8909 match(Set dst (ConvL2I (RShiftL src cnt))); 8910 8911 size(4); 8912 format %{ "SRAX $src,$cnt,$dst" %} 8913 opcode(Assembler::srax_op3, Assembler::arith_op); 8914 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8915 ins_pipe(ialu_reg_imm); 8916 %} 8917 8918 //----------Control Flow Instructions------------------------------------------ 8919 // Compare Instructions 8920 // Compare Integers 8921 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8922 match(Set icc (CmpI op1 op2)); 8923 effect( DEF icc, USE op1, USE op2 ); 8924 8925 size(4); 8926 format %{ "CMP $op1,$op2" %} 8927 opcode(Assembler::subcc_op3, Assembler::arith_op); 8928 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8929 ins_pipe(ialu_cconly_reg_reg); 8930 %} 8931 8932 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8933 match(Set icc (CmpU op1 op2)); 8934 8935 size(4); 8936 format %{ "CMP $op1,$op2\t! unsigned" %} 8937 opcode(Assembler::subcc_op3, Assembler::arith_op); 8938 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8939 ins_pipe(ialu_cconly_reg_reg); 8940 %} 8941 8942 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8943 match(Set icc (CmpI op1 op2)); 8944 effect( DEF icc, USE op1 ); 8945 8946 size(4); 8947 format %{ "CMP $op1,$op2" %} 8948 opcode(Assembler::subcc_op3, Assembler::arith_op); 8949 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8950 ins_pipe(ialu_cconly_reg_imm); 8951 %} 8952 8953 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8954 match(Set icc (CmpI (AndI op1 op2) zero)); 8955 8956 size(4); 8957 format %{ "BTST $op2,$op1" %} 8958 opcode(Assembler::andcc_op3, Assembler::arith_op); 8959 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8960 ins_pipe(ialu_cconly_reg_reg_zero); 8961 %} 8962 8963 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8964 match(Set icc (CmpI (AndI op1 op2) zero)); 8965 8966 size(4); 8967 format %{ "BTST $op2,$op1" %} 8968 opcode(Assembler::andcc_op3, Assembler::arith_op); 8969 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8970 ins_pipe(ialu_cconly_reg_imm_zero); 8971 %} 8972 8973 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8974 match(Set xcc (CmpL op1 op2)); 8975 effect( DEF xcc, USE op1, USE op2 ); 8976 8977 size(4); 8978 format %{ "CMP $op1,$op2\t\t! long" %} 8979 opcode(Assembler::subcc_op3, Assembler::arith_op); 8980 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8981 ins_pipe(ialu_cconly_reg_reg); 8982 %} 8983 8984 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8985 match(Set xcc (CmpL op1 con)); 8986 effect( DEF xcc, USE op1, USE con ); 8987 8988 size(4); 8989 format %{ "CMP $op1,$con\t\t! long" %} 8990 opcode(Assembler::subcc_op3, Assembler::arith_op); 8991 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8992 ins_pipe(ialu_cconly_reg_reg); 8993 %} 8994 8995 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8996 match(Set xcc (CmpL (AndL op1 op2) zero)); 8997 effect( DEF xcc, USE op1, USE op2 ); 8998 8999 size(4); 9000 format %{ "BTST $op1,$op2\t\t! long" %} 9001 opcode(Assembler::andcc_op3, Assembler::arith_op); 9002 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9003 ins_pipe(ialu_cconly_reg_reg); 9004 %} 9005 9006 // useful for checking the alignment of a pointer: 9007 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 9008 match(Set xcc (CmpL (AndL op1 con) zero)); 9009 effect( DEF xcc, USE op1, USE con ); 9010 9011 size(4); 9012 format %{ "BTST $op1,$con\t\t! long" %} 9013 opcode(Assembler::andcc_op3, Assembler::arith_op); 9014 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 9015 ins_pipe(ialu_cconly_reg_reg); 9016 %} 9017 9018 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 9019 match(Set icc (CmpU op1 op2)); 9020 9021 size(4); 9022 format %{ "CMP $op1,$op2\t! unsigned" %} 9023 opcode(Assembler::subcc_op3, Assembler::arith_op); 9024 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9025 ins_pipe(ialu_cconly_reg_imm); 9026 %} 9027 9028 // Compare Pointers 9029 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 9030 match(Set pcc (CmpP op1 op2)); 9031 9032 size(4); 9033 format %{ "CMP $op1,$op2\t! ptr" %} 9034 opcode(Assembler::subcc_op3, Assembler::arith_op); 9035 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9036 ins_pipe(ialu_cconly_reg_reg); 9037 %} 9038 9039 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 9040 match(Set pcc (CmpP op1 op2)); 9041 9042 size(4); 9043 format %{ "CMP $op1,$op2\t! ptr" %} 9044 opcode(Assembler::subcc_op3, Assembler::arith_op); 9045 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9046 ins_pipe(ialu_cconly_reg_imm); 9047 %} 9048 9049 // Compare Narrow oops 9050 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 9051 match(Set icc (CmpN op1 op2)); 9052 9053 size(4); 9054 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9055 opcode(Assembler::subcc_op3, Assembler::arith_op); 9056 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9057 ins_pipe(ialu_cconly_reg_reg); 9058 %} 9059 9060 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 9061 match(Set icc (CmpN op1 op2)); 9062 9063 size(4); 9064 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9065 opcode(Assembler::subcc_op3, Assembler::arith_op); 9066 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9067 ins_pipe(ialu_cconly_reg_imm); 9068 %} 9069 9070 //----------Max and Min-------------------------------------------------------- 9071 // Min Instructions 9072 // Conditional move for min 9073 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9074 effect( USE_DEF op2, USE op1, USE icc ); 9075 9076 size(4); 9077 format %{ "MOVlt icc,$op1,$op2\t! min" %} 9078 opcode(Assembler::less); 9079 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9080 ins_pipe(ialu_reg_flags); 9081 %} 9082 9083 // Min Register with Register. 9084 instruct minI_eReg(iRegI op1, iRegI op2) %{ 9085 match(Set op2 (MinI op1 op2)); 9086 ins_cost(DEFAULT_COST*2); 9087 expand %{ 9088 flagsReg icc; 9089 compI_iReg(icc,op1,op2); 9090 cmovI_reg_lt(op2,op1,icc); 9091 %} 9092 %} 9093 9094 // Max Instructions 9095 // Conditional move for max 9096 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9097 effect( USE_DEF op2, USE op1, USE icc ); 9098 format %{ "MOVgt icc,$op1,$op2\t! max" %} 9099 opcode(Assembler::greater); 9100 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9101 ins_pipe(ialu_reg_flags); 9102 %} 9103 9104 // Max Register with Register 9105 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 9106 match(Set op2 (MaxI op1 op2)); 9107 ins_cost(DEFAULT_COST*2); 9108 expand %{ 9109 flagsReg icc; 9110 compI_iReg(icc,op1,op2); 9111 cmovI_reg_gt(op2,op1,icc); 9112 %} 9113 %} 9114 9115 9116 //----------Float Compares---------------------------------------------------- 9117 // Compare floating, generate condition code 9118 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 9119 match(Set fcc (CmpF src1 src2)); 9120 9121 size(4); 9122 format %{ "FCMPs $fcc,$src1,$src2" %} 9123 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 9124 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 9125 ins_pipe(faddF_fcc_reg_reg_zero); 9126 %} 9127 9128 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 9129 match(Set fcc (CmpD src1 src2)); 9130 9131 size(4); 9132 format %{ "FCMPd $fcc,$src1,$src2" %} 9133 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 9134 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 9135 ins_pipe(faddD_fcc_reg_reg_zero); 9136 %} 9137 9138 9139 // Compare floating, generate -1,0,1 9140 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 9141 match(Set dst (CmpF3 src1 src2)); 9142 effect(KILL fcc0); 9143 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9144 format %{ "fcmpl $dst,$src1,$src2" %} 9145 // Primary = float 9146 opcode( true ); 9147 ins_encode( floating_cmp( dst, src1, src2 ) ); 9148 ins_pipe( floating_cmp ); 9149 %} 9150 9151 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 9152 match(Set dst (CmpD3 src1 src2)); 9153 effect(KILL fcc0); 9154 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9155 format %{ "dcmpl $dst,$src1,$src2" %} 9156 // Primary = double (not float) 9157 opcode( false ); 9158 ins_encode( floating_cmp( dst, src1, src2 ) ); 9159 ins_pipe( floating_cmp ); 9160 %} 9161 9162 //----------Branches--------------------------------------------------------- 9163 // Jump 9164 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 9165 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 9166 match(Jump switch_val); 9167 effect(TEMP table); 9168 9169 ins_cost(350); 9170 9171 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 9172 "LD [O7 + $switch_val], O7\n\t" 9173 "JUMP O7" %} 9174 ins_encode %{ 9175 // Calculate table address into a register. 9176 Register table_reg; 9177 Register label_reg = O7; 9178 // If we are calculating the size of this instruction don't trust 9179 // zero offsets because they might change when 9180 // MachConstantBaseNode decides to optimize the constant table 9181 // base. 9182 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 9183 table_reg = $constanttablebase; 9184 } else { 9185 table_reg = O7; 9186 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 9187 __ add($constanttablebase, con_offset, table_reg); 9188 } 9189 9190 // Jump to base address + switch value 9191 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 9192 __ jmp(label_reg, G0); 9193 __ delayed()->nop(); 9194 %} 9195 ins_pipe(ialu_reg_reg); 9196 %} 9197 9198 // Direct Branch. Use V8 version with longer range. 9199 instruct branch(label labl) %{ 9200 match(Goto); 9201 effect(USE labl); 9202 9203 size(8); 9204 ins_cost(BRANCH_COST); 9205 format %{ "BA $labl" %} 9206 ins_encode %{ 9207 Label* L = $labl$$label; 9208 __ ba(*L); 9209 __ delayed()->nop(); 9210 %} 9211 ins_avoid_back_to_back(AVOID_BEFORE); 9212 ins_pipe(br); 9213 %} 9214 9215 // Direct Branch, short with no delay slot 9216 instruct branch_short(label labl) %{ 9217 match(Goto); 9218 predicate(UseCBCond); 9219 effect(USE labl); 9220 9221 size(4); 9222 ins_cost(BRANCH_COST); 9223 format %{ "BA $labl\t! short branch" %} 9224 ins_encode %{ 9225 Label* L = $labl$$label; 9226 assert(__ use_cbcond(*L), "back to back cbcond"); 9227 __ ba_short(*L); 9228 %} 9229 ins_short_branch(1); 9230 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9231 ins_pipe(cbcond_reg_imm); 9232 %} 9233 9234 // Conditional Direct Branch 9235 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 9236 match(If cmp icc); 9237 effect(USE labl); 9238 9239 size(8); 9240 ins_cost(BRANCH_COST); 9241 format %{ "BP$cmp $icc,$labl" %} 9242 // Prim = bits 24-22, Secnd = bits 31-30 9243 ins_encode( enc_bp( labl, cmp, icc ) ); 9244 ins_avoid_back_to_back(AVOID_BEFORE); 9245 ins_pipe(br_cc); 9246 %} 9247 9248 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9249 match(If cmp icc); 9250 effect(USE labl); 9251 9252 ins_cost(BRANCH_COST); 9253 format %{ "BP$cmp $icc,$labl" %} 9254 // Prim = bits 24-22, Secnd = bits 31-30 9255 ins_encode( enc_bp( labl, cmp, icc ) ); 9256 ins_avoid_back_to_back(AVOID_BEFORE); 9257 ins_pipe(br_cc); 9258 %} 9259 9260 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9261 match(If cmp pcc); 9262 effect(USE labl); 9263 9264 size(8); 9265 ins_cost(BRANCH_COST); 9266 format %{ "BP$cmp $pcc,$labl" %} 9267 ins_encode %{ 9268 Label* L = $labl$$label; 9269 Assembler::Predict predict_taken = 9270 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9271 9272 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9273 __ delayed()->nop(); 9274 %} 9275 ins_avoid_back_to_back(AVOID_BEFORE); 9276 ins_pipe(br_cc); 9277 %} 9278 9279 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9280 match(If cmp fcc); 9281 effect(USE labl); 9282 9283 size(8); 9284 ins_cost(BRANCH_COST); 9285 format %{ "FBP$cmp $fcc,$labl" %} 9286 ins_encode %{ 9287 Label* L = $labl$$label; 9288 Assembler::Predict predict_taken = 9289 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9290 9291 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 9292 __ delayed()->nop(); 9293 %} 9294 ins_avoid_back_to_back(AVOID_BEFORE); 9295 ins_pipe(br_fcc); 9296 %} 9297 9298 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9299 match(CountedLoopEnd cmp icc); 9300 effect(USE labl); 9301 9302 size(8); 9303 ins_cost(BRANCH_COST); 9304 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9305 // Prim = bits 24-22, Secnd = bits 31-30 9306 ins_encode( enc_bp( labl, cmp, icc ) ); 9307 ins_avoid_back_to_back(AVOID_BEFORE); 9308 ins_pipe(br_cc); 9309 %} 9310 9311 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9312 match(CountedLoopEnd cmp icc); 9313 effect(USE labl); 9314 9315 size(8); 9316 ins_cost(BRANCH_COST); 9317 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9318 // Prim = bits 24-22, Secnd = bits 31-30 9319 ins_encode( enc_bp( labl, cmp, icc ) ); 9320 ins_avoid_back_to_back(AVOID_BEFORE); 9321 ins_pipe(br_cc); 9322 %} 9323 9324 // Compare and branch instructions 9325 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9326 match(If cmp (CmpI op1 op2)); 9327 effect(USE labl, KILL icc); 9328 9329 size(12); 9330 ins_cost(BRANCH_COST); 9331 format %{ "CMP $op1,$op2\t! int\n\t" 9332 "BP$cmp $labl" %} 9333 ins_encode %{ 9334 Label* L = $labl$$label; 9335 Assembler::Predict predict_taken = 9336 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9337 __ cmp($op1$$Register, $op2$$Register); 9338 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9339 __ delayed()->nop(); 9340 %} 9341 ins_pipe(cmp_br_reg_reg); 9342 %} 9343 9344 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9345 match(If cmp (CmpI op1 op2)); 9346 effect(USE labl, KILL icc); 9347 9348 size(12); 9349 ins_cost(BRANCH_COST); 9350 format %{ "CMP $op1,$op2\t! int\n\t" 9351 "BP$cmp $labl" %} 9352 ins_encode %{ 9353 Label* L = $labl$$label; 9354 Assembler::Predict predict_taken = 9355 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9356 __ cmp($op1$$Register, $op2$$constant); 9357 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9358 __ delayed()->nop(); 9359 %} 9360 ins_pipe(cmp_br_reg_imm); 9361 %} 9362 9363 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9364 match(If cmp (CmpU op1 op2)); 9365 effect(USE labl, KILL icc); 9366 9367 size(12); 9368 ins_cost(BRANCH_COST); 9369 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9370 "BP$cmp $labl" %} 9371 ins_encode %{ 9372 Label* L = $labl$$label; 9373 Assembler::Predict predict_taken = 9374 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9375 __ cmp($op1$$Register, $op2$$Register); 9376 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9377 __ delayed()->nop(); 9378 %} 9379 ins_pipe(cmp_br_reg_reg); 9380 %} 9381 9382 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9383 match(If cmp (CmpU op1 op2)); 9384 effect(USE labl, KILL icc); 9385 9386 size(12); 9387 ins_cost(BRANCH_COST); 9388 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9389 "BP$cmp $labl" %} 9390 ins_encode %{ 9391 Label* L = $labl$$label; 9392 Assembler::Predict predict_taken = 9393 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9394 __ cmp($op1$$Register, $op2$$constant); 9395 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9396 __ delayed()->nop(); 9397 %} 9398 ins_pipe(cmp_br_reg_imm); 9399 %} 9400 9401 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9402 match(If cmp (CmpL op1 op2)); 9403 effect(USE labl, KILL xcc); 9404 9405 size(12); 9406 ins_cost(BRANCH_COST); 9407 format %{ "CMP $op1,$op2\t! long\n\t" 9408 "BP$cmp $labl" %} 9409 ins_encode %{ 9410 Label* L = $labl$$label; 9411 Assembler::Predict predict_taken = 9412 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9413 __ cmp($op1$$Register, $op2$$Register); 9414 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9415 __ delayed()->nop(); 9416 %} 9417 ins_pipe(cmp_br_reg_reg); 9418 %} 9419 9420 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9421 match(If cmp (CmpL op1 op2)); 9422 effect(USE labl, KILL xcc); 9423 9424 size(12); 9425 ins_cost(BRANCH_COST); 9426 format %{ "CMP $op1,$op2\t! long\n\t" 9427 "BP$cmp $labl" %} 9428 ins_encode %{ 9429 Label* L = $labl$$label; 9430 Assembler::Predict predict_taken = 9431 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9432 __ cmp($op1$$Register, $op2$$constant); 9433 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9434 __ delayed()->nop(); 9435 %} 9436 ins_pipe(cmp_br_reg_imm); 9437 %} 9438 9439 // Compare Pointers and branch 9440 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9441 match(If cmp (CmpP op1 op2)); 9442 effect(USE labl, KILL pcc); 9443 9444 size(12); 9445 ins_cost(BRANCH_COST); 9446 format %{ "CMP $op1,$op2\t! ptr\n\t" 9447 "B$cmp $labl" %} 9448 ins_encode %{ 9449 Label* L = $labl$$label; 9450 Assembler::Predict predict_taken = 9451 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9452 __ cmp($op1$$Register, $op2$$Register); 9453 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9454 __ delayed()->nop(); 9455 %} 9456 ins_pipe(cmp_br_reg_reg); 9457 %} 9458 9459 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9460 match(If cmp (CmpP op1 null)); 9461 effect(USE labl, KILL pcc); 9462 9463 size(12); 9464 ins_cost(BRANCH_COST); 9465 format %{ "CMP $op1,0\t! ptr\n\t" 9466 "B$cmp $labl" %} 9467 ins_encode %{ 9468 Label* L = $labl$$label; 9469 Assembler::Predict predict_taken = 9470 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9471 __ cmp($op1$$Register, G0); 9472 // bpr() is not used here since it has shorter distance. 9473 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9474 __ delayed()->nop(); 9475 %} 9476 ins_pipe(cmp_br_reg_reg); 9477 %} 9478 9479 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9480 match(If cmp (CmpN op1 op2)); 9481 effect(USE labl, KILL icc); 9482 9483 size(12); 9484 ins_cost(BRANCH_COST); 9485 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9486 "BP$cmp $labl" %} 9487 ins_encode %{ 9488 Label* L = $labl$$label; 9489 Assembler::Predict predict_taken = 9490 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9491 __ cmp($op1$$Register, $op2$$Register); 9492 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9493 __ delayed()->nop(); 9494 %} 9495 ins_pipe(cmp_br_reg_reg); 9496 %} 9497 9498 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9499 match(If cmp (CmpN op1 null)); 9500 effect(USE labl, KILL icc); 9501 9502 size(12); 9503 ins_cost(BRANCH_COST); 9504 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9505 "BP$cmp $labl" %} 9506 ins_encode %{ 9507 Label* L = $labl$$label; 9508 Assembler::Predict predict_taken = 9509 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9510 __ cmp($op1$$Register, G0); 9511 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9512 __ delayed()->nop(); 9513 %} 9514 ins_pipe(cmp_br_reg_reg); 9515 %} 9516 9517 // Loop back branch 9518 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9519 match(CountedLoopEnd cmp (CmpI op1 op2)); 9520 effect(USE labl, KILL icc); 9521 9522 size(12); 9523 ins_cost(BRANCH_COST); 9524 format %{ "CMP $op1,$op2\t! int\n\t" 9525 "BP$cmp $labl\t! Loop end" %} 9526 ins_encode %{ 9527 Label* L = $labl$$label; 9528 Assembler::Predict predict_taken = 9529 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9530 __ cmp($op1$$Register, $op2$$Register); 9531 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9532 __ delayed()->nop(); 9533 %} 9534 ins_pipe(cmp_br_reg_reg); 9535 %} 9536 9537 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9538 match(CountedLoopEnd cmp (CmpI op1 op2)); 9539 effect(USE labl, KILL icc); 9540 9541 size(12); 9542 ins_cost(BRANCH_COST); 9543 format %{ "CMP $op1,$op2\t! int\n\t" 9544 "BP$cmp $labl\t! Loop end" %} 9545 ins_encode %{ 9546 Label* L = $labl$$label; 9547 Assembler::Predict predict_taken = 9548 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9549 __ cmp($op1$$Register, $op2$$constant); 9550 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9551 __ delayed()->nop(); 9552 %} 9553 ins_pipe(cmp_br_reg_imm); 9554 %} 9555 9556 // Short compare and branch instructions 9557 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9558 match(If cmp (CmpI op1 op2)); 9559 predicate(UseCBCond); 9560 effect(USE labl, KILL icc); 9561 9562 size(4); 9563 ins_cost(BRANCH_COST); 9564 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9565 ins_encode %{ 9566 Label* L = $labl$$label; 9567 assert(__ use_cbcond(*L), "back to back cbcond"); 9568 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9569 %} 9570 ins_short_branch(1); 9571 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9572 ins_pipe(cbcond_reg_reg); 9573 %} 9574 9575 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9576 match(If cmp (CmpI op1 op2)); 9577 predicate(UseCBCond); 9578 effect(USE labl, KILL icc); 9579 9580 size(4); 9581 ins_cost(BRANCH_COST); 9582 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9583 ins_encode %{ 9584 Label* L = $labl$$label; 9585 assert(__ use_cbcond(*L), "back to back cbcond"); 9586 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9587 %} 9588 ins_short_branch(1); 9589 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9590 ins_pipe(cbcond_reg_imm); 9591 %} 9592 9593 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9594 match(If cmp (CmpU op1 op2)); 9595 predicate(UseCBCond); 9596 effect(USE labl, KILL icc); 9597 9598 size(4); 9599 ins_cost(BRANCH_COST); 9600 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9601 ins_encode %{ 9602 Label* L = $labl$$label; 9603 assert(__ use_cbcond(*L), "back to back cbcond"); 9604 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9605 %} 9606 ins_short_branch(1); 9607 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9608 ins_pipe(cbcond_reg_reg); 9609 %} 9610 9611 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9612 match(If cmp (CmpU op1 op2)); 9613 predicate(UseCBCond); 9614 effect(USE labl, KILL icc); 9615 9616 size(4); 9617 ins_cost(BRANCH_COST); 9618 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9619 ins_encode %{ 9620 Label* L = $labl$$label; 9621 assert(__ use_cbcond(*L), "back to back cbcond"); 9622 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9623 %} 9624 ins_short_branch(1); 9625 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9626 ins_pipe(cbcond_reg_imm); 9627 %} 9628 9629 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9630 match(If cmp (CmpL op1 op2)); 9631 predicate(UseCBCond); 9632 effect(USE labl, KILL xcc); 9633 9634 size(4); 9635 ins_cost(BRANCH_COST); 9636 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9637 ins_encode %{ 9638 Label* L = $labl$$label; 9639 assert(__ use_cbcond(*L), "back to back cbcond"); 9640 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9641 %} 9642 ins_short_branch(1); 9643 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9644 ins_pipe(cbcond_reg_reg); 9645 %} 9646 9647 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9648 match(If cmp (CmpL op1 op2)); 9649 predicate(UseCBCond); 9650 effect(USE labl, KILL xcc); 9651 9652 size(4); 9653 ins_cost(BRANCH_COST); 9654 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9655 ins_encode %{ 9656 Label* L = $labl$$label; 9657 assert(__ use_cbcond(*L), "back to back cbcond"); 9658 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9659 %} 9660 ins_short_branch(1); 9661 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9662 ins_pipe(cbcond_reg_imm); 9663 %} 9664 9665 // Compare Pointers and branch 9666 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9667 match(If cmp (CmpP op1 op2)); 9668 predicate(UseCBCond); 9669 effect(USE labl, KILL pcc); 9670 9671 size(4); 9672 ins_cost(BRANCH_COST); 9673 #ifdef _LP64 9674 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9675 #else 9676 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} 9677 #endif 9678 ins_encode %{ 9679 Label* L = $labl$$label; 9680 assert(__ use_cbcond(*L), "back to back cbcond"); 9681 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9682 %} 9683 ins_short_branch(1); 9684 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9685 ins_pipe(cbcond_reg_reg); 9686 %} 9687 9688 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9689 match(If cmp (CmpP op1 null)); 9690 predicate(UseCBCond); 9691 effect(USE labl, KILL pcc); 9692 9693 size(4); 9694 ins_cost(BRANCH_COST); 9695 #ifdef _LP64 9696 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9697 #else 9698 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} 9699 #endif 9700 ins_encode %{ 9701 Label* L = $labl$$label; 9702 assert(__ use_cbcond(*L), "back to back cbcond"); 9703 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9704 %} 9705 ins_short_branch(1); 9706 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9707 ins_pipe(cbcond_reg_reg); 9708 %} 9709 9710 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9711 match(If cmp (CmpN op1 op2)); 9712 predicate(UseCBCond); 9713 effect(USE labl, KILL icc); 9714 9715 size(4); 9716 ins_cost(BRANCH_COST); 9717 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9718 ins_encode %{ 9719 Label* L = $labl$$label; 9720 assert(__ use_cbcond(*L), "back to back cbcond"); 9721 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9722 %} 9723 ins_short_branch(1); 9724 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9725 ins_pipe(cbcond_reg_reg); 9726 %} 9727 9728 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9729 match(If cmp (CmpN op1 null)); 9730 predicate(UseCBCond); 9731 effect(USE labl, KILL icc); 9732 9733 size(4); 9734 ins_cost(BRANCH_COST); 9735 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9736 ins_encode %{ 9737 Label* L = $labl$$label; 9738 assert(__ use_cbcond(*L), "back to back cbcond"); 9739 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9740 %} 9741 ins_short_branch(1); 9742 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9743 ins_pipe(cbcond_reg_reg); 9744 %} 9745 9746 // Loop back branch 9747 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9748 match(CountedLoopEnd cmp (CmpI op1 op2)); 9749 predicate(UseCBCond); 9750 effect(USE labl, KILL icc); 9751 9752 size(4); 9753 ins_cost(BRANCH_COST); 9754 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9755 ins_encode %{ 9756 Label* L = $labl$$label; 9757 assert(__ use_cbcond(*L), "back to back cbcond"); 9758 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9759 %} 9760 ins_short_branch(1); 9761 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9762 ins_pipe(cbcond_reg_reg); 9763 %} 9764 9765 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9766 match(CountedLoopEnd cmp (CmpI op1 op2)); 9767 predicate(UseCBCond); 9768 effect(USE labl, KILL icc); 9769 9770 size(4); 9771 ins_cost(BRANCH_COST); 9772 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9773 ins_encode %{ 9774 Label* L = $labl$$label; 9775 assert(__ use_cbcond(*L), "back to back cbcond"); 9776 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9777 %} 9778 ins_short_branch(1); 9779 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9780 ins_pipe(cbcond_reg_imm); 9781 %} 9782 9783 // Branch-on-register tests all 64 bits. We assume that values 9784 // in 64-bit registers always remains zero or sign extended 9785 // unless our code munges the high bits. Interrupts can chop 9786 // the high order bits to zero or sign at any time. 9787 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9788 match(If cmp (CmpI op1 zero)); 9789 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9790 effect(USE labl); 9791 9792 size(8); 9793 ins_cost(BRANCH_COST); 9794 format %{ "BR$cmp $op1,$labl" %} 9795 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9796 ins_avoid_back_to_back(AVOID_BEFORE); 9797 ins_pipe(br_reg); 9798 %} 9799 9800 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9801 match(If cmp (CmpP op1 null)); 9802 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9803 effect(USE labl); 9804 9805 size(8); 9806 ins_cost(BRANCH_COST); 9807 format %{ "BR$cmp $op1,$labl" %} 9808 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9809 ins_avoid_back_to_back(AVOID_BEFORE); 9810 ins_pipe(br_reg); 9811 %} 9812 9813 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9814 match(If cmp (CmpL op1 zero)); 9815 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9816 effect(USE labl); 9817 9818 size(8); 9819 ins_cost(BRANCH_COST); 9820 format %{ "BR$cmp $op1,$labl" %} 9821 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9822 ins_avoid_back_to_back(AVOID_BEFORE); 9823 ins_pipe(br_reg); 9824 %} 9825 9826 9827 // ============================================================================ 9828 // Long Compare 9829 // 9830 // Currently we hold longs in 2 registers. Comparing such values efficiently 9831 // is tricky. The flavor of compare used depends on whether we are testing 9832 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9833 // The GE test is the negated LT test. The LE test can be had by commuting 9834 // the operands (yielding a GE test) and then negating; negate again for the 9835 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9836 // NE test is negated from that. 9837 9838 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9839 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9840 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9841 // are collapsed internally in the ADLC's dfa-gen code. The match for 9842 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9843 // foo match ends up with the wrong leaf. One fix is to not match both 9844 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9845 // both forms beat the trinary form of long-compare and both are very useful 9846 // on Intel which has so few registers. 9847 9848 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9849 match(If cmp xcc); 9850 effect(USE labl); 9851 9852 size(8); 9853 ins_cost(BRANCH_COST); 9854 format %{ "BP$cmp $xcc,$labl" %} 9855 ins_encode %{ 9856 Label* L = $labl$$label; 9857 Assembler::Predict predict_taken = 9858 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9859 9860 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9861 __ delayed()->nop(); 9862 %} 9863 ins_avoid_back_to_back(AVOID_BEFORE); 9864 ins_pipe(br_cc); 9865 %} 9866 9867 // Manifest a CmpL3 result in an integer register. Very painful. 9868 // This is the test to avoid. 9869 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9870 match(Set dst (CmpL3 src1 src2) ); 9871 effect( KILL ccr ); 9872 ins_cost(6*DEFAULT_COST); 9873 size(24); 9874 format %{ "CMP $src1,$src2\t\t! long\n" 9875 "\tBLT,a,pn done\n" 9876 "\tMOV -1,$dst\t! delay slot\n" 9877 "\tBGT,a,pn done\n" 9878 "\tMOV 1,$dst\t! delay slot\n" 9879 "\tCLR $dst\n" 9880 "done:" %} 9881 ins_encode( cmpl_flag(src1,src2,dst) ); 9882 ins_pipe(cmpL_reg); 9883 %} 9884 9885 // Conditional move 9886 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9887 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9888 ins_cost(150); 9889 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9890 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9891 ins_pipe(ialu_reg); 9892 %} 9893 9894 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9895 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9896 ins_cost(140); 9897 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9898 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9899 ins_pipe(ialu_imm); 9900 %} 9901 9902 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9903 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9904 ins_cost(150); 9905 format %{ "MOV$cmp $xcc,$src,$dst" %} 9906 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9907 ins_pipe(ialu_reg); 9908 %} 9909 9910 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9911 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9912 ins_cost(140); 9913 format %{ "MOV$cmp $xcc,$src,$dst" %} 9914 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9915 ins_pipe(ialu_imm); 9916 %} 9917 9918 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9919 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9920 ins_cost(150); 9921 format %{ "MOV$cmp $xcc,$src,$dst" %} 9922 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9923 ins_pipe(ialu_reg); 9924 %} 9925 9926 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9927 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9928 ins_cost(150); 9929 format %{ "MOV$cmp $xcc,$src,$dst" %} 9930 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9931 ins_pipe(ialu_reg); 9932 %} 9933 9934 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9935 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9936 ins_cost(140); 9937 format %{ "MOV$cmp $xcc,$src,$dst" %} 9938 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9939 ins_pipe(ialu_imm); 9940 %} 9941 9942 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9943 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9944 ins_cost(150); 9945 opcode(0x101); 9946 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9947 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9948 ins_pipe(int_conditional_float_move); 9949 %} 9950 9951 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9952 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9953 ins_cost(150); 9954 opcode(0x102); 9955 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9956 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9957 ins_pipe(int_conditional_float_move); 9958 %} 9959 9960 // ============================================================================ 9961 // Safepoint Instruction 9962 instruct safePoint_poll(iRegP poll) %{ 9963 match(SafePoint poll); 9964 effect(USE poll); 9965 9966 size(4); 9967 #ifdef _LP64 9968 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9969 #else 9970 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9971 #endif 9972 ins_encode %{ 9973 __ relocate(relocInfo::poll_type); 9974 __ ld_ptr($poll$$Register, 0, G0); 9975 %} 9976 ins_pipe(loadPollP); 9977 %} 9978 9979 // ============================================================================ 9980 // Call Instructions 9981 // Call Java Static Instruction 9982 instruct CallStaticJavaDirect( method meth ) %{ 9983 match(CallStaticJava); 9984 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9985 effect(USE meth); 9986 9987 size(8); 9988 ins_cost(CALL_COST); 9989 format %{ "CALL,static ; NOP ==> " %} 9990 ins_encode( Java_Static_Call( meth ), call_epilog ); 9991 ins_avoid_back_to_back(AVOID_BEFORE); 9992 ins_pipe(simple_call); 9993 %} 9994 9995 // Call Java Static Instruction (method handle version) 9996 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9997 match(CallStaticJava); 9998 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9999 effect(USE meth, KILL l7_mh_SP_save); 10000 10001 size(16); 10002 ins_cost(CALL_COST); 10003 format %{ "CALL,static/MethodHandle" %} 10004 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 10005 ins_pipe(simple_call); 10006 %} 10007 10008 // Call Java Dynamic Instruction 10009 instruct CallDynamicJavaDirect( method meth ) %{ 10010 match(CallDynamicJava); 10011 effect(USE meth); 10012 10013 ins_cost(CALL_COST); 10014 format %{ "SET (empty),R_G5\n\t" 10015 "CALL,dynamic ; NOP ==> " %} 10016 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 10017 ins_pipe(call); 10018 %} 10019 10020 // Call Runtime Instruction 10021 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 10022 match(CallRuntime); 10023 effect(USE meth, KILL l7); 10024 ins_cost(CALL_COST); 10025 format %{ "CALL,runtime" %} 10026 ins_encode( Java_To_Runtime( meth ), 10027 call_epilog, adjust_long_from_native_call ); 10028 ins_avoid_back_to_back(AVOID_BEFORE); 10029 ins_pipe(simple_call); 10030 %} 10031 10032 // Call runtime without safepoint - same as CallRuntime 10033 instruct CallLeafDirect(method meth, l7RegP l7) %{ 10034 match(CallLeaf); 10035 effect(USE meth, KILL l7); 10036 ins_cost(CALL_COST); 10037 format %{ "CALL,runtime leaf" %} 10038 ins_encode( Java_To_Runtime( meth ), 10039 call_epilog, 10040 adjust_long_from_native_call ); 10041 ins_avoid_back_to_back(AVOID_BEFORE); 10042 ins_pipe(simple_call); 10043 %} 10044 10045 // Call runtime without safepoint - same as CallLeaf 10046 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 10047 match(CallLeafNoFP); 10048 effect(USE meth, KILL l7); 10049 ins_cost(CALL_COST); 10050 format %{ "CALL,runtime leaf nofp" %} 10051 ins_encode( Java_To_Runtime( meth ), 10052 call_epilog, 10053 adjust_long_from_native_call ); 10054 ins_avoid_back_to_back(AVOID_BEFORE); 10055 ins_pipe(simple_call); 10056 %} 10057 10058 // Tail Call; Jump from runtime stub to Java code. 10059 // Also known as an 'interprocedural jump'. 10060 // Target of jump will eventually return to caller. 10061 // TailJump below removes the return address. 10062 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 10063 match(TailCall jump_target method_oop ); 10064 10065 ins_cost(CALL_COST); 10066 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 10067 ins_encode(form_jmpl(jump_target)); 10068 ins_avoid_back_to_back(AVOID_BEFORE); 10069 ins_pipe(tail_call); 10070 %} 10071 10072 10073 // Return Instruction 10074 instruct Ret() %{ 10075 match(Return); 10076 10077 // The epilogue node did the ret already. 10078 size(0); 10079 format %{ "! return" %} 10080 ins_encode(); 10081 ins_pipe(empty); 10082 %} 10083 10084 10085 // Tail Jump; remove the return address; jump to target. 10086 // TailCall above leaves the return address around. 10087 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 10088 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 10089 // "restore" before this instruction (in Epilogue), we need to materialize it 10090 // in %i0. 10091 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 10092 match( TailJump jump_target ex_oop ); 10093 ins_cost(CALL_COST); 10094 format %{ "! discard R_O7\n\t" 10095 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 10096 ins_encode(form_jmpl_set_exception_pc(jump_target)); 10097 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 10098 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 10099 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 10100 ins_avoid_back_to_back(AVOID_BEFORE); 10101 ins_pipe(tail_call); 10102 %} 10103 10104 // Create exception oop: created by stack-crawling runtime code. 10105 // Created exception is now available to this handler, and is setup 10106 // just prior to jumping to this handler. No code emitted. 10107 instruct CreateException( o0RegP ex_oop ) 10108 %{ 10109 match(Set ex_oop (CreateEx)); 10110 ins_cost(0); 10111 10112 size(0); 10113 // use the following format syntax 10114 format %{ "! exception oop is in R_O0; no code emitted" %} 10115 ins_encode(); 10116 ins_pipe(empty); 10117 %} 10118 10119 10120 // Rethrow exception: 10121 // The exception oop will come in the first argument position. 10122 // Then JUMP (not call) to the rethrow stub code. 10123 instruct RethrowException() 10124 %{ 10125 match(Rethrow); 10126 ins_cost(CALL_COST); 10127 10128 // use the following format syntax 10129 format %{ "Jmp rethrow_stub" %} 10130 ins_encode(enc_rethrow); 10131 ins_avoid_back_to_back(AVOID_BEFORE); 10132 ins_pipe(tail_call); 10133 %} 10134 10135 10136 // Die now 10137 instruct ShouldNotReachHere( ) 10138 %{ 10139 match(Halt); 10140 ins_cost(CALL_COST); 10141 10142 size(4); 10143 // Use the following format syntax 10144 format %{ "ILLTRAP ; ShouldNotReachHere" %} 10145 ins_encode( form2_illtrap() ); 10146 ins_pipe(tail_call); 10147 %} 10148 10149 // ============================================================================ 10150 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10151 // array for an instance of the superklass. Set a hidden internal cache on a 10152 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10153 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10154 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 10155 match(Set index (PartialSubtypeCheck sub super)); 10156 effect( KILL pcc, KILL o7 ); 10157 ins_cost(DEFAULT_COST*10); 10158 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 10159 ins_encode( enc_PartialSubtypeCheck() ); 10160 ins_avoid_back_to_back(AVOID_BEFORE); 10161 ins_pipe(partial_subtype_check_pipe); 10162 %} 10163 10164 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 10165 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 10166 effect( KILL idx, KILL o7 ); 10167 ins_cost(DEFAULT_COST*10); 10168 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 10169 ins_encode( enc_PartialSubtypeCheck() ); 10170 ins_avoid_back_to_back(AVOID_BEFORE); 10171 ins_pipe(partial_subtype_check_pipe); 10172 %} 10173 10174 10175 // ============================================================================ 10176 // inlined locking and unlocking 10177 10178 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10179 match(Set pcc (FastLock object box)); 10180 10181 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10182 ins_cost(100); 10183 10184 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10185 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 10186 ins_pipe(long_memory_op); 10187 %} 10188 10189 10190 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10191 match(Set pcc (FastUnlock object box)); 10192 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10193 ins_cost(100); 10194 10195 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10196 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 10197 ins_pipe(long_memory_op); 10198 %} 10199 10200 // The encodings are generic. 10201 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 10202 predicate(!use_block_zeroing(n->in(2)) ); 10203 match(Set dummy (ClearArray cnt base)); 10204 effect(TEMP temp, KILL ccr); 10205 ins_cost(300); 10206 format %{ "MOV $cnt,$temp\n" 10207 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 10208 " BRge loop\t\t! Clearing loop\n" 10209 " STX G0,[$base+$temp]\t! delay slot" %} 10210 10211 ins_encode %{ 10212 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 10213 Register nof_bytes_arg = $cnt$$Register; 10214 Register nof_bytes_tmp = $temp$$Register; 10215 Register base_pointer_arg = $base$$Register; 10216 10217 Label loop; 10218 __ mov(nof_bytes_arg, nof_bytes_tmp); 10219 10220 // Loop and clear, walking backwards through the array. 10221 // nof_bytes_tmp (if >0) is always the number of bytes to zero 10222 __ bind(loop); 10223 __ deccc(nof_bytes_tmp, 8); 10224 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 10225 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 10226 // %%%% this mini-loop must not cross a cache boundary! 10227 %} 10228 ins_pipe(long_memory_op); 10229 %} 10230 10231 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 10232 predicate(use_block_zeroing(n->in(2))); 10233 match(Set dummy (ClearArray cnt base)); 10234 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 10235 ins_cost(300); 10236 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10237 10238 ins_encode %{ 10239 10240 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10241 Register to = $base$$Register; 10242 Register count = $cnt$$Register; 10243 10244 Label Ldone; 10245 __ nop(); // Separate short branches 10246 // Use BIS for zeroing (temp is not used). 10247 __ bis_zeroing(to, count, G0, Ldone); 10248 __ bind(Ldone); 10249 10250 %} 10251 ins_pipe(long_memory_op); 10252 %} 10253 10254 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 10255 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 10256 match(Set dummy (ClearArray cnt base)); 10257 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 10258 ins_cost(300); 10259 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10260 10261 ins_encode %{ 10262 10263 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10264 Register to = $base$$Register; 10265 Register count = $cnt$$Register; 10266 Register temp = $tmp$$Register; 10267 10268 Label Ldone; 10269 __ nop(); // Separate short branches 10270 // Use BIS for zeroing 10271 __ bis_zeroing(to, count, temp, Ldone); 10272 __ bind(Ldone); 10273 10274 %} 10275 ins_pipe(long_memory_op); 10276 %} 10277 10278 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10279 o7RegI tmp, flagsReg ccr) %{ 10280 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10281 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10282 ins_cost(300); 10283 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10284 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 10285 ins_pipe(long_memory_op); 10286 %} 10287 10288 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10289 o7RegI tmp, flagsReg ccr) %{ 10290 match(Set result (StrEquals (Binary str1 str2) cnt)); 10291 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10292 ins_cost(300); 10293 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 10294 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 10295 ins_pipe(long_memory_op); 10296 %} 10297 10298 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10299 o7RegI tmp2, flagsReg ccr) %{ 10300 match(Set result (AryEq ary1 ary2)); 10301 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10302 ins_cost(300); 10303 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10304 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 10305 ins_pipe(long_memory_op); 10306 %} 10307 10308 10309 //---------- Zeros Count Instructions ------------------------------------------ 10310 10311 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10312 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10313 match(Set dst (CountLeadingZerosI src)); 10314 effect(TEMP dst, TEMP tmp, KILL cr); 10315 10316 // x |= (x >> 1); 10317 // x |= (x >> 2); 10318 // x |= (x >> 4); 10319 // x |= (x >> 8); 10320 // x |= (x >> 16); 10321 // return (WORDBITS - popc(x)); 10322 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10323 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10324 "OR $dst,$tmp,$dst\n\t" 10325 "SRL $dst,2,$tmp\n\t" 10326 "OR $dst,$tmp,$dst\n\t" 10327 "SRL $dst,4,$tmp\n\t" 10328 "OR $dst,$tmp,$dst\n\t" 10329 "SRL $dst,8,$tmp\n\t" 10330 "OR $dst,$tmp,$dst\n\t" 10331 "SRL $dst,16,$tmp\n\t" 10332 "OR $dst,$tmp,$dst\n\t" 10333 "POPC $dst,$dst\n\t" 10334 "MOV 32,$tmp\n\t" 10335 "SUB $tmp,$dst,$dst" %} 10336 ins_encode %{ 10337 Register Rdst = $dst$$Register; 10338 Register Rsrc = $src$$Register; 10339 Register Rtmp = $tmp$$Register; 10340 __ srl(Rsrc, 1, Rtmp); 10341 __ srl(Rsrc, 0, Rdst); 10342 __ or3(Rdst, Rtmp, Rdst); 10343 __ srl(Rdst, 2, Rtmp); 10344 __ or3(Rdst, Rtmp, Rdst); 10345 __ srl(Rdst, 4, Rtmp); 10346 __ or3(Rdst, Rtmp, Rdst); 10347 __ srl(Rdst, 8, Rtmp); 10348 __ or3(Rdst, Rtmp, Rdst); 10349 __ srl(Rdst, 16, Rtmp); 10350 __ or3(Rdst, Rtmp, Rdst); 10351 __ popc(Rdst, Rdst); 10352 __ mov(BitsPerInt, Rtmp); 10353 __ sub(Rtmp, Rdst, Rdst); 10354 %} 10355 ins_pipe(ialu_reg); 10356 %} 10357 10358 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10359 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10360 match(Set dst (CountLeadingZerosL src)); 10361 effect(TEMP dst, TEMP tmp, KILL cr); 10362 10363 // x |= (x >> 1); 10364 // x |= (x >> 2); 10365 // x |= (x >> 4); 10366 // x |= (x >> 8); 10367 // x |= (x >> 16); 10368 // x |= (x >> 32); 10369 // return (WORDBITS - popc(x)); 10370 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10371 "OR $src,$tmp,$dst\n\t" 10372 "SRLX $dst,2,$tmp\n\t" 10373 "OR $dst,$tmp,$dst\n\t" 10374 "SRLX $dst,4,$tmp\n\t" 10375 "OR $dst,$tmp,$dst\n\t" 10376 "SRLX $dst,8,$tmp\n\t" 10377 "OR $dst,$tmp,$dst\n\t" 10378 "SRLX $dst,16,$tmp\n\t" 10379 "OR $dst,$tmp,$dst\n\t" 10380 "SRLX $dst,32,$tmp\n\t" 10381 "OR $dst,$tmp,$dst\n\t" 10382 "POPC $dst,$dst\n\t" 10383 "MOV 64,$tmp\n\t" 10384 "SUB $tmp,$dst,$dst" %} 10385 ins_encode %{ 10386 Register Rdst = $dst$$Register; 10387 Register Rsrc = $src$$Register; 10388 Register Rtmp = $tmp$$Register; 10389 __ srlx(Rsrc, 1, Rtmp); 10390 __ or3( Rsrc, Rtmp, Rdst); 10391 __ srlx(Rdst, 2, Rtmp); 10392 __ or3( Rdst, Rtmp, Rdst); 10393 __ srlx(Rdst, 4, Rtmp); 10394 __ or3( Rdst, Rtmp, Rdst); 10395 __ srlx(Rdst, 8, Rtmp); 10396 __ or3( Rdst, Rtmp, Rdst); 10397 __ srlx(Rdst, 16, Rtmp); 10398 __ or3( Rdst, Rtmp, Rdst); 10399 __ srlx(Rdst, 32, Rtmp); 10400 __ or3( Rdst, Rtmp, Rdst); 10401 __ popc(Rdst, Rdst); 10402 __ mov(BitsPerLong, Rtmp); 10403 __ sub(Rtmp, Rdst, Rdst); 10404 %} 10405 ins_pipe(ialu_reg); 10406 %} 10407 10408 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 10409 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10410 match(Set dst (CountTrailingZerosI src)); 10411 effect(TEMP dst, KILL cr); 10412 10413 // return popc(~x & (x - 1)); 10414 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10415 "ANDN $dst,$src,$dst\n\t" 10416 "SRL $dst,R_G0,$dst\n\t" 10417 "POPC $dst,$dst" %} 10418 ins_encode %{ 10419 Register Rdst = $dst$$Register; 10420 Register Rsrc = $src$$Register; 10421 __ sub(Rsrc, 1, Rdst); 10422 __ andn(Rdst, Rsrc, Rdst); 10423 __ srl(Rdst, G0, Rdst); 10424 __ popc(Rdst, Rdst); 10425 %} 10426 ins_pipe(ialu_reg); 10427 %} 10428 10429 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10430 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10431 match(Set dst (CountTrailingZerosL src)); 10432 effect(TEMP dst, KILL cr); 10433 10434 // return popc(~x & (x - 1)); 10435 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10436 "ANDN $dst,$src,$dst\n\t" 10437 "POPC $dst,$dst" %} 10438 ins_encode %{ 10439 Register Rdst = $dst$$Register; 10440 Register Rsrc = $src$$Register; 10441 __ sub(Rsrc, 1, Rdst); 10442 __ andn(Rdst, Rsrc, Rdst); 10443 __ popc(Rdst, Rdst); 10444 %} 10445 ins_pipe(ialu_reg); 10446 %} 10447 10448 10449 //---------- Population Count Instructions ------------------------------------- 10450 10451 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10452 predicate(UsePopCountInstruction); 10453 match(Set dst (PopCountI src)); 10454 10455 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10456 "POPC $dst, $dst" %} 10457 ins_encode %{ 10458 __ srl($src$$Register, G0, $dst$$Register); 10459 __ popc($dst$$Register, $dst$$Register); 10460 %} 10461 ins_pipe(ialu_reg); 10462 %} 10463 10464 // Note: Long.bitCount(long) returns an int. 10465 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10466 predicate(UsePopCountInstruction); 10467 match(Set dst (PopCountL src)); 10468 10469 format %{ "POPC $src, $dst" %} 10470 ins_encode %{ 10471 __ popc($src$$Register, $dst$$Register); 10472 %} 10473 ins_pipe(ialu_reg); 10474 %} 10475 10476 10477 // ============================================================================ 10478 //------------Bytes reverse-------------------------------------------------- 10479 10480 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10481 match(Set dst (ReverseBytesI src)); 10482 10483 // Op cost is artificially doubled to make sure that load or store 10484 // instructions are preferred over this one which requires a spill 10485 // onto a stack slot. 10486 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10487 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10488 10489 ins_encode %{ 10490 __ set($src$$disp + STACK_BIAS, O7); 10491 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10492 %} 10493 ins_pipe( iload_mem ); 10494 %} 10495 10496 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10497 match(Set dst (ReverseBytesL src)); 10498 10499 // Op cost is artificially doubled to make sure that load or store 10500 // instructions are preferred over this one which requires a spill 10501 // onto a stack slot. 10502 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10503 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10504 10505 ins_encode %{ 10506 __ set($src$$disp + STACK_BIAS, O7); 10507 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10508 %} 10509 ins_pipe( iload_mem ); 10510 %} 10511 10512 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10513 match(Set dst (ReverseBytesUS src)); 10514 10515 // Op cost is artificially doubled to make sure that load or store 10516 // instructions are preferred over this one which requires a spill 10517 // onto a stack slot. 10518 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10519 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10520 10521 ins_encode %{ 10522 // the value was spilled as an int so bias the load 10523 __ set($src$$disp + STACK_BIAS + 2, O7); 10524 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10525 %} 10526 ins_pipe( iload_mem ); 10527 %} 10528 10529 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10530 match(Set dst (ReverseBytesS src)); 10531 10532 // Op cost is artificially doubled to make sure that load or store 10533 // instructions are preferred over this one which requires a spill 10534 // onto a stack slot. 10535 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10536 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10537 10538 ins_encode %{ 10539 // the value was spilled as an int so bias the load 10540 __ set($src$$disp + STACK_BIAS + 2, O7); 10541 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10542 %} 10543 ins_pipe( iload_mem ); 10544 %} 10545 10546 // Load Integer reversed byte order 10547 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10548 match(Set dst (ReverseBytesI (LoadI src))); 10549 10550 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10551 size(4); 10552 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10553 10554 ins_encode %{ 10555 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10556 %} 10557 ins_pipe(iload_mem); 10558 %} 10559 10560 // Load Long - aligned and reversed 10561 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10562 match(Set dst (ReverseBytesL (LoadL src))); 10563 10564 ins_cost(MEMORY_REF_COST); 10565 size(4); 10566 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10567 10568 ins_encode %{ 10569 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10570 %} 10571 ins_pipe(iload_mem); 10572 %} 10573 10574 // Load unsigned short / char reversed byte order 10575 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10576 match(Set dst (ReverseBytesUS (LoadUS src))); 10577 10578 ins_cost(MEMORY_REF_COST); 10579 size(4); 10580 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10581 10582 ins_encode %{ 10583 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10584 %} 10585 ins_pipe(iload_mem); 10586 %} 10587 10588 // Load short reversed byte order 10589 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10590 match(Set dst (ReverseBytesS (LoadS src))); 10591 10592 ins_cost(MEMORY_REF_COST); 10593 size(4); 10594 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10595 10596 ins_encode %{ 10597 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10598 %} 10599 ins_pipe(iload_mem); 10600 %} 10601 10602 // Store Integer reversed byte order 10603 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10604 match(Set dst (StoreI dst (ReverseBytesI src))); 10605 10606 ins_cost(MEMORY_REF_COST); 10607 size(4); 10608 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10609 10610 ins_encode %{ 10611 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10612 %} 10613 ins_pipe(istore_mem_reg); 10614 %} 10615 10616 // Store Long reversed byte order 10617 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10618 match(Set dst (StoreL dst (ReverseBytesL src))); 10619 10620 ins_cost(MEMORY_REF_COST); 10621 size(4); 10622 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10623 10624 ins_encode %{ 10625 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10626 %} 10627 ins_pipe(istore_mem_reg); 10628 %} 10629 10630 // Store unsighed short/char reversed byte order 10631 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10632 match(Set dst (StoreC dst (ReverseBytesUS src))); 10633 10634 ins_cost(MEMORY_REF_COST); 10635 size(4); 10636 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10637 10638 ins_encode %{ 10639 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10640 %} 10641 ins_pipe(istore_mem_reg); 10642 %} 10643 10644 // Store short reversed byte order 10645 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10646 match(Set dst (StoreC dst (ReverseBytesS src))); 10647 10648 ins_cost(MEMORY_REF_COST); 10649 size(4); 10650 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10651 10652 ins_encode %{ 10653 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10654 %} 10655 ins_pipe(istore_mem_reg); 10656 %} 10657 10658 // ====================VECTOR INSTRUCTIONS===================================== 10659 10660 // Load Aligned Packed values into a Double Register 10661 instruct loadV8(regD dst, memory mem) %{ 10662 predicate(n->as_LoadVector()->memory_size() == 8); 10663 match(Set dst (LoadVector mem)); 10664 ins_cost(MEMORY_REF_COST); 10665 size(4); 10666 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10667 ins_encode %{ 10668 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10669 %} 10670 ins_pipe(floadD_mem); 10671 %} 10672 10673 // Store Vector in Double register to memory 10674 instruct storeV8(memory mem, regD src) %{ 10675 predicate(n->as_StoreVector()->memory_size() == 8); 10676 match(Set mem (StoreVector mem src)); 10677 ins_cost(MEMORY_REF_COST); 10678 size(4); 10679 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10680 ins_encode %{ 10681 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10682 %} 10683 ins_pipe(fstoreD_mem_reg); 10684 %} 10685 10686 // Store Zero into vector in memory 10687 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10688 predicate(n->as_StoreVector()->memory_size() == 8); 10689 match(Set mem (StoreVector mem (ReplicateB zero))); 10690 ins_cost(MEMORY_REF_COST); 10691 size(4); 10692 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10693 ins_encode %{ 10694 __ stx(G0, $mem$$Address); 10695 %} 10696 ins_pipe(fstoreD_mem_zero); 10697 %} 10698 10699 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10700 predicate(n->as_StoreVector()->memory_size() == 8); 10701 match(Set mem (StoreVector mem (ReplicateS zero))); 10702 ins_cost(MEMORY_REF_COST); 10703 size(4); 10704 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10705 ins_encode %{ 10706 __ stx(G0, $mem$$Address); 10707 %} 10708 ins_pipe(fstoreD_mem_zero); 10709 %} 10710 10711 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10712 predicate(n->as_StoreVector()->memory_size() == 8); 10713 match(Set mem (StoreVector mem (ReplicateI zero))); 10714 ins_cost(MEMORY_REF_COST); 10715 size(4); 10716 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10717 ins_encode %{ 10718 __ stx(G0, $mem$$Address); 10719 %} 10720 ins_pipe(fstoreD_mem_zero); 10721 %} 10722 10723 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10724 predicate(n->as_StoreVector()->memory_size() == 8); 10725 match(Set mem (StoreVector mem (ReplicateF zero))); 10726 ins_cost(MEMORY_REF_COST); 10727 size(4); 10728 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10729 ins_encode %{ 10730 __ stx(G0, $mem$$Address); 10731 %} 10732 ins_pipe(fstoreD_mem_zero); 10733 %} 10734 10735 // Replicate scalar to packed byte values into Double register 10736 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10737 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10738 match(Set dst (ReplicateB src)); 10739 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10740 format %{ "SLLX $src,56,$tmp\n\t" 10741 "SRLX $tmp, 8,$tmp2\n\t" 10742 "OR $tmp,$tmp2,$tmp\n\t" 10743 "SRLX $tmp,16,$tmp2\n\t" 10744 "OR $tmp,$tmp2,$tmp\n\t" 10745 "SRLX $tmp,32,$tmp2\n\t" 10746 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10747 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10748 ins_encode %{ 10749 Register Rsrc = $src$$Register; 10750 Register Rtmp = $tmp$$Register; 10751 Register Rtmp2 = $tmp2$$Register; 10752 __ sllx(Rsrc, 56, Rtmp); 10753 __ srlx(Rtmp, 8, Rtmp2); 10754 __ or3 (Rtmp, Rtmp2, Rtmp); 10755 __ srlx(Rtmp, 16, Rtmp2); 10756 __ or3 (Rtmp, Rtmp2, Rtmp); 10757 __ srlx(Rtmp, 32, Rtmp2); 10758 __ or3 (Rtmp, Rtmp2, Rtmp); 10759 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10760 %} 10761 ins_pipe(ialu_reg); 10762 %} 10763 10764 // Replicate scalar to packed byte values into Double stack 10765 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10766 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10767 match(Set dst (ReplicateB src)); 10768 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10769 format %{ "SLLX $src,56,$tmp\n\t" 10770 "SRLX $tmp, 8,$tmp2\n\t" 10771 "OR $tmp,$tmp2,$tmp\n\t" 10772 "SRLX $tmp,16,$tmp2\n\t" 10773 "OR $tmp,$tmp2,$tmp\n\t" 10774 "SRLX $tmp,32,$tmp2\n\t" 10775 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10776 "STX $tmp,$dst\t! regL to stkD" %} 10777 ins_encode %{ 10778 Register Rsrc = $src$$Register; 10779 Register Rtmp = $tmp$$Register; 10780 Register Rtmp2 = $tmp2$$Register; 10781 __ sllx(Rsrc, 56, Rtmp); 10782 __ srlx(Rtmp, 8, Rtmp2); 10783 __ or3 (Rtmp, Rtmp2, Rtmp); 10784 __ srlx(Rtmp, 16, Rtmp2); 10785 __ or3 (Rtmp, Rtmp2, Rtmp); 10786 __ srlx(Rtmp, 32, Rtmp2); 10787 __ or3 (Rtmp, Rtmp2, Rtmp); 10788 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10789 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10790 %} 10791 ins_pipe(ialu_reg); 10792 %} 10793 10794 // Replicate scalar constant to packed byte values in Double register 10795 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10796 predicate(n->as_Vector()->length() == 8); 10797 match(Set dst (ReplicateB con)); 10798 effect(KILL tmp); 10799 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10800 ins_encode %{ 10801 // XXX This is a quick fix for 6833573. 10802 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10803 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10804 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10805 %} 10806 ins_pipe(loadConFD); 10807 %} 10808 10809 // Replicate scalar to packed char/short values into Double register 10810 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10811 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10812 match(Set dst (ReplicateS src)); 10813 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10814 format %{ "SLLX $src,48,$tmp\n\t" 10815 "SRLX $tmp,16,$tmp2\n\t" 10816 "OR $tmp,$tmp2,$tmp\n\t" 10817 "SRLX $tmp,32,$tmp2\n\t" 10818 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10819 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10820 ins_encode %{ 10821 Register Rsrc = $src$$Register; 10822 Register Rtmp = $tmp$$Register; 10823 Register Rtmp2 = $tmp2$$Register; 10824 __ sllx(Rsrc, 48, Rtmp); 10825 __ srlx(Rtmp, 16, Rtmp2); 10826 __ or3 (Rtmp, Rtmp2, Rtmp); 10827 __ srlx(Rtmp, 32, Rtmp2); 10828 __ or3 (Rtmp, Rtmp2, Rtmp); 10829 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10830 %} 10831 ins_pipe(ialu_reg); 10832 %} 10833 10834 // Replicate scalar to packed char/short values into Double stack 10835 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10836 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10837 match(Set dst (ReplicateS src)); 10838 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10839 format %{ "SLLX $src,48,$tmp\n\t" 10840 "SRLX $tmp,16,$tmp2\n\t" 10841 "OR $tmp,$tmp2,$tmp\n\t" 10842 "SRLX $tmp,32,$tmp2\n\t" 10843 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10844 "STX $tmp,$dst\t! regL to stkD" %} 10845 ins_encode %{ 10846 Register Rsrc = $src$$Register; 10847 Register Rtmp = $tmp$$Register; 10848 Register Rtmp2 = $tmp2$$Register; 10849 __ sllx(Rsrc, 48, Rtmp); 10850 __ srlx(Rtmp, 16, Rtmp2); 10851 __ or3 (Rtmp, Rtmp2, Rtmp); 10852 __ srlx(Rtmp, 32, Rtmp2); 10853 __ or3 (Rtmp, Rtmp2, Rtmp); 10854 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10855 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10856 %} 10857 ins_pipe(ialu_reg); 10858 %} 10859 10860 // Replicate scalar constant to packed char/short values in Double register 10861 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10862 predicate(n->as_Vector()->length() == 4); 10863 match(Set dst (ReplicateS con)); 10864 effect(KILL tmp); 10865 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10866 ins_encode %{ 10867 // XXX This is a quick fix for 6833573. 10868 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10869 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10870 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10871 %} 10872 ins_pipe(loadConFD); 10873 %} 10874 10875 // Replicate scalar to packed int values into Double register 10876 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10877 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10878 match(Set dst (ReplicateI src)); 10879 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10880 format %{ "SLLX $src,32,$tmp\n\t" 10881 "SRLX $tmp,32,$tmp2\n\t" 10882 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10883 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10884 ins_encode %{ 10885 Register Rsrc = $src$$Register; 10886 Register Rtmp = $tmp$$Register; 10887 Register Rtmp2 = $tmp2$$Register; 10888 __ sllx(Rsrc, 32, Rtmp); 10889 __ srlx(Rtmp, 32, Rtmp2); 10890 __ or3 (Rtmp, Rtmp2, Rtmp); 10891 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10892 %} 10893 ins_pipe(ialu_reg); 10894 %} 10895 10896 // Replicate scalar to packed int values into Double stack 10897 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10898 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10899 match(Set dst (ReplicateI src)); 10900 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10901 format %{ "SLLX $src,32,$tmp\n\t" 10902 "SRLX $tmp,32,$tmp2\n\t" 10903 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10904 "STX $tmp,$dst\t! regL to stkD" %} 10905 ins_encode %{ 10906 Register Rsrc = $src$$Register; 10907 Register Rtmp = $tmp$$Register; 10908 Register Rtmp2 = $tmp2$$Register; 10909 __ sllx(Rsrc, 32, Rtmp); 10910 __ srlx(Rtmp, 32, Rtmp2); 10911 __ or3 (Rtmp, Rtmp2, Rtmp); 10912 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10913 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10914 %} 10915 ins_pipe(ialu_reg); 10916 %} 10917 10918 // Replicate scalar zero constant to packed int values in Double register 10919 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10920 predicate(n->as_Vector()->length() == 2); 10921 match(Set dst (ReplicateI con)); 10922 effect(KILL tmp); 10923 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10924 ins_encode %{ 10925 // XXX This is a quick fix for 6833573. 10926 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10927 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10928 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10929 %} 10930 ins_pipe(loadConFD); 10931 %} 10932 10933 // Replicate scalar to packed float values into Double stack 10934 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10935 predicate(n->as_Vector()->length() == 2); 10936 match(Set dst (ReplicateF src)); 10937 ins_cost(MEMORY_REF_COST*2); 10938 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10939 "STF $src,$dst.lo" %} 10940 opcode(Assembler::stf_op3); 10941 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10942 ins_pipe(fstoreF_stk_reg); 10943 %} 10944 10945 // Replicate scalar zero constant to packed float values in Double register 10946 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10947 predicate(n->as_Vector()->length() == 2); 10948 match(Set dst (ReplicateF con)); 10949 effect(KILL tmp); 10950 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10951 ins_encode %{ 10952 // XXX This is a quick fix for 6833573. 10953 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10954 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10955 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10956 %} 10957 ins_pipe(loadConFD); 10958 %} 10959 10960 //----------PEEPHOLE RULES----------------------------------------------------- 10961 // These must follow all instruction definitions as they use the names 10962 // defined in the instructions definitions. 10963 // 10964 // peepmatch ( root_instr_name [preceding_instruction]* ); 10965 // 10966 // peepconstraint %{ 10967 // (instruction_number.operand_name relational_op instruction_number.operand_name 10968 // [, ...] ); 10969 // // instruction numbers are zero-based using left to right order in peepmatch 10970 // 10971 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10972 // // provide an instruction_number.operand_name for each operand that appears 10973 // // in the replacement instruction's match rule 10974 // 10975 // ---------VM FLAGS--------------------------------------------------------- 10976 // 10977 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10978 // 10979 // Each peephole rule is given an identifying number starting with zero and 10980 // increasing by one in the order seen by the parser. An individual peephole 10981 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10982 // on the command-line. 10983 // 10984 // ---------CURRENT LIMITATIONS---------------------------------------------- 10985 // 10986 // Only match adjacent instructions in same basic block 10987 // Only equality constraints 10988 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10989 // Only one replacement instruction 10990 // 10991 // ---------EXAMPLE---------------------------------------------------------- 10992 // 10993 // // pertinent parts of existing instructions in architecture description 10994 // instruct movI(eRegI dst, eRegI src) %{ 10995 // match(Set dst (CopyI src)); 10996 // %} 10997 // 10998 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10999 // match(Set dst (AddI dst src)); 11000 // effect(KILL cr); 11001 // %} 11002 // 11003 // // Change (inc mov) to lea 11004 // peephole %{ 11005 // // increment preceeded by register-register move 11006 // peepmatch ( incI_eReg movI ); 11007 // // require that the destination register of the increment 11008 // // match the destination register of the move 11009 // peepconstraint ( 0.dst == 1.dst ); 11010 // // construct a replacement instruction that sets 11011 // // the destination to ( move's source register + one ) 11012 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 11013 // %} 11014 // 11015 11016 // // Change load of spilled value to only a spill 11017 // instruct storeI(memory mem, eRegI src) %{ 11018 // match(Set mem (StoreI mem src)); 11019 // %} 11020 // 11021 // instruct loadI(eRegI dst, memory mem) %{ 11022 // match(Set dst (LoadI mem)); 11023 // %} 11024 // 11025 // peephole %{ 11026 // peepmatch ( loadI storeI ); 11027 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 11028 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 11029 // %} 11030 11031 //----------SMARTSPILL RULES--------------------------------------------------- 11032 // These must follow all instruction definitions as they use the names 11033 // defined in the instructions definitions. 11034 // 11035 // SPARC will probably not have any of these rules due to RISC instruction set. 11036 11037 //----------PIPELINE----------------------------------------------------------- 11038 // Rules which define the behavior of the target architectures pipeline.