1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (2 * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
360
361
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
368
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
375
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() const {
378 // if rounding, must let FrameMap know!
379
380 // The frame_map records size in slots (32bit word)
381
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
385
386
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
394
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size);
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
402
403 int offset = code_offset();
404
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
408
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
411
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
416 __ end_a_stub();
417
418 return offset;
419 }
420
421
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
430
431 int offset = code_offset();
432
433 // Fetch the exception from TLS and clear out exception related thread state
434 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
435 NOT_LP64(__ get_thread(rsi));
436 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
437 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
438 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439
440 __ bind(_unwind_handler_entry);
441 __ verify_not_null_oop(rax);
442 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
443 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
444 }
445
446 // Preform needed unlocking
447 MonitorExitStub* stub = NULL;
448 if (method()->is_synchronized()) {
449 monitor_address(0, FrameMap::rax_opr);
450 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
451 __ unlock_object(rdi, rsi, rax, *stub->entry());
452 __ bind(*stub->continuation());
453 }
454
455 if (compilation()->env()->dtrace_method_probes()) {
456 #ifdef _LP64
457 __ mov(rdi, r15_thread);
458 __ mov_metadata(rsi, method()->constant_encoding());
459 #else
460 __ get_thread(rax);
461 __ movptr(Address(rsp, 0), rax);
462 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
463 #endif
464 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
465 }
466
467 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
468 __ mov(rax, rbx); // Restore the exception
469 }
470
471 // remove the activation and dispatch to the unwind handler
472 __ remove_frame(initial_frame_size_in_bytes());
473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
474
475 // Emit the slow path assembly
476 if (stub != NULL) {
477 stub->emit_code(this);
478 }
479
480 return offset;
481 }
482
483
484 int LIR_Assembler::emit_deopt_handler() {
485 // if the last instruction is a call (typically to do a throw which
486 // is coming at the end after block reordering) the return address
487 // must still point into the code area in order to avoid assertion
488 // failures when searching for the corresponding bci => add a nop
489 // (was bug 5/14/1999 - gri)
490 __ nop();
491
492 // generate code for exception handler
493 address handler_base = __ start_a_stub(deopt_handler_size);
494 if (handler_base == NULL) {
495 // not enough space left for the handler
496 bailout("deopt handler overflow");
497 return -1;
498 }
499
500 int offset = code_offset();
501 InternalAddress here(__ pc());
502
503 __ pushptr(here.addr());
504 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
505 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
506 __ end_a_stub();
507
508 return offset;
509 }
510
511
512 // This is the fast version of java.lang.String.compare; it has not
513 // OSR-entry and therefore, we generate a slow version for OSR's
514 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
515 __ movptr (rbx, rcx); // receiver is in rcx
516 __ movptr (rax, arg1->as_register());
517
518 // Get addresses of first characters from both Strings
519 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
520 if (java_lang_String::has_offset_field()) {
521 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
522 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
523 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
524 } else {
525 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
526 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
527 }
528
529 // rbx, may be NULL
530 add_debug_info_for_null_check_here(info);
531 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
532 if (java_lang_String::has_offset_field()) {
533 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
534 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
535 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
536 } else {
537 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
538 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
539 }
540
541 // compute minimum length (in rax) and difference of lengths (on top of stack)
542 __ mov (rcx, rbx);
543 __ subptr(rbx, rax); // subtract lengths
544 __ push (rbx); // result
545 __ cmov (Assembler::lessEqual, rax, rcx);
546
547 // is minimum length 0?
548 Label noLoop, haveResult;
549 __ testptr (rax, rax);
550 __ jcc (Assembler::zero, noLoop);
551
552 // compare first characters
553 __ load_unsigned_short(rcx, Address(rdi, 0));
554 __ load_unsigned_short(rbx, Address(rsi, 0));
555 __ subl(rcx, rbx);
556 __ jcc(Assembler::notZero, haveResult);
557 // starting loop
558 __ decrement(rax); // we already tested index: skip one
559 __ jcc(Assembler::zero, noLoop);
560
561 // set rsi.edi to the end of the arrays (arrays have same length)
562 // negate the index
563
564 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
565 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
566 __ negptr(rax);
567
568 // compare the strings in a loop
569
570 Label loop;
571 __ align(wordSize);
572 __ bind(loop);
573 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
574 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
575 __ subl(rcx, rbx);
576 __ jcc(Assembler::notZero, haveResult);
577 __ increment(rax);
578 __ jcc(Assembler::notZero, loop);
579
580 // strings are equal up to min length
581
582 __ bind(noLoop);
583 __ pop(rax);
584 return_op(LIR_OprFact::illegalOpr);
585
586 __ bind(haveResult);
587 // leave instruction is going to discard the TOS value
588 __ mov (rax, rcx); // result of call is in rax,
589 }
590
591
592 void LIR_Assembler::return_op(LIR_Opr result) {
593 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
594 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
595 assert(result->fpu() == 0, "result must already be on TOS");
596 }
597
598 // Pop the stack before the safepoint code
599 __ remove_frame(initial_frame_size_in_bytes());
600
601 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
602 __ reserved_stack_check();
603 }
604
605 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
606
607 // Note: we do not need to round double result; float result has the right precision
608 // the poll sets the condition code, but no data registers
609 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
610
611 if (Assembler::is_polling_page_far()) {
612 __ lea(rscratch1, polling_page);
613 __ relocate(relocInfo::poll_return_type);
614 __ testl(rax, Address(rscratch1, 0));
615 } else {
616 __ testl(rax, polling_page);
617 }
618 __ ret(0);
619 }
620
621
622 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
623 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
624 guarantee(info != NULL, "Shouldn't be NULL");
625 int offset = __ offset();
626 if (Assembler::is_polling_page_far()) {
627 __ lea(rscratch1, polling_page);
628 offset = __ offset();
629 add_debug_info_for_branch(info);
630 __ relocate(relocInfo::poll_type);
631 __ testl(rax, Address(rscratch1, 0));
632 } else {
633 add_debug_info_for_branch(info);
634 __ testl(rax, polling_page);
635 }
636 return offset;
637 }
638
639
640 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
641 if (from_reg != to_reg) __ mov(to_reg, from_reg);
642 }
643
644 void LIR_Assembler::swap_reg(Register a, Register b) {
645 __ xchgptr(a, b);
646 }
647
648
649 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
650 assert(src->is_constant(), "should not call otherwise");
651 assert(dest->is_register(), "should not call otherwise");
652 LIR_Const* c = src->as_constant_ptr();
653
654 switch (c->type()) {
655 case T_INT: {
656 assert(patch_code == lir_patch_none, "no patching handled here");
657 __ movl(dest->as_register(), c->as_jint());
658 break;
659 }
660
661 case T_ADDRESS: {
662 assert(patch_code == lir_patch_none, "no patching handled here");
663 __ movptr(dest->as_register(), c->as_jint());
664 break;
665 }
666
667 case T_LONG: {
668 assert(patch_code == lir_patch_none, "no patching handled here");
669 #ifdef _LP64
670 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
671 #else
672 __ movptr(dest->as_register_lo(), c->as_jint_lo());
673 __ movptr(dest->as_register_hi(), c->as_jint_hi());
674 #endif // _LP64
675 break;
676 }
677
678 case T_OBJECT: {
679 if (patch_code != lir_patch_none) {
680 jobject2reg_with_patching(dest->as_register(), info);
681 } else {
682 __ movoop(dest->as_register(), c->as_jobject());
683 }
684 break;
685 }
686
687 case T_METADATA: {
688 if (patch_code != lir_patch_none) {
689 klass2reg_with_patching(dest->as_register(), info);
690 } else {
691 __ mov_metadata(dest->as_register(), c->as_metadata());
692 }
693 break;
694 }
695
696 case T_FLOAT: {
697 if (dest->is_single_xmm()) {
698 if (c->is_zero_float()) {
699 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
700 } else {
701 __ movflt(dest->as_xmm_float_reg(),
702 InternalAddress(float_constant(c->as_jfloat())));
703 }
704 } else {
705 assert(dest->is_single_fpu(), "must be");
706 assert(dest->fpu_regnr() == 0, "dest must be TOS");
707 if (c->is_zero_float()) {
708 __ fldz();
709 } else if (c->is_one_float()) {
710 __ fld1();
711 } else {
712 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
713 }
714 }
715 break;
716 }
717
718 case T_DOUBLE: {
719 if (dest->is_double_xmm()) {
720 if (c->is_zero_double()) {
721 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
722 } else {
723 __ movdbl(dest->as_xmm_double_reg(),
724 InternalAddress(double_constant(c->as_jdouble())));
725 }
726 } else {
727 assert(dest->is_double_fpu(), "must be");
728 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
729 if (c->is_zero_double()) {
730 __ fldz();
731 } else if (c->is_one_double()) {
732 __ fld1();
733 } else {
734 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
735 }
736 }
737 break;
738 }
739
740 default:
741 ShouldNotReachHere();
742 }
743 }
744
745 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
746 assert(src->is_constant(), "should not call otherwise");
747 assert(dest->is_stack(), "should not call otherwise");
748 LIR_Const* c = src->as_constant_ptr();
749
750 switch (c->type()) {
751 case T_INT: // fall through
752 case T_FLOAT:
753 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
754 break;
755
756 case T_ADDRESS:
757 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
758 break;
759
760 case T_OBJECT:
761 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
762 break;
763
764 case T_LONG: // fall through
765 case T_DOUBLE:
766 #ifdef _LP64
767 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
768 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
769 #else
770 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
771 lo_word_offset_in_bytes), c->as_jint_lo_bits());
772 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
773 hi_word_offset_in_bytes), c->as_jint_hi_bits());
774 #endif // _LP64
775 break;
776
777 default:
778 ShouldNotReachHere();
779 }
780 }
781
782 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
783 assert(src->is_constant(), "should not call otherwise");
784 assert(dest->is_address(), "should not call otherwise");
785 LIR_Const* c = src->as_constant_ptr();
786 LIR_Address* addr = dest->as_address_ptr();
787
788 int null_check_here = code_offset();
789 switch (type) {
790 case T_INT: // fall through
791 case T_FLOAT:
792 __ movl(as_Address(addr), c->as_jint_bits());
793 break;
794
795 case T_ADDRESS:
796 __ movptr(as_Address(addr), c->as_jint_bits());
797 break;
798
799 case T_OBJECT: // fall through
800 case T_ARRAY:
801 if (c->as_jobject() == NULL) {
802 if (UseCompressedOops && !wide) {
803 __ movl(as_Address(addr), (int32_t)NULL_WORD);
804 } else {
805 #ifdef _LP64
806 __ xorptr(rscratch1, rscratch1);
807 null_check_here = code_offset();
808 __ movptr(as_Address(addr), rscratch1);
809 #else
810 __ movptr(as_Address(addr), NULL_WORD);
811 #endif
812 }
813 } else {
814 if (is_literal_address(addr)) {
815 ShouldNotReachHere();
816 __ movoop(as_Address(addr, noreg), c->as_jobject());
817 } else {
818 #ifdef _LP64
819 __ movoop(rscratch1, c->as_jobject());
820 if (UseCompressedOops && !wide) {
821 __ encode_heap_oop(rscratch1);
822 null_check_here = code_offset();
823 __ movl(as_Address_lo(addr), rscratch1);
824 } else {
825 null_check_here = code_offset();
826 __ movptr(as_Address_lo(addr), rscratch1);
827 }
828 #else
829 __ movoop(as_Address(addr), c->as_jobject());
830 #endif
831 }
832 }
833 break;
834
835 case T_LONG: // fall through
836 case T_DOUBLE:
837 #ifdef _LP64
838 if (is_literal_address(addr)) {
839 ShouldNotReachHere();
840 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
841 } else {
842 __ movptr(r10, (intptr_t)c->as_jlong_bits());
843 null_check_here = code_offset();
844 __ movptr(as_Address_lo(addr), r10);
845 }
846 #else
847 // Always reachable in 32bit so this doesn't produce useless move literal
848 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
849 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
850 #endif // _LP64
851 break;
852
853 case T_BOOLEAN: // fall through
854 case T_BYTE:
855 __ movb(as_Address(addr), c->as_jint() & 0xFF);
856 break;
857
858 case T_CHAR: // fall through
859 case T_SHORT:
860 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
861 break;
862
863 default:
864 ShouldNotReachHere();
865 };
866
867 if (info != NULL) {
868 add_debug_info_for_null_check(null_check_here, info);
869 }
870 }
871
872
873 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
874 assert(src->is_register(), "should not call otherwise");
875 assert(dest->is_register(), "should not call otherwise");
876
877 // move between cpu-registers
878 if (dest->is_single_cpu()) {
879 #ifdef _LP64
880 if (src->type() == T_LONG) {
881 // Can do LONG -> OBJECT
882 move_regs(src->as_register_lo(), dest->as_register());
883 return;
884 }
885 #endif
886 assert(src->is_single_cpu(), "must match");
887 if (src->type() == T_OBJECT) {
888 __ verify_oop(src->as_register());
889 }
890 move_regs(src->as_register(), dest->as_register());
891
892 } else if (dest->is_double_cpu()) {
893 #ifdef _LP64
894 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
895 // Surprising to me but we can see move of a long to t_object
896 __ verify_oop(src->as_register());
897 move_regs(src->as_register(), dest->as_register_lo());
898 return;
899 }
900 #endif
901 assert(src->is_double_cpu(), "must match");
902 Register f_lo = src->as_register_lo();
903 Register f_hi = src->as_register_hi();
904 Register t_lo = dest->as_register_lo();
905 Register t_hi = dest->as_register_hi();
906 #ifdef _LP64
907 assert(f_hi == f_lo, "must be same");
908 assert(t_hi == t_lo, "must be same");
909 move_regs(f_lo, t_lo);
910 #else
911 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
912
913
914 if (f_lo == t_hi && f_hi == t_lo) {
915 swap_reg(f_lo, f_hi);
916 } else if (f_hi == t_lo) {
917 assert(f_lo != t_hi, "overwriting register");
918 move_regs(f_hi, t_hi);
919 move_regs(f_lo, t_lo);
920 } else {
921 assert(f_hi != t_lo, "overwriting register");
922 move_regs(f_lo, t_lo);
923 move_regs(f_hi, t_hi);
924 }
925 #endif // LP64
926
927 // special moves from fpu-register to xmm-register
928 // necessary for method results
929 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
930 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
931 __ fld_s(Address(rsp, 0));
932 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
933 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
934 __ fld_d(Address(rsp, 0));
935 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
936 __ fstp_s(Address(rsp, 0));
937 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
938 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
939 __ fstp_d(Address(rsp, 0));
940 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
941
942 // move between xmm-registers
943 } else if (dest->is_single_xmm()) {
944 assert(src->is_single_xmm(), "must match");
945 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
946 } else if (dest->is_double_xmm()) {
947 assert(src->is_double_xmm(), "must match");
948 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
949
950 // move between fpu-registers (no instruction necessary because of fpu-stack)
951 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
952 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
953 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
954 } else {
955 ShouldNotReachHere();
956 }
957 }
958
959 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
960 assert(src->is_register(), "should not call otherwise");
961 assert(dest->is_stack(), "should not call otherwise");
962
963 if (src->is_single_cpu()) {
964 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
965 if (type == T_OBJECT || type == T_ARRAY) {
966 __ verify_oop(src->as_register());
967 __ movptr (dst, src->as_register());
968 } else if (type == T_METADATA) {
969 __ movptr (dst, src->as_register());
970 } else {
971 __ movl (dst, src->as_register());
972 }
973
974 } else if (src->is_double_cpu()) {
975 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
976 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
977 __ movptr (dstLO, src->as_register_lo());
978 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
979
980 } else if (src->is_single_xmm()) {
981 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
982 __ movflt(dst_addr, src->as_xmm_float_reg());
983
984 } else if (src->is_double_xmm()) {
985 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
986 __ movdbl(dst_addr, src->as_xmm_double_reg());
987
988 } else if (src->is_single_fpu()) {
989 assert(src->fpu_regnr() == 0, "argument must be on TOS");
990 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
991 if (pop_fpu_stack) __ fstp_s (dst_addr);
992 else __ fst_s (dst_addr);
993
994 } else if (src->is_double_fpu()) {
995 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
996 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
997 if (pop_fpu_stack) __ fstp_d (dst_addr);
998 else __ fst_d (dst_addr);
999
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005
1006 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
1007 LIR_Address* to_addr = dest->as_address_ptr();
1008 PatchingStub* patch = NULL;
1009 Register compressed_src = rscratch1;
1010
1011 if (type == T_ARRAY || type == T_OBJECT) {
1012 __ verify_oop(src->as_register());
1013 #ifdef _LP64
1014 if (UseCompressedOops && !wide) {
1015 __ movptr(compressed_src, src->as_register());
1016 __ encode_heap_oop(compressed_src);
1017 if (patch_code != lir_patch_none) {
1018 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1019 }
1020 }
1021 #endif
1022 }
1023
1024 if (patch_code != lir_patch_none) {
1025 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1026 Address toa = as_Address(to_addr);
1027 assert(toa.disp() != 0, "must have");
1028 }
1029
1030 int null_check_here = code_offset();
1031 switch (type) {
1032 case T_FLOAT: {
1033 if (src->is_single_xmm()) {
1034 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1035 } else {
1036 assert(src->is_single_fpu(), "must be");
1037 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1038 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1039 else __ fst_s (as_Address(to_addr));
1040 }
1041 break;
1042 }
1043
1044 case T_DOUBLE: {
1045 if (src->is_double_xmm()) {
1046 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1047 } else {
1048 assert(src->is_double_fpu(), "must be");
1049 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1050 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1051 else __ fst_d (as_Address(to_addr));
1052 }
1053 break;
1054 }
1055
1056 case T_ARRAY: // fall through
1057 case T_OBJECT: // fall through
1058 if (UseCompressedOops && !wide) {
1059 __ movl(as_Address(to_addr), compressed_src);
1060 } else {
1061 __ movptr(as_Address(to_addr), src->as_register());
1062 }
1063 break;
1064 case T_METADATA:
1065 // We get here to store a method pointer to the stack to pass to
1066 // a dtrace runtime call. This can't work on 64 bit with
1067 // compressed klass ptrs: T_METADATA can be a compressed klass
1068 // ptr or a 64 bit method pointer.
1069 LP64_ONLY(ShouldNotReachHere());
1070 __ movptr(as_Address(to_addr), src->as_register());
1071 break;
1072 case T_ADDRESS:
1073 __ movptr(as_Address(to_addr), src->as_register());
1074 break;
1075 case T_INT:
1076 __ movl(as_Address(to_addr), src->as_register());
1077 break;
1078
1079 case T_LONG: {
1080 Register from_lo = src->as_register_lo();
1081 Register from_hi = src->as_register_hi();
1082 #ifdef _LP64
1083 __ movptr(as_Address_lo(to_addr), from_lo);
1084 #else
1085 Register base = to_addr->base()->as_register();
1086 Register index = noreg;
1087 if (to_addr->index()->is_register()) {
1088 index = to_addr->index()->as_register();
1089 }
1090 if (base == from_lo || index == from_lo) {
1091 assert(base != from_hi, "can't be");
1092 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1093 __ movl(as_Address_hi(to_addr), from_hi);
1094 if (patch != NULL) {
1095 patching_epilog(patch, lir_patch_high, base, info);
1096 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1097 patch_code = lir_patch_low;
1098 }
1099 __ movl(as_Address_lo(to_addr), from_lo);
1100 } else {
1101 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1102 __ movl(as_Address_lo(to_addr), from_lo);
1103 if (patch != NULL) {
1104 patching_epilog(patch, lir_patch_low, base, info);
1105 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1106 patch_code = lir_patch_high;
1107 }
1108 __ movl(as_Address_hi(to_addr), from_hi);
1109 }
1110 #endif // _LP64
1111 break;
1112 }
1113
1114 case T_BYTE: // fall through
1115 case T_BOOLEAN: {
1116 Register src_reg = src->as_register();
1117 Address dst_addr = as_Address(to_addr);
1118 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1119 __ movb(dst_addr, src_reg);
1120 break;
1121 }
1122
1123 case T_CHAR: // fall through
1124 case T_SHORT:
1125 __ movw(as_Address(to_addr), src->as_register());
1126 break;
1127
1128 default:
1129 ShouldNotReachHere();
1130 }
1131 if (info != NULL) {
1132 add_debug_info_for_null_check(null_check_here, info);
1133 }
1134
1135 if (patch_code != lir_patch_none) {
1136 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1137 }
1138 }
1139
1140
1141 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1142 assert(src->is_stack(), "should not call otherwise");
1143 assert(dest->is_register(), "should not call otherwise");
1144
1145 if (dest->is_single_cpu()) {
1146 if (type == T_ARRAY || type == T_OBJECT) {
1147 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1148 __ verify_oop(dest->as_register());
1149 } else if (type == T_METADATA) {
1150 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1151 } else {
1152 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1153 }
1154
1155 } else if (dest->is_double_cpu()) {
1156 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1157 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1158 __ movptr(dest->as_register_lo(), src_addr_LO);
1159 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1160
1161 } else if (dest->is_single_xmm()) {
1162 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1163 __ movflt(dest->as_xmm_float_reg(), src_addr);
1164
1165 } else if (dest->is_double_xmm()) {
1166 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1167 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1168
1169 } else if (dest->is_single_fpu()) {
1170 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1171 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1172 __ fld_s(src_addr);
1173
1174 } else if (dest->is_double_fpu()) {
1175 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1176 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1177 __ fld_d(src_addr);
1178
1179 } else {
1180 ShouldNotReachHere();
1181 }
1182 }
1183
1184
1185 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1186 if (src->is_single_stack()) {
1187 if (type == T_OBJECT || type == T_ARRAY) {
1188 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1189 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1190 } else {
1191 #ifndef _LP64
1192 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1193 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1194 #else
1195 //no pushl on 64bits
1196 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1197 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1198 #endif
1199 }
1200
1201 } else if (src->is_double_stack()) {
1202 #ifdef _LP64
1203 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1204 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1205 #else
1206 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1207 // push and pop the part at src + wordSize, adding wordSize for the previous push
1208 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1209 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1210 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1211 #endif // _LP64
1212
1213 } else {
1214 ShouldNotReachHere();
1215 }
1216 }
1217
1218
1219 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1220 assert(src->is_address(), "should not call otherwise");
1221 assert(dest->is_register(), "should not call otherwise");
1222
1223 LIR_Address* addr = src->as_address_ptr();
1224 Address from_addr = as_Address(addr);
1225
1226 if (addr->base()->type() == T_OBJECT) {
1227 __ verify_oop(addr->base()->as_pointer_register());
1228 }
1229
1230 switch (type) {
1231 case T_BOOLEAN: // fall through
1232 case T_BYTE: // fall through
1233 case T_CHAR: // fall through
1234 case T_SHORT:
1235 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1236 // on pre P6 processors we may get partial register stalls
1237 // so blow away the value of to_rinfo before loading a
1238 // partial word into it. Do it here so that it precedes
1239 // the potential patch point below.
1240 __ xorptr(dest->as_register(), dest->as_register());
1241 }
1242 break;
1243 }
1244
1245 PatchingStub* patch = NULL;
1246 if (patch_code != lir_patch_none) {
1247 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1248 assert(from_addr.disp() != 0, "must have");
1249 }
1250 if (info != NULL) {
1251 add_debug_info_for_null_check_here(info);
1252 }
1253
1254 switch (type) {
1255 case T_FLOAT: {
1256 if (dest->is_single_xmm()) {
1257 __ movflt(dest->as_xmm_float_reg(), from_addr);
1258 } else {
1259 assert(dest->is_single_fpu(), "must be");
1260 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1261 __ fld_s(from_addr);
1262 }
1263 break;
1264 }
1265
1266 case T_DOUBLE: {
1267 if (dest->is_double_xmm()) {
1268 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1269 } else {
1270 assert(dest->is_double_fpu(), "must be");
1271 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1272 __ fld_d(from_addr);
1273 }
1274 break;
1275 }
1276
1277 case T_OBJECT: // fall through
1278 case T_ARRAY: // fall through
1279 if (UseCompressedOops && !wide) {
1280 __ movl(dest->as_register(), from_addr);
1281 } else {
1282 __ movptr(dest->as_register(), from_addr);
1283 }
1284 break;
1285
1286 case T_ADDRESS:
1287 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1288 __ movl(dest->as_register(), from_addr);
1289 } else {
1290 __ movptr(dest->as_register(), from_addr);
1291 }
1292 break;
1293 case T_INT:
1294 __ movl(dest->as_register(), from_addr);
1295 break;
1296
1297 case T_LONG: {
1298 Register to_lo = dest->as_register_lo();
1299 Register to_hi = dest->as_register_hi();
1300 #ifdef _LP64
1301 __ movptr(to_lo, as_Address_lo(addr));
1302 #else
1303 Register base = addr->base()->as_register();
1304 Register index = noreg;
1305 if (addr->index()->is_register()) {
1306 index = addr->index()->as_register();
1307 }
1308 if ((base == to_lo && index == to_hi) ||
1309 (base == to_hi && index == to_lo)) {
1310 // addresses with 2 registers are only formed as a result of
1311 // array access so this code will never have to deal with
1312 // patches or null checks.
1313 assert(info == NULL && patch == NULL, "must be");
1314 __ lea(to_hi, as_Address(addr));
1315 __ movl(to_lo, Address(to_hi, 0));
1316 __ movl(to_hi, Address(to_hi, BytesPerWord));
1317 } else if (base == to_lo || index == to_lo) {
1318 assert(base != to_hi, "can't be");
1319 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1320 __ movl(to_hi, as_Address_hi(addr));
1321 if (patch != NULL) {
1322 patching_epilog(patch, lir_patch_high, base, info);
1323 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1324 patch_code = lir_patch_low;
1325 }
1326 __ movl(to_lo, as_Address_lo(addr));
1327 } else {
1328 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1329 __ movl(to_lo, as_Address_lo(addr));
1330 if (patch != NULL) {
1331 patching_epilog(patch, lir_patch_low, base, info);
1332 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1333 patch_code = lir_patch_high;
1334 }
1335 __ movl(to_hi, as_Address_hi(addr));
1336 }
1337 #endif // _LP64
1338 break;
1339 }
1340
1341 case T_BOOLEAN: // fall through
1342 case T_BYTE: {
1343 Register dest_reg = dest->as_register();
1344 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1345 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1346 __ movsbl(dest_reg, from_addr);
1347 } else {
1348 __ movb(dest_reg, from_addr);
1349 __ shll(dest_reg, 24);
1350 __ sarl(dest_reg, 24);
1351 }
1352 break;
1353 }
1354
1355 case T_CHAR: {
1356 Register dest_reg = dest->as_register();
1357 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1358 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1359 __ movzwl(dest_reg, from_addr);
1360 } else {
1361 __ movw(dest_reg, from_addr);
1362 }
1363 break;
1364 }
1365
1366 case T_SHORT: {
1367 Register dest_reg = dest->as_register();
1368 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1369 __ movswl(dest_reg, from_addr);
1370 } else {
1371 __ movw(dest_reg, from_addr);
1372 __ shll(dest_reg, 16);
1373 __ sarl(dest_reg, 16);
1374 }
1375 break;
1376 }
1377
1378 default:
1379 ShouldNotReachHere();
1380 }
1381
1382 if (patch != NULL) {
1383 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1384 }
1385
1386 if (type == T_ARRAY || type == T_OBJECT) {
1387 #ifdef _LP64
1388 if (UseCompressedOops && !wide) {
1389 __ decode_heap_oop(dest->as_register());
1390 }
1391 #endif
1392 __ verify_oop(dest->as_register());
1393 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1394 #ifdef _LP64
1395 if (UseCompressedClassPointers) {
1396 __ decode_klass_not_null(dest->as_register());
1397 }
1398 #endif
1399 }
1400 }
1401
1402
1403 NEEDS_CLEANUP; // This could be static?
1404 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1405 int elem_size = type2aelembytes(type);
1406 switch (elem_size) {
1407 case 1: return Address::times_1;
1408 case 2: return Address::times_2;
1409 case 4: return Address::times_4;
1410 case 8: return Address::times_8;
1411 }
1412 ShouldNotReachHere();
1413 return Address::no_scale;
1414 }
1415
1416
1417 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1418 switch (op->code()) {
1419 case lir_idiv:
1420 case lir_irem:
1421 arithmetic_idiv(op->code(),
1422 op->in_opr1(),
1423 op->in_opr2(),
1424 op->in_opr3(),
1425 op->result_opr(),
1426 op->info());
1427 break;
1428 default: ShouldNotReachHere(); break;
1429 }
1430 }
1431
1432 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1433 #ifdef ASSERT
1434 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1435 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1436 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1437 #endif
1438
1439 if (op->cond() == lir_cond_always) {
1440 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1441 __ jmp (*(op->label()));
1442 } else {
1443 Assembler::Condition acond = Assembler::zero;
1444 if (op->code() == lir_cond_float_branch) {
1445 assert(op->ublock() != NULL, "must have unordered successor");
1446 __ jcc(Assembler::parity, *(op->ublock()->label()));
1447 switch(op->cond()) {
1448 case lir_cond_equal: acond = Assembler::equal; break;
1449 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1450 case lir_cond_less: acond = Assembler::below; break;
1451 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1452 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1453 case lir_cond_greater: acond = Assembler::above; break;
1454 default: ShouldNotReachHere();
1455 }
1456 } else {
1457 switch (op->cond()) {
1458 case lir_cond_equal: acond = Assembler::equal; break;
1459 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1460 case lir_cond_less: acond = Assembler::less; break;
1461 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1462 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1463 case lir_cond_greater: acond = Assembler::greater; break;
1464 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1465 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1466 default: ShouldNotReachHere();
1467 }
1468 }
1469 __ jcc(acond,*(op->label()));
1470 }
1471 }
1472
1473 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1474 LIR_Opr src = op->in_opr();
1475 LIR_Opr dest = op->result_opr();
1476
1477 switch (op->bytecode()) {
1478 case Bytecodes::_i2l:
1479 #ifdef _LP64
1480 __ movl2ptr(dest->as_register_lo(), src->as_register());
1481 #else
1482 move_regs(src->as_register(), dest->as_register_lo());
1483 move_regs(src->as_register(), dest->as_register_hi());
1484 __ sarl(dest->as_register_hi(), 31);
1485 #endif // LP64
1486 break;
1487
1488 case Bytecodes::_l2i:
1489 #ifdef _LP64
1490 __ movl(dest->as_register(), src->as_register_lo());
1491 #else
1492 move_regs(src->as_register_lo(), dest->as_register());
1493 #endif
1494 break;
1495
1496 case Bytecodes::_i2b:
1497 move_regs(src->as_register(), dest->as_register());
1498 __ sign_extend_byte(dest->as_register());
1499 break;
1500
1501 case Bytecodes::_i2c:
1502 move_regs(src->as_register(), dest->as_register());
1503 __ andl(dest->as_register(), 0xFFFF);
1504 break;
1505
1506 case Bytecodes::_i2s:
1507 move_regs(src->as_register(), dest->as_register());
1508 __ sign_extend_short(dest->as_register());
1509 break;
1510
1511
1512 case Bytecodes::_f2d:
1513 case Bytecodes::_d2f:
1514 if (dest->is_single_xmm()) {
1515 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1516 } else if (dest->is_double_xmm()) {
1517 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1518 } else {
1519 assert(src->fpu() == dest->fpu(), "register must be equal");
1520 // do nothing (float result is rounded later through spilling)
1521 }
1522 break;
1523
1524 case Bytecodes::_i2f:
1525 case Bytecodes::_i2d:
1526 if (dest->is_single_xmm()) {
1527 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1528 } else if (dest->is_double_xmm()) {
1529 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1530 } else {
1531 assert(dest->fpu() == 0, "result must be on TOS");
1532 __ movl(Address(rsp, 0), src->as_register());
1533 __ fild_s(Address(rsp, 0));
1534 }
1535 break;
1536
1537 case Bytecodes::_f2i:
1538 case Bytecodes::_d2i:
1539 if (src->is_single_xmm()) {
1540 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1541 } else if (src->is_double_xmm()) {
1542 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1543 } else {
1544 assert(src->fpu() == 0, "input must be on TOS");
1545 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1546 __ fist_s(Address(rsp, 0));
1547 __ movl(dest->as_register(), Address(rsp, 0));
1548 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1549 }
1550
1551 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1552 assert(op->stub() != NULL, "stub required");
1553 __ cmpl(dest->as_register(), 0x80000000);
1554 __ jcc(Assembler::equal, *op->stub()->entry());
1555 __ bind(*op->stub()->continuation());
1556 break;
1557
1558 case Bytecodes::_l2f:
1559 case Bytecodes::_l2d:
1560 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1561 assert(dest->fpu() == 0, "result must be on TOS");
1562
1563 __ movptr(Address(rsp, 0), src->as_register_lo());
1564 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1565 __ fild_d(Address(rsp, 0));
1566 // float result is rounded later through spilling
1567 break;
1568
1569 case Bytecodes::_f2l:
1570 case Bytecodes::_d2l:
1571 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1572 assert(src->fpu() == 0, "input must be on TOS");
1573 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1574
1575 // instruction sequence too long to inline it here
1576 {
1577 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1578 }
1579 break;
1580
1581 default: ShouldNotReachHere();
1582 }
1583 }
1584
1585 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1586 if (op->init_check()) {
1587 __ cmpb(Address(op->klass()->as_register(),
1588 InstanceKlass::init_state_offset()),
1589 InstanceKlass::fully_initialized);
1590 add_debug_info_for_null_check_here(op->stub()->info());
1591 __ jcc(Assembler::notEqual, *op->stub()->entry());
1592 }
1593 __ allocate_object(op->obj()->as_register(),
1594 op->tmp1()->as_register(),
1595 op->tmp2()->as_register(),
1596 op->header_size(),
1597 op->object_size(),
1598 op->klass()->as_register(),
1599 *op->stub()->entry());
1600 __ bind(*op->stub()->continuation());
1601 }
1602
1603 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1604 Register len = op->len()->as_register();
1605 LP64_ONLY( __ movslq(len, len); )
1606
1607 if (UseSlowPath ||
1608 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1609 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1610 __ jmp(*op->stub()->entry());
1611 } else {
1612 Register tmp1 = op->tmp1()->as_register();
1613 Register tmp2 = op->tmp2()->as_register();
1614 Register tmp3 = op->tmp3()->as_register();
1615 if (len == tmp1) {
1616 tmp1 = tmp3;
1617 } else if (len == tmp2) {
1618 tmp2 = tmp3;
1619 } else if (len == tmp3) {
1620 // everything is ok
1621 } else {
1622 __ mov(tmp3, len);
1623 }
1624 __ allocate_array(op->obj()->as_register(),
1625 len,
1626 tmp1,
1627 tmp2,
1628 arrayOopDesc::header_size(op->type()),
1629 array_element_size(op->type()),
1630 op->klass()->as_register(),
1631 *op->stub()->entry());
1632 }
1633 __ bind(*op->stub()->continuation());
1634 }
1635
1636 void LIR_Assembler::type_profile_helper(Register mdo,
1637 ciMethodData *md, ciProfileData *data,
1638 Register recv, Label* update_done) {
1639 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1640 Label next_test;
1641 // See if the receiver is receiver[n].
1642 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1643 __ jccb(Assembler::notEqual, next_test);
1644 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1645 __ addptr(data_addr, DataLayout::counter_increment);
1646 __ jmp(*update_done);
1647 __ bind(next_test);
1648 }
1649
1650 // Didn't find receiver; find next empty slot and fill it in
1651 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1652 Label next_test;
1653 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1654 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1655 __ jccb(Assembler::notEqual, next_test);
1656 __ movptr(recv_addr, recv);
1657 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1658 __ jmp(*update_done);
1659 __ bind(next_test);
1660 }
1661 }
1662
1663 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1664 // we always need a stub for the failure case.
1665 CodeStub* stub = op->stub();
1666 Register obj = op->object()->as_register();
1667 Register k_RInfo = op->tmp1()->as_register();
1668 Register klass_RInfo = op->tmp2()->as_register();
1669 Register dst = op->result_opr()->as_register();
1670 ciKlass* k = op->klass();
1671 Register Rtmp1 = noreg;
1672
1673 // check if it needs to be profiled
1674 ciMethodData* md;
1675 ciProfileData* data;
1676
1677 if (op->should_profile()) {
1678 ciMethod* method = op->profiled_method();
1679 assert(method != NULL, "Should have method");
1680 int bci = op->profiled_bci();
1681 md = method->method_data_or_null();
1682 assert(md != NULL, "Sanity");
1683 data = md->bci_to_data(bci);
1684 assert(data != NULL, "need data for type check");
1685 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1686 }
1687 Label profile_cast_success, profile_cast_failure;
1688 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1689 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1690
1691 if (obj == k_RInfo) {
1692 k_RInfo = dst;
1693 } else if (obj == klass_RInfo) {
1694 klass_RInfo = dst;
1695 }
1696 if (k->is_loaded() && !UseCompressedClassPointers) {
1697 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1698 } else {
1699 Rtmp1 = op->tmp3()->as_register();
1700 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1701 }
1702
1703 assert_different_registers(obj, k_RInfo, klass_RInfo);
1704
1705 __ cmpptr(obj, (int32_t)NULL_WORD);
1706 if (op->should_profile()) {
1707 Label not_null;
1708 __ jccb(Assembler::notEqual, not_null);
1709 // Object is null; update MDO and exit
1710 Register mdo = klass_RInfo;
1711 __ mov_metadata(mdo, md->constant_encoding());
1712 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1713 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1714 __ orl(data_addr, header_bits);
1715 __ jmp(*obj_is_null);
1716 __ bind(not_null);
1717 } else {
1718 __ jcc(Assembler::equal, *obj_is_null);
1719 }
1720
1721 if (!k->is_loaded()) {
1722 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1723 } else {
1724 #ifdef _LP64
1725 __ mov_metadata(k_RInfo, k->constant_encoding());
1726 #endif // _LP64
1727 }
1728 __ verify_oop(obj);
1729
1730 if (op->fast_check()) {
1731 // get object class
1732 // not a safepoint as obj null check happens earlier
1733 #ifdef _LP64
1734 if (UseCompressedClassPointers) {
1735 __ load_klass(Rtmp1, obj);
1736 __ cmpptr(k_RInfo, Rtmp1);
1737 } else {
1738 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1739 }
1740 #else
1741 if (k->is_loaded()) {
1742 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1743 } else {
1744 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1745 }
1746 #endif
1747 __ jcc(Assembler::notEqual, *failure_target);
1748 // successful cast, fall through to profile or jump
1749 } else {
1750 // get object class
1751 // not a safepoint as obj null check happens earlier
1752 __ load_klass(klass_RInfo, obj);
1753 if (k->is_loaded()) {
1754 // See if we get an immediate positive hit
1755 #ifdef _LP64
1756 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1757 #else
1758 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1759 #endif // _LP64
1760 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1761 __ jcc(Assembler::notEqual, *failure_target);
1762 // successful cast, fall through to profile or jump
1763 } else {
1764 // See if we get an immediate positive hit
1765 __ jcc(Assembler::equal, *success_target);
1766 // check for self
1767 #ifdef _LP64
1768 __ cmpptr(klass_RInfo, k_RInfo);
1769 #else
1770 __ cmpklass(klass_RInfo, k->constant_encoding());
1771 #endif // _LP64
1772 __ jcc(Assembler::equal, *success_target);
1773
1774 __ push(klass_RInfo);
1775 #ifdef _LP64
1776 __ push(k_RInfo);
1777 #else
1778 __ pushklass(k->constant_encoding());
1779 #endif // _LP64
1780 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1781 __ pop(klass_RInfo);
1782 __ pop(klass_RInfo);
1783 // result is a boolean
1784 __ cmpl(klass_RInfo, 0);
1785 __ jcc(Assembler::equal, *failure_target);
1786 // successful cast, fall through to profile or jump
1787 }
1788 } else {
1789 // perform the fast part of the checking logic
1790 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1791 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1792 __ push(klass_RInfo);
1793 __ push(k_RInfo);
1794 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1795 __ pop(klass_RInfo);
1796 __ pop(k_RInfo);
1797 // result is a boolean
1798 __ cmpl(k_RInfo, 0);
1799 __ jcc(Assembler::equal, *failure_target);
1800 // successful cast, fall through to profile or jump
1801 }
1802 }
1803 if (op->should_profile()) {
1804 Register mdo = klass_RInfo, recv = k_RInfo;
1805 __ bind(profile_cast_success);
1806 __ mov_metadata(mdo, md->constant_encoding());
1807 __ load_klass(recv, obj);
1808 Label update_done;
1809 type_profile_helper(mdo, md, data, recv, success);
1810 __ jmp(*success);
1811
1812 __ bind(profile_cast_failure);
1813 __ mov_metadata(mdo, md->constant_encoding());
1814 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1815 __ subptr(counter_addr, DataLayout::counter_increment);
1816 __ jmp(*failure);
1817 }
1818 __ jmp(*success);
1819 }
1820
1821
1822 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1823 LIR_Code code = op->code();
1824 if (code == lir_store_check) {
1825 Register value = op->object()->as_register();
1826 Register array = op->array()->as_register();
1827 Register k_RInfo = op->tmp1()->as_register();
1828 Register klass_RInfo = op->tmp2()->as_register();
1829 Register Rtmp1 = op->tmp3()->as_register();
1830
1831 CodeStub* stub = op->stub();
1832
1833 // check if it needs to be profiled
1834 ciMethodData* md;
1835 ciProfileData* data;
1836
1837 if (op->should_profile()) {
1838 ciMethod* method = op->profiled_method();
1839 assert(method != NULL, "Should have method");
1840 int bci = op->profiled_bci();
1841 md = method->method_data_or_null();
1842 assert(md != NULL, "Sanity");
1843 data = md->bci_to_data(bci);
1844 assert(data != NULL, "need data for type check");
1845 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1846 }
1847 Label profile_cast_success, profile_cast_failure, done;
1848 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1849 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1850
1851 __ cmpptr(value, (int32_t)NULL_WORD);
1852 if (op->should_profile()) {
1853 Label not_null;
1854 __ jccb(Assembler::notEqual, not_null);
1855 // Object is null; update MDO and exit
1856 Register mdo = klass_RInfo;
1857 __ mov_metadata(mdo, md->constant_encoding());
1858 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1859 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1860 __ orl(data_addr, header_bits);
1861 __ jmp(done);
1862 __ bind(not_null);
1863 } else {
1864 __ jcc(Assembler::equal, done);
1865 }
1866
1867 add_debug_info_for_null_check_here(op->info_for_exception());
1868 __ load_klass(k_RInfo, array);
1869 __ load_klass(klass_RInfo, value);
1870
1871 // get instance klass (it's already uncompressed)
1872 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1873 // perform the fast part of the checking logic
1874 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1875 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1876 __ push(klass_RInfo);
1877 __ push(k_RInfo);
1878 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1879 __ pop(klass_RInfo);
1880 __ pop(k_RInfo);
1881 // result is a boolean
1882 __ cmpl(k_RInfo, 0);
1883 __ jcc(Assembler::equal, *failure_target);
1884 // fall through to the success case
1885
1886 if (op->should_profile()) {
1887 Register mdo = klass_RInfo, recv = k_RInfo;
1888 __ bind(profile_cast_success);
1889 __ mov_metadata(mdo, md->constant_encoding());
1890 __ load_klass(recv, value);
1891 Label update_done;
1892 type_profile_helper(mdo, md, data, recv, &done);
1893 __ jmpb(done);
1894
1895 __ bind(profile_cast_failure);
1896 __ mov_metadata(mdo, md->constant_encoding());
1897 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1898 __ subptr(counter_addr, DataLayout::counter_increment);
1899 __ jmp(*stub->entry());
1900 }
1901
1902 __ bind(done);
1903 } else
1904 if (code == lir_checkcast) {
1905 Register obj = op->object()->as_register();
1906 Register dst = op->result_opr()->as_register();
1907 Label success;
1908 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1909 __ bind(success);
1910 if (dst != obj) {
1911 __ mov(dst, obj);
1912 }
1913 } else
1914 if (code == lir_instanceof) {
1915 Register obj = op->object()->as_register();
1916 Register dst = op->result_opr()->as_register();
1917 Label success, failure, done;
1918 emit_typecheck_helper(op, &success, &failure, &failure);
1919 __ bind(failure);
1920 __ xorptr(dst, dst);
1921 __ jmpb(done);
1922 __ bind(success);
1923 __ movptr(dst, 1);
1924 __ bind(done);
1925 } else {
1926 ShouldNotReachHere();
1927 }
1928
1929 }
1930
1931
1932 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1933 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1934 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1935 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1936 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1937 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1938 Register addr = op->addr()->as_register();
1939 if (os::is_MP()) {
1940 __ lock();
1941 }
1942 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1943
1944 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1945 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1946 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1947 Register newval = op->new_value()->as_register();
1948 Register cmpval = op->cmp_value()->as_register();
1949 assert(cmpval == rax, "wrong register");
1950 assert(newval != NULL, "new val must be register");
1951 assert(cmpval != newval, "cmp and new values must be in different registers");
1952 assert(cmpval != addr, "cmp and addr must be in different registers");
1953 assert(newval != addr, "new value and addr must be in different registers");
1954
1955 if ( op->code() == lir_cas_obj) {
1956 #ifdef _LP64
1957 if (UseCompressedOops) {
1958 __ encode_heap_oop(cmpval);
1959 __ mov(rscratch1, newval);
1960 __ encode_heap_oop(rscratch1);
1961 if (os::is_MP()) {
1962 __ lock();
1963 }
1964 // cmpval (rax) is implicitly used by this instruction
1965 __ cmpxchgl(rscratch1, Address(addr, 0));
1966 } else
1967 #endif
1968 {
1969 if (os::is_MP()) {
1970 __ lock();
1971 }
1972 __ cmpxchgptr(newval, Address(addr, 0));
1973 }
1974 } else {
1975 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1976 if (os::is_MP()) {
1977 __ lock();
1978 }
1979 __ cmpxchgl(newval, Address(addr, 0));
1980 }
1981 #ifdef _LP64
1982 } else if (op->code() == lir_cas_long) {
1983 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1984 Register newval = op->new_value()->as_register_lo();
1985 Register cmpval = op->cmp_value()->as_register_lo();
1986 assert(cmpval == rax, "wrong register");
1987 assert(newval != NULL, "new val must be register");
1988 assert(cmpval != newval, "cmp and new values must be in different registers");
1989 assert(cmpval != addr, "cmp and addr must be in different registers");
1990 assert(newval != addr, "new value and addr must be in different registers");
1991 if (os::is_MP()) {
1992 __ lock();
1993 }
1994 __ cmpxchgq(newval, Address(addr, 0));
1995 #endif // _LP64
1996 } else {
1997 Unimplemented();
1998 }
1999 }
2000
2001 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2002 Assembler::Condition acond, ncond;
2003 switch (condition) {
2004 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2005 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2006 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2007 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2008 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2009 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2010 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2011 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2012 default: ShouldNotReachHere();
2013 }
2014
2015 if (opr1->is_cpu_register()) {
2016 reg2reg(opr1, result);
2017 } else if (opr1->is_stack()) {
2018 stack2reg(opr1, result, result->type());
2019 } else if (opr1->is_constant()) {
2020 const2reg(opr1, result, lir_patch_none, NULL);
2021 } else {
2022 ShouldNotReachHere();
2023 }
2024
2025 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2026 // optimized version that does not require a branch
2027 if (opr2->is_single_cpu()) {
2028 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2029 __ cmov(ncond, result->as_register(), opr2->as_register());
2030 } else if (opr2->is_double_cpu()) {
2031 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2032 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2033 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2034 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2035 } else if (opr2->is_single_stack()) {
2036 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2037 } else if (opr2->is_double_stack()) {
2038 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2039 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2040 } else {
2041 ShouldNotReachHere();
2042 }
2043
2044 } else {
2045 Label skip;
2046 __ jcc (acond, skip);
2047 if (opr2->is_cpu_register()) {
2048 reg2reg(opr2, result);
2049 } else if (opr2->is_stack()) {
2050 stack2reg(opr2, result, result->type());
2051 } else if (opr2->is_constant()) {
2052 const2reg(opr2, result, lir_patch_none, NULL);
2053 } else {
2054 ShouldNotReachHere();
2055 }
2056 __ bind(skip);
2057 }
2058 }
2059
2060
2061 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2062 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2063
2064 if (left->is_single_cpu()) {
2065 assert(left == dest, "left and dest must be equal");
2066 Register lreg = left->as_register();
2067
2068 if (right->is_single_cpu()) {
2069 // cpu register - cpu register
2070 Register rreg = right->as_register();
2071 switch (code) {
2072 case lir_add: __ addl (lreg, rreg); break;
2073 case lir_sub: __ subl (lreg, rreg); break;
2074 case lir_mul: __ imull(lreg, rreg); break;
2075 default: ShouldNotReachHere();
2076 }
2077
2078 } else if (right->is_stack()) {
2079 // cpu register - stack
2080 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2081 switch (code) {
2082 case lir_add: __ addl(lreg, raddr); break;
2083 case lir_sub: __ subl(lreg, raddr); break;
2084 default: ShouldNotReachHere();
2085 }
2086
2087 } else if (right->is_constant()) {
2088 // cpu register - constant
2089 jint c = right->as_constant_ptr()->as_jint();
2090 switch (code) {
2091 case lir_add: {
2092 __ incrementl(lreg, c);
2093 break;
2094 }
2095 case lir_sub: {
2096 __ decrementl(lreg, c);
2097 break;
2098 }
2099 default: ShouldNotReachHere();
2100 }
2101
2102 } else {
2103 ShouldNotReachHere();
2104 }
2105
2106 } else if (left->is_double_cpu()) {
2107 assert(left == dest, "left and dest must be equal");
2108 Register lreg_lo = left->as_register_lo();
2109 Register lreg_hi = left->as_register_hi();
2110
2111 if (right->is_double_cpu()) {
2112 // cpu register - cpu register
2113 Register rreg_lo = right->as_register_lo();
2114 Register rreg_hi = right->as_register_hi();
2115 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2116 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2117 switch (code) {
2118 case lir_add:
2119 __ addptr(lreg_lo, rreg_lo);
2120 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2121 break;
2122 case lir_sub:
2123 __ subptr(lreg_lo, rreg_lo);
2124 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2125 break;
2126 case lir_mul:
2127 #ifdef _LP64
2128 __ imulq(lreg_lo, rreg_lo);
2129 #else
2130 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2131 __ imull(lreg_hi, rreg_lo);
2132 __ imull(rreg_hi, lreg_lo);
2133 __ addl (rreg_hi, lreg_hi);
2134 __ mull (rreg_lo);
2135 __ addl (lreg_hi, rreg_hi);
2136 #endif // _LP64
2137 break;
2138 default:
2139 ShouldNotReachHere();
2140 }
2141
2142 } else if (right->is_constant()) {
2143 // cpu register - constant
2144 #ifdef _LP64
2145 jlong c = right->as_constant_ptr()->as_jlong_bits();
2146 __ movptr(r10, (intptr_t) c);
2147 switch (code) {
2148 case lir_add:
2149 __ addptr(lreg_lo, r10);
2150 break;
2151 case lir_sub:
2152 __ subptr(lreg_lo, r10);
2153 break;
2154 default:
2155 ShouldNotReachHere();
2156 }
2157 #else
2158 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2159 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2160 switch (code) {
2161 case lir_add:
2162 __ addptr(lreg_lo, c_lo);
2163 __ adcl(lreg_hi, c_hi);
2164 break;
2165 case lir_sub:
2166 __ subptr(lreg_lo, c_lo);
2167 __ sbbl(lreg_hi, c_hi);
2168 break;
2169 default:
2170 ShouldNotReachHere();
2171 }
2172 #endif // _LP64
2173
2174 } else {
2175 ShouldNotReachHere();
2176 }
2177
2178 } else if (left->is_single_xmm()) {
2179 assert(left == dest, "left and dest must be equal");
2180 XMMRegister lreg = left->as_xmm_float_reg();
2181
2182 if (right->is_single_xmm()) {
2183 XMMRegister rreg = right->as_xmm_float_reg();
2184 switch (code) {
2185 case lir_add: __ addss(lreg, rreg); break;
2186 case lir_sub: __ subss(lreg, rreg); break;
2187 case lir_mul_strictfp: // fall through
2188 case lir_mul: __ mulss(lreg, rreg); break;
2189 case lir_div_strictfp: // fall through
2190 case lir_div: __ divss(lreg, rreg); break;
2191 default: ShouldNotReachHere();
2192 }
2193 } else {
2194 Address raddr;
2195 if (right->is_single_stack()) {
2196 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2197 } else if (right->is_constant()) {
2198 // hack for now
2199 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2200 } else {
2201 ShouldNotReachHere();
2202 }
2203 switch (code) {
2204 case lir_add: __ addss(lreg, raddr); break;
2205 case lir_sub: __ subss(lreg, raddr); break;
2206 case lir_mul_strictfp: // fall through
2207 case lir_mul: __ mulss(lreg, raddr); break;
2208 case lir_div_strictfp: // fall through
2209 case lir_div: __ divss(lreg, raddr); break;
2210 default: ShouldNotReachHere();
2211 }
2212 }
2213
2214 } else if (left->is_double_xmm()) {
2215 assert(left == dest, "left and dest must be equal");
2216
2217 XMMRegister lreg = left->as_xmm_double_reg();
2218 if (right->is_double_xmm()) {
2219 XMMRegister rreg = right->as_xmm_double_reg();
2220 switch (code) {
2221 case lir_add: __ addsd(lreg, rreg); break;
2222 case lir_sub: __ subsd(lreg, rreg); break;
2223 case lir_mul_strictfp: // fall through
2224 case lir_mul: __ mulsd(lreg, rreg); break;
2225 case lir_div_strictfp: // fall through
2226 case lir_div: __ divsd(lreg, rreg); break;
2227 default: ShouldNotReachHere();
2228 }
2229 } else {
2230 Address raddr;
2231 if (right->is_double_stack()) {
2232 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2233 } else if (right->is_constant()) {
2234 // hack for now
2235 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2236 } else {
2237 ShouldNotReachHere();
2238 }
2239 switch (code) {
2240 case lir_add: __ addsd(lreg, raddr); break;
2241 case lir_sub: __ subsd(lreg, raddr); break;
2242 case lir_mul_strictfp: // fall through
2243 case lir_mul: __ mulsd(lreg, raddr); break;
2244 case lir_div_strictfp: // fall through
2245 case lir_div: __ divsd(lreg, raddr); break;
2246 default: ShouldNotReachHere();
2247 }
2248 }
2249
2250 } else if (left->is_single_fpu()) {
2251 assert(dest->is_single_fpu(), "fpu stack allocation required");
2252
2253 if (right->is_single_fpu()) {
2254 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2255
2256 } else {
2257 assert(left->fpu_regnr() == 0, "left must be on TOS");
2258 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2259
2260 Address raddr;
2261 if (right->is_single_stack()) {
2262 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2263 } else if (right->is_constant()) {
2264 address const_addr = float_constant(right->as_jfloat());
2265 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2266 // hack for now
2267 raddr = __ as_Address(InternalAddress(const_addr));
2268 } else {
2269 ShouldNotReachHere();
2270 }
2271
2272 switch (code) {
2273 case lir_add: __ fadd_s(raddr); break;
2274 case lir_sub: __ fsub_s(raddr); break;
2275 case lir_mul_strictfp: // fall through
2276 case lir_mul: __ fmul_s(raddr); break;
2277 case lir_div_strictfp: // fall through
2278 case lir_div: __ fdiv_s(raddr); break;
2279 default: ShouldNotReachHere();
2280 }
2281 }
2282
2283 } else if (left->is_double_fpu()) {
2284 assert(dest->is_double_fpu(), "fpu stack allocation required");
2285
2286 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2287 // Double values require special handling for strictfp mul/div on x86
2288 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2289 __ fmulp(left->fpu_regnrLo() + 1);
2290 }
2291
2292 if (right->is_double_fpu()) {
2293 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2294
2295 } else {
2296 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2297 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2298
2299 Address raddr;
2300 if (right->is_double_stack()) {
2301 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2302 } else if (right->is_constant()) {
2303 // hack for now
2304 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2305 } else {
2306 ShouldNotReachHere();
2307 }
2308
2309 switch (code) {
2310 case lir_add: __ fadd_d(raddr); break;
2311 case lir_sub: __ fsub_d(raddr); break;
2312 case lir_mul_strictfp: // fall through
2313 case lir_mul: __ fmul_d(raddr); break;
2314 case lir_div_strictfp: // fall through
2315 case lir_div: __ fdiv_d(raddr); break;
2316 default: ShouldNotReachHere();
2317 }
2318 }
2319
2320 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2321 // Double values require special handling for strictfp mul/div on x86
2322 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2323 __ fmulp(dest->fpu_regnrLo() + 1);
2324 }
2325
2326 } else if (left->is_single_stack() || left->is_address()) {
2327 assert(left == dest, "left and dest must be equal");
2328
2329 Address laddr;
2330 if (left->is_single_stack()) {
2331 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2332 } else if (left->is_address()) {
2333 laddr = as_Address(left->as_address_ptr());
2334 } else {
2335 ShouldNotReachHere();
2336 }
2337
2338 if (right->is_single_cpu()) {
2339 Register rreg = right->as_register();
2340 switch (code) {
2341 case lir_add: __ addl(laddr, rreg); break;
2342 case lir_sub: __ subl(laddr, rreg); break;
2343 default: ShouldNotReachHere();
2344 }
2345 } else if (right->is_constant()) {
2346 jint c = right->as_constant_ptr()->as_jint();
2347 switch (code) {
2348 case lir_add: {
2349 __ incrementl(laddr, c);
2350 break;
2351 }
2352 case lir_sub: {
2353 __ decrementl(laddr, c);
2354 break;
2355 }
2356 default: ShouldNotReachHere();
2357 }
2358 } else {
2359 ShouldNotReachHere();
2360 }
2361
2362 } else {
2363 ShouldNotReachHere();
2364 }
2365 }
2366
2367 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2368 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2369 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2370 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2371
2372 bool left_is_tos = (left_index == 0);
2373 bool dest_is_tos = (dest_index == 0);
2374 int non_tos_index = (left_is_tos ? right_index : left_index);
2375
2376 switch (code) {
2377 case lir_add:
2378 if (pop_fpu_stack) __ faddp(non_tos_index);
2379 else if (dest_is_tos) __ fadd (non_tos_index);
2380 else __ fadda(non_tos_index);
2381 break;
2382
2383 case lir_sub:
2384 if (left_is_tos) {
2385 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2386 else if (dest_is_tos) __ fsub (non_tos_index);
2387 else __ fsubra(non_tos_index);
2388 } else {
2389 if (pop_fpu_stack) __ fsubp (non_tos_index);
2390 else if (dest_is_tos) __ fsubr (non_tos_index);
2391 else __ fsuba (non_tos_index);
2392 }
2393 break;
2394
2395 case lir_mul_strictfp: // fall through
2396 case lir_mul:
2397 if (pop_fpu_stack) __ fmulp(non_tos_index);
2398 else if (dest_is_tos) __ fmul (non_tos_index);
2399 else __ fmula(non_tos_index);
2400 break;
2401
2402 case lir_div_strictfp: // fall through
2403 case lir_div:
2404 if (left_is_tos) {
2405 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2406 else if (dest_is_tos) __ fdiv (non_tos_index);
2407 else __ fdivra(non_tos_index);
2408 } else {
2409 if (pop_fpu_stack) __ fdivp (non_tos_index);
2410 else if (dest_is_tos) __ fdivr (non_tos_index);
2411 else __ fdiva (non_tos_index);
2412 }
2413 break;
2414
2415 case lir_rem:
2416 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2417 __ fremr(noreg);
2418 break;
2419
2420 default:
2421 ShouldNotReachHere();
2422 }
2423 }
2424
2425
2426 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2427 if (value->is_double_xmm()) {
2428 switch(code) {
2429 case lir_abs :
2430 {
2431 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2432 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2433 }
2434 __ andpd(dest->as_xmm_double_reg(),
2435 ExternalAddress((address)double_signmask_pool));
2436 }
2437 break;
2438
2439 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2440 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2441 default : ShouldNotReachHere();
2442 }
2443
2444 } else if (value->is_double_fpu()) {
2445 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2446 switch(code) {
2447 case lir_log : __ flog() ; break;
2448 case lir_log10 : __ flog10() ; break;
2449 case lir_abs : __ fabs() ; break;
2450 case lir_sqrt : __ fsqrt(); break;
2451 case lir_sin :
2452 // Should consider not saving rbx, if not necessary
2453 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2454 break;
2455 case lir_cos :
2456 // Should consider not saving rbx, if not necessary
2457 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2458 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2459 break;
2460 case lir_tan :
2461 // Should consider not saving rbx, if not necessary
2462 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2463 break;
2464 case lir_pow :
2465 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2466 break;
2467 default : ShouldNotReachHere();
2468 }
2469 } else {
2470 Unimplemented();
2471 }
2472 }
2473
2474 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2475 // assert(left->destroys_register(), "check");
2476 if (left->is_single_cpu()) {
2477 Register reg = left->as_register();
2478 if (right->is_constant()) {
2479 int val = right->as_constant_ptr()->as_jint();
2480 switch (code) {
2481 case lir_logic_and: __ andl (reg, val); break;
2482 case lir_logic_or: __ orl (reg, val); break;
2483 case lir_logic_xor: __ xorl (reg, val); break;
2484 default: ShouldNotReachHere();
2485 }
2486 } else if (right->is_stack()) {
2487 // added support for stack operands
2488 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2489 switch (code) {
2490 case lir_logic_and: __ andl (reg, raddr); break;
2491 case lir_logic_or: __ orl (reg, raddr); break;
2492 case lir_logic_xor: __ xorl (reg, raddr); break;
2493 default: ShouldNotReachHere();
2494 }
2495 } else {
2496 Register rright = right->as_register();
2497 switch (code) {
2498 case lir_logic_and: __ andptr (reg, rright); break;
2499 case lir_logic_or : __ orptr (reg, rright); break;
2500 case lir_logic_xor: __ xorptr (reg, rright); break;
2501 default: ShouldNotReachHere();
2502 }
2503 }
2504 move_regs(reg, dst->as_register());
2505 } else {
2506 Register l_lo = left->as_register_lo();
2507 Register l_hi = left->as_register_hi();
2508 if (right->is_constant()) {
2509 #ifdef _LP64
2510 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2511 switch (code) {
2512 case lir_logic_and:
2513 __ andq(l_lo, rscratch1);
2514 break;
2515 case lir_logic_or:
2516 __ orq(l_lo, rscratch1);
2517 break;
2518 case lir_logic_xor:
2519 __ xorq(l_lo, rscratch1);
2520 break;
2521 default: ShouldNotReachHere();
2522 }
2523 #else
2524 int r_lo = right->as_constant_ptr()->as_jint_lo();
2525 int r_hi = right->as_constant_ptr()->as_jint_hi();
2526 switch (code) {
2527 case lir_logic_and:
2528 __ andl(l_lo, r_lo);
2529 __ andl(l_hi, r_hi);
2530 break;
2531 case lir_logic_or:
2532 __ orl(l_lo, r_lo);
2533 __ orl(l_hi, r_hi);
2534 break;
2535 case lir_logic_xor:
2536 __ xorl(l_lo, r_lo);
2537 __ xorl(l_hi, r_hi);
2538 break;
2539 default: ShouldNotReachHere();
2540 }
2541 #endif // _LP64
2542 } else {
2543 #ifdef _LP64
2544 Register r_lo;
2545 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2546 r_lo = right->as_register();
2547 } else {
2548 r_lo = right->as_register_lo();
2549 }
2550 #else
2551 Register r_lo = right->as_register_lo();
2552 Register r_hi = right->as_register_hi();
2553 assert(l_lo != r_hi, "overwriting registers");
2554 #endif
2555 switch (code) {
2556 case lir_logic_and:
2557 __ andptr(l_lo, r_lo);
2558 NOT_LP64(__ andptr(l_hi, r_hi);)
2559 break;
2560 case lir_logic_or:
2561 __ orptr(l_lo, r_lo);
2562 NOT_LP64(__ orptr(l_hi, r_hi);)
2563 break;
2564 case lir_logic_xor:
2565 __ xorptr(l_lo, r_lo);
2566 NOT_LP64(__ xorptr(l_hi, r_hi);)
2567 break;
2568 default: ShouldNotReachHere();
2569 }
2570 }
2571
2572 Register dst_lo = dst->as_register_lo();
2573 Register dst_hi = dst->as_register_hi();
2574
2575 #ifdef _LP64
2576 move_regs(l_lo, dst_lo);
2577 #else
2578 if (dst_lo == l_hi) {
2579 assert(dst_hi != l_lo, "overwriting registers");
2580 move_regs(l_hi, dst_hi);
2581 move_regs(l_lo, dst_lo);
2582 } else {
2583 assert(dst_lo != l_hi, "overwriting registers");
2584 move_regs(l_lo, dst_lo);
2585 move_regs(l_hi, dst_hi);
2586 }
2587 #endif // _LP64
2588 }
2589 }
2590
2591
2592 // we assume that rax, and rdx can be overwritten
2593 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2594
2595 assert(left->is_single_cpu(), "left must be register");
2596 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2597 assert(result->is_single_cpu(), "result must be register");
2598
2599 // assert(left->destroys_register(), "check");
2600 // assert(right->destroys_register(), "check");
2601
2602 Register lreg = left->as_register();
2603 Register dreg = result->as_register();
2604
2605 if (right->is_constant()) {
2606 int divisor = right->as_constant_ptr()->as_jint();
2607 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2608 if (code == lir_idiv) {
2609 assert(lreg == rax, "must be rax,");
2610 assert(temp->as_register() == rdx, "tmp register must be rdx");
2611 __ cdql(); // sign extend into rdx:rax
2612 if (divisor == 2) {
2613 __ subl(lreg, rdx);
2614 } else {
2615 __ andl(rdx, divisor - 1);
2616 __ addl(lreg, rdx);
2617 }
2618 __ sarl(lreg, log2_intptr(divisor));
2619 move_regs(lreg, dreg);
2620 } else if (code == lir_irem) {
2621 Label done;
2622 __ mov(dreg, lreg);
2623 __ andl(dreg, 0x80000000 | (divisor - 1));
2624 __ jcc(Assembler::positive, done);
2625 __ decrement(dreg);
2626 __ orl(dreg, ~(divisor - 1));
2627 __ increment(dreg);
2628 __ bind(done);
2629 } else {
2630 ShouldNotReachHere();
2631 }
2632 } else {
2633 Register rreg = right->as_register();
2634 assert(lreg == rax, "left register must be rax,");
2635 assert(rreg != rdx, "right register must not be rdx");
2636 assert(temp->as_register() == rdx, "tmp register must be rdx");
2637
2638 move_regs(lreg, rax);
2639
2640 int idivl_offset = __ corrected_idivl(rreg);
2641 add_debug_info_for_div0(idivl_offset, info);
2642 if (code == lir_irem) {
2643 move_regs(rdx, dreg); // result is in rdx
2644 } else {
2645 move_regs(rax, dreg);
2646 }
2647 }
2648 }
2649
2650
2651 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2652 if (opr1->is_single_cpu()) {
2653 Register reg1 = opr1->as_register();
2654 if (opr2->is_single_cpu()) {
2655 // cpu register - cpu register
2656 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2657 __ cmpptr(reg1, opr2->as_register());
2658 } else {
2659 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2660 __ cmpl(reg1, opr2->as_register());
2661 }
2662 } else if (opr2->is_stack()) {
2663 // cpu register - stack
2664 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2665 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2666 } else {
2667 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2668 }
2669 } else if (opr2->is_constant()) {
2670 // cpu register - constant
2671 LIR_Const* c = opr2->as_constant_ptr();
2672 if (c->type() == T_INT) {
2673 __ cmpl(reg1, c->as_jint());
2674 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2675 // In 64bit oops are single register
2676 jobject o = c->as_jobject();
2677 if (o == NULL) {
2678 __ cmpptr(reg1, (int32_t)NULL_WORD);
2679 } else {
2680 #ifdef _LP64
2681 __ movoop(rscratch1, o);
2682 __ cmpptr(reg1, rscratch1);
2683 #else
2684 __ cmpoop(reg1, c->as_jobject());
2685 #endif // _LP64
2686 }
2687 } else {
2688 fatal("unexpected type: %s", basictype_to_str(c->type()));
2689 }
2690 // cpu register - address
2691 } else if (opr2->is_address()) {
2692 if (op->info() != NULL) {
2693 add_debug_info_for_null_check_here(op->info());
2694 }
2695 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2696 } else {
2697 ShouldNotReachHere();
2698 }
2699
2700 } else if(opr1->is_double_cpu()) {
2701 Register xlo = opr1->as_register_lo();
2702 Register xhi = opr1->as_register_hi();
2703 if (opr2->is_double_cpu()) {
2704 #ifdef _LP64
2705 __ cmpptr(xlo, opr2->as_register_lo());
2706 #else
2707 // cpu register - cpu register
2708 Register ylo = opr2->as_register_lo();
2709 Register yhi = opr2->as_register_hi();
2710 __ subl(xlo, ylo);
2711 __ sbbl(xhi, yhi);
2712 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2713 __ orl(xhi, xlo);
2714 }
2715 #endif // _LP64
2716 } else if (opr2->is_constant()) {
2717 // cpu register - constant 0
2718 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2719 #ifdef _LP64
2720 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2721 #else
2722 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2723 __ orl(xhi, xlo);
2724 #endif // _LP64
2725 } else {
2726 ShouldNotReachHere();
2727 }
2728
2729 } else if (opr1->is_single_xmm()) {
2730 XMMRegister reg1 = opr1->as_xmm_float_reg();
2731 if (opr2->is_single_xmm()) {
2732 // xmm register - xmm register
2733 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2734 } else if (opr2->is_stack()) {
2735 // xmm register - stack
2736 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2737 } else if (opr2->is_constant()) {
2738 // xmm register - constant
2739 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2740 } else if (opr2->is_address()) {
2741 // xmm register - address
2742 if (op->info() != NULL) {
2743 add_debug_info_for_null_check_here(op->info());
2744 }
2745 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2746 } else {
2747 ShouldNotReachHere();
2748 }
2749
2750 } else if (opr1->is_double_xmm()) {
2751 XMMRegister reg1 = opr1->as_xmm_double_reg();
2752 if (opr2->is_double_xmm()) {
2753 // xmm register - xmm register
2754 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2755 } else if (opr2->is_stack()) {
2756 // xmm register - stack
2757 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2758 } else if (opr2->is_constant()) {
2759 // xmm register - constant
2760 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2761 } else if (opr2->is_address()) {
2762 // xmm register - address
2763 if (op->info() != NULL) {
2764 add_debug_info_for_null_check_here(op->info());
2765 }
2766 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2767 } else {
2768 ShouldNotReachHere();
2769 }
2770
2771 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2772 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2773 assert(opr2->is_fpu_register(), "both must be registers");
2774 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2775
2776 } else if (opr1->is_address() && opr2->is_constant()) {
2777 LIR_Const* c = opr2->as_constant_ptr();
2778 #ifdef _LP64
2779 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2780 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2781 __ movoop(rscratch1, c->as_jobject());
2782 }
2783 #endif // LP64
2784 if (op->info() != NULL) {
2785 add_debug_info_for_null_check_here(op->info());
2786 }
2787 // special case: address - constant
2788 LIR_Address* addr = opr1->as_address_ptr();
2789 if (c->type() == T_INT) {
2790 __ cmpl(as_Address(addr), c->as_jint());
2791 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2792 #ifdef _LP64
2793 // %%% Make this explode if addr isn't reachable until we figure out a
2794 // better strategy by giving noreg as the temp for as_Address
2795 __ cmpptr(rscratch1, as_Address(addr, noreg));
2796 #else
2797 __ cmpoop(as_Address(addr), c->as_jobject());
2798 #endif // _LP64
2799 } else {
2800 ShouldNotReachHere();
2801 }
2802
2803 } else {
2804 ShouldNotReachHere();
2805 }
2806 }
2807
2808 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2809 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2810 if (left->is_single_xmm()) {
2811 assert(right->is_single_xmm(), "must match");
2812 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2813 } else if (left->is_double_xmm()) {
2814 assert(right->is_double_xmm(), "must match");
2815 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2816
2817 } else {
2818 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2819 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2820
2821 assert(left->fpu() == 0, "left must be on TOS");
2822 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2823 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2824 }
2825 } else {
2826 assert(code == lir_cmp_l2i, "check");
2827 #ifdef _LP64
2828 Label done;
2829 Register dest = dst->as_register();
2830 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2831 __ movl(dest, -1);
2832 __ jccb(Assembler::less, done);
2833 __ set_byte_if_not_zero(dest);
2834 __ movzbl(dest, dest);
2835 __ bind(done);
2836 #else
2837 __ lcmp2int(left->as_register_hi(),
2838 left->as_register_lo(),
2839 right->as_register_hi(),
2840 right->as_register_lo());
2841 move_regs(left->as_register_hi(), dst->as_register());
2842 #endif // _LP64
2843 }
2844 }
2845
2846
2847 void LIR_Assembler::align_call(LIR_Code code) {
2848 if (os::is_MP()) {
2849 // make sure that the displacement word of the call ends up word aligned
2850 int offset = __ offset();
2851 switch (code) {
2852 case lir_static_call:
2853 case lir_optvirtual_call:
2854 case lir_dynamic_call:
2855 offset += NativeCall::displacement_offset;
2856 break;
2857 case lir_icvirtual_call:
2858 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2859 break;
2860 case lir_virtual_call: // currently, sparc-specific for niagara
2861 default: ShouldNotReachHere();
2862 }
2863 __ align(BytesPerWord, offset);
2864 }
2865 }
2866
2867
2868 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2869 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2870 "must be aligned");
2871 __ call(AddressLiteral(op->addr(), rtype));
2872 add_call_info(code_offset(), op->info());
2873 }
2874
2875
2876 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2877 __ ic_call(op->addr());
2878 add_call_info(code_offset(), op->info());
2879 assert(!os::is_MP() ||
2880 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2881 "must be aligned");
2882 }
2883
2884
2885 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2886 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2887 ShouldNotReachHere();
2888 }
2889
2890
2891 void LIR_Assembler::emit_static_call_stub() {
2892 address call_pc = __ pc();
2893 address stub = __ start_a_stub(call_stub_size);
2894 if (stub == NULL) {
2895 bailout("static call stub overflow");
2896 return;
2897 }
2898
2899 int start = __ offset();
2900 if (os::is_MP()) {
2901 // make sure that the displacement word of the call ends up word aligned
2902 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2903 }
2904 __ relocate(static_stub_Relocation::spec(call_pc));
2905 __ mov_metadata(rbx, (Metadata*)NULL);
2906 // must be set to -1 at code generation time
2907 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2908 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2909 __ jump(RuntimeAddress(__ pc()));
2910
2911 assert(__ offset() - start <= call_stub_size, "stub too big");
2912 __ end_a_stub();
2913 }
2914
2915
2916 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2917 assert(exceptionOop->as_register() == rax, "must match");
2918 assert(exceptionPC->as_register() == rdx, "must match");
2919
2920 // exception object is not added to oop map by LinearScan
2921 // (LinearScan assumes that no oops are in fixed registers)
2922 info->add_register_oop(exceptionOop);
2923 Runtime1::StubID unwind_id;
2924
2925 // get current pc information
2926 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2927 int pc_for_athrow_offset = __ offset();
2928 InternalAddress pc_for_athrow(__ pc());
2929 __ lea(exceptionPC->as_register(), pc_for_athrow);
2930 add_call_info(pc_for_athrow_offset, info); // for exception handler
2931
2932 __ verify_not_null_oop(rax);
2933 // search an exception handler (rax: exception oop, rdx: throwing pc)
2934 if (compilation()->has_fpu_code()) {
2935 unwind_id = Runtime1::handle_exception_id;
2936 } else {
2937 unwind_id = Runtime1::handle_exception_nofpu_id;
2938 }
2939 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2940
2941 // enough room for two byte trap
2942 __ nop();
2943 }
2944
2945
2946 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2947 assert(exceptionOop->as_register() == rax, "must match");
2948
2949 __ jmp(_unwind_handler_entry);
2950 }
2951
2952
2953 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2954
2955 // optimized version for linear scan:
2956 // * count must be already in ECX (guaranteed by LinearScan)
2957 // * left and dest must be equal
2958 // * tmp must be unused
2959 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2960 assert(left == dest, "left and dest must be equal");
2961 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2962
2963 if (left->is_single_cpu()) {
2964 Register value = left->as_register();
2965 assert(value != SHIFT_count, "left cannot be ECX");
2966
2967 switch (code) {
2968 case lir_shl: __ shll(value); break;
2969 case lir_shr: __ sarl(value); break;
2970 case lir_ushr: __ shrl(value); break;
2971 default: ShouldNotReachHere();
2972 }
2973 } else if (left->is_double_cpu()) {
2974 Register lo = left->as_register_lo();
2975 Register hi = left->as_register_hi();
2976 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2977 #ifdef _LP64
2978 switch (code) {
2979 case lir_shl: __ shlptr(lo); break;
2980 case lir_shr: __ sarptr(lo); break;
2981 case lir_ushr: __ shrptr(lo); break;
2982 default: ShouldNotReachHere();
2983 }
2984 #else
2985
2986 switch (code) {
2987 case lir_shl: __ lshl(hi, lo); break;
2988 case lir_shr: __ lshr(hi, lo, true); break;
2989 case lir_ushr: __ lshr(hi, lo, false); break;
2990 default: ShouldNotReachHere();
2991 }
2992 #endif // LP64
2993 } else {
2994 ShouldNotReachHere();
2995 }
2996 }
2997
2998
2999 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3000 if (dest->is_single_cpu()) {
3001 // first move left into dest so that left is not destroyed by the shift
3002 Register value = dest->as_register();
3003 count = count & 0x1F; // Java spec
3004
3005 move_regs(left->as_register(), value);
3006 switch (code) {
3007 case lir_shl: __ shll(value, count); break;
3008 case lir_shr: __ sarl(value, count); break;
3009 case lir_ushr: __ shrl(value, count); break;
3010 default: ShouldNotReachHere();
3011 }
3012 } else if (dest->is_double_cpu()) {
3013 #ifndef _LP64
3014 Unimplemented();
3015 #else
3016 // first move left into dest so that left is not destroyed by the shift
3017 Register value = dest->as_register_lo();
3018 count = count & 0x1F; // Java spec
3019
3020 move_regs(left->as_register_lo(), value);
3021 switch (code) {
3022 case lir_shl: __ shlptr(value, count); break;
3023 case lir_shr: __ sarptr(value, count); break;
3024 case lir_ushr: __ shrptr(value, count); break;
3025 default: ShouldNotReachHere();
3026 }
3027 #endif // _LP64
3028 } else {
3029 ShouldNotReachHere();
3030 }
3031 }
3032
3033
3034 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3035 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3036 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3037 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3038 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3039 }
3040
3041
3042 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3043 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3044 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3045 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3046 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3047 }
3048
3049
3050 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3051 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3052 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3053 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3054 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3055 }
3056
3057
3058 // This code replaces a call to arraycopy; no exception may
3059 // be thrown in this code, they must be thrown in the System.arraycopy
3060 // activation frame; we could save some checks if this would not be the case
3061 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3062 ciArrayKlass* default_type = op->expected_type();
3063 Register src = op->src()->as_register();
3064 Register dst = op->dst()->as_register();
3065 Register src_pos = op->src_pos()->as_register();
3066 Register dst_pos = op->dst_pos()->as_register();
3067 Register length = op->length()->as_register();
3068 Register tmp = op->tmp()->as_register();
3069
3070 CodeStub* stub = op->stub();
3071 int flags = op->flags();
3072 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3073 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3074
3075 // if we don't know anything, just go through the generic arraycopy
3076 if (default_type == NULL) {
3077 Label done;
3078 // save outgoing arguments on stack in case call to System.arraycopy is needed
3079 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3080 // for interpreter calling conventions. Now we have to do it in new style conventions.
3081 // For the moment until C1 gets the new register allocator I just force all the
3082 // args to the right place (except the register args) and then on the back side
3083 // reload the register args properly if we go slow path. Yuck
3084
3085 // These are proper for the calling convention
3086 store_parameter(length, 2);
3087 store_parameter(dst_pos, 1);
3088 store_parameter(dst, 0);
3089
3090 // these are just temporary placements until we need to reload
3091 store_parameter(src_pos, 3);
3092 store_parameter(src, 4);
3093 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3094
3095 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3096
3097 address copyfunc_addr = StubRoutines::generic_arraycopy();
3098
3099 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3100 #ifdef _LP64
3101 // The arguments are in java calling convention so we can trivially shift them to C
3102 // convention
3103 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3104 __ mov(c_rarg0, j_rarg0);
3105 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3106 __ mov(c_rarg1, j_rarg1);
3107 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3108 __ mov(c_rarg2, j_rarg2);
3109 assert_different_registers(c_rarg3, j_rarg4);
3110 __ mov(c_rarg3, j_rarg3);
3111 #ifdef _WIN64
3112 // Allocate abi space for args but be sure to keep stack aligned
3113 __ subptr(rsp, 6*wordSize);
3114 store_parameter(j_rarg4, 4);
3115 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3116 __ call(RuntimeAddress(C_entry));
3117 } else {
3118 #ifndef PRODUCT
3119 if (PrintC1Statistics) {
3120 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3121 }
3122 #endif
3123 __ call(RuntimeAddress(copyfunc_addr));
3124 }
3125 __ addptr(rsp, 6*wordSize);
3126 #else
3127 __ mov(c_rarg4, j_rarg4);
3128 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3129 __ call(RuntimeAddress(C_entry));
3130 } else {
3131 #ifndef PRODUCT
3132 if (PrintC1Statistics) {
3133 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3134 }
3135 #endif
3136 __ call(RuntimeAddress(copyfunc_addr));
3137 }
3138 #endif // _WIN64
3139 #else
3140 __ push(length);
3141 __ push(dst_pos);
3142 __ push(dst);
3143 __ push(src_pos);
3144 __ push(src);
3145
3146 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3147 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3148 } else {
3149 #ifndef PRODUCT
3150 if (PrintC1Statistics) {
3151 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3152 }
3153 #endif
3154 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3155 }
3156
3157 #endif // _LP64
3158
3159 __ cmpl(rax, 0);
3160 __ jcc(Assembler::equal, *stub->continuation());
3161
3162 if (copyfunc_addr != NULL) {
3163 __ mov(tmp, rax);
3164 __ xorl(tmp, -1);
3165 }
3166
3167 // Reload values from the stack so they are where the stub
3168 // expects them.
3169 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3170 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3171 __ movptr (length, Address(rsp, 2*BytesPerWord));
3172 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3173 __ movptr (src, Address(rsp, 4*BytesPerWord));
3174
3175 if (copyfunc_addr != NULL) {
3176 __ subl(length, tmp);
3177 __ addl(src_pos, tmp);
3178 __ addl(dst_pos, tmp);
3179 }
3180 __ jmp(*stub->entry());
3181
3182 __ bind(*stub->continuation());
3183 return;
3184 }
3185
3186 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3187
3188 int elem_size = type2aelembytes(basic_type);
3189 int shift_amount;
3190 Address::ScaleFactor scale;
3191
3192 switch (elem_size) {
3193 case 1 :
3194 shift_amount = 0;
3195 scale = Address::times_1;
3196 break;
3197 case 2 :
3198 shift_amount = 1;
3199 scale = Address::times_2;
3200 break;
3201 case 4 :
3202 shift_amount = 2;
3203 scale = Address::times_4;
3204 break;
3205 case 8 :
3206 shift_amount = 3;
3207 scale = Address::times_8;
3208 break;
3209 default:
3210 ShouldNotReachHere();
3211 }
3212
3213 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3214 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3215 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3216 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3217
3218 // length and pos's are all sign extended at this point on 64bit
3219
3220 // test for NULL
3221 if (flags & LIR_OpArrayCopy::src_null_check) {
3222 __ testptr(src, src);
3223 __ jcc(Assembler::zero, *stub->entry());
3224 }
3225 if (flags & LIR_OpArrayCopy::dst_null_check) {
3226 __ testptr(dst, dst);
3227 __ jcc(Assembler::zero, *stub->entry());
3228 }
3229
3230 // check if negative
3231 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3232 __ testl(src_pos, src_pos);
3233 __ jcc(Assembler::less, *stub->entry());
3234 }
3235 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3236 __ testl(dst_pos, dst_pos);
3237 __ jcc(Assembler::less, *stub->entry());
3238 }
3239
3240 if (flags & LIR_OpArrayCopy::src_range_check) {
3241 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3242 __ cmpl(tmp, src_length_addr);
3243 __ jcc(Assembler::above, *stub->entry());
3244 }
3245 if (flags & LIR_OpArrayCopy::dst_range_check) {
3246 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3247 __ cmpl(tmp, dst_length_addr);
3248 __ jcc(Assembler::above, *stub->entry());
3249 }
3250
3251 if (flags & LIR_OpArrayCopy::length_positive_check) {
3252 __ testl(length, length);
3253 __ jcc(Assembler::less, *stub->entry());
3254 __ jcc(Assembler::zero, *stub->continuation());
3255 }
3256
3257 #ifdef _LP64
3258 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3259 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3260 #endif
3261
3262 if (flags & LIR_OpArrayCopy::type_check) {
3263 // We don't know the array types are compatible
3264 if (basic_type != T_OBJECT) {
3265 // Simple test for basic type arrays
3266 if (UseCompressedClassPointers) {
3267 __ movl(tmp, src_klass_addr);
3268 __ cmpl(tmp, dst_klass_addr);
3269 } else {
3270 __ movptr(tmp, src_klass_addr);
3271 __ cmpptr(tmp, dst_klass_addr);
3272 }
3273 __ jcc(Assembler::notEqual, *stub->entry());
3274 } else {
3275 // For object arrays, if src is a sub class of dst then we can
3276 // safely do the copy.
3277 Label cont, slow;
3278
3279 __ push(src);
3280 __ push(dst);
3281
3282 __ load_klass(src, src);
3283 __ load_klass(dst, dst);
3284
3285 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3286
3287 __ push(src);
3288 __ push(dst);
3289 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3290 __ pop(dst);
3291 __ pop(src);
3292
3293 __ cmpl(src, 0);
3294 __ jcc(Assembler::notEqual, cont);
3295
3296 __ bind(slow);
3297 __ pop(dst);
3298 __ pop(src);
3299
3300 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3301 if (copyfunc_addr != NULL) { // use stub if available
3302 // src is not a sub class of dst so we have to do a
3303 // per-element check.
3304
3305 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3306 if ((flags & mask) != mask) {
3307 // Check that at least both of them object arrays.
3308 assert(flags & mask, "one of the two should be known to be an object array");
3309
3310 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3311 __ load_klass(tmp, src);
3312 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3313 __ load_klass(tmp, dst);
3314 }
3315 int lh_offset = in_bytes(Klass::layout_helper_offset());
3316 Address klass_lh_addr(tmp, lh_offset);
3317 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3318 __ cmpl(klass_lh_addr, objArray_lh);
3319 __ jcc(Assembler::notEqual, *stub->entry());
3320 }
3321
3322 // Spill because stubs can use any register they like and it's
3323 // easier to restore just those that we care about.
3324 store_parameter(dst, 0);
3325 store_parameter(dst_pos, 1);
3326 store_parameter(length, 2);
3327 store_parameter(src_pos, 3);
3328 store_parameter(src, 4);
3329
3330 #ifndef _LP64
3331 __ movptr(tmp, dst_klass_addr);
3332 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3333 __ push(tmp);
3334 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3335 __ push(tmp);
3336 __ push(length);
3337 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3338 __ push(tmp);
3339 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3340 __ push(tmp);
3341
3342 __ call_VM_leaf(copyfunc_addr, 5);
3343 #else
3344 __ movl2ptr(length, length); //higher 32bits must be null
3345
3346 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3347 assert_different_registers(c_rarg0, dst, dst_pos, length);
3348 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3349 assert_different_registers(c_rarg1, dst, length);
3350
3351 __ mov(c_rarg2, length);
3352 assert_different_registers(c_rarg2, dst);
3353
3354 #ifdef _WIN64
3355 // Allocate abi space for args but be sure to keep stack aligned
3356 __ subptr(rsp, 6*wordSize);
3357 __ load_klass(c_rarg3, dst);
3358 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3359 store_parameter(c_rarg3, 4);
3360 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3361 __ call(RuntimeAddress(copyfunc_addr));
3362 __ addptr(rsp, 6*wordSize);
3363 #else
3364 __ load_klass(c_rarg4, dst);
3365 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3366 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3367 __ call(RuntimeAddress(copyfunc_addr));
3368 #endif
3369
3370 #endif
3371
3372 #ifndef PRODUCT
3373 if (PrintC1Statistics) {
3374 Label failed;
3375 __ testl(rax, rax);
3376 __ jcc(Assembler::notZero, failed);
3377 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3378 __ bind(failed);
3379 }
3380 #endif
3381
3382 __ testl(rax, rax);
3383 __ jcc(Assembler::zero, *stub->continuation());
3384
3385 #ifndef PRODUCT
3386 if (PrintC1Statistics) {
3387 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3388 }
3389 #endif
3390
3391 __ mov(tmp, rax);
3392
3393 __ xorl(tmp, -1);
3394
3395 // Restore previously spilled arguments
3396 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3397 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3398 __ movptr (length, Address(rsp, 2*BytesPerWord));
3399 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3400 __ movptr (src, Address(rsp, 4*BytesPerWord));
3401
3402
3403 __ subl(length, tmp);
3404 __ addl(src_pos, tmp);
3405 __ addl(dst_pos, tmp);
3406 }
3407
3408 __ jmp(*stub->entry());
3409
3410 __ bind(cont);
3411 __ pop(dst);
3412 __ pop(src);
3413 }
3414 }
3415
3416 #ifdef ASSERT
3417 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3418 // Sanity check the known type with the incoming class. For the
3419 // primitive case the types must match exactly with src.klass and
3420 // dst.klass each exactly matching the default type. For the
3421 // object array case, if no type check is needed then either the
3422 // dst type is exactly the expected type and the src type is a
3423 // subtype which we can't check or src is the same array as dst
3424 // but not necessarily exactly of type default_type.
3425 Label known_ok, halt;
3426 __ mov_metadata(tmp, default_type->constant_encoding());
3427 #ifdef _LP64
3428 if (UseCompressedClassPointers) {
3429 __ encode_klass_not_null(tmp);
3430 }
3431 #endif
3432
3433 if (basic_type != T_OBJECT) {
3434
3435 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3436 else __ cmpptr(tmp, dst_klass_addr);
3437 __ jcc(Assembler::notEqual, halt);
3438 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3439 else __ cmpptr(tmp, src_klass_addr);
3440 __ jcc(Assembler::equal, known_ok);
3441 } else {
3442 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3443 else __ cmpptr(tmp, dst_klass_addr);
3444 __ jcc(Assembler::equal, known_ok);
3445 __ cmpptr(src, dst);
3446 __ jcc(Assembler::equal, known_ok);
3447 }
3448 __ bind(halt);
3449 __ stop("incorrect type information in arraycopy");
3450 __ bind(known_ok);
3451 }
3452 #endif
3453
3454 #ifndef PRODUCT
3455 if (PrintC1Statistics) {
3456 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3457 }
3458 #endif
3459
3460 #ifdef _LP64
3461 assert_different_registers(c_rarg0, dst, dst_pos, length);
3462 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3463 assert_different_registers(c_rarg1, length);
3464 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3465 __ mov(c_rarg2, length);
3466
3467 #else
3468 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3469 store_parameter(tmp, 0);
3470 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3471 store_parameter(tmp, 1);
3472 store_parameter(length, 2);
3473 #endif // _LP64
3474
3475 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3476 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3477 const char *name;
3478 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3479 __ call_VM_leaf(entry, 0);
3480
3481 __ bind(*stub->continuation());
3482 }
3483
3484 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3485 assert(op->crc()->is_single_cpu(), "crc must be register");
3486 assert(op->val()->is_single_cpu(), "byte value must be register");
3487 assert(op->result_opr()->is_single_cpu(), "result must be register");
3488 Register crc = op->crc()->as_register();
3489 Register val = op->val()->as_register();
3490 Register res = op->result_opr()->as_register();
3491
3492 assert_different_registers(val, crc, res);
3493
3494 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3495 __ notl(crc); // ~crc
3496 __ update_byte_crc32(crc, val, res);
3497 __ notl(crc); // ~crc
3498 __ mov(res, crc);
3499 }
3500
3501 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3502 Register obj = op->obj_opr()->as_register(); // may not be an oop
3503 Register hdr = op->hdr_opr()->as_register();
3504 Register lock = op->lock_opr()->as_register();
3505 if (!UseFastLocking) {
3506 __ jmp(*op->stub()->entry());
3507 } else if (op->code() == lir_lock) {
3508 Register scratch = noreg;
3509 if (UseBiasedLocking) {
3510 scratch = op->scratch_opr()->as_register();
3511 }
3512 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3513 // add debug info for NullPointerException only if one is possible
3514 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3515 if (op->info() != NULL) {
3516 add_debug_info_for_null_check(null_check_offset, op->info());
3517 }
3518 // done
3519 } else if (op->code() == lir_unlock) {
3520 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3521 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3522 } else {
3523 Unimplemented();
3524 }
3525 __ bind(*op->stub()->continuation());
3526 }
3527
3528
3529 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3530 ciMethod* method = op->profiled_method();
3531 int bci = op->profiled_bci();
3532 ciMethod* callee = op->profiled_callee();
3533
3534 // Update counter for all call types
3535 ciMethodData* md = method->method_data_or_null();
3536 assert(md != NULL, "Sanity");
3537 ciProfileData* data = md->bci_to_data(bci);
3538 assert(data->is_CounterData(), "need CounterData for calls");
3539 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3540 Register mdo = op->mdo()->as_register();
3541 __ mov_metadata(mdo, md->constant_encoding());
3542 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3543 Bytecodes::Code bc = method->java_code_at_bci(bci);
3544 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3545 // Perform additional virtual call profiling for invokevirtual and
3546 // invokeinterface bytecodes
3547 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3548 !callee_is_static && // required for optimized MH invokes
3549 C1ProfileVirtualCalls) {
3550 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3551 Register recv = op->recv()->as_register();
3552 assert_different_registers(mdo, recv);
3553 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3554 ciKlass* known_klass = op->known_holder();
3555 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3556 // We know the type that will be seen at this call site; we can
3557 // statically update the MethodData* rather than needing to do
3558 // dynamic tests on the receiver type
3559
3560 // NOTE: we should probably put a lock around this search to
3561 // avoid collisions by concurrent compilations
3562 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3563 uint i;
3564 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3565 ciKlass* receiver = vc_data->receiver(i);
3566 if (known_klass->equals(receiver)) {
3567 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3568 __ addptr(data_addr, DataLayout::counter_increment);
3569 return;
3570 }
3571 }
3572
3573 // Receiver type not found in profile data; select an empty slot
3574
3575 // Note that this is less efficient than it should be because it
3576 // always does a write to the receiver part of the
3577 // VirtualCallData rather than just the first time
3578 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3579 ciKlass* receiver = vc_data->receiver(i);
3580 if (receiver == NULL) {
3581 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3582 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3583 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3584 __ addptr(data_addr, DataLayout::counter_increment);
3585 return;
3586 }
3587 }
3588 } else {
3589 __ load_klass(recv, recv);
3590 Label update_done;
3591 type_profile_helper(mdo, md, data, recv, &update_done);
3592 // Receiver did not match any saved receiver and there is no empty row for it.
3593 // Increment total counter to indicate polymorphic case.
3594 __ addptr(counter_addr, DataLayout::counter_increment);
3595
3596 __ bind(update_done);
3597 }
3598 } else {
3599 // Static call
3600 __ addptr(counter_addr, DataLayout::counter_increment);
3601 }
3602 }
3603
3604 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3605 Register obj = op->obj()->as_register();
3606 Register tmp = op->tmp()->as_pointer_register();
3607 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3608 ciKlass* exact_klass = op->exact_klass();
3609 intptr_t current_klass = op->current_klass();
3610 bool not_null = op->not_null();
3611 bool no_conflict = op->no_conflict();
3612
3613 Label update, next, none;
3614
3615 bool do_null = !not_null;
3616 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3617 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3618
3619 assert(do_null || do_update, "why are we here?");
3620 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3621
3622 __ verify_oop(obj);
3623
3624 if (tmp != obj) {
3625 __ mov(tmp, obj);
3626 }
3627 if (do_null) {
3628 __ testptr(tmp, tmp);
3629 __ jccb(Assembler::notZero, update);
3630 if (!TypeEntries::was_null_seen(current_klass)) {
3631 __ orptr(mdo_addr, TypeEntries::null_seen);
3632 }
3633 if (do_update) {
3634 #ifndef ASSERT
3635 __ jmpb(next);
3636 }
3637 #else
3638 __ jmp(next);
3639 }
3640 } else {
3641 __ testptr(tmp, tmp);
3642 __ jccb(Assembler::notZero, update);
3643 __ stop("unexpect null obj");
3644 #endif
3645 }
3646
3647 __ bind(update);
3648
3649 if (do_update) {
3650 #ifdef ASSERT
3651 if (exact_klass != NULL) {
3652 Label ok;
3653 __ load_klass(tmp, tmp);
3654 __ push(tmp);
3655 __ mov_metadata(tmp, exact_klass->constant_encoding());
3656 __ cmpptr(tmp, Address(rsp, 0));
3657 __ jccb(Assembler::equal, ok);
3658 __ stop("exact klass and actual klass differ");
3659 __ bind(ok);
3660 __ pop(tmp);
3661 }
3662 #endif
3663 if (!no_conflict) {
3664 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3665 if (exact_klass != NULL) {
3666 __ mov_metadata(tmp, exact_klass->constant_encoding());
3667 } else {
3668 __ load_klass(tmp, tmp);
3669 }
3670
3671 __ xorptr(tmp, mdo_addr);
3672 __ testptr(tmp, TypeEntries::type_klass_mask);
3673 // klass seen before, nothing to do. The unknown bit may have been
3674 // set already but no need to check.
3675 __ jccb(Assembler::zero, next);
3676
3677 __ testptr(tmp, TypeEntries::type_unknown);
3678 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3679
3680 if (TypeEntries::is_type_none(current_klass)) {
3681 __ cmpptr(mdo_addr, 0);
3682 __ jccb(Assembler::equal, none);
3683 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3684 __ jccb(Assembler::equal, none);
3685 // There is a chance that the checks above (re-reading profiling
3686 // data from memory) fail if another thread has just set the
3687 // profiling to this obj's klass
3688 __ xorptr(tmp, mdo_addr);
3689 __ testptr(tmp, TypeEntries::type_klass_mask);
3690 __ jccb(Assembler::zero, next);
3691 }
3692 } else {
3693 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3694 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3695
3696 __ movptr(tmp, mdo_addr);
3697 __ testptr(tmp, TypeEntries::type_unknown);
3698 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3699 }
3700
3701 // different than before. Cannot keep accurate profile.
3702 __ orptr(mdo_addr, TypeEntries::type_unknown);
3703
3704 if (TypeEntries::is_type_none(current_klass)) {
3705 __ jmpb(next);
3706
3707 __ bind(none);
3708 // first time here. Set profile type.
3709 __ movptr(mdo_addr, tmp);
3710 }
3711 } else {
3712 // There's a single possible klass at this profile point
3713 assert(exact_klass != NULL, "should be");
3714 if (TypeEntries::is_type_none(current_klass)) {
3715 __ mov_metadata(tmp, exact_klass->constant_encoding());
3716 __ xorptr(tmp, mdo_addr);
3717 __ testptr(tmp, TypeEntries::type_klass_mask);
3718 #ifdef ASSERT
3719 __ jcc(Assembler::zero, next);
3720
3721 {
3722 Label ok;
3723 __ push(tmp);
3724 __ cmpptr(mdo_addr, 0);
3725 __ jcc(Assembler::equal, ok);
3726 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3727 __ jcc(Assembler::equal, ok);
3728 // may have been set by another thread
3729 __ mov_metadata(tmp, exact_klass->constant_encoding());
3730 __ xorptr(tmp, mdo_addr);
3731 __ testptr(tmp, TypeEntries::type_mask);
3732 __ jcc(Assembler::zero, ok);
3733
3734 __ stop("unexpected profiling mismatch");
3735 __ bind(ok);
3736 __ pop(tmp);
3737 }
3738 #else
3739 __ jccb(Assembler::zero, next);
3740 #endif
3741 // first time here. Set profile type.
3742 __ movptr(mdo_addr, tmp);
3743 } else {
3744 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3745 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3746
3747 __ movptr(tmp, mdo_addr);
3748 __ testptr(tmp, TypeEntries::type_unknown);
3749 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3750
3751 __ orptr(mdo_addr, TypeEntries::type_unknown);
3752 }
3753 }
3754
3755 __ bind(next);
3756 }
3757 }
3758
3759 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3760 Unimplemented();
3761 }
3762
3763
3764 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3765 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3766 }
3767
3768
3769 void LIR_Assembler::align_backward_branch_target() {
3770 __ align(BytesPerWord);
3771 }
3772
3773
3774 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3775 if (left->is_single_cpu()) {
3776 __ negl(left->as_register());
3777 move_regs(left->as_register(), dest->as_register());
3778
3779 } else if (left->is_double_cpu()) {
3780 Register lo = left->as_register_lo();
3781 #ifdef _LP64
3782 Register dst = dest->as_register_lo();
3783 __ movptr(dst, lo);
3784 __ negptr(dst);
3785 #else
3786 Register hi = left->as_register_hi();
3787 __ lneg(hi, lo);
3788 if (dest->as_register_lo() == hi) {
3789 assert(dest->as_register_hi() != lo, "destroying register");
3790 move_regs(hi, dest->as_register_hi());
3791 move_regs(lo, dest->as_register_lo());
3792 } else {
3793 move_regs(lo, dest->as_register_lo());
3794 move_regs(hi, dest->as_register_hi());
3795 }
3796 #endif // _LP64
3797
3798 } else if (dest->is_single_xmm()) {
3799 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3800 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3801 }
3802 if (UseAVX > 1) {
3803 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3804 ExternalAddress((address)float_signflip_pool));
3805 } else {
3806 __ xorps(dest->as_xmm_float_reg(),
3807 ExternalAddress((address)float_signflip_pool));
3808 }
3809 } else if (dest->is_double_xmm()) {
3810 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3811 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3812 }
3813 if (UseAVX > 1) {
3814 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3815 ExternalAddress((address)double_signflip_pool));
3816 } else {
3817 __ xorpd(dest->as_xmm_double_reg(),
3818 ExternalAddress((address)double_signflip_pool));
3819 }
3820 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3821 assert(left->fpu() == 0, "arg must be on TOS");
3822 assert(dest->fpu() == 0, "dest must be TOS");
3823 __ fchs();
3824
3825 } else {
3826 ShouldNotReachHere();
3827 }
3828 }
3829
3830
3831 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3832 assert(addr->is_address() && dest->is_register(), "check");
3833 Register reg;
3834 reg = dest->as_pointer_register();
3835 __ lea(reg, as_Address(addr->as_address_ptr()));
3836 }
3837
3838
3839
3840 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3841 assert(!tmp->is_valid(), "don't need temporary");
3842 __ call(RuntimeAddress(dest));
3843 if (info != NULL) {
3844 add_call_info_here(info);
3845 }
3846 }
3847
3848
3849 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3850 assert(type == T_LONG, "only for volatile long fields");
3851
3852 if (info != NULL) {
3853 add_debug_info_for_null_check_here(info);
3854 }
3855
3856 if (src->is_double_xmm()) {
3857 if (dest->is_double_cpu()) {
3858 #ifdef _LP64
3859 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3860 #else
3861 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3862 __ psrlq(src->as_xmm_double_reg(), 32);
3863 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3864 #endif // _LP64
3865 } else if (dest->is_double_stack()) {
3866 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3867 } else if (dest->is_address()) {
3868 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3869 } else {
3870 ShouldNotReachHere();
3871 }
3872
3873 } else if (dest->is_double_xmm()) {
3874 if (src->is_double_stack()) {
3875 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3876 } else if (src->is_address()) {
3877 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3878 } else {
3879 ShouldNotReachHere();
3880 }
3881
3882 } else if (src->is_double_fpu()) {
3883 assert(src->fpu_regnrLo() == 0, "must be TOS");
3884 if (dest->is_double_stack()) {
3885 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3886 } else if (dest->is_address()) {
3887 __ fistp_d(as_Address(dest->as_address_ptr()));
3888 } else {
3889 ShouldNotReachHere();
3890 }
3891
3892 } else if (dest->is_double_fpu()) {
3893 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3894 if (src->is_double_stack()) {
3895 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3896 } else if (src->is_address()) {
3897 __ fild_d(as_Address(src->as_address_ptr()));
3898 } else {
3899 ShouldNotReachHere();
3900 }
3901 } else {
3902 ShouldNotReachHere();
3903 }
3904 }
3905
3906 #ifdef ASSERT
3907 // emit run-time assertion
3908 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3909 assert(op->code() == lir_assert, "must be");
3910
3911 if (op->in_opr1()->is_valid()) {
3912 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3913 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3914 } else {
3915 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3916 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3917 }
3918
3919 Label ok;
3920 if (op->condition() != lir_cond_always) {
3921 Assembler::Condition acond = Assembler::zero;
3922 switch (op->condition()) {
3923 case lir_cond_equal: acond = Assembler::equal; break;
3924 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3925 case lir_cond_less: acond = Assembler::less; break;
3926 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3927 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3928 case lir_cond_greater: acond = Assembler::greater; break;
3929 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3930 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3931 default: ShouldNotReachHere();
3932 }
3933 __ jcc(acond, ok);
3934 }
3935 if (op->halt()) {
3936 const char* str = __ code_string(op->msg());
3937 __ stop(str);
3938 } else {
3939 breakpoint();
3940 }
3941 __ bind(ok);
3942 }
3943 #endif
3944
3945 void LIR_Assembler::membar() {
3946 // QQQ sparc TSO uses this,
3947 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3948 }
3949
3950 void LIR_Assembler::membar_acquire() {
3951 // No x86 machines currently require load fences
3952 }
3953
3954 void LIR_Assembler::membar_release() {
3955 // No x86 machines currently require store fences
3956 }
3957
3958 void LIR_Assembler::membar_loadload() {
3959 // no-op
3960 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3961 }
3962
3963 void LIR_Assembler::membar_storestore() {
3964 // no-op
3965 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3966 }
3967
3968 void LIR_Assembler::membar_loadstore() {
3969 // no-op
3970 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3971 }
3972
3973 void LIR_Assembler::membar_storeload() {
3974 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3975 }
3976
3977 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3978 assert(result_reg->is_register(), "check");
3979 #ifdef _LP64
3980 // __ get_thread(result_reg->as_register_lo());
3981 __ mov(result_reg->as_register(), r15_thread);
3982 #else
3983 __ get_thread(result_reg->as_register());
3984 #endif // _LP64
3985 }
3986
3987
3988 void LIR_Assembler::peephole(LIR_List*) {
3989 // do nothing for now
3990 }
3991
3992 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3993 assert(data == dest, "xchg/xadd uses only 2 operands");
3994
3995 if (data->type() == T_INT) {
3996 if (code == lir_xadd) {
3997 if (os::is_MP()) {
3998 __ lock();
3999 }
4000 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4001 } else {
4002 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4003 }
4004 } else if (data->is_oop()) {
4005 assert (code == lir_xchg, "xadd for oops");
4006 Register obj = data->as_register();
4007 #ifdef _LP64
4008 if (UseCompressedOops) {
4009 __ encode_heap_oop(obj);
4010 __ xchgl(obj, as_Address(src->as_address_ptr()));
4011 __ decode_heap_oop(obj);
4012 } else {
4013 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4014 }
4015 #else
4016 __ xchgl(obj, as_Address(src->as_address_ptr()));
4017 #endif
4018 } else if (data->type() == T_LONG) {
4019 #ifdef _LP64
4020 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4021 if (code == lir_xadd) {
4022 if (os::is_MP()) {
4023 __ lock();
4024 }
4025 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4026 } else {
4027 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4028 }
4029 #else
4030 ShouldNotReachHere();
4031 #endif
4032 } else {
4033 ShouldNotReachHere();
4034 }
4035 }
4036
4037 #undef __