40   #endif
  41 #elif defined(COMPILER1)
  42   // pure C1, 32-bit, small machine
  43   // i486 was the last Intel chip with 16-byte cache line size
  44   #define DEFAULT_CACHE_LINE_SIZE 32
  45 #elif defined(COMPILER2) || defined(SHARK)
  46   #ifdef _LP64
  47     // pure C2, 64-bit, large machine
  48     #define DEFAULT_CACHE_LINE_SIZE 128
  49   #else
  50     // pure C2, 32-bit, medium machine
  51     #define DEFAULT_CACHE_LINE_SIZE 64
  52   #endif
  53 #endif
  54 
  55 #if defined(COMPILER2) && !defined(JAVASE_EMBEDDED)
  56 // Include Restricted Transactional Memory lock eliding optimization
  57 #define INCLUDE_RTM_OPT 1
  58 #endif
  59 




  60 #endif // CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP

  40   #endif
  41 #elif defined(COMPILER1)
  42   // pure C1, 32-bit, small machine
  43   // i486 was the last Intel chip with 16-byte cache line size
  44   #define DEFAULT_CACHE_LINE_SIZE 32
  45 #elif defined(COMPILER2) || defined(SHARK)
  46   #ifdef _LP64
  47     // pure C2, 64-bit, large machine
  48     #define DEFAULT_CACHE_LINE_SIZE 128
  49   #else
  50     // pure C2, 32-bit, medium machine
  51     #define DEFAULT_CACHE_LINE_SIZE 64
  52   #endif
  53 #endif
  54 
  55 #if defined(COMPILER2) && !defined(JAVASE_EMBEDDED)
  56 // Include Restricted Transactional Memory lock eliding optimization
  57 #define INCLUDE_RTM_OPT 1
  58 #endif
  59 
  60 #if defined(LINUX) || defined(SOLARIS) || defined(__APPLE__)
  61 #define SUPPORT_RESERVED_STACK_AREA
  62 #endif
  63 
  64 #endif // CPU_X86_VM_GLOBALDEFINITIONS_X86_HPP