1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 if(UseAVX > 2) {
540 return 0; // vzeroupper is ignored
541 } else {
542 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
543 }
544 }
545
546 // !!!!! Special hack to get all types of calls to specify the byte offset
547 // from the start of the call to the point where the return address
548 // will point.
549 int MachCallStaticJavaNode::ret_addr_offset()
550 {
551 int offset = 5; // 5 bytes from start of call to where return address points
552 offset += clear_avx_size();
553 return offset;
554 }
555
556 int MachCallDynamicJavaNode::ret_addr_offset()
557 {
558 int offset = 15; // 15 bytes from start of call to where return address points
559 offset += clear_avx_size();
560 return offset;
561 }
562
563 int MachCallRuntimeNode::ret_addr_offset() {
564 int offset = 13; // movq r10,#addr; callq (r10)
565 offset += clear_avx_size();
566 return offset;
567 }
568
569 // Indicate if the safepoint node needs the polling page as an input,
570 // it does if the polling page is more than disp32 away.
571 bool SafePointNode::needs_polling_address_input()
572 {
573 return Assembler::is_polling_page_far();
574 }
575
576 //
577 // Compute padding required for nodes which need alignment
578 //
579
580 // The address of the call instruction needs to be 4-byte aligned to
581 // ensure that it does not span a cache line so that it can be patched.
582 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
583 {
584 current_offset += clear_avx_size(); // skip vzeroupper
585 current_offset += 1; // skip call opcode byte
586 return round_to(current_offset, alignment_required()) - current_offset;
587 }
588
589 // The address of the call instruction needs to be 4-byte aligned to
590 // ensure that it does not span a cache line so that it can be patched.
591 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
592 {
593 current_offset += clear_avx_size(); // skip vzeroupper
594 current_offset += 11; // skip movq instruction + call opcode byte
595 return round_to(current_offset, alignment_required()) - current_offset;
596 }
597
598 // EMIT_RM()
599 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
600 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
601 cbuf.insts()->emit_int8(c);
602 }
603
604 // EMIT_CC()
605 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
606 unsigned char c = (unsigned char) (f1 | f2);
607 cbuf.insts()->emit_int8(c);
608 }
609
610 // EMIT_OPCODE()
611 void emit_opcode(CodeBuffer &cbuf, int code) {
612 cbuf.insts()->emit_int8((unsigned char) code);
613 }
614
615 // EMIT_OPCODE() w/ relocation information
616 void emit_opcode(CodeBuffer &cbuf,
617 int code, relocInfo::relocType reloc, int offset, int format)
618 {
619 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
620 emit_opcode(cbuf, code);
621 }
622
623 // EMIT_D8()
624 void emit_d8(CodeBuffer &cbuf, int d8) {
625 cbuf.insts()->emit_int8((unsigned char) d8);
626 }
627
628 // EMIT_D16()
629 void emit_d16(CodeBuffer &cbuf, int d16) {
630 cbuf.insts()->emit_int16(d16);
631 }
632
633 // EMIT_D32()
634 void emit_d32(CodeBuffer &cbuf, int d32) {
635 cbuf.insts()->emit_int32(d32);
636 }
637
638 // EMIT_D64()
639 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
640 cbuf.insts()->emit_int64(d64);
641 }
642
643 // emit 32 bit value and construct relocation entry from relocInfo::relocType
644 void emit_d32_reloc(CodeBuffer& cbuf,
645 int d32,
646 relocInfo::relocType reloc,
647 int format)
648 {
649 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
650 cbuf.relocate(cbuf.insts_mark(), reloc, format);
651 cbuf.insts()->emit_int32(d32);
652 }
653
654 // emit 32 bit value and construct relocation entry from RelocationHolder
655 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
656 #ifdef ASSERT
657 if (rspec.reloc()->type() == relocInfo::oop_type &&
658 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
659 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
660 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
661 }
662 #endif
663 cbuf.relocate(cbuf.insts_mark(), rspec, format);
664 cbuf.insts()->emit_int32(d32);
665 }
666
667 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
668 address next_ip = cbuf.insts_end() + 4;
669 emit_d32_reloc(cbuf, (int) (addr - next_ip),
670 external_word_Relocation::spec(addr),
671 RELOC_DISP32);
672 }
673
674
675 // emit 64 bit value and construct relocation entry from relocInfo::relocType
676 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
677 cbuf.relocate(cbuf.insts_mark(), reloc, format);
678 cbuf.insts()->emit_int64(d64);
679 }
680
681 // emit 64 bit value and construct relocation entry from RelocationHolder
682 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
683 #ifdef ASSERT
684 if (rspec.reloc()->type() == relocInfo::oop_type &&
685 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
686 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
687 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
688 "cannot embed scavengable oops in code");
689 }
690 #endif
691 cbuf.relocate(cbuf.insts_mark(), rspec, format);
692 cbuf.insts()->emit_int64(d64);
693 }
694
695 // Access stack slot for load or store
696 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
697 {
698 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
699 if (-0x80 <= disp && disp < 0x80) {
700 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d8(cbuf, disp); // Displacement // R/M byte
703 } else {
704 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
705 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
706 emit_d32(cbuf, disp); // Displacement // R/M byte
707 }
708 }
709
710 // rRegI ereg, memory mem) %{ // emit_reg_mem
711 void encode_RegMem(CodeBuffer &cbuf,
712 int reg,
713 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
714 {
715 assert(disp_reloc == relocInfo::none, "cannot have disp");
716 int regenc = reg & 7;
717 int baseenc = base & 7;
718 int indexenc = index & 7;
719
720 // There is no index & no scale, use form without SIB byte
721 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
722 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
723 if (disp == 0 && base != RBP_enc && base != R13_enc) {
724 emit_rm(cbuf, 0x0, regenc, baseenc); // *
725 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
726 // If 8-bit displacement, mode 0x1
727 emit_rm(cbuf, 0x1, regenc, baseenc); // *
728 emit_d8(cbuf, disp);
729 } else {
730 // If 32-bit displacement
731 if (base == -1) { // Special flag for absolute address
732 emit_rm(cbuf, 0x0, regenc, 0x5); // *
733 if (disp_reloc != relocInfo::none) {
734 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
735 } else {
736 emit_d32(cbuf, disp);
737 }
738 } else {
739 // Normal base + offset
740 emit_rm(cbuf, 0x2, regenc, baseenc); // *
741 if (disp_reloc != relocInfo::none) {
742 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
743 } else {
744 emit_d32(cbuf, disp);
745 }
746 }
747 }
748 } else {
749 // Else, encode with the SIB byte
750 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
751 if (disp == 0 && base != RBP_enc && base != R13_enc) {
752 // If no displacement
753 emit_rm(cbuf, 0x0, regenc, 0x4); // *
754 emit_rm(cbuf, scale, indexenc, baseenc);
755 } else {
756 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
757 // If 8-bit displacement, mode 0x1
758 emit_rm(cbuf, 0x1, regenc, 0x4); // *
759 emit_rm(cbuf, scale, indexenc, baseenc);
760 emit_d8(cbuf, disp);
761 } else {
762 // If 32-bit displacement
763 if (base == 0x04 ) {
764 emit_rm(cbuf, 0x2, regenc, 0x4);
765 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
766 } else {
767 emit_rm(cbuf, 0x2, regenc, 0x4);
768 emit_rm(cbuf, scale, indexenc, baseenc); // *
769 }
770 if (disp_reloc != relocInfo::none) {
771 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
772 } else {
773 emit_d32(cbuf, disp);
774 }
775 }
776 }
777 }
778 }
779
780 // This could be in MacroAssembler but it's fairly C2 specific
781 void emit_cmpfp_fixup(MacroAssembler& _masm) {
782 Label exit;
783 __ jccb(Assembler::noParity, exit);
784 __ pushf();
785 //
786 // comiss/ucomiss instructions set ZF,PF,CF flags and
787 // zero OF,AF,SF for NaN values.
788 // Fixup flags by zeroing ZF,PF so that compare of NaN
789 // values returns 'less than' result (CF is set).
790 // Leave the rest of flags unchanged.
791 //
792 // 7 6 5 4 3 2 1 0
793 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
794 // 0 0 1 0 1 0 1 1 (0x2B)
795 //
796 __ andq(Address(rsp, 0), 0xffffff2b);
797 __ popf();
798 __ bind(exit);
799 }
800
801 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
802 Label done;
803 __ movl(dst, -1);
804 __ jcc(Assembler::parity, done);
805 __ jcc(Assembler::below, done);
806 __ setb(Assembler::notEqual, dst);
807 __ movzbl(dst, dst);
808 __ bind(done);
809 }
810
811
812 //=============================================================================
813 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
814
815 int Compile::ConstantTable::calculate_table_base_offset() const {
816 return 0; // absolute addressing, no offset
817 }
818
819 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
820 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
821 ShouldNotReachHere();
822 }
823
824 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
825 // Empty encoding
826 }
827
828 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
829 return 0;
830 }
831
832 #ifndef PRODUCT
833 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
834 st->print("# MachConstantBaseNode (empty encoding)");
835 }
836 #endif
837
838
839 //=============================================================================
840 #ifndef PRODUCT
841 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
842 Compile* C = ra_->C;
843
844 int framesize = C->frame_size_in_bytes();
845 int bangsize = C->bang_size_in_bytes();
846 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
847 // Remove wordSize for return addr which is already pushed.
848 framesize -= wordSize;
849
850 if (C->need_stack_bang(bangsize)) {
851 framesize -= wordSize;
852 st->print("# stack bang (%d bytes)", bangsize);
853 st->print("\n\t");
854 st->print("pushq rbp\t# Save rbp");
855 if (PreserveFramePointer) {
856 st->print("\n\t");
857 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
858 }
859 if (framesize) {
860 st->print("\n\t");
861 st->print("subq rsp, #%d\t# Create frame",framesize);
862 }
863 } else {
864 st->print("subq rsp, #%d\t# Create frame",framesize);
865 st->print("\n\t");
866 framesize -= wordSize;
867 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
868 if (PreserveFramePointer) {
869 st->print("\n\t");
870 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
871 if (framesize > 0) {
872 st->print("\n\t");
873 st->print("addq rbp, #%d", framesize);
874 }
875 }
876 }
877
878 if (VerifyStackAtCalls) {
879 st->print("\n\t");
880 framesize -= wordSize;
881 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
882 #ifdef ASSERT
883 st->print("\n\t");
884 st->print("# stack alignment check");
885 #endif
886 }
887 st->cr();
888 }
889 #endif
890
891 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
892 Compile* C = ra_->C;
893 MacroAssembler _masm(&cbuf);
894
895 int framesize = C->frame_size_in_bytes();
896 int bangsize = C->bang_size_in_bytes();
897
898 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
899
900 C->set_frame_complete(cbuf.insts_size());
901
902 if (C->has_mach_constant_base_node()) {
903 // NOTE: We set the table base offset here because users might be
904 // emitted before MachConstantBaseNode.
905 Compile::ConstantTable& constant_table = C->constant_table();
906 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
907 }
908 }
909
910 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
911 {
912 return MachNode::size(ra_); // too many variables; just compute it
913 // the hard way
914 }
915
916 int MachPrologNode::reloc() const
917 {
918 return 0; // a large enough number
919 }
920
921 //=============================================================================
922 #ifndef PRODUCT
923 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
924 {
925 Compile* C = ra_->C;
926 if (C->max_vector_size() > 16) {
927 st->print("vzeroupper");
928 st->cr(); st->print("\t");
929 }
930
931 int framesize = C->frame_size_in_bytes();
932 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
933 // Remove word for return adr already pushed
934 // and RBP
935 framesize -= 2*wordSize;
936
937 if (framesize) {
938 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
939 st->print("\t");
940 }
941
942 st->print_cr("popq rbp");
943 if (do_polling() && C->is_method_compilation()) {
944 st->print("\t");
945 if (Assembler::is_polling_page_far()) {
946 st->print_cr("movq rscratch1, #polling_page_address\n\t"
947 "testl rax, [rscratch1]\t"
948 "# Safepoint: poll for GC");
949 } else {
950 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
951 "# Safepoint: poll for GC");
952 }
953 }
954 }
955 #endif
956
957 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
958 {
959 Compile* C = ra_->C;
960 MacroAssembler _masm(&cbuf);
961
962 if (C->max_vector_size() > 16) {
963 // Clear upper bits of YMM registers when current compiled code uses
964 // wide vectors to avoid AVX <-> SSE transition penalty during call.
965 __ vzeroupper();
966 }
967
968 int framesize = C->frame_size_in_bytes();
969 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
970 // Remove word for return adr already pushed
971 // and RBP
972 framesize -= 2*wordSize;
973
974 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
975
976 if (framesize) {
977 emit_opcode(cbuf, Assembler::REX_W);
978 if (framesize < 0x80) {
979 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
981 emit_d8(cbuf, framesize);
982 } else {
983 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
984 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
985 emit_d32(cbuf, framesize);
986 }
987 }
988
989 // popq rbp
990 emit_opcode(cbuf, 0x58 | RBP_enc);
991
992 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
993 __ reserved_stack_check();
994 }
995
996 if (do_polling() && C->is_method_compilation()) {
997 MacroAssembler _masm(&cbuf);
998 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
999 if (Assembler::is_polling_page_far()) {
1000 __ lea(rscratch1, polling_page);
1001 __ relocate(relocInfo::poll_return_type);
1002 __ testl(rax, Address(rscratch1, 0));
1003 } else {
1004 __ testl(rax, polling_page);
1005 }
1006 }
1007 }
1008
1009 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1010 {
1011 return MachNode::size(ra_); // too many variables; just compute it
1012 // the hard way
1013 }
1014
1015 int MachEpilogNode::reloc() const
1016 {
1017 return 2; // a large enough number
1018 }
1019
1020 const Pipeline* MachEpilogNode::pipeline() const
1021 {
1022 return MachNode::pipeline_class();
1023 }
1024
1025 int MachEpilogNode::safepoint_offset() const
1026 {
1027 return 0;
1028 }
1029
1030 //=============================================================================
1031
1032 enum RC {
1033 rc_bad,
1034 rc_int,
1035 rc_float,
1036 rc_stack
1037 };
1038
1039 static enum RC rc_class(OptoReg::Name reg)
1040 {
1041 if( !OptoReg::is_valid(reg) ) return rc_bad;
1042
1043 if (OptoReg::is_stack(reg)) return rc_stack;
1044
1045 VMReg r = OptoReg::as_VMReg(reg);
1046
1047 if (r->is_Register()) return rc_int;
1048
1049 assert(r->is_XMMRegister(), "must be");
1050 return rc_float;
1051 }
1052
1053 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1054 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1055 int src_hi, int dst_hi, uint ireg, outputStream* st);
1056
1057 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1058 int stack_offset, int reg, uint ireg, outputStream* st);
1059
1060 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1061 int dst_offset, uint ireg, outputStream* st) {
1062 if (cbuf) {
1063 MacroAssembler _masm(cbuf);
1064 switch (ireg) {
1065 case Op_VecS:
1066 __ movq(Address(rsp, -8), rax);
1067 __ movl(rax, Address(rsp, src_offset));
1068 __ movl(Address(rsp, dst_offset), rax);
1069 __ movq(rax, Address(rsp, -8));
1070 break;
1071 case Op_VecD:
1072 __ pushq(Address(rsp, src_offset));
1073 __ popq (Address(rsp, dst_offset));
1074 break;
1075 case Op_VecX:
1076 __ pushq(Address(rsp, src_offset));
1077 __ popq (Address(rsp, dst_offset));
1078 __ pushq(Address(rsp, src_offset+8));
1079 __ popq (Address(rsp, dst_offset+8));
1080 break;
1081 case Op_VecY:
1082 __ vmovdqu(Address(rsp, -32), xmm0);
1083 __ vmovdqu(xmm0, Address(rsp, src_offset));
1084 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1085 __ vmovdqu(xmm0, Address(rsp, -32));
1086 case Op_VecZ:
1087 __ evmovdqul(Address(rsp, -64), xmm0, 2);
1088 __ evmovdqul(xmm0, Address(rsp, src_offset), 2);
1089 __ evmovdqul(Address(rsp, dst_offset), xmm0, 2);
1090 __ evmovdqul(xmm0, Address(rsp, -64), 2);
1091 break;
1092 default:
1093 ShouldNotReachHere();
1094 }
1095 #ifndef PRODUCT
1096 } else {
1097 switch (ireg) {
1098 case Op_VecS:
1099 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1100 "movl rax, [rsp + #%d]\n\t"
1101 "movl [rsp + #%d], rax\n\t"
1102 "movq rax, [rsp - #8]",
1103 src_offset, dst_offset);
1104 break;
1105 case Op_VecD:
1106 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1107 "popq [rsp + #%d]",
1108 src_offset, dst_offset);
1109 break;
1110 case Op_VecX:
1111 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1112 "popq [rsp + #%d]\n\t"
1113 "pushq [rsp + #%d]\n\t"
1114 "popq [rsp + #%d]",
1115 src_offset, dst_offset, src_offset+8, dst_offset+8);
1116 break;
1117 case Op_VecY:
1118 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1119 "vmovdqu xmm0, [rsp + #%d]\n\t"
1120 "vmovdqu [rsp + #%d], xmm0\n\t"
1121 "vmovdqu xmm0, [rsp - #32]",
1122 src_offset, dst_offset);
1123 break;
1124 case Op_VecZ:
1125 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1126 "vmovdqu xmm0, [rsp + #%d]\n\t"
1127 "vmovdqu [rsp + #%d], xmm0\n\t"
1128 "vmovdqu xmm0, [rsp - #64]",
1129 src_offset, dst_offset);
1130 break;
1131 default:
1132 ShouldNotReachHere();
1133 }
1134 #endif
1135 }
1136 }
1137
1138 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1139 PhaseRegAlloc* ra_,
1140 bool do_size,
1141 outputStream* st) const {
1142 assert(cbuf != NULL || st != NULL, "sanity");
1143 // Get registers to move
1144 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1145 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1146 OptoReg::Name dst_second = ra_->get_reg_second(this);
1147 OptoReg::Name dst_first = ra_->get_reg_first(this);
1148
1149 enum RC src_second_rc = rc_class(src_second);
1150 enum RC src_first_rc = rc_class(src_first);
1151 enum RC dst_second_rc = rc_class(dst_second);
1152 enum RC dst_first_rc = rc_class(dst_first);
1153
1154 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1155 "must move at least 1 register" );
1156
1157 if (src_first == dst_first && src_second == dst_second) {
1158 // Self copy, no move
1159 return 0;
1160 }
1161 if (bottom_type()->isa_vect() != NULL) {
1162 uint ireg = ideal_reg();
1163 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1164 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1165 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1166 // mem -> mem
1167 int src_offset = ra_->reg2offset(src_first);
1168 int dst_offset = ra_->reg2offset(dst_first);
1169 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1170 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1171 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1172 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1173 int stack_offset = ra_->reg2offset(dst_first);
1174 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1175 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1176 int stack_offset = ra_->reg2offset(src_first);
1177 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1178 } else {
1179 ShouldNotReachHere();
1180 }
1181 return 0;
1182 }
1183 if (src_first_rc == rc_stack) {
1184 // mem ->
1185 if (dst_first_rc == rc_stack) {
1186 // mem -> mem
1187 assert(src_second != dst_first, "overlap");
1188 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1189 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1190 // 64-bit
1191 int src_offset = ra_->reg2offset(src_first);
1192 int dst_offset = ra_->reg2offset(dst_first);
1193 if (cbuf) {
1194 MacroAssembler _masm(cbuf);
1195 __ pushq(Address(rsp, src_offset));
1196 __ popq (Address(rsp, dst_offset));
1197 #ifndef PRODUCT
1198 } else {
1199 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1200 "popq [rsp + #%d]",
1201 src_offset, dst_offset);
1202 #endif
1203 }
1204 } else {
1205 // 32-bit
1206 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1207 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1208 // No pushl/popl, so:
1209 int src_offset = ra_->reg2offset(src_first);
1210 int dst_offset = ra_->reg2offset(dst_first);
1211 if (cbuf) {
1212 MacroAssembler _masm(cbuf);
1213 __ movq(Address(rsp, -8), rax);
1214 __ movl(rax, Address(rsp, src_offset));
1215 __ movl(Address(rsp, dst_offset), rax);
1216 __ movq(rax, Address(rsp, -8));
1217 #ifndef PRODUCT
1218 } else {
1219 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1220 "movl rax, [rsp + #%d]\n\t"
1221 "movl [rsp + #%d], rax\n\t"
1222 "movq rax, [rsp - #8]",
1223 src_offset, dst_offset);
1224 #endif
1225 }
1226 }
1227 return 0;
1228 } else if (dst_first_rc == rc_int) {
1229 // mem -> gpr
1230 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1231 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1232 // 64-bit
1233 int offset = ra_->reg2offset(src_first);
1234 if (cbuf) {
1235 MacroAssembler _masm(cbuf);
1236 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1237 #ifndef PRODUCT
1238 } else {
1239 st->print("movq %s, [rsp + #%d]\t# spill",
1240 Matcher::regName[dst_first],
1241 offset);
1242 #endif
1243 }
1244 } else {
1245 // 32-bit
1246 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1247 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1248 int offset = ra_->reg2offset(src_first);
1249 if (cbuf) {
1250 MacroAssembler _masm(cbuf);
1251 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1252 #ifndef PRODUCT
1253 } else {
1254 st->print("movl %s, [rsp + #%d]\t# spill",
1255 Matcher::regName[dst_first],
1256 offset);
1257 #endif
1258 }
1259 }
1260 return 0;
1261 } else if (dst_first_rc == rc_float) {
1262 // mem-> xmm
1263 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1264 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1265 // 64-bit
1266 int offset = ra_->reg2offset(src_first);
1267 if (cbuf) {
1268 MacroAssembler _masm(cbuf);
1269 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1270 #ifndef PRODUCT
1271 } else {
1272 st->print("%s %s, [rsp + #%d]\t# spill",
1273 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1274 Matcher::regName[dst_first],
1275 offset);
1276 #endif
1277 }
1278 } else {
1279 // 32-bit
1280 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1281 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1282 int offset = ra_->reg2offset(src_first);
1283 if (cbuf) {
1284 MacroAssembler _masm(cbuf);
1285 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1286 #ifndef PRODUCT
1287 } else {
1288 st->print("movss %s, [rsp + #%d]\t# spill",
1289 Matcher::regName[dst_first],
1290 offset);
1291 #endif
1292 }
1293 }
1294 return 0;
1295 }
1296 } else if (src_first_rc == rc_int) {
1297 // gpr ->
1298 if (dst_first_rc == rc_stack) {
1299 // gpr -> mem
1300 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1301 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1302 // 64-bit
1303 int offset = ra_->reg2offset(dst_first);
1304 if (cbuf) {
1305 MacroAssembler _masm(cbuf);
1306 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1307 #ifndef PRODUCT
1308 } else {
1309 st->print("movq [rsp + #%d], %s\t# spill",
1310 offset,
1311 Matcher::regName[src_first]);
1312 #endif
1313 }
1314 } else {
1315 // 32-bit
1316 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1317 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1318 int offset = ra_->reg2offset(dst_first);
1319 if (cbuf) {
1320 MacroAssembler _masm(cbuf);
1321 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1322 #ifndef PRODUCT
1323 } else {
1324 st->print("movl [rsp + #%d], %s\t# spill",
1325 offset,
1326 Matcher::regName[src_first]);
1327 #endif
1328 }
1329 }
1330 return 0;
1331 } else if (dst_first_rc == rc_int) {
1332 // gpr -> gpr
1333 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1334 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1335 // 64-bit
1336 if (cbuf) {
1337 MacroAssembler _masm(cbuf);
1338 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1339 as_Register(Matcher::_regEncode[src_first]));
1340 #ifndef PRODUCT
1341 } else {
1342 st->print("movq %s, %s\t# spill",
1343 Matcher::regName[dst_first],
1344 Matcher::regName[src_first]);
1345 #endif
1346 }
1347 return 0;
1348 } else {
1349 // 32-bit
1350 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1351 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1352 if (cbuf) {
1353 MacroAssembler _masm(cbuf);
1354 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1355 as_Register(Matcher::_regEncode[src_first]));
1356 #ifndef PRODUCT
1357 } else {
1358 st->print("movl %s, %s\t# spill",
1359 Matcher::regName[dst_first],
1360 Matcher::regName[src_first]);
1361 #endif
1362 }
1363 return 0;
1364 }
1365 } else if (dst_first_rc == rc_float) {
1366 // gpr -> xmm
1367 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1368 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1369 // 64-bit
1370 if (cbuf) {
1371 MacroAssembler _masm(cbuf);
1372 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1373 #ifndef PRODUCT
1374 } else {
1375 st->print("movdq %s, %s\t# spill",
1376 Matcher::regName[dst_first],
1377 Matcher::regName[src_first]);
1378 #endif
1379 }
1380 } else {
1381 // 32-bit
1382 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1383 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1384 if (cbuf) {
1385 MacroAssembler _masm(cbuf);
1386 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1387 #ifndef PRODUCT
1388 } else {
1389 st->print("movdl %s, %s\t# spill",
1390 Matcher::regName[dst_first],
1391 Matcher::regName[src_first]);
1392 #endif
1393 }
1394 }
1395 return 0;
1396 }
1397 } else if (src_first_rc == rc_float) {
1398 // xmm ->
1399 if (dst_first_rc == rc_stack) {
1400 // xmm -> mem
1401 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1402 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1403 // 64-bit
1404 int offset = ra_->reg2offset(dst_first);
1405 if (cbuf) {
1406 MacroAssembler _masm(cbuf);
1407 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1408 #ifndef PRODUCT
1409 } else {
1410 st->print("movsd [rsp + #%d], %s\t# spill",
1411 offset,
1412 Matcher::regName[src_first]);
1413 #endif
1414 }
1415 } else {
1416 // 32-bit
1417 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1418 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1419 int offset = ra_->reg2offset(dst_first);
1420 if (cbuf) {
1421 MacroAssembler _masm(cbuf);
1422 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1423 #ifndef PRODUCT
1424 } else {
1425 st->print("movss [rsp + #%d], %s\t# spill",
1426 offset,
1427 Matcher::regName[src_first]);
1428 #endif
1429 }
1430 }
1431 return 0;
1432 } else if (dst_first_rc == rc_int) {
1433 // xmm -> gpr
1434 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1435 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1436 // 64-bit
1437 if (cbuf) {
1438 MacroAssembler _masm(cbuf);
1439 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1440 #ifndef PRODUCT
1441 } else {
1442 st->print("movdq %s, %s\t# spill",
1443 Matcher::regName[dst_first],
1444 Matcher::regName[src_first]);
1445 #endif
1446 }
1447 } else {
1448 // 32-bit
1449 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1450 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1451 if (cbuf) {
1452 MacroAssembler _masm(cbuf);
1453 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1454 #ifndef PRODUCT
1455 } else {
1456 st->print("movdl %s, %s\t# spill",
1457 Matcher::regName[dst_first],
1458 Matcher::regName[src_first]);
1459 #endif
1460 }
1461 }
1462 return 0;
1463 } else if (dst_first_rc == rc_float) {
1464 // xmm -> xmm
1465 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1466 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1467 // 64-bit
1468 if (cbuf) {
1469 MacroAssembler _masm(cbuf);
1470 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1471 #ifndef PRODUCT
1472 } else {
1473 st->print("%s %s, %s\t# spill",
1474 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1475 Matcher::regName[dst_first],
1476 Matcher::regName[src_first]);
1477 #endif
1478 }
1479 } else {
1480 // 32-bit
1481 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1482 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1483 if (cbuf) {
1484 MacroAssembler _masm(cbuf);
1485 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1486 #ifndef PRODUCT
1487 } else {
1488 st->print("%s %s, %s\t# spill",
1489 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1490 Matcher::regName[dst_first],
1491 Matcher::regName[src_first]);
1492 #endif
1493 }
1494 }
1495 return 0;
1496 }
1497 }
1498
1499 assert(0," foo ");
1500 Unimplemented();
1501 return 0;
1502 }
1503
1504 #ifndef PRODUCT
1505 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1506 implementation(NULL, ra_, false, st);
1507 }
1508 #endif
1509
1510 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1511 implementation(&cbuf, ra_, false, NULL);
1512 }
1513
1514 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1515 return MachNode::size(ra_);
1516 }
1517
1518 //=============================================================================
1519 #ifndef PRODUCT
1520 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1521 {
1522 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1523 int reg = ra_->get_reg_first(this);
1524 st->print("leaq %s, [rsp + #%d]\t# box lock",
1525 Matcher::regName[reg], offset);
1526 }
1527 #endif
1528
1529 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1530 {
1531 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1532 int reg = ra_->get_encode(this);
1533 if (offset >= 0x80) {
1534 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1535 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1536 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1537 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1538 emit_d32(cbuf, offset);
1539 } else {
1540 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1541 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1542 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1543 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1544 emit_d8(cbuf, offset);
1545 }
1546 }
1547
1548 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1549 {
1550 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1551 return (offset < 0x80) ? 5 : 8; // REX
1552 }
1553
1554 //=============================================================================
1555 #ifndef PRODUCT
1556 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1557 {
1558 if (UseCompressedClassPointers) {
1559 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1560 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1561 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1562 } else {
1563 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1564 "# Inline cache check");
1565 }
1566 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1567 st->print_cr("\tnop\t# nops to align entry point");
1568 }
1569 #endif
1570
1571 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1572 {
1573 MacroAssembler masm(&cbuf);
1574 uint insts_size = cbuf.insts_size();
1575 if (UseCompressedClassPointers) {
1576 masm.load_klass(rscratch1, j_rarg0);
1577 masm.cmpptr(rax, rscratch1);
1578 } else {
1579 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1580 }
1581
1582 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1583
1584 /* WARNING these NOPs are critical so that verified entry point is properly
1585 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1586 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1587 if (OptoBreakpoint) {
1588 // Leave space for int3
1589 nops_cnt -= 1;
1590 }
1591 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1592 if (nops_cnt > 0)
1593 masm.nop(nops_cnt);
1594 }
1595
1596 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1597 {
1598 return MachNode::size(ra_); // too many variables; just compute it
1599 // the hard way
1600 }
1601
1602
1603 //=============================================================================
1604
1605 int Matcher::regnum_to_fpu_offset(int regnum)
1606 {
1607 return regnum - 32; // The FP registers are in the second chunk
1608 }
1609
1610 // This is UltraSparc specific, true just means we have fast l2f conversion
1611 const bool Matcher::convL2FSupported(void) {
1612 return true;
1613 }
1614
1615 // Is this branch offset short enough that a short branch can be used?
1616 //
1617 // NOTE: If the platform does not provide any short branch variants, then
1618 // this method should return false for offset 0.
1619 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1620 // The passed offset is relative to address of the branch.
1621 // On 86 a branch displacement is calculated relative to address
1622 // of a next instruction.
1623 offset -= br_size;
1624
1625 // the short version of jmpConUCF2 contains multiple branches,
1626 // making the reach slightly less
1627 if (rule == jmpConUCF2_rule)
1628 return (-126 <= offset && offset <= 125);
1629 return (-128 <= offset && offset <= 127);
1630 }
1631
1632 const bool Matcher::isSimpleConstant64(jlong value) {
1633 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1634 //return value == (int) value; // Cf. storeImmL and immL32.
1635
1636 // Probably always true, even if a temp register is required.
1637 return true;
1638 }
1639
1640 // The ecx parameter to rep stosq for the ClearArray node is in words.
1641 const bool Matcher::init_array_count_is_in_bytes = false;
1642
1643 // Threshold size for cleararray.
1644 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1645
1646 // No additional cost for CMOVL.
1647 const int Matcher::long_cmove_cost() { return 0; }
1648
1649 // No CMOVF/CMOVD with SSE2
1650 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1651
1652 // Does the CPU require late expand (see block.cpp for description of late expand)?
1653 const bool Matcher::require_postalloc_expand = false;
1654
1655 // Should the Matcher clone shifts on addressing modes, expecting them
1656 // to be subsumed into complex addressing expressions or compute them
1657 // into registers? True for Intel but false for most RISCs
1658 const bool Matcher::clone_shift_expressions = true;
1659
1660 // Do we need to mask the count passed to shift instructions or does
1661 // the cpu only look at the lower 5/6 bits anyway?
1662 const bool Matcher::need_masked_shift_count = false;
1663
1664 bool Matcher::narrow_oop_use_complex_address() {
1665 assert(UseCompressedOops, "only for compressed oops code");
1666 return (LogMinObjAlignmentInBytes <= 3);
1667 }
1668
1669 bool Matcher::narrow_klass_use_complex_address() {
1670 assert(UseCompressedClassPointers, "only for compressed klass code");
1671 return (LogKlassAlignmentInBytes <= 3);
1672 }
1673
1674 // Is it better to copy float constants, or load them directly from
1675 // memory? Intel can load a float constant from a direct address,
1676 // requiring no extra registers. Most RISCs will have to materialize
1677 // an address into a register first, so they would do better to copy
1678 // the constant from stack.
1679 const bool Matcher::rematerialize_float_constants = true; // XXX
1680
1681 // If CPU can load and store mis-aligned doubles directly then no
1682 // fixup is needed. Else we split the double into 2 integer pieces
1683 // and move it piece-by-piece. Only happens when passing doubles into
1684 // C code as the Java calling convention forces doubles to be aligned.
1685 const bool Matcher::misaligned_doubles_ok = true;
1686
1687 // No-op on amd64
1688 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1689
1690 // Advertise here if the CPU requires explicit rounding operations to
1691 // implement the UseStrictFP mode.
1692 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1693
1694 // Are floats conerted to double when stored to stack during deoptimization?
1695 // On x64 it is stored without convertion so we can use normal access.
1696 bool Matcher::float_in_double() { return false; }
1697
1698 // Do ints take an entire long register or just half?
1699 const bool Matcher::int_in_long = true;
1700
1701 // Return whether or not this register is ever used as an argument.
1702 // This function is used on startup to build the trampoline stubs in
1703 // generateOptoStub. Registers not mentioned will be killed by the VM
1704 // call in the trampoline, and arguments in those registers not be
1705 // available to the callee.
1706 bool Matcher::can_be_java_arg(int reg)
1707 {
1708 return
1709 reg == RDI_num || reg == RDI_H_num ||
1710 reg == RSI_num || reg == RSI_H_num ||
1711 reg == RDX_num || reg == RDX_H_num ||
1712 reg == RCX_num || reg == RCX_H_num ||
1713 reg == R8_num || reg == R8_H_num ||
1714 reg == R9_num || reg == R9_H_num ||
1715 reg == R12_num || reg == R12_H_num ||
1716 reg == XMM0_num || reg == XMM0b_num ||
1717 reg == XMM1_num || reg == XMM1b_num ||
1718 reg == XMM2_num || reg == XMM2b_num ||
1719 reg == XMM3_num || reg == XMM3b_num ||
1720 reg == XMM4_num || reg == XMM4b_num ||
1721 reg == XMM5_num || reg == XMM5b_num ||
1722 reg == XMM6_num || reg == XMM6b_num ||
1723 reg == XMM7_num || reg == XMM7b_num;
1724 }
1725
1726 bool Matcher::is_spillable_arg(int reg)
1727 {
1728 return can_be_java_arg(reg);
1729 }
1730
1731 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1732 // In 64 bit mode a code which use multiply when
1733 // devisor is constant is faster than hardware
1734 // DIV instruction (it uses MulHiL).
1735 return false;
1736 }
1737
1738 // Register for DIVI projection of divmodI
1739 RegMask Matcher::divI_proj_mask() {
1740 return INT_RAX_REG_mask();
1741 }
1742
1743 // Register for MODI projection of divmodI
1744 RegMask Matcher::modI_proj_mask() {
1745 return INT_RDX_REG_mask();
1746 }
1747
1748 // Register for DIVL projection of divmodL
1749 RegMask Matcher::divL_proj_mask() {
1750 return LONG_RAX_REG_mask();
1751 }
1752
1753 // Register for MODL projection of divmodL
1754 RegMask Matcher::modL_proj_mask() {
1755 return LONG_RDX_REG_mask();
1756 }
1757
1758 // Register for saving SP into on method handle invokes. Not used on x86_64.
1759 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1760 return NO_REG_mask();
1761 }
1762
1763 %}
1764
1765 //----------ENCODING BLOCK-----------------------------------------------------
1766 // This block specifies the encoding classes used by the compiler to
1767 // output byte streams. Encoding classes are parameterized macros
1768 // used by Machine Instruction Nodes in order to generate the bit
1769 // encoding of the instruction. Operands specify their base encoding
1770 // interface with the interface keyword. There are currently
1771 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1772 // COND_INTER. REG_INTER causes an operand to generate a function
1773 // which returns its register number when queried. CONST_INTER causes
1774 // an operand to generate a function which returns the value of the
1775 // constant when queried. MEMORY_INTER causes an operand to generate
1776 // four functions which return the Base Register, the Index Register,
1777 // the Scale Value, and the Offset Value of the operand when queried.
1778 // COND_INTER causes an operand to generate six functions which return
1779 // the encoding code (ie - encoding bits for the instruction)
1780 // associated with each basic boolean condition for a conditional
1781 // instruction.
1782 //
1783 // Instructions specify two basic values for encoding. Again, a
1784 // function is available to check if the constant displacement is an
1785 // oop. They use the ins_encode keyword to specify their encoding
1786 // classes (which must be a sequence of enc_class names, and their
1787 // parameters, specified in the encoding block), and they use the
1788 // opcode keyword to specify, in order, their primary, secondary, and
1789 // tertiary opcode. Only the opcode sections which a particular
1790 // instruction needs for encoding need to be specified.
1791 encode %{
1792 // Build emit functions for each basic byte or larger field in the
1793 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1794 // from C++ code in the enc_class source block. Emit functions will
1795 // live in the main source block for now. In future, we can
1796 // generalize this by adding a syntax that specifies the sizes of
1797 // fields in an order, so that the adlc can build the emit functions
1798 // automagically
1799
1800 // Emit primary opcode
1801 enc_class OpcP
1802 %{
1803 emit_opcode(cbuf, $primary);
1804 %}
1805
1806 // Emit secondary opcode
1807 enc_class OpcS
1808 %{
1809 emit_opcode(cbuf, $secondary);
1810 %}
1811
1812 // Emit tertiary opcode
1813 enc_class OpcT
1814 %{
1815 emit_opcode(cbuf, $tertiary);
1816 %}
1817
1818 // Emit opcode directly
1819 enc_class Opcode(immI d8)
1820 %{
1821 emit_opcode(cbuf, $d8$$constant);
1822 %}
1823
1824 // Emit size prefix
1825 enc_class SizePrefix
1826 %{
1827 emit_opcode(cbuf, 0x66);
1828 %}
1829
1830 enc_class reg(rRegI reg)
1831 %{
1832 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1833 %}
1834
1835 enc_class reg_reg(rRegI dst, rRegI src)
1836 %{
1837 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1838 %}
1839
1840 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1841 %{
1842 emit_opcode(cbuf, $opcode$$constant);
1843 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1844 %}
1845
1846 enc_class cdql_enc(no_rax_rdx_RegI div)
1847 %{
1848 // Full implementation of Java idiv and irem; checks for
1849 // special case as described in JVM spec., p.243 & p.271.
1850 //
1851 // normal case special case
1852 //
1853 // input : rax: dividend min_int
1854 // reg: divisor -1
1855 //
1856 // output: rax: quotient (= rax idiv reg) min_int
1857 // rdx: remainder (= rax irem reg) 0
1858 //
1859 // Code sequnce:
1860 //
1861 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1862 // 5: 75 07/08 jne e <normal>
1863 // 7: 33 d2 xor %edx,%edx
1864 // [div >= 8 -> offset + 1]
1865 // [REX_B]
1866 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1867 // c: 74 03/04 je 11 <done>
1868 // 000000000000000e <normal>:
1869 // e: 99 cltd
1870 // [div >= 8 -> offset + 1]
1871 // [REX_B]
1872 // f: f7 f9 idiv $div
1873 // 0000000000000011 <done>:
1874
1875 // cmp $0x80000000,%eax
1876 emit_opcode(cbuf, 0x3d);
1877 emit_d8(cbuf, 0x00);
1878 emit_d8(cbuf, 0x00);
1879 emit_d8(cbuf, 0x00);
1880 emit_d8(cbuf, 0x80);
1881
1882 // jne e <normal>
1883 emit_opcode(cbuf, 0x75);
1884 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1885
1886 // xor %edx,%edx
1887 emit_opcode(cbuf, 0x33);
1888 emit_d8(cbuf, 0xD2);
1889
1890 // cmp $0xffffffffffffffff,%ecx
1891 if ($div$$reg >= 8) {
1892 emit_opcode(cbuf, Assembler::REX_B);
1893 }
1894 emit_opcode(cbuf, 0x83);
1895 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1896 emit_d8(cbuf, 0xFF);
1897
1898 // je 11 <done>
1899 emit_opcode(cbuf, 0x74);
1900 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1901
1902 // <normal>
1903 // cltd
1904 emit_opcode(cbuf, 0x99);
1905
1906 // idivl (note: must be emitted by the user of this rule)
1907 // <done>
1908 %}
1909
1910 enc_class cdqq_enc(no_rax_rdx_RegL div)
1911 %{
1912 // Full implementation of Java ldiv and lrem; checks for
1913 // special case as described in JVM spec., p.243 & p.271.
1914 //
1915 // normal case special case
1916 //
1917 // input : rax: dividend min_long
1918 // reg: divisor -1
1919 //
1920 // output: rax: quotient (= rax idiv reg) min_long
1921 // rdx: remainder (= rax irem reg) 0
1922 //
1923 // Code sequnce:
1924 //
1925 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1926 // 7: 00 00 80
1927 // a: 48 39 d0 cmp %rdx,%rax
1928 // d: 75 08 jne 17 <normal>
1929 // f: 33 d2 xor %edx,%edx
1930 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1931 // 15: 74 05 je 1c <done>
1932 // 0000000000000017 <normal>:
1933 // 17: 48 99 cqto
1934 // 19: 48 f7 f9 idiv $div
1935 // 000000000000001c <done>:
1936
1937 // mov $0x8000000000000000,%rdx
1938 emit_opcode(cbuf, Assembler::REX_W);
1939 emit_opcode(cbuf, 0xBA);
1940 emit_d8(cbuf, 0x00);
1941 emit_d8(cbuf, 0x00);
1942 emit_d8(cbuf, 0x00);
1943 emit_d8(cbuf, 0x00);
1944 emit_d8(cbuf, 0x00);
1945 emit_d8(cbuf, 0x00);
1946 emit_d8(cbuf, 0x00);
1947 emit_d8(cbuf, 0x80);
1948
1949 // cmp %rdx,%rax
1950 emit_opcode(cbuf, Assembler::REX_W);
1951 emit_opcode(cbuf, 0x39);
1952 emit_d8(cbuf, 0xD0);
1953
1954 // jne 17 <normal>
1955 emit_opcode(cbuf, 0x75);
1956 emit_d8(cbuf, 0x08);
1957
1958 // xor %edx,%edx
1959 emit_opcode(cbuf, 0x33);
1960 emit_d8(cbuf, 0xD2);
1961
1962 // cmp $0xffffffffffffffff,$div
1963 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1964 emit_opcode(cbuf, 0x83);
1965 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1966 emit_d8(cbuf, 0xFF);
1967
1968 // je 1e <done>
1969 emit_opcode(cbuf, 0x74);
1970 emit_d8(cbuf, 0x05);
1971
1972 // <normal>
1973 // cqto
1974 emit_opcode(cbuf, Assembler::REX_W);
1975 emit_opcode(cbuf, 0x99);
1976
1977 // idivq (note: must be emitted by the user of this rule)
1978 // <done>
1979 %}
1980
1981 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1982 enc_class OpcSE(immI imm)
1983 %{
1984 // Emit primary opcode and set sign-extend bit
1985 // Check for 8-bit immediate, and set sign extend bit in opcode
1986 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1987 emit_opcode(cbuf, $primary | 0x02);
1988 } else {
1989 // 32-bit immediate
1990 emit_opcode(cbuf, $primary);
1991 }
1992 %}
1993
1994 enc_class OpcSErm(rRegI dst, immI imm)
1995 %{
1996 // OpcSEr/m
1997 int dstenc = $dst$$reg;
1998 if (dstenc >= 8) {
1999 emit_opcode(cbuf, Assembler::REX_B);
2000 dstenc -= 8;
2001 }
2002 // Emit primary opcode and set sign-extend bit
2003 // Check for 8-bit immediate, and set sign extend bit in opcode
2004 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2005 emit_opcode(cbuf, $primary | 0x02);
2006 } else {
2007 // 32-bit immediate
2008 emit_opcode(cbuf, $primary);
2009 }
2010 // Emit r/m byte with secondary opcode, after primary opcode.
2011 emit_rm(cbuf, 0x3, $secondary, dstenc);
2012 %}
2013
2014 enc_class OpcSErm_wide(rRegL dst, immI imm)
2015 %{
2016 // OpcSEr/m
2017 int dstenc = $dst$$reg;
2018 if (dstenc < 8) {
2019 emit_opcode(cbuf, Assembler::REX_W);
2020 } else {
2021 emit_opcode(cbuf, Assembler::REX_WB);
2022 dstenc -= 8;
2023 }
2024 // Emit primary opcode and set sign-extend bit
2025 // Check for 8-bit immediate, and set sign extend bit in opcode
2026 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2027 emit_opcode(cbuf, $primary | 0x02);
2028 } else {
2029 // 32-bit immediate
2030 emit_opcode(cbuf, $primary);
2031 }
2032 // Emit r/m byte with secondary opcode, after primary opcode.
2033 emit_rm(cbuf, 0x3, $secondary, dstenc);
2034 %}
2035
2036 enc_class Con8or32(immI imm)
2037 %{
2038 // Check for 8-bit immediate, and set sign extend bit in opcode
2039 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2040 $$$emit8$imm$$constant;
2041 } else {
2042 // 32-bit immediate
2043 $$$emit32$imm$$constant;
2044 }
2045 %}
2046
2047 enc_class opc2_reg(rRegI dst)
2048 %{
2049 // BSWAP
2050 emit_cc(cbuf, $secondary, $dst$$reg);
2051 %}
2052
2053 enc_class opc3_reg(rRegI dst)
2054 %{
2055 // BSWAP
2056 emit_cc(cbuf, $tertiary, $dst$$reg);
2057 %}
2058
2059 enc_class reg_opc(rRegI div)
2060 %{
2061 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2062 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2063 %}
2064
2065 enc_class enc_cmov(cmpOp cop)
2066 %{
2067 // CMOV
2068 $$$emit8$primary;
2069 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2070 %}
2071
2072 enc_class enc_PartialSubtypeCheck()
2073 %{
2074 Register Rrdi = as_Register(RDI_enc); // result register
2075 Register Rrax = as_Register(RAX_enc); // super class
2076 Register Rrcx = as_Register(RCX_enc); // killed
2077 Register Rrsi = as_Register(RSI_enc); // sub class
2078 Label miss;
2079 const bool set_cond_codes = true;
2080
2081 MacroAssembler _masm(&cbuf);
2082 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2083 NULL, &miss,
2084 /*set_cond_codes:*/ true);
2085 if ($primary) {
2086 __ xorptr(Rrdi, Rrdi);
2087 }
2088 __ bind(miss);
2089 %}
2090
2091 enc_class clear_avx %{
2092 debug_only(int off0 = cbuf.insts_size());
2093 if (ra_->C->max_vector_size() > 16) {
2094 // Clear upper bits of YMM registers when current compiled code uses
2095 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2096 MacroAssembler _masm(&cbuf);
2097 __ vzeroupper();
2098 }
2099 debug_only(int off1 = cbuf.insts_size());
2100 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2101 %}
2102
2103 enc_class Java_To_Runtime(method meth) %{
2104 // No relocation needed
2105 MacroAssembler _masm(&cbuf);
2106 __ mov64(r10, (int64_t) $meth$$method);
2107 __ call(r10);
2108 %}
2109
2110 enc_class Java_To_Interpreter(method meth)
2111 %{
2112 // CALL Java_To_Interpreter
2113 // This is the instruction starting address for relocation info.
2114 cbuf.set_insts_mark();
2115 $$$emit8$primary;
2116 // CALL directly to the runtime
2117 emit_d32_reloc(cbuf,
2118 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2119 runtime_call_Relocation::spec(),
2120 RELOC_DISP32);
2121 %}
2122
2123 enc_class Java_Static_Call(method meth)
2124 %{
2125 // JAVA STATIC CALL
2126 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2127 // determine who we intended to call.
2128 cbuf.set_insts_mark();
2129 $$$emit8$primary;
2130
2131 if (!_method) {
2132 emit_d32_reloc(cbuf,
2133 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2134 runtime_call_Relocation::spec(),
2135 RELOC_DISP32);
2136 } else if (_optimized_virtual) {
2137 emit_d32_reloc(cbuf,
2138 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2139 opt_virtual_call_Relocation::spec(),
2140 RELOC_DISP32);
2141 } else {
2142 emit_d32_reloc(cbuf,
2143 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2144 static_call_Relocation::spec(),
2145 RELOC_DISP32);
2146 }
2147 if (_method) {
2148 // Emit stubs for static call.
2149 address mark = cbuf.insts_mark();
2150 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2151 if (stub == NULL) {
2152 ciEnv::current()->record_failure("CodeCache is full");
2153 return;
2154 }
2155 }
2156 %}
2157
2158 enc_class Java_Dynamic_Call(method meth) %{
2159 MacroAssembler _masm(&cbuf);
2160 __ ic_call((address)$meth$$method);
2161 %}
2162
2163 enc_class Java_Compiled_Call(method meth)
2164 %{
2165 // JAVA COMPILED CALL
2166 int disp = in_bytes(Method:: from_compiled_offset());
2167
2168 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2169 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2170
2171 // callq *disp(%rax)
2172 cbuf.set_insts_mark();
2173 $$$emit8$primary;
2174 if (disp < 0x80) {
2175 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2176 emit_d8(cbuf, disp); // Displacement
2177 } else {
2178 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2179 emit_d32(cbuf, disp); // Displacement
2180 }
2181 %}
2182
2183 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2184 %{
2185 // SAL, SAR, SHR
2186 int dstenc = $dst$$reg;
2187 if (dstenc >= 8) {
2188 emit_opcode(cbuf, Assembler::REX_B);
2189 dstenc -= 8;
2190 }
2191 $$$emit8$primary;
2192 emit_rm(cbuf, 0x3, $secondary, dstenc);
2193 $$$emit8$shift$$constant;
2194 %}
2195
2196 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2197 %{
2198 // SAL, SAR, SHR
2199 int dstenc = $dst$$reg;
2200 if (dstenc < 8) {
2201 emit_opcode(cbuf, Assembler::REX_W);
2202 } else {
2203 emit_opcode(cbuf, Assembler::REX_WB);
2204 dstenc -= 8;
2205 }
2206 $$$emit8$primary;
2207 emit_rm(cbuf, 0x3, $secondary, dstenc);
2208 $$$emit8$shift$$constant;
2209 %}
2210
2211 enc_class load_immI(rRegI dst, immI src)
2212 %{
2213 int dstenc = $dst$$reg;
2214 if (dstenc >= 8) {
2215 emit_opcode(cbuf, Assembler::REX_B);
2216 dstenc -= 8;
2217 }
2218 emit_opcode(cbuf, 0xB8 | dstenc);
2219 $$$emit32$src$$constant;
2220 %}
2221
2222 enc_class load_immL(rRegL dst, immL src)
2223 %{
2224 int dstenc = $dst$$reg;
2225 if (dstenc < 8) {
2226 emit_opcode(cbuf, Assembler::REX_W);
2227 } else {
2228 emit_opcode(cbuf, Assembler::REX_WB);
2229 dstenc -= 8;
2230 }
2231 emit_opcode(cbuf, 0xB8 | dstenc);
2232 emit_d64(cbuf, $src$$constant);
2233 %}
2234
2235 enc_class load_immUL32(rRegL dst, immUL32 src)
2236 %{
2237 // same as load_immI, but this time we care about zeroes in the high word
2238 int dstenc = $dst$$reg;
2239 if (dstenc >= 8) {
2240 emit_opcode(cbuf, Assembler::REX_B);
2241 dstenc -= 8;
2242 }
2243 emit_opcode(cbuf, 0xB8 | dstenc);
2244 $$$emit32$src$$constant;
2245 %}
2246
2247 enc_class load_immL32(rRegL dst, immL32 src)
2248 %{
2249 int dstenc = $dst$$reg;
2250 if (dstenc < 8) {
2251 emit_opcode(cbuf, Assembler::REX_W);
2252 } else {
2253 emit_opcode(cbuf, Assembler::REX_WB);
2254 dstenc -= 8;
2255 }
2256 emit_opcode(cbuf, 0xC7);
2257 emit_rm(cbuf, 0x03, 0x00, dstenc);
2258 $$$emit32$src$$constant;
2259 %}
2260
2261 enc_class load_immP31(rRegP dst, immP32 src)
2262 %{
2263 // same as load_immI, but this time we care about zeroes in the high word
2264 int dstenc = $dst$$reg;
2265 if (dstenc >= 8) {
2266 emit_opcode(cbuf, Assembler::REX_B);
2267 dstenc -= 8;
2268 }
2269 emit_opcode(cbuf, 0xB8 | dstenc);
2270 $$$emit32$src$$constant;
2271 %}
2272
2273 enc_class load_immP(rRegP dst, immP src)
2274 %{
2275 int dstenc = $dst$$reg;
2276 if (dstenc < 8) {
2277 emit_opcode(cbuf, Assembler::REX_W);
2278 } else {
2279 emit_opcode(cbuf, Assembler::REX_WB);
2280 dstenc -= 8;
2281 }
2282 emit_opcode(cbuf, 0xB8 | dstenc);
2283 // This next line should be generated from ADLC
2284 if ($src->constant_reloc() != relocInfo::none) {
2285 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2286 } else {
2287 emit_d64(cbuf, $src$$constant);
2288 }
2289 %}
2290
2291 enc_class Con32(immI src)
2292 %{
2293 // Output immediate
2294 $$$emit32$src$$constant;
2295 %}
2296
2297 enc_class Con32F_as_bits(immF src)
2298 %{
2299 // Output Float immediate bits
2300 jfloat jf = $src$$constant;
2301 jint jf_as_bits = jint_cast(jf);
2302 emit_d32(cbuf, jf_as_bits);
2303 %}
2304
2305 enc_class Con16(immI src)
2306 %{
2307 // Output immediate
2308 $$$emit16$src$$constant;
2309 %}
2310
2311 // How is this different from Con32??? XXX
2312 enc_class Con_d32(immI src)
2313 %{
2314 emit_d32(cbuf,$src$$constant);
2315 %}
2316
2317 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2318 // Output immediate memory reference
2319 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2320 emit_d32(cbuf, 0x00);
2321 %}
2322
2323 enc_class lock_prefix()
2324 %{
2325 if (os::is_MP()) {
2326 emit_opcode(cbuf, 0xF0); // lock
2327 }
2328 %}
2329
2330 enc_class REX_mem(memory mem)
2331 %{
2332 if ($mem$$base >= 8) {
2333 if ($mem$$index < 8) {
2334 emit_opcode(cbuf, Assembler::REX_B);
2335 } else {
2336 emit_opcode(cbuf, Assembler::REX_XB);
2337 }
2338 } else {
2339 if ($mem$$index >= 8) {
2340 emit_opcode(cbuf, Assembler::REX_X);
2341 }
2342 }
2343 %}
2344
2345 enc_class REX_mem_wide(memory mem)
2346 %{
2347 if ($mem$$base >= 8) {
2348 if ($mem$$index < 8) {
2349 emit_opcode(cbuf, Assembler::REX_WB);
2350 } else {
2351 emit_opcode(cbuf, Assembler::REX_WXB);
2352 }
2353 } else {
2354 if ($mem$$index < 8) {
2355 emit_opcode(cbuf, Assembler::REX_W);
2356 } else {
2357 emit_opcode(cbuf, Assembler::REX_WX);
2358 }
2359 }
2360 %}
2361
2362 // for byte regs
2363 enc_class REX_breg(rRegI reg)
2364 %{
2365 if ($reg$$reg >= 4) {
2366 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2367 }
2368 %}
2369
2370 // for byte regs
2371 enc_class REX_reg_breg(rRegI dst, rRegI src)
2372 %{
2373 if ($dst$$reg < 8) {
2374 if ($src$$reg >= 4) {
2375 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2376 }
2377 } else {
2378 if ($src$$reg < 8) {
2379 emit_opcode(cbuf, Assembler::REX_R);
2380 } else {
2381 emit_opcode(cbuf, Assembler::REX_RB);
2382 }
2383 }
2384 %}
2385
2386 // for byte regs
2387 enc_class REX_breg_mem(rRegI reg, memory mem)
2388 %{
2389 if ($reg$$reg < 8) {
2390 if ($mem$$base < 8) {
2391 if ($mem$$index >= 8) {
2392 emit_opcode(cbuf, Assembler::REX_X);
2393 } else if ($reg$$reg >= 4) {
2394 emit_opcode(cbuf, Assembler::REX);
2395 }
2396 } else {
2397 if ($mem$$index < 8) {
2398 emit_opcode(cbuf, Assembler::REX_B);
2399 } else {
2400 emit_opcode(cbuf, Assembler::REX_XB);
2401 }
2402 }
2403 } else {
2404 if ($mem$$base < 8) {
2405 if ($mem$$index < 8) {
2406 emit_opcode(cbuf, Assembler::REX_R);
2407 } else {
2408 emit_opcode(cbuf, Assembler::REX_RX);
2409 }
2410 } else {
2411 if ($mem$$index < 8) {
2412 emit_opcode(cbuf, Assembler::REX_RB);
2413 } else {
2414 emit_opcode(cbuf, Assembler::REX_RXB);
2415 }
2416 }
2417 }
2418 %}
2419
2420 enc_class REX_reg(rRegI reg)
2421 %{
2422 if ($reg$$reg >= 8) {
2423 emit_opcode(cbuf, Assembler::REX_B);
2424 }
2425 %}
2426
2427 enc_class REX_reg_wide(rRegI reg)
2428 %{
2429 if ($reg$$reg < 8) {
2430 emit_opcode(cbuf, Assembler::REX_W);
2431 } else {
2432 emit_opcode(cbuf, Assembler::REX_WB);
2433 }
2434 %}
2435
2436 enc_class REX_reg_reg(rRegI dst, rRegI src)
2437 %{
2438 if ($dst$$reg < 8) {
2439 if ($src$$reg >= 8) {
2440 emit_opcode(cbuf, Assembler::REX_B);
2441 }
2442 } else {
2443 if ($src$$reg < 8) {
2444 emit_opcode(cbuf, Assembler::REX_R);
2445 } else {
2446 emit_opcode(cbuf, Assembler::REX_RB);
2447 }
2448 }
2449 %}
2450
2451 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2452 %{
2453 if ($dst$$reg < 8) {
2454 if ($src$$reg < 8) {
2455 emit_opcode(cbuf, Assembler::REX_W);
2456 } else {
2457 emit_opcode(cbuf, Assembler::REX_WB);
2458 }
2459 } else {
2460 if ($src$$reg < 8) {
2461 emit_opcode(cbuf, Assembler::REX_WR);
2462 } else {
2463 emit_opcode(cbuf, Assembler::REX_WRB);
2464 }
2465 }
2466 %}
2467
2468 enc_class REX_reg_mem(rRegI reg, memory mem)
2469 %{
2470 if ($reg$$reg < 8) {
2471 if ($mem$$base < 8) {
2472 if ($mem$$index >= 8) {
2473 emit_opcode(cbuf, Assembler::REX_X);
2474 }
2475 } else {
2476 if ($mem$$index < 8) {
2477 emit_opcode(cbuf, Assembler::REX_B);
2478 } else {
2479 emit_opcode(cbuf, Assembler::REX_XB);
2480 }
2481 }
2482 } else {
2483 if ($mem$$base < 8) {
2484 if ($mem$$index < 8) {
2485 emit_opcode(cbuf, Assembler::REX_R);
2486 } else {
2487 emit_opcode(cbuf, Assembler::REX_RX);
2488 }
2489 } else {
2490 if ($mem$$index < 8) {
2491 emit_opcode(cbuf, Assembler::REX_RB);
2492 } else {
2493 emit_opcode(cbuf, Assembler::REX_RXB);
2494 }
2495 }
2496 }
2497 %}
2498
2499 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2500 %{
2501 if ($reg$$reg < 8) {
2502 if ($mem$$base < 8) {
2503 if ($mem$$index < 8) {
2504 emit_opcode(cbuf, Assembler::REX_W);
2505 } else {
2506 emit_opcode(cbuf, Assembler::REX_WX);
2507 }
2508 } else {
2509 if ($mem$$index < 8) {
2510 emit_opcode(cbuf, Assembler::REX_WB);
2511 } else {
2512 emit_opcode(cbuf, Assembler::REX_WXB);
2513 }
2514 }
2515 } else {
2516 if ($mem$$base < 8) {
2517 if ($mem$$index < 8) {
2518 emit_opcode(cbuf, Assembler::REX_WR);
2519 } else {
2520 emit_opcode(cbuf, Assembler::REX_WRX);
2521 }
2522 } else {
2523 if ($mem$$index < 8) {
2524 emit_opcode(cbuf, Assembler::REX_WRB);
2525 } else {
2526 emit_opcode(cbuf, Assembler::REX_WRXB);
2527 }
2528 }
2529 }
2530 %}
2531
2532 enc_class reg_mem(rRegI ereg, memory mem)
2533 %{
2534 // High registers handle in encode_RegMem
2535 int reg = $ereg$$reg;
2536 int base = $mem$$base;
2537 int index = $mem$$index;
2538 int scale = $mem$$scale;
2539 int disp = $mem$$disp;
2540 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2541
2542 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2543 %}
2544
2545 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2546 %{
2547 int rm_byte_opcode = $rm_opcode$$constant;
2548
2549 // High registers handle in encode_RegMem
2550 int base = $mem$$base;
2551 int index = $mem$$index;
2552 int scale = $mem$$scale;
2553 int displace = $mem$$disp;
2554
2555 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2556 // working with static
2557 // globals
2558 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2559 disp_reloc);
2560 %}
2561
2562 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2563 %{
2564 int reg_encoding = $dst$$reg;
2565 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2566 int index = 0x04; // 0x04 indicates no index
2567 int scale = 0x00; // 0x00 indicates no scale
2568 int displace = $src1$$constant; // 0x00 indicates no displacement
2569 relocInfo::relocType disp_reloc = relocInfo::none;
2570 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2571 disp_reloc);
2572 %}
2573
2574 enc_class neg_reg(rRegI dst)
2575 %{
2576 int dstenc = $dst$$reg;
2577 if (dstenc >= 8) {
2578 emit_opcode(cbuf, Assembler::REX_B);
2579 dstenc -= 8;
2580 }
2581 // NEG $dst
2582 emit_opcode(cbuf, 0xF7);
2583 emit_rm(cbuf, 0x3, 0x03, dstenc);
2584 %}
2585
2586 enc_class neg_reg_wide(rRegI dst)
2587 %{
2588 int dstenc = $dst$$reg;
2589 if (dstenc < 8) {
2590 emit_opcode(cbuf, Assembler::REX_W);
2591 } else {
2592 emit_opcode(cbuf, Assembler::REX_WB);
2593 dstenc -= 8;
2594 }
2595 // NEG $dst
2596 emit_opcode(cbuf, 0xF7);
2597 emit_rm(cbuf, 0x3, 0x03, dstenc);
2598 %}
2599
2600 enc_class setLT_reg(rRegI dst)
2601 %{
2602 int dstenc = $dst$$reg;
2603 if (dstenc >= 8) {
2604 emit_opcode(cbuf, Assembler::REX_B);
2605 dstenc -= 8;
2606 } else if (dstenc >= 4) {
2607 emit_opcode(cbuf, Assembler::REX);
2608 }
2609 // SETLT $dst
2610 emit_opcode(cbuf, 0x0F);
2611 emit_opcode(cbuf, 0x9C);
2612 emit_rm(cbuf, 0x3, 0x0, dstenc);
2613 %}
2614
2615 enc_class setNZ_reg(rRegI dst)
2616 %{
2617 int dstenc = $dst$$reg;
2618 if (dstenc >= 8) {
2619 emit_opcode(cbuf, Assembler::REX_B);
2620 dstenc -= 8;
2621 } else if (dstenc >= 4) {
2622 emit_opcode(cbuf, Assembler::REX);
2623 }
2624 // SETNZ $dst
2625 emit_opcode(cbuf, 0x0F);
2626 emit_opcode(cbuf, 0x95);
2627 emit_rm(cbuf, 0x3, 0x0, dstenc);
2628 %}
2629
2630
2631 // Compare the lonogs and set -1, 0, or 1 into dst
2632 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2633 %{
2634 int src1enc = $src1$$reg;
2635 int src2enc = $src2$$reg;
2636 int dstenc = $dst$$reg;
2637
2638 // cmpq $src1, $src2
2639 if (src1enc < 8) {
2640 if (src2enc < 8) {
2641 emit_opcode(cbuf, Assembler::REX_W);
2642 } else {
2643 emit_opcode(cbuf, Assembler::REX_WB);
2644 }
2645 } else {
2646 if (src2enc < 8) {
2647 emit_opcode(cbuf, Assembler::REX_WR);
2648 } else {
2649 emit_opcode(cbuf, Assembler::REX_WRB);
2650 }
2651 }
2652 emit_opcode(cbuf, 0x3B);
2653 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2654
2655 // movl $dst, -1
2656 if (dstenc >= 8) {
2657 emit_opcode(cbuf, Assembler::REX_B);
2658 }
2659 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2660 emit_d32(cbuf, -1);
2661
2662 // jl,s done
2663 emit_opcode(cbuf, 0x7C);
2664 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2665
2666 // setne $dst
2667 if (dstenc >= 4) {
2668 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2669 }
2670 emit_opcode(cbuf, 0x0F);
2671 emit_opcode(cbuf, 0x95);
2672 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2673
2674 // movzbl $dst, $dst
2675 if (dstenc >= 4) {
2676 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2677 }
2678 emit_opcode(cbuf, 0x0F);
2679 emit_opcode(cbuf, 0xB6);
2680 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2681 %}
2682
2683 enc_class Push_ResultXD(regD dst) %{
2684 MacroAssembler _masm(&cbuf);
2685 __ fstp_d(Address(rsp, 0));
2686 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2687 __ addptr(rsp, 8);
2688 %}
2689
2690 enc_class Push_SrcXD(regD src) %{
2691 MacroAssembler _masm(&cbuf);
2692 __ subptr(rsp, 8);
2693 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2694 __ fld_d(Address(rsp, 0));
2695 %}
2696
2697
2698 enc_class enc_rethrow()
2699 %{
2700 cbuf.set_insts_mark();
2701 emit_opcode(cbuf, 0xE9); // jmp entry
2702 emit_d32_reloc(cbuf,
2703 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2704 runtime_call_Relocation::spec(),
2705 RELOC_DISP32);
2706 %}
2707
2708 %}
2709
2710
2711
2712 //----------FRAME--------------------------------------------------------------
2713 // Definition of frame structure and management information.
2714 //
2715 // S T A C K L A Y O U T Allocators stack-slot number
2716 // | (to get allocators register number
2717 // G Owned by | | v add OptoReg::stack0())
2718 // r CALLER | |
2719 // o | +--------+ pad to even-align allocators stack-slot
2720 // w V | pad0 | numbers; owned by CALLER
2721 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2722 // h ^ | in | 5
2723 // | | args | 4 Holes in incoming args owned by SELF
2724 // | | | | 3
2725 // | | +--------+
2726 // V | | old out| Empty on Intel, window on Sparc
2727 // | old |preserve| Must be even aligned.
2728 // | SP-+--------+----> Matcher::_old_SP, even aligned
2729 // | | in | 3 area for Intel ret address
2730 // Owned by |preserve| Empty on Sparc.
2731 // SELF +--------+
2732 // | | pad2 | 2 pad to align old SP
2733 // | +--------+ 1
2734 // | | locks | 0
2735 // | +--------+----> OptoReg::stack0(), even aligned
2736 // | | pad1 | 11 pad to align new SP
2737 // | +--------+
2738 // | | | 10
2739 // | | spills | 9 spills
2740 // V | | 8 (pad0 slot for callee)
2741 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2742 // ^ | out | 7
2743 // | | args | 6 Holes in outgoing args owned by CALLEE
2744 // Owned by +--------+
2745 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2746 // | new |preserve| Must be even-aligned.
2747 // | SP-+--------+----> Matcher::_new_SP, even aligned
2748 // | | |
2749 //
2750 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2751 // known from SELF's arguments and the Java calling convention.
2752 // Region 6-7 is determined per call site.
2753 // Note 2: If the calling convention leaves holes in the incoming argument
2754 // area, those holes are owned by SELF. Holes in the outgoing area
2755 // are owned by the CALLEE. Holes should not be nessecary in the
2756 // incoming area, as the Java calling convention is completely under
2757 // the control of the AD file. Doubles can be sorted and packed to
2758 // avoid holes. Holes in the outgoing arguments may be nessecary for
2759 // varargs C calling conventions.
2760 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2761 // even aligned with pad0 as needed.
2762 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2763 // region 6-11 is even aligned; it may be padded out more so that
2764 // the region from SP to FP meets the minimum stack alignment.
2765 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2766 // alignment. Region 11, pad1, may be dynamically extended so that
2767 // SP meets the minimum alignment.
2768
2769 frame
2770 %{
2771 // What direction does stack grow in (assumed to be same for C & Java)
2772 stack_direction(TOWARDS_LOW);
2773
2774 // These three registers define part of the calling convention
2775 // between compiled code and the interpreter.
2776 inline_cache_reg(RAX); // Inline Cache Register
2777 interpreter_method_oop_reg(RBX); // Method Oop Register when
2778 // calling interpreter
2779
2780 // Optional: name the operand used by cisc-spilling to access
2781 // [stack_pointer + offset]
2782 cisc_spilling_operand_name(indOffset32);
2783
2784 // Number of stack slots consumed by locking an object
2785 sync_stack_slots(2);
2786
2787 // Compiled code's Frame Pointer
2788 frame_pointer(RSP);
2789
2790 // Interpreter stores its frame pointer in a register which is
2791 // stored to the stack by I2CAdaptors.
2792 // I2CAdaptors convert from interpreted java to compiled java.
2793 interpreter_frame_pointer(RBP);
2794
2795 // Stack alignment requirement
2796 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2797
2798 // Number of stack slots between incoming argument block and the start of
2799 // a new frame. The PROLOG must add this many slots to the stack. The
2800 // EPILOG must remove this many slots. amd64 needs two slots for
2801 // return address.
2802 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2803
2804 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2805 // for calls to C. Supports the var-args backing area for register parms.
2806 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2807
2808 // The after-PROLOG location of the return address. Location of
2809 // return address specifies a type (REG or STACK) and a number
2810 // representing the register number (i.e. - use a register name) or
2811 // stack slot.
2812 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2813 // Otherwise, it is above the locks and verification slot and alignment word
2814 return_addr(STACK - 2 +
2815 round_to((Compile::current()->in_preserve_stack_slots() +
2816 Compile::current()->fixed_slots()),
2817 stack_alignment_in_slots()));
2818
2819 // Body of function which returns an integer array locating
2820 // arguments either in registers or in stack slots. Passed an array
2821 // of ideal registers called "sig" and a "length" count. Stack-slot
2822 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2823 // arguments for a CALLEE. Incoming stack arguments are
2824 // automatically biased by the preserve_stack_slots field above.
2825
2826 calling_convention
2827 %{
2828 // No difference between ingoing/outgoing just pass false
2829 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2830 %}
2831
2832 c_calling_convention
2833 %{
2834 // This is obviously always outgoing
2835 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2836 %}
2837
2838 // Location of compiled Java return values. Same as C for now.
2839 return_value
2840 %{
2841 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2842 "only return normal values");
2843
2844 static const int lo[Op_RegL + 1] = {
2845 0,
2846 0,
2847 RAX_num, // Op_RegN
2848 RAX_num, // Op_RegI
2849 RAX_num, // Op_RegP
2850 XMM0_num, // Op_RegF
2851 XMM0_num, // Op_RegD
2852 RAX_num // Op_RegL
2853 };
2854 static const int hi[Op_RegL + 1] = {
2855 0,
2856 0,
2857 OptoReg::Bad, // Op_RegN
2858 OptoReg::Bad, // Op_RegI
2859 RAX_H_num, // Op_RegP
2860 OptoReg::Bad, // Op_RegF
2861 XMM0b_num, // Op_RegD
2862 RAX_H_num // Op_RegL
2863 };
2864 // Excluded flags and vector registers.
2865 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2866 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2867 %}
2868 %}
2869
2870 //----------ATTRIBUTES---------------------------------------------------------
2871 //----------Operand Attributes-------------------------------------------------
2872 op_attrib op_cost(0); // Required cost attribute
2873
2874 //----------Instruction Attributes---------------------------------------------
2875 ins_attrib ins_cost(100); // Required cost attribute
2876 ins_attrib ins_size(8); // Required size attribute (in bits)
2877 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2878 // a non-matching short branch variant
2879 // of some long branch?
2880 ins_attrib ins_alignment(1); // Required alignment attribute (must
2881 // be a power of 2) specifies the
2882 // alignment that some part of the
2883 // instruction (not necessarily the
2884 // start) requires. If > 1, a
2885 // compute_padding() function must be
2886 // provided for the instruction
2887
2888 //----------OPERANDS-----------------------------------------------------------
2889 // Operand definitions must precede instruction definitions for correct parsing
2890 // in the ADLC because operands constitute user defined types which are used in
2891 // instruction definitions.
2892
2893 //----------Simple Operands----------------------------------------------------
2894 // Immediate Operands
2895 // Integer Immediate
2896 operand immI()
2897 %{
2898 match(ConI);
2899
2900 op_cost(10);
2901 format %{ %}
2902 interface(CONST_INTER);
2903 %}
2904
2905 // Constant for test vs zero
2906 operand immI0()
2907 %{
2908 predicate(n->get_int() == 0);
2909 match(ConI);
2910
2911 op_cost(0);
2912 format %{ %}
2913 interface(CONST_INTER);
2914 %}
2915
2916 // Constant for increment
2917 operand immI1()
2918 %{
2919 predicate(n->get_int() == 1);
2920 match(ConI);
2921
2922 op_cost(0);
2923 format %{ %}
2924 interface(CONST_INTER);
2925 %}
2926
2927 // Constant for decrement
2928 operand immI_M1()
2929 %{
2930 predicate(n->get_int() == -1);
2931 match(ConI);
2932
2933 op_cost(0);
2934 format %{ %}
2935 interface(CONST_INTER);
2936 %}
2937
2938 // Valid scale values for addressing modes
2939 operand immI2()
2940 %{
2941 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2942 match(ConI);
2943
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 operand immI8()
2949 %{
2950 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2951 match(ConI);
2952
2953 op_cost(5);
2954 format %{ %}
2955 interface(CONST_INTER);
2956 %}
2957
2958 operand immI16()
2959 %{
2960 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2961 match(ConI);
2962
2963 op_cost(10);
2964 format %{ %}
2965 interface(CONST_INTER);
2966 %}
2967
2968 // Int Immediate non-negative
2969 operand immU31()
2970 %{
2971 predicate(n->get_int() >= 0);
2972 match(ConI);
2973
2974 op_cost(0);
2975 format %{ %}
2976 interface(CONST_INTER);
2977 %}
2978
2979 // Constant for long shifts
2980 operand immI_32()
2981 %{
2982 predicate( n->get_int() == 32 );
2983 match(ConI);
2984
2985 op_cost(0);
2986 format %{ %}
2987 interface(CONST_INTER);
2988 %}
2989
2990 // Constant for long shifts
2991 operand immI_64()
2992 %{
2993 predicate( n->get_int() == 64 );
2994 match(ConI);
2995
2996 op_cost(0);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 // Pointer Immediate
3002 operand immP()
3003 %{
3004 match(ConP);
3005
3006 op_cost(10);
3007 format %{ %}
3008 interface(CONST_INTER);
3009 %}
3010
3011 // NULL Pointer Immediate
3012 operand immP0()
3013 %{
3014 predicate(n->get_ptr() == 0);
3015 match(ConP);
3016
3017 op_cost(5);
3018 format %{ %}
3019 interface(CONST_INTER);
3020 %}
3021
3022 // Pointer Immediate
3023 operand immN() %{
3024 match(ConN);
3025
3026 op_cost(10);
3027 format %{ %}
3028 interface(CONST_INTER);
3029 %}
3030
3031 operand immNKlass() %{
3032 match(ConNKlass);
3033
3034 op_cost(10);
3035 format %{ %}
3036 interface(CONST_INTER);
3037 %}
3038
3039 // NULL Pointer Immediate
3040 operand immN0() %{
3041 predicate(n->get_narrowcon() == 0);
3042 match(ConN);
3043
3044 op_cost(5);
3045 format %{ %}
3046 interface(CONST_INTER);
3047 %}
3048
3049 operand immP31()
3050 %{
3051 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3052 && (n->get_ptr() >> 31) == 0);
3053 match(ConP);
3054
3055 op_cost(5);
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060
3061 // Long Immediate
3062 operand immL()
3063 %{
3064 match(ConL);
3065
3066 op_cost(20);
3067 format %{ %}
3068 interface(CONST_INTER);
3069 %}
3070
3071 // Long Immediate 8-bit
3072 operand immL8()
3073 %{
3074 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3075 match(ConL);
3076
3077 op_cost(5);
3078 format %{ %}
3079 interface(CONST_INTER);
3080 %}
3081
3082 // Long Immediate 32-bit unsigned
3083 operand immUL32()
3084 %{
3085 predicate(n->get_long() == (unsigned int) (n->get_long()));
3086 match(ConL);
3087
3088 op_cost(10);
3089 format %{ %}
3090 interface(CONST_INTER);
3091 %}
3092
3093 // Long Immediate 32-bit signed
3094 operand immL32()
3095 %{
3096 predicate(n->get_long() == (int) (n->get_long()));
3097 match(ConL);
3098
3099 op_cost(15);
3100 format %{ %}
3101 interface(CONST_INTER);
3102 %}
3103
3104 // Long Immediate zero
3105 operand immL0()
3106 %{
3107 predicate(n->get_long() == 0L);
3108 match(ConL);
3109
3110 op_cost(10);
3111 format %{ %}
3112 interface(CONST_INTER);
3113 %}
3114
3115 // Constant for increment
3116 operand immL1()
3117 %{
3118 predicate(n->get_long() == 1);
3119 match(ConL);
3120
3121 format %{ %}
3122 interface(CONST_INTER);
3123 %}
3124
3125 // Constant for decrement
3126 operand immL_M1()
3127 %{
3128 predicate(n->get_long() == -1);
3129 match(ConL);
3130
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Long Immediate: the value 10
3136 operand immL10()
3137 %{
3138 predicate(n->get_long() == 10);
3139 match(ConL);
3140
3141 format %{ %}
3142 interface(CONST_INTER);
3143 %}
3144
3145 // Long immediate from 0 to 127.
3146 // Used for a shorter form of long mul by 10.
3147 operand immL_127()
3148 %{
3149 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3150 match(ConL);
3151
3152 op_cost(10);
3153 format %{ %}
3154 interface(CONST_INTER);
3155 %}
3156
3157 // Long Immediate: low 32-bit mask
3158 operand immL_32bits()
3159 %{
3160 predicate(n->get_long() == 0xFFFFFFFFL);
3161 match(ConL);
3162 op_cost(20);
3163
3164 format %{ %}
3165 interface(CONST_INTER);
3166 %}
3167
3168 // Float Immediate zero
3169 operand immF0()
3170 %{
3171 predicate(jint_cast(n->getf()) == 0);
3172 match(ConF);
3173
3174 op_cost(5);
3175 format %{ %}
3176 interface(CONST_INTER);
3177 %}
3178
3179 // Float Immediate
3180 operand immF()
3181 %{
3182 match(ConF);
3183
3184 op_cost(15);
3185 format %{ %}
3186 interface(CONST_INTER);
3187 %}
3188
3189 // Double Immediate zero
3190 operand immD0()
3191 %{
3192 predicate(jlong_cast(n->getd()) == 0);
3193 match(ConD);
3194
3195 op_cost(5);
3196 format %{ %}
3197 interface(CONST_INTER);
3198 %}
3199
3200 // Double Immediate
3201 operand immD()
3202 %{
3203 match(ConD);
3204
3205 op_cost(15);
3206 format %{ %}
3207 interface(CONST_INTER);
3208 %}
3209
3210 // Immediates for special shifts (sign extend)
3211
3212 // Constants for increment
3213 operand immI_16()
3214 %{
3215 predicate(n->get_int() == 16);
3216 match(ConI);
3217
3218 format %{ %}
3219 interface(CONST_INTER);
3220 %}
3221
3222 operand immI_24()
3223 %{
3224 predicate(n->get_int() == 24);
3225 match(ConI);
3226
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Constant for byte-wide masking
3232 operand immI_255()
3233 %{
3234 predicate(n->get_int() == 255);
3235 match(ConI);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Constant for short-wide masking
3242 operand immI_65535()
3243 %{
3244 predicate(n->get_int() == 65535);
3245 match(ConI);
3246
3247 format %{ %}
3248 interface(CONST_INTER);
3249 %}
3250
3251 // Constant for byte-wide masking
3252 operand immL_255()
3253 %{
3254 predicate(n->get_long() == 255);
3255 match(ConL);
3256
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3260
3261 // Constant for short-wide masking
3262 operand immL_65535()
3263 %{
3264 predicate(n->get_long() == 65535);
3265 match(ConL);
3266
3267 format %{ %}
3268 interface(CONST_INTER);
3269 %}
3270
3271 // Register Operands
3272 // Integer Register
3273 operand rRegI()
3274 %{
3275 constraint(ALLOC_IN_RC(int_reg));
3276 match(RegI);
3277
3278 match(rax_RegI);
3279 match(rbx_RegI);
3280 match(rcx_RegI);
3281 match(rdx_RegI);
3282 match(rdi_RegI);
3283
3284 format %{ %}
3285 interface(REG_INTER);
3286 %}
3287
3288 // Special Registers
3289 operand rax_RegI()
3290 %{
3291 constraint(ALLOC_IN_RC(int_rax_reg));
3292 match(RegI);
3293 match(rRegI);
3294
3295 format %{ "RAX" %}
3296 interface(REG_INTER);
3297 %}
3298
3299 // Special Registers
3300 operand rbx_RegI()
3301 %{
3302 constraint(ALLOC_IN_RC(int_rbx_reg));
3303 match(RegI);
3304 match(rRegI);
3305
3306 format %{ "RBX" %}
3307 interface(REG_INTER);
3308 %}
3309
3310 operand rcx_RegI()
3311 %{
3312 constraint(ALLOC_IN_RC(int_rcx_reg));
3313 match(RegI);
3314 match(rRegI);
3315
3316 format %{ "RCX" %}
3317 interface(REG_INTER);
3318 %}
3319
3320 operand rdx_RegI()
3321 %{
3322 constraint(ALLOC_IN_RC(int_rdx_reg));
3323 match(RegI);
3324 match(rRegI);
3325
3326 format %{ "RDX" %}
3327 interface(REG_INTER);
3328 %}
3329
3330 operand rdi_RegI()
3331 %{
3332 constraint(ALLOC_IN_RC(int_rdi_reg));
3333 match(RegI);
3334 match(rRegI);
3335
3336 format %{ "RDI" %}
3337 interface(REG_INTER);
3338 %}
3339
3340 operand no_rcx_RegI()
3341 %{
3342 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3343 match(RegI);
3344 match(rax_RegI);
3345 match(rbx_RegI);
3346 match(rdx_RegI);
3347 match(rdi_RegI);
3348
3349 format %{ %}
3350 interface(REG_INTER);
3351 %}
3352
3353 operand no_rax_rdx_RegI()
3354 %{
3355 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3356 match(RegI);
3357 match(rbx_RegI);
3358 match(rcx_RegI);
3359 match(rdi_RegI);
3360
3361 format %{ %}
3362 interface(REG_INTER);
3363 %}
3364
3365 // Pointer Register
3366 operand any_RegP()
3367 %{
3368 constraint(ALLOC_IN_RC(any_reg));
3369 match(RegP);
3370 match(rax_RegP);
3371 match(rbx_RegP);
3372 match(rdi_RegP);
3373 match(rsi_RegP);
3374 match(rbp_RegP);
3375 match(r15_RegP);
3376 match(rRegP);
3377
3378 format %{ %}
3379 interface(REG_INTER);
3380 %}
3381
3382 operand rRegP()
3383 %{
3384 constraint(ALLOC_IN_RC(ptr_reg));
3385 match(RegP);
3386 match(rax_RegP);
3387 match(rbx_RegP);
3388 match(rdi_RegP);
3389 match(rsi_RegP);
3390 match(rbp_RegP); // See Q&A below about
3391 match(r15_RegP); // r15_RegP and rbp_RegP.
3392
3393 format %{ %}
3394 interface(REG_INTER);
3395 %}
3396
3397 operand rRegN() %{
3398 constraint(ALLOC_IN_RC(int_reg));
3399 match(RegN);
3400
3401 format %{ %}
3402 interface(REG_INTER);
3403 %}
3404
3405 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3406 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3407 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3408 // The output of an instruction is controlled by the allocator, which respects
3409 // register class masks, not match rules. Unless an instruction mentions
3410 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3411 // by the allocator as an input.
3412 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3413 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3414 // result, RBP is not included in the output of the instruction either.
3415
3416 operand no_rax_RegP()
3417 %{
3418 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3419 match(RegP);
3420 match(rbx_RegP);
3421 match(rsi_RegP);
3422 match(rdi_RegP);
3423
3424 format %{ %}
3425 interface(REG_INTER);
3426 %}
3427
3428 // This operand is not allowed to use RBP even if
3429 // RBP is not used to hold the frame pointer.
3430 operand no_rbp_RegP()
3431 %{
3432 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3433 match(RegP);
3434 match(rbx_RegP);
3435 match(rsi_RegP);
3436 match(rdi_RegP);
3437
3438 format %{ %}
3439 interface(REG_INTER);
3440 %}
3441
3442 operand no_rax_rbx_RegP()
3443 %{
3444 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3445 match(RegP);
3446 match(rsi_RegP);
3447 match(rdi_RegP);
3448
3449 format %{ %}
3450 interface(REG_INTER);
3451 %}
3452
3453 // Special Registers
3454 // Return a pointer value
3455 operand rax_RegP()
3456 %{
3457 constraint(ALLOC_IN_RC(ptr_rax_reg));
3458 match(RegP);
3459 match(rRegP);
3460
3461 format %{ %}
3462 interface(REG_INTER);
3463 %}
3464
3465 // Special Registers
3466 // Return a compressed pointer value
3467 operand rax_RegN()
3468 %{
3469 constraint(ALLOC_IN_RC(int_rax_reg));
3470 match(RegN);
3471 match(rRegN);
3472
3473 format %{ %}
3474 interface(REG_INTER);
3475 %}
3476
3477 // Used in AtomicAdd
3478 operand rbx_RegP()
3479 %{
3480 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3481 match(RegP);
3482 match(rRegP);
3483
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 operand rsi_RegP()
3489 %{
3490 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3491 match(RegP);
3492 match(rRegP);
3493
3494 format %{ %}
3495 interface(REG_INTER);
3496 %}
3497
3498 // Used in rep stosq
3499 operand rdi_RegP()
3500 %{
3501 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3502 match(RegP);
3503 match(rRegP);
3504
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 operand r15_RegP()
3510 %{
3511 constraint(ALLOC_IN_RC(ptr_r15_reg));
3512 match(RegP);
3513 match(rRegP);
3514
3515 format %{ %}
3516 interface(REG_INTER);
3517 %}
3518
3519 operand rRegL()
3520 %{
3521 constraint(ALLOC_IN_RC(long_reg));
3522 match(RegL);
3523 match(rax_RegL);
3524 match(rdx_RegL);
3525
3526 format %{ %}
3527 interface(REG_INTER);
3528 %}
3529
3530 // Special Registers
3531 operand no_rax_rdx_RegL()
3532 %{
3533 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3534 match(RegL);
3535 match(rRegL);
3536
3537 format %{ %}
3538 interface(REG_INTER);
3539 %}
3540
3541 operand no_rax_RegL()
3542 %{
3543 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3544 match(RegL);
3545 match(rRegL);
3546 match(rdx_RegL);
3547
3548 format %{ %}
3549 interface(REG_INTER);
3550 %}
3551
3552 operand no_rcx_RegL()
3553 %{
3554 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3555 match(RegL);
3556 match(rRegL);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 operand rax_RegL()
3563 %{
3564 constraint(ALLOC_IN_RC(long_rax_reg));
3565 match(RegL);
3566 match(rRegL);
3567
3568 format %{ "RAX" %}
3569 interface(REG_INTER);
3570 %}
3571
3572 operand rcx_RegL()
3573 %{
3574 constraint(ALLOC_IN_RC(long_rcx_reg));
3575 match(RegL);
3576 match(rRegL);
3577
3578 format %{ %}
3579 interface(REG_INTER);
3580 %}
3581
3582 operand rdx_RegL()
3583 %{
3584 constraint(ALLOC_IN_RC(long_rdx_reg));
3585 match(RegL);
3586 match(rRegL);
3587
3588 format %{ %}
3589 interface(REG_INTER);
3590 %}
3591
3592 // Flags register, used as output of compare instructions
3593 operand rFlagsReg()
3594 %{
3595 constraint(ALLOC_IN_RC(int_flags));
3596 match(RegFlags);
3597
3598 format %{ "RFLAGS" %}
3599 interface(REG_INTER);
3600 %}
3601
3602 // Flags register, used as output of FLOATING POINT compare instructions
3603 operand rFlagsRegU()
3604 %{
3605 constraint(ALLOC_IN_RC(int_flags));
3606 match(RegFlags);
3607
3608 format %{ "RFLAGS_U" %}
3609 interface(REG_INTER);
3610 %}
3611
3612 operand rFlagsRegUCF() %{
3613 constraint(ALLOC_IN_RC(int_flags));
3614 match(RegFlags);
3615 predicate(false);
3616
3617 format %{ "RFLAGS_U_CF" %}
3618 interface(REG_INTER);
3619 %}
3620
3621 // Float register operands
3622 operand regF() %{
3623 constraint(ALLOC_IN_RC(float_reg));
3624 match(RegF);
3625
3626 format %{ %}
3627 interface(REG_INTER);
3628 %}
3629
3630 // Double register operands
3631 operand regD() %{
3632 constraint(ALLOC_IN_RC(double_reg));
3633 match(RegD);
3634
3635 format %{ %}
3636 interface(REG_INTER);
3637 %}
3638
3639 // Vectors
3640 operand vecS() %{
3641 constraint(ALLOC_IN_RC(vectors_reg));
3642 match(VecS);
3643
3644 format %{ %}
3645 interface(REG_INTER);
3646 %}
3647
3648 operand vecD() %{
3649 constraint(ALLOC_IN_RC(vectord_reg));
3650 match(VecD);
3651
3652 format %{ %}
3653 interface(REG_INTER);
3654 %}
3655
3656 operand vecX() %{
3657 constraint(ALLOC_IN_RC(vectorx_reg));
3658 match(VecX);
3659
3660 format %{ %}
3661 interface(REG_INTER);
3662 %}
3663
3664 operand vecY() %{
3665 constraint(ALLOC_IN_RC(vectory_reg));
3666 match(VecY);
3667
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3671
3672 //----------Memory Operands----------------------------------------------------
3673 // Direct Memory Operand
3674 // operand direct(immP addr)
3675 // %{
3676 // match(addr);
3677
3678 // format %{ "[$addr]" %}
3679 // interface(MEMORY_INTER) %{
3680 // base(0xFFFFFFFF);
3681 // index(0x4);
3682 // scale(0x0);
3683 // disp($addr);
3684 // %}
3685 // %}
3686
3687 // Indirect Memory Operand
3688 operand indirect(any_RegP reg)
3689 %{
3690 constraint(ALLOC_IN_RC(ptr_reg));
3691 match(reg);
3692
3693 format %{ "[$reg]" %}
3694 interface(MEMORY_INTER) %{
3695 base($reg);
3696 index(0x4);
3697 scale(0x0);
3698 disp(0x0);
3699 %}
3700 %}
3701
3702 // Indirect Memory Plus Short Offset Operand
3703 operand indOffset8(any_RegP reg, immL8 off)
3704 %{
3705 constraint(ALLOC_IN_RC(ptr_reg));
3706 match(AddP reg off);
3707
3708 format %{ "[$reg + $off (8-bit)]" %}
3709 interface(MEMORY_INTER) %{
3710 base($reg);
3711 index(0x4);
3712 scale(0x0);
3713 disp($off);
3714 %}
3715 %}
3716
3717 // Indirect Memory Plus Long Offset Operand
3718 operand indOffset32(any_RegP reg, immL32 off)
3719 %{
3720 constraint(ALLOC_IN_RC(ptr_reg));
3721 match(AddP reg off);
3722
3723 format %{ "[$reg + $off (32-bit)]" %}
3724 interface(MEMORY_INTER) %{
3725 base($reg);
3726 index(0x4);
3727 scale(0x0);
3728 disp($off);
3729 %}
3730 %}
3731
3732 // Indirect Memory Plus Index Register Plus Offset Operand
3733 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3734 %{
3735 constraint(ALLOC_IN_RC(ptr_reg));
3736 match(AddP (AddP reg lreg) off);
3737
3738 op_cost(10);
3739 format %{"[$reg + $off + $lreg]" %}
3740 interface(MEMORY_INTER) %{
3741 base($reg);
3742 index($lreg);
3743 scale(0x0);
3744 disp($off);
3745 %}
3746 %}
3747
3748 // Indirect Memory Plus Index Register Plus Offset Operand
3749 operand indIndex(any_RegP reg, rRegL lreg)
3750 %{
3751 constraint(ALLOC_IN_RC(ptr_reg));
3752 match(AddP reg lreg);
3753
3754 op_cost(10);
3755 format %{"[$reg + $lreg]" %}
3756 interface(MEMORY_INTER) %{
3757 base($reg);
3758 index($lreg);
3759 scale(0x0);
3760 disp(0x0);
3761 %}
3762 %}
3763
3764 // Indirect Memory Times Scale Plus Index Register
3765 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3766 %{
3767 constraint(ALLOC_IN_RC(ptr_reg));
3768 match(AddP reg (LShiftL lreg scale));
3769
3770 op_cost(10);
3771 format %{"[$reg + $lreg << $scale]" %}
3772 interface(MEMORY_INTER) %{
3773 base($reg);
3774 index($lreg);
3775 scale($scale);
3776 disp(0x0);
3777 %}
3778 %}
3779
3780 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3781 %{
3782 constraint(ALLOC_IN_RC(ptr_reg));
3783 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3784 match(AddP reg (LShiftL (ConvI2L idx) scale));
3785
3786 op_cost(10);
3787 format %{"[$reg + pos $idx << $scale]" %}
3788 interface(MEMORY_INTER) %{
3789 base($reg);
3790 index($idx);
3791 scale($scale);
3792 disp(0x0);
3793 %}
3794 %}
3795
3796 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3797 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3798 %{
3799 constraint(ALLOC_IN_RC(ptr_reg));
3800 match(AddP (AddP reg (LShiftL lreg scale)) off);
3801
3802 op_cost(10);
3803 format %{"[$reg + $off + $lreg << $scale]" %}
3804 interface(MEMORY_INTER) %{
3805 base($reg);
3806 index($lreg);
3807 scale($scale);
3808 disp($off);
3809 %}
3810 %}
3811
3812 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3813 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3814 %{
3815 constraint(ALLOC_IN_RC(ptr_reg));
3816 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3817 match(AddP (AddP reg (ConvI2L idx)) off);
3818
3819 op_cost(10);
3820 format %{"[$reg + $off + $idx]" %}
3821 interface(MEMORY_INTER) %{
3822 base($reg);
3823 index($idx);
3824 scale(0x0);
3825 disp($off);
3826 %}
3827 %}
3828
3829 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3830 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3831 %{
3832 constraint(ALLOC_IN_RC(ptr_reg));
3833 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3834 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3835
3836 op_cost(10);
3837 format %{"[$reg + $off + $idx << $scale]" %}
3838 interface(MEMORY_INTER) %{
3839 base($reg);
3840 index($idx);
3841 scale($scale);
3842 disp($off);
3843 %}
3844 %}
3845
3846 // Indirect Narrow Oop Plus Offset Operand
3847 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3848 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3849 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3850 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3851 constraint(ALLOC_IN_RC(ptr_reg));
3852 match(AddP (DecodeN reg) off);
3853
3854 op_cost(10);
3855 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3856 interface(MEMORY_INTER) %{
3857 base(0xc); // R12
3858 index($reg);
3859 scale(0x3);
3860 disp($off);
3861 %}
3862 %}
3863
3864 // Indirect Memory Operand
3865 operand indirectNarrow(rRegN reg)
3866 %{
3867 predicate(Universe::narrow_oop_shift() == 0);
3868 constraint(ALLOC_IN_RC(ptr_reg));
3869 match(DecodeN reg);
3870
3871 format %{ "[$reg]" %}
3872 interface(MEMORY_INTER) %{
3873 base($reg);
3874 index(0x4);
3875 scale(0x0);
3876 disp(0x0);
3877 %}
3878 %}
3879
3880 // Indirect Memory Plus Short Offset Operand
3881 operand indOffset8Narrow(rRegN reg, immL8 off)
3882 %{
3883 predicate(Universe::narrow_oop_shift() == 0);
3884 constraint(ALLOC_IN_RC(ptr_reg));
3885 match(AddP (DecodeN reg) off);
3886
3887 format %{ "[$reg + $off (8-bit)]" %}
3888 interface(MEMORY_INTER) %{
3889 base($reg);
3890 index(0x4);
3891 scale(0x0);
3892 disp($off);
3893 %}
3894 %}
3895
3896 // Indirect Memory Plus Long Offset Operand
3897 operand indOffset32Narrow(rRegN reg, immL32 off)
3898 %{
3899 predicate(Universe::narrow_oop_shift() == 0);
3900 constraint(ALLOC_IN_RC(ptr_reg));
3901 match(AddP (DecodeN reg) off);
3902
3903 format %{ "[$reg + $off (32-bit)]" %}
3904 interface(MEMORY_INTER) %{
3905 base($reg);
3906 index(0x4);
3907 scale(0x0);
3908 disp($off);
3909 %}
3910 %}
3911
3912 // Indirect Memory Plus Index Register Plus Offset Operand
3913 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3914 %{
3915 predicate(Universe::narrow_oop_shift() == 0);
3916 constraint(ALLOC_IN_RC(ptr_reg));
3917 match(AddP (AddP (DecodeN reg) lreg) off);
3918
3919 op_cost(10);
3920 format %{"[$reg + $off + $lreg]" %}
3921 interface(MEMORY_INTER) %{
3922 base($reg);
3923 index($lreg);
3924 scale(0x0);
3925 disp($off);
3926 %}
3927 %}
3928
3929 // Indirect Memory Plus Index Register Plus Offset Operand
3930 operand indIndexNarrow(rRegN reg, rRegL lreg)
3931 %{
3932 predicate(Universe::narrow_oop_shift() == 0);
3933 constraint(ALLOC_IN_RC(ptr_reg));
3934 match(AddP (DecodeN reg) lreg);
3935
3936 op_cost(10);
3937 format %{"[$reg + $lreg]" %}
3938 interface(MEMORY_INTER) %{
3939 base($reg);
3940 index($lreg);
3941 scale(0x0);
3942 disp(0x0);
3943 %}
3944 %}
3945
3946 // Indirect Memory Times Scale Plus Index Register
3947 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3948 %{
3949 predicate(Universe::narrow_oop_shift() == 0);
3950 constraint(ALLOC_IN_RC(ptr_reg));
3951 match(AddP (DecodeN reg) (LShiftL lreg scale));
3952
3953 op_cost(10);
3954 format %{"[$reg + $lreg << $scale]" %}
3955 interface(MEMORY_INTER) %{
3956 base($reg);
3957 index($lreg);
3958 scale($scale);
3959 disp(0x0);
3960 %}
3961 %}
3962
3963 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3964 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3965 %{
3966 predicate(Universe::narrow_oop_shift() == 0);
3967 constraint(ALLOC_IN_RC(ptr_reg));
3968 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3969
3970 op_cost(10);
3971 format %{"[$reg + $off + $lreg << $scale]" %}
3972 interface(MEMORY_INTER) %{
3973 base($reg);
3974 index($lreg);
3975 scale($scale);
3976 disp($off);
3977 %}
3978 %}
3979
3980 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3981 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3982 %{
3983 constraint(ALLOC_IN_RC(ptr_reg));
3984 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3985 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3986
3987 op_cost(10);
3988 format %{"[$reg + $off + $idx]" %}
3989 interface(MEMORY_INTER) %{
3990 base($reg);
3991 index($idx);
3992 scale(0x0);
3993 disp($off);
3994 %}
3995 %}
3996
3997 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3998 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3999 %{
4000 constraint(ALLOC_IN_RC(ptr_reg));
4001 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4002 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4003
4004 op_cost(10);
4005 format %{"[$reg + $off + $idx << $scale]" %}
4006 interface(MEMORY_INTER) %{
4007 base($reg);
4008 index($idx);
4009 scale($scale);
4010 disp($off);
4011 %}
4012 %}
4013
4014 //----------Special Memory Operands--------------------------------------------
4015 // Stack Slot Operand - This operand is used for loading and storing temporary
4016 // values on the stack where a match requires a value to
4017 // flow through memory.
4018 operand stackSlotP(sRegP reg)
4019 %{
4020 constraint(ALLOC_IN_RC(stack_slots));
4021 // No match rule because this operand is only generated in matching
4022
4023 format %{ "[$reg]" %}
4024 interface(MEMORY_INTER) %{
4025 base(0x4); // RSP
4026 index(0x4); // No Index
4027 scale(0x0); // No Scale
4028 disp($reg); // Stack Offset
4029 %}
4030 %}
4031
4032 operand stackSlotI(sRegI reg)
4033 %{
4034 constraint(ALLOC_IN_RC(stack_slots));
4035 // No match rule because this operand is only generated in matching
4036
4037 format %{ "[$reg]" %}
4038 interface(MEMORY_INTER) %{
4039 base(0x4); // RSP
4040 index(0x4); // No Index
4041 scale(0x0); // No Scale
4042 disp($reg); // Stack Offset
4043 %}
4044 %}
4045
4046 operand stackSlotF(sRegF reg)
4047 %{
4048 constraint(ALLOC_IN_RC(stack_slots));
4049 // No match rule because this operand is only generated in matching
4050
4051 format %{ "[$reg]" %}
4052 interface(MEMORY_INTER) %{
4053 base(0x4); // RSP
4054 index(0x4); // No Index
4055 scale(0x0); // No Scale
4056 disp($reg); // Stack Offset
4057 %}
4058 %}
4059
4060 operand stackSlotD(sRegD reg)
4061 %{
4062 constraint(ALLOC_IN_RC(stack_slots));
4063 // No match rule because this operand is only generated in matching
4064
4065 format %{ "[$reg]" %}
4066 interface(MEMORY_INTER) %{
4067 base(0x4); // RSP
4068 index(0x4); // No Index
4069 scale(0x0); // No Scale
4070 disp($reg); // Stack Offset
4071 %}
4072 %}
4073 operand stackSlotL(sRegL reg)
4074 %{
4075 constraint(ALLOC_IN_RC(stack_slots));
4076 // No match rule because this operand is only generated in matching
4077
4078 format %{ "[$reg]" %}
4079 interface(MEMORY_INTER) %{
4080 base(0x4); // RSP
4081 index(0x4); // No Index
4082 scale(0x0); // No Scale
4083 disp($reg); // Stack Offset
4084 %}
4085 %}
4086
4087 //----------Conditional Branch Operands----------------------------------------
4088 // Comparison Op - This is the operation of the comparison, and is limited to
4089 // the following set of codes:
4090 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4091 //
4092 // Other attributes of the comparison, such as unsignedness, are specified
4093 // by the comparison instruction that sets a condition code flags register.
4094 // That result is represented by a flags operand whose subtype is appropriate
4095 // to the unsignedness (etc.) of the comparison.
4096 //
4097 // Later, the instruction which matches both the Comparison Op (a Bool) and
4098 // the flags (produced by the Cmp) specifies the coding of the comparison op
4099 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4100
4101 // Comparision Code
4102 operand cmpOp()
4103 %{
4104 match(Bool);
4105
4106 format %{ "" %}
4107 interface(COND_INTER) %{
4108 equal(0x4, "e");
4109 not_equal(0x5, "ne");
4110 less(0xC, "l");
4111 greater_equal(0xD, "ge");
4112 less_equal(0xE, "le");
4113 greater(0xF, "g");
4114 overflow(0x0, "o");
4115 no_overflow(0x1, "no");
4116 %}
4117 %}
4118
4119 // Comparison Code, unsigned compare. Used by FP also, with
4120 // C2 (unordered) turned into GT or LT already. The other bits
4121 // C0 and C3 are turned into Carry & Zero flags.
4122 operand cmpOpU()
4123 %{
4124 match(Bool);
4125
4126 format %{ "" %}
4127 interface(COND_INTER) %{
4128 equal(0x4, "e");
4129 not_equal(0x5, "ne");
4130 less(0x2, "b");
4131 greater_equal(0x3, "nb");
4132 less_equal(0x6, "be");
4133 greater(0x7, "nbe");
4134 overflow(0x0, "o");
4135 no_overflow(0x1, "no");
4136 %}
4137 %}
4138
4139
4140 // Floating comparisons that don't require any fixup for the unordered case
4141 operand cmpOpUCF() %{
4142 match(Bool);
4143 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4144 n->as_Bool()->_test._test == BoolTest::ge ||
4145 n->as_Bool()->_test._test == BoolTest::le ||
4146 n->as_Bool()->_test._test == BoolTest::gt);
4147 format %{ "" %}
4148 interface(COND_INTER) %{
4149 equal(0x4, "e");
4150 not_equal(0x5, "ne");
4151 less(0x2, "b");
4152 greater_equal(0x3, "nb");
4153 less_equal(0x6, "be");
4154 greater(0x7, "nbe");
4155 overflow(0x0, "o");
4156 no_overflow(0x1, "no");
4157 %}
4158 %}
4159
4160
4161 // Floating comparisons that can be fixed up with extra conditional jumps
4162 operand cmpOpUCF2() %{
4163 match(Bool);
4164 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4165 n->as_Bool()->_test._test == BoolTest::eq);
4166 format %{ "" %}
4167 interface(COND_INTER) %{
4168 equal(0x4, "e");
4169 not_equal(0x5, "ne");
4170 less(0x2, "b");
4171 greater_equal(0x3, "nb");
4172 less_equal(0x6, "be");
4173 greater(0x7, "nbe");
4174 overflow(0x0, "o");
4175 no_overflow(0x1, "no");
4176 %}
4177 %}
4178
4179
4180 //----------OPERAND CLASSES----------------------------------------------------
4181 // Operand Classes are groups of operands that are used as to simplify
4182 // instruction definitions by not requiring the AD writer to specify separate
4183 // instructions for every form of operand when the instruction accepts
4184 // multiple operand types with the same basic encoding and format. The classic
4185 // case of this is memory operands.
4186
4187 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4188 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4189 indCompressedOopOffset,
4190 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4191 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4192 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4193
4194 //----------PIPELINE-----------------------------------------------------------
4195 // Rules which define the behavior of the target architectures pipeline.
4196 pipeline %{
4197
4198 //----------ATTRIBUTES---------------------------------------------------------
4199 attributes %{
4200 variable_size_instructions; // Fixed size instructions
4201 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4202 instruction_unit_size = 1; // An instruction is 1 bytes long
4203 instruction_fetch_unit_size = 16; // The processor fetches one line
4204 instruction_fetch_units = 1; // of 16 bytes
4205
4206 // List of nop instructions
4207 nops( MachNop );
4208 %}
4209
4210 //----------RESOURCES----------------------------------------------------------
4211 // Resources are the functional units available to the machine
4212
4213 // Generic P2/P3 pipeline
4214 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4215 // 3 instructions decoded per cycle.
4216 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4217 // 3 ALU op, only ALU0 handles mul instructions.
4218 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4219 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4220 BR, FPU,
4221 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4222
4223 //----------PIPELINE DESCRIPTION-----------------------------------------------
4224 // Pipeline Description specifies the stages in the machine's pipeline
4225
4226 // Generic P2/P3 pipeline
4227 pipe_desc(S0, S1, S2, S3, S4, S5);
4228
4229 //----------PIPELINE CLASSES---------------------------------------------------
4230 // Pipeline Classes describe the stages in which input and output are
4231 // referenced by the hardware pipeline.
4232
4233 // Naming convention: ialu or fpu
4234 // Then: _reg
4235 // Then: _reg if there is a 2nd register
4236 // Then: _long if it's a pair of instructions implementing a long
4237 // Then: _fat if it requires the big decoder
4238 // Or: _mem if it requires the big decoder and a memory unit.
4239
4240 // Integer ALU reg operation
4241 pipe_class ialu_reg(rRegI dst)
4242 %{
4243 single_instruction;
4244 dst : S4(write);
4245 dst : S3(read);
4246 DECODE : S0; // any decoder
4247 ALU : S3; // any alu
4248 %}
4249
4250 // Long ALU reg operation
4251 pipe_class ialu_reg_long(rRegL dst)
4252 %{
4253 instruction_count(2);
4254 dst : S4(write);
4255 dst : S3(read);
4256 DECODE : S0(2); // any 2 decoders
4257 ALU : S3(2); // both alus
4258 %}
4259
4260 // Integer ALU reg operation using big decoder
4261 pipe_class ialu_reg_fat(rRegI dst)
4262 %{
4263 single_instruction;
4264 dst : S4(write);
4265 dst : S3(read);
4266 D0 : S0; // big decoder only
4267 ALU : S3; // any alu
4268 %}
4269
4270 // Long ALU reg operation using big decoder
4271 pipe_class ialu_reg_long_fat(rRegL dst)
4272 %{
4273 instruction_count(2);
4274 dst : S4(write);
4275 dst : S3(read);
4276 D0 : S0(2); // big decoder only; twice
4277 ALU : S3(2); // any 2 alus
4278 %}
4279
4280 // Integer ALU reg-reg operation
4281 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4282 %{
4283 single_instruction;
4284 dst : S4(write);
4285 src : S3(read);
4286 DECODE : S0; // any decoder
4287 ALU : S3; // any alu
4288 %}
4289
4290 // Long ALU reg-reg operation
4291 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4292 %{
4293 instruction_count(2);
4294 dst : S4(write);
4295 src : S3(read);
4296 DECODE : S0(2); // any 2 decoders
4297 ALU : S3(2); // both alus
4298 %}
4299
4300 // Integer ALU reg-reg operation
4301 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4302 %{
4303 single_instruction;
4304 dst : S4(write);
4305 src : S3(read);
4306 D0 : S0; // big decoder only
4307 ALU : S3; // any alu
4308 %}
4309
4310 // Long ALU reg-reg operation
4311 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4312 %{
4313 instruction_count(2);
4314 dst : S4(write);
4315 src : S3(read);
4316 D0 : S0(2); // big decoder only; twice
4317 ALU : S3(2); // both alus
4318 %}
4319
4320 // Integer ALU reg-mem operation
4321 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4322 %{
4323 single_instruction;
4324 dst : S5(write);
4325 mem : S3(read);
4326 D0 : S0; // big decoder only
4327 ALU : S4; // any alu
4328 MEM : S3; // any mem
4329 %}
4330
4331 // Integer mem operation (prefetch)
4332 pipe_class ialu_mem(memory mem)
4333 %{
4334 single_instruction;
4335 mem : S3(read);
4336 D0 : S0; // big decoder only
4337 MEM : S3; // any mem
4338 %}
4339
4340 // Integer Store to Memory
4341 pipe_class ialu_mem_reg(memory mem, rRegI src)
4342 %{
4343 single_instruction;
4344 mem : S3(read);
4345 src : S5(read);
4346 D0 : S0; // big decoder only
4347 ALU : S4; // any alu
4348 MEM : S3;
4349 %}
4350
4351 // // Long Store to Memory
4352 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4353 // %{
4354 // instruction_count(2);
4355 // mem : S3(read);
4356 // src : S5(read);
4357 // D0 : S0(2); // big decoder only; twice
4358 // ALU : S4(2); // any 2 alus
4359 // MEM : S3(2); // Both mems
4360 // %}
4361
4362 // Integer Store to Memory
4363 pipe_class ialu_mem_imm(memory mem)
4364 %{
4365 single_instruction;
4366 mem : S3(read);
4367 D0 : S0; // big decoder only
4368 ALU : S4; // any alu
4369 MEM : S3;
4370 %}
4371
4372 // Integer ALU0 reg-reg operation
4373 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4374 %{
4375 single_instruction;
4376 dst : S4(write);
4377 src : S3(read);
4378 D0 : S0; // Big decoder only
4379 ALU0 : S3; // only alu0
4380 %}
4381
4382 // Integer ALU0 reg-mem operation
4383 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4384 %{
4385 single_instruction;
4386 dst : S5(write);
4387 mem : S3(read);
4388 D0 : S0; // big decoder only
4389 ALU0 : S4; // ALU0 only
4390 MEM : S3; // any mem
4391 %}
4392
4393 // Integer ALU reg-reg operation
4394 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4395 %{
4396 single_instruction;
4397 cr : S4(write);
4398 src1 : S3(read);
4399 src2 : S3(read);
4400 DECODE : S0; // any decoder
4401 ALU : S3; // any alu
4402 %}
4403
4404 // Integer ALU reg-imm operation
4405 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4406 %{
4407 single_instruction;
4408 cr : S4(write);
4409 src1 : S3(read);
4410 DECODE : S0; // any decoder
4411 ALU : S3; // any alu
4412 %}
4413
4414 // Integer ALU reg-mem operation
4415 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4416 %{
4417 single_instruction;
4418 cr : S4(write);
4419 src1 : S3(read);
4420 src2 : S3(read);
4421 D0 : S0; // big decoder only
4422 ALU : S4; // any alu
4423 MEM : S3;
4424 %}
4425
4426 // Conditional move reg-reg
4427 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4428 %{
4429 instruction_count(4);
4430 y : S4(read);
4431 q : S3(read);
4432 p : S3(read);
4433 DECODE : S0(4); // any decoder
4434 %}
4435
4436 // Conditional move reg-reg
4437 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4438 %{
4439 single_instruction;
4440 dst : S4(write);
4441 src : S3(read);
4442 cr : S3(read);
4443 DECODE : S0; // any decoder
4444 %}
4445
4446 // Conditional move reg-mem
4447 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4448 %{
4449 single_instruction;
4450 dst : S4(write);
4451 src : S3(read);
4452 cr : S3(read);
4453 DECODE : S0; // any decoder
4454 MEM : S3;
4455 %}
4456
4457 // Conditional move reg-reg long
4458 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4459 %{
4460 single_instruction;
4461 dst : S4(write);
4462 src : S3(read);
4463 cr : S3(read);
4464 DECODE : S0(2); // any 2 decoders
4465 %}
4466
4467 // XXX
4468 // // Conditional move double reg-reg
4469 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4470 // %{
4471 // single_instruction;
4472 // dst : S4(write);
4473 // src : S3(read);
4474 // cr : S3(read);
4475 // DECODE : S0; // any decoder
4476 // %}
4477
4478 // Float reg-reg operation
4479 pipe_class fpu_reg(regD dst)
4480 %{
4481 instruction_count(2);
4482 dst : S3(read);
4483 DECODE : S0(2); // any 2 decoders
4484 FPU : S3;
4485 %}
4486
4487 // Float reg-reg operation
4488 pipe_class fpu_reg_reg(regD dst, regD src)
4489 %{
4490 instruction_count(2);
4491 dst : S4(write);
4492 src : S3(read);
4493 DECODE : S0(2); // any 2 decoders
4494 FPU : S3;
4495 %}
4496
4497 // Float reg-reg operation
4498 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4499 %{
4500 instruction_count(3);
4501 dst : S4(write);
4502 src1 : S3(read);
4503 src2 : S3(read);
4504 DECODE : S0(3); // any 3 decoders
4505 FPU : S3(2);
4506 %}
4507
4508 // Float reg-reg operation
4509 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4510 %{
4511 instruction_count(4);
4512 dst : S4(write);
4513 src1 : S3(read);
4514 src2 : S3(read);
4515 src3 : S3(read);
4516 DECODE : S0(4); // any 3 decoders
4517 FPU : S3(2);
4518 %}
4519
4520 // Float reg-reg operation
4521 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4522 %{
4523 instruction_count(4);
4524 dst : S4(write);
4525 src1 : S3(read);
4526 src2 : S3(read);
4527 src3 : S3(read);
4528 DECODE : S1(3); // any 3 decoders
4529 D0 : S0; // Big decoder only
4530 FPU : S3(2);
4531 MEM : S3;
4532 %}
4533
4534 // Float reg-mem operation
4535 pipe_class fpu_reg_mem(regD dst, memory mem)
4536 %{
4537 instruction_count(2);
4538 dst : S5(write);
4539 mem : S3(read);
4540 D0 : S0; // big decoder only
4541 DECODE : S1; // any decoder for FPU POP
4542 FPU : S4;
4543 MEM : S3; // any mem
4544 %}
4545
4546 // Float reg-mem operation
4547 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4548 %{
4549 instruction_count(3);
4550 dst : S5(write);
4551 src1 : S3(read);
4552 mem : S3(read);
4553 D0 : S0; // big decoder only
4554 DECODE : S1(2); // any decoder for FPU POP
4555 FPU : S4;
4556 MEM : S3; // any mem
4557 %}
4558
4559 // Float mem-reg operation
4560 pipe_class fpu_mem_reg(memory mem, regD src)
4561 %{
4562 instruction_count(2);
4563 src : S5(read);
4564 mem : S3(read);
4565 DECODE : S0; // any decoder for FPU PUSH
4566 D0 : S1; // big decoder only
4567 FPU : S4;
4568 MEM : S3; // any mem
4569 %}
4570
4571 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4572 %{
4573 instruction_count(3);
4574 src1 : S3(read);
4575 src2 : S3(read);
4576 mem : S3(read);
4577 DECODE : S0(2); // any decoder for FPU PUSH
4578 D0 : S1; // big decoder only
4579 FPU : S4;
4580 MEM : S3; // any mem
4581 %}
4582
4583 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4584 %{
4585 instruction_count(3);
4586 src1 : S3(read);
4587 src2 : S3(read);
4588 mem : S4(read);
4589 DECODE : S0; // any decoder for FPU PUSH
4590 D0 : S0(2); // big decoder only
4591 FPU : S4;
4592 MEM : S3(2); // any mem
4593 %}
4594
4595 pipe_class fpu_mem_mem(memory dst, memory src1)
4596 %{
4597 instruction_count(2);
4598 src1 : S3(read);
4599 dst : S4(read);
4600 D0 : S0(2); // big decoder only
4601 MEM : S3(2); // any mem
4602 %}
4603
4604 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4605 %{
4606 instruction_count(3);
4607 src1 : S3(read);
4608 src2 : S3(read);
4609 dst : S4(read);
4610 D0 : S0(3); // big decoder only
4611 FPU : S4;
4612 MEM : S3(3); // any mem
4613 %}
4614
4615 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4616 %{
4617 instruction_count(3);
4618 src1 : S4(read);
4619 mem : S4(read);
4620 DECODE : S0; // any decoder for FPU PUSH
4621 D0 : S0(2); // big decoder only
4622 FPU : S4;
4623 MEM : S3(2); // any mem
4624 %}
4625
4626 // Float load constant
4627 pipe_class fpu_reg_con(regD dst)
4628 %{
4629 instruction_count(2);
4630 dst : S5(write);
4631 D0 : S0; // big decoder only for the load
4632 DECODE : S1; // any decoder for FPU POP
4633 FPU : S4;
4634 MEM : S3; // any mem
4635 %}
4636
4637 // Float load constant
4638 pipe_class fpu_reg_reg_con(regD dst, regD src)
4639 %{
4640 instruction_count(3);
4641 dst : S5(write);
4642 src : S3(read);
4643 D0 : S0; // big decoder only for the load
4644 DECODE : S1(2); // any decoder for FPU POP
4645 FPU : S4;
4646 MEM : S3; // any mem
4647 %}
4648
4649 // UnConditional branch
4650 pipe_class pipe_jmp(label labl)
4651 %{
4652 single_instruction;
4653 BR : S3;
4654 %}
4655
4656 // Conditional branch
4657 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4658 %{
4659 single_instruction;
4660 cr : S1(read);
4661 BR : S3;
4662 %}
4663
4664 // Allocation idiom
4665 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4666 %{
4667 instruction_count(1); force_serialization;
4668 fixed_latency(6);
4669 heap_ptr : S3(read);
4670 DECODE : S0(3);
4671 D0 : S2;
4672 MEM : S3;
4673 ALU : S3(2);
4674 dst : S5(write);
4675 BR : S5;
4676 %}
4677
4678 // Generic big/slow expanded idiom
4679 pipe_class pipe_slow()
4680 %{
4681 instruction_count(10); multiple_bundles; force_serialization;
4682 fixed_latency(100);
4683 D0 : S0(2);
4684 MEM : S3(2);
4685 %}
4686
4687 // The real do-nothing guy
4688 pipe_class empty()
4689 %{
4690 instruction_count(0);
4691 %}
4692
4693 // Define the class for the Nop node
4694 define
4695 %{
4696 MachNop = empty;
4697 %}
4698
4699 %}
4700
4701 //----------INSTRUCTIONS-------------------------------------------------------
4702 //
4703 // match -- States which machine-independent subtree may be replaced
4704 // by this instruction.
4705 // ins_cost -- The estimated cost of this instruction is used by instruction
4706 // selection to identify a minimum cost tree of machine
4707 // instructions that matches a tree of machine-independent
4708 // instructions.
4709 // format -- A string providing the disassembly for this instruction.
4710 // The value of an instruction's operand may be inserted
4711 // by referring to it with a '$' prefix.
4712 // opcode -- Three instruction opcodes may be provided. These are referred
4713 // to within an encode class as $primary, $secondary, and $tertiary
4714 // rrspectively. The primary opcode is commonly used to
4715 // indicate the type of machine instruction, while secondary
4716 // and tertiary are often used for prefix options or addressing
4717 // modes.
4718 // ins_encode -- A list of encode classes with parameters. The encode class
4719 // name must have been defined in an 'enc_class' specification
4720 // in the encode section of the architecture description.
4721
4722
4723 //----------Load/Store/Move Instructions---------------------------------------
4724 //----------Load Instructions--------------------------------------------------
4725
4726 // Load Byte (8 bit signed)
4727 instruct loadB(rRegI dst, memory mem)
4728 %{
4729 match(Set dst (LoadB mem));
4730
4731 ins_cost(125);
4732 format %{ "movsbl $dst, $mem\t# byte" %}
4733
4734 ins_encode %{
4735 __ movsbl($dst$$Register, $mem$$Address);
4736 %}
4737
4738 ins_pipe(ialu_reg_mem);
4739 %}
4740
4741 // Load Byte (8 bit signed) into Long Register
4742 instruct loadB2L(rRegL dst, memory mem)
4743 %{
4744 match(Set dst (ConvI2L (LoadB mem)));
4745
4746 ins_cost(125);
4747 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4748
4749 ins_encode %{
4750 __ movsbq($dst$$Register, $mem$$Address);
4751 %}
4752
4753 ins_pipe(ialu_reg_mem);
4754 %}
4755
4756 // Load Unsigned Byte (8 bit UNsigned)
4757 instruct loadUB(rRegI dst, memory mem)
4758 %{
4759 match(Set dst (LoadUB mem));
4760
4761 ins_cost(125);
4762 format %{ "movzbl $dst, $mem\t# ubyte" %}
4763
4764 ins_encode %{
4765 __ movzbl($dst$$Register, $mem$$Address);
4766 %}
4767
4768 ins_pipe(ialu_reg_mem);
4769 %}
4770
4771 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4772 instruct loadUB2L(rRegL dst, memory mem)
4773 %{
4774 match(Set dst (ConvI2L (LoadUB mem)));
4775
4776 ins_cost(125);
4777 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4778
4779 ins_encode %{
4780 __ movzbq($dst$$Register, $mem$$Address);
4781 %}
4782
4783 ins_pipe(ialu_reg_mem);
4784 %}
4785
4786 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4787 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4788 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4789 effect(KILL cr);
4790
4791 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4792 "andl $dst, right_n_bits($mask, 8)" %}
4793 ins_encode %{
4794 Register Rdst = $dst$$Register;
4795 __ movzbq(Rdst, $mem$$Address);
4796 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4797 %}
4798 ins_pipe(ialu_reg_mem);
4799 %}
4800
4801 // Load Short (16 bit signed)
4802 instruct loadS(rRegI dst, memory mem)
4803 %{
4804 match(Set dst (LoadS mem));
4805
4806 ins_cost(125);
4807 format %{ "movswl $dst, $mem\t# short" %}
4808
4809 ins_encode %{
4810 __ movswl($dst$$Register, $mem$$Address);
4811 %}
4812
4813 ins_pipe(ialu_reg_mem);
4814 %}
4815
4816 // Load Short (16 bit signed) to Byte (8 bit signed)
4817 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4818 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4819
4820 ins_cost(125);
4821 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4822 ins_encode %{
4823 __ movsbl($dst$$Register, $mem$$Address);
4824 %}
4825 ins_pipe(ialu_reg_mem);
4826 %}
4827
4828 // Load Short (16 bit signed) into Long Register
4829 instruct loadS2L(rRegL dst, memory mem)
4830 %{
4831 match(Set dst (ConvI2L (LoadS mem)));
4832
4833 ins_cost(125);
4834 format %{ "movswq $dst, $mem\t# short -> long" %}
4835
4836 ins_encode %{
4837 __ movswq($dst$$Register, $mem$$Address);
4838 %}
4839
4840 ins_pipe(ialu_reg_mem);
4841 %}
4842
4843 // Load Unsigned Short/Char (16 bit UNsigned)
4844 instruct loadUS(rRegI dst, memory mem)
4845 %{
4846 match(Set dst (LoadUS mem));
4847
4848 ins_cost(125);
4849 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4850
4851 ins_encode %{
4852 __ movzwl($dst$$Register, $mem$$Address);
4853 %}
4854
4855 ins_pipe(ialu_reg_mem);
4856 %}
4857
4858 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4859 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4860 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4861
4862 ins_cost(125);
4863 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4864 ins_encode %{
4865 __ movsbl($dst$$Register, $mem$$Address);
4866 %}
4867 ins_pipe(ialu_reg_mem);
4868 %}
4869
4870 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4871 instruct loadUS2L(rRegL dst, memory mem)
4872 %{
4873 match(Set dst (ConvI2L (LoadUS mem)));
4874
4875 ins_cost(125);
4876 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4877
4878 ins_encode %{
4879 __ movzwq($dst$$Register, $mem$$Address);
4880 %}
4881
4882 ins_pipe(ialu_reg_mem);
4883 %}
4884
4885 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4886 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4887 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4888
4889 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4890 ins_encode %{
4891 __ movzbq($dst$$Register, $mem$$Address);
4892 %}
4893 ins_pipe(ialu_reg_mem);
4894 %}
4895
4896 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4897 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4898 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4899 effect(KILL cr);
4900
4901 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4902 "andl $dst, right_n_bits($mask, 16)" %}
4903 ins_encode %{
4904 Register Rdst = $dst$$Register;
4905 __ movzwq(Rdst, $mem$$Address);
4906 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4907 %}
4908 ins_pipe(ialu_reg_mem);
4909 %}
4910
4911 // Load Integer
4912 instruct loadI(rRegI dst, memory mem)
4913 %{
4914 match(Set dst (LoadI mem));
4915
4916 ins_cost(125);
4917 format %{ "movl $dst, $mem\t# int" %}
4918
4919 ins_encode %{
4920 __ movl($dst$$Register, $mem$$Address);
4921 %}
4922
4923 ins_pipe(ialu_reg_mem);
4924 %}
4925
4926 // Load Integer (32 bit signed) to Byte (8 bit signed)
4927 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4928 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4929
4930 ins_cost(125);
4931 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4932 ins_encode %{
4933 __ movsbl($dst$$Register, $mem$$Address);
4934 %}
4935 ins_pipe(ialu_reg_mem);
4936 %}
4937
4938 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4939 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4940 match(Set dst (AndI (LoadI mem) mask));
4941
4942 ins_cost(125);
4943 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4944 ins_encode %{
4945 __ movzbl($dst$$Register, $mem$$Address);
4946 %}
4947 ins_pipe(ialu_reg_mem);
4948 %}
4949
4950 // Load Integer (32 bit signed) to Short (16 bit signed)
4951 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4952 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4953
4954 ins_cost(125);
4955 format %{ "movswl $dst, $mem\t# int -> short" %}
4956 ins_encode %{
4957 __ movswl($dst$$Register, $mem$$Address);
4958 %}
4959 ins_pipe(ialu_reg_mem);
4960 %}
4961
4962 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4963 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4964 match(Set dst (AndI (LoadI mem) mask));
4965
4966 ins_cost(125);
4967 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4968 ins_encode %{
4969 __ movzwl($dst$$Register, $mem$$Address);
4970 %}
4971 ins_pipe(ialu_reg_mem);
4972 %}
4973
4974 // Load Integer into Long Register
4975 instruct loadI2L(rRegL dst, memory mem)
4976 %{
4977 match(Set dst (ConvI2L (LoadI mem)));
4978
4979 ins_cost(125);
4980 format %{ "movslq $dst, $mem\t# int -> long" %}
4981
4982 ins_encode %{
4983 __ movslq($dst$$Register, $mem$$Address);
4984 %}
4985
4986 ins_pipe(ialu_reg_mem);
4987 %}
4988
4989 // Load Integer with mask 0xFF into Long Register
4990 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4991 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4992
4993 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4994 ins_encode %{
4995 __ movzbq($dst$$Register, $mem$$Address);
4996 %}
4997 ins_pipe(ialu_reg_mem);
4998 %}
4999
5000 // Load Integer with mask 0xFFFF into Long Register
5001 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5002 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5003
5004 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5005 ins_encode %{
5006 __ movzwq($dst$$Register, $mem$$Address);
5007 %}
5008 ins_pipe(ialu_reg_mem);
5009 %}
5010
5011 // Load Integer with a 31-bit mask into Long Register
5012 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5013 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5014 effect(KILL cr);
5015
5016 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5017 "andl $dst, $mask" %}
5018 ins_encode %{
5019 Register Rdst = $dst$$Register;
5020 __ movl(Rdst, $mem$$Address);
5021 __ andl(Rdst, $mask$$constant);
5022 %}
5023 ins_pipe(ialu_reg_mem);
5024 %}
5025
5026 // Load Unsigned Integer into Long Register
5027 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5028 %{
5029 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5030
5031 ins_cost(125);
5032 format %{ "movl $dst, $mem\t# uint -> long" %}
5033
5034 ins_encode %{
5035 __ movl($dst$$Register, $mem$$Address);
5036 %}
5037
5038 ins_pipe(ialu_reg_mem);
5039 %}
5040
5041 // Load Long
5042 instruct loadL(rRegL dst, memory mem)
5043 %{
5044 match(Set dst (LoadL mem));
5045
5046 ins_cost(125);
5047 format %{ "movq $dst, $mem\t# long" %}
5048
5049 ins_encode %{
5050 __ movq($dst$$Register, $mem$$Address);
5051 %}
5052
5053 ins_pipe(ialu_reg_mem); // XXX
5054 %}
5055
5056 // Load Range
5057 instruct loadRange(rRegI dst, memory mem)
5058 %{
5059 match(Set dst (LoadRange mem));
5060
5061 ins_cost(125); // XXX
5062 format %{ "movl $dst, $mem\t# range" %}
5063 opcode(0x8B);
5064 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5065 ins_pipe(ialu_reg_mem);
5066 %}
5067
5068 // Load Pointer
5069 instruct loadP(rRegP dst, memory mem)
5070 %{
5071 match(Set dst (LoadP mem));
5072
5073 ins_cost(125); // XXX
5074 format %{ "movq $dst, $mem\t# ptr" %}
5075 opcode(0x8B);
5076 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5077 ins_pipe(ialu_reg_mem); // XXX
5078 %}
5079
5080 // Load Compressed Pointer
5081 instruct loadN(rRegN dst, memory mem)
5082 %{
5083 match(Set dst (LoadN mem));
5084
5085 ins_cost(125); // XXX
5086 format %{ "movl $dst, $mem\t# compressed ptr" %}
5087 ins_encode %{
5088 __ movl($dst$$Register, $mem$$Address);
5089 %}
5090 ins_pipe(ialu_reg_mem); // XXX
5091 %}
5092
5093
5094 // Load Klass Pointer
5095 instruct loadKlass(rRegP dst, memory mem)
5096 %{
5097 match(Set dst (LoadKlass mem));
5098
5099 ins_cost(125); // XXX
5100 format %{ "movq $dst, $mem\t# class" %}
5101 opcode(0x8B);
5102 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5103 ins_pipe(ialu_reg_mem); // XXX
5104 %}
5105
5106 // Load narrow Klass Pointer
5107 instruct loadNKlass(rRegN dst, memory mem)
5108 %{
5109 match(Set dst (LoadNKlass mem));
5110
5111 ins_cost(125); // XXX
5112 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5113 ins_encode %{
5114 __ movl($dst$$Register, $mem$$Address);
5115 %}
5116 ins_pipe(ialu_reg_mem); // XXX
5117 %}
5118
5119 // Load Float
5120 instruct loadF(regF dst, memory mem)
5121 %{
5122 match(Set dst (LoadF mem));
5123
5124 ins_cost(145); // XXX
5125 format %{ "movss $dst, $mem\t# float" %}
5126 ins_encode %{
5127 __ movflt($dst$$XMMRegister, $mem$$Address);
5128 %}
5129 ins_pipe(pipe_slow); // XXX
5130 %}
5131
5132 // Load Double
5133 instruct loadD_partial(regD dst, memory mem)
5134 %{
5135 predicate(!UseXmmLoadAndClearUpper);
5136 match(Set dst (LoadD mem));
5137
5138 ins_cost(145); // XXX
5139 format %{ "movlpd $dst, $mem\t# double" %}
5140 ins_encode %{
5141 __ movdbl($dst$$XMMRegister, $mem$$Address);
5142 %}
5143 ins_pipe(pipe_slow); // XXX
5144 %}
5145
5146 instruct loadD(regD dst, memory mem)
5147 %{
5148 predicate(UseXmmLoadAndClearUpper);
5149 match(Set dst (LoadD mem));
5150
5151 ins_cost(145); // XXX
5152 format %{ "movsd $dst, $mem\t# double" %}
5153 ins_encode %{
5154 __ movdbl($dst$$XMMRegister, $mem$$Address);
5155 %}
5156 ins_pipe(pipe_slow); // XXX
5157 %}
5158
5159 // Load Effective Address
5160 instruct leaP8(rRegP dst, indOffset8 mem)
5161 %{
5162 match(Set dst mem);
5163
5164 ins_cost(110); // XXX
5165 format %{ "leaq $dst, $mem\t# ptr 8" %}
5166 opcode(0x8D);
5167 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5168 ins_pipe(ialu_reg_reg_fat);
5169 %}
5170
5171 instruct leaP32(rRegP dst, indOffset32 mem)
5172 %{
5173 match(Set dst mem);
5174
5175 ins_cost(110);
5176 format %{ "leaq $dst, $mem\t# ptr 32" %}
5177 opcode(0x8D);
5178 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5179 ins_pipe(ialu_reg_reg_fat);
5180 %}
5181
5182 // instruct leaPIdx(rRegP dst, indIndex mem)
5183 // %{
5184 // match(Set dst mem);
5185
5186 // ins_cost(110);
5187 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5188 // opcode(0x8D);
5189 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5190 // ins_pipe(ialu_reg_reg_fat);
5191 // %}
5192
5193 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5194 %{
5195 match(Set dst mem);
5196
5197 ins_cost(110);
5198 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5199 opcode(0x8D);
5200 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5201 ins_pipe(ialu_reg_reg_fat);
5202 %}
5203
5204 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5205 %{
5206 match(Set dst mem);
5207
5208 ins_cost(110);
5209 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5210 opcode(0x8D);
5211 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5212 ins_pipe(ialu_reg_reg_fat);
5213 %}
5214
5215 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5216 %{
5217 match(Set dst mem);
5218
5219 ins_cost(110);
5220 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5221 opcode(0x8D);
5222 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5223 ins_pipe(ialu_reg_reg_fat);
5224 %}
5225
5226 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5227 %{
5228 match(Set dst mem);
5229
5230 ins_cost(110);
5231 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5232 opcode(0x8D);
5233 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5234 ins_pipe(ialu_reg_reg_fat);
5235 %}
5236
5237 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5238 %{
5239 match(Set dst mem);
5240
5241 ins_cost(110);
5242 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5243 opcode(0x8D);
5244 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5245 ins_pipe(ialu_reg_reg_fat);
5246 %}
5247
5248 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5249 %{
5250 match(Set dst mem);
5251
5252 ins_cost(110);
5253 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5254 opcode(0x8D);
5255 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5256 ins_pipe(ialu_reg_reg_fat);
5257 %}
5258
5259 // Load Effective Address which uses Narrow (32-bits) oop
5260 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5261 %{
5262 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5263 match(Set dst mem);
5264
5265 ins_cost(110);
5266 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5267 opcode(0x8D);
5268 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5269 ins_pipe(ialu_reg_reg_fat);
5270 %}
5271
5272 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5273 %{
5274 predicate(Universe::narrow_oop_shift() == 0);
5275 match(Set dst mem);
5276
5277 ins_cost(110); // XXX
5278 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5279 opcode(0x8D);
5280 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5281 ins_pipe(ialu_reg_reg_fat);
5282 %}
5283
5284 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5285 %{
5286 predicate(Universe::narrow_oop_shift() == 0);
5287 match(Set dst mem);
5288
5289 ins_cost(110);
5290 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5291 opcode(0x8D);
5292 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5293 ins_pipe(ialu_reg_reg_fat);
5294 %}
5295
5296 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5297 %{
5298 predicate(Universe::narrow_oop_shift() == 0);
5299 match(Set dst mem);
5300
5301 ins_cost(110);
5302 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5303 opcode(0x8D);
5304 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5305 ins_pipe(ialu_reg_reg_fat);
5306 %}
5307
5308 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5309 %{
5310 predicate(Universe::narrow_oop_shift() == 0);
5311 match(Set dst mem);
5312
5313 ins_cost(110);
5314 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5315 opcode(0x8D);
5316 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5317 ins_pipe(ialu_reg_reg_fat);
5318 %}
5319
5320 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5321 %{
5322 predicate(Universe::narrow_oop_shift() == 0);
5323 match(Set dst mem);
5324
5325 ins_cost(110);
5326 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5327 opcode(0x8D);
5328 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5329 ins_pipe(ialu_reg_reg_fat);
5330 %}
5331
5332 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5333 %{
5334 predicate(Universe::narrow_oop_shift() == 0);
5335 match(Set dst mem);
5336
5337 ins_cost(110);
5338 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5339 opcode(0x8D);
5340 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5341 ins_pipe(ialu_reg_reg_fat);
5342 %}
5343
5344 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5345 %{
5346 predicate(Universe::narrow_oop_shift() == 0);
5347 match(Set dst mem);
5348
5349 ins_cost(110);
5350 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5351 opcode(0x8D);
5352 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5353 ins_pipe(ialu_reg_reg_fat);
5354 %}
5355
5356 instruct loadConI(rRegI dst, immI src)
5357 %{
5358 match(Set dst src);
5359
5360 format %{ "movl $dst, $src\t# int" %}
5361 ins_encode(load_immI(dst, src));
5362 ins_pipe(ialu_reg_fat); // XXX
5363 %}
5364
5365 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5366 %{
5367 match(Set dst src);
5368 effect(KILL cr);
5369
5370 ins_cost(50);
5371 format %{ "xorl $dst, $dst\t# int" %}
5372 opcode(0x33); /* + rd */
5373 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5374 ins_pipe(ialu_reg);
5375 %}
5376
5377 instruct loadConL(rRegL dst, immL src)
5378 %{
5379 match(Set dst src);
5380
5381 ins_cost(150);
5382 format %{ "movq $dst, $src\t# long" %}
5383 ins_encode(load_immL(dst, src));
5384 ins_pipe(ialu_reg);
5385 %}
5386
5387 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5388 %{
5389 match(Set dst src);
5390 effect(KILL cr);
5391
5392 ins_cost(50);
5393 format %{ "xorl $dst, $dst\t# long" %}
5394 opcode(0x33); /* + rd */
5395 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5396 ins_pipe(ialu_reg); // XXX
5397 %}
5398
5399 instruct loadConUL32(rRegL dst, immUL32 src)
5400 %{
5401 match(Set dst src);
5402
5403 ins_cost(60);
5404 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5405 ins_encode(load_immUL32(dst, src));
5406 ins_pipe(ialu_reg);
5407 %}
5408
5409 instruct loadConL32(rRegL dst, immL32 src)
5410 %{
5411 match(Set dst src);
5412
5413 ins_cost(70);
5414 format %{ "movq $dst, $src\t# long (32-bit)" %}
5415 ins_encode(load_immL32(dst, src));
5416 ins_pipe(ialu_reg);
5417 %}
5418
5419 instruct loadConP(rRegP dst, immP con) %{
5420 match(Set dst con);
5421
5422 format %{ "movq $dst, $con\t# ptr" %}
5423 ins_encode(load_immP(dst, con));
5424 ins_pipe(ialu_reg_fat); // XXX
5425 %}
5426
5427 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5428 %{
5429 match(Set dst src);
5430 effect(KILL cr);
5431
5432 ins_cost(50);
5433 format %{ "xorl $dst, $dst\t# ptr" %}
5434 opcode(0x33); /* + rd */
5435 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5436 ins_pipe(ialu_reg);
5437 %}
5438
5439 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5440 %{
5441 match(Set dst src);
5442 effect(KILL cr);
5443
5444 ins_cost(60);
5445 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5446 ins_encode(load_immP31(dst, src));
5447 ins_pipe(ialu_reg);
5448 %}
5449
5450 instruct loadConF(regF dst, immF con) %{
5451 match(Set dst con);
5452 ins_cost(125);
5453 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5454 ins_encode %{
5455 __ movflt($dst$$XMMRegister, $constantaddress($con));
5456 %}
5457 ins_pipe(pipe_slow);
5458 %}
5459
5460 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5461 match(Set dst src);
5462 effect(KILL cr);
5463 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5464 ins_encode %{
5465 __ xorq($dst$$Register, $dst$$Register);
5466 %}
5467 ins_pipe(ialu_reg);
5468 %}
5469
5470 instruct loadConN(rRegN dst, immN src) %{
5471 match(Set dst src);
5472
5473 ins_cost(125);
5474 format %{ "movl $dst, $src\t# compressed ptr" %}
5475 ins_encode %{
5476 address con = (address)$src$$constant;
5477 if (con == NULL) {
5478 ShouldNotReachHere();
5479 } else {
5480 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5481 }
5482 %}
5483 ins_pipe(ialu_reg_fat); // XXX
5484 %}
5485
5486 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5487 match(Set dst src);
5488
5489 ins_cost(125);
5490 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5491 ins_encode %{
5492 address con = (address)$src$$constant;
5493 if (con == NULL) {
5494 ShouldNotReachHere();
5495 } else {
5496 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5497 }
5498 %}
5499 ins_pipe(ialu_reg_fat); // XXX
5500 %}
5501
5502 instruct loadConF0(regF dst, immF0 src)
5503 %{
5504 match(Set dst src);
5505 ins_cost(100);
5506
5507 format %{ "xorps $dst, $dst\t# float 0.0" %}
5508 ins_encode %{
5509 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5510 %}
5511 ins_pipe(pipe_slow);
5512 %}
5513
5514 // Use the same format since predicate() can not be used here.
5515 instruct loadConD(regD dst, immD con) %{
5516 match(Set dst con);
5517 ins_cost(125);
5518 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5519 ins_encode %{
5520 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5521 %}
5522 ins_pipe(pipe_slow);
5523 %}
5524
5525 instruct loadConD0(regD dst, immD0 src)
5526 %{
5527 match(Set dst src);
5528 ins_cost(100);
5529
5530 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5531 ins_encode %{
5532 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5533 %}
5534 ins_pipe(pipe_slow);
5535 %}
5536
5537 instruct loadSSI(rRegI dst, stackSlotI src)
5538 %{
5539 match(Set dst src);
5540
5541 ins_cost(125);
5542 format %{ "movl $dst, $src\t# int stk" %}
5543 opcode(0x8B);
5544 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5545 ins_pipe(ialu_reg_mem);
5546 %}
5547
5548 instruct loadSSL(rRegL dst, stackSlotL src)
5549 %{
5550 match(Set dst src);
5551
5552 ins_cost(125);
5553 format %{ "movq $dst, $src\t# long stk" %}
5554 opcode(0x8B);
5555 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5556 ins_pipe(ialu_reg_mem);
5557 %}
5558
5559 instruct loadSSP(rRegP dst, stackSlotP src)
5560 %{
5561 match(Set dst src);
5562
5563 ins_cost(125);
5564 format %{ "movq $dst, $src\t# ptr stk" %}
5565 opcode(0x8B);
5566 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5567 ins_pipe(ialu_reg_mem);
5568 %}
5569
5570 instruct loadSSF(regF dst, stackSlotF src)
5571 %{
5572 match(Set dst src);
5573
5574 ins_cost(125);
5575 format %{ "movss $dst, $src\t# float stk" %}
5576 ins_encode %{
5577 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5578 %}
5579 ins_pipe(pipe_slow); // XXX
5580 %}
5581
5582 // Use the same format since predicate() can not be used here.
5583 instruct loadSSD(regD dst, stackSlotD src)
5584 %{
5585 match(Set dst src);
5586
5587 ins_cost(125);
5588 format %{ "movsd $dst, $src\t# double stk" %}
5589 ins_encode %{
5590 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5591 %}
5592 ins_pipe(pipe_slow); // XXX
5593 %}
5594
5595 // Prefetch instructions for allocation.
5596 // Must be safe to execute with invalid address (cannot fault).
5597
5598 instruct prefetchAlloc( memory mem ) %{
5599 predicate(AllocatePrefetchInstr==3);
5600 match(PrefetchAllocation mem);
5601 ins_cost(125);
5602
5603 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5604 ins_encode %{
5605 __ prefetchw($mem$$Address);
5606 %}
5607 ins_pipe(ialu_mem);
5608 %}
5609
5610 instruct prefetchAllocNTA( memory mem ) %{
5611 predicate(AllocatePrefetchInstr==0);
5612 match(PrefetchAllocation mem);
5613 ins_cost(125);
5614
5615 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5616 ins_encode %{
5617 __ prefetchnta($mem$$Address);
5618 %}
5619 ins_pipe(ialu_mem);
5620 %}
5621
5622 instruct prefetchAllocT0( memory mem ) %{
5623 predicate(AllocatePrefetchInstr==1);
5624 match(PrefetchAllocation mem);
5625 ins_cost(125);
5626
5627 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5628 ins_encode %{
5629 __ prefetcht0($mem$$Address);
5630 %}
5631 ins_pipe(ialu_mem);
5632 %}
5633
5634 instruct prefetchAllocT2( memory mem ) %{
5635 predicate(AllocatePrefetchInstr==2);
5636 match(PrefetchAllocation mem);
5637 ins_cost(125);
5638
5639 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5640 ins_encode %{
5641 __ prefetcht2($mem$$Address);
5642 %}
5643 ins_pipe(ialu_mem);
5644 %}
5645
5646 //----------Store Instructions-------------------------------------------------
5647
5648 // Store Byte
5649 instruct storeB(memory mem, rRegI src)
5650 %{
5651 match(Set mem (StoreB mem src));
5652
5653 ins_cost(125); // XXX
5654 format %{ "movb $mem, $src\t# byte" %}
5655 opcode(0x88);
5656 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5657 ins_pipe(ialu_mem_reg);
5658 %}
5659
5660 // Store Char/Short
5661 instruct storeC(memory mem, rRegI src)
5662 %{
5663 match(Set mem (StoreC mem src));
5664
5665 ins_cost(125); // XXX
5666 format %{ "movw $mem, $src\t# char/short" %}
5667 opcode(0x89);
5668 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5669 ins_pipe(ialu_mem_reg);
5670 %}
5671
5672 // Store Integer
5673 instruct storeI(memory mem, rRegI src)
5674 %{
5675 match(Set mem (StoreI mem src));
5676
5677 ins_cost(125); // XXX
5678 format %{ "movl $mem, $src\t# int" %}
5679 opcode(0x89);
5680 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5681 ins_pipe(ialu_mem_reg);
5682 %}
5683
5684 // Store Long
5685 instruct storeL(memory mem, rRegL src)
5686 %{
5687 match(Set mem (StoreL mem src));
5688
5689 ins_cost(125); // XXX
5690 format %{ "movq $mem, $src\t# long" %}
5691 opcode(0x89);
5692 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5693 ins_pipe(ialu_mem_reg); // XXX
5694 %}
5695
5696 // Store Pointer
5697 instruct storeP(memory mem, any_RegP src)
5698 %{
5699 match(Set mem (StoreP mem src));
5700
5701 ins_cost(125); // XXX
5702 format %{ "movq $mem, $src\t# ptr" %}
5703 opcode(0x89);
5704 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5705 ins_pipe(ialu_mem_reg);
5706 %}
5707
5708 instruct storeImmP0(memory mem, immP0 zero)
5709 %{
5710 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5711 match(Set mem (StoreP mem zero));
5712
5713 ins_cost(125); // XXX
5714 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5715 ins_encode %{
5716 __ movq($mem$$Address, r12);
5717 %}
5718 ins_pipe(ialu_mem_reg);
5719 %}
5720
5721 // Store NULL Pointer, mark word, or other simple pointer constant.
5722 instruct storeImmP(memory mem, immP31 src)
5723 %{
5724 match(Set mem (StoreP mem src));
5725
5726 ins_cost(150); // XXX
5727 format %{ "movq $mem, $src\t# ptr" %}
5728 opcode(0xC7); /* C7 /0 */
5729 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5730 ins_pipe(ialu_mem_imm);
5731 %}
5732
5733 // Store Compressed Pointer
5734 instruct storeN(memory mem, rRegN src)
5735 %{
5736 match(Set mem (StoreN mem src));
5737
5738 ins_cost(125); // XXX
5739 format %{ "movl $mem, $src\t# compressed ptr" %}
5740 ins_encode %{
5741 __ movl($mem$$Address, $src$$Register);
5742 %}
5743 ins_pipe(ialu_mem_reg);
5744 %}
5745
5746 instruct storeNKlass(memory mem, rRegN src)
5747 %{
5748 match(Set mem (StoreNKlass mem src));
5749
5750 ins_cost(125); // XXX
5751 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5752 ins_encode %{
5753 __ movl($mem$$Address, $src$$Register);
5754 %}
5755 ins_pipe(ialu_mem_reg);
5756 %}
5757
5758 instruct storeImmN0(memory mem, immN0 zero)
5759 %{
5760 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5761 match(Set mem (StoreN mem zero));
5762
5763 ins_cost(125); // XXX
5764 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5765 ins_encode %{
5766 __ movl($mem$$Address, r12);
5767 %}
5768 ins_pipe(ialu_mem_reg);
5769 %}
5770
5771 instruct storeImmN(memory mem, immN src)
5772 %{
5773 match(Set mem (StoreN mem src));
5774
5775 ins_cost(150); // XXX
5776 format %{ "movl $mem, $src\t# compressed ptr" %}
5777 ins_encode %{
5778 address con = (address)$src$$constant;
5779 if (con == NULL) {
5780 __ movl($mem$$Address, (int32_t)0);
5781 } else {
5782 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5783 }
5784 %}
5785 ins_pipe(ialu_mem_imm);
5786 %}
5787
5788 instruct storeImmNKlass(memory mem, immNKlass src)
5789 %{
5790 match(Set mem (StoreNKlass mem src));
5791
5792 ins_cost(150); // XXX
5793 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5794 ins_encode %{
5795 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5796 %}
5797 ins_pipe(ialu_mem_imm);
5798 %}
5799
5800 // Store Integer Immediate
5801 instruct storeImmI0(memory mem, immI0 zero)
5802 %{
5803 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5804 match(Set mem (StoreI mem zero));
5805
5806 ins_cost(125); // XXX
5807 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5808 ins_encode %{
5809 __ movl($mem$$Address, r12);
5810 %}
5811 ins_pipe(ialu_mem_reg);
5812 %}
5813
5814 instruct storeImmI(memory mem, immI src)
5815 %{
5816 match(Set mem (StoreI mem src));
5817
5818 ins_cost(150);
5819 format %{ "movl $mem, $src\t# int" %}
5820 opcode(0xC7); /* C7 /0 */
5821 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5822 ins_pipe(ialu_mem_imm);
5823 %}
5824
5825 // Store Long Immediate
5826 instruct storeImmL0(memory mem, immL0 zero)
5827 %{
5828 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5829 match(Set mem (StoreL mem zero));
5830
5831 ins_cost(125); // XXX
5832 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5833 ins_encode %{
5834 __ movq($mem$$Address, r12);
5835 %}
5836 ins_pipe(ialu_mem_reg);
5837 %}
5838
5839 instruct storeImmL(memory mem, immL32 src)
5840 %{
5841 match(Set mem (StoreL mem src));
5842
5843 ins_cost(150);
5844 format %{ "movq $mem, $src\t# long" %}
5845 opcode(0xC7); /* C7 /0 */
5846 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5847 ins_pipe(ialu_mem_imm);
5848 %}
5849
5850 // Store Short/Char Immediate
5851 instruct storeImmC0(memory mem, immI0 zero)
5852 %{
5853 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5854 match(Set mem (StoreC mem zero));
5855
5856 ins_cost(125); // XXX
5857 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5858 ins_encode %{
5859 __ movw($mem$$Address, r12);
5860 %}
5861 ins_pipe(ialu_mem_reg);
5862 %}
5863
5864 instruct storeImmI16(memory mem, immI16 src)
5865 %{
5866 predicate(UseStoreImmI16);
5867 match(Set mem (StoreC mem src));
5868
5869 ins_cost(150);
5870 format %{ "movw $mem, $src\t# short/char" %}
5871 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5872 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5873 ins_pipe(ialu_mem_imm);
5874 %}
5875
5876 // Store Byte Immediate
5877 instruct storeImmB0(memory mem, immI0 zero)
5878 %{
5879 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5880 match(Set mem (StoreB mem zero));
5881
5882 ins_cost(125); // XXX
5883 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5884 ins_encode %{
5885 __ movb($mem$$Address, r12);
5886 %}
5887 ins_pipe(ialu_mem_reg);
5888 %}
5889
5890 instruct storeImmB(memory mem, immI8 src)
5891 %{
5892 match(Set mem (StoreB mem src));
5893
5894 ins_cost(150); // XXX
5895 format %{ "movb $mem, $src\t# byte" %}
5896 opcode(0xC6); /* C6 /0 */
5897 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5898 ins_pipe(ialu_mem_imm);
5899 %}
5900
5901 // Store CMS card-mark Immediate
5902 instruct storeImmCM0_reg(memory mem, immI0 zero)
5903 %{
5904 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5905 match(Set mem (StoreCM mem zero));
5906
5907 ins_cost(125); // XXX
5908 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5909 ins_encode %{
5910 __ movb($mem$$Address, r12);
5911 %}
5912 ins_pipe(ialu_mem_reg);
5913 %}
5914
5915 instruct storeImmCM0(memory mem, immI0 src)
5916 %{
5917 match(Set mem (StoreCM mem src));
5918
5919 ins_cost(150); // XXX
5920 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5921 opcode(0xC6); /* C6 /0 */
5922 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5923 ins_pipe(ialu_mem_imm);
5924 %}
5925
5926 // Store Float
5927 instruct storeF(memory mem, regF src)
5928 %{
5929 match(Set mem (StoreF mem src));
5930
5931 ins_cost(95); // XXX
5932 format %{ "movss $mem, $src\t# float" %}
5933 ins_encode %{
5934 __ movflt($mem$$Address, $src$$XMMRegister);
5935 %}
5936 ins_pipe(pipe_slow); // XXX
5937 %}
5938
5939 // Store immediate Float value (it is faster than store from XMM register)
5940 instruct storeF0(memory mem, immF0 zero)
5941 %{
5942 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5943 match(Set mem (StoreF mem zero));
5944
5945 ins_cost(25); // XXX
5946 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5947 ins_encode %{
5948 __ movl($mem$$Address, r12);
5949 %}
5950 ins_pipe(ialu_mem_reg);
5951 %}
5952
5953 instruct storeF_imm(memory mem, immF src)
5954 %{
5955 match(Set mem (StoreF mem src));
5956
5957 ins_cost(50);
5958 format %{ "movl $mem, $src\t# float" %}
5959 opcode(0xC7); /* C7 /0 */
5960 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5961 ins_pipe(ialu_mem_imm);
5962 %}
5963
5964 // Store Double
5965 instruct storeD(memory mem, regD src)
5966 %{
5967 match(Set mem (StoreD mem src));
5968
5969 ins_cost(95); // XXX
5970 format %{ "movsd $mem, $src\t# double" %}
5971 ins_encode %{
5972 __ movdbl($mem$$Address, $src$$XMMRegister);
5973 %}
5974 ins_pipe(pipe_slow); // XXX
5975 %}
5976
5977 // Store immediate double 0.0 (it is faster than store from XMM register)
5978 instruct storeD0_imm(memory mem, immD0 src)
5979 %{
5980 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5981 match(Set mem (StoreD mem src));
5982
5983 ins_cost(50);
5984 format %{ "movq $mem, $src\t# double 0." %}
5985 opcode(0xC7); /* C7 /0 */
5986 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5987 ins_pipe(ialu_mem_imm);
5988 %}
5989
5990 instruct storeD0(memory mem, immD0 zero)
5991 %{
5992 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5993 match(Set mem (StoreD mem zero));
5994
5995 ins_cost(25); // XXX
5996 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5997 ins_encode %{
5998 __ movq($mem$$Address, r12);
5999 %}
6000 ins_pipe(ialu_mem_reg);
6001 %}
6002
6003 instruct storeSSI(stackSlotI dst, rRegI src)
6004 %{
6005 match(Set dst src);
6006
6007 ins_cost(100);
6008 format %{ "movl $dst, $src\t# int stk" %}
6009 opcode(0x89);
6010 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6011 ins_pipe( ialu_mem_reg );
6012 %}
6013
6014 instruct storeSSL(stackSlotL dst, rRegL src)
6015 %{
6016 match(Set dst src);
6017
6018 ins_cost(100);
6019 format %{ "movq $dst, $src\t# long stk" %}
6020 opcode(0x89);
6021 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6022 ins_pipe(ialu_mem_reg);
6023 %}
6024
6025 instruct storeSSP(stackSlotP dst, rRegP src)
6026 %{
6027 match(Set dst src);
6028
6029 ins_cost(100);
6030 format %{ "movq $dst, $src\t# ptr stk" %}
6031 opcode(0x89);
6032 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6033 ins_pipe(ialu_mem_reg);
6034 %}
6035
6036 instruct storeSSF(stackSlotF dst, regF src)
6037 %{
6038 match(Set dst src);
6039
6040 ins_cost(95); // XXX
6041 format %{ "movss $dst, $src\t# float stk" %}
6042 ins_encode %{
6043 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6044 %}
6045 ins_pipe(pipe_slow); // XXX
6046 %}
6047
6048 instruct storeSSD(stackSlotD dst, regD src)
6049 %{
6050 match(Set dst src);
6051
6052 ins_cost(95); // XXX
6053 format %{ "movsd $dst, $src\t# double stk" %}
6054 ins_encode %{
6055 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6056 %}
6057 ins_pipe(pipe_slow); // XXX
6058 %}
6059
6060 //----------BSWAP Instructions-------------------------------------------------
6061 instruct bytes_reverse_int(rRegI dst) %{
6062 match(Set dst (ReverseBytesI dst));
6063
6064 format %{ "bswapl $dst" %}
6065 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6066 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6067 ins_pipe( ialu_reg );
6068 %}
6069
6070 instruct bytes_reverse_long(rRegL dst) %{
6071 match(Set dst (ReverseBytesL dst));
6072
6073 format %{ "bswapq $dst" %}
6074 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6075 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6076 ins_pipe( ialu_reg);
6077 %}
6078
6079 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6080 match(Set dst (ReverseBytesUS dst));
6081 effect(KILL cr);
6082
6083 format %{ "bswapl $dst\n\t"
6084 "shrl $dst,16\n\t" %}
6085 ins_encode %{
6086 __ bswapl($dst$$Register);
6087 __ shrl($dst$$Register, 16);
6088 %}
6089 ins_pipe( ialu_reg );
6090 %}
6091
6092 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6093 match(Set dst (ReverseBytesS dst));
6094 effect(KILL cr);
6095
6096 format %{ "bswapl $dst\n\t"
6097 "sar $dst,16\n\t" %}
6098 ins_encode %{
6099 __ bswapl($dst$$Register);
6100 __ sarl($dst$$Register, 16);
6101 %}
6102 ins_pipe( ialu_reg );
6103 %}
6104
6105 //---------- Zeros Count Instructions ------------------------------------------
6106
6107 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6108 predicate(UseCountLeadingZerosInstruction);
6109 match(Set dst (CountLeadingZerosI src));
6110 effect(KILL cr);
6111
6112 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6113 ins_encode %{
6114 __ lzcntl($dst$$Register, $src$$Register);
6115 %}
6116 ins_pipe(ialu_reg);
6117 %}
6118
6119 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6120 predicate(!UseCountLeadingZerosInstruction);
6121 match(Set dst (CountLeadingZerosI src));
6122 effect(KILL cr);
6123
6124 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6125 "jnz skip\n\t"
6126 "movl $dst, -1\n"
6127 "skip:\n\t"
6128 "negl $dst\n\t"
6129 "addl $dst, 31" %}
6130 ins_encode %{
6131 Register Rdst = $dst$$Register;
6132 Register Rsrc = $src$$Register;
6133 Label skip;
6134 __ bsrl(Rdst, Rsrc);
6135 __ jccb(Assembler::notZero, skip);
6136 __ movl(Rdst, -1);
6137 __ bind(skip);
6138 __ negl(Rdst);
6139 __ addl(Rdst, BitsPerInt - 1);
6140 %}
6141 ins_pipe(ialu_reg);
6142 %}
6143
6144 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6145 predicate(UseCountLeadingZerosInstruction);
6146 match(Set dst (CountLeadingZerosL src));
6147 effect(KILL cr);
6148
6149 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6150 ins_encode %{
6151 __ lzcntq($dst$$Register, $src$$Register);
6152 %}
6153 ins_pipe(ialu_reg);
6154 %}
6155
6156 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6157 predicate(!UseCountLeadingZerosInstruction);
6158 match(Set dst (CountLeadingZerosL src));
6159 effect(KILL cr);
6160
6161 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6162 "jnz skip\n\t"
6163 "movl $dst, -1\n"
6164 "skip:\n\t"
6165 "negl $dst\n\t"
6166 "addl $dst, 63" %}
6167 ins_encode %{
6168 Register Rdst = $dst$$Register;
6169 Register Rsrc = $src$$Register;
6170 Label skip;
6171 __ bsrq(Rdst, Rsrc);
6172 __ jccb(Assembler::notZero, skip);
6173 __ movl(Rdst, -1);
6174 __ bind(skip);
6175 __ negl(Rdst);
6176 __ addl(Rdst, BitsPerLong - 1);
6177 %}
6178 ins_pipe(ialu_reg);
6179 %}
6180
6181 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6182 predicate(UseCountTrailingZerosInstruction);
6183 match(Set dst (CountTrailingZerosI src));
6184 effect(KILL cr);
6185
6186 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6187 ins_encode %{
6188 __ tzcntl($dst$$Register, $src$$Register);
6189 %}
6190 ins_pipe(ialu_reg);
6191 %}
6192
6193 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6194 predicate(!UseCountTrailingZerosInstruction);
6195 match(Set dst (CountTrailingZerosI src));
6196 effect(KILL cr);
6197
6198 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6199 "jnz done\n\t"
6200 "movl $dst, 32\n"
6201 "done:" %}
6202 ins_encode %{
6203 Register Rdst = $dst$$Register;
6204 Label done;
6205 __ bsfl(Rdst, $src$$Register);
6206 __ jccb(Assembler::notZero, done);
6207 __ movl(Rdst, BitsPerInt);
6208 __ bind(done);
6209 %}
6210 ins_pipe(ialu_reg);
6211 %}
6212
6213 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6214 predicate(UseCountTrailingZerosInstruction);
6215 match(Set dst (CountTrailingZerosL src));
6216 effect(KILL cr);
6217
6218 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6219 ins_encode %{
6220 __ tzcntq($dst$$Register, $src$$Register);
6221 %}
6222 ins_pipe(ialu_reg);
6223 %}
6224
6225 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6226 predicate(!UseCountTrailingZerosInstruction);
6227 match(Set dst (CountTrailingZerosL src));
6228 effect(KILL cr);
6229
6230 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6231 "jnz done\n\t"
6232 "movl $dst, 64\n"
6233 "done:" %}
6234 ins_encode %{
6235 Register Rdst = $dst$$Register;
6236 Label done;
6237 __ bsfq(Rdst, $src$$Register);
6238 __ jccb(Assembler::notZero, done);
6239 __ movl(Rdst, BitsPerLong);
6240 __ bind(done);
6241 %}
6242 ins_pipe(ialu_reg);
6243 %}
6244
6245
6246 //---------- Population Count Instructions -------------------------------------
6247
6248 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6249 predicate(UsePopCountInstruction);
6250 match(Set dst (PopCountI src));
6251 effect(KILL cr);
6252
6253 format %{ "popcnt $dst, $src" %}
6254 ins_encode %{
6255 __ popcntl($dst$$Register, $src$$Register);
6256 %}
6257 ins_pipe(ialu_reg);
6258 %}
6259
6260 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6261 predicate(UsePopCountInstruction);
6262 match(Set dst (PopCountI (LoadI mem)));
6263 effect(KILL cr);
6264
6265 format %{ "popcnt $dst, $mem" %}
6266 ins_encode %{
6267 __ popcntl($dst$$Register, $mem$$Address);
6268 %}
6269 ins_pipe(ialu_reg);
6270 %}
6271
6272 // Note: Long.bitCount(long) returns an int.
6273 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6274 predicate(UsePopCountInstruction);
6275 match(Set dst (PopCountL src));
6276 effect(KILL cr);
6277
6278 format %{ "popcnt $dst, $src" %}
6279 ins_encode %{
6280 __ popcntq($dst$$Register, $src$$Register);
6281 %}
6282 ins_pipe(ialu_reg);
6283 %}
6284
6285 // Note: Long.bitCount(long) returns an int.
6286 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6287 predicate(UsePopCountInstruction);
6288 match(Set dst (PopCountL (LoadL mem)));
6289 effect(KILL cr);
6290
6291 format %{ "popcnt $dst, $mem" %}
6292 ins_encode %{
6293 __ popcntq($dst$$Register, $mem$$Address);
6294 %}
6295 ins_pipe(ialu_reg);
6296 %}
6297
6298
6299 //----------MemBar Instructions-----------------------------------------------
6300 // Memory barrier flavors
6301
6302 instruct membar_acquire()
6303 %{
6304 match(MemBarAcquire);
6305 match(LoadFence);
6306 ins_cost(0);
6307
6308 size(0);
6309 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6310 ins_encode();
6311 ins_pipe(empty);
6312 %}
6313
6314 instruct membar_acquire_lock()
6315 %{
6316 match(MemBarAcquireLock);
6317 ins_cost(0);
6318
6319 size(0);
6320 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6321 ins_encode();
6322 ins_pipe(empty);
6323 %}
6324
6325 instruct membar_release()
6326 %{
6327 match(MemBarRelease);
6328 match(StoreFence);
6329 ins_cost(0);
6330
6331 size(0);
6332 format %{ "MEMBAR-release ! (empty encoding)" %}
6333 ins_encode();
6334 ins_pipe(empty);
6335 %}
6336
6337 instruct membar_release_lock()
6338 %{
6339 match(MemBarReleaseLock);
6340 ins_cost(0);
6341
6342 size(0);
6343 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6344 ins_encode();
6345 ins_pipe(empty);
6346 %}
6347
6348 instruct membar_volatile(rFlagsReg cr) %{
6349 match(MemBarVolatile);
6350 effect(KILL cr);
6351 ins_cost(400);
6352
6353 format %{
6354 $$template
6355 if (os::is_MP()) {
6356 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6357 } else {
6358 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6359 }
6360 %}
6361 ins_encode %{
6362 __ membar(Assembler::StoreLoad);
6363 %}
6364 ins_pipe(pipe_slow);
6365 %}
6366
6367 instruct unnecessary_membar_volatile()
6368 %{
6369 match(MemBarVolatile);
6370 predicate(Matcher::post_store_load_barrier(n));
6371 ins_cost(0);
6372
6373 size(0);
6374 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6375 ins_encode();
6376 ins_pipe(empty);
6377 %}
6378
6379 instruct membar_storestore() %{
6380 match(MemBarStoreStore);
6381 ins_cost(0);
6382
6383 size(0);
6384 format %{ "MEMBAR-storestore (empty encoding)" %}
6385 ins_encode( );
6386 ins_pipe(empty);
6387 %}
6388
6389 //----------Move Instructions--------------------------------------------------
6390
6391 instruct castX2P(rRegP dst, rRegL src)
6392 %{
6393 match(Set dst (CastX2P src));
6394
6395 format %{ "movq $dst, $src\t# long->ptr" %}
6396 ins_encode %{
6397 if ($dst$$reg != $src$$reg) {
6398 __ movptr($dst$$Register, $src$$Register);
6399 }
6400 %}
6401 ins_pipe(ialu_reg_reg); // XXX
6402 %}
6403
6404 instruct castP2X(rRegL dst, rRegP src)
6405 %{
6406 match(Set dst (CastP2X src));
6407
6408 format %{ "movq $dst, $src\t# ptr -> long" %}
6409 ins_encode %{
6410 if ($dst$$reg != $src$$reg) {
6411 __ movptr($dst$$Register, $src$$Register);
6412 }
6413 %}
6414 ins_pipe(ialu_reg_reg); // XXX
6415 %}
6416
6417 // Convert oop into int for vectors alignment masking
6418 instruct convP2I(rRegI dst, rRegP src)
6419 %{
6420 match(Set dst (ConvL2I (CastP2X src)));
6421
6422 format %{ "movl $dst, $src\t# ptr -> int" %}
6423 ins_encode %{
6424 __ movl($dst$$Register, $src$$Register);
6425 %}
6426 ins_pipe(ialu_reg_reg); // XXX
6427 %}
6428
6429 // Convert compressed oop into int for vectors alignment masking
6430 // in case of 32bit oops (heap < 4Gb).
6431 instruct convN2I(rRegI dst, rRegN src)
6432 %{
6433 predicate(Universe::narrow_oop_shift() == 0);
6434 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6435
6436 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6437 ins_encode %{
6438 __ movl($dst$$Register, $src$$Register);
6439 %}
6440 ins_pipe(ialu_reg_reg); // XXX
6441 %}
6442
6443 // Convert oop pointer into compressed form
6444 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6445 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6446 match(Set dst (EncodeP src));
6447 effect(KILL cr);
6448 format %{ "encode_heap_oop $dst,$src" %}
6449 ins_encode %{
6450 Register s = $src$$Register;
6451 Register d = $dst$$Register;
6452 if (s != d) {
6453 __ movq(d, s);
6454 }
6455 __ encode_heap_oop(d);
6456 %}
6457 ins_pipe(ialu_reg_long);
6458 %}
6459
6460 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6461 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6462 match(Set dst (EncodeP src));
6463 effect(KILL cr);
6464 format %{ "encode_heap_oop_not_null $dst,$src" %}
6465 ins_encode %{
6466 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6467 %}
6468 ins_pipe(ialu_reg_long);
6469 %}
6470
6471 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6472 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6473 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6474 match(Set dst (DecodeN src));
6475 effect(KILL cr);
6476 format %{ "decode_heap_oop $dst,$src" %}
6477 ins_encode %{
6478 Register s = $src$$Register;
6479 Register d = $dst$$Register;
6480 if (s != d) {
6481 __ movq(d, s);
6482 }
6483 __ decode_heap_oop(d);
6484 %}
6485 ins_pipe(ialu_reg_long);
6486 %}
6487
6488 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6489 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6490 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6491 match(Set dst (DecodeN src));
6492 effect(KILL cr);
6493 format %{ "decode_heap_oop_not_null $dst,$src" %}
6494 ins_encode %{
6495 Register s = $src$$Register;
6496 Register d = $dst$$Register;
6497 if (s != d) {
6498 __ decode_heap_oop_not_null(d, s);
6499 } else {
6500 __ decode_heap_oop_not_null(d);
6501 }
6502 %}
6503 ins_pipe(ialu_reg_long);
6504 %}
6505
6506 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6507 match(Set dst (EncodePKlass src));
6508 effect(KILL cr);
6509 format %{ "encode_klass_not_null $dst,$src" %}
6510 ins_encode %{
6511 __ encode_klass_not_null($dst$$Register, $src$$Register);
6512 %}
6513 ins_pipe(ialu_reg_long);
6514 %}
6515
6516 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6517 match(Set dst (DecodeNKlass src));
6518 effect(KILL cr);
6519 format %{ "decode_klass_not_null $dst,$src" %}
6520 ins_encode %{
6521 Register s = $src$$Register;
6522 Register d = $dst$$Register;
6523 if (s != d) {
6524 __ decode_klass_not_null(d, s);
6525 } else {
6526 __ decode_klass_not_null(d);
6527 }
6528 %}
6529 ins_pipe(ialu_reg_long);
6530 %}
6531
6532
6533 //----------Conditional Move---------------------------------------------------
6534 // Jump
6535 // dummy instruction for generating temp registers
6536 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6537 match(Jump (LShiftL switch_val shift));
6538 ins_cost(350);
6539 predicate(false);
6540 effect(TEMP dest);
6541
6542 format %{ "leaq $dest, [$constantaddress]\n\t"
6543 "jmp [$dest + $switch_val << $shift]\n\t" %}
6544 ins_encode %{
6545 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6546 // to do that and the compiler is using that register as one it can allocate.
6547 // So we build it all by hand.
6548 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6549 // ArrayAddress dispatch(table, index);
6550 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6551 __ lea($dest$$Register, $constantaddress);
6552 __ jmp(dispatch);
6553 %}
6554 ins_pipe(pipe_jmp);
6555 %}
6556
6557 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6558 match(Jump (AddL (LShiftL switch_val shift) offset));
6559 ins_cost(350);
6560 effect(TEMP dest);
6561
6562 format %{ "leaq $dest, [$constantaddress]\n\t"
6563 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6564 ins_encode %{
6565 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6566 // to do that and the compiler is using that register as one it can allocate.
6567 // So we build it all by hand.
6568 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6569 // ArrayAddress dispatch(table, index);
6570 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6571 __ lea($dest$$Register, $constantaddress);
6572 __ jmp(dispatch);
6573 %}
6574 ins_pipe(pipe_jmp);
6575 %}
6576
6577 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6578 match(Jump switch_val);
6579 ins_cost(350);
6580 effect(TEMP dest);
6581
6582 format %{ "leaq $dest, [$constantaddress]\n\t"
6583 "jmp [$dest + $switch_val]\n\t" %}
6584 ins_encode %{
6585 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6586 // to do that and the compiler is using that register as one it can allocate.
6587 // So we build it all by hand.
6588 // Address index(noreg, switch_reg, Address::times_1);
6589 // ArrayAddress dispatch(table, index);
6590 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6591 __ lea($dest$$Register, $constantaddress);
6592 __ jmp(dispatch);
6593 %}
6594 ins_pipe(pipe_jmp);
6595 %}
6596
6597 // Conditional move
6598 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6599 %{
6600 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6601
6602 ins_cost(200); // XXX
6603 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6604 opcode(0x0F, 0x40);
6605 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6606 ins_pipe(pipe_cmov_reg);
6607 %}
6608
6609 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6610 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6611
6612 ins_cost(200); // XXX
6613 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6614 opcode(0x0F, 0x40);
6615 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6616 ins_pipe(pipe_cmov_reg);
6617 %}
6618
6619 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6620 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6621 ins_cost(200);
6622 expand %{
6623 cmovI_regU(cop, cr, dst, src);
6624 %}
6625 %}
6626
6627 // Conditional move
6628 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6629 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6630
6631 ins_cost(250); // XXX
6632 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6633 opcode(0x0F, 0x40);
6634 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6635 ins_pipe(pipe_cmov_mem);
6636 %}
6637
6638 // Conditional move
6639 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6640 %{
6641 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6642
6643 ins_cost(250); // XXX
6644 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6645 opcode(0x0F, 0x40);
6646 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6647 ins_pipe(pipe_cmov_mem);
6648 %}
6649
6650 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6651 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6652 ins_cost(250);
6653 expand %{
6654 cmovI_memU(cop, cr, dst, src);
6655 %}
6656 %}
6657
6658 // Conditional move
6659 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6660 %{
6661 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6662
6663 ins_cost(200); // XXX
6664 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6665 opcode(0x0F, 0x40);
6666 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6667 ins_pipe(pipe_cmov_reg);
6668 %}
6669
6670 // Conditional move
6671 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6672 %{
6673 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6674
6675 ins_cost(200); // XXX
6676 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6677 opcode(0x0F, 0x40);
6678 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6679 ins_pipe(pipe_cmov_reg);
6680 %}
6681
6682 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6683 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6684 ins_cost(200);
6685 expand %{
6686 cmovN_regU(cop, cr, dst, src);
6687 %}
6688 %}
6689
6690 // Conditional move
6691 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6692 %{
6693 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6694
6695 ins_cost(200); // XXX
6696 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6697 opcode(0x0F, 0x40);
6698 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6699 ins_pipe(pipe_cmov_reg); // XXX
6700 %}
6701
6702 // Conditional move
6703 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6704 %{
6705 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6706
6707 ins_cost(200); // XXX
6708 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6709 opcode(0x0F, 0x40);
6710 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6711 ins_pipe(pipe_cmov_reg); // XXX
6712 %}
6713
6714 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6715 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6716 ins_cost(200);
6717 expand %{
6718 cmovP_regU(cop, cr, dst, src);
6719 %}
6720 %}
6721
6722 // DISABLED: Requires the ADLC to emit a bottom_type call that
6723 // correctly meets the two pointer arguments; one is an incoming
6724 // register but the other is a memory operand. ALSO appears to
6725 // be buggy with implicit null checks.
6726 //
6727 //// Conditional move
6728 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6729 //%{
6730 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6731 // ins_cost(250);
6732 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6733 // opcode(0x0F,0x40);
6734 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6735 // ins_pipe( pipe_cmov_mem );
6736 //%}
6737 //
6738 //// Conditional move
6739 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6740 //%{
6741 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6742 // ins_cost(250);
6743 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6744 // opcode(0x0F,0x40);
6745 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6746 // ins_pipe( pipe_cmov_mem );
6747 //%}
6748
6749 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6750 %{
6751 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6752
6753 ins_cost(200); // XXX
6754 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6755 opcode(0x0F, 0x40);
6756 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6757 ins_pipe(pipe_cmov_reg); // XXX
6758 %}
6759
6760 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6761 %{
6762 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6763
6764 ins_cost(200); // XXX
6765 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6766 opcode(0x0F, 0x40);
6767 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6768 ins_pipe(pipe_cmov_mem); // XXX
6769 %}
6770
6771 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6772 %{
6773 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6774
6775 ins_cost(200); // XXX
6776 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6777 opcode(0x0F, 0x40);
6778 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6779 ins_pipe(pipe_cmov_reg); // XXX
6780 %}
6781
6782 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6783 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6784 ins_cost(200);
6785 expand %{
6786 cmovL_regU(cop, cr, dst, src);
6787 %}
6788 %}
6789
6790 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6791 %{
6792 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6793
6794 ins_cost(200); // XXX
6795 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6796 opcode(0x0F, 0x40);
6797 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6798 ins_pipe(pipe_cmov_mem); // XXX
6799 %}
6800
6801 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6802 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6803 ins_cost(200);
6804 expand %{
6805 cmovL_memU(cop, cr, dst, src);
6806 %}
6807 %}
6808
6809 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6810 %{
6811 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6812
6813 ins_cost(200); // XXX
6814 format %{ "jn$cop skip\t# signed cmove float\n\t"
6815 "movss $dst, $src\n"
6816 "skip:" %}
6817 ins_encode %{
6818 Label Lskip;
6819 // Invert sense of branch from sense of CMOV
6820 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6821 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6822 __ bind(Lskip);
6823 %}
6824 ins_pipe(pipe_slow);
6825 %}
6826
6827 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6828 // %{
6829 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6830
6831 // ins_cost(200); // XXX
6832 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6833 // "movss $dst, $src\n"
6834 // "skip:" %}
6835 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6836 // ins_pipe(pipe_slow);
6837 // %}
6838
6839 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6840 %{
6841 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6842
6843 ins_cost(200); // XXX
6844 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6845 "movss $dst, $src\n"
6846 "skip:" %}
6847 ins_encode %{
6848 Label Lskip;
6849 // Invert sense of branch from sense of CMOV
6850 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6851 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6852 __ bind(Lskip);
6853 %}
6854 ins_pipe(pipe_slow);
6855 %}
6856
6857 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6858 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6859 ins_cost(200);
6860 expand %{
6861 cmovF_regU(cop, cr, dst, src);
6862 %}
6863 %}
6864
6865 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6866 %{
6867 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6868
6869 ins_cost(200); // XXX
6870 format %{ "jn$cop skip\t# signed cmove double\n\t"
6871 "movsd $dst, $src\n"
6872 "skip:" %}
6873 ins_encode %{
6874 Label Lskip;
6875 // Invert sense of branch from sense of CMOV
6876 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6877 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6878 __ bind(Lskip);
6879 %}
6880 ins_pipe(pipe_slow);
6881 %}
6882
6883 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6884 %{
6885 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6886
6887 ins_cost(200); // XXX
6888 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6889 "movsd $dst, $src\n"
6890 "skip:" %}
6891 ins_encode %{
6892 Label Lskip;
6893 // Invert sense of branch from sense of CMOV
6894 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6895 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6896 __ bind(Lskip);
6897 %}
6898 ins_pipe(pipe_slow);
6899 %}
6900
6901 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6902 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6903 ins_cost(200);
6904 expand %{
6905 cmovD_regU(cop, cr, dst, src);
6906 %}
6907 %}
6908
6909 //----------Arithmetic Instructions--------------------------------------------
6910 //----------Addition Instructions----------------------------------------------
6911
6912 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6913 %{
6914 match(Set dst (AddI dst src));
6915 effect(KILL cr);
6916
6917 format %{ "addl $dst, $src\t# int" %}
6918 opcode(0x03);
6919 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6920 ins_pipe(ialu_reg_reg);
6921 %}
6922
6923 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6924 %{
6925 match(Set dst (AddI dst src));
6926 effect(KILL cr);
6927
6928 format %{ "addl $dst, $src\t# int" %}
6929 opcode(0x81, 0x00); /* /0 id */
6930 ins_encode(OpcSErm(dst, src), Con8or32(src));
6931 ins_pipe( ialu_reg );
6932 %}
6933
6934 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6935 %{
6936 match(Set dst (AddI dst (LoadI src)));
6937 effect(KILL cr);
6938
6939 ins_cost(125); // XXX
6940 format %{ "addl $dst, $src\t# int" %}
6941 opcode(0x03);
6942 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6943 ins_pipe(ialu_reg_mem);
6944 %}
6945
6946 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6947 %{
6948 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6949 effect(KILL cr);
6950
6951 ins_cost(150); // XXX
6952 format %{ "addl $dst, $src\t# int" %}
6953 opcode(0x01); /* Opcode 01 /r */
6954 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6955 ins_pipe(ialu_mem_reg);
6956 %}
6957
6958 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6959 %{
6960 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6961 effect(KILL cr);
6962
6963 ins_cost(125); // XXX
6964 format %{ "addl $dst, $src\t# int" %}
6965 opcode(0x81); /* Opcode 81 /0 id */
6966 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6967 ins_pipe(ialu_mem_imm);
6968 %}
6969
6970 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6971 %{
6972 predicate(UseIncDec);
6973 match(Set dst (AddI dst src));
6974 effect(KILL cr);
6975
6976 format %{ "incl $dst\t# int" %}
6977 opcode(0xFF, 0x00); // FF /0
6978 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6979 ins_pipe(ialu_reg);
6980 %}
6981
6982 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6983 %{
6984 predicate(UseIncDec);
6985 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6986 effect(KILL cr);
6987
6988 ins_cost(125); // XXX
6989 format %{ "incl $dst\t# int" %}
6990 opcode(0xFF); /* Opcode FF /0 */
6991 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6992 ins_pipe(ialu_mem_imm);
6993 %}
6994
6995 // XXX why does that use AddI
6996 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6997 %{
6998 predicate(UseIncDec);
6999 match(Set dst (AddI dst src));
7000 effect(KILL cr);
7001
7002 format %{ "decl $dst\t# int" %}
7003 opcode(0xFF, 0x01); // FF /1
7004 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7005 ins_pipe(ialu_reg);
7006 %}
7007
7008 // XXX why does that use AddI
7009 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7010 %{
7011 predicate(UseIncDec);
7012 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7013 effect(KILL cr);
7014
7015 ins_cost(125); // XXX
7016 format %{ "decl $dst\t# int" %}
7017 opcode(0xFF); /* Opcode FF /1 */
7018 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7019 ins_pipe(ialu_mem_imm);
7020 %}
7021
7022 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7023 %{
7024 match(Set dst (AddI src0 src1));
7025
7026 ins_cost(110);
7027 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7028 opcode(0x8D); /* 0x8D /r */
7029 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7030 ins_pipe(ialu_reg_reg);
7031 %}
7032
7033 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7034 %{
7035 match(Set dst (AddL dst src));
7036 effect(KILL cr);
7037
7038 format %{ "addq $dst, $src\t# long" %}
7039 opcode(0x03);
7040 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7041 ins_pipe(ialu_reg_reg);
7042 %}
7043
7044 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7045 %{
7046 match(Set dst (AddL dst src));
7047 effect(KILL cr);
7048
7049 format %{ "addq $dst, $src\t# long" %}
7050 opcode(0x81, 0x00); /* /0 id */
7051 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7052 ins_pipe( ialu_reg );
7053 %}
7054
7055 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7056 %{
7057 match(Set dst (AddL dst (LoadL src)));
7058 effect(KILL cr);
7059
7060 ins_cost(125); // XXX
7061 format %{ "addq $dst, $src\t# long" %}
7062 opcode(0x03);
7063 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7064 ins_pipe(ialu_reg_mem);
7065 %}
7066
7067 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7068 %{
7069 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7070 effect(KILL cr);
7071
7072 ins_cost(150); // XXX
7073 format %{ "addq $dst, $src\t# long" %}
7074 opcode(0x01); /* Opcode 01 /r */
7075 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7076 ins_pipe(ialu_mem_reg);
7077 %}
7078
7079 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7080 %{
7081 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7082 effect(KILL cr);
7083
7084 ins_cost(125); // XXX
7085 format %{ "addq $dst, $src\t# long" %}
7086 opcode(0x81); /* Opcode 81 /0 id */
7087 ins_encode(REX_mem_wide(dst),
7088 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7089 ins_pipe(ialu_mem_imm);
7090 %}
7091
7092 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7093 %{
7094 predicate(UseIncDec);
7095 match(Set dst (AddL dst src));
7096 effect(KILL cr);
7097
7098 format %{ "incq $dst\t# long" %}
7099 opcode(0xFF, 0x00); // FF /0
7100 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7101 ins_pipe(ialu_reg);
7102 %}
7103
7104 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7105 %{
7106 predicate(UseIncDec);
7107 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7108 effect(KILL cr);
7109
7110 ins_cost(125); // XXX
7111 format %{ "incq $dst\t# long" %}
7112 opcode(0xFF); /* Opcode FF /0 */
7113 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7114 ins_pipe(ialu_mem_imm);
7115 %}
7116
7117 // XXX why does that use AddL
7118 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7119 %{
7120 predicate(UseIncDec);
7121 match(Set dst (AddL dst src));
7122 effect(KILL cr);
7123
7124 format %{ "decq $dst\t# long" %}
7125 opcode(0xFF, 0x01); // FF /1
7126 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7127 ins_pipe(ialu_reg);
7128 %}
7129
7130 // XXX why does that use AddL
7131 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7132 %{
7133 predicate(UseIncDec);
7134 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7135 effect(KILL cr);
7136
7137 ins_cost(125); // XXX
7138 format %{ "decq $dst\t# long" %}
7139 opcode(0xFF); /* Opcode FF /1 */
7140 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7141 ins_pipe(ialu_mem_imm);
7142 %}
7143
7144 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7145 %{
7146 match(Set dst (AddL src0 src1));
7147
7148 ins_cost(110);
7149 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7150 opcode(0x8D); /* 0x8D /r */
7151 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7152 ins_pipe(ialu_reg_reg);
7153 %}
7154
7155 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7156 %{
7157 match(Set dst (AddP dst src));
7158 effect(KILL cr);
7159
7160 format %{ "addq $dst, $src\t# ptr" %}
7161 opcode(0x03);
7162 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7163 ins_pipe(ialu_reg_reg);
7164 %}
7165
7166 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7167 %{
7168 match(Set dst (AddP dst src));
7169 effect(KILL cr);
7170
7171 format %{ "addq $dst, $src\t# ptr" %}
7172 opcode(0x81, 0x00); /* /0 id */
7173 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7174 ins_pipe( ialu_reg );
7175 %}
7176
7177 // XXX addP mem ops ????
7178
7179 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7180 %{
7181 match(Set dst (AddP src0 src1));
7182
7183 ins_cost(110);
7184 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7185 opcode(0x8D); /* 0x8D /r */
7186 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7187 ins_pipe(ialu_reg_reg);
7188 %}
7189
7190 instruct checkCastPP(rRegP dst)
7191 %{
7192 match(Set dst (CheckCastPP dst));
7193
7194 size(0);
7195 format %{ "# checkcastPP of $dst" %}
7196 ins_encode(/* empty encoding */);
7197 ins_pipe(empty);
7198 %}
7199
7200 instruct castPP(rRegP dst)
7201 %{
7202 match(Set dst (CastPP dst));
7203
7204 size(0);
7205 format %{ "# castPP of $dst" %}
7206 ins_encode(/* empty encoding */);
7207 ins_pipe(empty);
7208 %}
7209
7210 instruct castII(rRegI dst)
7211 %{
7212 match(Set dst (CastII dst));
7213
7214 size(0);
7215 format %{ "# castII of $dst" %}
7216 ins_encode(/* empty encoding */);
7217 ins_cost(0);
7218 ins_pipe(empty);
7219 %}
7220
7221 // LoadP-locked same as a regular LoadP when used with compare-swap
7222 instruct loadPLocked(rRegP dst, memory mem)
7223 %{
7224 match(Set dst (LoadPLocked mem));
7225
7226 ins_cost(125); // XXX
7227 format %{ "movq $dst, $mem\t# ptr locked" %}
7228 opcode(0x8B);
7229 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7230 ins_pipe(ialu_reg_mem); // XXX
7231 %}
7232
7233 // Conditional-store of the updated heap-top.
7234 // Used during allocation of the shared heap.
7235 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7236
7237 instruct storePConditional(memory heap_top_ptr,
7238 rax_RegP oldval, rRegP newval,
7239 rFlagsReg cr)
7240 %{
7241 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7242
7243 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7244 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7245 opcode(0x0F, 0xB1);
7246 ins_encode(lock_prefix,
7247 REX_reg_mem_wide(newval, heap_top_ptr),
7248 OpcP, OpcS,
7249 reg_mem(newval, heap_top_ptr));
7250 ins_pipe(pipe_cmpxchg);
7251 %}
7252
7253 // Conditional-store of an int value.
7254 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7255 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7256 %{
7257 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7258 effect(KILL oldval);
7259
7260 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7261 opcode(0x0F, 0xB1);
7262 ins_encode(lock_prefix,
7263 REX_reg_mem(newval, mem),
7264 OpcP, OpcS,
7265 reg_mem(newval, mem));
7266 ins_pipe(pipe_cmpxchg);
7267 %}
7268
7269 // Conditional-store of a long value.
7270 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7271 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7272 %{
7273 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7274 effect(KILL oldval);
7275
7276 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7277 opcode(0x0F, 0xB1);
7278 ins_encode(lock_prefix,
7279 REX_reg_mem_wide(newval, mem),
7280 OpcP, OpcS,
7281 reg_mem(newval, mem));
7282 ins_pipe(pipe_cmpxchg);
7283 %}
7284
7285
7286 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7287 instruct compareAndSwapP(rRegI res,
7288 memory mem_ptr,
7289 rax_RegP oldval, rRegP newval,
7290 rFlagsReg cr)
7291 %{
7292 predicate(VM_Version::supports_cx8());
7293 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7294 effect(KILL cr, KILL oldval);
7295
7296 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7297 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7298 "sete $res\n\t"
7299 "movzbl $res, $res" %}
7300 opcode(0x0F, 0xB1);
7301 ins_encode(lock_prefix,
7302 REX_reg_mem_wide(newval, mem_ptr),
7303 OpcP, OpcS,
7304 reg_mem(newval, mem_ptr),
7305 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7306 REX_reg_breg(res, res), // movzbl
7307 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7308 ins_pipe( pipe_cmpxchg );
7309 %}
7310
7311 instruct compareAndSwapL(rRegI res,
7312 memory mem_ptr,
7313 rax_RegL oldval, rRegL newval,
7314 rFlagsReg cr)
7315 %{
7316 predicate(VM_Version::supports_cx8());
7317 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7318 effect(KILL cr, KILL oldval);
7319
7320 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7321 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7322 "sete $res\n\t"
7323 "movzbl $res, $res" %}
7324 opcode(0x0F, 0xB1);
7325 ins_encode(lock_prefix,
7326 REX_reg_mem_wide(newval, mem_ptr),
7327 OpcP, OpcS,
7328 reg_mem(newval, mem_ptr),
7329 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7330 REX_reg_breg(res, res), // movzbl
7331 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7332 ins_pipe( pipe_cmpxchg );
7333 %}
7334
7335 instruct compareAndSwapI(rRegI res,
7336 memory mem_ptr,
7337 rax_RegI oldval, rRegI newval,
7338 rFlagsReg cr)
7339 %{
7340 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7341 effect(KILL cr, KILL oldval);
7342
7343 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7344 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7345 "sete $res\n\t"
7346 "movzbl $res, $res" %}
7347 opcode(0x0F, 0xB1);
7348 ins_encode(lock_prefix,
7349 REX_reg_mem(newval, mem_ptr),
7350 OpcP, OpcS,
7351 reg_mem(newval, mem_ptr),
7352 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7353 REX_reg_breg(res, res), // movzbl
7354 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7355 ins_pipe( pipe_cmpxchg );
7356 %}
7357
7358
7359 instruct compareAndSwapN(rRegI res,
7360 memory mem_ptr,
7361 rax_RegN oldval, rRegN newval,
7362 rFlagsReg cr) %{
7363 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7364 effect(KILL cr, KILL oldval);
7365
7366 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7367 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7368 "sete $res\n\t"
7369 "movzbl $res, $res" %}
7370 opcode(0x0F, 0xB1);
7371 ins_encode(lock_prefix,
7372 REX_reg_mem(newval, mem_ptr),
7373 OpcP, OpcS,
7374 reg_mem(newval, mem_ptr),
7375 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7376 REX_reg_breg(res, res), // movzbl
7377 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7378 ins_pipe( pipe_cmpxchg );
7379 %}
7380
7381 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7382 predicate(n->as_LoadStore()->result_not_used());
7383 match(Set dummy (GetAndAddI mem add));
7384 effect(KILL cr);
7385 format %{ "ADDL [$mem],$add" %}
7386 ins_encode %{
7387 if (os::is_MP()) { __ lock(); }
7388 __ addl($mem$$Address, $add$$constant);
7389 %}
7390 ins_pipe( pipe_cmpxchg );
7391 %}
7392
7393 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7394 match(Set newval (GetAndAddI mem newval));
7395 effect(KILL cr);
7396 format %{ "XADDL [$mem],$newval" %}
7397 ins_encode %{
7398 if (os::is_MP()) { __ lock(); }
7399 __ xaddl($mem$$Address, $newval$$Register);
7400 %}
7401 ins_pipe( pipe_cmpxchg );
7402 %}
7403
7404 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7405 predicate(n->as_LoadStore()->result_not_used());
7406 match(Set dummy (GetAndAddL mem add));
7407 effect(KILL cr);
7408 format %{ "ADDQ [$mem],$add" %}
7409 ins_encode %{
7410 if (os::is_MP()) { __ lock(); }
7411 __ addq($mem$$Address, $add$$constant);
7412 %}
7413 ins_pipe( pipe_cmpxchg );
7414 %}
7415
7416 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7417 match(Set newval (GetAndAddL mem newval));
7418 effect(KILL cr);
7419 format %{ "XADDQ [$mem],$newval" %}
7420 ins_encode %{
7421 if (os::is_MP()) { __ lock(); }
7422 __ xaddq($mem$$Address, $newval$$Register);
7423 %}
7424 ins_pipe( pipe_cmpxchg );
7425 %}
7426
7427 instruct xchgI( memory mem, rRegI newval) %{
7428 match(Set newval (GetAndSetI mem newval));
7429 format %{ "XCHGL $newval,[$mem]" %}
7430 ins_encode %{
7431 __ xchgl($newval$$Register, $mem$$Address);
7432 %}
7433 ins_pipe( pipe_cmpxchg );
7434 %}
7435
7436 instruct xchgL( memory mem, rRegL newval) %{
7437 match(Set newval (GetAndSetL mem newval));
7438 format %{ "XCHGL $newval,[$mem]" %}
7439 ins_encode %{
7440 __ xchgq($newval$$Register, $mem$$Address);
7441 %}
7442 ins_pipe( pipe_cmpxchg );
7443 %}
7444
7445 instruct xchgP( memory mem, rRegP newval) %{
7446 match(Set newval (GetAndSetP mem newval));
7447 format %{ "XCHGQ $newval,[$mem]" %}
7448 ins_encode %{
7449 __ xchgq($newval$$Register, $mem$$Address);
7450 %}
7451 ins_pipe( pipe_cmpxchg );
7452 %}
7453
7454 instruct xchgN( memory mem, rRegN newval) %{
7455 match(Set newval (GetAndSetN mem newval));
7456 format %{ "XCHGL $newval,$mem]" %}
7457 ins_encode %{
7458 __ xchgl($newval$$Register, $mem$$Address);
7459 %}
7460 ins_pipe( pipe_cmpxchg );
7461 %}
7462
7463 //----------Subtraction Instructions-------------------------------------------
7464
7465 // Integer Subtraction Instructions
7466 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7467 %{
7468 match(Set dst (SubI dst src));
7469 effect(KILL cr);
7470
7471 format %{ "subl $dst, $src\t# int" %}
7472 opcode(0x2B);
7473 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7474 ins_pipe(ialu_reg_reg);
7475 %}
7476
7477 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7478 %{
7479 match(Set dst (SubI dst src));
7480 effect(KILL cr);
7481
7482 format %{ "subl $dst, $src\t# int" %}
7483 opcode(0x81, 0x05); /* Opcode 81 /5 */
7484 ins_encode(OpcSErm(dst, src), Con8or32(src));
7485 ins_pipe(ialu_reg);
7486 %}
7487
7488 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7489 %{
7490 match(Set dst (SubI dst (LoadI src)));
7491 effect(KILL cr);
7492
7493 ins_cost(125);
7494 format %{ "subl $dst, $src\t# int" %}
7495 opcode(0x2B);
7496 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7497 ins_pipe(ialu_reg_mem);
7498 %}
7499
7500 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7501 %{
7502 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7503 effect(KILL cr);
7504
7505 ins_cost(150);
7506 format %{ "subl $dst, $src\t# int" %}
7507 opcode(0x29); /* Opcode 29 /r */
7508 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7509 ins_pipe(ialu_mem_reg);
7510 %}
7511
7512 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7513 %{
7514 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7515 effect(KILL cr);
7516
7517 ins_cost(125); // XXX
7518 format %{ "subl $dst, $src\t# int" %}
7519 opcode(0x81); /* Opcode 81 /5 id */
7520 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7521 ins_pipe(ialu_mem_imm);
7522 %}
7523
7524 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7525 %{
7526 match(Set dst (SubL dst src));
7527 effect(KILL cr);
7528
7529 format %{ "subq $dst, $src\t# long" %}
7530 opcode(0x2B);
7531 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7532 ins_pipe(ialu_reg_reg);
7533 %}
7534
7535 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7536 %{
7537 match(Set dst (SubL dst src));
7538 effect(KILL cr);
7539
7540 format %{ "subq $dst, $src\t# long" %}
7541 opcode(0x81, 0x05); /* Opcode 81 /5 */
7542 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7543 ins_pipe(ialu_reg);
7544 %}
7545
7546 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7547 %{
7548 match(Set dst (SubL dst (LoadL src)));
7549 effect(KILL cr);
7550
7551 ins_cost(125);
7552 format %{ "subq $dst, $src\t# long" %}
7553 opcode(0x2B);
7554 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7555 ins_pipe(ialu_reg_mem);
7556 %}
7557
7558 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7559 %{
7560 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7561 effect(KILL cr);
7562
7563 ins_cost(150);
7564 format %{ "subq $dst, $src\t# long" %}
7565 opcode(0x29); /* Opcode 29 /r */
7566 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7567 ins_pipe(ialu_mem_reg);
7568 %}
7569
7570 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7571 %{
7572 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7573 effect(KILL cr);
7574
7575 ins_cost(125); // XXX
7576 format %{ "subq $dst, $src\t# long" %}
7577 opcode(0x81); /* Opcode 81 /5 id */
7578 ins_encode(REX_mem_wide(dst),
7579 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7580 ins_pipe(ialu_mem_imm);
7581 %}
7582
7583 // Subtract from a pointer
7584 // XXX hmpf???
7585 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7586 %{
7587 match(Set dst (AddP dst (SubI zero src)));
7588 effect(KILL cr);
7589
7590 format %{ "subq $dst, $src\t# ptr - int" %}
7591 opcode(0x2B);
7592 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7593 ins_pipe(ialu_reg_reg);
7594 %}
7595
7596 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7597 %{
7598 match(Set dst (SubI zero dst));
7599 effect(KILL cr);
7600
7601 format %{ "negl $dst\t# int" %}
7602 opcode(0xF7, 0x03); // Opcode F7 /3
7603 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7604 ins_pipe(ialu_reg);
7605 %}
7606
7607 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7608 %{
7609 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7610 effect(KILL cr);
7611
7612 format %{ "negl $dst\t# int" %}
7613 opcode(0xF7, 0x03); // Opcode F7 /3
7614 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7615 ins_pipe(ialu_reg);
7616 %}
7617
7618 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7619 %{
7620 match(Set dst (SubL zero dst));
7621 effect(KILL cr);
7622
7623 format %{ "negq $dst\t# long" %}
7624 opcode(0xF7, 0x03); // Opcode F7 /3
7625 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7626 ins_pipe(ialu_reg);
7627 %}
7628
7629 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7630 %{
7631 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7632 effect(KILL cr);
7633
7634 format %{ "negq $dst\t# long" %}
7635 opcode(0xF7, 0x03); // Opcode F7 /3
7636 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7637 ins_pipe(ialu_reg);
7638 %}
7639
7640 //----------Multiplication/Division Instructions-------------------------------
7641 // Integer Multiplication Instructions
7642 // Multiply Register
7643
7644 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7645 %{
7646 match(Set dst (MulI dst src));
7647 effect(KILL cr);
7648
7649 ins_cost(300);
7650 format %{ "imull $dst, $src\t# int" %}
7651 opcode(0x0F, 0xAF);
7652 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7653 ins_pipe(ialu_reg_reg_alu0);
7654 %}
7655
7656 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7657 %{
7658 match(Set dst (MulI src imm));
7659 effect(KILL cr);
7660
7661 ins_cost(300);
7662 format %{ "imull $dst, $src, $imm\t# int" %}
7663 opcode(0x69); /* 69 /r id */
7664 ins_encode(REX_reg_reg(dst, src),
7665 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7666 ins_pipe(ialu_reg_reg_alu0);
7667 %}
7668
7669 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7670 %{
7671 match(Set dst (MulI dst (LoadI src)));
7672 effect(KILL cr);
7673
7674 ins_cost(350);
7675 format %{ "imull $dst, $src\t# int" %}
7676 opcode(0x0F, 0xAF);
7677 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7678 ins_pipe(ialu_reg_mem_alu0);
7679 %}
7680
7681 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7682 %{
7683 match(Set dst (MulI (LoadI src) imm));
7684 effect(KILL cr);
7685
7686 ins_cost(300);
7687 format %{ "imull $dst, $src, $imm\t# int" %}
7688 opcode(0x69); /* 69 /r id */
7689 ins_encode(REX_reg_mem(dst, src),
7690 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7691 ins_pipe(ialu_reg_mem_alu0);
7692 %}
7693
7694 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7695 %{
7696 match(Set dst (MulL dst src));
7697 effect(KILL cr);
7698
7699 ins_cost(300);
7700 format %{ "imulq $dst, $src\t# long" %}
7701 opcode(0x0F, 0xAF);
7702 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7703 ins_pipe(ialu_reg_reg_alu0);
7704 %}
7705
7706 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7707 %{
7708 match(Set dst (MulL src imm));
7709 effect(KILL cr);
7710
7711 ins_cost(300);
7712 format %{ "imulq $dst, $src, $imm\t# long" %}
7713 opcode(0x69); /* 69 /r id */
7714 ins_encode(REX_reg_reg_wide(dst, src),
7715 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7716 ins_pipe(ialu_reg_reg_alu0);
7717 %}
7718
7719 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7720 %{
7721 match(Set dst (MulL dst (LoadL src)));
7722 effect(KILL cr);
7723
7724 ins_cost(350);
7725 format %{ "imulq $dst, $src\t# long" %}
7726 opcode(0x0F, 0xAF);
7727 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7728 ins_pipe(ialu_reg_mem_alu0);
7729 %}
7730
7731 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7732 %{
7733 match(Set dst (MulL (LoadL src) imm));
7734 effect(KILL cr);
7735
7736 ins_cost(300);
7737 format %{ "imulq $dst, $src, $imm\t# long" %}
7738 opcode(0x69); /* 69 /r id */
7739 ins_encode(REX_reg_mem_wide(dst, src),
7740 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7741 ins_pipe(ialu_reg_mem_alu0);
7742 %}
7743
7744 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7745 %{
7746 match(Set dst (MulHiL src rax));
7747 effect(USE_KILL rax, KILL cr);
7748
7749 ins_cost(300);
7750 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7751 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7752 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7753 ins_pipe(ialu_reg_reg_alu0);
7754 %}
7755
7756 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7757 rFlagsReg cr)
7758 %{
7759 match(Set rax (DivI rax div));
7760 effect(KILL rdx, KILL cr);
7761
7762 ins_cost(30*100+10*100); // XXX
7763 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7764 "jne,s normal\n\t"
7765 "xorl rdx, rdx\n\t"
7766 "cmpl $div, -1\n\t"
7767 "je,s done\n"
7768 "normal: cdql\n\t"
7769 "idivl $div\n"
7770 "done:" %}
7771 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7772 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7773 ins_pipe(ialu_reg_reg_alu0);
7774 %}
7775
7776 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7777 rFlagsReg cr)
7778 %{
7779 match(Set rax (DivL rax div));
7780 effect(KILL rdx, KILL cr);
7781
7782 ins_cost(30*100+10*100); // XXX
7783 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7784 "cmpq rax, rdx\n\t"
7785 "jne,s normal\n\t"
7786 "xorl rdx, rdx\n\t"
7787 "cmpq $div, -1\n\t"
7788 "je,s done\n"
7789 "normal: cdqq\n\t"
7790 "idivq $div\n"
7791 "done:" %}
7792 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7793 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7794 ins_pipe(ialu_reg_reg_alu0);
7795 %}
7796
7797 // Integer DIVMOD with Register, both quotient and mod results
7798 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7799 rFlagsReg cr)
7800 %{
7801 match(DivModI rax div);
7802 effect(KILL cr);
7803
7804 ins_cost(30*100+10*100); // XXX
7805 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7806 "jne,s normal\n\t"
7807 "xorl rdx, rdx\n\t"
7808 "cmpl $div, -1\n\t"
7809 "je,s done\n"
7810 "normal: cdql\n\t"
7811 "idivl $div\n"
7812 "done:" %}
7813 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7814 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7815 ins_pipe(pipe_slow);
7816 %}
7817
7818 // Long DIVMOD with Register, both quotient and mod results
7819 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7820 rFlagsReg cr)
7821 %{
7822 match(DivModL rax div);
7823 effect(KILL cr);
7824
7825 ins_cost(30*100+10*100); // XXX
7826 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7827 "cmpq rax, rdx\n\t"
7828 "jne,s normal\n\t"
7829 "xorl rdx, rdx\n\t"
7830 "cmpq $div, -1\n\t"
7831 "je,s done\n"
7832 "normal: cdqq\n\t"
7833 "idivq $div\n"
7834 "done:" %}
7835 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7836 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7837 ins_pipe(pipe_slow);
7838 %}
7839
7840 //----------- DivL-By-Constant-Expansions--------------------------------------
7841 // DivI cases are handled by the compiler
7842
7843 // Magic constant, reciprocal of 10
7844 instruct loadConL_0x6666666666666667(rRegL dst)
7845 %{
7846 effect(DEF dst);
7847
7848 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7849 ins_encode(load_immL(dst, 0x6666666666666667));
7850 ins_pipe(ialu_reg);
7851 %}
7852
7853 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7854 %{
7855 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7856
7857 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7858 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7859 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7860 ins_pipe(ialu_reg_reg_alu0);
7861 %}
7862
7863 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7864 %{
7865 effect(USE_DEF dst, KILL cr);
7866
7867 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7868 opcode(0xC1, 0x7); /* C1 /7 ib */
7869 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7870 ins_pipe(ialu_reg);
7871 %}
7872
7873 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7874 %{
7875 effect(USE_DEF dst, KILL cr);
7876
7877 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7878 opcode(0xC1, 0x7); /* C1 /7 ib */
7879 ins_encode(reg_opc_imm_wide(dst, 0x2));
7880 ins_pipe(ialu_reg);
7881 %}
7882
7883 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7884 %{
7885 match(Set dst (DivL src div));
7886
7887 ins_cost((5+8)*100);
7888 expand %{
7889 rax_RegL rax; // Killed temp
7890 rFlagsReg cr; // Killed
7891 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7892 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7893 sarL_rReg_63(src, cr); // sarq src, 63
7894 sarL_rReg_2(dst, cr); // sarq rdx, 2
7895 subL_rReg(dst, src, cr); // subl rdx, src
7896 %}
7897 %}
7898
7899 //-----------------------------------------------------------------------------
7900
7901 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7902 rFlagsReg cr)
7903 %{
7904 match(Set rdx (ModI rax div));
7905 effect(KILL rax, KILL cr);
7906
7907 ins_cost(300); // XXX
7908 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7909 "jne,s normal\n\t"
7910 "xorl rdx, rdx\n\t"
7911 "cmpl $div, -1\n\t"
7912 "je,s done\n"
7913 "normal: cdql\n\t"
7914 "idivl $div\n"
7915 "done:" %}
7916 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7917 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7918 ins_pipe(ialu_reg_reg_alu0);
7919 %}
7920
7921 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7922 rFlagsReg cr)
7923 %{
7924 match(Set rdx (ModL rax div));
7925 effect(KILL rax, KILL cr);
7926
7927 ins_cost(300); // XXX
7928 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7929 "cmpq rax, rdx\n\t"
7930 "jne,s normal\n\t"
7931 "xorl rdx, rdx\n\t"
7932 "cmpq $div, -1\n\t"
7933 "je,s done\n"
7934 "normal: cdqq\n\t"
7935 "idivq $div\n"
7936 "done:" %}
7937 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7938 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7939 ins_pipe(ialu_reg_reg_alu0);
7940 %}
7941
7942 // Integer Shift Instructions
7943 // Shift Left by one
7944 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7945 %{
7946 match(Set dst (LShiftI dst shift));
7947 effect(KILL cr);
7948
7949 format %{ "sall $dst, $shift" %}
7950 opcode(0xD1, 0x4); /* D1 /4 */
7951 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7952 ins_pipe(ialu_reg);
7953 %}
7954
7955 // Shift Left by one
7956 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7957 %{
7958 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7959 effect(KILL cr);
7960
7961 format %{ "sall $dst, $shift\t" %}
7962 opcode(0xD1, 0x4); /* D1 /4 */
7963 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7964 ins_pipe(ialu_mem_imm);
7965 %}
7966
7967 // Shift Left by 8-bit immediate
7968 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7969 %{
7970 match(Set dst (LShiftI dst shift));
7971 effect(KILL cr);
7972
7973 format %{ "sall $dst, $shift" %}
7974 opcode(0xC1, 0x4); /* C1 /4 ib */
7975 ins_encode(reg_opc_imm(dst, shift));
7976 ins_pipe(ialu_reg);
7977 %}
7978
7979 // Shift Left by 8-bit immediate
7980 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7981 %{
7982 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7983 effect(KILL cr);
7984
7985 format %{ "sall $dst, $shift" %}
7986 opcode(0xC1, 0x4); /* C1 /4 ib */
7987 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7988 ins_pipe(ialu_mem_imm);
7989 %}
7990
7991 // Shift Left by variable
7992 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7993 %{
7994 match(Set dst (LShiftI dst shift));
7995 effect(KILL cr);
7996
7997 format %{ "sall $dst, $shift" %}
7998 opcode(0xD3, 0x4); /* D3 /4 */
7999 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8000 ins_pipe(ialu_reg_reg);
8001 %}
8002
8003 // Shift Left by variable
8004 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8005 %{
8006 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8007 effect(KILL cr);
8008
8009 format %{ "sall $dst, $shift" %}
8010 opcode(0xD3, 0x4); /* D3 /4 */
8011 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8012 ins_pipe(ialu_mem_reg);
8013 %}
8014
8015 // Arithmetic shift right by one
8016 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8017 %{
8018 match(Set dst (RShiftI dst shift));
8019 effect(KILL cr);
8020
8021 format %{ "sarl $dst, $shift" %}
8022 opcode(0xD1, 0x7); /* D1 /7 */
8023 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8024 ins_pipe(ialu_reg);
8025 %}
8026
8027 // Arithmetic shift right by one
8028 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8029 %{
8030 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8031 effect(KILL cr);
8032
8033 format %{ "sarl $dst, $shift" %}
8034 opcode(0xD1, 0x7); /* D1 /7 */
8035 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8036 ins_pipe(ialu_mem_imm);
8037 %}
8038
8039 // Arithmetic Shift Right by 8-bit immediate
8040 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8041 %{
8042 match(Set dst (RShiftI dst shift));
8043 effect(KILL cr);
8044
8045 format %{ "sarl $dst, $shift" %}
8046 opcode(0xC1, 0x7); /* C1 /7 ib */
8047 ins_encode(reg_opc_imm(dst, shift));
8048 ins_pipe(ialu_mem_imm);
8049 %}
8050
8051 // Arithmetic Shift Right by 8-bit immediate
8052 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8053 %{
8054 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8055 effect(KILL cr);
8056
8057 format %{ "sarl $dst, $shift" %}
8058 opcode(0xC1, 0x7); /* C1 /7 ib */
8059 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8060 ins_pipe(ialu_mem_imm);
8061 %}
8062
8063 // Arithmetic Shift Right by variable
8064 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8065 %{
8066 match(Set dst (RShiftI dst shift));
8067 effect(KILL cr);
8068
8069 format %{ "sarl $dst, $shift" %}
8070 opcode(0xD3, 0x7); /* D3 /7 */
8071 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8072 ins_pipe(ialu_reg_reg);
8073 %}
8074
8075 // Arithmetic Shift Right by variable
8076 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8077 %{
8078 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8079 effect(KILL cr);
8080
8081 format %{ "sarl $dst, $shift" %}
8082 opcode(0xD3, 0x7); /* D3 /7 */
8083 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8084 ins_pipe(ialu_mem_reg);
8085 %}
8086
8087 // Logical shift right by one
8088 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8089 %{
8090 match(Set dst (URShiftI dst shift));
8091 effect(KILL cr);
8092
8093 format %{ "shrl $dst, $shift" %}
8094 opcode(0xD1, 0x5); /* D1 /5 */
8095 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8096 ins_pipe(ialu_reg);
8097 %}
8098
8099 // Logical shift right by one
8100 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8101 %{
8102 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8103 effect(KILL cr);
8104
8105 format %{ "shrl $dst, $shift" %}
8106 opcode(0xD1, 0x5); /* D1 /5 */
8107 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8108 ins_pipe(ialu_mem_imm);
8109 %}
8110
8111 // Logical Shift Right by 8-bit immediate
8112 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8113 %{
8114 match(Set dst (URShiftI dst shift));
8115 effect(KILL cr);
8116
8117 format %{ "shrl $dst, $shift" %}
8118 opcode(0xC1, 0x5); /* C1 /5 ib */
8119 ins_encode(reg_opc_imm(dst, shift));
8120 ins_pipe(ialu_reg);
8121 %}
8122
8123 // Logical Shift Right by 8-bit immediate
8124 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8125 %{
8126 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8127 effect(KILL cr);
8128
8129 format %{ "shrl $dst, $shift" %}
8130 opcode(0xC1, 0x5); /* C1 /5 ib */
8131 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8132 ins_pipe(ialu_mem_imm);
8133 %}
8134
8135 // Logical Shift Right by variable
8136 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8137 %{
8138 match(Set dst (URShiftI dst shift));
8139 effect(KILL cr);
8140
8141 format %{ "shrl $dst, $shift" %}
8142 opcode(0xD3, 0x5); /* D3 /5 */
8143 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8144 ins_pipe(ialu_reg_reg);
8145 %}
8146
8147 // Logical Shift Right by variable
8148 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8149 %{
8150 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8151 effect(KILL cr);
8152
8153 format %{ "shrl $dst, $shift" %}
8154 opcode(0xD3, 0x5); /* D3 /5 */
8155 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8156 ins_pipe(ialu_mem_reg);
8157 %}
8158
8159 // Long Shift Instructions
8160 // Shift Left by one
8161 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8162 %{
8163 match(Set dst (LShiftL dst shift));
8164 effect(KILL cr);
8165
8166 format %{ "salq $dst, $shift" %}
8167 opcode(0xD1, 0x4); /* D1 /4 */
8168 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8169 ins_pipe(ialu_reg);
8170 %}
8171
8172 // Shift Left by one
8173 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8174 %{
8175 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8176 effect(KILL cr);
8177
8178 format %{ "salq $dst, $shift" %}
8179 opcode(0xD1, 0x4); /* D1 /4 */
8180 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8181 ins_pipe(ialu_mem_imm);
8182 %}
8183
8184 // Shift Left by 8-bit immediate
8185 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8186 %{
8187 match(Set dst (LShiftL dst shift));
8188 effect(KILL cr);
8189
8190 format %{ "salq $dst, $shift" %}
8191 opcode(0xC1, 0x4); /* C1 /4 ib */
8192 ins_encode(reg_opc_imm_wide(dst, shift));
8193 ins_pipe(ialu_reg);
8194 %}
8195
8196 // Shift Left by 8-bit immediate
8197 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8198 %{
8199 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8200 effect(KILL cr);
8201
8202 format %{ "salq $dst, $shift" %}
8203 opcode(0xC1, 0x4); /* C1 /4 ib */
8204 ins_encode(REX_mem_wide(dst), OpcP,
8205 RM_opc_mem(secondary, dst), Con8or32(shift));
8206 ins_pipe(ialu_mem_imm);
8207 %}
8208
8209 // Shift Left by variable
8210 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8211 %{
8212 match(Set dst (LShiftL dst shift));
8213 effect(KILL cr);
8214
8215 format %{ "salq $dst, $shift" %}
8216 opcode(0xD3, 0x4); /* D3 /4 */
8217 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8218 ins_pipe(ialu_reg_reg);
8219 %}
8220
8221 // Shift Left by variable
8222 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8223 %{
8224 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8225 effect(KILL cr);
8226
8227 format %{ "salq $dst, $shift" %}
8228 opcode(0xD3, 0x4); /* D3 /4 */
8229 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8230 ins_pipe(ialu_mem_reg);
8231 %}
8232
8233 // Arithmetic shift right by one
8234 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8235 %{
8236 match(Set dst (RShiftL dst shift));
8237 effect(KILL cr);
8238
8239 format %{ "sarq $dst, $shift" %}
8240 opcode(0xD1, 0x7); /* D1 /7 */
8241 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8242 ins_pipe(ialu_reg);
8243 %}
8244
8245 // Arithmetic shift right by one
8246 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8247 %{
8248 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8249 effect(KILL cr);
8250
8251 format %{ "sarq $dst, $shift" %}
8252 opcode(0xD1, 0x7); /* D1 /7 */
8253 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8254 ins_pipe(ialu_mem_imm);
8255 %}
8256
8257 // Arithmetic Shift Right by 8-bit immediate
8258 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8259 %{
8260 match(Set dst (RShiftL dst shift));
8261 effect(KILL cr);
8262
8263 format %{ "sarq $dst, $shift" %}
8264 opcode(0xC1, 0x7); /* C1 /7 ib */
8265 ins_encode(reg_opc_imm_wide(dst, shift));
8266 ins_pipe(ialu_mem_imm);
8267 %}
8268
8269 // Arithmetic Shift Right by 8-bit immediate
8270 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8271 %{
8272 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8273 effect(KILL cr);
8274
8275 format %{ "sarq $dst, $shift" %}
8276 opcode(0xC1, 0x7); /* C1 /7 ib */
8277 ins_encode(REX_mem_wide(dst), OpcP,
8278 RM_opc_mem(secondary, dst), Con8or32(shift));
8279 ins_pipe(ialu_mem_imm);
8280 %}
8281
8282 // Arithmetic Shift Right by variable
8283 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8284 %{
8285 match(Set dst (RShiftL dst shift));
8286 effect(KILL cr);
8287
8288 format %{ "sarq $dst, $shift" %}
8289 opcode(0xD3, 0x7); /* D3 /7 */
8290 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8291 ins_pipe(ialu_reg_reg);
8292 %}
8293
8294 // Arithmetic Shift Right by variable
8295 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8296 %{
8297 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8298 effect(KILL cr);
8299
8300 format %{ "sarq $dst, $shift" %}
8301 opcode(0xD3, 0x7); /* D3 /7 */
8302 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8303 ins_pipe(ialu_mem_reg);
8304 %}
8305
8306 // Logical shift right by one
8307 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8308 %{
8309 match(Set dst (URShiftL dst shift));
8310 effect(KILL cr);
8311
8312 format %{ "shrq $dst, $shift" %}
8313 opcode(0xD1, 0x5); /* D1 /5 */
8314 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8315 ins_pipe(ialu_reg);
8316 %}
8317
8318 // Logical shift right by one
8319 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8320 %{
8321 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8322 effect(KILL cr);
8323
8324 format %{ "shrq $dst, $shift" %}
8325 opcode(0xD1, 0x5); /* D1 /5 */
8326 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8327 ins_pipe(ialu_mem_imm);
8328 %}
8329
8330 // Logical Shift Right by 8-bit immediate
8331 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8332 %{
8333 match(Set dst (URShiftL dst shift));
8334 effect(KILL cr);
8335
8336 format %{ "shrq $dst, $shift" %}
8337 opcode(0xC1, 0x5); /* C1 /5 ib */
8338 ins_encode(reg_opc_imm_wide(dst, shift));
8339 ins_pipe(ialu_reg);
8340 %}
8341
8342
8343 // Logical Shift Right by 8-bit immediate
8344 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8345 %{
8346 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8347 effect(KILL cr);
8348
8349 format %{ "shrq $dst, $shift" %}
8350 opcode(0xC1, 0x5); /* C1 /5 ib */
8351 ins_encode(REX_mem_wide(dst), OpcP,
8352 RM_opc_mem(secondary, dst), Con8or32(shift));
8353 ins_pipe(ialu_mem_imm);
8354 %}
8355
8356 // Logical Shift Right by variable
8357 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8358 %{
8359 match(Set dst (URShiftL dst shift));
8360 effect(KILL cr);
8361
8362 format %{ "shrq $dst, $shift" %}
8363 opcode(0xD3, 0x5); /* D3 /5 */
8364 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8365 ins_pipe(ialu_reg_reg);
8366 %}
8367
8368 // Logical Shift Right by variable
8369 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8370 %{
8371 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8372 effect(KILL cr);
8373
8374 format %{ "shrq $dst, $shift" %}
8375 opcode(0xD3, 0x5); /* D3 /5 */
8376 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8377 ins_pipe(ialu_mem_reg);
8378 %}
8379
8380 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8381 // This idiom is used by the compiler for the i2b bytecode.
8382 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8383 %{
8384 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8385
8386 format %{ "movsbl $dst, $src\t# i2b" %}
8387 opcode(0x0F, 0xBE);
8388 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8389 ins_pipe(ialu_reg_reg);
8390 %}
8391
8392 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8393 // This idiom is used by the compiler the i2s bytecode.
8394 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8395 %{
8396 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8397
8398 format %{ "movswl $dst, $src\t# i2s" %}
8399 opcode(0x0F, 0xBF);
8400 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8401 ins_pipe(ialu_reg_reg);
8402 %}
8403
8404 // ROL/ROR instructions
8405
8406 // ROL expand
8407 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8408 effect(KILL cr, USE_DEF dst);
8409
8410 format %{ "roll $dst" %}
8411 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8412 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8413 ins_pipe(ialu_reg);
8414 %}
8415
8416 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8417 effect(USE_DEF dst, USE shift, KILL cr);
8418
8419 format %{ "roll $dst, $shift" %}
8420 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8421 ins_encode( reg_opc_imm(dst, shift) );
8422 ins_pipe(ialu_reg);
8423 %}
8424
8425 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8426 %{
8427 effect(USE_DEF dst, USE shift, KILL cr);
8428
8429 format %{ "roll $dst, $shift" %}
8430 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8431 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8432 ins_pipe(ialu_reg_reg);
8433 %}
8434 // end of ROL expand
8435
8436 // Rotate Left by one
8437 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8438 %{
8439 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8440
8441 expand %{
8442 rolI_rReg_imm1(dst, cr);
8443 %}
8444 %}
8445
8446 // Rotate Left by 8-bit immediate
8447 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8448 %{
8449 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8450 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8451
8452 expand %{
8453 rolI_rReg_imm8(dst, lshift, cr);
8454 %}
8455 %}
8456
8457 // Rotate Left by variable
8458 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8459 %{
8460 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8461
8462 expand %{
8463 rolI_rReg_CL(dst, shift, cr);
8464 %}
8465 %}
8466
8467 // Rotate Left by variable
8468 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8469 %{
8470 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8471
8472 expand %{
8473 rolI_rReg_CL(dst, shift, cr);
8474 %}
8475 %}
8476
8477 // ROR expand
8478 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8479 %{
8480 effect(USE_DEF dst, KILL cr);
8481
8482 format %{ "rorl $dst" %}
8483 opcode(0xD1, 0x1); /* D1 /1 */
8484 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8485 ins_pipe(ialu_reg);
8486 %}
8487
8488 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8489 %{
8490 effect(USE_DEF dst, USE shift, KILL cr);
8491
8492 format %{ "rorl $dst, $shift" %}
8493 opcode(0xC1, 0x1); /* C1 /1 ib */
8494 ins_encode(reg_opc_imm(dst, shift));
8495 ins_pipe(ialu_reg);
8496 %}
8497
8498 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8499 %{
8500 effect(USE_DEF dst, USE shift, KILL cr);
8501
8502 format %{ "rorl $dst, $shift" %}
8503 opcode(0xD3, 0x1); /* D3 /1 */
8504 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8505 ins_pipe(ialu_reg_reg);
8506 %}
8507 // end of ROR expand
8508
8509 // Rotate Right by one
8510 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8511 %{
8512 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8513
8514 expand %{
8515 rorI_rReg_imm1(dst, cr);
8516 %}
8517 %}
8518
8519 // Rotate Right by 8-bit immediate
8520 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8521 %{
8522 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8523 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8524
8525 expand %{
8526 rorI_rReg_imm8(dst, rshift, cr);
8527 %}
8528 %}
8529
8530 // Rotate Right by variable
8531 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8532 %{
8533 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8534
8535 expand %{
8536 rorI_rReg_CL(dst, shift, cr);
8537 %}
8538 %}
8539
8540 // Rotate Right by variable
8541 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8542 %{
8543 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8544
8545 expand %{
8546 rorI_rReg_CL(dst, shift, cr);
8547 %}
8548 %}
8549
8550 // for long rotate
8551 // ROL expand
8552 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8553 effect(USE_DEF dst, KILL cr);
8554
8555 format %{ "rolq $dst" %}
8556 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8557 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8558 ins_pipe(ialu_reg);
8559 %}
8560
8561 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8562 effect(USE_DEF dst, USE shift, KILL cr);
8563
8564 format %{ "rolq $dst, $shift" %}
8565 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8566 ins_encode( reg_opc_imm_wide(dst, shift) );
8567 ins_pipe(ialu_reg);
8568 %}
8569
8570 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8571 %{
8572 effect(USE_DEF dst, USE shift, KILL cr);
8573
8574 format %{ "rolq $dst, $shift" %}
8575 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8576 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8577 ins_pipe(ialu_reg_reg);
8578 %}
8579 // end of ROL expand
8580
8581 // Rotate Left by one
8582 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8583 %{
8584 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8585
8586 expand %{
8587 rolL_rReg_imm1(dst, cr);
8588 %}
8589 %}
8590
8591 // Rotate Left by 8-bit immediate
8592 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8593 %{
8594 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8595 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8596
8597 expand %{
8598 rolL_rReg_imm8(dst, lshift, cr);
8599 %}
8600 %}
8601
8602 // Rotate Left by variable
8603 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8604 %{
8605 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8606
8607 expand %{
8608 rolL_rReg_CL(dst, shift, cr);
8609 %}
8610 %}
8611
8612 // Rotate Left by variable
8613 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8614 %{
8615 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8616
8617 expand %{
8618 rolL_rReg_CL(dst, shift, cr);
8619 %}
8620 %}
8621
8622 // ROR expand
8623 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8624 %{
8625 effect(USE_DEF dst, KILL cr);
8626
8627 format %{ "rorq $dst" %}
8628 opcode(0xD1, 0x1); /* D1 /1 */
8629 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8630 ins_pipe(ialu_reg);
8631 %}
8632
8633 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8634 %{
8635 effect(USE_DEF dst, USE shift, KILL cr);
8636
8637 format %{ "rorq $dst, $shift" %}
8638 opcode(0xC1, 0x1); /* C1 /1 ib */
8639 ins_encode(reg_opc_imm_wide(dst, shift));
8640 ins_pipe(ialu_reg);
8641 %}
8642
8643 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8644 %{
8645 effect(USE_DEF dst, USE shift, KILL cr);
8646
8647 format %{ "rorq $dst, $shift" %}
8648 opcode(0xD3, 0x1); /* D3 /1 */
8649 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8650 ins_pipe(ialu_reg_reg);
8651 %}
8652 // end of ROR expand
8653
8654 // Rotate Right by one
8655 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8656 %{
8657 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8658
8659 expand %{
8660 rorL_rReg_imm1(dst, cr);
8661 %}
8662 %}
8663
8664 // Rotate Right by 8-bit immediate
8665 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8666 %{
8667 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8668 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8669
8670 expand %{
8671 rorL_rReg_imm8(dst, rshift, cr);
8672 %}
8673 %}
8674
8675 // Rotate Right by variable
8676 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8677 %{
8678 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8679
8680 expand %{
8681 rorL_rReg_CL(dst, shift, cr);
8682 %}
8683 %}
8684
8685 // Rotate Right by variable
8686 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8687 %{
8688 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8689
8690 expand %{
8691 rorL_rReg_CL(dst, shift, cr);
8692 %}
8693 %}
8694
8695 // Logical Instructions
8696
8697 // Integer Logical Instructions
8698
8699 // And Instructions
8700 // And Register with Register
8701 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8702 %{
8703 match(Set dst (AndI dst src));
8704 effect(KILL cr);
8705
8706 format %{ "andl $dst, $src\t# int" %}
8707 opcode(0x23);
8708 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8709 ins_pipe(ialu_reg_reg);
8710 %}
8711
8712 // And Register with Immediate 255
8713 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8714 %{
8715 match(Set dst (AndI dst src));
8716
8717 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8718 opcode(0x0F, 0xB6);
8719 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8720 ins_pipe(ialu_reg);
8721 %}
8722
8723 // And Register with Immediate 255 and promote to long
8724 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8725 %{
8726 match(Set dst (ConvI2L (AndI src mask)));
8727
8728 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8729 opcode(0x0F, 0xB6);
8730 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8731 ins_pipe(ialu_reg);
8732 %}
8733
8734 // And Register with Immediate 65535
8735 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8736 %{
8737 match(Set dst (AndI dst src));
8738
8739 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8740 opcode(0x0F, 0xB7);
8741 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8742 ins_pipe(ialu_reg);
8743 %}
8744
8745 // And Register with Immediate 65535 and promote to long
8746 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8747 %{
8748 match(Set dst (ConvI2L (AndI src mask)));
8749
8750 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8751 opcode(0x0F, 0xB7);
8752 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8753 ins_pipe(ialu_reg);
8754 %}
8755
8756 // And Register with Immediate
8757 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8758 %{
8759 match(Set dst (AndI dst src));
8760 effect(KILL cr);
8761
8762 format %{ "andl $dst, $src\t# int" %}
8763 opcode(0x81, 0x04); /* Opcode 81 /4 */
8764 ins_encode(OpcSErm(dst, src), Con8or32(src));
8765 ins_pipe(ialu_reg);
8766 %}
8767
8768 // And Register with Memory
8769 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8770 %{
8771 match(Set dst (AndI dst (LoadI src)));
8772 effect(KILL cr);
8773
8774 ins_cost(125);
8775 format %{ "andl $dst, $src\t# int" %}
8776 opcode(0x23);
8777 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8778 ins_pipe(ialu_reg_mem);
8779 %}
8780
8781 // And Memory with Register
8782 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8783 %{
8784 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8785 effect(KILL cr);
8786
8787 ins_cost(150);
8788 format %{ "andl $dst, $src\t# int" %}
8789 opcode(0x21); /* Opcode 21 /r */
8790 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8791 ins_pipe(ialu_mem_reg);
8792 %}
8793
8794 // And Memory with Immediate
8795 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8796 %{
8797 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8798 effect(KILL cr);
8799
8800 ins_cost(125);
8801 format %{ "andl $dst, $src\t# int" %}
8802 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8803 ins_encode(REX_mem(dst), OpcSE(src),
8804 RM_opc_mem(secondary, dst), Con8or32(src));
8805 ins_pipe(ialu_mem_imm);
8806 %}
8807
8808 // BMI1 instructions
8809 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8810 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8811 predicate(UseBMI1Instructions);
8812 effect(KILL cr);
8813
8814 ins_cost(125);
8815 format %{ "andnl $dst, $src1, $src2" %}
8816
8817 ins_encode %{
8818 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8819 %}
8820 ins_pipe(ialu_reg_mem);
8821 %}
8822
8823 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8824 match(Set dst (AndI (XorI src1 minus_1) src2));
8825 predicate(UseBMI1Instructions);
8826 effect(KILL cr);
8827
8828 format %{ "andnl $dst, $src1, $src2" %}
8829
8830 ins_encode %{
8831 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8832 %}
8833 ins_pipe(ialu_reg);
8834 %}
8835
8836 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8837 match(Set dst (AndI (SubI imm_zero src) src));
8838 predicate(UseBMI1Instructions);
8839 effect(KILL cr);
8840
8841 format %{ "blsil $dst, $src" %}
8842
8843 ins_encode %{
8844 __ blsil($dst$$Register, $src$$Register);
8845 %}
8846 ins_pipe(ialu_reg);
8847 %}
8848
8849 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8850 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8851 predicate(UseBMI1Instructions);
8852 effect(KILL cr);
8853
8854 ins_cost(125);
8855 format %{ "blsil $dst, $src" %}
8856
8857 ins_encode %{
8858 __ blsil($dst$$Register, $src$$Address);
8859 %}
8860 ins_pipe(ialu_reg_mem);
8861 %}
8862
8863 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8864 %{
8865 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8866 predicate(UseBMI1Instructions);
8867 effect(KILL cr);
8868
8869 ins_cost(125);
8870 format %{ "blsmskl $dst, $src" %}
8871
8872 ins_encode %{
8873 __ blsmskl($dst$$Register, $src$$Address);
8874 %}
8875 ins_pipe(ialu_reg_mem);
8876 %}
8877
8878 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8879 %{
8880 match(Set dst (XorI (AddI src minus_1) src));
8881 predicate(UseBMI1Instructions);
8882 effect(KILL cr);
8883
8884 format %{ "blsmskl $dst, $src" %}
8885
8886 ins_encode %{
8887 __ blsmskl($dst$$Register, $src$$Register);
8888 %}
8889
8890 ins_pipe(ialu_reg);
8891 %}
8892
8893 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8894 %{
8895 match(Set dst (AndI (AddI src minus_1) src) );
8896 predicate(UseBMI1Instructions);
8897 effect(KILL cr);
8898
8899 format %{ "blsrl $dst, $src" %}
8900
8901 ins_encode %{
8902 __ blsrl($dst$$Register, $src$$Register);
8903 %}
8904
8905 ins_pipe(ialu_reg_mem);
8906 %}
8907
8908 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8909 %{
8910 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8911 predicate(UseBMI1Instructions);
8912 effect(KILL cr);
8913
8914 ins_cost(125);
8915 format %{ "blsrl $dst, $src" %}
8916
8917 ins_encode %{
8918 __ blsrl($dst$$Register, $src$$Address);
8919 %}
8920
8921 ins_pipe(ialu_reg);
8922 %}
8923
8924 // Or Instructions
8925 // Or Register with Register
8926 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8927 %{
8928 match(Set dst (OrI dst src));
8929 effect(KILL cr);
8930
8931 format %{ "orl $dst, $src\t# int" %}
8932 opcode(0x0B);
8933 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8934 ins_pipe(ialu_reg_reg);
8935 %}
8936
8937 // Or Register with Immediate
8938 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8939 %{
8940 match(Set dst (OrI dst src));
8941 effect(KILL cr);
8942
8943 format %{ "orl $dst, $src\t# int" %}
8944 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8945 ins_encode(OpcSErm(dst, src), Con8or32(src));
8946 ins_pipe(ialu_reg);
8947 %}
8948
8949 // Or Register with Memory
8950 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8951 %{
8952 match(Set dst (OrI dst (LoadI src)));
8953 effect(KILL cr);
8954
8955 ins_cost(125);
8956 format %{ "orl $dst, $src\t# int" %}
8957 opcode(0x0B);
8958 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8959 ins_pipe(ialu_reg_mem);
8960 %}
8961
8962 // Or Memory with Register
8963 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8964 %{
8965 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8966 effect(KILL cr);
8967
8968 ins_cost(150);
8969 format %{ "orl $dst, $src\t# int" %}
8970 opcode(0x09); /* Opcode 09 /r */
8971 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8972 ins_pipe(ialu_mem_reg);
8973 %}
8974
8975 // Or Memory with Immediate
8976 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8977 %{
8978 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8979 effect(KILL cr);
8980
8981 ins_cost(125);
8982 format %{ "orl $dst, $src\t# int" %}
8983 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8984 ins_encode(REX_mem(dst), OpcSE(src),
8985 RM_opc_mem(secondary, dst), Con8or32(src));
8986 ins_pipe(ialu_mem_imm);
8987 %}
8988
8989 // Xor Instructions
8990 // Xor Register with Register
8991 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8992 %{
8993 match(Set dst (XorI dst src));
8994 effect(KILL cr);
8995
8996 format %{ "xorl $dst, $src\t# int" %}
8997 opcode(0x33);
8998 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8999 ins_pipe(ialu_reg_reg);
9000 %}
9001
9002 // Xor Register with Immediate -1
9003 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9004 match(Set dst (XorI dst imm));
9005
9006 format %{ "not $dst" %}
9007 ins_encode %{
9008 __ notl($dst$$Register);
9009 %}
9010 ins_pipe(ialu_reg);
9011 %}
9012
9013 // Xor Register with Immediate
9014 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9015 %{
9016 match(Set dst (XorI dst src));
9017 effect(KILL cr);
9018
9019 format %{ "xorl $dst, $src\t# int" %}
9020 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9021 ins_encode(OpcSErm(dst, src), Con8or32(src));
9022 ins_pipe(ialu_reg);
9023 %}
9024
9025 // Xor Register with Memory
9026 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9027 %{
9028 match(Set dst (XorI dst (LoadI src)));
9029 effect(KILL cr);
9030
9031 ins_cost(125);
9032 format %{ "xorl $dst, $src\t# int" %}
9033 opcode(0x33);
9034 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9035 ins_pipe(ialu_reg_mem);
9036 %}
9037
9038 // Xor Memory with Register
9039 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9040 %{
9041 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9042 effect(KILL cr);
9043
9044 ins_cost(150);
9045 format %{ "xorl $dst, $src\t# int" %}
9046 opcode(0x31); /* Opcode 31 /r */
9047 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9048 ins_pipe(ialu_mem_reg);
9049 %}
9050
9051 // Xor Memory with Immediate
9052 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9053 %{
9054 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9055 effect(KILL cr);
9056
9057 ins_cost(125);
9058 format %{ "xorl $dst, $src\t# int" %}
9059 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9060 ins_encode(REX_mem(dst), OpcSE(src),
9061 RM_opc_mem(secondary, dst), Con8or32(src));
9062 ins_pipe(ialu_mem_imm);
9063 %}
9064
9065
9066 // Long Logical Instructions
9067
9068 // And Instructions
9069 // And Register with Register
9070 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9071 %{
9072 match(Set dst (AndL dst src));
9073 effect(KILL cr);
9074
9075 format %{ "andq $dst, $src\t# long" %}
9076 opcode(0x23);
9077 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9078 ins_pipe(ialu_reg_reg);
9079 %}
9080
9081 // And Register with Immediate 255
9082 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9083 %{
9084 match(Set dst (AndL dst src));
9085
9086 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9087 opcode(0x0F, 0xB6);
9088 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9089 ins_pipe(ialu_reg);
9090 %}
9091
9092 // And Register with Immediate 65535
9093 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9094 %{
9095 match(Set dst (AndL dst src));
9096
9097 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9098 opcode(0x0F, 0xB7);
9099 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9100 ins_pipe(ialu_reg);
9101 %}
9102
9103 // And Register with Immediate
9104 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9105 %{
9106 match(Set dst (AndL dst src));
9107 effect(KILL cr);
9108
9109 format %{ "andq $dst, $src\t# long" %}
9110 opcode(0x81, 0x04); /* Opcode 81 /4 */
9111 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9112 ins_pipe(ialu_reg);
9113 %}
9114
9115 // And Register with Memory
9116 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9117 %{
9118 match(Set dst (AndL dst (LoadL src)));
9119 effect(KILL cr);
9120
9121 ins_cost(125);
9122 format %{ "andq $dst, $src\t# long" %}
9123 opcode(0x23);
9124 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9125 ins_pipe(ialu_reg_mem);
9126 %}
9127
9128 // And Memory with Register
9129 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9130 %{
9131 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9132 effect(KILL cr);
9133
9134 ins_cost(150);
9135 format %{ "andq $dst, $src\t# long" %}
9136 opcode(0x21); /* Opcode 21 /r */
9137 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9138 ins_pipe(ialu_mem_reg);
9139 %}
9140
9141 // And Memory with Immediate
9142 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9143 %{
9144 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9145 effect(KILL cr);
9146
9147 ins_cost(125);
9148 format %{ "andq $dst, $src\t# long" %}
9149 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9150 ins_encode(REX_mem_wide(dst), OpcSE(src),
9151 RM_opc_mem(secondary, dst), Con8or32(src));
9152 ins_pipe(ialu_mem_imm);
9153 %}
9154
9155 // BMI1 instructions
9156 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9157 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9158 predicate(UseBMI1Instructions);
9159 effect(KILL cr);
9160
9161 ins_cost(125);
9162 format %{ "andnq $dst, $src1, $src2" %}
9163
9164 ins_encode %{
9165 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9166 %}
9167 ins_pipe(ialu_reg_mem);
9168 %}
9169
9170 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9171 match(Set dst (AndL (XorL src1 minus_1) src2));
9172 predicate(UseBMI1Instructions);
9173 effect(KILL cr);
9174
9175 format %{ "andnq $dst, $src1, $src2" %}
9176
9177 ins_encode %{
9178 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9179 %}
9180 ins_pipe(ialu_reg_mem);
9181 %}
9182
9183 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9184 match(Set dst (AndL (SubL imm_zero src) src));
9185 predicate(UseBMI1Instructions);
9186 effect(KILL cr);
9187
9188 format %{ "blsiq $dst, $src" %}
9189
9190 ins_encode %{
9191 __ blsiq($dst$$Register, $src$$Register);
9192 %}
9193 ins_pipe(ialu_reg);
9194 %}
9195
9196 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9197 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9198 predicate(UseBMI1Instructions);
9199 effect(KILL cr);
9200
9201 ins_cost(125);
9202 format %{ "blsiq $dst, $src" %}
9203
9204 ins_encode %{
9205 __ blsiq($dst$$Register, $src$$Address);
9206 %}
9207 ins_pipe(ialu_reg_mem);
9208 %}
9209
9210 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9211 %{
9212 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9213 predicate(UseBMI1Instructions);
9214 effect(KILL cr);
9215
9216 ins_cost(125);
9217 format %{ "blsmskq $dst, $src" %}
9218
9219 ins_encode %{
9220 __ blsmskq($dst$$Register, $src$$Address);
9221 %}
9222 ins_pipe(ialu_reg_mem);
9223 %}
9224
9225 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9226 %{
9227 match(Set dst (XorL (AddL src minus_1) src));
9228 predicate(UseBMI1Instructions);
9229 effect(KILL cr);
9230
9231 format %{ "blsmskq $dst, $src" %}
9232
9233 ins_encode %{
9234 __ blsmskq($dst$$Register, $src$$Register);
9235 %}
9236
9237 ins_pipe(ialu_reg);
9238 %}
9239
9240 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9241 %{
9242 match(Set dst (AndL (AddL src minus_1) src) );
9243 predicate(UseBMI1Instructions);
9244 effect(KILL cr);
9245
9246 format %{ "blsrq $dst, $src" %}
9247
9248 ins_encode %{
9249 __ blsrq($dst$$Register, $src$$Register);
9250 %}
9251
9252 ins_pipe(ialu_reg);
9253 %}
9254
9255 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9256 %{
9257 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9258 predicate(UseBMI1Instructions);
9259 effect(KILL cr);
9260
9261 ins_cost(125);
9262 format %{ "blsrq $dst, $src" %}
9263
9264 ins_encode %{
9265 __ blsrq($dst$$Register, $src$$Address);
9266 %}
9267
9268 ins_pipe(ialu_reg);
9269 %}
9270
9271 // Or Instructions
9272 // Or Register with Register
9273 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9274 %{
9275 match(Set dst (OrL dst src));
9276 effect(KILL cr);
9277
9278 format %{ "orq $dst, $src\t# long" %}
9279 opcode(0x0B);
9280 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9281 ins_pipe(ialu_reg_reg);
9282 %}
9283
9284 // Use any_RegP to match R15 (TLS register) without spilling.
9285 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9286 match(Set dst (OrL dst (CastP2X src)));
9287 effect(KILL cr);
9288
9289 format %{ "orq $dst, $src\t# long" %}
9290 opcode(0x0B);
9291 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9292 ins_pipe(ialu_reg_reg);
9293 %}
9294
9295
9296 // Or Register with Immediate
9297 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9298 %{
9299 match(Set dst (OrL dst src));
9300 effect(KILL cr);
9301
9302 format %{ "orq $dst, $src\t# long" %}
9303 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9304 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9305 ins_pipe(ialu_reg);
9306 %}
9307
9308 // Or Register with Memory
9309 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9310 %{
9311 match(Set dst (OrL dst (LoadL src)));
9312 effect(KILL cr);
9313
9314 ins_cost(125);
9315 format %{ "orq $dst, $src\t# long" %}
9316 opcode(0x0B);
9317 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9318 ins_pipe(ialu_reg_mem);
9319 %}
9320
9321 // Or Memory with Register
9322 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9323 %{
9324 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9325 effect(KILL cr);
9326
9327 ins_cost(150);
9328 format %{ "orq $dst, $src\t# long" %}
9329 opcode(0x09); /* Opcode 09 /r */
9330 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9331 ins_pipe(ialu_mem_reg);
9332 %}
9333
9334 // Or Memory with Immediate
9335 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9336 %{
9337 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9338 effect(KILL cr);
9339
9340 ins_cost(125);
9341 format %{ "orq $dst, $src\t# long" %}
9342 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9343 ins_encode(REX_mem_wide(dst), OpcSE(src),
9344 RM_opc_mem(secondary, dst), Con8or32(src));
9345 ins_pipe(ialu_mem_imm);
9346 %}
9347
9348 // Xor Instructions
9349 // Xor Register with Register
9350 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9351 %{
9352 match(Set dst (XorL dst src));
9353 effect(KILL cr);
9354
9355 format %{ "xorq $dst, $src\t# long" %}
9356 opcode(0x33);
9357 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9358 ins_pipe(ialu_reg_reg);
9359 %}
9360
9361 // Xor Register with Immediate -1
9362 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9363 match(Set dst (XorL dst imm));
9364
9365 format %{ "notq $dst" %}
9366 ins_encode %{
9367 __ notq($dst$$Register);
9368 %}
9369 ins_pipe(ialu_reg);
9370 %}
9371
9372 // Xor Register with Immediate
9373 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9374 %{
9375 match(Set dst (XorL dst src));
9376 effect(KILL cr);
9377
9378 format %{ "xorq $dst, $src\t# long" %}
9379 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9380 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9381 ins_pipe(ialu_reg);
9382 %}
9383
9384 // Xor Register with Memory
9385 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9386 %{
9387 match(Set dst (XorL dst (LoadL src)));
9388 effect(KILL cr);
9389
9390 ins_cost(125);
9391 format %{ "xorq $dst, $src\t# long" %}
9392 opcode(0x33);
9393 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9394 ins_pipe(ialu_reg_mem);
9395 %}
9396
9397 // Xor Memory with Register
9398 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9399 %{
9400 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9401 effect(KILL cr);
9402
9403 ins_cost(150);
9404 format %{ "xorq $dst, $src\t# long" %}
9405 opcode(0x31); /* Opcode 31 /r */
9406 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9407 ins_pipe(ialu_mem_reg);
9408 %}
9409
9410 // Xor Memory with Immediate
9411 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9412 %{
9413 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9414 effect(KILL cr);
9415
9416 ins_cost(125);
9417 format %{ "xorq $dst, $src\t# long" %}
9418 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9419 ins_encode(REX_mem_wide(dst), OpcSE(src),
9420 RM_opc_mem(secondary, dst), Con8or32(src));
9421 ins_pipe(ialu_mem_imm);
9422 %}
9423
9424 // Convert Int to Boolean
9425 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9426 %{
9427 match(Set dst (Conv2B src));
9428 effect(KILL cr);
9429
9430 format %{ "testl $src, $src\t# ci2b\n\t"
9431 "setnz $dst\n\t"
9432 "movzbl $dst, $dst" %}
9433 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9434 setNZ_reg(dst),
9435 REX_reg_breg(dst, dst), // movzbl
9436 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9437 ins_pipe(pipe_slow); // XXX
9438 %}
9439
9440 // Convert Pointer to Boolean
9441 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9442 %{
9443 match(Set dst (Conv2B src));
9444 effect(KILL cr);
9445
9446 format %{ "testq $src, $src\t# cp2b\n\t"
9447 "setnz $dst\n\t"
9448 "movzbl $dst, $dst" %}
9449 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9450 setNZ_reg(dst),
9451 REX_reg_breg(dst, dst), // movzbl
9452 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9453 ins_pipe(pipe_slow); // XXX
9454 %}
9455
9456 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9457 %{
9458 match(Set dst (CmpLTMask p q));
9459 effect(KILL cr);
9460
9461 ins_cost(400);
9462 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9463 "setlt $dst\n\t"
9464 "movzbl $dst, $dst\n\t"
9465 "negl $dst" %}
9466 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9467 setLT_reg(dst),
9468 REX_reg_breg(dst, dst), // movzbl
9469 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9470 neg_reg(dst));
9471 ins_pipe(pipe_slow);
9472 %}
9473
9474 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9475 %{
9476 match(Set dst (CmpLTMask dst zero));
9477 effect(KILL cr);
9478
9479 ins_cost(100);
9480 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9481 ins_encode %{
9482 __ sarl($dst$$Register, 31);
9483 %}
9484 ins_pipe(ialu_reg);
9485 %}
9486
9487 /* Better to save a register than avoid a branch */
9488 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9489 %{
9490 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9491 effect(KILL cr);
9492 ins_cost(300);
9493 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9494 "jge done\n\t"
9495 "addl $p,$y\n"
9496 "done: " %}
9497 ins_encode %{
9498 Register Rp = $p$$Register;
9499 Register Rq = $q$$Register;
9500 Register Ry = $y$$Register;
9501 Label done;
9502 __ subl(Rp, Rq);
9503 __ jccb(Assembler::greaterEqual, done);
9504 __ addl(Rp, Ry);
9505 __ bind(done);
9506 %}
9507 ins_pipe(pipe_cmplt);
9508 %}
9509
9510 /* Better to save a register than avoid a branch */
9511 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9512 %{
9513 match(Set y (AndI (CmpLTMask p q) y));
9514 effect(KILL cr);
9515
9516 ins_cost(300);
9517
9518 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9519 "jlt done\n\t"
9520 "xorl $y, $y\n"
9521 "done: " %}
9522 ins_encode %{
9523 Register Rp = $p$$Register;
9524 Register Rq = $q$$Register;
9525 Register Ry = $y$$Register;
9526 Label done;
9527 __ cmpl(Rp, Rq);
9528 __ jccb(Assembler::less, done);
9529 __ xorl(Ry, Ry);
9530 __ bind(done);
9531 %}
9532 ins_pipe(pipe_cmplt);
9533 %}
9534
9535
9536 //---------- FP Instructions------------------------------------------------
9537
9538 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9539 %{
9540 match(Set cr (CmpF src1 src2));
9541
9542 ins_cost(145);
9543 format %{ "ucomiss $src1, $src2\n\t"
9544 "jnp,s exit\n\t"
9545 "pushfq\t# saw NaN, set CF\n\t"
9546 "andq [rsp], #0xffffff2b\n\t"
9547 "popfq\n"
9548 "exit:" %}
9549 ins_encode %{
9550 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9551 emit_cmpfp_fixup(_masm);
9552 %}
9553 ins_pipe(pipe_slow);
9554 %}
9555
9556 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9557 match(Set cr (CmpF src1 src2));
9558
9559 ins_cost(100);
9560 format %{ "ucomiss $src1, $src2" %}
9561 ins_encode %{
9562 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9563 %}
9564 ins_pipe(pipe_slow);
9565 %}
9566
9567 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9568 %{
9569 match(Set cr (CmpF src1 (LoadF src2)));
9570
9571 ins_cost(145);
9572 format %{ "ucomiss $src1, $src2\n\t"
9573 "jnp,s exit\n\t"
9574 "pushfq\t# saw NaN, set CF\n\t"
9575 "andq [rsp], #0xffffff2b\n\t"
9576 "popfq\n"
9577 "exit:" %}
9578 ins_encode %{
9579 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9580 emit_cmpfp_fixup(_masm);
9581 %}
9582 ins_pipe(pipe_slow);
9583 %}
9584
9585 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9586 match(Set cr (CmpF src1 (LoadF src2)));
9587
9588 ins_cost(100);
9589 format %{ "ucomiss $src1, $src2" %}
9590 ins_encode %{
9591 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9592 %}
9593 ins_pipe(pipe_slow);
9594 %}
9595
9596 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9597 match(Set cr (CmpF src con));
9598
9599 ins_cost(145);
9600 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9601 "jnp,s exit\n\t"
9602 "pushfq\t# saw NaN, set CF\n\t"
9603 "andq [rsp], #0xffffff2b\n\t"
9604 "popfq\n"
9605 "exit:" %}
9606 ins_encode %{
9607 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9608 emit_cmpfp_fixup(_masm);
9609 %}
9610 ins_pipe(pipe_slow);
9611 %}
9612
9613 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9614 match(Set cr (CmpF src con));
9615 ins_cost(100);
9616 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9617 ins_encode %{
9618 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9619 %}
9620 ins_pipe(pipe_slow);
9621 %}
9622
9623 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9624 %{
9625 match(Set cr (CmpD src1 src2));
9626
9627 ins_cost(145);
9628 format %{ "ucomisd $src1, $src2\n\t"
9629 "jnp,s exit\n\t"
9630 "pushfq\t# saw NaN, set CF\n\t"
9631 "andq [rsp], #0xffffff2b\n\t"
9632 "popfq\n"
9633 "exit:" %}
9634 ins_encode %{
9635 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9636 emit_cmpfp_fixup(_masm);
9637 %}
9638 ins_pipe(pipe_slow);
9639 %}
9640
9641 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9642 match(Set cr (CmpD src1 src2));
9643
9644 ins_cost(100);
9645 format %{ "ucomisd $src1, $src2 test" %}
9646 ins_encode %{
9647 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9648 %}
9649 ins_pipe(pipe_slow);
9650 %}
9651
9652 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9653 %{
9654 match(Set cr (CmpD src1 (LoadD src2)));
9655
9656 ins_cost(145);
9657 format %{ "ucomisd $src1, $src2\n\t"
9658 "jnp,s exit\n\t"
9659 "pushfq\t# saw NaN, set CF\n\t"
9660 "andq [rsp], #0xffffff2b\n\t"
9661 "popfq\n"
9662 "exit:" %}
9663 ins_encode %{
9664 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9665 emit_cmpfp_fixup(_masm);
9666 %}
9667 ins_pipe(pipe_slow);
9668 %}
9669
9670 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9671 match(Set cr (CmpD src1 (LoadD src2)));
9672
9673 ins_cost(100);
9674 format %{ "ucomisd $src1, $src2" %}
9675 ins_encode %{
9676 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9677 %}
9678 ins_pipe(pipe_slow);
9679 %}
9680
9681 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9682 match(Set cr (CmpD src con));
9683
9684 ins_cost(145);
9685 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9686 "jnp,s exit\n\t"
9687 "pushfq\t# saw NaN, set CF\n\t"
9688 "andq [rsp], #0xffffff2b\n\t"
9689 "popfq\n"
9690 "exit:" %}
9691 ins_encode %{
9692 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9693 emit_cmpfp_fixup(_masm);
9694 %}
9695 ins_pipe(pipe_slow);
9696 %}
9697
9698 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9699 match(Set cr (CmpD src con));
9700 ins_cost(100);
9701 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9702 ins_encode %{
9703 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9704 %}
9705 ins_pipe(pipe_slow);
9706 %}
9707
9708 // Compare into -1,0,1
9709 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9710 %{
9711 match(Set dst (CmpF3 src1 src2));
9712 effect(KILL cr);
9713
9714 ins_cost(275);
9715 format %{ "ucomiss $src1, $src2\n\t"
9716 "movl $dst, #-1\n\t"
9717 "jp,s done\n\t"
9718 "jb,s done\n\t"
9719 "setne $dst\n\t"
9720 "movzbl $dst, $dst\n"
9721 "done:" %}
9722 ins_encode %{
9723 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9724 emit_cmpfp3(_masm, $dst$$Register);
9725 %}
9726 ins_pipe(pipe_slow);
9727 %}
9728
9729 // Compare into -1,0,1
9730 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9731 %{
9732 match(Set dst (CmpF3 src1 (LoadF src2)));
9733 effect(KILL cr);
9734
9735 ins_cost(275);
9736 format %{ "ucomiss $src1, $src2\n\t"
9737 "movl $dst, #-1\n\t"
9738 "jp,s done\n\t"
9739 "jb,s done\n\t"
9740 "setne $dst\n\t"
9741 "movzbl $dst, $dst\n"
9742 "done:" %}
9743 ins_encode %{
9744 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9745 emit_cmpfp3(_masm, $dst$$Register);
9746 %}
9747 ins_pipe(pipe_slow);
9748 %}
9749
9750 // Compare into -1,0,1
9751 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9752 match(Set dst (CmpF3 src con));
9753 effect(KILL cr);
9754
9755 ins_cost(275);
9756 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9757 "movl $dst, #-1\n\t"
9758 "jp,s done\n\t"
9759 "jb,s done\n\t"
9760 "setne $dst\n\t"
9761 "movzbl $dst, $dst\n"
9762 "done:" %}
9763 ins_encode %{
9764 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9765 emit_cmpfp3(_masm, $dst$$Register);
9766 %}
9767 ins_pipe(pipe_slow);
9768 %}
9769
9770 // Compare into -1,0,1
9771 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9772 %{
9773 match(Set dst (CmpD3 src1 src2));
9774 effect(KILL cr);
9775
9776 ins_cost(275);
9777 format %{ "ucomisd $src1, $src2\n\t"
9778 "movl $dst, #-1\n\t"
9779 "jp,s done\n\t"
9780 "jb,s done\n\t"
9781 "setne $dst\n\t"
9782 "movzbl $dst, $dst\n"
9783 "done:" %}
9784 ins_encode %{
9785 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9786 emit_cmpfp3(_masm, $dst$$Register);
9787 %}
9788 ins_pipe(pipe_slow);
9789 %}
9790
9791 // Compare into -1,0,1
9792 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9793 %{
9794 match(Set dst (CmpD3 src1 (LoadD src2)));
9795 effect(KILL cr);
9796
9797 ins_cost(275);
9798 format %{ "ucomisd $src1, $src2\n\t"
9799 "movl $dst, #-1\n\t"
9800 "jp,s done\n\t"
9801 "jb,s done\n\t"
9802 "setne $dst\n\t"
9803 "movzbl $dst, $dst\n"
9804 "done:" %}
9805 ins_encode %{
9806 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9807 emit_cmpfp3(_masm, $dst$$Register);
9808 %}
9809 ins_pipe(pipe_slow);
9810 %}
9811
9812 // Compare into -1,0,1
9813 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9814 match(Set dst (CmpD3 src con));
9815 effect(KILL cr);
9816
9817 ins_cost(275);
9818 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9819 "movl $dst, #-1\n\t"
9820 "jp,s done\n\t"
9821 "jb,s done\n\t"
9822 "setne $dst\n\t"
9823 "movzbl $dst, $dst\n"
9824 "done:" %}
9825 ins_encode %{
9826 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9827 emit_cmpfp3(_masm, $dst$$Register);
9828 %}
9829 ins_pipe(pipe_slow);
9830 %}
9831
9832 // -----------Trig and Trancendental Instructions------------------------------
9833 instruct cosD_reg(regD dst) %{
9834 match(Set dst (CosD dst));
9835
9836 format %{ "dcos $dst\n\t" %}
9837 opcode(0xD9, 0xFF);
9838 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9839 ins_pipe( pipe_slow );
9840 %}
9841
9842 instruct sinD_reg(regD dst) %{
9843 match(Set dst (SinD dst));
9844
9845 format %{ "dsin $dst\n\t" %}
9846 opcode(0xD9, 0xFE);
9847 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9848 ins_pipe( pipe_slow );
9849 %}
9850
9851 instruct tanD_reg(regD dst) %{
9852 match(Set dst (TanD dst));
9853
9854 format %{ "dtan $dst\n\t" %}
9855 ins_encode( Push_SrcXD(dst),
9856 Opcode(0xD9), Opcode(0xF2), //fptan
9857 Opcode(0xDD), Opcode(0xD8), //fstp st
9858 Push_ResultXD(dst) );
9859 ins_pipe( pipe_slow );
9860 %}
9861
9862 instruct log10D_reg(regD dst) %{
9863 // The source and result Double operands in XMM registers
9864 match(Set dst (Log10D dst));
9865 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9866 // fyl2x ; compute log_10(2) * log_2(x)
9867 format %{ "fldlg2\t\t\t#Log10\n\t"
9868 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9869 %}
9870 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9871 Push_SrcXD(dst),
9872 Opcode(0xD9), Opcode(0xF1), // fyl2x
9873 Push_ResultXD(dst));
9874
9875 ins_pipe( pipe_slow );
9876 %}
9877
9878 instruct logD_reg(regD dst) %{
9879 // The source and result Double operands in XMM registers
9880 match(Set dst (LogD dst));
9881 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9882 // fyl2x ; compute log_e(2) * log_2(x)
9883 format %{ "fldln2\t\t\t#Log_e\n\t"
9884 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9885 %}
9886 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9887 Push_SrcXD(dst),
9888 Opcode(0xD9), Opcode(0xF1), // fyl2x
9889 Push_ResultXD(dst));
9890 ins_pipe( pipe_slow );
9891 %}
9892
9893 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9894 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9895 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9896 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9897 ins_encode %{
9898 __ subptr(rsp, 8);
9899 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9900 __ fld_d(Address(rsp, 0));
9901 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9902 __ fld_d(Address(rsp, 0));
9903 __ fast_pow();
9904 __ fstp_d(Address(rsp, 0));
9905 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9906 __ addptr(rsp, 8);
9907 %}
9908 ins_pipe( pipe_slow );
9909 %}
9910
9911 //----------Arithmetic Conversion Instructions---------------------------------
9912
9913 instruct roundFloat_nop(regF dst)
9914 %{
9915 match(Set dst (RoundFloat dst));
9916
9917 ins_cost(0);
9918 ins_encode();
9919 ins_pipe(empty);
9920 %}
9921
9922 instruct roundDouble_nop(regD dst)
9923 %{
9924 match(Set dst (RoundDouble dst));
9925
9926 ins_cost(0);
9927 ins_encode();
9928 ins_pipe(empty);
9929 %}
9930
9931 instruct convF2D_reg_reg(regD dst, regF src)
9932 %{
9933 match(Set dst (ConvF2D src));
9934
9935 format %{ "cvtss2sd $dst, $src" %}
9936 ins_encode %{
9937 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9938 %}
9939 ins_pipe(pipe_slow); // XXX
9940 %}
9941
9942 instruct convF2D_reg_mem(regD dst, memory src)
9943 %{
9944 match(Set dst (ConvF2D (LoadF src)));
9945
9946 format %{ "cvtss2sd $dst, $src" %}
9947 ins_encode %{
9948 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9949 %}
9950 ins_pipe(pipe_slow); // XXX
9951 %}
9952
9953 instruct convD2F_reg_reg(regF dst, regD src)
9954 %{
9955 match(Set dst (ConvD2F src));
9956
9957 format %{ "cvtsd2ss $dst, $src" %}
9958 ins_encode %{
9959 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9960 %}
9961 ins_pipe(pipe_slow); // XXX
9962 %}
9963
9964 instruct convD2F_reg_mem(regF dst, memory src)
9965 %{
9966 match(Set dst (ConvD2F (LoadD src)));
9967
9968 format %{ "cvtsd2ss $dst, $src" %}
9969 ins_encode %{
9970 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9971 %}
9972 ins_pipe(pipe_slow); // XXX
9973 %}
9974
9975 // XXX do mem variants
9976 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9977 %{
9978 match(Set dst (ConvF2I src));
9979 effect(KILL cr);
9980
9981 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9982 "cmpl $dst, #0x80000000\n\t"
9983 "jne,s done\n\t"
9984 "subq rsp, #8\n\t"
9985 "movss [rsp], $src\n\t"
9986 "call f2i_fixup\n\t"
9987 "popq $dst\n"
9988 "done: "%}
9989 ins_encode %{
9990 Label done;
9991 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9992 __ cmpl($dst$$Register, 0x80000000);
9993 __ jccb(Assembler::notEqual, done);
9994 __ subptr(rsp, 8);
9995 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9996 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9997 __ pop($dst$$Register);
9998 __ bind(done);
9999 %}
10000 ins_pipe(pipe_slow);
10001 %}
10002
10003 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10004 %{
10005 match(Set dst (ConvF2L src));
10006 effect(KILL cr);
10007
10008 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10009 "cmpq $dst, [0x8000000000000000]\n\t"
10010 "jne,s done\n\t"
10011 "subq rsp, #8\n\t"
10012 "movss [rsp], $src\n\t"
10013 "call f2l_fixup\n\t"
10014 "popq $dst\n"
10015 "done: "%}
10016 ins_encode %{
10017 Label done;
10018 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10019 __ cmp64($dst$$Register,
10020 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10021 __ jccb(Assembler::notEqual, done);
10022 __ subptr(rsp, 8);
10023 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10024 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10025 __ pop($dst$$Register);
10026 __ bind(done);
10027 %}
10028 ins_pipe(pipe_slow);
10029 %}
10030
10031 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10032 %{
10033 match(Set dst (ConvD2I src));
10034 effect(KILL cr);
10035
10036 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10037 "cmpl $dst, #0x80000000\n\t"
10038 "jne,s done\n\t"
10039 "subq rsp, #8\n\t"
10040 "movsd [rsp], $src\n\t"
10041 "call d2i_fixup\n\t"
10042 "popq $dst\n"
10043 "done: "%}
10044 ins_encode %{
10045 Label done;
10046 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10047 __ cmpl($dst$$Register, 0x80000000);
10048 __ jccb(Assembler::notEqual, done);
10049 __ subptr(rsp, 8);
10050 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10051 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10052 __ pop($dst$$Register);
10053 __ bind(done);
10054 %}
10055 ins_pipe(pipe_slow);
10056 %}
10057
10058 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10059 %{
10060 match(Set dst (ConvD2L src));
10061 effect(KILL cr);
10062
10063 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10064 "cmpq $dst, [0x8000000000000000]\n\t"
10065 "jne,s done\n\t"
10066 "subq rsp, #8\n\t"
10067 "movsd [rsp], $src\n\t"
10068 "call d2l_fixup\n\t"
10069 "popq $dst\n"
10070 "done: "%}
10071 ins_encode %{
10072 Label done;
10073 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10074 __ cmp64($dst$$Register,
10075 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10076 __ jccb(Assembler::notEqual, done);
10077 __ subptr(rsp, 8);
10078 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10079 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10080 __ pop($dst$$Register);
10081 __ bind(done);
10082 %}
10083 ins_pipe(pipe_slow);
10084 %}
10085
10086 instruct convI2F_reg_reg(regF dst, rRegI src)
10087 %{
10088 predicate(!UseXmmI2F);
10089 match(Set dst (ConvI2F src));
10090
10091 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10092 ins_encode %{
10093 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10094 %}
10095 ins_pipe(pipe_slow); // XXX
10096 %}
10097
10098 instruct convI2F_reg_mem(regF dst, memory src)
10099 %{
10100 match(Set dst (ConvI2F (LoadI src)));
10101
10102 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10103 ins_encode %{
10104 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10105 %}
10106 ins_pipe(pipe_slow); // XXX
10107 %}
10108
10109 instruct convI2D_reg_reg(regD dst, rRegI src)
10110 %{
10111 predicate(!UseXmmI2D);
10112 match(Set dst (ConvI2D src));
10113
10114 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10115 ins_encode %{
10116 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10117 %}
10118 ins_pipe(pipe_slow); // XXX
10119 %}
10120
10121 instruct convI2D_reg_mem(regD dst, memory src)
10122 %{
10123 match(Set dst (ConvI2D (LoadI src)));
10124
10125 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10126 ins_encode %{
10127 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10128 %}
10129 ins_pipe(pipe_slow); // XXX
10130 %}
10131
10132 instruct convXI2F_reg(regF dst, rRegI src)
10133 %{
10134 predicate(UseXmmI2F);
10135 match(Set dst (ConvI2F src));
10136
10137 format %{ "movdl $dst, $src\n\t"
10138 "cvtdq2psl $dst, $dst\t# i2f" %}
10139 ins_encode %{
10140 __ movdl($dst$$XMMRegister, $src$$Register);
10141 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10142 %}
10143 ins_pipe(pipe_slow); // XXX
10144 %}
10145
10146 instruct convXI2D_reg(regD dst, rRegI src)
10147 %{
10148 predicate(UseXmmI2D);
10149 match(Set dst (ConvI2D src));
10150
10151 format %{ "movdl $dst, $src\n\t"
10152 "cvtdq2pdl $dst, $dst\t# i2d" %}
10153 ins_encode %{
10154 __ movdl($dst$$XMMRegister, $src$$Register);
10155 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10156 %}
10157 ins_pipe(pipe_slow); // XXX
10158 %}
10159
10160 instruct convL2F_reg_reg(regF dst, rRegL src)
10161 %{
10162 match(Set dst (ConvL2F src));
10163
10164 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10165 ins_encode %{
10166 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10167 %}
10168 ins_pipe(pipe_slow); // XXX
10169 %}
10170
10171 instruct convL2F_reg_mem(regF dst, memory src)
10172 %{
10173 match(Set dst (ConvL2F (LoadL src)));
10174
10175 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10176 ins_encode %{
10177 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10178 %}
10179 ins_pipe(pipe_slow); // XXX
10180 %}
10181
10182 instruct convL2D_reg_reg(regD dst, rRegL src)
10183 %{
10184 match(Set dst (ConvL2D src));
10185
10186 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10187 ins_encode %{
10188 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10189 %}
10190 ins_pipe(pipe_slow); // XXX
10191 %}
10192
10193 instruct convL2D_reg_mem(regD dst, memory src)
10194 %{
10195 match(Set dst (ConvL2D (LoadL src)));
10196
10197 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10198 ins_encode %{
10199 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10200 %}
10201 ins_pipe(pipe_slow); // XXX
10202 %}
10203
10204 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10205 %{
10206 match(Set dst (ConvI2L src));
10207
10208 ins_cost(125);
10209 format %{ "movslq $dst, $src\t# i2l" %}
10210 ins_encode %{
10211 __ movslq($dst$$Register, $src$$Register);
10212 %}
10213 ins_pipe(ialu_reg_reg);
10214 %}
10215
10216 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10217 // %{
10218 // match(Set dst (ConvI2L src));
10219 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10220 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10221 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10222 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10223 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10224 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10225
10226 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10227 // ins_encode(enc_copy(dst, src));
10228 // // opcode(0x63); // needs REX.W
10229 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10230 // ins_pipe(ialu_reg_reg);
10231 // %}
10232
10233 // Zero-extend convert int to long
10234 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10235 %{
10236 match(Set dst (AndL (ConvI2L src) mask));
10237
10238 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10239 ins_encode %{
10240 if ($dst$$reg != $src$$reg) {
10241 __ movl($dst$$Register, $src$$Register);
10242 }
10243 %}
10244 ins_pipe(ialu_reg_reg);
10245 %}
10246
10247 // Zero-extend convert int to long
10248 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10249 %{
10250 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10251
10252 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10253 ins_encode %{
10254 __ movl($dst$$Register, $src$$Address);
10255 %}
10256 ins_pipe(ialu_reg_mem);
10257 %}
10258
10259 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10260 %{
10261 match(Set dst (AndL src mask));
10262
10263 format %{ "movl $dst, $src\t# zero-extend long" %}
10264 ins_encode %{
10265 __ movl($dst$$Register, $src$$Register);
10266 %}
10267 ins_pipe(ialu_reg_reg);
10268 %}
10269
10270 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10271 %{
10272 match(Set dst (ConvL2I src));
10273
10274 format %{ "movl $dst, $src\t# l2i" %}
10275 ins_encode %{
10276 __ movl($dst$$Register, $src$$Register);
10277 %}
10278 ins_pipe(ialu_reg_reg);
10279 %}
10280
10281
10282 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10283 match(Set dst (MoveF2I src));
10284 effect(DEF dst, USE src);
10285
10286 ins_cost(125);
10287 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10288 ins_encode %{
10289 __ movl($dst$$Register, Address(rsp, $src$$disp));
10290 %}
10291 ins_pipe(ialu_reg_mem);
10292 %}
10293
10294 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10295 match(Set dst (MoveI2F src));
10296 effect(DEF dst, USE src);
10297
10298 ins_cost(125);
10299 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10300 ins_encode %{
10301 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10302 %}
10303 ins_pipe(pipe_slow);
10304 %}
10305
10306 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10307 match(Set dst (MoveD2L src));
10308 effect(DEF dst, USE src);
10309
10310 ins_cost(125);
10311 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10312 ins_encode %{
10313 __ movq($dst$$Register, Address(rsp, $src$$disp));
10314 %}
10315 ins_pipe(ialu_reg_mem);
10316 %}
10317
10318 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10319 predicate(!UseXmmLoadAndClearUpper);
10320 match(Set dst (MoveL2D src));
10321 effect(DEF dst, USE src);
10322
10323 ins_cost(125);
10324 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10325 ins_encode %{
10326 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10327 %}
10328 ins_pipe(pipe_slow);
10329 %}
10330
10331 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10332 predicate(UseXmmLoadAndClearUpper);
10333 match(Set dst (MoveL2D src));
10334 effect(DEF dst, USE src);
10335
10336 ins_cost(125);
10337 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10338 ins_encode %{
10339 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10340 %}
10341 ins_pipe(pipe_slow);
10342 %}
10343
10344
10345 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10346 match(Set dst (MoveF2I src));
10347 effect(DEF dst, USE src);
10348
10349 ins_cost(95); // XXX
10350 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10351 ins_encode %{
10352 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10353 %}
10354 ins_pipe(pipe_slow);
10355 %}
10356
10357 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10358 match(Set dst (MoveI2F src));
10359 effect(DEF dst, USE src);
10360
10361 ins_cost(100);
10362 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10363 ins_encode %{
10364 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10365 %}
10366 ins_pipe( ialu_mem_reg );
10367 %}
10368
10369 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10370 match(Set dst (MoveD2L src));
10371 effect(DEF dst, USE src);
10372
10373 ins_cost(95); // XXX
10374 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10375 ins_encode %{
10376 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10377 %}
10378 ins_pipe(pipe_slow);
10379 %}
10380
10381 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10382 match(Set dst (MoveL2D src));
10383 effect(DEF dst, USE src);
10384
10385 ins_cost(100);
10386 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10387 ins_encode %{
10388 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10389 %}
10390 ins_pipe(ialu_mem_reg);
10391 %}
10392
10393 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10394 match(Set dst (MoveF2I src));
10395 effect(DEF dst, USE src);
10396 ins_cost(85);
10397 format %{ "movd $dst,$src\t# MoveF2I" %}
10398 ins_encode %{
10399 __ movdl($dst$$Register, $src$$XMMRegister);
10400 %}
10401 ins_pipe( pipe_slow );
10402 %}
10403
10404 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10405 match(Set dst (MoveD2L src));
10406 effect(DEF dst, USE src);
10407 ins_cost(85);
10408 format %{ "movd $dst,$src\t# MoveD2L" %}
10409 ins_encode %{
10410 __ movdq($dst$$Register, $src$$XMMRegister);
10411 %}
10412 ins_pipe( pipe_slow );
10413 %}
10414
10415 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10416 match(Set dst (MoveI2F src));
10417 effect(DEF dst, USE src);
10418 ins_cost(100);
10419 format %{ "movd $dst,$src\t# MoveI2F" %}
10420 ins_encode %{
10421 __ movdl($dst$$XMMRegister, $src$$Register);
10422 %}
10423 ins_pipe( pipe_slow );
10424 %}
10425
10426 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10427 match(Set dst (MoveL2D src));
10428 effect(DEF dst, USE src);
10429 ins_cost(100);
10430 format %{ "movd $dst,$src\t# MoveL2D" %}
10431 ins_encode %{
10432 __ movdq($dst$$XMMRegister, $src$$Register);
10433 %}
10434 ins_pipe( pipe_slow );
10435 %}
10436
10437
10438 // =======================================================================
10439 // fast clearing of an array
10440 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10441 rFlagsReg cr)
10442 %{
10443 predicate(!UseFastStosb);
10444 match(Set dummy (ClearArray cnt base));
10445 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10446
10447 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10448 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10449 ins_encode %{
10450 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10451 %}
10452 ins_pipe(pipe_slow);
10453 %}
10454
10455 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10456 rFlagsReg cr)
10457 %{
10458 predicate(UseFastStosb);
10459 match(Set dummy (ClearArray cnt base));
10460 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10461 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10462 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10463 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10464 ins_encode %{
10465 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10466 %}
10467 ins_pipe( pipe_slow );
10468 %}
10469
10470 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10471 rax_RegI result, regD tmp1, rFlagsReg cr)
10472 %{
10473 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10474 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10475
10476 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10477 ins_encode %{
10478 __ string_compare($str1$$Register, $str2$$Register,
10479 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10480 $tmp1$$XMMRegister);
10481 %}
10482 ins_pipe( pipe_slow );
10483 %}
10484
10485 // fast search of substring with known size.
10486 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10487 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10488 %{
10489 predicate(UseSSE42Intrinsics);
10490 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10491 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10492
10493 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10494 ins_encode %{
10495 int icnt2 = (int)$int_cnt2$$constant;
10496 if (icnt2 >= 8) {
10497 // IndexOf for constant substrings with size >= 8 elements
10498 // which don't need to be loaded through stack.
10499 __ string_indexofC8($str1$$Register, $str2$$Register,
10500 $cnt1$$Register, $cnt2$$Register,
10501 icnt2, $result$$Register,
10502 $vec$$XMMRegister, $tmp$$Register);
10503 } else {
10504 // Small strings are loaded through stack if they cross page boundary.
10505 __ string_indexof($str1$$Register, $str2$$Register,
10506 $cnt1$$Register, $cnt2$$Register,
10507 icnt2, $result$$Register,
10508 $vec$$XMMRegister, $tmp$$Register);
10509 }
10510 %}
10511 ins_pipe( pipe_slow );
10512 %}
10513
10514 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10515 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10516 %{
10517 predicate(UseSSE42Intrinsics);
10518 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10519 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10520
10521 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10522 ins_encode %{
10523 __ string_indexof($str1$$Register, $str2$$Register,
10524 $cnt1$$Register, $cnt2$$Register,
10525 (-1), $result$$Register,
10526 $vec$$XMMRegister, $tmp$$Register);
10527 %}
10528 ins_pipe( pipe_slow );
10529 %}
10530
10531 // fast string equals
10532 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10533 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10534 %{
10535 match(Set result (StrEquals (Binary str1 str2) cnt));
10536 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10537
10538 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10539 ins_encode %{
10540 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10541 $cnt$$Register, $result$$Register, $tmp3$$Register,
10542 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10543 %}
10544 ins_pipe( pipe_slow );
10545 %}
10546
10547 // fast array equals
10548 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10549 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10550 %{
10551 match(Set result (AryEq ary1 ary2));
10552 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10553 //ins_cost(300);
10554
10555 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10556 ins_encode %{
10557 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10558 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10559 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10560 %}
10561 ins_pipe( pipe_slow );
10562 %}
10563
10564 // encode char[] to byte[] in ISO_8859_1
10565 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10566 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10567 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10568 match(Set result (EncodeISOArray src (Binary dst len)));
10569 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10570
10571 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10572 ins_encode %{
10573 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10574 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10575 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10576 %}
10577 ins_pipe( pipe_slow );
10578 %}
10579
10580 //----------Overflow Math Instructions-----------------------------------------
10581
10582 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10583 %{
10584 match(Set cr (OverflowAddI op1 op2));
10585 effect(DEF cr, USE_KILL op1, USE op2);
10586
10587 format %{ "addl $op1, $op2\t# overflow check int" %}
10588
10589 ins_encode %{
10590 __ addl($op1$$Register, $op2$$Register);
10591 %}
10592 ins_pipe(ialu_reg_reg);
10593 %}
10594
10595 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10596 %{
10597 match(Set cr (OverflowAddI op1 op2));
10598 effect(DEF cr, USE_KILL op1, USE op2);
10599
10600 format %{ "addl $op1, $op2\t# overflow check int" %}
10601
10602 ins_encode %{
10603 __ addl($op1$$Register, $op2$$constant);
10604 %}
10605 ins_pipe(ialu_reg_reg);
10606 %}
10607
10608 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10609 %{
10610 match(Set cr (OverflowAddL op1 op2));
10611 effect(DEF cr, USE_KILL op1, USE op2);
10612
10613 format %{ "addq $op1, $op2\t# overflow check long" %}
10614 ins_encode %{
10615 __ addq($op1$$Register, $op2$$Register);
10616 %}
10617 ins_pipe(ialu_reg_reg);
10618 %}
10619
10620 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10621 %{
10622 match(Set cr (OverflowAddL op1 op2));
10623 effect(DEF cr, USE_KILL op1, USE op2);
10624
10625 format %{ "addq $op1, $op2\t# overflow check long" %}
10626 ins_encode %{
10627 __ addq($op1$$Register, $op2$$constant);
10628 %}
10629 ins_pipe(ialu_reg_reg);
10630 %}
10631
10632 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10633 %{
10634 match(Set cr (OverflowSubI op1 op2));
10635
10636 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10637 ins_encode %{
10638 __ cmpl($op1$$Register, $op2$$Register);
10639 %}
10640 ins_pipe(ialu_reg_reg);
10641 %}
10642
10643 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10644 %{
10645 match(Set cr (OverflowSubI op1 op2));
10646
10647 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10648 ins_encode %{
10649 __ cmpl($op1$$Register, $op2$$constant);
10650 %}
10651 ins_pipe(ialu_reg_reg);
10652 %}
10653
10654 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10655 %{
10656 match(Set cr (OverflowSubL op1 op2));
10657
10658 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10659 ins_encode %{
10660 __ cmpq($op1$$Register, $op2$$Register);
10661 %}
10662 ins_pipe(ialu_reg_reg);
10663 %}
10664
10665 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10666 %{
10667 match(Set cr (OverflowSubL op1 op2));
10668
10669 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10670 ins_encode %{
10671 __ cmpq($op1$$Register, $op2$$constant);
10672 %}
10673 ins_pipe(ialu_reg_reg);
10674 %}
10675
10676 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10677 %{
10678 match(Set cr (OverflowSubI zero op2));
10679 effect(DEF cr, USE_KILL op2);
10680
10681 format %{ "negl $op2\t# overflow check int" %}
10682 ins_encode %{
10683 __ negl($op2$$Register);
10684 %}
10685 ins_pipe(ialu_reg_reg);
10686 %}
10687
10688 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10689 %{
10690 match(Set cr (OverflowSubL zero op2));
10691 effect(DEF cr, USE_KILL op2);
10692
10693 format %{ "negq $op2\t# overflow check long" %}
10694 ins_encode %{
10695 __ negq($op2$$Register);
10696 %}
10697 ins_pipe(ialu_reg_reg);
10698 %}
10699
10700 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10701 %{
10702 match(Set cr (OverflowMulI op1 op2));
10703 effect(DEF cr, USE_KILL op1, USE op2);
10704
10705 format %{ "imull $op1, $op2\t# overflow check int" %}
10706 ins_encode %{
10707 __ imull($op1$$Register, $op2$$Register);
10708 %}
10709 ins_pipe(ialu_reg_reg_alu0);
10710 %}
10711
10712 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10713 %{
10714 match(Set cr (OverflowMulI op1 op2));
10715 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10716
10717 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10718 ins_encode %{
10719 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10720 %}
10721 ins_pipe(ialu_reg_reg_alu0);
10722 %}
10723
10724 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10725 %{
10726 match(Set cr (OverflowMulL op1 op2));
10727 effect(DEF cr, USE_KILL op1, USE op2);
10728
10729 format %{ "imulq $op1, $op2\t# overflow check long" %}
10730 ins_encode %{
10731 __ imulq($op1$$Register, $op2$$Register);
10732 %}
10733 ins_pipe(ialu_reg_reg_alu0);
10734 %}
10735
10736 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10737 %{
10738 match(Set cr (OverflowMulL op1 op2));
10739 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10740
10741 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10742 ins_encode %{
10743 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10744 %}
10745 ins_pipe(ialu_reg_reg_alu0);
10746 %}
10747
10748
10749 //----------Control Flow Instructions------------------------------------------
10750 // Signed compare Instructions
10751
10752 // XXX more variants!!
10753 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10754 %{
10755 match(Set cr (CmpI op1 op2));
10756 effect(DEF cr, USE op1, USE op2);
10757
10758 format %{ "cmpl $op1, $op2" %}
10759 opcode(0x3B); /* Opcode 3B /r */
10760 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10761 ins_pipe(ialu_cr_reg_reg);
10762 %}
10763
10764 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10765 %{
10766 match(Set cr (CmpI op1 op2));
10767
10768 format %{ "cmpl $op1, $op2" %}
10769 opcode(0x81, 0x07); /* Opcode 81 /7 */
10770 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10771 ins_pipe(ialu_cr_reg_imm);
10772 %}
10773
10774 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10775 %{
10776 match(Set cr (CmpI op1 (LoadI op2)));
10777
10778 ins_cost(500); // XXX
10779 format %{ "cmpl $op1, $op2" %}
10780 opcode(0x3B); /* Opcode 3B /r */
10781 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10782 ins_pipe(ialu_cr_reg_mem);
10783 %}
10784
10785 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10786 %{
10787 match(Set cr (CmpI src zero));
10788
10789 format %{ "testl $src, $src" %}
10790 opcode(0x85);
10791 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10792 ins_pipe(ialu_cr_reg_imm);
10793 %}
10794
10795 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10796 %{
10797 match(Set cr (CmpI (AndI src con) zero));
10798
10799 format %{ "testl $src, $con" %}
10800 opcode(0xF7, 0x00);
10801 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10802 ins_pipe(ialu_cr_reg_imm);
10803 %}
10804
10805 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10806 %{
10807 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10808
10809 format %{ "testl $src, $mem" %}
10810 opcode(0x85);
10811 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10812 ins_pipe(ialu_cr_reg_mem);
10813 %}
10814
10815 // Unsigned compare Instructions; really, same as signed except they
10816 // produce an rFlagsRegU instead of rFlagsReg.
10817 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10818 %{
10819 match(Set cr (CmpU op1 op2));
10820
10821 format %{ "cmpl $op1, $op2\t# unsigned" %}
10822 opcode(0x3B); /* Opcode 3B /r */
10823 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10824 ins_pipe(ialu_cr_reg_reg);
10825 %}
10826
10827 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10828 %{
10829 match(Set cr (CmpU op1 op2));
10830
10831 format %{ "cmpl $op1, $op2\t# unsigned" %}
10832 opcode(0x81,0x07); /* Opcode 81 /7 */
10833 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10834 ins_pipe(ialu_cr_reg_imm);
10835 %}
10836
10837 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10838 %{
10839 match(Set cr (CmpU op1 (LoadI op2)));
10840
10841 ins_cost(500); // XXX
10842 format %{ "cmpl $op1, $op2\t# unsigned" %}
10843 opcode(0x3B); /* Opcode 3B /r */
10844 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10845 ins_pipe(ialu_cr_reg_mem);
10846 %}
10847
10848 // // // Cisc-spilled version of cmpU_rReg
10849 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10850 // //%{
10851 // // match(Set cr (CmpU (LoadI op1) op2));
10852 // //
10853 // // format %{ "CMPu $op1,$op2" %}
10854 // // ins_cost(500);
10855 // // opcode(0x39); /* Opcode 39 /r */
10856 // // ins_encode( OpcP, reg_mem( op1, op2) );
10857 // //%}
10858
10859 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10860 %{
10861 match(Set cr (CmpU src zero));
10862
10863 format %{ "testl $src, $src\t# unsigned" %}
10864 opcode(0x85);
10865 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10866 ins_pipe(ialu_cr_reg_imm);
10867 %}
10868
10869 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10870 %{
10871 match(Set cr (CmpP op1 op2));
10872
10873 format %{ "cmpq $op1, $op2\t# ptr" %}
10874 opcode(0x3B); /* Opcode 3B /r */
10875 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10876 ins_pipe(ialu_cr_reg_reg);
10877 %}
10878
10879 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10880 %{
10881 match(Set cr (CmpP op1 (LoadP op2)));
10882
10883 ins_cost(500); // XXX
10884 format %{ "cmpq $op1, $op2\t# ptr" %}
10885 opcode(0x3B); /* Opcode 3B /r */
10886 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10887 ins_pipe(ialu_cr_reg_mem);
10888 %}
10889
10890 // // // Cisc-spilled version of cmpP_rReg
10891 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10892 // //%{
10893 // // match(Set cr (CmpP (LoadP op1) op2));
10894 // //
10895 // // format %{ "CMPu $op1,$op2" %}
10896 // // ins_cost(500);
10897 // // opcode(0x39); /* Opcode 39 /r */
10898 // // ins_encode( OpcP, reg_mem( op1, op2) );
10899 // //%}
10900
10901 // XXX this is generalized by compP_rReg_mem???
10902 // Compare raw pointer (used in out-of-heap check).
10903 // Only works because non-oop pointers must be raw pointers
10904 // and raw pointers have no anti-dependencies.
10905 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10906 %{
10907 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10908 match(Set cr (CmpP op1 (LoadP op2)));
10909
10910 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10911 opcode(0x3B); /* Opcode 3B /r */
10912 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10913 ins_pipe(ialu_cr_reg_mem);
10914 %}
10915
10916 // This will generate a signed flags result. This should be OK since
10917 // any compare to a zero should be eq/neq.
10918 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10919 %{
10920 match(Set cr (CmpP src zero));
10921
10922 format %{ "testq $src, $src\t# ptr" %}
10923 opcode(0x85);
10924 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10925 ins_pipe(ialu_cr_reg_imm);
10926 %}
10927
10928 // This will generate a signed flags result. This should be OK since
10929 // any compare to a zero should be eq/neq.
10930 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10931 %{
10932 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10933 match(Set cr (CmpP (LoadP op) zero));
10934
10935 ins_cost(500); // XXX
10936 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10937 opcode(0xF7); /* Opcode F7 /0 */
10938 ins_encode(REX_mem_wide(op),
10939 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10940 ins_pipe(ialu_cr_reg_imm);
10941 %}
10942
10943 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10944 %{
10945 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10946 match(Set cr (CmpP (LoadP mem) zero));
10947
10948 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10949 ins_encode %{
10950 __ cmpq(r12, $mem$$Address);
10951 %}
10952 ins_pipe(ialu_cr_reg_mem);
10953 %}
10954
10955 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10956 %{
10957 match(Set cr (CmpN op1 op2));
10958
10959 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10960 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10961 ins_pipe(ialu_cr_reg_reg);
10962 %}
10963
10964 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10965 %{
10966 match(Set cr (CmpN src (LoadN mem)));
10967
10968 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10969 ins_encode %{
10970 __ cmpl($src$$Register, $mem$$Address);
10971 %}
10972 ins_pipe(ialu_cr_reg_mem);
10973 %}
10974
10975 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10976 match(Set cr (CmpN op1 op2));
10977
10978 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10979 ins_encode %{
10980 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10981 %}
10982 ins_pipe(ialu_cr_reg_imm);
10983 %}
10984
10985 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10986 %{
10987 match(Set cr (CmpN src (LoadN mem)));
10988
10989 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10990 ins_encode %{
10991 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10992 %}
10993 ins_pipe(ialu_cr_reg_mem);
10994 %}
10995
10996 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10997 match(Set cr (CmpN op1 op2));
10998
10999 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11000 ins_encode %{
11001 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11002 %}
11003 ins_pipe(ialu_cr_reg_imm);
11004 %}
11005
11006 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11007 %{
11008 match(Set cr (CmpN src (LoadNKlass mem)));
11009
11010 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11011 ins_encode %{
11012 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11013 %}
11014 ins_pipe(ialu_cr_reg_mem);
11015 %}
11016
11017 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11018 match(Set cr (CmpN src zero));
11019
11020 format %{ "testl $src, $src\t# compressed ptr" %}
11021 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11022 ins_pipe(ialu_cr_reg_imm);
11023 %}
11024
11025 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11026 %{
11027 predicate(Universe::narrow_oop_base() != NULL);
11028 match(Set cr (CmpN (LoadN mem) zero));
11029
11030 ins_cost(500); // XXX
11031 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11032 ins_encode %{
11033 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11034 %}
11035 ins_pipe(ialu_cr_reg_mem);
11036 %}
11037
11038 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11039 %{
11040 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11041 match(Set cr (CmpN (LoadN mem) zero));
11042
11043 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11044 ins_encode %{
11045 __ cmpl(r12, $mem$$Address);
11046 %}
11047 ins_pipe(ialu_cr_reg_mem);
11048 %}
11049
11050 // Yanked all unsigned pointer compare operations.
11051 // Pointer compares are done with CmpP which is already unsigned.
11052
11053 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11054 %{
11055 match(Set cr (CmpL op1 op2));
11056
11057 format %{ "cmpq $op1, $op2" %}
11058 opcode(0x3B); /* Opcode 3B /r */
11059 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11060 ins_pipe(ialu_cr_reg_reg);
11061 %}
11062
11063 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11064 %{
11065 match(Set cr (CmpL op1 op2));
11066
11067 format %{ "cmpq $op1, $op2" %}
11068 opcode(0x81, 0x07); /* Opcode 81 /7 */
11069 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11070 ins_pipe(ialu_cr_reg_imm);
11071 %}
11072
11073 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11074 %{
11075 match(Set cr (CmpL op1 (LoadL op2)));
11076
11077 format %{ "cmpq $op1, $op2" %}
11078 opcode(0x3B); /* Opcode 3B /r */
11079 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11080 ins_pipe(ialu_cr_reg_mem);
11081 %}
11082
11083 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11084 %{
11085 match(Set cr (CmpL src zero));
11086
11087 format %{ "testq $src, $src" %}
11088 opcode(0x85);
11089 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11090 ins_pipe(ialu_cr_reg_imm);
11091 %}
11092
11093 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11094 %{
11095 match(Set cr (CmpL (AndL src con) zero));
11096
11097 format %{ "testq $src, $con\t# long" %}
11098 opcode(0xF7, 0x00);
11099 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11100 ins_pipe(ialu_cr_reg_imm);
11101 %}
11102
11103 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11104 %{
11105 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11106
11107 format %{ "testq $src, $mem" %}
11108 opcode(0x85);
11109 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11110 ins_pipe(ialu_cr_reg_mem);
11111 %}
11112
11113 // Manifest a CmpL result in an integer register. Very painful.
11114 // This is the test to avoid.
11115 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11116 %{
11117 match(Set dst (CmpL3 src1 src2));
11118 effect(KILL flags);
11119
11120 ins_cost(275); // XXX
11121 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11122 "movl $dst, -1\n\t"
11123 "jl,s done\n\t"
11124 "setne $dst\n\t"
11125 "movzbl $dst, $dst\n\t"
11126 "done:" %}
11127 ins_encode(cmpl3_flag(src1, src2, dst));
11128 ins_pipe(pipe_slow);
11129 %}
11130
11131 //----------Max and Min--------------------------------------------------------
11132 // Min Instructions
11133
11134 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11135 %{
11136 effect(USE_DEF dst, USE src, USE cr);
11137
11138 format %{ "cmovlgt $dst, $src\t# min" %}
11139 opcode(0x0F, 0x4F);
11140 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11141 ins_pipe(pipe_cmov_reg);
11142 %}
11143
11144
11145 instruct minI_rReg(rRegI dst, rRegI src)
11146 %{
11147 match(Set dst (MinI dst src));
11148
11149 ins_cost(200);
11150 expand %{
11151 rFlagsReg cr;
11152 compI_rReg(cr, dst, src);
11153 cmovI_reg_g(dst, src, cr);
11154 %}
11155 %}
11156
11157 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11158 %{
11159 effect(USE_DEF dst, USE src, USE cr);
11160
11161 format %{ "cmovllt $dst, $src\t# max" %}
11162 opcode(0x0F, 0x4C);
11163 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11164 ins_pipe(pipe_cmov_reg);
11165 %}
11166
11167
11168 instruct maxI_rReg(rRegI dst, rRegI src)
11169 %{
11170 match(Set dst (MaxI dst src));
11171
11172 ins_cost(200);
11173 expand %{
11174 rFlagsReg cr;
11175 compI_rReg(cr, dst, src);
11176 cmovI_reg_l(dst, src, cr);
11177 %}
11178 %}
11179
11180 // ============================================================================
11181 // Branch Instructions
11182
11183 // Jump Direct - Label defines a relative address from JMP+1
11184 instruct jmpDir(label labl)
11185 %{
11186 match(Goto);
11187 effect(USE labl);
11188
11189 ins_cost(300);
11190 format %{ "jmp $labl" %}
11191 size(5);
11192 ins_encode %{
11193 Label* L = $labl$$label;
11194 __ jmp(*L, false); // Always long jump
11195 %}
11196 ins_pipe(pipe_jmp);
11197 %}
11198
11199 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11200 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11201 %{
11202 match(If cop cr);
11203 effect(USE labl);
11204
11205 ins_cost(300);
11206 format %{ "j$cop $labl" %}
11207 size(6);
11208 ins_encode %{
11209 Label* L = $labl$$label;
11210 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11211 %}
11212 ins_pipe(pipe_jcc);
11213 %}
11214
11215 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11216 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11217 %{
11218 match(CountedLoopEnd cop cr);
11219 effect(USE labl);
11220
11221 ins_cost(300);
11222 format %{ "j$cop $labl\t# loop end" %}
11223 size(6);
11224 ins_encode %{
11225 Label* L = $labl$$label;
11226 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11227 %}
11228 ins_pipe(pipe_jcc);
11229 %}
11230
11231 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11232 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11233 match(CountedLoopEnd cop cmp);
11234 effect(USE labl);
11235
11236 ins_cost(300);
11237 format %{ "j$cop,u $labl\t# loop end" %}
11238 size(6);
11239 ins_encode %{
11240 Label* L = $labl$$label;
11241 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11242 %}
11243 ins_pipe(pipe_jcc);
11244 %}
11245
11246 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11247 match(CountedLoopEnd cop cmp);
11248 effect(USE labl);
11249
11250 ins_cost(200);
11251 format %{ "j$cop,u $labl\t# loop end" %}
11252 size(6);
11253 ins_encode %{
11254 Label* L = $labl$$label;
11255 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11256 %}
11257 ins_pipe(pipe_jcc);
11258 %}
11259
11260 // Jump Direct Conditional - using unsigned comparison
11261 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11262 match(If cop cmp);
11263 effect(USE labl);
11264
11265 ins_cost(300);
11266 format %{ "j$cop,u $labl" %}
11267 size(6);
11268 ins_encode %{
11269 Label* L = $labl$$label;
11270 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11271 %}
11272 ins_pipe(pipe_jcc);
11273 %}
11274
11275 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11276 match(If cop cmp);
11277 effect(USE labl);
11278
11279 ins_cost(200);
11280 format %{ "j$cop,u $labl" %}
11281 size(6);
11282 ins_encode %{
11283 Label* L = $labl$$label;
11284 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11285 %}
11286 ins_pipe(pipe_jcc);
11287 %}
11288
11289 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11290 match(If cop cmp);
11291 effect(USE labl);
11292
11293 ins_cost(200);
11294 format %{ $$template
11295 if ($cop$$cmpcode == Assembler::notEqual) {
11296 $$emit$$"jp,u $labl\n\t"
11297 $$emit$$"j$cop,u $labl"
11298 } else {
11299 $$emit$$"jp,u done\n\t"
11300 $$emit$$"j$cop,u $labl\n\t"
11301 $$emit$$"done:"
11302 }
11303 %}
11304 ins_encode %{
11305 Label* l = $labl$$label;
11306 if ($cop$$cmpcode == Assembler::notEqual) {
11307 __ jcc(Assembler::parity, *l, false);
11308 __ jcc(Assembler::notEqual, *l, false);
11309 } else if ($cop$$cmpcode == Assembler::equal) {
11310 Label done;
11311 __ jccb(Assembler::parity, done);
11312 __ jcc(Assembler::equal, *l, false);
11313 __ bind(done);
11314 } else {
11315 ShouldNotReachHere();
11316 }
11317 %}
11318 ins_pipe(pipe_jcc);
11319 %}
11320
11321 // ============================================================================
11322 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11323 // superklass array for an instance of the superklass. Set a hidden
11324 // internal cache on a hit (cache is checked with exposed code in
11325 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11326 // encoding ALSO sets flags.
11327
11328 instruct partialSubtypeCheck(rdi_RegP result,
11329 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11330 rFlagsReg cr)
11331 %{
11332 match(Set result (PartialSubtypeCheck sub super));
11333 effect(KILL rcx, KILL cr);
11334
11335 ins_cost(1100); // slightly larger than the next version
11336 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11337 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11338 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11339 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11340 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11341 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11342 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11343 "miss:\t" %}
11344
11345 opcode(0x1); // Force a XOR of RDI
11346 ins_encode(enc_PartialSubtypeCheck());
11347 ins_pipe(pipe_slow);
11348 %}
11349
11350 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11351 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11352 immP0 zero,
11353 rdi_RegP result)
11354 %{
11355 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11356 effect(KILL rcx, KILL result);
11357
11358 ins_cost(1000);
11359 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11360 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11361 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11362 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11363 "jne,s miss\t\t# Missed: flags nz\n\t"
11364 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11365 "miss:\t" %}
11366
11367 opcode(0x0); // No need to XOR RDI
11368 ins_encode(enc_PartialSubtypeCheck());
11369 ins_pipe(pipe_slow);
11370 %}
11371
11372 // ============================================================================
11373 // Branch Instructions -- short offset versions
11374 //
11375 // These instructions are used to replace jumps of a long offset (the default
11376 // match) with jumps of a shorter offset. These instructions are all tagged
11377 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11378 // match rules in general matching. Instead, the ADLC generates a conversion
11379 // method in the MachNode which can be used to do in-place replacement of the
11380 // long variant with the shorter variant. The compiler will determine if a
11381 // branch can be taken by the is_short_branch_offset() predicate in the machine
11382 // specific code section of the file.
11383
11384 // Jump Direct - Label defines a relative address from JMP+1
11385 instruct jmpDir_short(label labl) %{
11386 match(Goto);
11387 effect(USE labl);
11388
11389 ins_cost(300);
11390 format %{ "jmp,s $labl" %}
11391 size(2);
11392 ins_encode %{
11393 Label* L = $labl$$label;
11394 __ jmpb(*L);
11395 %}
11396 ins_pipe(pipe_jmp);
11397 ins_short_branch(1);
11398 %}
11399
11400 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11401 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11402 match(If cop cr);
11403 effect(USE labl);
11404
11405 ins_cost(300);
11406 format %{ "j$cop,s $labl" %}
11407 size(2);
11408 ins_encode %{
11409 Label* L = $labl$$label;
11410 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11411 %}
11412 ins_pipe(pipe_jcc);
11413 ins_short_branch(1);
11414 %}
11415
11416 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11417 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11418 match(CountedLoopEnd cop cr);
11419 effect(USE labl);
11420
11421 ins_cost(300);
11422 format %{ "j$cop,s $labl\t# loop end" %}
11423 size(2);
11424 ins_encode %{
11425 Label* L = $labl$$label;
11426 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11427 %}
11428 ins_pipe(pipe_jcc);
11429 ins_short_branch(1);
11430 %}
11431
11432 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11433 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11434 match(CountedLoopEnd cop cmp);
11435 effect(USE labl);
11436
11437 ins_cost(300);
11438 format %{ "j$cop,us $labl\t# loop end" %}
11439 size(2);
11440 ins_encode %{
11441 Label* L = $labl$$label;
11442 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11443 %}
11444 ins_pipe(pipe_jcc);
11445 ins_short_branch(1);
11446 %}
11447
11448 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11449 match(CountedLoopEnd cop cmp);
11450 effect(USE labl);
11451
11452 ins_cost(300);
11453 format %{ "j$cop,us $labl\t# loop end" %}
11454 size(2);
11455 ins_encode %{
11456 Label* L = $labl$$label;
11457 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11458 %}
11459 ins_pipe(pipe_jcc);
11460 ins_short_branch(1);
11461 %}
11462
11463 // Jump Direct Conditional - using unsigned comparison
11464 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11465 match(If cop cmp);
11466 effect(USE labl);
11467
11468 ins_cost(300);
11469 format %{ "j$cop,us $labl" %}
11470 size(2);
11471 ins_encode %{
11472 Label* L = $labl$$label;
11473 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11474 %}
11475 ins_pipe(pipe_jcc);
11476 ins_short_branch(1);
11477 %}
11478
11479 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11480 match(If cop cmp);
11481 effect(USE labl);
11482
11483 ins_cost(300);
11484 format %{ "j$cop,us $labl" %}
11485 size(2);
11486 ins_encode %{
11487 Label* L = $labl$$label;
11488 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11489 %}
11490 ins_pipe(pipe_jcc);
11491 ins_short_branch(1);
11492 %}
11493
11494 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11495 match(If cop cmp);
11496 effect(USE labl);
11497
11498 ins_cost(300);
11499 format %{ $$template
11500 if ($cop$$cmpcode == Assembler::notEqual) {
11501 $$emit$$"jp,u,s $labl\n\t"
11502 $$emit$$"j$cop,u,s $labl"
11503 } else {
11504 $$emit$$"jp,u,s done\n\t"
11505 $$emit$$"j$cop,u,s $labl\n\t"
11506 $$emit$$"done:"
11507 }
11508 %}
11509 size(4);
11510 ins_encode %{
11511 Label* l = $labl$$label;
11512 if ($cop$$cmpcode == Assembler::notEqual) {
11513 __ jccb(Assembler::parity, *l);
11514 __ jccb(Assembler::notEqual, *l);
11515 } else if ($cop$$cmpcode == Assembler::equal) {
11516 Label done;
11517 __ jccb(Assembler::parity, done);
11518 __ jccb(Assembler::equal, *l);
11519 __ bind(done);
11520 } else {
11521 ShouldNotReachHere();
11522 }
11523 %}
11524 ins_pipe(pipe_jcc);
11525 ins_short_branch(1);
11526 %}
11527
11528 // ============================================================================
11529 // inlined locking and unlocking
11530
11531 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11532 predicate(Compile::current()->use_rtm());
11533 match(Set cr (FastLock object box));
11534 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11535 ins_cost(300);
11536 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11537 ins_encode %{
11538 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11539 $scr$$Register, $cx1$$Register, $cx2$$Register,
11540 _counters, _rtm_counters, _stack_rtm_counters,
11541 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11542 true, ra_->C->profile_rtm());
11543 %}
11544 ins_pipe(pipe_slow);
11545 %}
11546
11547 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11548 predicate(!Compile::current()->use_rtm());
11549 match(Set cr (FastLock object box));
11550 effect(TEMP tmp, TEMP scr, USE_KILL box);
11551 ins_cost(300);
11552 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11553 ins_encode %{
11554 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11555 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
11556 %}
11557 ins_pipe(pipe_slow);
11558 %}
11559
11560 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11561 match(Set cr (FastUnlock object box));
11562 effect(TEMP tmp, USE_KILL box);
11563 ins_cost(300);
11564 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11565 ins_encode %{
11566 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
11567 %}
11568 ins_pipe(pipe_slow);
11569 %}
11570
11571
11572 // ============================================================================
11573 // Safepoint Instructions
11574 instruct safePoint_poll(rFlagsReg cr)
11575 %{
11576 predicate(!Assembler::is_polling_page_far());
11577 match(SafePoint);
11578 effect(KILL cr);
11579
11580 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11581 "# Safepoint: poll for GC" %}
11582 ins_cost(125);
11583 ins_encode %{
11584 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11585 __ testl(rax, addr);
11586 %}
11587 ins_pipe(ialu_reg_mem);
11588 %}
11589
11590 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11591 %{
11592 predicate(Assembler::is_polling_page_far());
11593 match(SafePoint poll);
11594 effect(KILL cr, USE poll);
11595
11596 format %{ "testl rax, [$poll]\t"
11597 "# Safepoint: poll for GC" %}
11598 ins_cost(125);
11599 ins_encode %{
11600 __ relocate(relocInfo::poll_type);
11601 __ testl(rax, Address($poll$$Register, 0));
11602 %}
11603 ins_pipe(ialu_reg_mem);
11604 %}
11605
11606 // ============================================================================
11607 // Procedure Call/Return Instructions
11608 // Call Java Static Instruction
11609 // Note: If this code changes, the corresponding ret_addr_offset() and
11610 // compute_padding() functions will have to be adjusted.
11611 instruct CallStaticJavaDirect(method meth) %{
11612 match(CallStaticJava);
11613 effect(USE meth);
11614
11615 ins_cost(300);
11616 format %{ "call,static " %}
11617 opcode(0xE8); /* E8 cd */
11618 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11619 ins_pipe(pipe_slow);
11620 ins_alignment(4);
11621 %}
11622
11623 // Call Java Dynamic Instruction
11624 // Note: If this code changes, the corresponding ret_addr_offset() and
11625 // compute_padding() functions will have to be adjusted.
11626 instruct CallDynamicJavaDirect(method meth)
11627 %{
11628 match(CallDynamicJava);
11629 effect(USE meth);
11630
11631 ins_cost(300);
11632 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11633 "call,dynamic " %}
11634 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11635 ins_pipe(pipe_slow);
11636 ins_alignment(4);
11637 %}
11638
11639 // Call Runtime Instruction
11640 instruct CallRuntimeDirect(method meth)
11641 %{
11642 match(CallRuntime);
11643 effect(USE meth);
11644
11645 ins_cost(300);
11646 format %{ "call,runtime " %}
11647 ins_encode(clear_avx, Java_To_Runtime(meth));
11648 ins_pipe(pipe_slow);
11649 %}
11650
11651 // Call runtime without safepoint
11652 instruct CallLeafDirect(method meth)
11653 %{
11654 match(CallLeaf);
11655 effect(USE meth);
11656
11657 ins_cost(300);
11658 format %{ "call_leaf,runtime " %}
11659 ins_encode(clear_avx, Java_To_Runtime(meth));
11660 ins_pipe(pipe_slow);
11661 %}
11662
11663 // Call runtime without safepoint
11664 instruct CallLeafNoFPDirect(method meth)
11665 %{
11666 match(CallLeafNoFP);
11667 effect(USE meth);
11668
11669 ins_cost(300);
11670 format %{ "call_leaf_nofp,runtime " %}
11671 ins_encode(Java_To_Runtime(meth));
11672 ins_pipe(pipe_slow);
11673 %}
11674
11675 // Return Instruction
11676 // Remove the return address & jump to it.
11677 // Notice: We always emit a nop after a ret to make sure there is room
11678 // for safepoint patching
11679 instruct Ret()
11680 %{
11681 match(Return);
11682
11683 format %{ "ret" %}
11684 opcode(0xC3);
11685 ins_encode(OpcP);
11686 ins_pipe(pipe_jmp);
11687 %}
11688
11689 // Tail Call; Jump from runtime stub to Java code.
11690 // Also known as an 'interprocedural jump'.
11691 // Target of jump will eventually return to caller.
11692 // TailJump below removes the return address.
11693 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11694 %{
11695 match(TailCall jump_target method_oop);
11696
11697 ins_cost(300);
11698 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11699 opcode(0xFF, 0x4); /* Opcode FF /4 */
11700 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11701 ins_pipe(pipe_jmp);
11702 %}
11703
11704 // Tail Jump; remove the return address; jump to target.
11705 // TailCall above leaves the return address around.
11706 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11707 %{
11708 match(TailJump jump_target ex_oop);
11709
11710 ins_cost(300);
11711 format %{ "popq rdx\t# pop return address\n\t"
11712 "jmp $jump_target" %}
11713 opcode(0xFF, 0x4); /* Opcode FF /4 */
11714 ins_encode(Opcode(0x5a), // popq rdx
11715 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11716 ins_pipe(pipe_jmp);
11717 %}
11718
11719 // Create exception oop: created by stack-crawling runtime code.
11720 // Created exception is now available to this handler, and is setup
11721 // just prior to jumping to this handler. No code emitted.
11722 instruct CreateException(rax_RegP ex_oop)
11723 %{
11724 match(Set ex_oop (CreateEx));
11725
11726 size(0);
11727 // use the following format syntax
11728 format %{ "# exception oop is in rax; no code emitted" %}
11729 ins_encode();
11730 ins_pipe(empty);
11731 %}
11732
11733 // Rethrow exception:
11734 // The exception oop will come in the first argument position.
11735 // Then JUMP (not call) to the rethrow stub code.
11736 instruct RethrowException()
11737 %{
11738 match(Rethrow);
11739
11740 // use the following format syntax
11741 format %{ "jmp rethrow_stub" %}
11742 ins_encode(enc_rethrow);
11743 ins_pipe(pipe_jmp);
11744 %}
11745
11746
11747 // ============================================================================
11748 // This name is KNOWN by the ADLC and cannot be changed.
11749 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11750 // for this guy.
11751 instruct tlsLoadP(r15_RegP dst) %{
11752 match(Set dst (ThreadLocal));
11753 effect(DEF dst);
11754
11755 size(0);
11756 format %{ "# TLS is in R15" %}
11757 ins_encode( /*empty encoding*/ );
11758 ins_pipe(ialu_reg_reg);
11759 %}
11760
11761
11762 //----------PEEPHOLE RULES-----------------------------------------------------
11763 // These must follow all instruction definitions as they use the names
11764 // defined in the instructions definitions.
11765 //
11766 // peepmatch ( root_instr_name [preceding_instruction]* );
11767 //
11768 // peepconstraint %{
11769 // (instruction_number.operand_name relational_op instruction_number.operand_name
11770 // [, ...] );
11771 // // instruction numbers are zero-based using left to right order in peepmatch
11772 //
11773 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11774 // // provide an instruction_number.operand_name for each operand that appears
11775 // // in the replacement instruction's match rule
11776 //
11777 // ---------VM FLAGS---------------------------------------------------------
11778 //
11779 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11780 //
11781 // Each peephole rule is given an identifying number starting with zero and
11782 // increasing by one in the order seen by the parser. An individual peephole
11783 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11784 // on the command-line.
11785 //
11786 // ---------CURRENT LIMITATIONS----------------------------------------------
11787 //
11788 // Only match adjacent instructions in same basic block
11789 // Only equality constraints
11790 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11791 // Only one replacement instruction
11792 //
11793 // ---------EXAMPLE----------------------------------------------------------
11794 //
11795 // // pertinent parts of existing instructions in architecture description
11796 // instruct movI(rRegI dst, rRegI src)
11797 // %{
11798 // match(Set dst (CopyI src));
11799 // %}
11800 //
11801 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11802 // %{
11803 // match(Set dst (AddI dst src));
11804 // effect(KILL cr);
11805 // %}
11806 //
11807 // // Change (inc mov) to lea
11808 // peephole %{
11809 // // increment preceeded by register-register move
11810 // peepmatch ( incI_rReg movI );
11811 // // require that the destination register of the increment
11812 // // match the destination register of the move
11813 // peepconstraint ( 0.dst == 1.dst );
11814 // // construct a replacement instruction that sets
11815 // // the destination to ( move's source register + one )
11816 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11817 // %}
11818 //
11819
11820 // Implementation no longer uses movX instructions since
11821 // machine-independent system no longer uses CopyX nodes.
11822 //
11823 // peephole
11824 // %{
11825 // peepmatch (incI_rReg movI);
11826 // peepconstraint (0.dst == 1.dst);
11827 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11828 // %}
11829
11830 // peephole
11831 // %{
11832 // peepmatch (decI_rReg movI);
11833 // peepconstraint (0.dst == 1.dst);
11834 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11835 // %}
11836
11837 // peephole
11838 // %{
11839 // peepmatch (addI_rReg_imm movI);
11840 // peepconstraint (0.dst == 1.dst);
11841 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11842 // %}
11843
11844 // peephole
11845 // %{
11846 // peepmatch (incL_rReg movL);
11847 // peepconstraint (0.dst == 1.dst);
11848 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11849 // %}
11850
11851 // peephole
11852 // %{
11853 // peepmatch (decL_rReg movL);
11854 // peepconstraint (0.dst == 1.dst);
11855 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11856 // %}
11857
11858 // peephole
11859 // %{
11860 // peepmatch (addL_rReg_imm movL);
11861 // peepconstraint (0.dst == 1.dst);
11862 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11863 // %}
11864
11865 // peephole
11866 // %{
11867 // peepmatch (addP_rReg_imm movP);
11868 // peepconstraint (0.dst == 1.dst);
11869 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11870 // %}
11871
11872 // // Change load of spilled value to only a spill
11873 // instruct storeI(memory mem, rRegI src)
11874 // %{
11875 // match(Set mem (StoreI mem src));
11876 // %}
11877 //
11878 // instruct loadI(rRegI dst, memory mem)
11879 // %{
11880 // match(Set dst (LoadI mem));
11881 // %}
11882 //
11883
11884 peephole
11885 %{
11886 peepmatch (loadI storeI);
11887 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11888 peepreplace (storeI(1.mem 1.mem 1.src));
11889 %}
11890
11891 peephole
11892 %{
11893 peepmatch (loadL storeL);
11894 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11895 peepreplace (storeL(1.mem 1.mem 1.src));
11896 %}
11897
11898 //----------SMARTSPILL RULES---------------------------------------------------
11899 // These must follow all instruction definitions as they use the names
11900 // defined in the instructions definitions.