1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/klass.inline.hpp"
38 #include "prims/methodHandles.hpp"
39 #include "runtime/biasedLocking.hpp"
40 #include "runtime/flags/flagSetting.hpp"
41 #include "runtime/interfaceSupport.inline.hpp"
42 #include "runtime/objectMonitor.hpp"
43 #include "runtime/os.hpp"
44 #include "runtime/safepoint.hpp"
45 #include "runtime/safepointMechanism.hpp"
46 #include "runtime/sharedRuntime.hpp"
47 #include "runtime/stubRoutines.hpp"
48 #include "runtime/thread.hpp"
49 #include "utilities/macros.hpp"
50 #include "crc32c.h"
51 #ifdef COMPILER2
52 #include "opto/intrinsicnode.hpp"
53 #endif
54
55 #ifdef PRODUCT
56 #define BLOCK_COMMENT(str) /* nothing */
57 #define STOP(error) stop(error)
58 #else
59 #define BLOCK_COMMENT(str) block_comment(str)
60 #define STOP(error) block_comment(error); stop(error)
61 #endif
62
63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
64
65 #ifdef ASSERT
66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
67 #endif
68
69 static Assembler::Condition reverse[] = {
70 Assembler::noOverflow /* overflow = 0x0 */ ,
71 Assembler::overflow /* noOverflow = 0x1 */ ,
72 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
73 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
74 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
75 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
76 Assembler::above /* belowEqual = 0x6 */ ,
77 Assembler::belowEqual /* above = 0x7 */ ,
78 Assembler::positive /* negative = 0x8 */ ,
79 Assembler::negative /* positive = 0x9 */ ,
80 Assembler::noParity /* parity = 0xa */ ,
81 Assembler::parity /* noParity = 0xb */ ,
82 Assembler::greaterEqual /* less = 0xc */ ,
83 Assembler::less /* greaterEqual = 0xd */ ,
84 Assembler::greater /* lessEqual = 0xe */ ,
85 Assembler::lessEqual /* greater = 0xf, */
86
87 };
88
89
90 // Implementation of MacroAssembler
91
92 // First all the versions that have distinct versions depending on 32/64 bit
93 // Unless the difference is trivial (1 line or so).
94
95 #ifndef _LP64
96
97 // 32bit versions
98
99 Address MacroAssembler::as_Address(AddressLiteral adr) {
100 return Address(adr.target(), adr.rspec());
101 }
102
103 Address MacroAssembler::as_Address(ArrayAddress adr) {
104 return Address::make_array(adr);
105 }
106
107 void MacroAssembler::call_VM_leaf_base(address entry_point,
108 int number_of_arguments) {
109 call(RuntimeAddress(entry_point));
110 increment(rsp, number_of_arguments * wordSize);
111 }
112
113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
114 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
115 }
116
117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
119 }
120
121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
122 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
123 }
124
125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
126 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
131 bs->obj_equals(this, src1, obj);
132 }
133
134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
136 bs->obj_equals(this, src1, obj);
137 }
138
139 void MacroAssembler::extend_sign(Register hi, Register lo) {
140 // According to Intel Doc. AP-526, "Integer Divide", p.18.
141 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
142 cdql();
143 } else {
144 movl(hi, lo);
145 sarl(hi, 31);
146 }
147 }
148
149 void MacroAssembler::jC2(Register tmp, Label& L) {
150 // set parity bit if FPU flag C2 is set (via rax)
151 save_rax(tmp);
152 fwait(); fnstsw_ax();
153 sahf();
154 restore_rax(tmp);
155 // branch
156 jcc(Assembler::parity, L);
157 }
158
159 void MacroAssembler::jnC2(Register tmp, Label& L) {
160 // set parity bit if FPU flag C2 is set (via rax)
161 save_rax(tmp);
162 fwait(); fnstsw_ax();
163 sahf();
164 restore_rax(tmp);
165 // branch
166 jcc(Assembler::noParity, L);
167 }
168
169 // 32bit can do a case table jump in one instruction but we no longer allow the base
170 // to be installed in the Address class
171 void MacroAssembler::jump(ArrayAddress entry) {
172 jmp(as_Address(entry));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj) {
309 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
310 }
311
312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
313 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
314 }
315
316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
317 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
318 }
319
320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
321 // scratch register is not used,
322 // it is defined to match parameters of 64-bit version of this method.
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
331 movl(as_Address(dst), src);
332 }
333
334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
335 movl(dst, as_Address(src));
336 }
337
338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
339 void MacroAssembler::movptr(Address dst, intptr_t src) {
340 movl(dst, src);
341 }
342
343
344 void MacroAssembler::pop_callee_saved_registers() {
345 pop(rcx);
346 pop(rdx);
347 pop(rdi);
348 pop(rsi);
349 }
350
351 void MacroAssembler::pop_fTOS() {
352 fld_d(Address(rsp, 0));
353 addl(rsp, 2 * wordSize);
354 }
355
356 void MacroAssembler::push_callee_saved_registers() {
357 push(rsi);
358 push(rdi);
359 push(rdx);
360 push(rcx);
361 }
362
363 void MacroAssembler::push_fTOS() {
364 subl(rsp, 2 * wordSize);
365 fstp_d(Address(rsp, 0));
366 }
367
368
369 void MacroAssembler::pushoop(jobject obj) {
370 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
371 }
372
373 void MacroAssembler::pushklass(Metadata* obj) {
374 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
375 }
376
377 void MacroAssembler::pushptr(AddressLiteral src) {
378 if (src.is_lval()) {
379 push_literal32((int32_t)src.target(), src.rspec());
380 } else {
381 pushl(as_Address(src));
382 }
383 }
384
385 void MacroAssembler::set_word_if_not_zero(Register dst) {
386 xorl(dst, dst);
387 set_byte_if_not_zero(dst);
388 }
389
390 static void pass_arg0(MacroAssembler* masm, Register arg) {
391 masm->push(arg);
392 }
393
394 static void pass_arg1(MacroAssembler* masm, Register arg) {
395 masm->push(arg);
396 }
397
398 static void pass_arg2(MacroAssembler* masm, Register arg) {
399 masm->push(arg);
400 }
401
402 static void pass_arg3(MacroAssembler* masm, Register arg) {
403 masm->push(arg);
404 }
405
406 #ifndef PRODUCT
407 extern "C" void findpc(intptr_t x);
408 #endif
409
410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
411 // In order to get locks to work, we need to fake a in_VM state
412 JavaThread* thread = JavaThread::current();
413 JavaThreadState saved_state = thread->thread_state();
414 thread->set_thread_state(_thread_in_vm);
415 if (ShowMessageBoxOnError) {
416 JavaThread* thread = JavaThread::current();
417 JavaThreadState saved_state = thread->thread_state();
418 thread->set_thread_state(_thread_in_vm);
419 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
420 ttyLocker ttyl;
421 BytecodeCounter::print();
422 }
423 // To see where a verify_oop failed, get $ebx+40/X for this frame.
424 // This is the value of eip which points to where verify_oop will return.
425 if (os::message_box(msg, "Execution stopped, print registers?")) {
426 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
427 BREAKPOINT;
428 }
429 } else {
430 ttyLocker ttyl;
431 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
432 }
433 // Don't assert holding the ttyLock
434 assert(false, "DEBUG MESSAGE: %s", msg);
435 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
436 }
437
438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
439 ttyLocker ttyl;
440 FlagSetting fs(Debugging, true);
441 tty->print_cr("eip = 0x%08x", eip);
442 #ifndef PRODUCT
443 if ((WizardMode || Verbose) && PrintMiscellaneous) {
444 tty->cr();
445 findpc(eip);
446 tty->cr();
447 }
448 #endif
449 #define PRINT_REG(rax) \
450 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
451 PRINT_REG(rax);
452 PRINT_REG(rbx);
453 PRINT_REG(rcx);
454 PRINT_REG(rdx);
455 PRINT_REG(rdi);
456 PRINT_REG(rsi);
457 PRINT_REG(rbp);
458 PRINT_REG(rsp);
459 #undef PRINT_REG
460 // Print some words near top of staack.
461 int* dump_sp = (int*) rsp;
462 for (int col1 = 0; col1 < 8; col1++) {
463 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
464 os::print_location(tty, *dump_sp++);
465 }
466 for (int row = 0; row < 16; row++) {
467 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
468 for (int col = 0; col < 8; col++) {
469 tty->print(" 0x%08x", *dump_sp++);
470 }
471 tty->cr();
472 }
473 // Print some instructions around pc:
474 Disassembler::decode((address)eip-64, (address)eip);
475 tty->print_cr("--------");
476 Disassembler::decode((address)eip, (address)eip+32);
477 }
478
479 void MacroAssembler::stop(const char* msg) {
480 ExternalAddress message((address)msg);
481 // push address of message
482 pushptr(message.addr());
483 { Label L; call(L, relocInfo::none); bind(L); } // push eip
484 pusha(); // push registers
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
486 hlt();
487 }
488
489 void MacroAssembler::warn(const char* msg) {
490 push_CPU_state();
491
492 ExternalAddress message((address) msg);
493 // push address of message
494 pushptr(message.addr());
495
496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
497 addl(rsp, wordSize); // discard argument
498 pop_CPU_state();
499 }
500
501 void MacroAssembler::print_state() {
502 { Label L; call(L, relocInfo::none); bind(L); } // push eip
503 pusha(); // push registers
504
505 push_CPU_state();
506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
507 pop_CPU_state();
508
509 popa();
510 addl(rsp, wordSize);
511 }
512
513 #else // _LP64
514
515 // 64 bit versions
516
517 Address MacroAssembler::as_Address(AddressLiteral adr) {
518 // amd64 always does this as a pc-rel
519 // we can be absolute or disp based on the instruction type
520 // jmp/call are displacements others are absolute
521 assert(!adr.is_lval(), "must be rval");
522 assert(reachable(adr), "must be");
523 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
524
525 }
526
527 Address MacroAssembler::as_Address(ArrayAddress adr) {
528 AddressLiteral base = adr.base();
529 lea(rscratch1, base);
530 Address index = adr.index();
531 assert(index._disp == 0, "must not have disp"); // maybe it can?
532 Address array(rscratch1, index._index, index._scale, index._disp);
533 return array;
534 }
535
536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
537 Label L, E;
538
539 #ifdef _WIN64
540 // Windows always allocates space for it's register args
541 assert(num_args <= 4, "only register arguments supported");
542 subq(rsp, frame::arg_reg_save_area_bytes);
543 #endif
544
545 // Align stack if necessary
546 testl(rsp, 15);
547 jcc(Assembler::zero, L);
548
549 subq(rsp, 8);
550 {
551 call(RuntimeAddress(entry_point));
552 }
553 addq(rsp, 8);
554 jmp(E);
555
556 bind(L);
557 {
558 call(RuntimeAddress(entry_point));
559 }
560
561 bind(E);
562
563 #ifdef _WIN64
564 // restore stack pointer
565 addq(rsp, frame::arg_reg_save_area_bytes);
566 #endif
567
568 }
569
570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
571 assert(!src2.is_lval(), "should use cmpptr");
572
573 if (reachable(src2)) {
574 cmpq(src1, as_Address(src2));
575 } else {
576 lea(rscratch1, src2);
577 Assembler::cmpq(src1, Address(rscratch1, 0));
578 }
579 }
580
581 int MacroAssembler::corrected_idivq(Register reg) {
582 // Full implementation of Java ldiv and lrem; checks for special
583 // case as described in JVM spec., p.243 & p.271. The function
584 // returns the (pc) offset of the idivl instruction - may be needed
585 // for implicit exceptions.
586 //
587 // normal case special case
588 //
589 // input : rax: dividend min_long
590 // reg: divisor (may not be eax/edx) -1
591 //
592 // output: rax: quotient (= rax idiv reg) min_long
593 // rdx: remainder (= rax irem reg) 0
594 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
595 static const int64_t min_long = 0x8000000000000000;
596 Label normal_case, special_case;
597
598 // check for special case
599 cmp64(rax, ExternalAddress((address) &min_long));
600 jcc(Assembler::notEqual, normal_case);
601 xorl(rdx, rdx); // prepare rdx for possible special case (where
602 // remainder = 0)
603 cmpq(reg, -1);
604 jcc(Assembler::equal, special_case);
605
606 // handle normal case
607 bind(normal_case);
608 cdqq();
609 int idivq_offset = offset();
610 idivq(reg);
611
612 // normal and special case exit
613 bind(special_case);
614
615 return idivq_offset;
616 }
617
618 void MacroAssembler::decrementq(Register reg, int value) {
619 if (value == min_jint) { subq(reg, value); return; }
620 if (value < 0) { incrementq(reg, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { decq(reg) ; return; }
623 /* else */ { subq(reg, value) ; return; }
624 }
625
626 void MacroAssembler::decrementq(Address dst, int value) {
627 if (value == min_jint) { subq(dst, value); return; }
628 if (value < 0) { incrementq(dst, -value); return; }
629 if (value == 0) { ; return; }
630 if (value == 1 && UseIncDec) { decq(dst) ; return; }
631 /* else */ { subq(dst, value) ; return; }
632 }
633
634 void MacroAssembler::incrementq(AddressLiteral dst) {
635 if (reachable(dst)) {
636 incrementq(as_Address(dst));
637 } else {
638 lea(rscratch1, dst);
639 incrementq(Address(rscratch1, 0));
640 }
641 }
642
643 void MacroAssembler::incrementq(Register reg, int value) {
644 if (value == min_jint) { addq(reg, value); return; }
645 if (value < 0) { decrementq(reg, -value); return; }
646 if (value == 0) { ; return; }
647 if (value == 1 && UseIncDec) { incq(reg) ; return; }
648 /* else */ { addq(reg, value) ; return; }
649 }
650
651 void MacroAssembler::incrementq(Address dst, int value) {
652 if (value == min_jint) { addq(dst, value); return; }
653 if (value < 0) { decrementq(dst, -value); return; }
654 if (value == 0) { ; return; }
655 if (value == 1 && UseIncDec) { incq(dst) ; return; }
656 /* else */ { addq(dst, value) ; return; }
657 }
658
659 // 32bit can do a case table jump in one instruction but we no longer allow the base
660 // to be installed in the Address class
661 void MacroAssembler::jump(ArrayAddress entry) {
662 lea(rscratch1, entry.base());
663 Address dispatch = entry.index();
664 assert(dispatch._base == noreg, "must be");
665 dispatch._base = rscratch1;
666 jmp(dispatch);
667 }
668
669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
670 ShouldNotReachHere(); // 64bit doesn't use two regs
671 cmpq(x_lo, y_lo);
672 }
673
674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
675 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
676 }
677
678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
679 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
680 movptr(dst, rscratch1);
681 }
682
683 void MacroAssembler::leave() {
684 // %%% is this really better? Why not on 32bit too?
685 emit_int8((unsigned char)0xC9); // LEAVE
686 }
687
688 void MacroAssembler::lneg(Register hi, Register lo) {
689 ShouldNotReachHere(); // 64bit doesn't use two regs
690 negq(lo);
691 }
692
693 void MacroAssembler::movoop(Register dst, jobject obj) {
694 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
695 }
696
697 void MacroAssembler::movoop(Address dst, jobject obj) {
698 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
699 movq(dst, rscratch1);
700 }
701
702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
703 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
704 }
705
706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
707 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
708 movq(dst, rscratch1);
709 }
710
711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
712 if (src.is_lval()) {
713 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
714 } else {
715 if (reachable(src)) {
716 movq(dst, as_Address(src));
717 } else {
718 lea(scratch, src);
719 movq(dst, Address(scratch, 0));
720 }
721 }
722 }
723
724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
725 movq(as_Address(dst), src);
726 }
727
728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
729 movq(dst, as_Address(src));
730 }
731
732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
733 void MacroAssembler::movptr(Address dst, intptr_t src) {
734 mov64(rscratch1, src);
735 movq(dst, rscratch1);
736 }
737
738 // These are mostly for initializing NULL
739 void MacroAssembler::movptr(Address dst, int32_t src) {
740 movslq(dst, src);
741 }
742
743 void MacroAssembler::movptr(Register dst, int32_t src) {
744 mov64(dst, (intptr_t)src);
745 }
746
747 void MacroAssembler::pushoop(jobject obj) {
748 movoop(rscratch1, obj);
749 push(rscratch1);
750 }
751
752 void MacroAssembler::pushklass(Metadata* obj) {
753 mov_metadata(rscratch1, obj);
754 push(rscratch1);
755 }
756
757 void MacroAssembler::pushptr(AddressLiteral src) {
758 lea(rscratch1, src);
759 if (src.is_lval()) {
760 push(rscratch1);
761 } else {
762 pushq(Address(rscratch1, 0));
763 }
764 }
765
766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
767 // we must set sp to zero to clear frame
768 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
769 // must clear fp, so that compiled frames are not confused; it is
770 // possible that we need it only for debugging
771 if (clear_fp) {
772 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
773 }
774
775 // Always clear the pc because it could have been set by make_walkable()
776 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
777 vzeroupper();
778 }
779
780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
781 Register last_java_fp,
782 address last_java_pc) {
783 vzeroupper();
784 // determine last_java_sp register
785 if (!last_java_sp->is_valid()) {
786 last_java_sp = rsp;
787 }
788
789 // last_java_fp is optional
790 if (last_java_fp->is_valid()) {
791 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
792 last_java_fp);
793 }
794
795 // last_java_pc is optional
796 if (last_java_pc != NULL) {
797 Address java_pc(r15_thread,
798 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
799 lea(rscratch1, InternalAddress(last_java_pc));
800 movptr(java_pc, rscratch1);
801 }
802
803 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
804 }
805
806 static void pass_arg0(MacroAssembler* masm, Register arg) {
807 if (c_rarg0 != arg ) {
808 masm->mov(c_rarg0, arg);
809 }
810 }
811
812 static void pass_arg1(MacroAssembler* masm, Register arg) {
813 if (c_rarg1 != arg ) {
814 masm->mov(c_rarg1, arg);
815 }
816 }
817
818 static void pass_arg2(MacroAssembler* masm, Register arg) {
819 if (c_rarg2 != arg ) {
820 masm->mov(c_rarg2, arg);
821 }
822 }
823
824 static void pass_arg3(MacroAssembler* masm, Register arg) {
825 if (c_rarg3 != arg ) {
826 masm->mov(c_rarg3, arg);
827 }
828 }
829
830 void MacroAssembler::stop(const char* msg) {
831 address rip = pc();
832 pusha(); // get regs on stack
833 lea(c_rarg0, ExternalAddress((address) msg));
834 lea(c_rarg1, InternalAddress(rip));
835 movq(c_rarg2, rsp); // pass pointer to regs array
836 andq(rsp, -16); // align stack as required by ABI
837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
838 hlt();
839 }
840
841 void MacroAssembler::warn(const char* msg) {
842 push(rbp);
843 movq(rbp, rsp);
844 andq(rsp, -16); // align stack as required by push_CPU_state and call
845 push_CPU_state(); // keeps alignment at 16 bytes
846 lea(c_rarg0, ExternalAddress((address) msg));
847 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
848 call(rax);
849 pop_CPU_state();
850 mov(rsp, rbp);
851 pop(rbp);
852 }
853
854 void MacroAssembler::print_state() {
855 address rip = pc();
856 pusha(); // get regs on stack
857 push(rbp);
858 movq(rbp, rsp);
859 andq(rsp, -16); // align stack as required by push_CPU_state and call
860 push_CPU_state(); // keeps alignment at 16 bytes
861
862 lea(c_rarg0, InternalAddress(rip));
863 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
864 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
865
866 pop_CPU_state();
867 mov(rsp, rbp);
868 pop(rbp);
869 popa();
870 }
871
872 #ifndef PRODUCT
873 extern "C" void findpc(intptr_t x);
874 #endif
875
876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
877 // In order to get locks to work, we need to fake a in_VM state
878 if (ShowMessageBoxOnError) {
879 JavaThread* thread = JavaThread::current();
880 JavaThreadState saved_state = thread->thread_state();
881 thread->set_thread_state(_thread_in_vm);
882 #ifndef PRODUCT
883 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
884 ttyLocker ttyl;
885 BytecodeCounter::print();
886 }
887 #endif
888 // To see where a verify_oop failed, get $ebx+40/X for this frame.
889 // XXX correct this offset for amd64
890 // This is the value of eip which points to where verify_oop will return.
891 if (os::message_box(msg, "Execution stopped, print registers?")) {
892 print_state64(pc, regs);
893 BREAKPOINT;
894 assert(false, "start up GDB");
895 }
896 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
897 } else {
898 ttyLocker ttyl;
899 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
900 msg);
901 assert(false, "DEBUG MESSAGE: %s", msg);
902 }
903 }
904
905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
906 ttyLocker ttyl;
907 FlagSetting fs(Debugging, true);
908 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
909 #ifndef PRODUCT
910 tty->cr();
911 findpc(pc);
912 tty->cr();
913 #endif
914 #define PRINT_REG(rax, value) \
915 { tty->print("%s = ", #rax); os::print_location(tty, value); }
916 PRINT_REG(rax, regs[15]);
917 PRINT_REG(rbx, regs[12]);
918 PRINT_REG(rcx, regs[14]);
919 PRINT_REG(rdx, regs[13]);
920 PRINT_REG(rdi, regs[8]);
921 PRINT_REG(rsi, regs[9]);
922 PRINT_REG(rbp, regs[10]);
923 PRINT_REG(rsp, regs[11]);
924 PRINT_REG(r8 , regs[7]);
925 PRINT_REG(r9 , regs[6]);
926 PRINT_REG(r10, regs[5]);
927 PRINT_REG(r11, regs[4]);
928 PRINT_REG(r12, regs[3]);
929 PRINT_REG(r13, regs[2]);
930 PRINT_REG(r14, regs[1]);
931 PRINT_REG(r15, regs[0]);
932 #undef PRINT_REG
933 // Print some words near top of staack.
934 int64_t* rsp = (int64_t*) regs[11];
935 int64_t* dump_sp = rsp;
936 for (int col1 = 0; col1 < 8; col1++) {
937 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
938 os::print_location(tty, *dump_sp++);
939 }
940 for (int row = 0; row < 25; row++) {
941 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
942 for (int col = 0; col < 4; col++) {
943 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
944 }
945 tty->cr();
946 }
947 // Print some instructions around pc:
948 Disassembler::decode((address)pc-64, (address)pc);
949 tty->print_cr("--------");
950 Disassembler::decode((address)pc, (address)pc+32);
951 }
952
953 #endif // _LP64
954
955 // Now versions that are common to 32/64 bit
956
957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
958 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
959 }
960
961 void MacroAssembler::addptr(Register dst, Register src) {
962 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
963 }
964
965 void MacroAssembler::addptr(Address dst, Register src) {
966 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
967 }
968
969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
970 if (reachable(src)) {
971 Assembler::addsd(dst, as_Address(src));
972 } else {
973 lea(rscratch1, src);
974 Assembler::addsd(dst, Address(rscratch1, 0));
975 }
976 }
977
978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
979 if (reachable(src)) {
980 addss(dst, as_Address(src));
981 } else {
982 lea(rscratch1, src);
983 addss(dst, Address(rscratch1, 0));
984 }
985 }
986
987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
988 if (reachable(src)) {
989 Assembler::addpd(dst, as_Address(src));
990 } else {
991 lea(rscratch1, src);
992 Assembler::addpd(dst, Address(rscratch1, 0));
993 }
994 }
995
996 void MacroAssembler::align(int modulus) {
997 align(modulus, offset());
998 }
999
1000 void MacroAssembler::align(int modulus, int target) {
1001 if (target % modulus != 0) {
1002 nop(modulus - (target % modulus));
1003 }
1004 }
1005
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1007 // Used in sign-masking with aligned address.
1008 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009 if (reachable(src)) {
1010 Assembler::andpd(dst, as_Address(src));
1011 } else {
1012 lea(rscratch1, src);
1013 Assembler::andpd(dst, Address(rscratch1, 0));
1014 }
1015 }
1016
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1018 // Used in sign-masking with aligned address.
1019 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020 if (reachable(src)) {
1021 Assembler::andps(dst, as_Address(src));
1022 } else {
1023 lea(rscratch1, src);
1024 Assembler::andps(dst, Address(rscratch1, 0));
1025 }
1026 }
1027
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033 if (os::is_MP())
1034 lock();
1035 incrementl(counter_addr);
1036 }
1037
1038 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1039 if (reachable(counter_addr)) {
1040 atomic_incl(as_Address(counter_addr));
1041 } else {
1042 lea(scr, counter_addr);
1043 atomic_incl(Address(scr, 0));
1044 }
1045 }
1046
1047 #ifdef _LP64
1048 void MacroAssembler::atomic_incq(Address counter_addr) {
1049 if (os::is_MP())
1050 lock();
1051 incrementq(counter_addr);
1052 }
1053
1054 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1055 if (reachable(counter_addr)) {
1056 atomic_incq(as_Address(counter_addr));
1057 } else {
1058 lea(scr, counter_addr);
1059 atomic_incq(Address(scr, 0));
1060 }
1061 }
1062 #endif
1063
1064 // Writes to stack successive pages until offset reached to check for
1065 // stack overflow + shadow pages. This clobbers tmp.
1066 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1067 movptr(tmp, rsp);
1068 // Bang stack for total size given plus shadow page size.
1069 // Bang one page at a time because large size can bang beyond yellow and
1070 // red zones.
1071 Label loop;
1072 bind(loop);
1073 movl(Address(tmp, (-os::vm_page_size())), size );
1074 subptr(tmp, os::vm_page_size());
1075 subl(size, os::vm_page_size());
1076 jcc(Assembler::greater, loop);
1077
1078 // Bang down shadow pages too.
1079 // At this point, (tmp-0) is the last address touched, so don't
1080 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1081 // was post-decremented.) Skip this address by starting at i=1, and
1082 // touch a few more pages below. N.B. It is important to touch all
1083 // the way down including all pages in the shadow zone.
1084 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1085 // this could be any sized move but this is can be a debugging crumb
1086 // so the bigger the better.
1087 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1088 }
1089 }
1090
1091 void MacroAssembler::reserved_stack_check() {
1092 // testing if reserved zone needs to be enabled
1093 Label no_reserved_zone_enabling;
1094 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1095 NOT_LP64(get_thread(rsi);)
1096
1097 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1098 jcc(Assembler::below, no_reserved_zone_enabling);
1099
1100 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1101 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1102 should_not_reach_here();
1103
1104 bind(no_reserved_zone_enabling);
1105 }
1106
1107 int MacroAssembler::biased_locking_enter(Register lock_reg,
1108 Register obj_reg,
1109 Register swap_reg,
1110 Register tmp_reg,
1111 bool swap_reg_contains_mark,
1112 Label& done,
1113 Label* slow_case,
1114 BiasedLockingCounters* counters) {
1115 assert(UseBiasedLocking, "why call this otherwise?");
1116 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1117 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1118 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1119 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1120 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1121 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1122
1123 if (PrintBiasedLockingStatistics && counters == NULL) {
1124 counters = BiasedLocking::counters();
1125 }
1126 // Biased locking
1127 // See whether the lock is currently biased toward our thread and
1128 // whether the epoch is still valid
1129 // Note that the runtime guarantees sufficient alignment of JavaThread
1130 // pointers to allow age to be placed into low bits
1131 // First check to see whether biasing is even enabled for this object
1132 Label cas_label;
1133 int null_check_offset = -1;
1134 if (!swap_reg_contains_mark) {
1135 null_check_offset = offset();
1136 movptr(swap_reg, mark_addr);
1137 }
1138 movptr(tmp_reg, swap_reg);
1139 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1140 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1141 jcc(Assembler::notEqual, cas_label);
1142 // The bias pattern is present in the object's header. Need to check
1143 // whether the bias owner and the epoch are both still current.
1144 #ifndef _LP64
1145 // Note that because there is no current thread register on x86_32 we
1146 // need to store off the mark word we read out of the object to
1147 // avoid reloading it and needing to recheck invariants below. This
1148 // store is unfortunate but it makes the overall code shorter and
1149 // simpler.
1150 movptr(saved_mark_addr, swap_reg);
1151 #endif
1152 if (swap_reg_contains_mark) {
1153 null_check_offset = offset();
1154 }
1155 load_prototype_header(tmp_reg, obj_reg);
1156 #ifdef _LP64
1157 orptr(tmp_reg, r15_thread);
1158 xorptr(tmp_reg, swap_reg);
1159 Register header_reg = tmp_reg;
1160 #else
1161 xorptr(tmp_reg, swap_reg);
1162 get_thread(swap_reg);
1163 xorptr(swap_reg, tmp_reg);
1164 Register header_reg = swap_reg;
1165 #endif
1166 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1167 if (counters != NULL) {
1168 cond_inc32(Assembler::zero,
1169 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1170 }
1171 jcc(Assembler::equal, done);
1172
1173 Label try_revoke_bias;
1174 Label try_rebias;
1175
1176 // At this point we know that the header has the bias pattern and
1177 // that we are not the bias owner in the current epoch. We need to
1178 // figure out more details about the state of the header in order to
1179 // know what operations can be legally performed on the object's
1180 // header.
1181
1182 // If the low three bits in the xor result aren't clear, that means
1183 // the prototype header is no longer biased and we have to revoke
1184 // the bias on this object.
1185 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1186 jccb(Assembler::notZero, try_revoke_bias);
1187
1188 // Biasing is still enabled for this data type. See whether the
1189 // epoch of the current bias is still valid, meaning that the epoch
1190 // bits of the mark word are equal to the epoch bits of the
1191 // prototype header. (Note that the prototype header's epoch bits
1192 // only change at a safepoint.) If not, attempt to rebias the object
1193 // toward the current thread. Note that we must be absolutely sure
1194 // that the current epoch is invalid in order to do this because
1195 // otherwise the manipulations it performs on the mark word are
1196 // illegal.
1197 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1198 jccb(Assembler::notZero, try_rebias);
1199
1200 // The epoch of the current bias is still valid but we know nothing
1201 // about the owner; it might be set or it might be clear. Try to
1202 // acquire the bias of the object using an atomic operation. If this
1203 // fails we will go in to the runtime to revoke the object's bias.
1204 // Note that we first construct the presumed unbiased header so we
1205 // don't accidentally blow away another thread's valid bias.
1206 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1207 andptr(swap_reg,
1208 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1209 #ifdef _LP64
1210 movptr(tmp_reg, swap_reg);
1211 orptr(tmp_reg, r15_thread);
1212 #else
1213 get_thread(tmp_reg);
1214 orptr(tmp_reg, swap_reg);
1215 #endif
1216 if (os::is_MP()) {
1217 lock();
1218 }
1219 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1220 // If the biasing toward our thread failed, this means that
1221 // another thread succeeded in biasing it toward itself and we
1222 // need to revoke that bias. The revocation will occur in the
1223 // interpreter runtime in the slow case.
1224 if (counters != NULL) {
1225 cond_inc32(Assembler::zero,
1226 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1227 }
1228 if (slow_case != NULL) {
1229 jcc(Assembler::notZero, *slow_case);
1230 }
1231 jmp(done);
1232
1233 bind(try_rebias);
1234 // At this point we know the epoch has expired, meaning that the
1235 // current "bias owner", if any, is actually invalid. Under these
1236 // circumstances _only_, we are allowed to use the current header's
1237 // value as the comparison value when doing the cas to acquire the
1238 // bias in the current epoch. In other words, we allow transfer of
1239 // the bias from one thread to another directly in this situation.
1240 //
1241 // FIXME: due to a lack of registers we currently blow away the age
1242 // bits in this situation. Should attempt to preserve them.
1243 load_prototype_header(tmp_reg, obj_reg);
1244 #ifdef _LP64
1245 orptr(tmp_reg, r15_thread);
1246 #else
1247 get_thread(swap_reg);
1248 orptr(tmp_reg, swap_reg);
1249 movptr(swap_reg, saved_mark_addr);
1250 #endif
1251 if (os::is_MP()) {
1252 lock();
1253 }
1254 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1255 // If the biasing toward our thread failed, then another thread
1256 // succeeded in biasing it toward itself and we need to revoke that
1257 // bias. The revocation will occur in the runtime in the slow case.
1258 if (counters != NULL) {
1259 cond_inc32(Assembler::zero,
1260 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1261 }
1262 if (slow_case != NULL) {
1263 jcc(Assembler::notZero, *slow_case);
1264 }
1265 jmp(done);
1266
1267 bind(try_revoke_bias);
1268 // The prototype mark in the klass doesn't have the bias bit set any
1269 // more, indicating that objects of this data type are not supposed
1270 // to be biased any more. We are going to try to reset the mark of
1271 // this object to the prototype value and fall through to the
1272 // CAS-based locking scheme. Note that if our CAS fails, it means
1273 // that another thread raced us for the privilege of revoking the
1274 // bias of this particular object, so it's okay to continue in the
1275 // normal locking code.
1276 //
1277 // FIXME: due to a lack of registers we currently blow away the age
1278 // bits in this situation. Should attempt to preserve them.
1279 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1280 load_prototype_header(tmp_reg, obj_reg);
1281 if (os::is_MP()) {
1282 lock();
1283 }
1284 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1285 // Fall through to the normal CAS-based lock, because no matter what
1286 // the result of the above CAS, some thread must have succeeded in
1287 // removing the bias bit from the object's header.
1288 if (counters != NULL) {
1289 cond_inc32(Assembler::zero,
1290 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1291 }
1292
1293 bind(cas_label);
1294
1295 return null_check_offset;
1296 }
1297
1298 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1299 assert(UseBiasedLocking, "why call this otherwise?");
1300
1301 // Check for biased locking unlock case, which is a no-op
1302 // Note: we do not have to check the thread ID for two reasons.
1303 // First, the interpreter checks for IllegalMonitorStateException at
1304 // a higher level. Second, if the bias was revoked while we held the
1305 // lock, the object could not be rebiased toward another thread, so
1306 // the bias bit would be clear.
1307 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1308 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1309 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1310 jcc(Assembler::equal, done);
1311 }
1312
1313 #ifdef COMPILER2
1314
1315 #if INCLUDE_RTM_OPT
1316
1317 // Update rtm_counters based on abort status
1318 // input: abort_status
1319 // rtm_counters (RTMLockingCounters*)
1320 // flags are killed
1321 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1322
1323 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1324 if (PrintPreciseRTMLockingStatistics) {
1325 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1326 Label check_abort;
1327 testl(abort_status, (1<<i));
1328 jccb(Assembler::equal, check_abort);
1329 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1330 bind(check_abort);
1331 }
1332 }
1333 }
1334
1335 // Branch if (random & (count-1) != 0), count is 2^n
1336 // tmp, scr and flags are killed
1337 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1338 assert(tmp == rax, "");
1339 assert(scr == rdx, "");
1340 rdtsc(); // modifies EDX:EAX
1341 andptr(tmp, count-1);
1342 jccb(Assembler::notZero, brLabel);
1343 }
1344
1345 // Perform abort ratio calculation, set no_rtm bit if high ratio
1346 // input: rtm_counters_Reg (RTMLockingCounters* address)
1347 // tmpReg, rtm_counters_Reg and flags are killed
1348 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1349 Register rtm_counters_Reg,
1350 RTMLockingCounters* rtm_counters,
1351 Metadata* method_data) {
1352 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1353
1354 if (RTMLockingCalculationDelay > 0) {
1355 // Delay calculation
1356 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1357 testptr(tmpReg, tmpReg);
1358 jccb(Assembler::equal, L_done);
1359 }
1360 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1361 // Aborted transactions = abort_count * 100
1362 // All transactions = total_count * RTMTotalCountIncrRate
1363 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1364
1365 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1366 cmpptr(tmpReg, RTMAbortThreshold);
1367 jccb(Assembler::below, L_check_always_rtm2);
1368 imulptr(tmpReg, tmpReg, 100);
1369
1370 Register scrReg = rtm_counters_Reg;
1371 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1373 imulptr(scrReg, scrReg, RTMAbortRatio);
1374 cmpptr(tmpReg, scrReg);
1375 jccb(Assembler::below, L_check_always_rtm1);
1376 if (method_data != NULL) {
1377 // set rtm_state to "no rtm" in MDO
1378 mov_metadata(tmpReg, method_data);
1379 if (os::is_MP()) {
1380 lock();
1381 }
1382 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1383 }
1384 jmpb(L_done);
1385 bind(L_check_always_rtm1);
1386 // Reload RTMLockingCounters* address
1387 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1388 bind(L_check_always_rtm2);
1389 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1390 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1391 jccb(Assembler::below, L_done);
1392 if (method_data != NULL) {
1393 // set rtm_state to "always rtm" in MDO
1394 mov_metadata(tmpReg, method_data);
1395 if (os::is_MP()) {
1396 lock();
1397 }
1398 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1399 }
1400 bind(L_done);
1401 }
1402
1403 // Update counters and perform abort ratio calculation
1404 // input: abort_status_Reg
1405 // rtm_counters_Reg, flags are killed
1406 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1407 Register rtm_counters_Reg,
1408 RTMLockingCounters* rtm_counters,
1409 Metadata* method_data,
1410 bool profile_rtm) {
1411
1412 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1413 // update rtm counters based on rax value at abort
1414 // reads abort_status_Reg, updates flags
1415 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1416 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1417 if (profile_rtm) {
1418 // Save abort status because abort_status_Reg is used by following code.
1419 if (RTMRetryCount > 0) {
1420 push(abort_status_Reg);
1421 }
1422 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1423 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1424 // restore abort status
1425 if (RTMRetryCount > 0) {
1426 pop(abort_status_Reg);
1427 }
1428 }
1429 }
1430
1431 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1432 // inputs: retry_count_Reg
1433 // : abort_status_Reg
1434 // output: retry_count_Reg decremented by 1
1435 // flags are killed
1436 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1437 Label doneRetry;
1438 assert(abort_status_Reg == rax, "");
1439 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1440 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1441 // if reason is in 0x6 and retry count != 0 then retry
1442 andptr(abort_status_Reg, 0x6);
1443 jccb(Assembler::zero, doneRetry);
1444 testl(retry_count_Reg, retry_count_Reg);
1445 jccb(Assembler::zero, doneRetry);
1446 pause();
1447 decrementl(retry_count_Reg);
1448 jmp(retryLabel);
1449 bind(doneRetry);
1450 }
1451
1452 // Spin and retry if lock is busy,
1453 // inputs: box_Reg (monitor address)
1454 // : retry_count_Reg
1455 // output: retry_count_Reg decremented by 1
1456 // : clear z flag if retry count exceeded
1457 // tmp_Reg, scr_Reg, flags are killed
1458 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1459 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1460 Label SpinLoop, SpinExit, doneRetry;
1461 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1462
1463 testl(retry_count_Reg, retry_count_Reg);
1464 jccb(Assembler::zero, doneRetry);
1465 decrementl(retry_count_Reg);
1466 movptr(scr_Reg, RTMSpinLoopCount);
1467
1468 bind(SpinLoop);
1469 pause();
1470 decrementl(scr_Reg);
1471 jccb(Assembler::lessEqual, SpinExit);
1472 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1473 testptr(tmp_Reg, tmp_Reg);
1474 jccb(Assembler::notZero, SpinLoop);
1475
1476 bind(SpinExit);
1477 jmp(retryLabel);
1478 bind(doneRetry);
1479 incrementl(retry_count_Reg); // clear z flag
1480 }
1481
1482 // Use RTM for normal stack locks
1483 // Input: objReg (object to lock)
1484 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1485 Register retry_on_abort_count_Reg,
1486 RTMLockingCounters* stack_rtm_counters,
1487 Metadata* method_data, bool profile_rtm,
1488 Label& DONE_LABEL, Label& IsInflated) {
1489 assert(UseRTMForStackLocks, "why call this otherwise?");
1490 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1491 assert(tmpReg == rax, "");
1492 assert(scrReg == rdx, "");
1493 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1494
1495 if (RTMRetryCount > 0) {
1496 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1497 bind(L_rtm_retry);
1498 }
1499 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1500 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1501 jcc(Assembler::notZero, IsInflated);
1502
1503 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1504 Label L_noincrement;
1505 if (RTMTotalCountIncrRate > 1) {
1506 // tmpReg, scrReg and flags are killed
1507 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1508 }
1509 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1510 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1511 bind(L_noincrement);
1512 }
1513 xbegin(L_on_abort);
1514 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1515 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1516 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1517 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1518
1519 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1520 if (UseRTMXendForLockBusy) {
1521 xend();
1522 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1523 jmp(L_decrement_retry);
1524 }
1525 else {
1526 xabort(0);
1527 }
1528 bind(L_on_abort);
1529 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1530 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1531 }
1532 bind(L_decrement_retry);
1533 if (RTMRetryCount > 0) {
1534 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1535 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1536 }
1537 }
1538
1539 // Use RTM for inflating locks
1540 // inputs: objReg (object to lock)
1541 // boxReg (on-stack box address (displaced header location) - KILLED)
1542 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1543 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1544 Register scrReg, Register retry_on_busy_count_Reg,
1545 Register retry_on_abort_count_Reg,
1546 RTMLockingCounters* rtm_counters,
1547 Metadata* method_data, bool profile_rtm,
1548 Label& DONE_LABEL) {
1549 assert(UseRTMLocking, "why call this otherwise?");
1550 assert(tmpReg == rax, "");
1551 assert(scrReg == rdx, "");
1552 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1553 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1554
1555 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1556 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1557 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1558
1559 if (RTMRetryCount > 0) {
1560 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1561 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1562 bind(L_rtm_retry);
1563 }
1564 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1565 Label L_noincrement;
1566 if (RTMTotalCountIncrRate > 1) {
1567 // tmpReg, scrReg and flags are killed
1568 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1569 }
1570 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1571 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1572 bind(L_noincrement);
1573 }
1574 xbegin(L_on_abort);
1575 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1576 movptr(tmpReg, Address(tmpReg, owner_offset));
1577 testptr(tmpReg, tmpReg);
1578 jcc(Assembler::zero, DONE_LABEL);
1579 if (UseRTMXendForLockBusy) {
1580 xend();
1581 jmp(L_decrement_retry);
1582 }
1583 else {
1584 xabort(0);
1585 }
1586 bind(L_on_abort);
1587 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1588 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1589 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1590 }
1591 if (RTMRetryCount > 0) {
1592 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1593 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1594 }
1595
1596 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1597 testptr(tmpReg, tmpReg) ;
1598 jccb(Assembler::notZero, L_decrement_retry) ;
1599
1600 // Appears unlocked - try to swing _owner from null to non-null.
1601 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1602 #ifdef _LP64
1603 Register threadReg = r15_thread;
1604 #else
1605 get_thread(scrReg);
1606 Register threadReg = scrReg;
1607 #endif
1608 if (os::is_MP()) {
1609 lock();
1610 }
1611 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1612
1613 if (RTMRetryCount > 0) {
1614 // success done else retry
1615 jccb(Assembler::equal, DONE_LABEL) ;
1616 bind(L_decrement_retry);
1617 // Spin and retry if lock is busy.
1618 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1619 }
1620 else {
1621 bind(L_decrement_retry);
1622 }
1623 }
1624
1625 #endif // INCLUDE_RTM_OPT
1626
1627 // Fast_Lock and Fast_Unlock used by C2
1628
1629 // Because the transitions from emitted code to the runtime
1630 // monitorenter/exit helper stubs are so slow it's critical that
1631 // we inline both the stack-locking fast-path and the inflated fast path.
1632 //
1633 // See also: cmpFastLock and cmpFastUnlock.
1634 //
1635 // What follows is a specialized inline transliteration of the code
1636 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1637 // another option would be to emit TrySlowEnter and TrySlowExit methods
1638 // at startup-time. These methods would accept arguments as
1639 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1640 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1641 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1642 // In practice, however, the # of lock sites is bounded and is usually small.
1643 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1644 // if the processor uses simple bimodal branch predictors keyed by EIP
1645 // Since the helper routines would be called from multiple synchronization
1646 // sites.
1647 //
1648 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1649 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1650 // to those specialized methods. That'd give us a mostly platform-independent
1651 // implementation that the JITs could optimize and inline at their pleasure.
1652 // Done correctly, the only time we'd need to cross to native could would be
1653 // to park() or unpark() threads. We'd also need a few more unsafe operators
1654 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1655 // (b) explicit barriers or fence operations.
1656 //
1657 // TODO:
1658 //
1659 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1660 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1661 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1662 // the lock operators would typically be faster than reifying Self.
1663 //
1664 // * Ideally I'd define the primitives as:
1665 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1666 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1667 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1668 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1669 // Furthermore the register assignments are overconstrained, possibly resulting in
1670 // sub-optimal code near the synchronization site.
1671 //
1672 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1673 // Alternately, use a better sp-proximity test.
1674 //
1675 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1676 // Either one is sufficient to uniquely identify a thread.
1677 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1678 //
1679 // * Intrinsify notify() and notifyAll() for the common cases where the
1680 // object is locked by the calling thread but the waitlist is empty.
1681 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1682 //
1683 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1684 // But beware of excessive branch density on AMD Opterons.
1685 //
1686 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1687 // or failure of the fast-path. If the fast-path fails then we pass
1688 // control to the slow-path, typically in C. In Fast_Lock and
1689 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1690 // will emit a conditional branch immediately after the node.
1691 // So we have branches to branches and lots of ICC.ZF games.
1692 // Instead, it might be better to have C2 pass a "FailureLabel"
1693 // into Fast_Lock and Fast_Unlock. In the case of success, control
1694 // will drop through the node. ICC.ZF is undefined at exit.
1695 // In the case of failure, the node will branch directly to the
1696 // FailureLabel
1697
1698
1699 // obj: object to lock
1700 // box: on-stack box address (displaced header location) - KILLED
1701 // rax,: tmp -- KILLED
1702 // scr: tmp -- KILLED
1703 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1704 Register scrReg, Register cx1Reg, Register cx2Reg,
1705 BiasedLockingCounters* counters,
1706 RTMLockingCounters* rtm_counters,
1707 RTMLockingCounters* stack_rtm_counters,
1708 Metadata* method_data,
1709 bool use_rtm, bool profile_rtm) {
1710 // Ensure the register assignments are disjoint
1711 assert(tmpReg == rax, "");
1712
1713 if (use_rtm) {
1714 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1715 } else {
1716 assert(cx1Reg == noreg, "");
1717 assert(cx2Reg == noreg, "");
1718 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1719 }
1720
1721 if (counters != NULL) {
1722 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1723 }
1724 if (EmitSync & 1) {
1725 // set box->dhw = markOopDesc::unused_mark()
1726 // Force all sync thru slow-path: slow_enter() and slow_exit()
1727 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1728 cmpptr (rsp, (int32_t)NULL_WORD);
1729 } else {
1730 // Possible cases that we'll encounter in fast_lock
1731 // ------------------------------------------------
1732 // * Inflated
1733 // -- unlocked
1734 // -- Locked
1735 // = by self
1736 // = by other
1737 // * biased
1738 // -- by Self
1739 // -- by other
1740 // * neutral
1741 // * stack-locked
1742 // -- by self
1743 // = sp-proximity test hits
1744 // = sp-proximity test generates false-negative
1745 // -- by other
1746 //
1747
1748 Label IsInflated, DONE_LABEL;
1749
1750 // it's stack-locked, biased or neutral
1751 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1752 // order to reduce the number of conditional branches in the most common cases.
1753 // Beware -- there's a subtle invariant that fetch of the markword
1754 // at [FETCH], below, will never observe a biased encoding (*101b).
1755 // If this invariant is not held we risk exclusion (safety) failure.
1756 if (UseBiasedLocking && !UseOptoBiasInlining) {
1757 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1758 }
1759
1760 #if INCLUDE_RTM_OPT
1761 if (UseRTMForStackLocks && use_rtm) {
1762 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1763 stack_rtm_counters, method_data, profile_rtm,
1764 DONE_LABEL, IsInflated);
1765 }
1766 #endif // INCLUDE_RTM_OPT
1767
1768 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1769 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1770 jccb(Assembler::notZero, IsInflated);
1771
1772 // Attempt stack-locking ...
1773 orptr (tmpReg, markOopDesc::unlocked_value);
1774 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1775 if (os::is_MP()) {
1776 lock();
1777 }
1778 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1779 if (counters != NULL) {
1780 cond_inc32(Assembler::equal,
1781 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1782 }
1783 jcc(Assembler::equal, DONE_LABEL); // Success
1784
1785 // Recursive locking.
1786 // The object is stack-locked: markword contains stack pointer to BasicLock.
1787 // Locked by current thread if difference with current SP is less than one page.
1788 subptr(tmpReg, rsp);
1789 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1790 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1791 movptr(Address(boxReg, 0), tmpReg);
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jmp(DONE_LABEL);
1797
1798 bind(IsInflated);
1799 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1800
1801 #if INCLUDE_RTM_OPT
1802 // Use the same RTM locking code in 32- and 64-bit VM.
1803 if (use_rtm) {
1804 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1805 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1806 } else {
1807 #endif // INCLUDE_RTM_OPT
1808
1809 #ifndef _LP64
1810 // The object is inflated.
1811
1812 // boxReg refers to the on-stack BasicLock in the current frame.
1813 // We'd like to write:
1814 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1815 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1816 // additional latency as we have another ST in the store buffer that must drain.
1817
1818 if (EmitSync & 8192) {
1819 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1820 get_thread (scrReg);
1821 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1822 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1823 if (os::is_MP()) {
1824 lock();
1825 }
1826 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1827 } else
1828 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1829 // register juggle because we need tmpReg for cmpxchgptr below
1830 movptr(scrReg, boxReg);
1831 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1832
1833 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1834 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1835 // prefetchw [eax + Offset(_owner)-2]
1836 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1837 }
1838
1839 if ((EmitSync & 64) == 0) {
1840 // Optimistic form: consider XORL tmpReg,tmpReg
1841 movptr(tmpReg, NULL_WORD);
1842 } else {
1843 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1844 // Test-And-CAS instead of CAS
1845 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1846 testptr(tmpReg, tmpReg); // Locked ?
1847 jccb (Assembler::notZero, DONE_LABEL);
1848 }
1849
1850 // Appears unlocked - try to swing _owner from null to non-null.
1851 // Ideally, I'd manifest "Self" with get_thread and then attempt
1852 // to CAS the register containing Self into m->Owner.
1853 // But we don't have enough registers, so instead we can either try to CAS
1854 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1855 // we later store "Self" into m->Owner. Transiently storing a stack address
1856 // (rsp or the address of the box) into m->owner is harmless.
1857 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1858 if (os::is_MP()) {
1859 lock();
1860 }
1861 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1862 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1863 // If we weren't able to swing _owner from NULL to the BasicLock
1864 // then take the slow path.
1865 jccb (Assembler::notZero, DONE_LABEL);
1866 // update _owner from BasicLock to thread
1867 get_thread (scrReg); // beware: clobbers ICCs
1868 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1869 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1870
1871 // If the CAS fails we can either retry or pass control to the slow-path.
1872 // We use the latter tactic.
1873 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1874 // If the CAS was successful ...
1875 // Self has acquired the lock
1876 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1877 // Intentional fall-through into DONE_LABEL ...
1878 } else {
1879 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1880 movptr(boxReg, tmpReg);
1881
1882 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1883 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1884 // prefetchw [eax + Offset(_owner)-2]
1885 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1886 }
1887
1888 if ((EmitSync & 64) == 0) {
1889 // Optimistic form
1890 xorptr (tmpReg, tmpReg);
1891 } else {
1892 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1893 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1894 testptr(tmpReg, tmpReg); // Locked ?
1895 jccb (Assembler::notZero, DONE_LABEL);
1896 }
1897
1898 // Appears unlocked - try to swing _owner from null to non-null.
1899 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1900 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1901 get_thread (scrReg);
1902 if (os::is_MP()) {
1903 lock();
1904 }
1905 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1906
1907 // If the CAS fails we can either retry or pass control to the slow-path.
1908 // We use the latter tactic.
1909 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1910 // If the CAS was successful ...
1911 // Self has acquired the lock
1912 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1913 // Intentional fall-through into DONE_LABEL ...
1914 }
1915 #else // _LP64
1916 // It's inflated
1917 movq(scrReg, tmpReg);
1918 xorq(tmpReg, tmpReg);
1919
1920 if (os::is_MP()) {
1921 lock();
1922 }
1923 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1924 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1925 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1926 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1927 // Intentional fall-through into DONE_LABEL ...
1928 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1929 #endif // _LP64
1930 #if INCLUDE_RTM_OPT
1931 } // use_rtm()
1932 #endif
1933 // DONE_LABEL is a hot target - we'd really like to place it at the
1934 // start of cache line by padding with NOPs.
1935 // See the AMD and Intel software optimization manuals for the
1936 // most efficient "long" NOP encodings.
1937 // Unfortunately none of our alignment mechanisms suffice.
1938 bind(DONE_LABEL);
1939
1940 // At DONE_LABEL the icc ZFlag is set as follows ...
1941 // Fast_Unlock uses the same protocol.
1942 // ZFlag == 1 -> Success
1943 // ZFlag == 0 -> Failure - force control through the slow-path
1944 }
1945 }
1946
1947 // obj: object to unlock
1948 // box: box address (displaced header location), killed. Must be EAX.
1949 // tmp: killed, cannot be obj nor box.
1950 //
1951 // Some commentary on balanced locking:
1952 //
1953 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1954 // Methods that don't have provably balanced locking are forced to run in the
1955 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1956 // The interpreter provides two properties:
1957 // I1: At return-time the interpreter automatically and quietly unlocks any
1958 // objects acquired the current activation (frame). Recall that the
1959 // interpreter maintains an on-stack list of locks currently held by
1960 // a frame.
1961 // I2: If a method attempts to unlock an object that is not held by the
1962 // the frame the interpreter throws IMSX.
1963 //
1964 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1965 // B() doesn't have provably balanced locking so it runs in the interpreter.
1966 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1967 // is still locked by A().
1968 //
1969 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1970 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1971 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1972 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1973 // Arguably given that the spec legislates the JNI case as undefined our implementation
1974 // could reasonably *avoid* checking owner in Fast_Unlock().
1975 // In the interest of performance we elide m->Owner==Self check in unlock.
1976 // A perfectly viable alternative is to elide the owner check except when
1977 // Xcheck:jni is enabled.
1978
1979 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1980 assert(boxReg == rax, "");
1981 assert_different_registers(objReg, boxReg, tmpReg);
1982
1983 if (EmitSync & 4) {
1984 // Disable - inhibit all inlining. Force control through the slow-path
1985 cmpptr (rsp, 0);
1986 } else {
1987 Label DONE_LABEL, Stacked, CheckSucc;
1988
1989 // Critically, the biased locking test must have precedence over
1990 // and appear before the (box->dhw == 0) recursive stack-lock test.
1991 if (UseBiasedLocking && !UseOptoBiasInlining) {
1992 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1993 }
1994
1995 #if INCLUDE_RTM_OPT
1996 if (UseRTMForStackLocks && use_rtm) {
1997 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1998 Label L_regular_unlock;
1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
2000 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2001 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2002 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2003 xend(); // otherwise end...
2004 jmp(DONE_LABEL); // ... and we're done
2005 bind(L_regular_unlock);
2006 }
2007 #endif
2008
2009 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2010 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2011 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2012 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2013 jccb (Assembler::zero, Stacked);
2014
2015 // It's inflated.
2016 #if INCLUDE_RTM_OPT
2017 if (use_rtm) {
2018 Label L_regular_inflated_unlock;
2019 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2020 movptr(boxReg, Address(tmpReg, owner_offset));
2021 testptr(boxReg, boxReg);
2022 jccb(Assembler::notZero, L_regular_inflated_unlock);
2023 xend();
2024 jmpb(DONE_LABEL);
2025 bind(L_regular_inflated_unlock);
2026 }
2027 #endif
2028
2029 // Despite our balanced locking property we still check that m->_owner == Self
2030 // as java routines or native JNI code called by this thread might
2031 // have released the lock.
2032 // Refer to the comments in synchronizer.cpp for how we might encode extra
2033 // state in _succ so we can avoid fetching EntryList|cxq.
2034 //
2035 // I'd like to add more cases in fast_lock() and fast_unlock() --
2036 // such as recursive enter and exit -- but we have to be wary of
2037 // I$ bloat, T$ effects and BP$ effects.
2038 //
2039 // If there's no contention try a 1-0 exit. That is, exit without
2040 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2041 // we detect and recover from the race that the 1-0 exit admits.
2042 //
2043 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2044 // before it STs null into _owner, releasing the lock. Updates
2045 // to data protected by the critical section must be visible before
2046 // we drop the lock (and thus before any other thread could acquire
2047 // the lock and observe the fields protected by the lock).
2048 // IA32's memory-model is SPO, so STs are ordered with respect to
2049 // each other and there's no need for an explicit barrier (fence).
2050 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2051 #ifndef _LP64
2052 get_thread (boxReg);
2053 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2054 // prefetchw [ebx + Offset(_owner)-2]
2055 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2056 }
2057
2058 // Note that we could employ various encoding schemes to reduce
2059 // the number of loads below (currently 4) to just 2 or 3.
2060 // Refer to the comments in synchronizer.cpp.
2061 // In practice the chain of fetches doesn't seem to impact performance, however.
2062 xorptr(boxReg, boxReg);
2063 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2064 // Attempt to reduce branch density - AMD's branch predictor.
2065 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2067 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2068 jccb (Assembler::notZero, DONE_LABEL);
2069 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2070 jmpb (DONE_LABEL);
2071 } else {
2072 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2073 jccb (Assembler::notZero, DONE_LABEL);
2074 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2075 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2076 jccb (Assembler::notZero, CheckSucc);
2077 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2078 jmpb (DONE_LABEL);
2079 }
2080
2081 // The Following code fragment (EmitSync & 65536) improves the performance of
2082 // contended applications and contended synchronization microbenchmarks.
2083 // Unfortunately the emission of the code - even though not executed - causes regressions
2084 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2085 // with an equal number of never-executed NOPs results in the same regression.
2086 // We leave it off by default.
2087
2088 if ((EmitSync & 65536) != 0) {
2089 Label LSuccess, LGoSlowPath ;
2090
2091 bind (CheckSucc);
2092
2093 // Optional pre-test ... it's safe to elide this
2094 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2095 jccb(Assembler::zero, LGoSlowPath);
2096
2097 // We have a classic Dekker-style idiom:
2098 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2099 // There are a number of ways to implement the barrier:
2100 // (1) lock:andl &m->_owner, 0
2101 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2102 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2103 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2104 // (2) If supported, an explicit MFENCE is appealing.
2105 // In older IA32 processors MFENCE is slower than lock:add or xchg
2106 // particularly if the write-buffer is full as might be the case if
2107 // if stores closely precede the fence or fence-equivalent instruction.
2108 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2109 // as the situation has changed with Nehalem and Shanghai.
2110 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2111 // The $lines underlying the top-of-stack should be in M-state.
2112 // The locked add instruction is serializing, of course.
2113 // (4) Use xchg, which is serializing
2114 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2115 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2116 // The integer condition codes will tell us if succ was 0.
2117 // Since _succ and _owner should reside in the same $line and
2118 // we just stored into _owner, it's likely that the $line
2119 // remains in M-state for the lock:orl.
2120 //
2121 // We currently use (3), although it's likely that switching to (2)
2122 // is correct for the future.
2123
2124 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2125 if (os::is_MP()) {
2126 lock(); addptr(Address(rsp, 0), 0);
2127 }
2128 // Ratify _succ remains non-null
2129 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2130 jccb (Assembler::notZero, LSuccess);
2131
2132 xorptr(boxReg, boxReg); // box is really EAX
2133 if (os::is_MP()) { lock(); }
2134 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2135 // There's no successor so we tried to regrab the lock with the
2136 // placeholder value. If that didn't work, then another thread
2137 // grabbed the lock so we're done (and exit was a success).
2138 jccb (Assembler::notEqual, LSuccess);
2139 // Since we're low on registers we installed rsp as a placeholding in _owner.
2140 // Now install Self over rsp. This is safe as we're transitioning from
2141 // non-null to non=null
2142 get_thread (boxReg);
2143 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2144 // Intentional fall-through into LGoSlowPath ...
2145
2146 bind (LGoSlowPath);
2147 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2148 jmpb (DONE_LABEL);
2149
2150 bind (LSuccess);
2151 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2152 jmpb (DONE_LABEL);
2153 }
2154
2155 bind (Stacked);
2156 // It's not inflated and it's not recursively stack-locked and it's not biased.
2157 // It must be stack-locked.
2158 // Try to reset the header to displaced header.
2159 // The "box" value on the stack is stable, so we can reload
2160 // and be assured we observe the same value as above.
2161 movptr(tmpReg, Address(boxReg, 0));
2162 if (os::is_MP()) {
2163 lock();
2164 }
2165 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2166 // Intention fall-thru into DONE_LABEL
2167
2168 // DONE_LABEL is a hot target - we'd really like to place it at the
2169 // start of cache line by padding with NOPs.
2170 // See the AMD and Intel software optimization manuals for the
2171 // most efficient "long" NOP encodings.
2172 // Unfortunately none of our alignment mechanisms suffice.
2173 if ((EmitSync & 65536) == 0) {
2174 bind (CheckSucc);
2175 }
2176 #else // _LP64
2177 // It's inflated
2178 if (EmitSync & 1024) {
2179 // Emit code to check that _owner == Self
2180 // We could fold the _owner test into subsequent code more efficiently
2181 // than using a stand-alone check, but since _owner checking is off by
2182 // default we don't bother. We also might consider predicating the
2183 // _owner==Self check on Xcheck:jni or running on a debug build.
2184 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2185 xorptr(boxReg, r15_thread);
2186 } else {
2187 xorptr(boxReg, boxReg);
2188 }
2189 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2190 jccb (Assembler::notZero, DONE_LABEL);
2191 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2192 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2193 jccb (Assembler::notZero, CheckSucc);
2194 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2195 jmpb (DONE_LABEL);
2196
2197 if ((EmitSync & 65536) == 0) {
2198 // Try to avoid passing control into the slow_path ...
2199 Label LSuccess, LGoSlowPath ;
2200 bind (CheckSucc);
2201
2202 // The following optional optimization can be elided if necessary
2203 // Effectively: if (succ == null) goto SlowPath
2204 // The code reduces the window for a race, however,
2205 // and thus benefits performance.
2206 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2207 jccb (Assembler::zero, LGoSlowPath);
2208
2209 xorptr(boxReg, boxReg);
2210 if ((EmitSync & 16) && os::is_MP()) {
2211 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2212 } else {
2213 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2214 if (os::is_MP()) {
2215 // Memory barrier/fence
2216 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2217 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2218 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2219 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2220 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2221 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2222 lock(); addl(Address(rsp, 0), 0);
2223 }
2224 }
2225 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2226 jccb (Assembler::notZero, LSuccess);
2227
2228 // Rare inopportune interleaving - race.
2229 // The successor vanished in the small window above.
2230 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2231 // We need to ensure progress and succession.
2232 // Try to reacquire the lock.
2233 // If that fails then the new owner is responsible for succession and this
2234 // thread needs to take no further action and can exit via the fast path (success).
2235 // If the re-acquire succeeds then pass control into the slow path.
2236 // As implemented, this latter mode is horrible because we generated more
2237 // coherence traffic on the lock *and* artifically extended the critical section
2238 // length while by virtue of passing control into the slow path.
2239
2240 // box is really RAX -- the following CMPXCHG depends on that binding
2241 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2242 if (os::is_MP()) { lock(); }
2243 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2244 // There's no successor so we tried to regrab the lock.
2245 // If that didn't work, then another thread grabbed the
2246 // lock so we're done (and exit was a success).
2247 jccb (Assembler::notEqual, LSuccess);
2248 // Intentional fall-through into slow-path
2249
2250 bind (LGoSlowPath);
2251 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2252 jmpb (DONE_LABEL);
2253
2254 bind (LSuccess);
2255 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2256 jmpb (DONE_LABEL);
2257 }
2258
2259 bind (Stacked);
2260 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2261 if (os::is_MP()) { lock(); }
2262 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2263
2264 if (EmitSync & 65536) {
2265 bind (CheckSucc);
2266 }
2267 #endif
2268 bind(DONE_LABEL);
2269 }
2270 }
2271 #endif // COMPILER2
2272
2273 void MacroAssembler::c2bool(Register x) {
2274 // implements x == 0 ? 0 : 1
2275 // note: must only look at least-significant byte of x
2276 // since C-style booleans are stored in one byte
2277 // only! (was bug)
2278 andl(x, 0xFF);
2279 setb(Assembler::notZero, x);
2280 }
2281
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284 Assembler::call(L, rtype);
2285 }
2286
2287 void MacroAssembler::call(Register entry) {
2288 Assembler::call(entry);
2289 }
2290
2291 void MacroAssembler::call(AddressLiteral entry) {
2292 if (reachable(entry)) {
2293 Assembler::call_literal(entry.target(), entry.rspec());
2294 } else {
2295 lea(rscratch1, entry);
2296 Assembler::call(rscratch1);
2297 }
2298 }
2299
2300 void MacroAssembler::ic_call(address entry, jint method_index) {
2301 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2302 movptr(rax, (intptr_t)Universe::non_oop_word());
2303 call(AddressLiteral(entry, rh));
2304 }
2305
2306 // Implementation of call_VM versions
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 bool check_exceptions) {
2311 Label C, E;
2312 call(C, relocInfo::none);
2313 jmp(E);
2314
2315 bind(C);
2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317 ret(0);
2318
2319 bind(E);
2320 }
2321
2322 void MacroAssembler::call_VM(Register oop_result,
2323 address entry_point,
2324 Register arg_1,
2325 bool check_exceptions) {
2326 Label C, E;
2327 call(C, relocInfo::none);
2328 jmp(E);
2329
2330 bind(C);
2331 pass_arg1(this, arg_1);
2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 Register arg_2,
2342 bool check_exceptions) {
2343 Label C, E;
2344 call(C, relocInfo::none);
2345 jmp(E);
2346
2347 bind(C);
2348
2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350
2351 pass_arg2(this, arg_2);
2352 pass_arg1(this, arg_1);
2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354 ret(0);
2355
2356 bind(E);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 address entry_point,
2361 Register arg_1,
2362 Register arg_2,
2363 Register arg_3,
2364 bool check_exceptions) {
2365 Label C, E;
2366 call(C, relocInfo::none);
2367 jmp(E);
2368
2369 bind(C);
2370
2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373 pass_arg3(this, arg_3);
2374
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377
2378 pass_arg1(this, arg_1);
2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380 ret(0);
2381
2382 bind(E);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 int number_of_arguments,
2389 bool check_exceptions) {
2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 bool check_exceptions) {
2399 pass_arg1(this, arg_1);
2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 Register arg_2,
2408 bool check_exceptions) {
2409
2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411 pass_arg2(this, arg_2);
2412 pass_arg1(this, arg_1);
2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415
2416 void MacroAssembler::call_VM(Register oop_result,
2417 Register last_java_sp,
2418 address entry_point,
2419 Register arg_1,
2420 Register arg_2,
2421 Register arg_3,
2422 bool check_exceptions) {
2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425 pass_arg3(this, arg_3);
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 int number_of_arguments,
2436 bool check_exceptions) {
2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 bool check_exceptions) {
2446 pass_arg1(this, arg_1);
2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 Register arg_1,
2454 Register arg_2,
2455 bool check_exceptions) {
2456
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 pass_arg1(this, arg_1);
2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464 Register last_java_sp,
2465 address entry_point,
2466 Register arg_1,
2467 Register arg_2,
2468 Register arg_3,
2469 bool check_exceptions) {
2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472 pass_arg3(this, arg_3);
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480 Register java_thread,
2481 Register last_java_sp,
2482 address entry_point,
2483 int number_of_arguments,
2484 bool check_exceptions) {
2485 // determine java_thread register
2486 if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488 java_thread = r15_thread;
2489 #else
2490 java_thread = rdi;
2491 get_thread(java_thread);
2492 #endif // LP64
2493 }
2494 // determine last_java_sp register
2495 if (!last_java_sp->is_valid()) {
2496 last_java_sp = rsp;
2497 }
2498 // debugging support
2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503 // r12 is the heapbase.
2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506
2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509
2510 // push java thread (becomes first argument of C function)
2511
2512 NOT_LP64(push(java_thread); number_of_arguments++);
2513 LP64_ONLY(mov(c_rarg0, r15_thread));
2514
2515 // set last Java frame before call
2516 assert(last_java_sp != rbp, "can't use ebp/rbp");
2517
2518 // Only interpreter should have to set fp
2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520
2521 // do the call, remove parameters
2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523
2524 // restore the thread (cannot use the pushed argument since arguments
2525 // may be overwritten by C code generated by an optimizing compiler);
2526 // however can use the register value directly if it is callee saved.
2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528 // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530 guarantee(java_thread != rax, "change this code");
2531 push(rax);
2532 { Label L;
2533 get_thread(rax);
2534 cmpptr(java_thread, rax);
2535 jcc(Assembler::equal, L);
2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537 bind(L);
2538 }
2539 pop(rax);
2540 #endif
2541 } else {
2542 get_thread(java_thread);
2543 }
2544 // reset last Java frame
2545 // Only interpreter should have to clear fp
2546 reset_last_Java_frame(java_thread, true);
2547
2548 // C++ interp handles this in the interpreter
2549 check_and_handle_popframe(java_thread);
2550 check_and_handle_earlyret(java_thread);
2551
2552 if (check_exceptions) {
2553 // check for pending exceptions (java_thread is set upon return)
2554 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2555 #ifndef _LP64
2556 jump_cc(Assembler::notEqual,
2557 RuntimeAddress(StubRoutines::forward_exception_entry()));
2558 #else
2559 // This used to conditionally jump to forward_exception however it is
2560 // possible if we relocate that the branch will not reach. So we must jump
2561 // around so we can always reach
2562
2563 Label ok;
2564 jcc(Assembler::equal, ok);
2565 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2566 bind(ok);
2567 #endif // LP64
2568 }
2569
2570 // get oop result if there is one and reset the value in the thread
2571 if (oop_result->is_valid()) {
2572 get_vm_result(oop_result, java_thread);
2573 }
2574 }
2575
2576 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2577
2578 // Calculate the value for last_Java_sp
2579 // somewhat subtle. call_VM does an intermediate call
2580 // which places a return address on the stack just under the
2581 // stack pointer as the user finsihed with it. This allows
2582 // use to retrieve last_Java_pc from last_Java_sp[-1].
2583 // On 32bit we then have to push additional args on the stack to accomplish
2584 // the actual requested call. On 64bit call_VM only can use register args
2585 // so the only extra space is the return address that call_VM created.
2586 // This hopefully explains the calculations here.
2587
2588 #ifdef _LP64
2589 // We've pushed one address, correct last_Java_sp
2590 lea(rax, Address(rsp, wordSize));
2591 #else
2592 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2593 #endif // LP64
2594
2595 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2596
2597 }
2598
2599 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2600 void MacroAssembler::call_VM_leaf0(address entry_point) {
2601 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2602 }
2603
2604 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2605 call_VM_leaf_base(entry_point, number_of_arguments);
2606 }
2607
2608 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2609 pass_arg0(this, arg_0);
2610 call_VM_leaf(entry_point, 1);
2611 }
2612
2613 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2614
2615 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2616 pass_arg1(this, arg_1);
2617 pass_arg0(this, arg_0);
2618 call_VM_leaf(entry_point, 2);
2619 }
2620
2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2622 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2623 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2624 pass_arg2(this, arg_2);
2625 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2626 pass_arg1(this, arg_1);
2627 pass_arg0(this, arg_0);
2628 call_VM_leaf(entry_point, 3);
2629 }
2630
2631 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2632 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2633 }
2634
2635 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2636 pass_arg0(this, arg_0);
2637 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2638 }
2639
2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2641
2642 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2643 pass_arg1(this, arg_1);
2644 pass_arg0(this, arg_0);
2645 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2646 }
2647
2648 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2649 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2650 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2651 pass_arg2(this, arg_2);
2652 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2653 pass_arg1(this, arg_1);
2654 pass_arg0(this, arg_0);
2655 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2656 }
2657
2658 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2659 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2660 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2661 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2662 pass_arg3(this, arg_3);
2663 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2664 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2665 pass_arg2(this, arg_2);
2666 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2667 pass_arg1(this, arg_1);
2668 pass_arg0(this, arg_0);
2669 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2670 }
2671
2672 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2673 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2674 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2675 verify_oop(oop_result, "broken oop in call_VM_base");
2676 }
2677
2678 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2679 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2680 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2681 }
2682
2683 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2684 }
2685
2686 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2687 }
2688
2689 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2690 if (reachable(src1)) {
2691 cmpl(as_Address(src1), imm);
2692 } else {
2693 lea(rscratch1, src1);
2694 cmpl(Address(rscratch1, 0), imm);
2695 }
2696 }
2697
2698 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2699 assert(!src2.is_lval(), "use cmpptr");
2700 if (reachable(src2)) {
2701 cmpl(src1, as_Address(src2));
2702 } else {
2703 lea(rscratch1, src2);
2704 cmpl(src1, Address(rscratch1, 0));
2705 }
2706 }
2707
2708 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2709 Assembler::cmpl(src1, imm);
2710 }
2711
2712 void MacroAssembler::cmp32(Register src1, Address src2) {
2713 Assembler::cmpl(src1, src2);
2714 }
2715
2716 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2717 ucomisd(opr1, opr2);
2718
2719 Label L;
2720 if (unordered_is_less) {
2721 movl(dst, -1);
2722 jcc(Assembler::parity, L);
2723 jcc(Assembler::below , L);
2724 movl(dst, 0);
2725 jcc(Assembler::equal , L);
2726 increment(dst);
2727 } else { // unordered is greater
2728 movl(dst, 1);
2729 jcc(Assembler::parity, L);
2730 jcc(Assembler::above , L);
2731 movl(dst, 0);
2732 jcc(Assembler::equal , L);
2733 decrementl(dst);
2734 }
2735 bind(L);
2736 }
2737
2738 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2739 ucomiss(opr1, opr2);
2740
2741 Label L;
2742 if (unordered_is_less) {
2743 movl(dst, -1);
2744 jcc(Assembler::parity, L);
2745 jcc(Assembler::below , L);
2746 movl(dst, 0);
2747 jcc(Assembler::equal , L);
2748 increment(dst);
2749 } else { // unordered is greater
2750 movl(dst, 1);
2751 jcc(Assembler::parity, L);
2752 jcc(Assembler::above , L);
2753 movl(dst, 0);
2754 jcc(Assembler::equal , L);
2755 decrementl(dst);
2756 }
2757 bind(L);
2758 }
2759
2760
2761 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2762 if (reachable(src1)) {
2763 cmpb(as_Address(src1), imm);
2764 } else {
2765 lea(rscratch1, src1);
2766 cmpb(Address(rscratch1, 0), imm);
2767 }
2768 }
2769
2770 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2771 #ifdef _LP64
2772 if (src2.is_lval()) {
2773 movptr(rscratch1, src2);
2774 Assembler::cmpq(src1, rscratch1);
2775 } else if (reachable(src2)) {
2776 cmpq(src1, as_Address(src2));
2777 } else {
2778 lea(rscratch1, src2);
2779 Assembler::cmpq(src1, Address(rscratch1, 0));
2780 }
2781 #else
2782 if (src2.is_lval()) {
2783 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2784 } else {
2785 cmpl(src1, as_Address(src2));
2786 }
2787 #endif // _LP64
2788 }
2789
2790 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2791 assert(src2.is_lval(), "not a mem-mem compare");
2792 #ifdef _LP64
2793 // moves src2's literal address
2794 movptr(rscratch1, src2);
2795 Assembler::cmpq(src1, rscratch1);
2796 #else
2797 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2798 #endif // _LP64
2799 }
2800
2801 void MacroAssembler::cmpoop(Register src1, Register src2) {
2802 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2803 bs->obj_equals(this, src1, src2);
2804 }
2805
2806 void MacroAssembler::cmpoop(Register src1, Address src2) {
2807 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2808 bs->obj_equals(this, src1, src2);
2809 }
2810
2811 #ifdef _LP64
2812 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2813 movoop(rscratch1, src2);
2814 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2815 bs->obj_equals(this, src1, rscratch1);
2816 }
2817 #endif
2818
2819 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2820 if (reachable(adr)) {
2821 if (os::is_MP())
2822 lock();
2823 cmpxchgptr(reg, as_Address(adr));
2824 } else {
2825 lea(rscratch1, adr);
2826 if (os::is_MP())
2827 lock();
2828 cmpxchgptr(reg, Address(rscratch1, 0));
2829 }
2830 }
2831
2832 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2833 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2834 }
2835
2836 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2837 if (reachable(src)) {
2838 Assembler::comisd(dst, as_Address(src));
2839 } else {
2840 lea(rscratch1, src);
2841 Assembler::comisd(dst, Address(rscratch1, 0));
2842 }
2843 }
2844
2845 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2846 if (reachable(src)) {
2847 Assembler::comiss(dst, as_Address(src));
2848 } else {
2849 lea(rscratch1, src);
2850 Assembler::comiss(dst, Address(rscratch1, 0));
2851 }
2852 }
2853
2854
2855 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2856 Condition negated_cond = negate_condition(cond);
2857 Label L;
2858 jcc(negated_cond, L);
2859 pushf(); // Preserve flags
2860 atomic_incl(counter_addr);
2861 popf();
2862 bind(L);
2863 }
2864
2865 int MacroAssembler::corrected_idivl(Register reg) {
2866 // Full implementation of Java idiv and irem; checks for
2867 // special case as described in JVM spec., p.243 & p.271.
2868 // The function returns the (pc) offset of the idivl
2869 // instruction - may be needed for implicit exceptions.
2870 //
2871 // normal case special case
2872 //
2873 // input : rax,: dividend min_int
2874 // reg: divisor (may not be rax,/rdx) -1
2875 //
2876 // output: rax,: quotient (= rax, idiv reg) min_int
2877 // rdx: remainder (= rax, irem reg) 0
2878 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2879 const int min_int = 0x80000000;
2880 Label normal_case, special_case;
2881
2882 // check for special case
2883 cmpl(rax, min_int);
2884 jcc(Assembler::notEqual, normal_case);
2885 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2886 cmpl(reg, -1);
2887 jcc(Assembler::equal, special_case);
2888
2889 // handle normal case
2890 bind(normal_case);
2891 cdql();
2892 int idivl_offset = offset();
2893 idivl(reg);
2894
2895 // normal and special case exit
2896 bind(special_case);
2897
2898 return idivl_offset;
2899 }
2900
2901
2902
2903 void MacroAssembler::decrementl(Register reg, int value) {
2904 if (value == min_jint) {subl(reg, value) ; return; }
2905 if (value < 0) { incrementl(reg, -value); return; }
2906 if (value == 0) { ; return; }
2907 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2908 /* else */ { subl(reg, value) ; return; }
2909 }
2910
2911 void MacroAssembler::decrementl(Address dst, int value) {
2912 if (value == min_jint) {subl(dst, value) ; return; }
2913 if (value < 0) { incrementl(dst, -value); return; }
2914 if (value == 0) { ; return; }
2915 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2916 /* else */ { subl(dst, value) ; return; }
2917 }
2918
2919 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2920 assert (shift_value > 0, "illegal shift value");
2921 Label _is_positive;
2922 testl (reg, reg);
2923 jcc (Assembler::positive, _is_positive);
2924 int offset = (1 << shift_value) - 1 ;
2925
2926 if (offset == 1) {
2927 incrementl(reg);
2928 } else {
2929 addl(reg, offset);
2930 }
2931
2932 bind (_is_positive);
2933 sarl(reg, shift_value);
2934 }
2935
2936 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2937 if (reachable(src)) {
2938 Assembler::divsd(dst, as_Address(src));
2939 } else {
2940 lea(rscratch1, src);
2941 Assembler::divsd(dst, Address(rscratch1, 0));
2942 }
2943 }
2944
2945 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2946 if (reachable(src)) {
2947 Assembler::divss(dst, as_Address(src));
2948 } else {
2949 lea(rscratch1, src);
2950 Assembler::divss(dst, Address(rscratch1, 0));
2951 }
2952 }
2953
2954 // !defined(COMPILER2) is because of stupid core builds
2955 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2956 void MacroAssembler::empty_FPU_stack() {
2957 if (VM_Version::supports_mmx()) {
2958 emms();
2959 } else {
2960 for (int i = 8; i-- > 0; ) ffree(i);
2961 }
2962 }
2963 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2964
2965
2966 void MacroAssembler::enter() {
2967 push(rbp);
2968 mov(rbp, rsp);
2969 }
2970
2971 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2972 void MacroAssembler::fat_nop() {
2973 if (UseAddressNop) {
2974 addr_nop_5();
2975 } else {
2976 emit_int8(0x26); // es:
2977 emit_int8(0x2e); // cs:
2978 emit_int8(0x64); // fs:
2979 emit_int8(0x65); // gs:
2980 emit_int8((unsigned char)0x90);
2981 }
2982 }
2983
2984 void MacroAssembler::fcmp(Register tmp) {
2985 fcmp(tmp, 1, true, true);
2986 }
2987
2988 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2989 assert(!pop_right || pop_left, "usage error");
2990 if (VM_Version::supports_cmov()) {
2991 assert(tmp == noreg, "unneeded temp");
2992 if (pop_left) {
2993 fucomip(index);
2994 } else {
2995 fucomi(index);
2996 }
2997 if (pop_right) {
2998 fpop();
2999 }
3000 } else {
3001 assert(tmp != noreg, "need temp");
3002 if (pop_left) {
3003 if (pop_right) {
3004 fcompp();
3005 } else {
3006 fcomp(index);
3007 }
3008 } else {
3009 fcom(index);
3010 }
3011 // convert FPU condition into eflags condition via rax,
3012 save_rax(tmp);
3013 fwait(); fnstsw_ax();
3014 sahf();
3015 restore_rax(tmp);
3016 }
3017 // condition codes set as follows:
3018 //
3019 // CF (corresponds to C0) if x < y
3020 // PF (corresponds to C2) if unordered
3021 // ZF (corresponds to C3) if x = y
3022 }
3023
3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3025 fcmp2int(dst, unordered_is_less, 1, true, true);
3026 }
3027
3028 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3029 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3030 Label L;
3031 if (unordered_is_less) {
3032 movl(dst, -1);
3033 jcc(Assembler::parity, L);
3034 jcc(Assembler::below , L);
3035 movl(dst, 0);
3036 jcc(Assembler::equal , L);
3037 increment(dst);
3038 } else { // unordered is greater
3039 movl(dst, 1);
3040 jcc(Assembler::parity, L);
3041 jcc(Assembler::above , L);
3042 movl(dst, 0);
3043 jcc(Assembler::equal , L);
3044 decrementl(dst);
3045 }
3046 bind(L);
3047 }
3048
3049 void MacroAssembler::fld_d(AddressLiteral src) {
3050 fld_d(as_Address(src));
3051 }
3052
3053 void MacroAssembler::fld_s(AddressLiteral src) {
3054 fld_s(as_Address(src));
3055 }
3056
3057 void MacroAssembler::fld_x(AddressLiteral src) {
3058 Assembler::fld_x(as_Address(src));
3059 }
3060
3061 void MacroAssembler::fldcw(AddressLiteral src) {
3062 Assembler::fldcw(as_Address(src));
3063 }
3064
3065 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3066 if (reachable(src)) {
3067 Assembler::mulpd(dst, as_Address(src));
3068 } else {
3069 lea(rscratch1, src);
3070 Assembler::mulpd(dst, Address(rscratch1, 0));
3071 }
3072 }
3073
3074 void MacroAssembler::increase_precision() {
3075 subptr(rsp, BytesPerWord);
3076 fnstcw(Address(rsp, 0));
3077 movl(rax, Address(rsp, 0));
3078 orl(rax, 0x300);
3079 push(rax);
3080 fldcw(Address(rsp, 0));
3081 pop(rax);
3082 }
3083
3084 void MacroAssembler::restore_precision() {
3085 fldcw(Address(rsp, 0));
3086 addptr(rsp, BytesPerWord);
3087 }
3088
3089 void MacroAssembler::fpop() {
3090 ffree();
3091 fincstp();
3092 }
3093
3094 void MacroAssembler::load_float(Address src) {
3095 if (UseSSE >= 1) {
3096 movflt(xmm0, src);
3097 } else {
3098 LP64_ONLY(ShouldNotReachHere());
3099 NOT_LP64(fld_s(src));
3100 }
3101 }
3102
3103 void MacroAssembler::store_float(Address dst) {
3104 if (UseSSE >= 1) {
3105 movflt(dst, xmm0);
3106 } else {
3107 LP64_ONLY(ShouldNotReachHere());
3108 NOT_LP64(fstp_s(dst));
3109 }
3110 }
3111
3112 void MacroAssembler::load_double(Address src) {
3113 if (UseSSE >= 2) {
3114 movdbl(xmm0, src);
3115 } else {
3116 LP64_ONLY(ShouldNotReachHere());
3117 NOT_LP64(fld_d(src));
3118 }
3119 }
3120
3121 void MacroAssembler::store_double(Address dst) {
3122 if (UseSSE >= 2) {
3123 movdbl(dst, xmm0);
3124 } else {
3125 LP64_ONLY(ShouldNotReachHere());
3126 NOT_LP64(fstp_d(dst));
3127 }
3128 }
3129
3130 void MacroAssembler::push_zmm(XMMRegister reg) {
3131 lea(rsp, Address(rsp, -64)); // Use lea to not affect flags
3132 evmovdqul(Address(rsp, 0), reg, Assembler::AVX_512bit);
3133 }
3134
3135 void MacroAssembler::pop_zmm(XMMRegister reg) {
3136 evmovdqul(reg, Address(rsp, 0), Assembler::AVX_512bit);
3137 lea(rsp, Address(rsp, 64)); // Use lea to not affect flags
3138 }
3139
3140 void MacroAssembler::fremr(Register tmp) {
3141 save_rax(tmp);
3142 { Label L;
3143 bind(L);
3144 fprem();
3145 fwait(); fnstsw_ax();
3146 #ifdef _LP64
3147 testl(rax, 0x400);
3148 jcc(Assembler::notEqual, L);
3149 #else
3150 sahf();
3151 jcc(Assembler::parity, L);
3152 #endif // _LP64
3153 }
3154 restore_rax(tmp);
3155 // Result is in ST0.
3156 // Note: fxch & fpop to get rid of ST1
3157 // (otherwise FPU stack could overflow eventually)
3158 fxch(1);
3159 fpop();
3160 }
3161
3162 // dst = c = a * b + c
3163 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3164 Assembler::vfmadd231sd(c, a, b);
3165 if (dst != c) {
3166 movdbl(dst, c);
3167 }
3168 }
3169
3170 // dst = c = a * b + c
3171 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3172 Assembler::vfmadd231ss(c, a, b);
3173 if (dst != c) {
3174 movflt(dst, c);
3175 }
3176 }
3177
3178 // dst = c = a * b + c
3179 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3180 Assembler::vfmadd231pd(c, a, b, vector_len);
3181 if (dst != c) {
3182 vmovdqu(dst, c);
3183 }
3184 }
3185
3186 // dst = c = a * b + c
3187 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3188 Assembler::vfmadd231ps(c, a, b, vector_len);
3189 if (dst != c) {
3190 vmovdqu(dst, c);
3191 }
3192 }
3193
3194 // dst = c = a * b + c
3195 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3196 Assembler::vfmadd231pd(c, a, b, vector_len);
3197 if (dst != c) {
3198 vmovdqu(dst, c);
3199 }
3200 }
3201
3202 // dst = c = a * b + c
3203 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3204 Assembler::vfmadd231ps(c, a, b, vector_len);
3205 if (dst != c) {
3206 vmovdqu(dst, c);
3207 }
3208 }
3209
3210 void MacroAssembler::incrementl(AddressLiteral dst) {
3211 if (reachable(dst)) {
3212 incrementl(as_Address(dst));
3213 } else {
3214 lea(rscratch1, dst);
3215 incrementl(Address(rscratch1, 0));
3216 }
3217 }
3218
3219 void MacroAssembler::incrementl(ArrayAddress dst) {
3220 incrementl(as_Address(dst));
3221 }
3222
3223 void MacroAssembler::incrementl(Register reg, int value) {
3224 if (value == min_jint) {addl(reg, value) ; return; }
3225 if (value < 0) { decrementl(reg, -value); return; }
3226 if (value == 0) { ; return; }
3227 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3228 /* else */ { addl(reg, value) ; return; }
3229 }
3230
3231 void MacroAssembler::incrementl(Address dst, int value) {
3232 if (value == min_jint) {addl(dst, value) ; return; }
3233 if (value < 0) { decrementl(dst, -value); return; }
3234 if (value == 0) { ; return; }
3235 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3236 /* else */ { addl(dst, value) ; return; }
3237 }
3238
3239 void MacroAssembler::jump(AddressLiteral dst) {
3240 if (reachable(dst)) {
3241 jmp_literal(dst.target(), dst.rspec());
3242 } else {
3243 lea(rscratch1, dst);
3244 jmp(rscratch1);
3245 }
3246 }
3247
3248 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3249 if (reachable(dst)) {
3250 InstructionMark im(this);
3251 relocate(dst.reloc());
3252 const int short_size = 2;
3253 const int long_size = 6;
3254 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3255 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3256 // 0111 tttn #8-bit disp
3257 emit_int8(0x70 | cc);
3258 emit_int8((offs - short_size) & 0xFF);
3259 } else {
3260 // 0000 1111 1000 tttn #32-bit disp
3261 emit_int8(0x0F);
3262 emit_int8((unsigned char)(0x80 | cc));
3263 emit_int32(offs - long_size);
3264 }
3265 } else {
3266 #ifdef ASSERT
3267 warning("reversing conditional branch");
3268 #endif /* ASSERT */
3269 Label skip;
3270 jccb(reverse[cc], skip);
3271 lea(rscratch1, dst);
3272 Assembler::jmp(rscratch1);
3273 bind(skip);
3274 }
3275 }
3276
3277 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3278 if (reachable(src)) {
3279 Assembler::ldmxcsr(as_Address(src));
3280 } else {
3281 lea(rscratch1, src);
3282 Assembler::ldmxcsr(Address(rscratch1, 0));
3283 }
3284 }
3285
3286 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3287 int off;
3288 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3289 off = offset();
3290 movsbl(dst, src); // movsxb
3291 } else {
3292 off = load_unsigned_byte(dst, src);
3293 shll(dst, 24);
3294 sarl(dst, 24);
3295 }
3296 return off;
3297 }
3298
3299 // Note: load_signed_short used to be called load_signed_word.
3300 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3301 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3302 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3303 int MacroAssembler::load_signed_short(Register dst, Address src) {
3304 int off;
3305 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3306 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3307 // version but this is what 64bit has always done. This seems to imply
3308 // that users are only using 32bits worth.
3309 off = offset();
3310 movswl(dst, src); // movsxw
3311 } else {
3312 off = load_unsigned_short(dst, src);
3313 shll(dst, 16);
3314 sarl(dst, 16);
3315 }
3316 return off;
3317 }
3318
3319 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3320 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3321 // and "3.9 Partial Register Penalties", p. 22).
3322 int off;
3323 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3324 off = offset();
3325 movzbl(dst, src); // movzxb
3326 } else {
3327 xorl(dst, dst);
3328 off = offset();
3329 movb(dst, src);
3330 }
3331 return off;
3332 }
3333
3334 // Note: load_unsigned_short used to be called load_unsigned_word.
3335 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3336 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3337 // and "3.9 Partial Register Penalties", p. 22).
3338 int off;
3339 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3340 off = offset();
3341 movzwl(dst, src); // movzxw
3342 } else {
3343 xorl(dst, dst);
3344 off = offset();
3345 movw(dst, src);
3346 }
3347 return off;
3348 }
3349
3350 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3351 switch (size_in_bytes) {
3352 #ifndef _LP64
3353 case 8:
3354 assert(dst2 != noreg, "second dest register required");
3355 movl(dst, src);
3356 movl(dst2, src.plus_disp(BytesPerInt));
3357 break;
3358 #else
3359 case 8: movq(dst, src); break;
3360 #endif
3361 case 4: movl(dst, src); break;
3362 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3363 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3364 default: ShouldNotReachHere();
3365 }
3366 }
3367
3368 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3369 switch (size_in_bytes) {
3370 #ifndef _LP64
3371 case 8:
3372 assert(src2 != noreg, "second source register required");
3373 movl(dst, src);
3374 movl(dst.plus_disp(BytesPerInt), src2);
3375 break;
3376 #else
3377 case 8: movq(dst, src); break;
3378 #endif
3379 case 4: movl(dst, src); break;
3380 case 2: movw(dst, src); break;
3381 case 1: movb(dst, src); break;
3382 default: ShouldNotReachHere();
3383 }
3384 }
3385
3386 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3387 if (reachable(dst)) {
3388 movl(as_Address(dst), src);
3389 } else {
3390 lea(rscratch1, dst);
3391 movl(Address(rscratch1, 0), src);
3392 }
3393 }
3394
3395 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3396 if (reachable(src)) {
3397 movl(dst, as_Address(src));
3398 } else {
3399 lea(rscratch1, src);
3400 movl(dst, Address(rscratch1, 0));
3401 }
3402 }
3403
3404 // C++ bool manipulation
3405
3406 void MacroAssembler::movbool(Register dst, Address src) {
3407 if(sizeof(bool) == 1)
3408 movb(dst, src);
3409 else if(sizeof(bool) == 2)
3410 movw(dst, src);
3411 else if(sizeof(bool) == 4)
3412 movl(dst, src);
3413 else
3414 // unsupported
3415 ShouldNotReachHere();
3416 }
3417
3418 void MacroAssembler::movbool(Address dst, bool boolconst) {
3419 if(sizeof(bool) == 1)
3420 movb(dst, (int) boolconst);
3421 else if(sizeof(bool) == 2)
3422 movw(dst, (int) boolconst);
3423 else if(sizeof(bool) == 4)
3424 movl(dst, (int) boolconst);
3425 else
3426 // unsupported
3427 ShouldNotReachHere();
3428 }
3429
3430 void MacroAssembler::movbool(Address dst, Register src) {
3431 if(sizeof(bool) == 1)
3432 movb(dst, src);
3433 else if(sizeof(bool) == 2)
3434 movw(dst, src);
3435 else if(sizeof(bool) == 4)
3436 movl(dst, src);
3437 else
3438 // unsupported
3439 ShouldNotReachHere();
3440 }
3441
3442 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3443 movb(as_Address(dst), src);
3444 }
3445
3446 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3447 if (reachable(src)) {
3448 movdl(dst, as_Address(src));
3449 } else {
3450 lea(rscratch1, src);
3451 movdl(dst, Address(rscratch1, 0));
3452 }
3453 }
3454
3455 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3456 if (reachable(src)) {
3457 movq(dst, as_Address(src));
3458 } else {
3459 lea(rscratch1, src);
3460 movq(dst, Address(rscratch1, 0));
3461 }
3462 }
3463
3464 void MacroAssembler::setvectmask(Register dst, Register src) {
3465 Assembler::movl(dst, 1);
3466 Assembler::shlxl(dst, dst, src);
3467 Assembler::decl(dst);
3468 Assembler::kmovdl(k1, dst);
3469 Assembler::movl(dst, src);
3470 }
3471
3472 void MacroAssembler::restorevectmask() {
3473 Assembler::knotwl(k1, k0);
3474 }
3475
3476 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3477 if (reachable(src)) {
3478 if (UseXmmLoadAndClearUpper) {
3479 movsd (dst, as_Address(src));
3480 } else {
3481 movlpd(dst, as_Address(src));
3482 }
3483 } else {
3484 lea(rscratch1, src);
3485 if (UseXmmLoadAndClearUpper) {
3486 movsd (dst, Address(rscratch1, 0));
3487 } else {
3488 movlpd(dst, Address(rscratch1, 0));
3489 }
3490 }
3491 }
3492
3493 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3494 if (reachable(src)) {
3495 movss(dst, as_Address(src));
3496 } else {
3497 lea(rscratch1, src);
3498 movss(dst, Address(rscratch1, 0));
3499 }
3500 }
3501
3502 void MacroAssembler::movptr(Register dst, Register src) {
3503 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3504 }
3505
3506 void MacroAssembler::movptr(Register dst, Address src) {
3507 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3508 }
3509
3510 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3511 void MacroAssembler::movptr(Register dst, intptr_t src) {
3512 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3513 }
3514
3515 void MacroAssembler::movptr(Address dst, Register src) {
3516 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3517 }
3518
3519 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3520 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3521 Assembler::vextractf32x4(dst, src, 0);
3522 } else {
3523 Assembler::movdqu(dst, src);
3524 }
3525 }
3526
3527 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3528 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3529 Assembler::vinsertf32x4(dst, dst, src, 0);
3530 } else {
3531 Assembler::movdqu(dst, src);
3532 }
3533 }
3534
3535 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3536 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3537 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3538 } else {
3539 Assembler::movdqu(dst, src);
3540 }
3541 }
3542
3543 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3544 if (reachable(src)) {
3545 movdqu(dst, as_Address(src));
3546 } else {
3547 lea(scratchReg, src);
3548 movdqu(dst, Address(scratchReg, 0));
3549 }
3550 }
3551
3552 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3553 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3554 vextractf64x4_low(dst, src);
3555 } else {
3556 Assembler::vmovdqu(dst, src);
3557 }
3558 }
3559
3560 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3561 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3562 vinsertf64x4_low(dst, src);
3563 } else {
3564 Assembler::vmovdqu(dst, src);
3565 }
3566 }
3567
3568 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3569 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3570 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3571 }
3572 else {
3573 Assembler::vmovdqu(dst, src);
3574 }
3575 }
3576
3577 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3578 if (reachable(src)) {
3579 vmovdqu(dst, as_Address(src));
3580 }
3581 else {
3582 lea(rscratch1, src);
3583 vmovdqu(dst, Address(rscratch1, 0));
3584 }
3585 }
3586
3587 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3588 if (reachable(src)) {
3589 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3590 } else {
3591 lea(rscratch, src);
3592 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3593 }
3594 }
3595
3596 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3597 if (reachable(src)) {
3598 Assembler::movdqa(dst, as_Address(src));
3599 } else {
3600 lea(rscratch1, src);
3601 Assembler::movdqa(dst, Address(rscratch1, 0));
3602 }
3603 }
3604
3605 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3606 if (reachable(src)) {
3607 Assembler::movsd(dst, as_Address(src));
3608 } else {
3609 lea(rscratch1, src);
3610 Assembler::movsd(dst, Address(rscratch1, 0));
3611 }
3612 }
3613
3614 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3615 if (reachable(src)) {
3616 Assembler::movss(dst, as_Address(src));
3617 } else {
3618 lea(rscratch1, src);
3619 Assembler::movss(dst, Address(rscratch1, 0));
3620 }
3621 }
3622
3623 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3624 if (reachable(src)) {
3625 Assembler::mulsd(dst, as_Address(src));
3626 } else {
3627 lea(rscratch1, src);
3628 Assembler::mulsd(dst, Address(rscratch1, 0));
3629 }
3630 }
3631
3632 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3633 if (reachable(src)) {
3634 Assembler::mulss(dst, as_Address(src));
3635 } else {
3636 lea(rscratch1, src);
3637 Assembler::mulss(dst, Address(rscratch1, 0));
3638 }
3639 }
3640
3641 void MacroAssembler::null_check(Register reg, int offset) {
3642 if (needs_explicit_null_check(offset)) {
3643 // provoke OS NULL exception if reg = NULL by
3644 // accessing M[reg] w/o changing any (non-CC) registers
3645 // NOTE: cmpl is plenty here to provoke a segv
3646 cmpptr(rax, Address(reg, 0));
3647 // Note: should probably use testl(rax, Address(reg, 0));
3648 // may be shorter code (however, this version of
3649 // testl needs to be implemented first)
3650 } else {
3651 // nothing to do, (later) access of M[reg + offset]
3652 // will provoke OS NULL exception if reg = NULL
3653 }
3654 }
3655
3656 void MacroAssembler::test_klass_is_value(Register klass, Register temp_reg, Label& is_value) {
3657 movl(temp_reg, Address(klass, Klass::access_flags_offset()));
3658 testl(temp_reg, JVM_ACC_VALUE);
3659 jcc(Assembler::notZero, is_value);
3660 }
3661
3662 void MacroAssembler::test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable) {
3663 movl(temp_reg, flags);
3664 shrl(temp_reg, ConstantPoolCacheEntry::is_flattenable_field_shift);
3665 andl(temp_reg, 0x1);
3666 testl(temp_reg, temp_reg);
3667 jcc(Assembler::notZero, is_flattenable);
3668 }
3669
3670 void MacroAssembler::test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable) {
3671 movl(temp_reg, flags);
3672 shrl(temp_reg, ConstantPoolCacheEntry::is_flattenable_field_shift);
3673 andl(temp_reg, 0x1);
3674 testl(temp_reg, temp_reg);
3675 jcc(Assembler::zero, notFlattenable);
3676 }
3677
3678 void MacroAssembler::test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened) {
3679 movl(temp_reg, flags);
3680 shrl(temp_reg, ConstantPoolCacheEntry::is_flattened_field_shift);
3681 andl(temp_reg, 0x1);
3682 testl(temp_reg, temp_reg);
3683 jcc(Assembler::notZero, is_flattened);
3684 }
3685
3686 void MacroAssembler::test_flat_array_klass(Register klass, Register temp_reg,
3687 Label& is_flat_array) {
3688 movl(temp_reg, Address(klass, Klass::layout_helper_offset()));
3689 sarl(temp_reg, Klass::_lh_array_tag_shift);
3690 cmpl(temp_reg, Klass::_lh_array_tag_vt_value);
3691 jcc(Assembler::equal, is_flat_array);
3692 }
3693
3694
3695 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
3696 Label& is_flat_array) {
3697 load_klass(temp_reg, oop);
3698 test_flat_array_klass(temp_reg, temp_reg, is_flat_array);
3699 }
3700
3701 void MacroAssembler::test_value_is_not_buffered(Register value, Register temp_reg, Label& not_buffered) {
3702 ExternalAddress VTBuffer_top(VTBuffer::top_addr());
3703 ExternalAddress VTBuffer_end(VTBuffer::end_addr());
3704
3705 // Test below is ordered based on the relative positions of
3706 // the Java heap and the VTBuffer to execute a single test for heap-allocated values
3707
3708 if (VTBuffer::base() < Universe::heap()->base()) {
3709 lea(temp_reg, VTBuffer_end);
3710 cmpptr(value, temp_reg);
3711 jcc(Assembler::greaterEqual, not_buffered);
3712 lea(temp_reg, VTBuffer_top);
3713 cmpptr(value, temp_reg);
3714 jcc(Assembler::less, not_buffered);
3715 } else {
3716 lea(temp_reg, VTBuffer_top);
3717 cmpptr(value, temp_reg);
3718 jcc(Assembler::less, not_buffered);
3719 lea(temp_reg, VTBuffer_end);
3720 cmpptr(value, temp_reg);
3721 jcc(Assembler::greaterEqual, not_buffered);
3722 }
3723 }
3724
3725 void MacroAssembler::os_breakpoint() {
3726 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3727 // (e.g., MSVC can't call ps() otherwise)
3728 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3729 }
3730
3731 void MacroAssembler::unimplemented(const char* what) {
3732 const char* buf = NULL;
3733 {
3734 ResourceMark rm;
3735 stringStream ss;
3736 ss.print("unimplemented: %s", what);
3737 buf = code_string(ss.as_string());
3738 }
3739 stop(buf);
3740 }
3741
3742 #ifdef _LP64
3743 #define XSTATE_BV 0x200
3744 #endif
3745
3746 void MacroAssembler::pop_CPU_state() {
3747 pop_FPU_state();
3748 pop_IU_state();
3749 }
3750
3751 void MacroAssembler::pop_FPU_state() {
3752 #ifndef _LP64
3753 frstor(Address(rsp, 0));
3754 #else
3755 fxrstor(Address(rsp, 0));
3756 #endif
3757 addptr(rsp, FPUStateSizeInWords * wordSize);
3758 }
3759
3760 void MacroAssembler::pop_IU_state() {
3761 popa();
3762 LP64_ONLY(addq(rsp, 8));
3763 popf();
3764 }
3765
3766 // Save Integer and Float state
3767 // Warning: Stack must be 16 byte aligned (64bit)
3768 void MacroAssembler::push_CPU_state() {
3769 push_IU_state();
3770 push_FPU_state();
3771 }
3772
3773 void MacroAssembler::push_FPU_state() {
3774 subptr(rsp, FPUStateSizeInWords * wordSize);
3775 #ifndef _LP64
3776 fnsave(Address(rsp, 0));
3777 fwait();
3778 #else
3779 fxsave(Address(rsp, 0));
3780 #endif // LP64
3781 }
3782
3783 void MacroAssembler::push_IU_state() {
3784 // Push flags first because pusha kills them
3785 pushf();
3786 // Make sure rsp stays 16-byte aligned
3787 LP64_ONLY(subq(rsp, 8));
3788 pusha();
3789 }
3790
3791 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3792 if (!java_thread->is_valid()) {
3793 java_thread = rdi;
3794 get_thread(java_thread);
3795 }
3796 // we must set sp to zero to clear frame
3797 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3798 if (clear_fp) {
3799 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3800 }
3801
3802 // Always clear the pc because it could have been set by make_walkable()
3803 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3804
3805 vzeroupper();
3806 }
3807
3808 void MacroAssembler::restore_rax(Register tmp) {
3809 if (tmp == noreg) pop(rax);
3810 else if (tmp != rax) mov(rax, tmp);
3811 }
3812
3813 void MacroAssembler::round_to(Register reg, int modulus) {
3814 addptr(reg, modulus - 1);
3815 andptr(reg, -modulus);
3816 }
3817
3818 void MacroAssembler::save_rax(Register tmp) {
3819 if (tmp == noreg) push(rax);
3820 else if (tmp != rax) mov(tmp, rax);
3821 }
3822
3823 // Write serialization page so VM thread can do a pseudo remote membar.
3824 // We use the current thread pointer to calculate a thread specific
3825 // offset to write to within the page. This minimizes bus traffic
3826 // due to cache line collision.
3827 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3828 movl(tmp, thread);
3829 shrl(tmp, os::get_serialize_page_shift_count());
3830 andl(tmp, (os::vm_page_size() - sizeof(int)));
3831
3832 Address index(noreg, tmp, Address::times_1);
3833 ExternalAddress page(os::get_memory_serialize_page());
3834
3835 // Size of store must match masking code above
3836 movl(as_Address(ArrayAddress(page, index)), tmp);
3837 }
3838
3839 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3840 if (SafepointMechanism::uses_thread_local_poll()) {
3841 #ifdef _LP64
3842 assert(thread_reg == r15_thread, "should be");
3843 #else
3844 if (thread_reg == noreg) {
3845 thread_reg = temp_reg;
3846 get_thread(thread_reg);
3847 }
3848 #endif
3849 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3850 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3851 } else {
3852 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3853 SafepointSynchronize::_not_synchronized);
3854 jcc(Assembler::notEqual, slow_path);
3855 }
3856 }
3857
3858 // Calls to C land
3859 //
3860 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3861 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3862 // has to be reset to 0. This is required to allow proper stack traversal.
3863 void MacroAssembler::set_last_Java_frame(Register java_thread,
3864 Register last_java_sp,
3865 Register last_java_fp,
3866 address last_java_pc) {
3867 vzeroupper();
3868 // determine java_thread register
3869 if (!java_thread->is_valid()) {
3870 java_thread = rdi;
3871 get_thread(java_thread);
3872 }
3873 // determine last_java_sp register
3874 if (!last_java_sp->is_valid()) {
3875 last_java_sp = rsp;
3876 }
3877
3878 // last_java_fp is optional
3879
3880 if (last_java_fp->is_valid()) {
3881 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3882 }
3883
3884 // last_java_pc is optional
3885
3886 if (last_java_pc != NULL) {
3887 lea(Address(java_thread,
3888 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3889 InternalAddress(last_java_pc));
3890
3891 }
3892 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3893 }
3894
3895 void MacroAssembler::shlptr(Register dst, int imm8) {
3896 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3897 }
3898
3899 void MacroAssembler::shrptr(Register dst, int imm8) {
3900 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3901 }
3902
3903 void MacroAssembler::sign_extend_byte(Register reg) {
3904 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3905 movsbl(reg, reg); // movsxb
3906 } else {
3907 shll(reg, 24);
3908 sarl(reg, 24);
3909 }
3910 }
3911
3912 void MacroAssembler::sign_extend_short(Register reg) {
3913 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3914 movswl(reg, reg); // movsxw
3915 } else {
3916 shll(reg, 16);
3917 sarl(reg, 16);
3918 }
3919 }
3920
3921 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3922 assert(reachable(src), "Address should be reachable");
3923 testl(dst, as_Address(src));
3924 }
3925
3926 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3927 int dst_enc = dst->encoding();
3928 int src_enc = src->encoding();
3929 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3930 Assembler::pcmpeqb(dst, src);
3931 } else if ((dst_enc < 16) && (src_enc < 16)) {
3932 Assembler::pcmpeqb(dst, src);
3933 } else if (src_enc < 16) {
3934 push_zmm(xmm0);
3935 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3936 Assembler::pcmpeqb(xmm0, src);
3937 movdqu(dst, xmm0);
3938 pop_zmm(xmm0);
3939 } else if (dst_enc < 16) {
3940 push_zmm(xmm0);
3941 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3942 Assembler::pcmpeqb(dst, xmm0);
3943 pop_zmm(xmm0);
3944 } else {
3945 push_zmm(xmm0);
3946 push_zmm(xmm1);
3947 movdqu(xmm0, src);
3948 movdqu(xmm1, dst);
3949 Assembler::pcmpeqb(xmm1, xmm0);
3950 movdqu(dst, xmm1);
3951 pop_zmm(xmm1);
3952 pop_zmm(xmm0);
3953 }
3954 }
3955
3956 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3957 int dst_enc = dst->encoding();
3958 int src_enc = src->encoding();
3959 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3960 Assembler::pcmpeqw(dst, src);
3961 } else if ((dst_enc < 16) && (src_enc < 16)) {
3962 Assembler::pcmpeqw(dst, src);
3963 } else if (src_enc < 16) {
3964 push_zmm(xmm0);
3965 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3966 Assembler::pcmpeqw(xmm0, src);
3967 movdqu(dst, xmm0);
3968 pop_zmm(xmm0);
3969 } else if (dst_enc < 16) {
3970 push_zmm(xmm0);
3971 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3972 Assembler::pcmpeqw(dst, xmm0);
3973 pop_zmm(xmm0);
3974 } else {
3975 push_zmm(xmm0);
3976 push_zmm(xmm1);
3977 movdqu(xmm0, src);
3978 movdqu(xmm1, dst);
3979 Assembler::pcmpeqw(xmm1, xmm0);
3980 movdqu(dst, xmm1);
3981 pop_zmm(xmm1);
3982 pop_zmm(xmm0);
3983 }
3984 }
3985
3986 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3987 int dst_enc = dst->encoding();
3988 if (dst_enc < 16) {
3989 Assembler::pcmpestri(dst, src, imm8);
3990 } else {
3991 push_zmm(xmm0);
3992 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3993 Assembler::pcmpestri(xmm0, src, imm8);
3994 movdqu(dst, xmm0);
3995 pop_zmm(xmm0);
3996 }
3997 }
3998
3999 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
4000 int dst_enc = dst->encoding();
4001 int src_enc = src->encoding();
4002 if ((dst_enc < 16) && (src_enc < 16)) {
4003 Assembler::pcmpestri(dst, src, imm8);
4004 } else if (src_enc < 16) {
4005 push_zmm(xmm0);
4006 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4007 Assembler::pcmpestri(xmm0, src, imm8);
4008 movdqu(dst, xmm0);
4009 pop_zmm(xmm0);
4010 } else if (dst_enc < 16) {
4011 push_zmm(xmm0);
4012 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4013 Assembler::pcmpestri(dst, xmm0, imm8);
4014 pop_zmm(xmm0);
4015 } else {
4016 push_zmm(xmm0);
4017 push_zmm(xmm1);
4018 movdqu(xmm0, src);
4019 movdqu(xmm1, dst);
4020 Assembler::pcmpestri(xmm1, xmm0, imm8);
4021 movdqu(dst, xmm1);
4022 pop_zmm(xmm1);
4023 pop_zmm(xmm0);
4024 }
4025 }
4026
4027 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
4028 int dst_enc = dst->encoding();
4029 int src_enc = src->encoding();
4030 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4031 Assembler::pmovzxbw(dst, src);
4032 } else if ((dst_enc < 16) && (src_enc < 16)) {
4033 Assembler::pmovzxbw(dst, src);
4034 } else if (src_enc < 16) {
4035 push_zmm(xmm0);
4036 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4037 Assembler::pmovzxbw(xmm0, src);
4038 movdqu(dst, xmm0);
4039 pop_zmm(xmm0);
4040 } else if (dst_enc < 16) {
4041 push_zmm(xmm0);
4042 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4043 Assembler::pmovzxbw(dst, xmm0);
4044 pop_zmm(xmm0);
4045 } else {
4046 push_zmm(xmm0);
4047 push_zmm(xmm1);
4048 movdqu(xmm0, src);
4049 movdqu(xmm1, dst);
4050 Assembler::pmovzxbw(xmm1, xmm0);
4051 movdqu(dst, xmm1);
4052 pop_zmm(xmm1);
4053 pop_zmm(xmm0);
4054 }
4055 }
4056
4057 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
4058 int dst_enc = dst->encoding();
4059 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4060 Assembler::pmovzxbw(dst, src);
4061 } else if (dst_enc < 16) {
4062 Assembler::pmovzxbw(dst, src);
4063 } else {
4064 push_zmm(xmm0);
4065 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4066 Assembler::pmovzxbw(xmm0, src);
4067 movdqu(dst, xmm0);
4068 pop_zmm(xmm0);
4069 }
4070 }
4071
4072 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
4073 int src_enc = src->encoding();
4074 if (src_enc < 16) {
4075 Assembler::pmovmskb(dst, src);
4076 } else {
4077 push_zmm(xmm0);
4078 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4079 Assembler::pmovmskb(dst, xmm0);
4080 pop_zmm(xmm0);
4081 }
4082 }
4083
4084 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
4085 int dst_enc = dst->encoding();
4086 int src_enc = src->encoding();
4087 if ((dst_enc < 16) && (src_enc < 16)) {
4088 Assembler::ptest(dst, src);
4089 } else if (src_enc < 16) {
4090 push_zmm(xmm0);
4091 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4092 Assembler::ptest(xmm0, src);
4093 pop_zmm(xmm0);
4094 } else if (dst_enc < 16) {
4095 push_zmm(xmm0);
4096 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4097 Assembler::ptest(dst, xmm0);
4098 pop_zmm(xmm0);
4099 } else {
4100 push_zmm(xmm0);
4101 push_zmm(xmm1);
4102 movdqu(xmm0, src);
4103 movdqu(xmm1, dst);
4104 Assembler::ptest(xmm1, xmm0);
4105 pop_zmm(xmm1);
4106 pop_zmm(xmm0);
4107 }
4108 }
4109
4110 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4111 if (reachable(src)) {
4112 Assembler::sqrtsd(dst, as_Address(src));
4113 } else {
4114 lea(rscratch1, src);
4115 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4116 }
4117 }
4118
4119 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4120 if (reachable(src)) {
4121 Assembler::sqrtss(dst, as_Address(src));
4122 } else {
4123 lea(rscratch1, src);
4124 Assembler::sqrtss(dst, Address(rscratch1, 0));
4125 }
4126 }
4127
4128 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4129 if (reachable(src)) {
4130 Assembler::subsd(dst, as_Address(src));
4131 } else {
4132 lea(rscratch1, src);
4133 Assembler::subsd(dst, Address(rscratch1, 0));
4134 }
4135 }
4136
4137 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4138 if (reachable(src)) {
4139 Assembler::subss(dst, as_Address(src));
4140 } else {
4141 lea(rscratch1, src);
4142 Assembler::subss(dst, Address(rscratch1, 0));
4143 }
4144 }
4145
4146 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4147 if (reachable(src)) {
4148 Assembler::ucomisd(dst, as_Address(src));
4149 } else {
4150 lea(rscratch1, src);
4151 Assembler::ucomisd(dst, Address(rscratch1, 0));
4152 }
4153 }
4154
4155 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4156 if (reachable(src)) {
4157 Assembler::ucomiss(dst, as_Address(src));
4158 } else {
4159 lea(rscratch1, src);
4160 Assembler::ucomiss(dst, Address(rscratch1, 0));
4161 }
4162 }
4163
4164 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4165 // Used in sign-bit flipping with aligned address.
4166 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4167 if (reachable(src)) {
4168 Assembler::xorpd(dst, as_Address(src));
4169 } else {
4170 lea(rscratch1, src);
4171 Assembler::xorpd(dst, Address(rscratch1, 0));
4172 }
4173 }
4174
4175 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4176 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4177 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4178 }
4179 else {
4180 Assembler::xorpd(dst, src);
4181 }
4182 }
4183
4184 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4185 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4186 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4187 } else {
4188 Assembler::xorps(dst, src);
4189 }
4190 }
4191
4192 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4193 // Used in sign-bit flipping with aligned address.
4194 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4195 if (reachable(src)) {
4196 Assembler::xorps(dst, as_Address(src));
4197 } else {
4198 lea(rscratch1, src);
4199 Assembler::xorps(dst, Address(rscratch1, 0));
4200 }
4201 }
4202
4203 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4204 // Used in sign-bit flipping with aligned address.
4205 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4206 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4207 if (reachable(src)) {
4208 Assembler::pshufb(dst, as_Address(src));
4209 } else {
4210 lea(rscratch1, src);
4211 Assembler::pshufb(dst, Address(rscratch1, 0));
4212 }
4213 }
4214
4215 // AVX 3-operands instructions
4216
4217 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4218 if (reachable(src)) {
4219 vaddsd(dst, nds, as_Address(src));
4220 } else {
4221 lea(rscratch1, src);
4222 vaddsd(dst, nds, Address(rscratch1, 0));
4223 }
4224 }
4225
4226 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4227 if (reachable(src)) {
4228 vaddss(dst, nds, as_Address(src));
4229 } else {
4230 lea(rscratch1, src);
4231 vaddss(dst, nds, Address(rscratch1, 0));
4232 }
4233 }
4234
4235 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4236 int dst_enc = dst->encoding();
4237 int nds_enc = nds->encoding();
4238 int src_enc = src->encoding();
4239 if ((dst_enc < 16) && (nds_enc < 16)) {
4240 vandps(dst, nds, negate_field, vector_len);
4241 } else if ((src_enc < 16) && (dst_enc < 16)) {
4242 // Use src scratch register
4243 evmovdqul(src, nds, Assembler::AVX_512bit);
4244 vandps(dst, src, negate_field, vector_len);
4245 } else if (dst_enc < 16) {
4246 evmovdqul(dst, nds, Assembler::AVX_512bit);
4247 vandps(dst, dst, negate_field, vector_len);
4248 } else if (nds_enc < 16) {
4249 vandps(nds, nds, negate_field, vector_len);
4250 evmovdqul(dst, nds, Assembler::AVX_512bit);
4251 } else if (src_enc < 16) {
4252 evmovdqul(src, nds, Assembler::AVX_512bit);
4253 vandps(src, src, negate_field, vector_len);
4254 evmovdqul(dst, src, Assembler::AVX_512bit);
4255 } else {
4256 if (src_enc != dst_enc) {
4257 // Use src scratch register
4258 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4259 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4260 vandps(xmm0, xmm0, negate_field, vector_len);
4261 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4262 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4263 } else {
4264 push_zmm(xmm0);
4265 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4266 vandps(xmm0, xmm0, negate_field, vector_len);
4267 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4268 pop_zmm(xmm0);
4269 }
4270 }
4271 }
4272
4273 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4274 int dst_enc = dst->encoding();
4275 int nds_enc = nds->encoding();
4276 int src_enc = src->encoding();
4277 if ((dst_enc < 16) && (nds_enc < 16)) {
4278 vandpd(dst, nds, negate_field, vector_len);
4279 } else if ((src_enc < 16) && (dst_enc < 16)) {
4280 // Use src scratch register
4281 evmovdqul(src, nds, Assembler::AVX_512bit);
4282 vandpd(dst, src, negate_field, vector_len);
4283 } else if (dst_enc < 16) {
4284 evmovdqul(dst, nds, Assembler::AVX_512bit);
4285 vandpd(dst, dst, negate_field, vector_len);
4286 } else if (nds_enc < 16) {
4287 vandpd(nds, nds, negate_field, vector_len);
4288 evmovdqul(dst, nds, Assembler::AVX_512bit);
4289 } else if (src_enc < 16) {
4290 evmovdqul(src, nds, Assembler::AVX_512bit);
4291 vandpd(src, src, negate_field, vector_len);
4292 evmovdqul(dst, src, Assembler::AVX_512bit);
4293 } else {
4294 if (src_enc != dst_enc) {
4295 evmovdqul(src, xmm0, Assembler::AVX_512bit);
4296 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4297 vandpd(xmm0, xmm0, negate_field, vector_len);
4298 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4299 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4300 } else {
4301 push_zmm(xmm0);
4302 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4303 vandpd(xmm0, xmm0, negate_field, vector_len);
4304 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4305 pop_zmm(xmm0);
4306 }
4307 }
4308 }
4309
4310 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4311 int dst_enc = dst->encoding();
4312 int nds_enc = nds->encoding();
4313 int src_enc = src->encoding();
4314 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4315 Assembler::vpaddb(dst, nds, src, vector_len);
4316 } else if ((dst_enc < 16) && (src_enc < 16)) {
4317 Assembler::vpaddb(dst, dst, src, vector_len);
4318 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4319 // use nds as scratch for src
4320 evmovdqul(nds, src, Assembler::AVX_512bit);
4321 Assembler::vpaddb(dst, dst, nds, vector_len);
4322 } else if ((src_enc < 16) && (nds_enc < 16)) {
4323 // use nds as scratch for dst
4324 evmovdqul(nds, dst, Assembler::AVX_512bit);
4325 Assembler::vpaddb(nds, nds, src, vector_len);
4326 evmovdqul(dst, nds, Assembler::AVX_512bit);
4327 } else if (dst_enc < 16) {
4328 // use nds as scatch for xmm0 to hold src
4329 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4330 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4331 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4332 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4333 } else {
4334 // worse case scenario, all regs are in the upper bank
4335 push_zmm(xmm1);
4336 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4337 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4338 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4339 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4340 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4341 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4342 pop_zmm(xmm1);
4343 }
4344 }
4345
4346 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4347 int dst_enc = dst->encoding();
4348 int nds_enc = nds->encoding();
4349 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4350 Assembler::vpaddb(dst, nds, src, vector_len);
4351 } else if (dst_enc < 16) {
4352 Assembler::vpaddb(dst, dst, src, vector_len);
4353 } else if (nds_enc < 16) {
4354 // implies dst_enc in upper bank with src as scratch
4355 evmovdqul(nds, dst, Assembler::AVX_512bit);
4356 Assembler::vpaddb(nds, nds, src, vector_len);
4357 evmovdqul(dst, nds, Assembler::AVX_512bit);
4358 } else {
4359 // worse case scenario, all regs in upper bank
4360 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4361 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4362 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4363 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4364 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4365 }
4366 }
4367
4368 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4369 int dst_enc = dst->encoding();
4370 int nds_enc = nds->encoding();
4371 int src_enc = src->encoding();
4372 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4373 Assembler::vpaddw(dst, nds, src, vector_len);
4374 } else if ((dst_enc < 16) && (src_enc < 16)) {
4375 Assembler::vpaddw(dst, dst, src, vector_len);
4376 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4377 // use nds as scratch for src
4378 evmovdqul(nds, src, Assembler::AVX_512bit);
4379 Assembler::vpaddw(dst, dst, nds, vector_len);
4380 } else if ((src_enc < 16) && (nds_enc < 16)) {
4381 // use nds as scratch for dst
4382 evmovdqul(nds, dst, Assembler::AVX_512bit);
4383 Assembler::vpaddw(nds, nds, src, vector_len);
4384 evmovdqul(dst, nds, Assembler::AVX_512bit);
4385 } else if (dst_enc < 16) {
4386 // use nds as scatch for xmm0 to hold src
4387 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4388 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4389 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4390 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4391 } else {
4392 // worse case scenario, all regs are in the upper bank
4393 push_zmm(xmm1);
4394 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4395 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4396 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4397 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4398 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4399 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4400 pop_zmm(xmm1);
4401 }
4402 }
4403
4404 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4405 int dst_enc = dst->encoding();
4406 int nds_enc = nds->encoding();
4407 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4408 Assembler::vpaddw(dst, nds, src, vector_len);
4409 } else if (dst_enc < 16) {
4410 Assembler::vpaddw(dst, dst, src, vector_len);
4411 } else if (nds_enc < 16) {
4412 // implies dst_enc in upper bank with nds as scratch
4413 evmovdqul(nds, dst, Assembler::AVX_512bit);
4414 Assembler::vpaddw(nds, nds, src, vector_len);
4415 evmovdqul(dst, nds, Assembler::AVX_512bit);
4416 } else {
4417 // worse case scenario, all regs in upper bank
4418 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4419 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4420 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4421 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4422 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4423 }
4424 }
4425
4426 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4427 if (reachable(src)) {
4428 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4429 } else {
4430 lea(rscratch1, src);
4431 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4432 }
4433 }
4434
4435 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4436 int dst_enc = dst->encoding();
4437 int src_enc = src->encoding();
4438 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4439 Assembler::vpbroadcastw(dst, src);
4440 } else if ((dst_enc < 16) && (src_enc < 16)) {
4441 Assembler::vpbroadcastw(dst, src);
4442 } else if (src_enc < 16) {
4443 push_zmm(xmm0);
4444 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4445 Assembler::vpbroadcastw(xmm0, src);
4446 movdqu(dst, xmm0);
4447 pop_zmm(xmm0);
4448 } else if (dst_enc < 16) {
4449 push_zmm(xmm0);
4450 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4451 Assembler::vpbroadcastw(dst, xmm0);
4452 pop_zmm(xmm0);
4453 } else {
4454 push_zmm(xmm0);
4455 push_zmm(xmm1);
4456 movdqu(xmm0, src);
4457 movdqu(xmm1, dst);
4458 Assembler::vpbroadcastw(xmm1, xmm0);
4459 movdqu(dst, xmm1);
4460 pop_zmm(xmm1);
4461 pop_zmm(xmm0);
4462 }
4463 }
4464
4465 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4466 int dst_enc = dst->encoding();
4467 int nds_enc = nds->encoding();
4468 int src_enc = src->encoding();
4469 assert(dst_enc == nds_enc, "");
4470 if ((dst_enc < 16) && (src_enc < 16)) {
4471 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4472 } else if (src_enc < 16) {
4473 push_zmm(xmm0);
4474 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4475 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4476 movdqu(dst, xmm0);
4477 pop_zmm(xmm0);
4478 } else if (dst_enc < 16) {
4479 push_zmm(xmm0);
4480 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4481 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4482 pop_zmm(xmm0);
4483 } else {
4484 push_zmm(xmm0);
4485 push_zmm(xmm1);
4486 movdqu(xmm0, src);
4487 movdqu(xmm1, dst);
4488 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4489 movdqu(dst, xmm1);
4490 pop_zmm(xmm1);
4491 pop_zmm(xmm0);
4492 }
4493 }
4494
4495 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4496 int dst_enc = dst->encoding();
4497 int nds_enc = nds->encoding();
4498 int src_enc = src->encoding();
4499 assert(dst_enc == nds_enc, "");
4500 if ((dst_enc < 16) && (src_enc < 16)) {
4501 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4502 } else if (src_enc < 16) {
4503 push_zmm(xmm0);
4504 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4505 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4506 movdqu(dst, xmm0);
4507 pop_zmm(xmm0);
4508 } else if (dst_enc < 16) {
4509 push_zmm(xmm0);
4510 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4511 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4512 pop_zmm(xmm0);
4513 } else {
4514 push_zmm(xmm0);
4515 push_zmm(xmm1);
4516 movdqu(xmm0, src);
4517 movdqu(xmm1, dst);
4518 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4519 movdqu(dst, xmm1);
4520 pop_zmm(xmm1);
4521 pop_zmm(xmm0);
4522 }
4523 }
4524
4525 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4526 int dst_enc = dst->encoding();
4527 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4528 Assembler::vpmovzxbw(dst, src, vector_len);
4529 } else if (dst_enc < 16) {
4530 Assembler::vpmovzxbw(dst, src, vector_len);
4531 } else {
4532 push_zmm(xmm0);
4533 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4534 Assembler::vpmovzxbw(xmm0, src, vector_len);
4535 movdqu(dst, xmm0);
4536 pop_zmm(xmm0);
4537 }
4538 }
4539
4540 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4541 int src_enc = src->encoding();
4542 if (src_enc < 16) {
4543 Assembler::vpmovmskb(dst, src);
4544 } else {
4545 push_zmm(xmm0);
4546 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4547 Assembler::vpmovmskb(dst, xmm0);
4548 pop_zmm(xmm0);
4549 }
4550 }
4551
4552 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4553 int dst_enc = dst->encoding();
4554 int nds_enc = nds->encoding();
4555 int src_enc = src->encoding();
4556 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4557 Assembler::vpmullw(dst, nds, src, vector_len);
4558 } else if ((dst_enc < 16) && (src_enc < 16)) {
4559 Assembler::vpmullw(dst, dst, src, vector_len);
4560 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4561 // use nds as scratch for src
4562 evmovdqul(nds, src, Assembler::AVX_512bit);
4563 Assembler::vpmullw(dst, dst, nds, vector_len);
4564 } else if ((src_enc < 16) && (nds_enc < 16)) {
4565 // use nds as scratch for dst
4566 evmovdqul(nds, dst, Assembler::AVX_512bit);
4567 Assembler::vpmullw(nds, nds, src, vector_len);
4568 evmovdqul(dst, nds, Assembler::AVX_512bit);
4569 } else if (dst_enc < 16) {
4570 // use nds as scatch for xmm0 to hold src
4571 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4572 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4573 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4574 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4575 } else {
4576 // worse case scenario, all regs are in the upper bank
4577 push_zmm(xmm1);
4578 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4579 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4580 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4581 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4582 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4583 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4584 pop_zmm(xmm1);
4585 }
4586 }
4587
4588 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4589 int dst_enc = dst->encoding();
4590 int nds_enc = nds->encoding();
4591 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4592 Assembler::vpmullw(dst, nds, src, vector_len);
4593 } else if (dst_enc < 16) {
4594 Assembler::vpmullw(dst, dst, src, vector_len);
4595 } else if (nds_enc < 16) {
4596 // implies dst_enc in upper bank with src as scratch
4597 evmovdqul(nds, dst, Assembler::AVX_512bit);
4598 Assembler::vpmullw(nds, nds, src, vector_len);
4599 evmovdqul(dst, nds, Assembler::AVX_512bit);
4600 } else {
4601 // worse case scenario, all regs in upper bank
4602 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4603 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4604 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4605 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4606 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4607 }
4608 }
4609
4610 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4611 int dst_enc = dst->encoding();
4612 int nds_enc = nds->encoding();
4613 int src_enc = src->encoding();
4614 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4615 Assembler::vpsubb(dst, nds, src, vector_len);
4616 } else if ((dst_enc < 16) && (src_enc < 16)) {
4617 Assembler::vpsubb(dst, dst, src, vector_len);
4618 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4619 // use nds as scratch for src
4620 evmovdqul(nds, src, Assembler::AVX_512bit);
4621 Assembler::vpsubb(dst, dst, nds, vector_len);
4622 } else if ((src_enc < 16) && (nds_enc < 16)) {
4623 // use nds as scratch for dst
4624 evmovdqul(nds, dst, Assembler::AVX_512bit);
4625 Assembler::vpsubb(nds, nds, src, vector_len);
4626 evmovdqul(dst, nds, Assembler::AVX_512bit);
4627 } else if (dst_enc < 16) {
4628 // use nds as scatch for xmm0 to hold src
4629 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4630 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4631 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4632 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4633 } else {
4634 // worse case scenario, all regs are in the upper bank
4635 push_zmm(xmm1);
4636 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4637 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4638 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4639 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4640 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4641 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4642 pop_zmm(xmm1);
4643 }
4644 }
4645
4646 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4647 int dst_enc = dst->encoding();
4648 int nds_enc = nds->encoding();
4649 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4650 Assembler::vpsubb(dst, nds, src, vector_len);
4651 } else if (dst_enc < 16) {
4652 Assembler::vpsubb(dst, dst, src, vector_len);
4653 } else if (nds_enc < 16) {
4654 // implies dst_enc in upper bank with src as scratch
4655 evmovdqul(nds, dst, Assembler::AVX_512bit);
4656 Assembler::vpsubb(nds, nds, src, vector_len);
4657 evmovdqul(dst, nds, Assembler::AVX_512bit);
4658 } else {
4659 // worse case scenario, all regs in upper bank
4660 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4661 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4662 Assembler::vpsubb(xmm0, xmm0, src, vector_len);
4663 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4664 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4665 }
4666 }
4667
4668 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4669 int dst_enc = dst->encoding();
4670 int nds_enc = nds->encoding();
4671 int src_enc = src->encoding();
4672 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4673 Assembler::vpsubw(dst, nds, src, vector_len);
4674 } else if ((dst_enc < 16) && (src_enc < 16)) {
4675 Assembler::vpsubw(dst, dst, src, vector_len);
4676 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4677 // use nds as scratch for src
4678 evmovdqul(nds, src, Assembler::AVX_512bit);
4679 Assembler::vpsubw(dst, dst, nds, vector_len);
4680 } else if ((src_enc < 16) && (nds_enc < 16)) {
4681 // use nds as scratch for dst
4682 evmovdqul(nds, dst, Assembler::AVX_512bit);
4683 Assembler::vpsubw(nds, nds, src, vector_len);
4684 evmovdqul(dst, nds, Assembler::AVX_512bit);
4685 } else if (dst_enc < 16) {
4686 // use nds as scatch for xmm0 to hold src
4687 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4688 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4689 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4690 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4691 } else {
4692 // worse case scenario, all regs are in the upper bank
4693 push_zmm(xmm1);
4694 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4695 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4696 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4697 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4698 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4699 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4700 pop_zmm(xmm1);
4701 }
4702 }
4703
4704 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4705 int dst_enc = dst->encoding();
4706 int nds_enc = nds->encoding();
4707 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4708 Assembler::vpsubw(dst, nds, src, vector_len);
4709 } else if (dst_enc < 16) {
4710 Assembler::vpsubw(dst, dst, src, vector_len);
4711 } else if (nds_enc < 16) {
4712 // implies dst_enc in upper bank with src as scratch
4713 evmovdqul(nds, dst, Assembler::AVX_512bit);
4714 Assembler::vpsubw(nds, nds, src, vector_len);
4715 evmovdqul(dst, nds, Assembler::AVX_512bit);
4716 } else {
4717 // worse case scenario, all regs in upper bank
4718 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4719 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4720 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4721 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4722 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4723 }
4724 }
4725
4726 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4727 int dst_enc = dst->encoding();
4728 int nds_enc = nds->encoding();
4729 int shift_enc = shift->encoding();
4730 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4731 Assembler::vpsraw(dst, nds, shift, vector_len);
4732 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4733 Assembler::vpsraw(dst, dst, shift, vector_len);
4734 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4735 // use nds as scratch with shift
4736 evmovdqul(nds, shift, Assembler::AVX_512bit);
4737 Assembler::vpsraw(dst, dst, nds, vector_len);
4738 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4739 // use nds as scratch with dst
4740 evmovdqul(nds, dst, Assembler::AVX_512bit);
4741 Assembler::vpsraw(nds, nds, shift, vector_len);
4742 evmovdqul(dst, nds, Assembler::AVX_512bit);
4743 } else if (dst_enc < 16) {
4744 // use nds to save a copy of xmm0 and hold shift
4745 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4746 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4747 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4748 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4749 } else if (nds_enc < 16) {
4750 // use nds and dst as temps
4751 evmovdqul(nds, dst, Assembler::AVX_512bit);
4752 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4753 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4754 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4755 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4756 evmovdqul(dst, nds, Assembler::AVX_512bit);
4757 } else {
4758 // worse case scenario, all regs are in the upper bank
4759 push_zmm(xmm1);
4760 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4761 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4762 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4763 Assembler::vpsraw(xmm0, xmm0, xmm1, vector_len);
4764 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4765 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4766 pop_zmm(xmm1);
4767 }
4768 }
4769
4770 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4771 int dst_enc = dst->encoding();
4772 int nds_enc = nds->encoding();
4773 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4774 Assembler::vpsraw(dst, nds, shift, vector_len);
4775 } else if (dst_enc < 16) {
4776 Assembler::vpsraw(dst, dst, shift, vector_len);
4777 } else if (nds_enc < 16) {
4778 // use nds as scratch
4779 evmovdqul(nds, dst, Assembler::AVX_512bit);
4780 Assembler::vpsraw(nds, nds, shift, vector_len);
4781 evmovdqul(dst, nds, Assembler::AVX_512bit);
4782 } else {
4783 // use nds as scratch for xmm0
4784 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4785 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4786 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4787 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4788 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4789 }
4790 }
4791
4792 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4793 int dst_enc = dst->encoding();
4794 int nds_enc = nds->encoding();
4795 int shift_enc = shift->encoding();
4796 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4797 Assembler::vpsrlw(dst, nds, shift, vector_len);
4798 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4799 Assembler::vpsrlw(dst, dst, shift, vector_len);
4800 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4801 // use nds as scratch with shift
4802 evmovdqul(nds, shift, Assembler::AVX_512bit);
4803 Assembler::vpsrlw(dst, dst, nds, vector_len);
4804 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4805 // use nds as scratch with dst
4806 evmovdqul(nds, dst, Assembler::AVX_512bit);
4807 Assembler::vpsrlw(nds, nds, shift, vector_len);
4808 evmovdqul(dst, nds, Assembler::AVX_512bit);
4809 } else if (dst_enc < 16) {
4810 // use nds to save a copy of xmm0 and hold shift
4811 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4812 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4813 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4814 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4815 } else if (nds_enc < 16) {
4816 // use nds and dst as temps
4817 evmovdqul(nds, dst, Assembler::AVX_512bit);
4818 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4819 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4820 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4821 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4822 evmovdqul(dst, nds, Assembler::AVX_512bit);
4823 } else {
4824 // worse case scenario, all regs are in the upper bank
4825 push_zmm(xmm1);
4826 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4827 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4828 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4829 Assembler::vpsrlw(xmm0, xmm0, xmm1, vector_len);
4830 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4831 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4832 pop_zmm(xmm1);
4833 }
4834 }
4835
4836 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4837 int dst_enc = dst->encoding();
4838 int nds_enc = nds->encoding();
4839 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4840 Assembler::vpsrlw(dst, nds, shift, vector_len);
4841 } else if (dst_enc < 16) {
4842 Assembler::vpsrlw(dst, dst, shift, vector_len);
4843 } else if (nds_enc < 16) {
4844 // use nds as scratch
4845 evmovdqul(nds, dst, Assembler::AVX_512bit);
4846 Assembler::vpsrlw(nds, nds, shift, vector_len);
4847 evmovdqul(dst, nds, Assembler::AVX_512bit);
4848 } else {
4849 // use nds as scratch for xmm0
4850 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4851 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4852 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4853 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4854 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4855 }
4856 }
4857
4858 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4859 int dst_enc = dst->encoding();
4860 int nds_enc = nds->encoding();
4861 int shift_enc = shift->encoding();
4862 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4863 Assembler::vpsllw(dst, nds, shift, vector_len);
4864 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4865 Assembler::vpsllw(dst, dst, shift, vector_len);
4866 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4867 // use nds as scratch with shift
4868 evmovdqul(nds, shift, Assembler::AVX_512bit);
4869 Assembler::vpsllw(dst, dst, nds, vector_len);
4870 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4871 // use nds as scratch with dst
4872 evmovdqul(nds, dst, Assembler::AVX_512bit);
4873 Assembler::vpsllw(nds, nds, shift, vector_len);
4874 evmovdqul(dst, nds, Assembler::AVX_512bit);
4875 } else if (dst_enc < 16) {
4876 // use nds to save a copy of xmm0 and hold shift
4877 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4878 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4879 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4880 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4881 } else if (nds_enc < 16) {
4882 // use nds and dst as temps
4883 evmovdqul(nds, dst, Assembler::AVX_512bit);
4884 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4885 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4886 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4887 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4888 evmovdqul(dst, nds, Assembler::AVX_512bit);
4889 } else {
4890 // worse case scenario, all regs are in the upper bank
4891 push_zmm(xmm1);
4892 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4893 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4894 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4895 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4896 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4897 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4898 pop_zmm(xmm1);
4899 }
4900 }
4901
4902 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4903 int dst_enc = dst->encoding();
4904 int nds_enc = nds->encoding();
4905 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4906 Assembler::vpsllw(dst, nds, shift, vector_len);
4907 } else if (dst_enc < 16) {
4908 Assembler::vpsllw(dst, dst, shift, vector_len);
4909 } else if (nds_enc < 16) {
4910 // use nds as scratch
4911 evmovdqul(nds, dst, Assembler::AVX_512bit);
4912 Assembler::vpsllw(nds, nds, shift, vector_len);
4913 evmovdqul(dst, nds, Assembler::AVX_512bit);
4914 } else {
4915 // use nds as scratch for xmm0
4916 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4917 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4918 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4919 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4920 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4921 }
4922 }
4923
4924 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4925 int dst_enc = dst->encoding();
4926 int src_enc = src->encoding();
4927 if ((dst_enc < 16) && (src_enc < 16)) {
4928 Assembler::vptest(dst, src);
4929 } else if (src_enc < 16) {
4930 push_zmm(xmm0);
4931 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4932 Assembler::vptest(xmm0, src);
4933 pop_zmm(xmm0);
4934 } else if (dst_enc < 16) {
4935 push_zmm(xmm0);
4936 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4937 Assembler::vptest(dst, xmm0);
4938 pop_zmm(xmm0);
4939 } else {
4940 push_zmm(xmm0);
4941 push_zmm(xmm1);
4942 movdqu(xmm0, src);
4943 movdqu(xmm1, dst);
4944 Assembler::vptest(xmm1, xmm0);
4945 pop_zmm(xmm1);
4946 pop_zmm(xmm0);
4947 }
4948 }
4949
4950 // This instruction exists within macros, ergo we cannot control its input
4951 // when emitted through those patterns.
4952 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4953 if (VM_Version::supports_avx512nobw()) {
4954 int dst_enc = dst->encoding();
4955 int src_enc = src->encoding();
4956 if (dst_enc == src_enc) {
4957 if (dst_enc < 16) {
4958 Assembler::punpcklbw(dst, src);
4959 } else {
4960 push_zmm(xmm0);
4961 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4962 Assembler::punpcklbw(xmm0, xmm0);
4963 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4964 pop_zmm(xmm0);
4965 }
4966 } else {
4967 if ((src_enc < 16) && (dst_enc < 16)) {
4968 Assembler::punpcklbw(dst, src);
4969 } else if (src_enc < 16) {
4970 push_zmm(xmm0);
4971 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4972 Assembler::punpcklbw(xmm0, src);
4973 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4974 pop_zmm(xmm0);
4975 } else if (dst_enc < 16) {
4976 push_zmm(xmm0);
4977 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4978 Assembler::punpcklbw(dst, xmm0);
4979 pop_zmm(xmm0);
4980 } else {
4981 push_zmm(xmm0);
4982 push_zmm(xmm1);
4983 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4984 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4985 Assembler::punpcklbw(xmm0, xmm1);
4986 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4987 pop_zmm(xmm1);
4988 pop_zmm(xmm0);
4989 }
4990 }
4991 } else {
4992 Assembler::punpcklbw(dst, src);
4993 }
4994 }
4995
4996 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4997 if (VM_Version::supports_avx512vl()) {
4998 Assembler::pshufd(dst, src, mode);
4999 } else {
5000 int dst_enc = dst->encoding();
5001 if (dst_enc < 16) {
5002 Assembler::pshufd(dst, src, mode);
5003 } else {
5004 push_zmm(xmm0);
5005 Assembler::pshufd(xmm0, src, mode);
5006 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5007 pop_zmm(xmm0);
5008 }
5009 }
5010 }
5011
5012 // This instruction exists within macros, ergo we cannot control its input
5013 // when emitted through those patterns.
5014 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5015 if (VM_Version::supports_avx512nobw()) {
5016 int dst_enc = dst->encoding();
5017 int src_enc = src->encoding();
5018 if (dst_enc == src_enc) {
5019 if (dst_enc < 16) {
5020 Assembler::pshuflw(dst, src, mode);
5021 } else {
5022 push_zmm(xmm0);
5023 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5024 Assembler::pshuflw(xmm0, xmm0, mode);
5025 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5026 pop_zmm(xmm0);
5027 }
5028 } else {
5029 if ((src_enc < 16) && (dst_enc < 16)) {
5030 Assembler::pshuflw(dst, src, mode);
5031 } else if (src_enc < 16) {
5032 push_zmm(xmm0);
5033 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5034 Assembler::pshuflw(xmm0, src, mode);
5035 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5036 pop_zmm(xmm0);
5037 } else if (dst_enc < 16) {
5038 push_zmm(xmm0);
5039 evmovdqul(xmm0, src, Assembler::AVX_512bit);
5040 Assembler::pshuflw(dst, xmm0, mode);
5041 pop_zmm(xmm0);
5042 } else {
5043 push_zmm(xmm0);
5044 push_zmm(xmm1);
5045 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5046 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5047 Assembler::pshuflw(xmm0, xmm1, mode);
5048 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5049 pop_zmm(xmm1);
5050 pop_zmm(xmm0);
5051 }
5052 }
5053 } else {
5054 Assembler::pshuflw(dst, src, mode);
5055 }
5056 }
5057
5058 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5059 if (reachable(src)) {
5060 vandpd(dst, nds, as_Address(src), vector_len);
5061 } else {
5062 lea(rscratch1, src);
5063 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5064 }
5065 }
5066
5067 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5068 if (reachable(src)) {
5069 vandps(dst, nds, as_Address(src), vector_len);
5070 } else {
5071 lea(rscratch1, src);
5072 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5073 }
5074 }
5075
5076 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5077 if (reachable(src)) {
5078 vdivsd(dst, nds, as_Address(src));
5079 } else {
5080 lea(rscratch1, src);
5081 vdivsd(dst, nds, Address(rscratch1, 0));
5082 }
5083 }
5084
5085 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5086 if (reachable(src)) {
5087 vdivss(dst, nds, as_Address(src));
5088 } else {
5089 lea(rscratch1, src);
5090 vdivss(dst, nds, Address(rscratch1, 0));
5091 }
5092 }
5093
5094 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5095 if (reachable(src)) {
5096 vmulsd(dst, nds, as_Address(src));
5097 } else {
5098 lea(rscratch1, src);
5099 vmulsd(dst, nds, Address(rscratch1, 0));
5100 }
5101 }
5102
5103 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5104 if (reachable(src)) {
5105 vmulss(dst, nds, as_Address(src));
5106 } else {
5107 lea(rscratch1, src);
5108 vmulss(dst, nds, Address(rscratch1, 0));
5109 }
5110 }
5111
5112 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5113 if (reachable(src)) {
5114 vsubsd(dst, nds, as_Address(src));
5115 } else {
5116 lea(rscratch1, src);
5117 vsubsd(dst, nds, Address(rscratch1, 0));
5118 }
5119 }
5120
5121 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5122 if (reachable(src)) {
5123 vsubss(dst, nds, as_Address(src));
5124 } else {
5125 lea(rscratch1, src);
5126 vsubss(dst, nds, Address(rscratch1, 0));
5127 }
5128 }
5129
5130 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5131 int nds_enc = nds->encoding();
5132 int dst_enc = dst->encoding();
5133 bool dst_upper_bank = (dst_enc > 15);
5134 bool nds_upper_bank = (nds_enc > 15);
5135 if (VM_Version::supports_avx512novl() &&
5136 (nds_upper_bank || dst_upper_bank)) {
5137 if (dst_upper_bank) {
5138 push_zmm(xmm0);
5139 movflt(xmm0, nds);
5140 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5141 movflt(dst, xmm0);
5142 pop_zmm(xmm0);
5143 } else {
5144 movflt(dst, nds);
5145 vxorps(dst, dst, src, Assembler::AVX_128bit);
5146 }
5147 } else {
5148 vxorps(dst, nds, src, Assembler::AVX_128bit);
5149 }
5150 }
5151
5152 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5153 int nds_enc = nds->encoding();
5154 int dst_enc = dst->encoding();
5155 bool dst_upper_bank = (dst_enc > 15);
5156 bool nds_upper_bank = (nds_enc > 15);
5157 if (VM_Version::supports_avx512novl() &&
5158 (nds_upper_bank || dst_upper_bank)) {
5159 if (dst_upper_bank) {
5160 push_zmm(xmm0);
5161 movdbl(xmm0, nds);
5162 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5163 movdbl(dst, xmm0);
5164 pop_zmm(xmm0);
5165 } else {
5166 movdbl(dst, nds);
5167 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5168 }
5169 } else {
5170 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5171 }
5172 }
5173
5174 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5175 if (reachable(src)) {
5176 vxorpd(dst, nds, as_Address(src), vector_len);
5177 } else {
5178 lea(rscratch1, src);
5179 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5180 }
5181 }
5182
5183 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5184 if (reachable(src)) {
5185 vxorps(dst, nds, as_Address(src), vector_len);
5186 } else {
5187 lea(rscratch1, src);
5188 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5189 }
5190 }
5191
5192 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5193 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5194 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5195 // The inverted mask is sign-extended
5196 andptr(possibly_jweak, inverted_jweak_mask);
5197 }
5198
5199 void MacroAssembler::resolve_jobject(Register value,
5200 Register thread,
5201 Register tmp) {
5202 assert_different_registers(value, thread, tmp);
5203 Label done, not_weak;
5204 testptr(value, value);
5205 jcc(Assembler::zero, done); // Use NULL as-is.
5206 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5207 jcc(Assembler::zero, not_weak);
5208 // Resolve jweak.
5209 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5210 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
5211 verify_oop(value);
5212 jmp(done);
5213 bind(not_weak);
5214 // Resolve (untagged) jobject.
5215 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
5216 verify_oop(value);
5217 bind(done);
5218 }
5219
5220 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5221 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5222 }
5223
5224 // Force generation of a 4 byte immediate value even if it fits into 8bit
5225 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5226 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5227 }
5228
5229 void MacroAssembler::subptr(Register dst, Register src) {
5230 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5231 }
5232
5233 // C++ bool manipulation
5234 void MacroAssembler::testbool(Register dst) {
5235 if(sizeof(bool) == 1)
5236 testb(dst, 0xff);
5237 else if(sizeof(bool) == 2) {
5238 // testw implementation needed for two byte bools
5239 ShouldNotReachHere();
5240 } else if(sizeof(bool) == 4)
5241 testl(dst, dst);
5242 else
5243 // unsupported
5244 ShouldNotReachHere();
5245 }
5246
5247 void MacroAssembler::testptr(Register dst, Register src) {
5248 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5249 }
5250
5251 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5252 void MacroAssembler::tlab_allocate(Register thread, Register obj,
5253 Register var_size_in_bytes,
5254 int con_size_in_bytes,
5255 Register t1,
5256 Register t2,
5257 Label& slow_case) {
5258 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5259 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5260 }
5261
5262 // Defines obj, preserves var_size_in_bytes
5263 void MacroAssembler::eden_allocate(Register thread, Register obj,
5264 Register var_size_in_bytes,
5265 int con_size_in_bytes,
5266 Register t1,
5267 Label& slow_case) {
5268 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5269 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
5270 }
5271
5272 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5273 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5274 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5275 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5276 Label done;
5277
5278 testptr(length_in_bytes, length_in_bytes);
5279 jcc(Assembler::zero, done);
5280
5281 // initialize topmost word, divide index by 2, check if odd and test if zero
5282 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5283 #ifdef ASSERT
5284 {
5285 Label L;
5286 testptr(length_in_bytes, BytesPerWord - 1);
5287 jcc(Assembler::zero, L);
5288 stop("length must be a multiple of BytesPerWord");
5289 bind(L);
5290 }
5291 #endif
5292 Register index = length_in_bytes;
5293 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5294 if (UseIncDec) {
5295 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5296 } else {
5297 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5298 shrptr(index, 1);
5299 }
5300 #ifndef _LP64
5301 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5302 {
5303 Label even;
5304 // note: if index was a multiple of 8, then it cannot
5305 // be 0 now otherwise it must have been 0 before
5306 // => if it is even, we don't need to check for 0 again
5307 jcc(Assembler::carryClear, even);
5308 // clear topmost word (no jump would be needed if conditional assignment worked here)
5309 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5310 // index could be 0 now, must check again
5311 jcc(Assembler::zero, done);
5312 bind(even);
5313 }
5314 #endif // !_LP64
5315 // initialize remaining object fields: index is a multiple of 2 now
5316 {
5317 Label loop;
5318 bind(loop);
5319 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5320 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5321 decrement(index);
5322 jcc(Assembler::notZero, loop);
5323 }
5324
5325 bind(done);
5326 }
5327
5328 // Look up the method for a megamorphic invokeinterface call.
5329 // The target method is determined by <intf_klass, itable_index>.
5330 // The receiver klass is in recv_klass.
5331 // On success, the result will be in method_result, and execution falls through.
5332 // On failure, execution transfers to the given label.
5333 void MacroAssembler::lookup_interface_method(Register recv_klass,
5334 Register intf_klass,
5335 RegisterOrConstant itable_index,
5336 Register method_result,
5337 Register scan_temp,
5338 Label& L_no_such_interface,
5339 bool return_method) {
5340 assert_different_registers(recv_klass, intf_klass, scan_temp);
5341 assert_different_registers(method_result, intf_klass, scan_temp);
5342 assert(recv_klass != method_result || !return_method,
5343 "recv_klass can be destroyed when method isn't needed");
5344
5345 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5346 "caller must use same register for non-constant itable index as for method");
5347
5348 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5349 int vtable_base = in_bytes(Klass::vtable_start_offset());
5350 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5351 int scan_step = itableOffsetEntry::size() * wordSize;
5352 int vte_size = vtableEntry::size_in_bytes();
5353 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5354 assert(vte_size == wordSize, "else adjust times_vte_scale");
5355
5356 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5357
5358 // %%% Could store the aligned, prescaled offset in the klassoop.
5359 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5360
5361 if (return_method) {
5362 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5363 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5364 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5365 }
5366
5367 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5368 // if (scan->interface() == intf) {
5369 // result = (klass + scan->offset() + itable_index);
5370 // }
5371 // }
5372 Label search, found_method;
5373
5374 for (int peel = 1; peel >= 0; peel--) {
5375 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5376 cmpptr(intf_klass, method_result);
5377
5378 if (peel) {
5379 jccb(Assembler::equal, found_method);
5380 } else {
5381 jccb(Assembler::notEqual, search);
5382 // (invert the test to fall through to found_method...)
5383 }
5384
5385 if (!peel) break;
5386
5387 bind(search);
5388
5389 // Check that the previous entry is non-null. A null entry means that
5390 // the receiver class doesn't implement the interface, and wasn't the
5391 // same as when the caller was compiled.
5392 testptr(method_result, method_result);
5393 jcc(Assembler::zero, L_no_such_interface);
5394 addptr(scan_temp, scan_step);
5395 }
5396
5397 bind(found_method);
5398
5399 if (return_method) {
5400 // Got a hit.
5401 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5402 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5403 }
5404 }
5405
5406
5407 // virtual method calling
5408 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5409 RegisterOrConstant vtable_index,
5410 Register method_result) {
5411 const int base = in_bytes(Klass::vtable_start_offset());
5412 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5413 Address vtable_entry_addr(recv_klass,
5414 vtable_index, Address::times_ptr,
5415 base + vtableEntry::method_offset_in_bytes());
5416 movptr(method_result, vtable_entry_addr);
5417 }
5418
5419
5420 void MacroAssembler::check_klass_subtype(Register sub_klass,
5421 Register super_klass,
5422 Register temp_reg,
5423 Label& L_success) {
5424 Label L_failure;
5425 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5426 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5427 bind(L_failure);
5428 }
5429
5430
5431 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5432 Register super_klass,
5433 Register temp_reg,
5434 Label* L_success,
5435 Label* L_failure,
5436 Label* L_slow_path,
5437 RegisterOrConstant super_check_offset) {
5438 assert_different_registers(sub_klass, super_klass, temp_reg);
5439 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5440 if (super_check_offset.is_register()) {
5441 assert_different_registers(sub_klass, super_klass,
5442 super_check_offset.as_register());
5443 } else if (must_load_sco) {
5444 assert(temp_reg != noreg, "supply either a temp or a register offset");
5445 }
5446
5447 Label L_fallthrough;
5448 int label_nulls = 0;
5449 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5450 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5451 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5452 assert(label_nulls <= 1, "at most one NULL in the batch");
5453
5454 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5455 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5456 Address super_check_offset_addr(super_klass, sco_offset);
5457
5458 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5459 // range of a jccb. If this routine grows larger, reconsider at
5460 // least some of these.
5461 #define local_jcc(assembler_cond, label) \
5462 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5463 else jcc( assembler_cond, label) /*omit semi*/
5464
5465 // Hacked jmp, which may only be used just before L_fallthrough.
5466 #define final_jmp(label) \
5467 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5468 else jmp(label) /*omit semi*/
5469
5470 // If the pointers are equal, we are done (e.g., String[] elements).
5471 // This self-check enables sharing of secondary supertype arrays among
5472 // non-primary types such as array-of-interface. Otherwise, each such
5473 // type would need its own customized SSA.
5474 // We move this check to the front of the fast path because many
5475 // type checks are in fact trivially successful in this manner,
5476 // so we get a nicely predicted branch right at the start of the check.
5477 cmpptr(sub_klass, super_klass);
5478 local_jcc(Assembler::equal, *L_success);
5479
5480 // Check the supertype display:
5481 if (must_load_sco) {
5482 // Positive movl does right thing on LP64.
5483 movl(temp_reg, super_check_offset_addr);
5484 super_check_offset = RegisterOrConstant(temp_reg);
5485 }
5486 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5487 cmpptr(super_klass, super_check_addr); // load displayed supertype
5488
5489 // This check has worked decisively for primary supers.
5490 // Secondary supers are sought in the super_cache ('super_cache_addr').
5491 // (Secondary supers are interfaces and very deeply nested subtypes.)
5492 // This works in the same check above because of a tricky aliasing
5493 // between the super_cache and the primary super display elements.
5494 // (The 'super_check_addr' can address either, as the case requires.)
5495 // Note that the cache is updated below if it does not help us find
5496 // what we need immediately.
5497 // So if it was a primary super, we can just fail immediately.
5498 // Otherwise, it's the slow path for us (no success at this point).
5499
5500 if (super_check_offset.is_register()) {
5501 local_jcc(Assembler::equal, *L_success);
5502 cmpl(super_check_offset.as_register(), sc_offset);
5503 if (L_failure == &L_fallthrough) {
5504 local_jcc(Assembler::equal, *L_slow_path);
5505 } else {
5506 local_jcc(Assembler::notEqual, *L_failure);
5507 final_jmp(*L_slow_path);
5508 }
5509 } else if (super_check_offset.as_constant() == sc_offset) {
5510 // Need a slow path; fast failure is impossible.
5511 if (L_slow_path == &L_fallthrough) {
5512 local_jcc(Assembler::equal, *L_success);
5513 } else {
5514 local_jcc(Assembler::notEqual, *L_slow_path);
5515 final_jmp(*L_success);
5516 }
5517 } else {
5518 // No slow path; it's a fast decision.
5519 if (L_failure == &L_fallthrough) {
5520 local_jcc(Assembler::equal, *L_success);
5521 } else {
5522 local_jcc(Assembler::notEqual, *L_failure);
5523 final_jmp(*L_success);
5524 }
5525 }
5526
5527 bind(L_fallthrough);
5528
5529 #undef local_jcc
5530 #undef final_jmp
5531 }
5532
5533
5534 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5535 Register super_klass,
5536 Register temp_reg,
5537 Register temp2_reg,
5538 Label* L_success,
5539 Label* L_failure,
5540 bool set_cond_codes) {
5541 assert_different_registers(sub_klass, super_klass, temp_reg);
5542 if (temp2_reg != noreg)
5543 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5544 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5545
5546 Label L_fallthrough;
5547 int label_nulls = 0;
5548 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5549 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5550 assert(label_nulls <= 1, "at most one NULL in the batch");
5551
5552 // a couple of useful fields in sub_klass:
5553 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5554 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5555 Address secondary_supers_addr(sub_klass, ss_offset);
5556 Address super_cache_addr( sub_klass, sc_offset);
5557
5558 // Do a linear scan of the secondary super-klass chain.
5559 // This code is rarely used, so simplicity is a virtue here.
5560 // The repne_scan instruction uses fixed registers, which we must spill.
5561 // Don't worry too much about pre-existing connections with the input regs.
5562
5563 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5564 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5565
5566 // Get super_klass value into rax (even if it was in rdi or rcx).
5567 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5568 if (super_klass != rax || UseCompressedOops) {
5569 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5570 mov(rax, super_klass);
5571 }
5572 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5573 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5574
5575 #ifndef PRODUCT
5576 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5577 ExternalAddress pst_counter_addr((address) pst_counter);
5578 NOT_LP64( incrementl(pst_counter_addr) );
5579 LP64_ONLY( lea(rcx, pst_counter_addr) );
5580 LP64_ONLY( incrementl(Address(rcx, 0)) );
5581 #endif //PRODUCT
5582
5583 // We will consult the secondary-super array.
5584 movptr(rdi, secondary_supers_addr);
5585 // Load the array length. (Positive movl does right thing on LP64.)
5586 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5587 // Skip to start of data.
5588 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5589
5590 // Scan RCX words at [RDI] for an occurrence of RAX.
5591 // Set NZ/Z based on last compare.
5592 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5593 // not change flags (only scas instruction which is repeated sets flags).
5594 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5595
5596 testptr(rax,rax); // Set Z = 0
5597 repne_scan();
5598
5599 // Unspill the temp. registers:
5600 if (pushed_rdi) pop(rdi);
5601 if (pushed_rcx) pop(rcx);
5602 if (pushed_rax) pop(rax);
5603
5604 if (set_cond_codes) {
5605 // Special hack for the AD files: rdi is guaranteed non-zero.
5606 assert(!pushed_rdi, "rdi must be left non-NULL");
5607 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5608 }
5609
5610 if (L_failure == &L_fallthrough)
5611 jccb(Assembler::notEqual, *L_failure);
5612 else jcc(Assembler::notEqual, *L_failure);
5613
5614 // Success. Cache the super we found and proceed in triumph.
5615 movptr(super_cache_addr, super_klass);
5616
5617 if (L_success != &L_fallthrough) {
5618 jmp(*L_success);
5619 }
5620
5621 #undef IS_A_TEMP
5622
5623 bind(L_fallthrough);
5624 }
5625
5626
5627 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5628 if (VM_Version::supports_cmov()) {
5629 cmovl(cc, dst, src);
5630 } else {
5631 Label L;
5632 jccb(negate_condition(cc), L);
5633 movl(dst, src);
5634 bind(L);
5635 }
5636 }
5637
5638 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5639 if (VM_Version::supports_cmov()) {
5640 cmovl(cc, dst, src);
5641 } else {
5642 Label L;
5643 jccb(negate_condition(cc), L);
5644 movl(dst, src);
5645 bind(L);
5646 }
5647 }
5648
5649 void MacroAssembler::verify_oop(Register reg, const char* s) {
5650 if (!VerifyOops || VerifyAdapterSharing) {
5651 // Below address of the code string confuses VerifyAdapterSharing
5652 // because it may differ between otherwise equivalent adapters.
5653 return;
5654 }
5655
5656 // Pass register number to verify_oop_subroutine
5657 const char* b = NULL;
5658 {
5659 ResourceMark rm;
5660 stringStream ss;
5661 ss.print("verify_oop: %s: %s", reg->name(), s);
5662 b = code_string(ss.as_string());
5663 }
5664 BLOCK_COMMENT("verify_oop {");
5665 #ifdef _LP64
5666 push(rscratch1); // save r10, trashed by movptr()
5667 #endif
5668 push(rax); // save rax,
5669 push(reg); // pass register argument
5670 ExternalAddress buffer((address) b);
5671 // avoid using pushptr, as it modifies scratch registers
5672 // and our contract is not to modify anything
5673 movptr(rax, buffer.addr());
5674 push(rax);
5675 // call indirectly to solve generation ordering problem
5676 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5677 call(rax);
5678 // Caller pops the arguments (oop, message) and restores rax, r10
5679 BLOCK_COMMENT("} verify_oop");
5680 }
5681
5682
5683 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5684 Register tmp,
5685 int offset) {
5686 intptr_t value = *delayed_value_addr;
5687 if (value != 0)
5688 return RegisterOrConstant(value + offset);
5689
5690 // load indirectly to solve generation ordering problem
5691 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5692
5693 #ifdef ASSERT
5694 { Label L;
5695 testptr(tmp, tmp);
5696 if (WizardMode) {
5697 const char* buf = NULL;
5698 {
5699 ResourceMark rm;
5700 stringStream ss;
5701 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5702 buf = code_string(ss.as_string());
5703 }
5704 jcc(Assembler::notZero, L);
5705 STOP(buf);
5706 } else {
5707 jccb(Assembler::notZero, L);
5708 hlt();
5709 }
5710 bind(L);
5711 }
5712 #endif
5713
5714 if (offset != 0)
5715 addptr(tmp, offset);
5716
5717 return RegisterOrConstant(tmp);
5718 }
5719
5720
5721 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5722 int extra_slot_offset) {
5723 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5724 int stackElementSize = Interpreter::stackElementSize;
5725 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5726 #ifdef ASSERT
5727 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5728 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5729 #endif
5730 Register scale_reg = noreg;
5731 Address::ScaleFactor scale_factor = Address::no_scale;
5732 if (arg_slot.is_constant()) {
5733 offset += arg_slot.as_constant() * stackElementSize;
5734 } else {
5735 scale_reg = arg_slot.as_register();
5736 scale_factor = Address::times(stackElementSize);
5737 }
5738 offset += wordSize; // return PC is on stack
5739 return Address(rsp, scale_reg, scale_factor, offset);
5740 }
5741
5742
5743 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5744 if (!VerifyOops || VerifyAdapterSharing) {
5745 // Below address of the code string confuses VerifyAdapterSharing
5746 // because it may differ between otherwise equivalent adapters.
5747 return;
5748 }
5749
5750 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5751 // Pass register number to verify_oop_subroutine
5752 const char* b = NULL;
5753 {
5754 ResourceMark rm;
5755 stringStream ss;
5756 ss.print("verify_oop_addr: %s", s);
5757 b = code_string(ss.as_string());
5758 }
5759 #ifdef _LP64
5760 push(rscratch1); // save r10, trashed by movptr()
5761 #endif
5762 push(rax); // save rax,
5763 // addr may contain rsp so we will have to adjust it based on the push
5764 // we just did (and on 64 bit we do two pushes)
5765 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5766 // stores rax into addr which is backwards of what was intended.
5767 if (addr.uses(rsp)) {
5768 lea(rax, addr);
5769 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5770 } else {
5771 pushptr(addr);
5772 }
5773
5774 ExternalAddress buffer((address) b);
5775 // pass msg argument
5776 // avoid using pushptr, as it modifies scratch registers
5777 // and our contract is not to modify anything
5778 movptr(rax, buffer.addr());
5779 push(rax);
5780
5781 // call indirectly to solve generation ordering problem
5782 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5783 call(rax);
5784 // Caller pops the arguments (addr, message) and restores rax, r10.
5785 }
5786
5787 void MacroAssembler::verify_tlab() {
5788 #ifdef ASSERT
5789 if (UseTLAB && VerifyOops) {
5790 Label next, ok;
5791 Register t1 = rsi;
5792 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5793
5794 push(t1);
5795 NOT_LP64(push(thread_reg));
5796 NOT_LP64(get_thread(thread_reg));
5797
5798 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5799 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5800 jcc(Assembler::aboveEqual, next);
5801 STOP("assert(top >= start)");
5802 should_not_reach_here();
5803
5804 bind(next);
5805 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5806 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5807 jcc(Assembler::aboveEqual, ok);
5808 STOP("assert(top <= end)");
5809 should_not_reach_here();
5810
5811 bind(ok);
5812 NOT_LP64(pop(thread_reg));
5813 pop(t1);
5814 }
5815 #endif
5816 }
5817
5818 class ControlWord {
5819 public:
5820 int32_t _value;
5821
5822 int rounding_control() const { return (_value >> 10) & 3 ; }
5823 int precision_control() const { return (_value >> 8) & 3 ; }
5824 bool precision() const { return ((_value >> 5) & 1) != 0; }
5825 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5826 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5827 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5828 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5829 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5830
5831 void print() const {
5832 // rounding control
5833 const char* rc;
5834 switch (rounding_control()) {
5835 case 0: rc = "round near"; break;
5836 case 1: rc = "round down"; break;
5837 case 2: rc = "round up "; break;
5838 case 3: rc = "chop "; break;
5839 };
5840 // precision control
5841 const char* pc;
5842 switch (precision_control()) {
5843 case 0: pc = "24 bits "; break;
5844 case 1: pc = "reserved"; break;
5845 case 2: pc = "53 bits "; break;
5846 case 3: pc = "64 bits "; break;
5847 };
5848 // flags
5849 char f[9];
5850 f[0] = ' ';
5851 f[1] = ' ';
5852 f[2] = (precision ()) ? 'P' : 'p';
5853 f[3] = (underflow ()) ? 'U' : 'u';
5854 f[4] = (overflow ()) ? 'O' : 'o';
5855 f[5] = (zero_divide ()) ? 'Z' : 'z';
5856 f[6] = (denormalized()) ? 'D' : 'd';
5857 f[7] = (invalid ()) ? 'I' : 'i';
5858 f[8] = '\x0';
5859 // output
5860 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5861 }
5862
5863 };
5864
5865 class StatusWord {
5866 public:
5867 int32_t _value;
5868
5869 bool busy() const { return ((_value >> 15) & 1) != 0; }
5870 bool C3() const { return ((_value >> 14) & 1) != 0; }
5871 bool C2() const { return ((_value >> 10) & 1) != 0; }
5872 bool C1() const { return ((_value >> 9) & 1) != 0; }
5873 bool C0() const { return ((_value >> 8) & 1) != 0; }
5874 int top() const { return (_value >> 11) & 7 ; }
5875 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5876 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5877 bool precision() const { return ((_value >> 5) & 1) != 0; }
5878 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5879 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5880 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5881 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5882 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5883
5884 void print() const {
5885 // condition codes
5886 char c[5];
5887 c[0] = (C3()) ? '3' : '-';
5888 c[1] = (C2()) ? '2' : '-';
5889 c[2] = (C1()) ? '1' : '-';
5890 c[3] = (C0()) ? '0' : '-';
5891 c[4] = '\x0';
5892 // flags
5893 char f[9];
5894 f[0] = (error_status()) ? 'E' : '-';
5895 f[1] = (stack_fault ()) ? 'S' : '-';
5896 f[2] = (precision ()) ? 'P' : '-';
5897 f[3] = (underflow ()) ? 'U' : '-';
5898 f[4] = (overflow ()) ? 'O' : '-';
5899 f[5] = (zero_divide ()) ? 'Z' : '-';
5900 f[6] = (denormalized()) ? 'D' : '-';
5901 f[7] = (invalid ()) ? 'I' : '-';
5902 f[8] = '\x0';
5903 // output
5904 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5905 }
5906
5907 };
5908
5909 class TagWord {
5910 public:
5911 int32_t _value;
5912
5913 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5914
5915 void print() const {
5916 printf("%04x", _value & 0xFFFF);
5917 }
5918
5919 };
5920
5921 class FPU_Register {
5922 public:
5923 int32_t _m0;
5924 int32_t _m1;
5925 int16_t _ex;
5926
5927 bool is_indefinite() const {
5928 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5929 }
5930
5931 void print() const {
5932 char sign = (_ex < 0) ? '-' : '+';
5933 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5934 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5935 };
5936
5937 };
5938
5939 class FPU_State {
5940 public:
5941 enum {
5942 register_size = 10,
5943 number_of_registers = 8,
5944 register_mask = 7
5945 };
5946
5947 ControlWord _control_word;
5948 StatusWord _status_word;
5949 TagWord _tag_word;
5950 int32_t _error_offset;
5951 int32_t _error_selector;
5952 int32_t _data_offset;
5953 int32_t _data_selector;
5954 int8_t _register[register_size * number_of_registers];
5955
5956 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5957 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5958
5959 const char* tag_as_string(int tag) const {
5960 switch (tag) {
5961 case 0: return "valid";
5962 case 1: return "zero";
5963 case 2: return "special";
5964 case 3: return "empty";
5965 }
5966 ShouldNotReachHere();
5967 return NULL;
5968 }
5969
5970 void print() const {
5971 // print computation registers
5972 { int t = _status_word.top();
5973 for (int i = 0; i < number_of_registers; i++) {
5974 int j = (i - t) & register_mask;
5975 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5976 st(j)->print();
5977 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5978 }
5979 }
5980 printf("\n");
5981 // print control registers
5982 printf("ctrl = "); _control_word.print(); printf("\n");
5983 printf("stat = "); _status_word .print(); printf("\n");
5984 printf("tags = "); _tag_word .print(); printf("\n");
5985 }
5986
5987 };
5988
5989 class Flag_Register {
5990 public:
5991 int32_t _value;
5992
5993 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5994 bool direction() const { return ((_value >> 10) & 1) != 0; }
5995 bool sign() const { return ((_value >> 7) & 1) != 0; }
5996 bool zero() const { return ((_value >> 6) & 1) != 0; }
5997 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5998 bool parity() const { return ((_value >> 2) & 1) != 0; }
5999 bool carry() const { return ((_value >> 0) & 1) != 0; }
6000
6001 void print() const {
6002 // flags
6003 char f[8];
6004 f[0] = (overflow ()) ? 'O' : '-';
6005 f[1] = (direction ()) ? 'D' : '-';
6006 f[2] = (sign ()) ? 'S' : '-';
6007 f[3] = (zero ()) ? 'Z' : '-';
6008 f[4] = (auxiliary_carry()) ? 'A' : '-';
6009 f[5] = (parity ()) ? 'P' : '-';
6010 f[6] = (carry ()) ? 'C' : '-';
6011 f[7] = '\x0';
6012 // output
6013 printf("%08x flags = %s", _value, f);
6014 }
6015
6016 };
6017
6018 class IU_Register {
6019 public:
6020 int32_t _value;
6021
6022 void print() const {
6023 printf("%08x %11d", _value, _value);
6024 }
6025
6026 };
6027
6028 class IU_State {
6029 public:
6030 Flag_Register _eflags;
6031 IU_Register _rdi;
6032 IU_Register _rsi;
6033 IU_Register _rbp;
6034 IU_Register _rsp;
6035 IU_Register _rbx;
6036 IU_Register _rdx;
6037 IU_Register _rcx;
6038 IU_Register _rax;
6039
6040 void print() const {
6041 // computation registers
6042 printf("rax, = "); _rax.print(); printf("\n");
6043 printf("rbx, = "); _rbx.print(); printf("\n");
6044 printf("rcx = "); _rcx.print(); printf("\n");
6045 printf("rdx = "); _rdx.print(); printf("\n");
6046 printf("rdi = "); _rdi.print(); printf("\n");
6047 printf("rsi = "); _rsi.print(); printf("\n");
6048 printf("rbp, = "); _rbp.print(); printf("\n");
6049 printf("rsp = "); _rsp.print(); printf("\n");
6050 printf("\n");
6051 // control registers
6052 printf("flgs = "); _eflags.print(); printf("\n");
6053 }
6054 };
6055
6056
6057 class CPU_State {
6058 public:
6059 FPU_State _fpu_state;
6060 IU_State _iu_state;
6061
6062 void print() const {
6063 printf("--------------------------------------------------\n");
6064 _iu_state .print();
6065 printf("\n");
6066 _fpu_state.print();
6067 printf("--------------------------------------------------\n");
6068 }
6069
6070 };
6071
6072
6073 static void _print_CPU_state(CPU_State* state) {
6074 state->print();
6075 };
6076
6077
6078 void MacroAssembler::print_CPU_state() {
6079 push_CPU_state();
6080 push(rsp); // pass CPU state
6081 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6082 addptr(rsp, wordSize); // discard argument
6083 pop_CPU_state();
6084 }
6085
6086
6087 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6088 static int counter = 0;
6089 FPU_State* fs = &state->_fpu_state;
6090 counter++;
6091 // For leaf calls, only verify that the top few elements remain empty.
6092 // We only need 1 empty at the top for C2 code.
6093 if( stack_depth < 0 ) {
6094 if( fs->tag_for_st(7) != 3 ) {
6095 printf("FPR7 not empty\n");
6096 state->print();
6097 assert(false, "error");
6098 return false;
6099 }
6100 return true; // All other stack states do not matter
6101 }
6102
6103 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6104 "bad FPU control word");
6105
6106 // compute stack depth
6107 int i = 0;
6108 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6109 int d = i;
6110 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6111 // verify findings
6112 if (i != FPU_State::number_of_registers) {
6113 // stack not contiguous
6114 printf("%s: stack not contiguous at ST%d\n", s, i);
6115 state->print();
6116 assert(false, "error");
6117 return false;
6118 }
6119 // check if computed stack depth corresponds to expected stack depth
6120 if (stack_depth < 0) {
6121 // expected stack depth is -stack_depth or less
6122 if (d > -stack_depth) {
6123 // too many elements on the stack
6124 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6125 state->print();
6126 assert(false, "error");
6127 return false;
6128 }
6129 } else {
6130 // expected stack depth is stack_depth
6131 if (d != stack_depth) {
6132 // wrong stack depth
6133 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6134 state->print();
6135 assert(false, "error");
6136 return false;
6137 }
6138 }
6139 // everything is cool
6140 return true;
6141 }
6142
6143
6144 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6145 if (!VerifyFPU) return;
6146 push_CPU_state();
6147 push(rsp); // pass CPU state
6148 ExternalAddress msg((address) s);
6149 // pass message string s
6150 pushptr(msg.addr());
6151 push(stack_depth); // pass stack depth
6152 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6153 addptr(rsp, 3 * wordSize); // discard arguments
6154 // check for error
6155 { Label L;
6156 testl(rax, rax);
6157 jcc(Assembler::notZero, L);
6158 int3(); // break if error condition
6159 bind(L);
6160 }
6161 pop_CPU_state();
6162 }
6163
6164 void MacroAssembler::restore_cpu_control_state_after_jni() {
6165 // Either restore the MXCSR register after returning from the JNI Call
6166 // or verify that it wasn't changed (with -Xcheck:jni flag).
6167 if (VM_Version::supports_sse()) {
6168 if (RestoreMXCSROnJNICalls) {
6169 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6170 } else if (CheckJNICalls) {
6171 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6172 }
6173 }
6174 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6175 vzeroupper();
6176 // Reset k1 to 0xffff.
6177 if (VM_Version::supports_evex()) {
6178 push(rcx);
6179 movl(rcx, 0xffff);
6180 kmovwl(k1, rcx);
6181 pop(rcx);
6182 }
6183
6184 #ifndef _LP64
6185 // Either restore the x87 floating pointer control word after returning
6186 // from the JNI call or verify that it wasn't changed.
6187 if (CheckJNICalls) {
6188 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6189 }
6190 #endif // _LP64
6191 }
6192
6193 // ((OopHandle)result).resolve();
6194 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
6195 assert_different_registers(result, tmp);
6196
6197 // Only 64 bit platforms support GCs that require a tmp register
6198 // Only IN_HEAP loads require a thread_tmp register
6199 // OopHandle::resolve is an indirection like jobject.
6200 access_load_at(T_OBJECT, IN_NATIVE,
6201 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
6202 }
6203
6204 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
6205 // get mirror
6206 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6207 movptr(mirror, Address(method, Method::const_offset()));
6208 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6209 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6210 movptr(mirror, Address(mirror, mirror_offset));
6211 resolve_oop_handle(mirror, tmp);
6212 }
6213
6214 void MacroAssembler::load_klass(Register dst, Register src) {
6215 #ifdef _LP64
6216 if (UseCompressedClassPointers) {
6217 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6218 decode_klass_not_null(dst);
6219 } else
6220 #endif
6221 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6222 }
6223
6224 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6225 load_klass(dst, src);
6226 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6227 }
6228
6229 void MacroAssembler::store_klass(Register dst, Register src) {
6230 #ifdef _LP64
6231 if (UseCompressedClassPointers) {
6232 encode_klass_not_null(src);
6233 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6234 } else
6235 #endif
6236 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6237 }
6238
6239 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6240 Register tmp1, Register thread_tmp) {
6241 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6242 decorators = AccessInternal::decorator_fixup(decorators);
6243 bool as_raw = (decorators & AS_RAW) != 0;
6244 if (as_raw) {
6245 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6246 } else {
6247 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6248 }
6249 }
6250
6251 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
6252 Register tmp1, Register tmp2) {
6253 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6254 decorators = AccessInternal::decorator_fixup(decorators);
6255 bool as_raw = (decorators & AS_RAW) != 0;
6256 if (as_raw) {
6257 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
6258 } else {
6259 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
6260 }
6261 }
6262
6263 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
6264 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
6265 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
6266 decorators |= ACCESS_READ | ACCESS_WRITE;
6267 }
6268 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6269 return bs->resolve(this, decorators, obj);
6270 }
6271
6272 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6273 Register thread_tmp, DecoratorSet decorators) {
6274 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6275 }
6276
6277 // Doesn't do verfication, generates fixed size code
6278 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6279 Register thread_tmp, DecoratorSet decorators) {
6280 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6281 }
6282
6283 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
6284 Register tmp2, DecoratorSet decorators) {
6285 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
6286 }
6287
6288 // Used for storing NULLs.
6289 void MacroAssembler::store_heap_oop_null(Address dst) {
6290 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
6291 }
6292
6293 #ifdef _LP64
6294 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6295 if (UseCompressedClassPointers) {
6296 // Store to klass gap in destination
6297 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6298 }
6299 }
6300
6301 #ifdef ASSERT
6302 void MacroAssembler::verify_heapbase(const char* msg) {
6303 assert (UseCompressedOops, "should be compressed");
6304 assert (Universe::heap() != NULL, "java heap should be initialized");
6305 if (CheckCompressedOops) {
6306 Label ok;
6307 push(rscratch1); // cmpptr trashes rscratch1
6308 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6309 jcc(Assembler::equal, ok);
6310 STOP(msg);
6311 bind(ok);
6312 pop(rscratch1);
6313 }
6314 }
6315 #endif
6316
6317 // Algorithm must match oop.inline.hpp encode_heap_oop.
6318 void MacroAssembler::encode_heap_oop(Register r) {
6319 #ifdef ASSERT
6320 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6321 #endif
6322 verify_oop(r, "broken oop in encode_heap_oop");
6323 if (Universe::narrow_oop_base() == NULL) {
6324 if (Universe::narrow_oop_shift() != 0) {
6325 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6326 shrq(r, LogMinObjAlignmentInBytes);
6327 }
6328 return;
6329 }
6330 testq(r, r);
6331 cmovq(Assembler::equal, r, r12_heapbase);
6332 subq(r, r12_heapbase);
6333 shrq(r, LogMinObjAlignmentInBytes);
6334 }
6335
6336 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6337 #ifdef ASSERT
6338 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6339 if (CheckCompressedOops) {
6340 Label ok;
6341 testq(r, r);
6342 jcc(Assembler::notEqual, ok);
6343 STOP("null oop passed to encode_heap_oop_not_null");
6344 bind(ok);
6345 }
6346 #endif
6347 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6348 if (Universe::narrow_oop_base() != NULL) {
6349 subq(r, r12_heapbase);
6350 }
6351 if (Universe::narrow_oop_shift() != 0) {
6352 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6353 shrq(r, LogMinObjAlignmentInBytes);
6354 }
6355 }
6356
6357 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6358 #ifdef ASSERT
6359 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6360 if (CheckCompressedOops) {
6361 Label ok;
6362 testq(src, src);
6363 jcc(Assembler::notEqual, ok);
6364 STOP("null oop passed to encode_heap_oop_not_null2");
6365 bind(ok);
6366 }
6367 #endif
6368 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6369 if (dst != src) {
6370 movq(dst, src);
6371 }
6372 if (Universe::narrow_oop_base() != NULL) {
6373 subq(dst, r12_heapbase);
6374 }
6375 if (Universe::narrow_oop_shift() != 0) {
6376 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6377 shrq(dst, LogMinObjAlignmentInBytes);
6378 }
6379 }
6380
6381 void MacroAssembler::decode_heap_oop(Register r) {
6382 #ifdef ASSERT
6383 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6384 #endif
6385 if (Universe::narrow_oop_base() == NULL) {
6386 if (Universe::narrow_oop_shift() != 0) {
6387 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6388 shlq(r, LogMinObjAlignmentInBytes);
6389 }
6390 } else {
6391 Label done;
6392 shlq(r, LogMinObjAlignmentInBytes);
6393 jccb(Assembler::equal, done);
6394 addq(r, r12_heapbase);
6395 bind(done);
6396 }
6397 verify_oop(r, "broken oop in decode_heap_oop");
6398 }
6399
6400 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6401 // Note: it will change flags
6402 assert (UseCompressedOops, "should only be used for compressed headers");
6403 assert (Universe::heap() != NULL, "java heap should be initialized");
6404 // Cannot assert, unverified entry point counts instructions (see .ad file)
6405 // vtableStubs also counts instructions in pd_code_size_limit.
6406 // Also do not verify_oop as this is called by verify_oop.
6407 if (Universe::narrow_oop_shift() != 0) {
6408 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6409 shlq(r, LogMinObjAlignmentInBytes);
6410 if (Universe::narrow_oop_base() != NULL) {
6411 addq(r, r12_heapbase);
6412 }
6413 } else {
6414 assert (Universe::narrow_oop_base() == NULL, "sanity");
6415 }
6416 }
6417
6418 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6419 // Note: it will change flags
6420 assert (UseCompressedOops, "should only be used for compressed headers");
6421 assert (Universe::heap() != NULL, "java heap should be initialized");
6422 // Cannot assert, unverified entry point counts instructions (see .ad file)
6423 // vtableStubs also counts instructions in pd_code_size_limit.
6424 // Also do not verify_oop as this is called by verify_oop.
6425 if (Universe::narrow_oop_shift() != 0) {
6426 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6427 if (LogMinObjAlignmentInBytes == Address::times_8) {
6428 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6429 } else {
6430 if (dst != src) {
6431 movq(dst, src);
6432 }
6433 shlq(dst, LogMinObjAlignmentInBytes);
6434 if (Universe::narrow_oop_base() != NULL) {
6435 addq(dst, r12_heapbase);
6436 }
6437 }
6438 } else {
6439 assert (Universe::narrow_oop_base() == NULL, "sanity");
6440 if (dst != src) {
6441 movq(dst, src);
6442 }
6443 }
6444 }
6445
6446 void MacroAssembler::encode_klass_not_null(Register r) {
6447 if (Universe::narrow_klass_base() != NULL) {
6448 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6449 assert(r != r12_heapbase, "Encoding a klass in r12");
6450 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6451 subq(r, r12_heapbase);
6452 }
6453 if (Universe::narrow_klass_shift() != 0) {
6454 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6455 shrq(r, LogKlassAlignmentInBytes);
6456 }
6457 if (Universe::narrow_klass_base() != NULL) {
6458 reinit_heapbase();
6459 }
6460 }
6461
6462 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6463 if (dst == src) {
6464 encode_klass_not_null(src);
6465 } else {
6466 if (Universe::narrow_klass_base() != NULL) {
6467 mov64(dst, (int64_t)Universe::narrow_klass_base());
6468 negq(dst);
6469 addq(dst, src);
6470 } else {
6471 movptr(dst, src);
6472 }
6473 if (Universe::narrow_klass_shift() != 0) {
6474 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6475 shrq(dst, LogKlassAlignmentInBytes);
6476 }
6477 }
6478 }
6479
6480 // Function instr_size_for_decode_klass_not_null() counts the instructions
6481 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6482 // when (Universe::heap() != NULL). Hence, if the instructions they
6483 // generate change, then this method needs to be updated.
6484 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6485 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6486 if (Universe::narrow_klass_base() != NULL) {
6487 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6488 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6489 } else {
6490 // longest load decode klass function, mov64, leaq
6491 return 16;
6492 }
6493 }
6494
6495 // !!! If the instructions that get generated here change then function
6496 // instr_size_for_decode_klass_not_null() needs to get updated.
6497 void MacroAssembler::decode_klass_not_null(Register r) {
6498 // Note: it will change flags
6499 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6500 assert(r != r12_heapbase, "Decoding a klass in r12");
6501 // Cannot assert, unverified entry point counts instructions (see .ad file)
6502 // vtableStubs also counts instructions in pd_code_size_limit.
6503 // Also do not verify_oop as this is called by verify_oop.
6504 if (Universe::narrow_klass_shift() != 0) {
6505 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6506 shlq(r, LogKlassAlignmentInBytes);
6507 }
6508 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6509 if (Universe::narrow_klass_base() != NULL) {
6510 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6511 addq(r, r12_heapbase);
6512 reinit_heapbase();
6513 }
6514 }
6515
6516 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6517 // Note: it will change flags
6518 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6519 if (dst == src) {
6520 decode_klass_not_null(dst);
6521 } else {
6522 // Cannot assert, unverified entry point counts instructions (see .ad file)
6523 // vtableStubs also counts instructions in pd_code_size_limit.
6524 // Also do not verify_oop as this is called by verify_oop.
6525 mov64(dst, (int64_t)Universe::narrow_klass_base());
6526 if (Universe::narrow_klass_shift() != 0) {
6527 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6528 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6529 leaq(dst, Address(dst, src, Address::times_8, 0));
6530 } else {
6531 addq(dst, src);
6532 }
6533 }
6534 }
6535
6536 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6537 assert (UseCompressedOops, "should only be used for compressed headers");
6538 assert (Universe::heap() != NULL, "java heap should be initialized");
6539 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6540 int oop_index = oop_recorder()->find_index(obj);
6541 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6542 mov_narrow_oop(dst, oop_index, rspec);
6543 }
6544
6545 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6546 assert (UseCompressedOops, "should only be used for compressed headers");
6547 assert (Universe::heap() != NULL, "java heap should be initialized");
6548 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6549 int oop_index = oop_recorder()->find_index(obj);
6550 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6551 mov_narrow_oop(dst, oop_index, rspec);
6552 }
6553
6554 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6555 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6556 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6557 int klass_index = oop_recorder()->find_index(k);
6558 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6559 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6560 }
6561
6562 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6563 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6564 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6565 int klass_index = oop_recorder()->find_index(k);
6566 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6567 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6568 }
6569
6570 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6571 assert (UseCompressedOops, "should only be used for compressed headers");
6572 assert (Universe::heap() != NULL, "java heap should be initialized");
6573 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6574 int oop_index = oop_recorder()->find_index(obj);
6575 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6576 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6577 }
6578
6579 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6580 assert (UseCompressedOops, "should only be used for compressed headers");
6581 assert (Universe::heap() != NULL, "java heap should be initialized");
6582 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6583 int oop_index = oop_recorder()->find_index(obj);
6584 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6585 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6586 }
6587
6588 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6589 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6590 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6591 int klass_index = oop_recorder()->find_index(k);
6592 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6593 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6594 }
6595
6596 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6597 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6598 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6599 int klass_index = oop_recorder()->find_index(k);
6600 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6601 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6602 }
6603
6604 void MacroAssembler::reinit_heapbase() {
6605 if (UseCompressedOops || UseCompressedClassPointers) {
6606 if (Universe::heap() != NULL) {
6607 if (Universe::narrow_oop_base() == NULL) {
6608 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6609 } else {
6610 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6611 }
6612 } else {
6613 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6614 }
6615 }
6616 }
6617
6618 #endif // _LP64
6619
6620 // C2 compiled method's prolog code.
6621 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6622
6623 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6624 // NativeJump::patch_verified_entry will be able to patch out the entry
6625 // code safely. The push to verify stack depth is ok at 5 bytes,
6626 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6627 // stack bang then we must use the 6 byte frame allocation even if
6628 // we have no frame. :-(
6629 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6630
6631 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6632 // Remove word for return addr
6633 framesize -= wordSize;
6634 stack_bang_size -= wordSize;
6635
6636 // Calls to C2R adapters often do not accept exceptional returns.
6637 // We require that their callers must bang for them. But be careful, because
6638 // some VM calls (such as call site linkage) can use several kilobytes of
6639 // stack. But the stack safety zone should account for that.
6640 // See bugs 4446381, 4468289, 4497237.
6641 if (stack_bang_size > 0) {
6642 generate_stack_overflow_check(stack_bang_size);
6643
6644 // We always push rbp, so that on return to interpreter rbp, will be
6645 // restored correctly and we can correct the stack.
6646 push(rbp);
6647 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6648 if (PreserveFramePointer) {
6649 mov(rbp, rsp);
6650 }
6651 // Remove word for ebp
6652 framesize -= wordSize;
6653
6654 // Create frame
6655 if (framesize) {
6656 subptr(rsp, framesize);
6657 }
6658 } else {
6659 // Create frame (force generation of a 4 byte immediate value)
6660 subptr_imm32(rsp, framesize);
6661
6662 // Save RBP register now.
6663 framesize -= wordSize;
6664 movptr(Address(rsp, framesize), rbp);
6665 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6666 if (PreserveFramePointer) {
6667 movptr(rbp, rsp);
6668 if (framesize > 0) {
6669 addptr(rbp, framesize);
6670 }
6671 }
6672 }
6673
6674 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6675 framesize -= wordSize;
6676 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6677 }
6678
6679 #ifndef _LP64
6680 // If method sets FPU control word do it now
6681 if (fp_mode_24b) {
6682 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6683 }
6684 if (UseSSE >= 2 && VerifyFPU) {
6685 verify_FPU(0, "FPU stack must be clean on entry");
6686 }
6687 #endif
6688
6689 #ifdef ASSERT
6690 if (VerifyStackAtCalls) {
6691 Label L;
6692 push(rax);
6693 mov(rax, rsp);
6694 andptr(rax, StackAlignmentInBytes-1);
6695 cmpptr(rax, StackAlignmentInBytes-wordSize);
6696 pop(rax);
6697 jcc(Assembler::equal, L);
6698 STOP("Stack is not properly aligned!");
6699 bind(L);
6700 }
6701 #endif
6702
6703 }
6704
6705 // Add null checks for all value type arguments
6706 void MacroAssembler::null_check_value_args(Method* method) {
6707 // Get registers/stack slots for arguments
6708 assert(method->has_value_args(), "must have value type args");
6709 Symbol* sig_ext = method->adapter()->get_sig_extended();
6710 assert(sig_ext != NULL, "must have extended signature");
6711 BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, 256);
6712 VMRegPair* regs = NEW_RESOURCE_ARRAY(VMRegPair, 256);
6713 int num = 0;
6714 for (SignatureStream ss(sig_ext); !ss.at_return_type(); ss.next()) {
6715 BasicType bt = ss.type();
6716 sig_bt[num++] = bt;
6717 if (type2size[bt] == 2) {
6718 sig_bt[num++] = T_VOID;
6719 }
6720 }
6721 SharedRuntime::java_calling_convention(sig_bt, regs, num, false);
6722
6723 // Jump to c2i adapter if a value type argument is null
6724 bool has_receiver = !method->is_static();
6725 RuntimeAddress interpreter_entry = RuntimeAddress(method->get_c2i_entry());
6726 num = 0;
6727 for (SignatureStream ss(sig_ext); !ss.at_return_type(); num += type2size[ss.type()], ss.next()) {
6728 if ((has_receiver && num == 0) || ss.type() != T_VALUETYPEPTR) {
6729 continue; // Skip receiver and non value type args
6730 }
6731 VMReg r = regs[num].first();
6732 if (r->is_reg()) {
6733 testptr(r->as_Register(), r->as_Register());
6734 } else {
6735 if (!r->is_stack()) {
6736 r->print();
6737 }
6738 int st_off = r->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6739 cmpptr(Address(rsp, st_off), NULL_WORD);
6740 }
6741 jump_cc(Assembler::zero, interpreter_entry);
6742 }
6743 }
6744
6745 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
6746 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp) {
6747 // cnt - number of qwords (8-byte words).
6748 // base - start address, qword aligned.
6749 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6750 movdq(xtmp, val);
6751 if (UseAVX >= 2) {
6752 punpcklqdq(xtmp, xtmp);
6753 vinserti128_high(xtmp, xtmp);
6754 } else {
6755 punpcklqdq(xtmp, xtmp);
6756 }
6757 jmp(L_zero_64_bytes);
6758
6759 BIND(L_loop);
6760 if (UseAVX >= 2) {
6761 vmovdqu(Address(base, 0), xtmp);
6762 vmovdqu(Address(base, 32), xtmp);
6763 } else {
6764 movdqu(Address(base, 0), xtmp);
6765 movdqu(Address(base, 16), xtmp);
6766 movdqu(Address(base, 32), xtmp);
6767 movdqu(Address(base, 48), xtmp);
6768 }
6769 addptr(base, 64);
6770
6771 BIND(L_zero_64_bytes);
6772 subptr(cnt, 8);
6773 jccb(Assembler::greaterEqual, L_loop);
6774 addptr(cnt, 4);
6775 jccb(Assembler::less, L_tail);
6776 // Copy trailing 32 bytes
6777 if (UseAVX >= 2) {
6778 vmovdqu(Address(base, 0), xtmp);
6779 } else {
6780 movdqu(Address(base, 0), xtmp);
6781 movdqu(Address(base, 16), xtmp);
6782 }
6783 addptr(base, 32);
6784 subptr(cnt, 4);
6785
6786 BIND(L_tail);
6787 addptr(cnt, 4);
6788 jccb(Assembler::lessEqual, L_end);
6789 decrement(cnt);
6790
6791 BIND(L_sloop);
6792 movq(Address(base, 0), xtmp);
6793 addptr(base, 8);
6794 decrement(cnt);
6795 jccb(Assembler::greaterEqual, L_sloop);
6796 BIND(L_end);
6797 }
6798
6799 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only) {
6800 // cnt - number of qwords (8-byte words).
6801 // base - start address, qword aligned.
6802 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6803 assert(base==rdi, "base register must be edi for rep stos");
6804 assert(val==rax, "tmp register must be eax for rep stos");
6805 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6806 assert(InitArrayShortSize % BytesPerLong == 0,
6807 "InitArrayShortSize should be the multiple of BytesPerLong");
6808
6809 Label DONE;
6810
6811 if (!is_large) {
6812 Label LOOP, LONG;
6813 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6814 jccb(Assembler::greater, LONG);
6815
6816 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6817
6818 decrement(cnt);
6819 jccb(Assembler::negative, DONE); // Zero length
6820
6821 // Use individual pointer-sized stores for small counts:
6822 BIND(LOOP);
6823 movptr(Address(base, cnt, Address::times_ptr), val);
6824 decrement(cnt);
6825 jccb(Assembler::greaterEqual, LOOP);
6826 jmpb(DONE);
6827
6828 BIND(LONG);
6829 }
6830
6831 // Use longer rep-prefixed ops for non-small counts:
6832 if (UseFastStosb && !word_copy_only) {
6833 shlptr(cnt, 3); // convert to number of bytes
6834 rep_stosb();
6835 } else if (UseXMMForObjInit) {
6836 xmm_clear_mem(base, cnt, val, xtmp);
6837 } else {
6838 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6839 rep_stos();
6840 }
6841
6842 BIND(DONE);
6843 }
6844
6845 #ifdef COMPILER2
6846
6847 // IndexOf for constant substrings with size >= 8 chars
6848 // which don't need to be loaded through stack.
6849 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6850 Register cnt1, Register cnt2,
6851 int int_cnt2, Register result,
6852 XMMRegister vec, Register tmp,
6853 int ae) {
6854 ShortBranchVerifier sbv(this);
6855 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6856 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6857
6858 // This method uses the pcmpestri instruction with bound registers
6859 // inputs:
6860 // xmm - substring
6861 // rax - substring length (elements count)
6862 // mem - scanned string
6863 // rdx - string length (elements count)
6864 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6865 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6866 // outputs:
6867 // rcx - matched index in string
6868 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6869 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6870 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6871 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6872 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6873
6874 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6875 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6876 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6877
6878 // Note, inline_string_indexOf() generates checks:
6879 // if (substr.count > string.count) return -1;
6880 // if (substr.count == 0) return 0;
6881 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
6882
6883 // Load substring.
6884 if (ae == StrIntrinsicNode::UL) {
6885 pmovzxbw(vec, Address(str2, 0));
6886 } else {
6887 movdqu(vec, Address(str2, 0));
6888 }
6889 movl(cnt2, int_cnt2);
6890 movptr(result, str1); // string addr
6891
6892 if (int_cnt2 > stride) {
6893 jmpb(SCAN_TO_SUBSTR);
6894
6895 // Reload substr for rescan, this code
6896 // is executed only for large substrings (> 8 chars)
6897 bind(RELOAD_SUBSTR);
6898 if (ae == StrIntrinsicNode::UL) {
6899 pmovzxbw(vec, Address(str2, 0));
6900 } else {
6901 movdqu(vec, Address(str2, 0));
6902 }
6903 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6904
6905 bind(RELOAD_STR);
6906 // We came here after the beginning of the substring was
6907 // matched but the rest of it was not so we need to search
6908 // again. Start from the next element after the previous match.
6909
6910 // cnt2 is number of substring reminding elements and
6911 // cnt1 is number of string reminding elements when cmp failed.
6912 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6913 subl(cnt1, cnt2);
6914 addl(cnt1, int_cnt2);
6915 movl(cnt2, int_cnt2); // Now restore cnt2
6916
6917 decrementl(cnt1); // Shift to next element
6918 cmpl(cnt1, cnt2);
6919 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6920
6921 addptr(result, (1<<scale1));
6922
6923 } // (int_cnt2 > 8)
6924
6925 // Scan string for start of substr in 16-byte vectors
6926 bind(SCAN_TO_SUBSTR);
6927 pcmpestri(vec, Address(result, 0), mode);
6928 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6929 subl(cnt1, stride);
6930 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6931 cmpl(cnt1, cnt2);
6932 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6933 addptr(result, 16);
6934 jmpb(SCAN_TO_SUBSTR);
6935
6936 // Found a potential substr
6937 bind(FOUND_CANDIDATE);
6938 // Matched whole vector if first element matched (tmp(rcx) == 0).
6939 if (int_cnt2 == stride) {
6940 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6941 } else { // int_cnt2 > 8
6942 jccb(Assembler::overflow, FOUND_SUBSTR);
6943 }
6944 // After pcmpestri tmp(rcx) contains matched element index
6945 // Compute start addr of substr
6946 lea(result, Address(result, tmp, scale1));
6947
6948 // Make sure string is still long enough
6949 subl(cnt1, tmp);
6950 cmpl(cnt1, cnt2);
6951 if (int_cnt2 == stride) {
6952 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6953 } else { // int_cnt2 > 8
6954 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6955 }
6956 // Left less then substring.
6957
6958 bind(RET_NOT_FOUND);
6959 movl(result, -1);
6960 jmp(EXIT);
6961
6962 if (int_cnt2 > stride) {
6963 // This code is optimized for the case when whole substring
6964 // is matched if its head is matched.
6965 bind(MATCH_SUBSTR_HEAD);
6966 pcmpestri(vec, Address(result, 0), mode);
6967 // Reload only string if does not match
6968 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
6969
6970 Label CONT_SCAN_SUBSTR;
6971 // Compare the rest of substring (> 8 chars).
6972 bind(FOUND_SUBSTR);
6973 // First 8 chars are already matched.
6974 negptr(cnt2);
6975 addptr(cnt2, stride);
6976
6977 bind(SCAN_SUBSTR);
6978 subl(cnt1, stride);
6979 cmpl(cnt2, -stride); // Do not read beyond substring
6980 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6981 // Back-up strings to avoid reading beyond substring:
6982 // cnt1 = cnt1 - cnt2 + 8
6983 addl(cnt1, cnt2); // cnt2 is negative
6984 addl(cnt1, stride);
6985 movl(cnt2, stride); negptr(cnt2);
6986 bind(CONT_SCAN_SUBSTR);
6987 if (int_cnt2 < (int)G) {
6988 int tail_off1 = int_cnt2<<scale1;
6989 int tail_off2 = int_cnt2<<scale2;
6990 if (ae == StrIntrinsicNode::UL) {
6991 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
6992 } else {
6993 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
6994 }
6995 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6996 } else {
6997 // calculate index in register to avoid integer overflow (int_cnt2*2)
6998 movl(tmp, int_cnt2);
6999 addptr(tmp, cnt2);
7000 if (ae == StrIntrinsicNode::UL) {
7001 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7002 } else {
7003 movdqu(vec, Address(str2, tmp, scale2, 0));
7004 }
7005 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7006 }
7007 // Need to reload strings pointers if not matched whole vector
7008 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7009 addptr(cnt2, stride);
7010 jcc(Assembler::negative, SCAN_SUBSTR);
7011 // Fall through if found full substring
7012
7013 } // (int_cnt2 > 8)
7014
7015 bind(RET_FOUND);
7016 // Found result if we matched full small substring.
7017 // Compute substr offset
7018 subptr(result, str1);
7019 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7020 shrl(result, 1); // index
7021 }
7022 bind(EXIT);
7023
7024 } // string_indexofC8
7025
7026 // Small strings are loaded through stack if they cross page boundary.
7027 void MacroAssembler::string_indexof(Register str1, Register str2,
7028 Register cnt1, Register cnt2,
7029 int int_cnt2, Register result,
7030 XMMRegister vec, Register tmp,
7031 int ae) {
7032 ShortBranchVerifier sbv(this);
7033 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7034 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7035
7036 //
7037 // int_cnt2 is length of small (< 8 chars) constant substring
7038 // or (-1) for non constant substring in which case its length
7039 // is in cnt2 register.
7040 //
7041 // Note, inline_string_indexOf() generates checks:
7042 // if (substr.count > string.count) return -1;
7043 // if (substr.count == 0) return 0;
7044 //
7045 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7046 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7047 // This method uses the pcmpestri instruction with bound registers
7048 // inputs:
7049 // xmm - substring
7050 // rax - substring length (elements count)
7051 // mem - scanned string
7052 // rdx - string length (elements count)
7053 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7054 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7055 // outputs:
7056 // rcx - matched index in string
7057 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7058 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7059 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7060 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7061
7062 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7063 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7064 FOUND_CANDIDATE;
7065
7066 { //========================================================
7067 // We don't know where these strings are located
7068 // and we can't read beyond them. Load them through stack.
7069 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7070
7071 movptr(tmp, rsp); // save old SP
7072
7073 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7074 if (int_cnt2 == (1>>scale2)) { // One byte
7075 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7076 load_unsigned_byte(result, Address(str2, 0));
7077 movdl(vec, result); // move 32 bits
7078 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7079 // Not enough header space in 32-bit VM: 12+3 = 15.
7080 movl(result, Address(str2, -1));
7081 shrl(result, 8);
7082 movdl(vec, result); // move 32 bits
7083 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7084 load_unsigned_short(result, Address(str2, 0));
7085 movdl(vec, result); // move 32 bits
7086 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7087 movdl(vec, Address(str2, 0)); // move 32 bits
7088 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7089 movq(vec, Address(str2, 0)); // move 64 bits
7090 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7091 // Array header size is 12 bytes in 32-bit VM
7092 // + 6 bytes for 3 chars == 18 bytes,
7093 // enough space to load vec and shift.
7094 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7095 if (ae == StrIntrinsicNode::UL) {
7096 int tail_off = int_cnt2-8;
7097 pmovzxbw(vec, Address(str2, tail_off));
7098 psrldq(vec, -2*tail_off);
7099 }
7100 else {
7101 int tail_off = int_cnt2*(1<<scale2);
7102 movdqu(vec, Address(str2, tail_off-16));
7103 psrldq(vec, 16-tail_off);
7104 }
7105 }
7106 } else { // not constant substring
7107 cmpl(cnt2, stride);
7108 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7109
7110 // We can read beyond string if srt+16 does not cross page boundary
7111 // since heaps are aligned and mapped by pages.
7112 assert(os::vm_page_size() < (int)G, "default page should be small");
7113 movl(result, str2); // We need only low 32 bits
7114 andl(result, (os::vm_page_size()-1));
7115 cmpl(result, (os::vm_page_size()-16));
7116 jccb(Assembler::belowEqual, CHECK_STR);
7117
7118 // Move small strings to stack to allow load 16 bytes into vec.
7119 subptr(rsp, 16);
7120 int stk_offset = wordSize-(1<<scale2);
7121 push(cnt2);
7122
7123 bind(COPY_SUBSTR);
7124 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7125 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7126 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7127 } else if (ae == StrIntrinsicNode::UU) {
7128 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7129 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7130 }
7131 decrement(cnt2);
7132 jccb(Assembler::notZero, COPY_SUBSTR);
7133
7134 pop(cnt2);
7135 movptr(str2, rsp); // New substring address
7136 } // non constant
7137
7138 bind(CHECK_STR);
7139 cmpl(cnt1, stride);
7140 jccb(Assembler::aboveEqual, BIG_STRINGS);
7141
7142 // Check cross page boundary.
7143 movl(result, str1); // We need only low 32 bits
7144 andl(result, (os::vm_page_size()-1));
7145 cmpl(result, (os::vm_page_size()-16));
7146 jccb(Assembler::belowEqual, BIG_STRINGS);
7147
7148 subptr(rsp, 16);
7149 int stk_offset = -(1<<scale1);
7150 if (int_cnt2 < 0) { // not constant
7151 push(cnt2);
7152 stk_offset += wordSize;
7153 }
7154 movl(cnt2, cnt1);
7155
7156 bind(COPY_STR);
7157 if (ae == StrIntrinsicNode::LL) {
7158 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7159 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7160 } else {
7161 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7162 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7163 }
7164 decrement(cnt2);
7165 jccb(Assembler::notZero, COPY_STR);
7166
7167 if (int_cnt2 < 0) { // not constant
7168 pop(cnt2);
7169 }
7170 movptr(str1, rsp); // New string address
7171
7172 bind(BIG_STRINGS);
7173 // Load substring.
7174 if (int_cnt2 < 0) { // -1
7175 if (ae == StrIntrinsicNode::UL) {
7176 pmovzxbw(vec, Address(str2, 0));
7177 } else {
7178 movdqu(vec, Address(str2, 0));
7179 }
7180 push(cnt2); // substr count
7181 push(str2); // substr addr
7182 push(str1); // string addr
7183 } else {
7184 // Small (< 8 chars) constant substrings are loaded already.
7185 movl(cnt2, int_cnt2);
7186 }
7187 push(tmp); // original SP
7188
7189 } // Finished loading
7190
7191 //========================================================
7192 // Start search
7193 //
7194
7195 movptr(result, str1); // string addr
7196
7197 if (int_cnt2 < 0) { // Only for non constant substring
7198 jmpb(SCAN_TO_SUBSTR);
7199
7200 // SP saved at sp+0
7201 // String saved at sp+1*wordSize
7202 // Substr saved at sp+2*wordSize
7203 // Substr count saved at sp+3*wordSize
7204
7205 // Reload substr for rescan, this code
7206 // is executed only for large substrings (> 8 chars)
7207 bind(RELOAD_SUBSTR);
7208 movptr(str2, Address(rsp, 2*wordSize));
7209 movl(cnt2, Address(rsp, 3*wordSize));
7210 if (ae == StrIntrinsicNode::UL) {
7211 pmovzxbw(vec, Address(str2, 0));
7212 } else {
7213 movdqu(vec, Address(str2, 0));
7214 }
7215 // We came here after the beginning of the substring was
7216 // matched but the rest of it was not so we need to search
7217 // again. Start from the next element after the previous match.
7218 subptr(str1, result); // Restore counter
7219 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7220 shrl(str1, 1);
7221 }
7222 addl(cnt1, str1);
7223 decrementl(cnt1); // Shift to next element
7224 cmpl(cnt1, cnt2);
7225 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7226
7227 addptr(result, (1<<scale1));
7228 } // non constant
7229
7230 // Scan string for start of substr in 16-byte vectors
7231 bind(SCAN_TO_SUBSTR);
7232 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7233 pcmpestri(vec, Address(result, 0), mode);
7234 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7235 subl(cnt1, stride);
7236 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7237 cmpl(cnt1, cnt2);
7238 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7239 addptr(result, 16);
7240
7241 bind(ADJUST_STR);
7242 cmpl(cnt1, stride); // Do not read beyond string
7243 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7244 // Back-up string to avoid reading beyond string.
7245 lea(result, Address(result, cnt1, scale1, -16));
7246 movl(cnt1, stride);
7247 jmpb(SCAN_TO_SUBSTR);
7248
7249 // Found a potential substr
7250 bind(FOUND_CANDIDATE);
7251 // After pcmpestri tmp(rcx) contains matched element index
7252
7253 // Make sure string is still long enough
7254 subl(cnt1, tmp);
7255 cmpl(cnt1, cnt2);
7256 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7257 // Left less then substring.
7258
7259 bind(RET_NOT_FOUND);
7260 movl(result, -1);
7261 jmp(CLEANUP);
7262
7263 bind(FOUND_SUBSTR);
7264 // Compute start addr of substr
7265 lea(result, Address(result, tmp, scale1));
7266 if (int_cnt2 > 0) { // Constant substring
7267 // Repeat search for small substring (< 8 chars)
7268 // from new point without reloading substring.
7269 // Have to check that we don't read beyond string.
7270 cmpl(tmp, stride-int_cnt2);
7271 jccb(Assembler::greater, ADJUST_STR);
7272 // Fall through if matched whole substring.
7273 } else { // non constant
7274 assert(int_cnt2 == -1, "should be != 0");
7275
7276 addl(tmp, cnt2);
7277 // Found result if we matched whole substring.
7278 cmpl(tmp, stride);
7279 jcc(Assembler::lessEqual, RET_FOUND);
7280
7281 // Repeat search for small substring (<= 8 chars)
7282 // from new point 'str1' without reloading substring.
7283 cmpl(cnt2, stride);
7284 // Have to check that we don't read beyond string.
7285 jccb(Assembler::lessEqual, ADJUST_STR);
7286
7287 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7288 // Compare the rest of substring (> 8 chars).
7289 movptr(str1, result);
7290
7291 cmpl(tmp, cnt2);
7292 // First 8 chars are already matched.
7293 jccb(Assembler::equal, CHECK_NEXT);
7294
7295 bind(SCAN_SUBSTR);
7296 pcmpestri(vec, Address(str1, 0), mode);
7297 // Need to reload strings pointers if not matched whole vector
7298 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7299
7300 bind(CHECK_NEXT);
7301 subl(cnt2, stride);
7302 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7303 addptr(str1, 16);
7304 if (ae == StrIntrinsicNode::UL) {
7305 addptr(str2, 8);
7306 } else {
7307 addptr(str2, 16);
7308 }
7309 subl(cnt1, stride);
7310 cmpl(cnt2, stride); // Do not read beyond substring
7311 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7312 // Back-up strings to avoid reading beyond substring.
7313
7314 if (ae == StrIntrinsicNode::UL) {
7315 lea(str2, Address(str2, cnt2, scale2, -8));
7316 lea(str1, Address(str1, cnt2, scale1, -16));
7317 } else {
7318 lea(str2, Address(str2, cnt2, scale2, -16));
7319 lea(str1, Address(str1, cnt2, scale1, -16));
7320 }
7321 subl(cnt1, cnt2);
7322 movl(cnt2, stride);
7323 addl(cnt1, stride);
7324 bind(CONT_SCAN_SUBSTR);
7325 if (ae == StrIntrinsicNode::UL) {
7326 pmovzxbw(vec, Address(str2, 0));
7327 } else {
7328 movdqu(vec, Address(str2, 0));
7329 }
7330 jmp(SCAN_SUBSTR);
7331
7332 bind(RET_FOUND_LONG);
7333 movptr(str1, Address(rsp, wordSize));
7334 } // non constant
7335
7336 bind(RET_FOUND);
7337 // Compute substr offset
7338 subptr(result, str1);
7339 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7340 shrl(result, 1); // index
7341 }
7342 bind(CLEANUP);
7343 pop(rsp); // restore SP
7344
7345 } // string_indexof
7346
7347 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7348 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7349 ShortBranchVerifier sbv(this);
7350 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7351
7352 int stride = 8;
7353
7354 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7355 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7356 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7357 FOUND_SEQ_CHAR, DONE_LABEL;
7358
7359 movptr(result, str1);
7360 if (UseAVX >= 2) {
7361 cmpl(cnt1, stride);
7362 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7363 cmpl(cnt1, 2*stride);
7364 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7365 movdl(vec1, ch);
7366 vpbroadcastw(vec1, vec1);
7367 vpxor(vec2, vec2);
7368 movl(tmp, cnt1);
7369 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7370 andl(cnt1,0x0000000F); //tail count (in chars)
7371
7372 bind(SCAN_TO_16_CHAR_LOOP);
7373 vmovdqu(vec3, Address(result, 0));
7374 vpcmpeqw(vec3, vec3, vec1, 1);
7375 vptest(vec2, vec3);
7376 jcc(Assembler::carryClear, FOUND_CHAR);
7377 addptr(result, 32);
7378 subl(tmp, 2*stride);
7379 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7380 jmp(SCAN_TO_8_CHAR);
7381 bind(SCAN_TO_8_CHAR_INIT);
7382 movdl(vec1, ch);
7383 pshuflw(vec1, vec1, 0x00);
7384 pshufd(vec1, vec1, 0);
7385 pxor(vec2, vec2);
7386 }
7387 bind(SCAN_TO_8_CHAR);
7388 cmpl(cnt1, stride);
7389 if (UseAVX >= 2) {
7390 jcc(Assembler::less, SCAN_TO_CHAR);
7391 } else {
7392 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7393 movdl(vec1, ch);
7394 pshuflw(vec1, vec1, 0x00);
7395 pshufd(vec1, vec1, 0);
7396 pxor(vec2, vec2);
7397 }
7398 movl(tmp, cnt1);
7399 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7400 andl(cnt1,0x00000007); //tail count (in chars)
7401
7402 bind(SCAN_TO_8_CHAR_LOOP);
7403 movdqu(vec3, Address(result, 0));
7404 pcmpeqw(vec3, vec1);
7405 ptest(vec2, vec3);
7406 jcc(Assembler::carryClear, FOUND_CHAR);
7407 addptr(result, 16);
7408 subl(tmp, stride);
7409 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7410 bind(SCAN_TO_CHAR);
7411 testl(cnt1, cnt1);
7412 jcc(Assembler::zero, RET_NOT_FOUND);
7413 bind(SCAN_TO_CHAR_LOOP);
7414 load_unsigned_short(tmp, Address(result, 0));
7415 cmpl(ch, tmp);
7416 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7417 addptr(result, 2);
7418 subl(cnt1, 1);
7419 jccb(Assembler::zero, RET_NOT_FOUND);
7420 jmp(SCAN_TO_CHAR_LOOP);
7421
7422 bind(RET_NOT_FOUND);
7423 movl(result, -1);
7424 jmpb(DONE_LABEL);
7425
7426 bind(FOUND_CHAR);
7427 if (UseAVX >= 2) {
7428 vpmovmskb(tmp, vec3);
7429 } else {
7430 pmovmskb(tmp, vec3);
7431 }
7432 bsfl(ch, tmp);
7433 addl(result, ch);
7434
7435 bind(FOUND_SEQ_CHAR);
7436 subptr(result, str1);
7437 shrl(result, 1);
7438
7439 bind(DONE_LABEL);
7440 } // string_indexof_char
7441
7442 // helper function for string_compare
7443 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7444 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7445 Address::ScaleFactor scale2, Register index, int ae) {
7446 if (ae == StrIntrinsicNode::LL) {
7447 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7448 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7449 } else if (ae == StrIntrinsicNode::UU) {
7450 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7451 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7452 } else {
7453 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7454 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7455 }
7456 }
7457
7458 // Compare strings, used for char[] and byte[].
7459 void MacroAssembler::string_compare(Register str1, Register str2,
7460 Register cnt1, Register cnt2, Register result,
7461 XMMRegister vec1, int ae) {
7462 ShortBranchVerifier sbv(this);
7463 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7464 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7465 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7466 int stride2x2 = 0x40;
7467 Address::ScaleFactor scale = Address::no_scale;
7468 Address::ScaleFactor scale1 = Address::no_scale;
7469 Address::ScaleFactor scale2 = Address::no_scale;
7470
7471 if (ae != StrIntrinsicNode::LL) {
7472 stride2x2 = 0x20;
7473 }
7474
7475 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7476 shrl(cnt2, 1);
7477 }
7478 // Compute the minimum of the string lengths and the
7479 // difference of the string lengths (stack).
7480 // Do the conditional move stuff
7481 movl(result, cnt1);
7482 subl(cnt1, cnt2);
7483 push(cnt1);
7484 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7485
7486 // Is the minimum length zero?
7487 testl(cnt2, cnt2);
7488 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7489 if (ae == StrIntrinsicNode::LL) {
7490 // Load first bytes
7491 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7492 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7493 } else if (ae == StrIntrinsicNode::UU) {
7494 // Load first characters
7495 load_unsigned_short(result, Address(str1, 0));
7496 load_unsigned_short(cnt1, Address(str2, 0));
7497 } else {
7498 load_unsigned_byte(result, Address(str1, 0));
7499 load_unsigned_short(cnt1, Address(str2, 0));
7500 }
7501 subl(result, cnt1);
7502 jcc(Assembler::notZero, POP_LABEL);
7503
7504 if (ae == StrIntrinsicNode::UU) {
7505 // Divide length by 2 to get number of chars
7506 shrl(cnt2, 1);
7507 }
7508 cmpl(cnt2, 1);
7509 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7510
7511 // Check if the strings start at the same location and setup scale and stride
7512 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7513 cmpptr(str1, str2);
7514 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7515 if (ae == StrIntrinsicNode::LL) {
7516 scale = Address::times_1;
7517 stride = 16;
7518 } else {
7519 scale = Address::times_2;
7520 stride = 8;
7521 }
7522 } else {
7523 scale1 = Address::times_1;
7524 scale2 = Address::times_2;
7525 // scale not used
7526 stride = 8;
7527 }
7528
7529 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7530 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7531 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7532 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7533 Label COMPARE_TAIL_LONG;
7534 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7535
7536 int pcmpmask = 0x19;
7537 if (ae == StrIntrinsicNode::LL) {
7538 pcmpmask &= ~0x01;
7539 }
7540
7541 // Setup to compare 16-chars (32-bytes) vectors,
7542 // start from first character again because it has aligned address.
7543 if (ae == StrIntrinsicNode::LL) {
7544 stride2 = 32;
7545 } else {
7546 stride2 = 16;
7547 }
7548 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7549 adr_stride = stride << scale;
7550 } else {
7551 adr_stride1 = 8; //stride << scale1;
7552 adr_stride2 = 16; //stride << scale2;
7553 }
7554
7555 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7556 // rax and rdx are used by pcmpestri as elements counters
7557 movl(result, cnt2);
7558 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7559 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7560
7561 // fast path : compare first 2 8-char vectors.
7562 bind(COMPARE_16_CHARS);
7563 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7564 movdqu(vec1, Address(str1, 0));
7565 } else {
7566 pmovzxbw(vec1, Address(str1, 0));
7567 }
7568 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7569 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7570
7571 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7572 movdqu(vec1, Address(str1, adr_stride));
7573 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7574 } else {
7575 pmovzxbw(vec1, Address(str1, adr_stride1));
7576 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7577 }
7578 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7579 addl(cnt1, stride);
7580
7581 // Compare the characters at index in cnt1
7582 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7583 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7584 subl(result, cnt2);
7585 jmp(POP_LABEL);
7586
7587 // Setup the registers to start vector comparison loop
7588 bind(COMPARE_WIDE_VECTORS);
7589 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7590 lea(str1, Address(str1, result, scale));
7591 lea(str2, Address(str2, result, scale));
7592 } else {
7593 lea(str1, Address(str1, result, scale1));
7594 lea(str2, Address(str2, result, scale2));
7595 }
7596 subl(result, stride2);
7597 subl(cnt2, stride2);
7598 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7599 negptr(result);
7600
7601 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7602 bind(COMPARE_WIDE_VECTORS_LOOP);
7603
7604 #ifdef _LP64
7605 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7606 cmpl(cnt2, stride2x2);
7607 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7608 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7609 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7610
7611 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7612 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7613 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7614 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7615 } else {
7616 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7617 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7618 }
7619 kortestql(k7, k7);
7620 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7621 addptr(result, stride2x2); // update since we already compared at this addr
7622 subl(cnt2, stride2x2); // and sub the size too
7623 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7624
7625 vpxor(vec1, vec1);
7626 jmpb(COMPARE_WIDE_TAIL);
7627 }//if (VM_Version::supports_avx512vlbw())
7628 #endif // _LP64
7629
7630
7631 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7632 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7633 vmovdqu(vec1, Address(str1, result, scale));
7634 vpxor(vec1, Address(str2, result, scale));
7635 } else {
7636 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7637 vpxor(vec1, Address(str2, result, scale2));
7638 }
7639 vptest(vec1, vec1);
7640 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7641 addptr(result, stride2);
7642 subl(cnt2, stride2);
7643 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7644 // clean upper bits of YMM registers
7645 vpxor(vec1, vec1);
7646
7647 // compare wide vectors tail
7648 bind(COMPARE_WIDE_TAIL);
7649 testptr(result, result);
7650 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7651
7652 movl(result, stride2);
7653 movl(cnt2, result);
7654 negptr(result);
7655 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7656
7657 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7658 bind(VECTOR_NOT_EQUAL);
7659 // clean upper bits of YMM registers
7660 vpxor(vec1, vec1);
7661 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7662 lea(str1, Address(str1, result, scale));
7663 lea(str2, Address(str2, result, scale));
7664 } else {
7665 lea(str1, Address(str1, result, scale1));
7666 lea(str2, Address(str2, result, scale2));
7667 }
7668 jmp(COMPARE_16_CHARS);
7669
7670 // Compare tail chars, length between 1 to 15 chars
7671 bind(COMPARE_TAIL_LONG);
7672 movl(cnt2, result);
7673 cmpl(cnt2, stride);
7674 jcc(Assembler::less, COMPARE_SMALL_STR);
7675
7676 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7677 movdqu(vec1, Address(str1, 0));
7678 } else {
7679 pmovzxbw(vec1, Address(str1, 0));
7680 }
7681 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7682 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7683 subptr(cnt2, stride);
7684 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7685 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7686 lea(str1, Address(str1, result, scale));
7687 lea(str2, Address(str2, result, scale));
7688 } else {
7689 lea(str1, Address(str1, result, scale1));
7690 lea(str2, Address(str2, result, scale2));
7691 }
7692 negptr(cnt2);
7693 jmpb(WHILE_HEAD_LABEL);
7694
7695 bind(COMPARE_SMALL_STR);
7696 } else if (UseSSE42Intrinsics) {
7697 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7698 int pcmpmask = 0x19;
7699 // Setup to compare 8-char (16-byte) vectors,
7700 // start from first character again because it has aligned address.
7701 movl(result, cnt2);
7702 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7703 if (ae == StrIntrinsicNode::LL) {
7704 pcmpmask &= ~0x01;
7705 }
7706 jcc(Assembler::zero, COMPARE_TAIL);
7707 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7708 lea(str1, Address(str1, result, scale));
7709 lea(str2, Address(str2, result, scale));
7710 } else {
7711 lea(str1, Address(str1, result, scale1));
7712 lea(str2, Address(str2, result, scale2));
7713 }
7714 negptr(result);
7715
7716 // pcmpestri
7717 // inputs:
7718 // vec1- substring
7719 // rax - negative string length (elements count)
7720 // mem - scanned string
7721 // rdx - string length (elements count)
7722 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7723 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7724 // outputs:
7725 // rcx - first mismatched element index
7726 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7727
7728 bind(COMPARE_WIDE_VECTORS);
7729 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7730 movdqu(vec1, Address(str1, result, scale));
7731 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7732 } else {
7733 pmovzxbw(vec1, Address(str1, result, scale1));
7734 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7735 }
7736 // After pcmpestri cnt1(rcx) contains mismatched element index
7737
7738 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
7739 addptr(result, stride);
7740 subptr(cnt2, stride);
7741 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
7742
7743 // compare wide vectors tail
7744 testptr(result, result);
7745 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7746
7747 movl(cnt2, stride);
7748 movl(result, stride);
7749 negptr(result);
7750 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7751 movdqu(vec1, Address(str1, result, scale));
7752 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7753 } else {
7754 pmovzxbw(vec1, Address(str1, result, scale1));
7755 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7756 }
7757 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
7758
7759 // Mismatched characters in the vectors
7760 bind(VECTOR_NOT_EQUAL);
7761 addptr(cnt1, result);
7762 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7763 subl(result, cnt2);
7764 jmpb(POP_LABEL);
7765
7766 bind(COMPARE_TAIL); // limit is zero
7767 movl(cnt2, result);
7768 // Fallthru to tail compare
7769 }
7770 // Shift str2 and str1 to the end of the arrays, negate min
7771 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7772 lea(str1, Address(str1, cnt2, scale));
7773 lea(str2, Address(str2, cnt2, scale));
7774 } else {
7775 lea(str1, Address(str1, cnt2, scale1));
7776 lea(str2, Address(str2, cnt2, scale2));
7777 }
7778 decrementl(cnt2); // first character was compared already
7779 negptr(cnt2);
7780
7781 // Compare the rest of the elements
7782 bind(WHILE_HEAD_LABEL);
7783 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
7784 subl(result, cnt1);
7785 jccb(Assembler::notZero, POP_LABEL);
7786 increment(cnt2);
7787 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
7788
7789 // Strings are equal up to min length. Return the length difference.
7790 bind(LENGTH_DIFF_LABEL);
7791 pop(result);
7792 if (ae == StrIntrinsicNode::UU) {
7793 // Divide diff by 2 to get number of chars
7794 sarl(result, 1);
7795 }
7796 jmpb(DONE_LABEL);
7797
7798 #ifdef _LP64
7799 if (VM_Version::supports_avx512vlbw()) {
7800
7801 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
7802
7803 kmovql(cnt1, k7);
7804 notq(cnt1);
7805 bsfq(cnt2, cnt1);
7806 if (ae != StrIntrinsicNode::LL) {
7807 // Divide diff by 2 to get number of chars
7808 sarl(cnt2, 1);
7809 }
7810 addq(result, cnt2);
7811 if (ae == StrIntrinsicNode::LL) {
7812 load_unsigned_byte(cnt1, Address(str2, result));
7813 load_unsigned_byte(result, Address(str1, result));
7814 } else if (ae == StrIntrinsicNode::UU) {
7815 load_unsigned_short(cnt1, Address(str2, result, scale));
7816 load_unsigned_short(result, Address(str1, result, scale));
7817 } else {
7818 load_unsigned_short(cnt1, Address(str2, result, scale2));
7819 load_unsigned_byte(result, Address(str1, result, scale1));
7820 }
7821 subl(result, cnt1);
7822 jmpb(POP_LABEL);
7823 }//if (VM_Version::supports_avx512vlbw())
7824 #endif // _LP64
7825
7826 // Discard the stored length difference
7827 bind(POP_LABEL);
7828 pop(cnt1);
7829
7830 // That's it
7831 bind(DONE_LABEL);
7832 if(ae == StrIntrinsicNode::UL) {
7833 negl(result);
7834 }
7835
7836 }
7837
7838 // Search for Non-ASCII character (Negative byte value) in a byte array,
7839 // return true if it has any and false otherwise.
7840 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
7841 // @HotSpotIntrinsicCandidate
7842 // private static boolean hasNegatives(byte[] ba, int off, int len) {
7843 // for (int i = off; i < off + len; i++) {
7844 // if (ba[i] < 0) {
7845 // return true;
7846 // }
7847 // }
7848 // return false;
7849 // }
7850 void MacroAssembler::has_negatives(Register ary1, Register len,
7851 Register result, Register tmp1,
7852 XMMRegister vec1, XMMRegister vec2) {
7853 // rsi: byte array
7854 // rcx: len
7855 // rax: result
7856 ShortBranchVerifier sbv(this);
7857 assert_different_registers(ary1, len, result, tmp1);
7858 assert_different_registers(vec1, vec2);
7859 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
7860
7861 // len == 0
7862 testl(len, len);
7863 jcc(Assembler::zero, FALSE_LABEL);
7864
7865 if ((UseAVX > 2) && // AVX512
7866 VM_Version::supports_avx512vlbw() &&
7867 VM_Version::supports_bmi2()) {
7868
7869 set_vector_masking(); // opening of the stub context for programming mask registers
7870
7871 Label test_64_loop, test_tail;
7872 Register tmp3_aliased = len;
7873
7874 movl(tmp1, len);
7875 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
7876
7877 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
7878 andl(len, ~(64 - 1)); // vector count (in chars)
7879 jccb(Assembler::zero, test_tail);
7880
7881 lea(ary1, Address(ary1, len, Address::times_1));
7882 negptr(len);
7883
7884 bind(test_64_loop);
7885 // Check whether our 64 elements of size byte contain negatives
7886 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
7887 kortestql(k2, k2);
7888 jcc(Assembler::notZero, TRUE_LABEL);
7889
7890 addptr(len, 64);
7891 jccb(Assembler::notZero, test_64_loop);
7892
7893
7894 bind(test_tail);
7895 // bail out when there is nothing to be done
7896 testl(tmp1, -1);
7897 jcc(Assembler::zero, FALSE_LABEL);
7898
7899 // Save k1
7900 kmovql(k3, k1);
7901
7902 // ~(~0 << len) applied up to two times (for 32-bit scenario)
7903 #ifdef _LP64
7904 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
7905 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
7906 notq(tmp3_aliased);
7907 kmovql(k1, tmp3_aliased);
7908 #else
7909 Label k_init;
7910 jmp(k_init);
7911
7912 // We could not read 64-bits from a general purpose register thus we move
7913 // data required to compose 64 1's to the instruction stream
7914 // We emit 64 byte wide series of elements from 0..63 which later on would
7915 // be used as a compare targets with tail count contained in tmp1 register.
7916 // Result would be a k1 register having tmp1 consecutive number or 1
7917 // counting from least significant bit.
7918 address tmp = pc();
7919 emit_int64(0x0706050403020100);
7920 emit_int64(0x0F0E0D0C0B0A0908);
7921 emit_int64(0x1716151413121110);
7922 emit_int64(0x1F1E1D1C1B1A1918);
7923 emit_int64(0x2726252423222120);
7924 emit_int64(0x2F2E2D2C2B2A2928);
7925 emit_int64(0x3736353433323130);
7926 emit_int64(0x3F3E3D3C3B3A3938);
7927
7928 bind(k_init);
7929 lea(len, InternalAddress(tmp));
7930 // create mask to test for negative byte inside a vector
7931 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
7932 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
7933
7934 #endif
7935 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
7936 ktestq(k2, k1);
7937 // Restore k1
7938 kmovql(k1, k3);
7939 jcc(Assembler::notZero, TRUE_LABEL);
7940
7941 jmp(FALSE_LABEL);
7942
7943 clear_vector_masking(); // closing of the stub context for programming mask registers
7944 } else {
7945 movl(result, len); // copy
7946
7947 if (UseAVX == 2 && UseSSE >= 2) {
7948 // With AVX2, use 32-byte vector compare
7949 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7950
7951 // Compare 32-byte vectors
7952 andl(result, 0x0000001f); // tail count (in bytes)
7953 andl(len, 0xffffffe0); // vector count (in bytes)
7954 jccb(Assembler::zero, COMPARE_TAIL);
7955
7956 lea(ary1, Address(ary1, len, Address::times_1));
7957 negptr(len);
7958
7959 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
7960 movdl(vec2, tmp1);
7961 vpbroadcastd(vec2, vec2);
7962
7963 bind(COMPARE_WIDE_VECTORS);
7964 vmovdqu(vec1, Address(ary1, len, Address::times_1));
7965 vptest(vec1, vec2);
7966 jccb(Assembler::notZero, TRUE_LABEL);
7967 addptr(len, 32);
7968 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7969
7970 testl(result, result);
7971 jccb(Assembler::zero, FALSE_LABEL);
7972
7973 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7974 vptest(vec1, vec2);
7975 jccb(Assembler::notZero, TRUE_LABEL);
7976 jmpb(FALSE_LABEL);
7977
7978 bind(COMPARE_TAIL); // len is zero
7979 movl(len, result);
7980 // Fallthru to tail compare
7981 } else if (UseSSE42Intrinsics) {
7982 // With SSE4.2, use double quad vector compare
7983 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7984
7985 // Compare 16-byte vectors
7986 andl(result, 0x0000000f); // tail count (in bytes)
7987 andl(len, 0xfffffff0); // vector count (in bytes)
7988 jcc(Assembler::zero, COMPARE_TAIL);
7989
7990 lea(ary1, Address(ary1, len, Address::times_1));
7991 negptr(len);
7992
7993 movl(tmp1, 0x80808080);
7994 movdl(vec2, tmp1);
7995 pshufd(vec2, vec2, 0);
7996
7997 bind(COMPARE_WIDE_VECTORS);
7998 movdqu(vec1, Address(ary1, len, Address::times_1));
7999 ptest(vec1, vec2);
8000 jcc(Assembler::notZero, TRUE_LABEL);
8001 addptr(len, 16);
8002 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8003
8004 testl(result, result);
8005 jcc(Assembler::zero, FALSE_LABEL);
8006
8007 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8008 ptest(vec1, vec2);
8009 jccb(Assembler::notZero, TRUE_LABEL);
8010 jmpb(FALSE_LABEL);
8011
8012 bind(COMPARE_TAIL); // len is zero
8013 movl(len, result);
8014 // Fallthru to tail compare
8015 }
8016 }
8017 // Compare 4-byte vectors
8018 andl(len, 0xfffffffc); // vector count (in bytes)
8019 jccb(Assembler::zero, COMPARE_CHAR);
8020
8021 lea(ary1, Address(ary1, len, Address::times_1));
8022 negptr(len);
8023
8024 bind(COMPARE_VECTORS);
8025 movl(tmp1, Address(ary1, len, Address::times_1));
8026 andl(tmp1, 0x80808080);
8027 jccb(Assembler::notZero, TRUE_LABEL);
8028 addptr(len, 4);
8029 jcc(Assembler::notZero, COMPARE_VECTORS);
8030
8031 // Compare trailing char (final 2 bytes), if any
8032 bind(COMPARE_CHAR);
8033 testl(result, 0x2); // tail char
8034 jccb(Assembler::zero, COMPARE_BYTE);
8035 load_unsigned_short(tmp1, Address(ary1, 0));
8036 andl(tmp1, 0x00008080);
8037 jccb(Assembler::notZero, TRUE_LABEL);
8038 subptr(result, 2);
8039 lea(ary1, Address(ary1, 2));
8040
8041 bind(COMPARE_BYTE);
8042 testl(result, 0x1); // tail byte
8043 jccb(Assembler::zero, FALSE_LABEL);
8044 load_unsigned_byte(tmp1, Address(ary1, 0));
8045 andl(tmp1, 0x00000080);
8046 jccb(Assembler::notEqual, TRUE_LABEL);
8047 jmpb(FALSE_LABEL);
8048
8049 bind(TRUE_LABEL);
8050 movl(result, 1); // return true
8051 jmpb(DONE);
8052
8053 bind(FALSE_LABEL);
8054 xorl(result, result); // return false
8055
8056 // That's it
8057 bind(DONE);
8058 if (UseAVX >= 2 && UseSSE >= 2) {
8059 // clean upper bits of YMM registers
8060 vpxor(vec1, vec1);
8061 vpxor(vec2, vec2);
8062 }
8063 }
8064 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8065 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8066 Register limit, Register result, Register chr,
8067 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8068 ShortBranchVerifier sbv(this);
8069 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8070
8071 int length_offset = arrayOopDesc::length_offset_in_bytes();
8072 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8073
8074 if (is_array_equ) {
8075 // Check the input args
8076 cmpoop(ary1, ary2);
8077 jcc(Assembler::equal, TRUE_LABEL);
8078
8079 // Need additional checks for arrays_equals.
8080 testptr(ary1, ary1);
8081 jcc(Assembler::zero, FALSE_LABEL);
8082 testptr(ary2, ary2);
8083 jcc(Assembler::zero, FALSE_LABEL);
8084
8085 // Check the lengths
8086 movl(limit, Address(ary1, length_offset));
8087 cmpl(limit, Address(ary2, length_offset));
8088 jcc(Assembler::notEqual, FALSE_LABEL);
8089 }
8090
8091 // count == 0
8092 testl(limit, limit);
8093 jcc(Assembler::zero, TRUE_LABEL);
8094
8095 if (is_array_equ) {
8096 // Load array address
8097 lea(ary1, Address(ary1, base_offset));
8098 lea(ary2, Address(ary2, base_offset));
8099 }
8100
8101 if (is_array_equ && is_char) {
8102 // arrays_equals when used for char[].
8103 shll(limit, 1); // byte count != 0
8104 }
8105 movl(result, limit); // copy
8106
8107 if (UseAVX >= 2) {
8108 // With AVX2, use 32-byte vector compare
8109 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8110
8111 // Compare 32-byte vectors
8112 andl(result, 0x0000001f); // tail count (in bytes)
8113 andl(limit, 0xffffffe0); // vector count (in bytes)
8114 jcc(Assembler::zero, COMPARE_TAIL);
8115
8116 lea(ary1, Address(ary1, limit, Address::times_1));
8117 lea(ary2, Address(ary2, limit, Address::times_1));
8118 negptr(limit);
8119
8120 bind(COMPARE_WIDE_VECTORS);
8121
8122 #ifdef _LP64
8123 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8124 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8125
8126 cmpl(limit, -64);
8127 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8128
8129 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8130
8131 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8132 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8133 kortestql(k7, k7);
8134 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8135 addptr(limit, 64); // update since we already compared at this addr
8136 cmpl(limit, -64);
8137 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8138
8139 // At this point we may still need to compare -limit+result bytes.
8140 // We could execute the next two instruction and just continue via non-wide path:
8141 // cmpl(limit, 0);
8142 // jcc(Assembler::equal, COMPARE_TAIL); // true
8143 // But since we stopped at the points ary{1,2}+limit which are
8144 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8145 // (|limit| <= 32 and result < 32),
8146 // we may just compare the last 64 bytes.
8147 //
8148 addptr(result, -64); // it is safe, bc we just came from this area
8149 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8150 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8151 kortestql(k7, k7);
8152 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8153
8154 jmp(TRUE_LABEL);
8155
8156 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8157
8158 }//if (VM_Version::supports_avx512vlbw())
8159 #endif //_LP64
8160
8161 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8162 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8163 vpxor(vec1, vec2);
8164
8165 vptest(vec1, vec1);
8166 jcc(Assembler::notZero, FALSE_LABEL);
8167 addptr(limit, 32);
8168 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8169
8170 testl(result, result);
8171 jcc(Assembler::zero, TRUE_LABEL);
8172
8173 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8174 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8175 vpxor(vec1, vec2);
8176
8177 vptest(vec1, vec1);
8178 jccb(Assembler::notZero, FALSE_LABEL);
8179 jmpb(TRUE_LABEL);
8180
8181 bind(COMPARE_TAIL); // limit is zero
8182 movl(limit, result);
8183 // Fallthru to tail compare
8184 } else if (UseSSE42Intrinsics) {
8185 // With SSE4.2, use double quad vector compare
8186 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8187
8188 // Compare 16-byte vectors
8189 andl(result, 0x0000000f); // tail count (in bytes)
8190 andl(limit, 0xfffffff0); // vector count (in bytes)
8191 jcc(Assembler::zero, COMPARE_TAIL);
8192
8193 lea(ary1, Address(ary1, limit, Address::times_1));
8194 lea(ary2, Address(ary2, limit, Address::times_1));
8195 negptr(limit);
8196
8197 bind(COMPARE_WIDE_VECTORS);
8198 movdqu(vec1, Address(ary1, limit, Address::times_1));
8199 movdqu(vec2, Address(ary2, limit, Address::times_1));
8200 pxor(vec1, vec2);
8201
8202 ptest(vec1, vec1);
8203 jcc(Assembler::notZero, FALSE_LABEL);
8204 addptr(limit, 16);
8205 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8206
8207 testl(result, result);
8208 jcc(Assembler::zero, TRUE_LABEL);
8209
8210 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8211 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8212 pxor(vec1, vec2);
8213
8214 ptest(vec1, vec1);
8215 jccb(Assembler::notZero, FALSE_LABEL);
8216 jmpb(TRUE_LABEL);
8217
8218 bind(COMPARE_TAIL); // limit is zero
8219 movl(limit, result);
8220 // Fallthru to tail compare
8221 }
8222
8223 // Compare 4-byte vectors
8224 andl(limit, 0xfffffffc); // vector count (in bytes)
8225 jccb(Assembler::zero, COMPARE_CHAR);
8226
8227 lea(ary1, Address(ary1, limit, Address::times_1));
8228 lea(ary2, Address(ary2, limit, Address::times_1));
8229 negptr(limit);
8230
8231 bind(COMPARE_VECTORS);
8232 movl(chr, Address(ary1, limit, Address::times_1));
8233 cmpl(chr, Address(ary2, limit, Address::times_1));
8234 jccb(Assembler::notEqual, FALSE_LABEL);
8235 addptr(limit, 4);
8236 jcc(Assembler::notZero, COMPARE_VECTORS);
8237
8238 // Compare trailing char (final 2 bytes), if any
8239 bind(COMPARE_CHAR);
8240 testl(result, 0x2); // tail char
8241 jccb(Assembler::zero, COMPARE_BYTE);
8242 load_unsigned_short(chr, Address(ary1, 0));
8243 load_unsigned_short(limit, Address(ary2, 0));
8244 cmpl(chr, limit);
8245 jccb(Assembler::notEqual, FALSE_LABEL);
8246
8247 if (is_array_equ && is_char) {
8248 bind(COMPARE_BYTE);
8249 } else {
8250 lea(ary1, Address(ary1, 2));
8251 lea(ary2, Address(ary2, 2));
8252
8253 bind(COMPARE_BYTE);
8254 testl(result, 0x1); // tail byte
8255 jccb(Assembler::zero, TRUE_LABEL);
8256 load_unsigned_byte(chr, Address(ary1, 0));
8257 load_unsigned_byte(limit, Address(ary2, 0));
8258 cmpl(chr, limit);
8259 jccb(Assembler::notEqual, FALSE_LABEL);
8260 }
8261 bind(TRUE_LABEL);
8262 movl(result, 1); // return true
8263 jmpb(DONE);
8264
8265 bind(FALSE_LABEL);
8266 xorl(result, result); // return false
8267
8268 // That's it
8269 bind(DONE);
8270 if (UseAVX >= 2) {
8271 // clean upper bits of YMM registers
8272 vpxor(vec1, vec1);
8273 vpxor(vec2, vec2);
8274 }
8275 }
8276
8277 #endif
8278
8279 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8280 Register to, Register value, Register count,
8281 Register rtmp, XMMRegister xtmp) {
8282 ShortBranchVerifier sbv(this);
8283 assert_different_registers(to, value, count, rtmp);
8284 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8285 Label L_fill_2_bytes, L_fill_4_bytes;
8286
8287 int shift = -1;
8288 switch (t) {
8289 case T_BYTE:
8290 shift = 2;
8291 break;
8292 case T_SHORT:
8293 shift = 1;
8294 break;
8295 case T_INT:
8296 shift = 0;
8297 break;
8298 default: ShouldNotReachHere();
8299 }
8300
8301 if (t == T_BYTE) {
8302 andl(value, 0xff);
8303 movl(rtmp, value);
8304 shll(rtmp, 8);
8305 orl(value, rtmp);
8306 }
8307 if (t == T_SHORT) {
8308 andl(value, 0xffff);
8309 }
8310 if (t == T_BYTE || t == T_SHORT) {
8311 movl(rtmp, value);
8312 shll(rtmp, 16);
8313 orl(value, rtmp);
8314 }
8315
8316 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8317 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8318 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8319 // align source address at 4 bytes address boundary
8320 if (t == T_BYTE) {
8321 // One byte misalignment happens only for byte arrays
8322 testptr(to, 1);
8323 jccb(Assembler::zero, L_skip_align1);
8324 movb(Address(to, 0), value);
8325 increment(to);
8326 decrement(count);
8327 BIND(L_skip_align1);
8328 }
8329 // Two bytes misalignment happens only for byte and short (char) arrays
8330 testptr(to, 2);
8331 jccb(Assembler::zero, L_skip_align2);
8332 movw(Address(to, 0), value);
8333 addptr(to, 2);
8334 subl(count, 1<<(shift-1));
8335 BIND(L_skip_align2);
8336 }
8337 if (UseSSE < 2) {
8338 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8339 // Fill 32-byte chunks
8340 subl(count, 8 << shift);
8341 jcc(Assembler::less, L_check_fill_8_bytes);
8342 align(16);
8343
8344 BIND(L_fill_32_bytes_loop);
8345
8346 for (int i = 0; i < 32; i += 4) {
8347 movl(Address(to, i), value);
8348 }
8349
8350 addptr(to, 32);
8351 subl(count, 8 << shift);
8352 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8353 BIND(L_check_fill_8_bytes);
8354 addl(count, 8 << shift);
8355 jccb(Assembler::zero, L_exit);
8356 jmpb(L_fill_8_bytes);
8357
8358 //
8359 // length is too short, just fill qwords
8360 //
8361 BIND(L_fill_8_bytes_loop);
8362 movl(Address(to, 0), value);
8363 movl(Address(to, 4), value);
8364 addptr(to, 8);
8365 BIND(L_fill_8_bytes);
8366 subl(count, 1 << (shift + 1));
8367 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8368 // fall through to fill 4 bytes
8369 } else {
8370 Label L_fill_32_bytes;
8371 if (!UseUnalignedLoadStores) {
8372 // align to 8 bytes, we know we are 4 byte aligned to start
8373 testptr(to, 4);
8374 jccb(Assembler::zero, L_fill_32_bytes);
8375 movl(Address(to, 0), value);
8376 addptr(to, 4);
8377 subl(count, 1<<shift);
8378 }
8379 BIND(L_fill_32_bytes);
8380 {
8381 assert( UseSSE >= 2, "supported cpu only" );
8382 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8383 if (UseAVX > 2) {
8384 movl(rtmp, 0xffff);
8385 kmovwl(k1, rtmp);
8386 }
8387 movdl(xtmp, value);
8388 if (UseAVX > 2 && UseUnalignedLoadStores) {
8389 // Fill 64-byte chunks
8390 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8391 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8392
8393 subl(count, 16 << shift);
8394 jcc(Assembler::less, L_check_fill_32_bytes);
8395 align(16);
8396
8397 BIND(L_fill_64_bytes_loop);
8398 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8399 addptr(to, 64);
8400 subl(count, 16 << shift);
8401 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8402
8403 BIND(L_check_fill_32_bytes);
8404 addl(count, 8 << shift);
8405 jccb(Assembler::less, L_check_fill_8_bytes);
8406 vmovdqu(Address(to, 0), xtmp);
8407 addptr(to, 32);
8408 subl(count, 8 << shift);
8409
8410 BIND(L_check_fill_8_bytes);
8411 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8412 // Fill 64-byte chunks
8413 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8414 vpbroadcastd(xtmp, xtmp);
8415
8416 subl(count, 16 << shift);
8417 jcc(Assembler::less, L_check_fill_32_bytes);
8418 align(16);
8419
8420 BIND(L_fill_64_bytes_loop);
8421 vmovdqu(Address(to, 0), xtmp);
8422 vmovdqu(Address(to, 32), xtmp);
8423 addptr(to, 64);
8424 subl(count, 16 << shift);
8425 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8426
8427 BIND(L_check_fill_32_bytes);
8428 addl(count, 8 << shift);
8429 jccb(Assembler::less, L_check_fill_8_bytes);
8430 vmovdqu(Address(to, 0), xtmp);
8431 addptr(to, 32);
8432 subl(count, 8 << shift);
8433
8434 BIND(L_check_fill_8_bytes);
8435 // clean upper bits of YMM registers
8436 movdl(xtmp, value);
8437 pshufd(xtmp, xtmp, 0);
8438 } else {
8439 // Fill 32-byte chunks
8440 pshufd(xtmp, xtmp, 0);
8441
8442 subl(count, 8 << shift);
8443 jcc(Assembler::less, L_check_fill_8_bytes);
8444 align(16);
8445
8446 BIND(L_fill_32_bytes_loop);
8447
8448 if (UseUnalignedLoadStores) {
8449 movdqu(Address(to, 0), xtmp);
8450 movdqu(Address(to, 16), xtmp);
8451 } else {
8452 movq(Address(to, 0), xtmp);
8453 movq(Address(to, 8), xtmp);
8454 movq(Address(to, 16), xtmp);
8455 movq(Address(to, 24), xtmp);
8456 }
8457
8458 addptr(to, 32);
8459 subl(count, 8 << shift);
8460 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8461
8462 BIND(L_check_fill_8_bytes);
8463 }
8464 addl(count, 8 << shift);
8465 jccb(Assembler::zero, L_exit);
8466 jmpb(L_fill_8_bytes);
8467
8468 //
8469 // length is too short, just fill qwords
8470 //
8471 BIND(L_fill_8_bytes_loop);
8472 movq(Address(to, 0), xtmp);
8473 addptr(to, 8);
8474 BIND(L_fill_8_bytes);
8475 subl(count, 1 << (shift + 1));
8476 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8477 }
8478 }
8479 // fill trailing 4 bytes
8480 BIND(L_fill_4_bytes);
8481 testl(count, 1<<shift);
8482 jccb(Assembler::zero, L_fill_2_bytes);
8483 movl(Address(to, 0), value);
8484 if (t == T_BYTE || t == T_SHORT) {
8485 addptr(to, 4);
8486 BIND(L_fill_2_bytes);
8487 // fill trailing 2 bytes
8488 testl(count, 1<<(shift-1));
8489 jccb(Assembler::zero, L_fill_byte);
8490 movw(Address(to, 0), value);
8491 if (t == T_BYTE) {
8492 addptr(to, 2);
8493 BIND(L_fill_byte);
8494 // fill trailing byte
8495 testl(count, 1);
8496 jccb(Assembler::zero, L_exit);
8497 movb(Address(to, 0), value);
8498 } else {
8499 BIND(L_fill_byte);
8500 }
8501 } else {
8502 BIND(L_fill_2_bytes);
8503 }
8504 BIND(L_exit);
8505 }
8506
8507 // encode char[] to byte[] in ISO_8859_1
8508 //@HotSpotIntrinsicCandidate
8509 //private static int implEncodeISOArray(byte[] sa, int sp,
8510 //byte[] da, int dp, int len) {
8511 // int i = 0;
8512 // for (; i < len; i++) {
8513 // char c = StringUTF16.getChar(sa, sp++);
8514 // if (c > '\u00FF')
8515 // break;
8516 // da[dp++] = (byte)c;
8517 // }
8518 // return i;
8519 //}
8520 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8521 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8522 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8523 Register tmp5, Register result) {
8524
8525 // rsi: src
8526 // rdi: dst
8527 // rdx: len
8528 // rcx: tmp5
8529 // rax: result
8530 ShortBranchVerifier sbv(this);
8531 assert_different_registers(src, dst, len, tmp5, result);
8532 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8533
8534 // set result
8535 xorl(result, result);
8536 // check for zero length
8537 testl(len, len);
8538 jcc(Assembler::zero, L_done);
8539
8540 movl(result, len);
8541
8542 // Setup pointers
8543 lea(src, Address(src, len, Address::times_2)); // char[]
8544 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8545 negptr(len);
8546
8547 if (UseSSE42Intrinsics || UseAVX >= 2) {
8548 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8549 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8550
8551 if (UseAVX >= 2) {
8552 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8553 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8554 movdl(tmp1Reg, tmp5);
8555 vpbroadcastd(tmp1Reg, tmp1Reg);
8556 jmp(L_chars_32_check);
8557
8558 bind(L_copy_32_chars);
8559 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8560 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8561 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8562 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8563 jccb(Assembler::notZero, L_copy_32_chars_exit);
8564 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8565 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8566 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8567
8568 bind(L_chars_32_check);
8569 addptr(len, 32);
8570 jcc(Assembler::lessEqual, L_copy_32_chars);
8571
8572 bind(L_copy_32_chars_exit);
8573 subptr(len, 16);
8574 jccb(Assembler::greater, L_copy_16_chars_exit);
8575
8576 } else if (UseSSE42Intrinsics) {
8577 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8578 movdl(tmp1Reg, tmp5);
8579 pshufd(tmp1Reg, tmp1Reg, 0);
8580 jmpb(L_chars_16_check);
8581 }
8582
8583 bind(L_copy_16_chars);
8584 if (UseAVX >= 2) {
8585 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8586 vptest(tmp2Reg, tmp1Reg);
8587 jcc(Assembler::notZero, L_copy_16_chars_exit);
8588 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8589 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8590 } else {
8591 if (UseAVX > 0) {
8592 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8593 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8594 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8595 } else {
8596 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8597 por(tmp2Reg, tmp3Reg);
8598 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8599 por(tmp2Reg, tmp4Reg);
8600 }
8601 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8602 jccb(Assembler::notZero, L_copy_16_chars_exit);
8603 packuswb(tmp3Reg, tmp4Reg);
8604 }
8605 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8606
8607 bind(L_chars_16_check);
8608 addptr(len, 16);
8609 jcc(Assembler::lessEqual, L_copy_16_chars);
8610
8611 bind(L_copy_16_chars_exit);
8612 if (UseAVX >= 2) {
8613 // clean upper bits of YMM registers
8614 vpxor(tmp2Reg, tmp2Reg);
8615 vpxor(tmp3Reg, tmp3Reg);
8616 vpxor(tmp4Reg, tmp4Reg);
8617 movdl(tmp1Reg, tmp5);
8618 pshufd(tmp1Reg, tmp1Reg, 0);
8619 }
8620 subptr(len, 8);
8621 jccb(Assembler::greater, L_copy_8_chars_exit);
8622
8623 bind(L_copy_8_chars);
8624 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8625 ptest(tmp3Reg, tmp1Reg);
8626 jccb(Assembler::notZero, L_copy_8_chars_exit);
8627 packuswb(tmp3Reg, tmp1Reg);
8628 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8629 addptr(len, 8);
8630 jccb(Assembler::lessEqual, L_copy_8_chars);
8631
8632 bind(L_copy_8_chars_exit);
8633 subptr(len, 8);
8634 jccb(Assembler::zero, L_done);
8635 }
8636
8637 bind(L_copy_1_char);
8638 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8639 testl(tmp5, 0xff00); // check if Unicode char
8640 jccb(Assembler::notZero, L_copy_1_char_exit);
8641 movb(Address(dst, len, Address::times_1, 0), tmp5);
8642 addptr(len, 1);
8643 jccb(Assembler::less, L_copy_1_char);
8644
8645 bind(L_copy_1_char_exit);
8646 addptr(result, len); // len is negative count of not processed elements
8647
8648 bind(L_done);
8649 }
8650
8651 #ifdef _LP64
8652 /**
8653 * Helper for multiply_to_len().
8654 */
8655 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8656 addq(dest_lo, src1);
8657 adcq(dest_hi, 0);
8658 addq(dest_lo, src2);
8659 adcq(dest_hi, 0);
8660 }
8661
8662 /**
8663 * Multiply 64 bit by 64 bit first loop.
8664 */
8665 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8666 Register y, Register y_idx, Register z,
8667 Register carry, Register product,
8668 Register idx, Register kdx) {
8669 //
8670 // jlong carry, x[], y[], z[];
8671 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8672 // huge_128 product = y[idx] * x[xstart] + carry;
8673 // z[kdx] = (jlong)product;
8674 // carry = (jlong)(product >>> 64);
8675 // }
8676 // z[xstart] = carry;
8677 //
8678
8679 Label L_first_loop, L_first_loop_exit;
8680 Label L_one_x, L_one_y, L_multiply;
8681
8682 decrementl(xstart);
8683 jcc(Assembler::negative, L_one_x);
8684
8685 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8686 rorq(x_xstart, 32); // convert big-endian to little-endian
8687
8688 bind(L_first_loop);
8689 decrementl(idx);
8690 jcc(Assembler::negative, L_first_loop_exit);
8691 decrementl(idx);
8692 jcc(Assembler::negative, L_one_y);
8693 movq(y_idx, Address(y, idx, Address::times_4, 0));
8694 rorq(y_idx, 32); // convert big-endian to little-endian
8695 bind(L_multiply);
8696 movq(product, x_xstart);
8697 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8698 addq(product, carry);
8699 adcq(rdx, 0);
8700 subl(kdx, 2);
8701 movl(Address(z, kdx, Address::times_4, 4), product);
8702 shrq(product, 32);
8703 movl(Address(z, kdx, Address::times_4, 0), product);
8704 movq(carry, rdx);
8705 jmp(L_first_loop);
8706
8707 bind(L_one_y);
8708 movl(y_idx, Address(y, 0));
8709 jmp(L_multiply);
8710
8711 bind(L_one_x);
8712 movl(x_xstart, Address(x, 0));
8713 jmp(L_first_loop);
8714
8715 bind(L_first_loop_exit);
8716 }
8717
8718 /**
8719 * Multiply 64 bit by 64 bit and add 128 bit.
8720 */
8721 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8722 Register yz_idx, Register idx,
8723 Register carry, Register product, int offset) {
8724 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8725 // z[kdx] = (jlong)product;
8726
8727 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8728 rorq(yz_idx, 32); // convert big-endian to little-endian
8729 movq(product, x_xstart);
8730 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8731 movq(yz_idx, Address(z, idx, Address::times_4, offset));
8732 rorq(yz_idx, 32); // convert big-endian to little-endian
8733
8734 add2_with_carry(rdx, product, carry, yz_idx);
8735
8736 movl(Address(z, idx, Address::times_4, offset+4), product);
8737 shrq(product, 32);
8738 movl(Address(z, idx, Address::times_4, offset), product);
8739
8740 }
8741
8742 /**
8743 * Multiply 128 bit by 128 bit. Unrolled inner loop.
8744 */
8745 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
8746 Register yz_idx, Register idx, Register jdx,
8747 Register carry, Register product,
8748 Register carry2) {
8749 // jlong carry, x[], y[], z[];
8750 // int kdx = ystart+1;
8751 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8752 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
8753 // z[kdx+idx+1] = (jlong)product;
8754 // jlong carry2 = (jlong)(product >>> 64);
8755 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
8756 // z[kdx+idx] = (jlong)product;
8757 // carry = (jlong)(product >>> 64);
8758 // }
8759 // idx += 2;
8760 // if (idx > 0) {
8761 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
8762 // z[kdx+idx] = (jlong)product;
8763 // carry = (jlong)(product >>> 64);
8764 // }
8765 //
8766
8767 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8768
8769 movl(jdx, idx);
8770 andl(jdx, 0xFFFFFFFC);
8771 shrl(jdx, 2);
8772
8773 bind(L_third_loop);
8774 subl(jdx, 1);
8775 jcc(Assembler::negative, L_third_loop_exit);
8776 subl(idx, 4);
8777
8778 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
8779 movq(carry2, rdx);
8780
8781 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
8782 movq(carry, rdx);
8783 jmp(L_third_loop);
8784
8785 bind (L_third_loop_exit);
8786
8787 andl (idx, 0x3);
8788 jcc(Assembler::zero, L_post_third_loop_done);
8789
8790 Label L_check_1;
8791 subl(idx, 2);
8792 jcc(Assembler::negative, L_check_1);
8793
8794 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
8795 movq(carry, rdx);
8796
8797 bind (L_check_1);
8798 addl (idx, 0x2);
8799 andl (idx, 0x1);
8800 subl(idx, 1);
8801 jcc(Assembler::negative, L_post_third_loop_done);
8802
8803 movl(yz_idx, Address(y, idx, Address::times_4, 0));
8804 movq(product, x_xstart);
8805 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8806 movl(yz_idx, Address(z, idx, Address::times_4, 0));
8807
8808 add2_with_carry(rdx, product, yz_idx, carry);
8809
8810 movl(Address(z, idx, Address::times_4, 0), product);
8811 shrq(product, 32);
8812
8813 shlq(rdx, 32);
8814 orq(product, rdx);
8815 movq(carry, product);
8816
8817 bind(L_post_third_loop_done);
8818 }
8819
8820 /**
8821 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
8822 *
8823 */
8824 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
8825 Register carry, Register carry2,
8826 Register idx, Register jdx,
8827 Register yz_idx1, Register yz_idx2,
8828 Register tmp, Register tmp3, Register tmp4) {
8829 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
8830
8831 // jlong carry, x[], y[], z[];
8832 // int kdx = ystart+1;
8833 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
8834 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
8835 // jlong carry2 = (jlong)(tmp3 >>> 64);
8836 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
8837 // carry = (jlong)(tmp4 >>> 64);
8838 // z[kdx+idx+1] = (jlong)tmp3;
8839 // z[kdx+idx] = (jlong)tmp4;
8840 // }
8841 // idx += 2;
8842 // if (idx > 0) {
8843 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
8844 // z[kdx+idx] = (jlong)yz_idx1;
8845 // carry = (jlong)(yz_idx1 >>> 64);
8846 // }
8847 //
8848
8849 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
8850
8851 movl(jdx, idx);
8852 andl(jdx, 0xFFFFFFFC);
8853 shrl(jdx, 2);
8854
8855 bind(L_third_loop);
8856 subl(jdx, 1);
8857 jcc(Assembler::negative, L_third_loop_exit);
8858 subl(idx, 4);
8859
8860 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
8861 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
8862 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
8863 rorxq(yz_idx2, yz_idx2, 32);
8864
8865 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8866 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
8867
8868 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
8869 rorxq(yz_idx1, yz_idx1, 32);
8870 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8871 rorxq(yz_idx2, yz_idx2, 32);
8872
8873 if (VM_Version::supports_adx()) {
8874 adcxq(tmp3, carry);
8875 adoxq(tmp3, yz_idx1);
8876
8877 adcxq(tmp4, tmp);
8878 adoxq(tmp4, yz_idx2);
8879
8880 movl(carry, 0); // does not affect flags
8881 adcxq(carry2, carry);
8882 adoxq(carry2, carry);
8883 } else {
8884 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
8885 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
8886 }
8887 movq(carry, carry2);
8888
8889 movl(Address(z, idx, Address::times_4, 12), tmp3);
8890 shrq(tmp3, 32);
8891 movl(Address(z, idx, Address::times_4, 8), tmp3);
8892
8893 movl(Address(z, idx, Address::times_4, 4), tmp4);
8894 shrq(tmp4, 32);
8895 movl(Address(z, idx, Address::times_4, 0), tmp4);
8896
8897 jmp(L_third_loop);
8898
8899 bind (L_third_loop_exit);
8900
8901 andl (idx, 0x3);
8902 jcc(Assembler::zero, L_post_third_loop_done);
8903
8904 Label L_check_1;
8905 subl(idx, 2);
8906 jcc(Assembler::negative, L_check_1);
8907
8908 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
8909 rorxq(yz_idx1, yz_idx1, 32);
8910 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
8911 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
8912 rorxq(yz_idx2, yz_idx2, 32);
8913
8914 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
8915
8916 movl(Address(z, idx, Address::times_4, 4), tmp3);
8917 shrq(tmp3, 32);
8918 movl(Address(z, idx, Address::times_4, 0), tmp3);
8919 movq(carry, tmp4);
8920
8921 bind (L_check_1);
8922 addl (idx, 0x2);
8923 andl (idx, 0x1);
8924 subl(idx, 1);
8925 jcc(Assembler::negative, L_post_third_loop_done);
8926 movl(tmp4, Address(y, idx, Address::times_4, 0));
8927 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
8928 movl(tmp4, Address(z, idx, Address::times_4, 0));
8929
8930 add2_with_carry(carry2, tmp3, tmp4, carry);
8931
8932 movl(Address(z, idx, Address::times_4, 0), tmp3);
8933 shrq(tmp3, 32);
8934
8935 shlq(carry2, 32);
8936 orq(tmp3, carry2);
8937 movq(carry, tmp3);
8938
8939 bind(L_post_third_loop_done);
8940 }
8941
8942 /**
8943 * Code for BigInteger::multiplyToLen() instrinsic.
8944 *
8945 * rdi: x
8946 * rax: xlen
8947 * rsi: y
8948 * rcx: ylen
8949 * r8: z
8950 * r11: zlen
8951 * r12: tmp1
8952 * r13: tmp2
8953 * r14: tmp3
8954 * r15: tmp4
8955 * rbx: tmp5
8956 *
8957 */
8958 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
8959 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
8960 ShortBranchVerifier sbv(this);
8961 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
8962
8963 push(tmp1);
8964 push(tmp2);
8965 push(tmp3);
8966 push(tmp4);
8967 push(tmp5);
8968
8969 push(xlen);
8970 push(zlen);
8971
8972 const Register idx = tmp1;
8973 const Register kdx = tmp2;
8974 const Register xstart = tmp3;
8975
8976 const Register y_idx = tmp4;
8977 const Register carry = tmp5;
8978 const Register product = xlen;
8979 const Register x_xstart = zlen; // reuse register
8980
8981 // First Loop.
8982 //
8983 // final static long LONG_MASK = 0xffffffffL;
8984 // int xstart = xlen - 1;
8985 // int ystart = ylen - 1;
8986 // long carry = 0;
8987 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8988 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
8989 // z[kdx] = (int)product;
8990 // carry = product >>> 32;
8991 // }
8992 // z[xstart] = (int)carry;
8993 //
8994
8995 movl(idx, ylen); // idx = ylen;
8996 movl(kdx, zlen); // kdx = xlen+ylen;
8997 xorq(carry, carry); // carry = 0;
8998
8999 Label L_done;
9000
9001 movl(xstart, xlen);
9002 decrementl(xstart);
9003 jcc(Assembler::negative, L_done);
9004
9005 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9006
9007 Label L_second_loop;
9008 testl(kdx, kdx);
9009 jcc(Assembler::zero, L_second_loop);
9010
9011 Label L_carry;
9012 subl(kdx, 1);
9013 jcc(Assembler::zero, L_carry);
9014
9015 movl(Address(z, kdx, Address::times_4, 0), carry);
9016 shrq(carry, 32);
9017 subl(kdx, 1);
9018
9019 bind(L_carry);
9020 movl(Address(z, kdx, Address::times_4, 0), carry);
9021
9022 // Second and third (nested) loops.
9023 //
9024 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9025 // carry = 0;
9026 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9027 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9028 // (z[k] & LONG_MASK) + carry;
9029 // z[k] = (int)product;
9030 // carry = product >>> 32;
9031 // }
9032 // z[i] = (int)carry;
9033 // }
9034 //
9035 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9036
9037 const Register jdx = tmp1;
9038
9039 bind(L_second_loop);
9040 xorl(carry, carry); // carry = 0;
9041 movl(jdx, ylen); // j = ystart+1
9042
9043 subl(xstart, 1); // i = xstart-1;
9044 jcc(Assembler::negative, L_done);
9045
9046 push (z);
9047
9048 Label L_last_x;
9049 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9050 subl(xstart, 1); // i = xstart-1;
9051 jcc(Assembler::negative, L_last_x);
9052
9053 if (UseBMI2Instructions) {
9054 movq(rdx, Address(x, xstart, Address::times_4, 0));
9055 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9056 } else {
9057 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9058 rorq(x_xstart, 32); // convert big-endian to little-endian
9059 }
9060
9061 Label L_third_loop_prologue;
9062 bind(L_third_loop_prologue);
9063
9064 push (x);
9065 push (xstart);
9066 push (ylen);
9067
9068
9069 if (UseBMI2Instructions) {
9070 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9071 } else { // !UseBMI2Instructions
9072 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9073 }
9074
9075 pop(ylen);
9076 pop(xlen);
9077 pop(x);
9078 pop(z);
9079
9080 movl(tmp3, xlen);
9081 addl(tmp3, 1);
9082 movl(Address(z, tmp3, Address::times_4, 0), carry);
9083 subl(tmp3, 1);
9084 jccb(Assembler::negative, L_done);
9085
9086 shrq(carry, 32);
9087 movl(Address(z, tmp3, Address::times_4, 0), carry);
9088 jmp(L_second_loop);
9089
9090 // Next infrequent code is moved outside loops.
9091 bind(L_last_x);
9092 if (UseBMI2Instructions) {
9093 movl(rdx, Address(x, 0));
9094 } else {
9095 movl(x_xstart, Address(x, 0));
9096 }
9097 jmp(L_third_loop_prologue);
9098
9099 bind(L_done);
9100
9101 pop(zlen);
9102 pop(xlen);
9103
9104 pop(tmp5);
9105 pop(tmp4);
9106 pop(tmp3);
9107 pop(tmp2);
9108 pop(tmp1);
9109 }
9110
9111 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9112 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9113 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9114 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9115 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9116 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9117 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9118 Label SAME_TILL_END, DONE;
9119 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9120
9121 //scale is in rcx in both Win64 and Unix
9122 ShortBranchVerifier sbv(this);
9123
9124 shlq(length);
9125 xorq(result, result);
9126
9127 if ((UseAVX > 2) &&
9128 VM_Version::supports_avx512vlbw()) {
9129 set_vector_masking(); // opening of the stub context for programming mask registers
9130 cmpq(length, 64);
9131 jcc(Assembler::less, VECTOR32_TAIL);
9132 movq(tmp1, length);
9133 andq(tmp1, 0x3F); // tail count
9134 andq(length, ~(0x3F)); //vector count
9135
9136 bind(VECTOR64_LOOP);
9137 // AVX512 code to compare 64 byte vectors.
9138 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9139 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9140 kortestql(k7, k7);
9141 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9142 addq(result, 64);
9143 subq(length, 64);
9144 jccb(Assembler::notZero, VECTOR64_LOOP);
9145
9146 //bind(VECTOR64_TAIL);
9147 testq(tmp1, tmp1);
9148 jcc(Assembler::zero, SAME_TILL_END);
9149
9150 bind(VECTOR64_TAIL);
9151 // AVX512 code to compare upto 63 byte vectors.
9152 // Save k1
9153 kmovql(k3, k1);
9154 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9155 shlxq(tmp2, tmp2, tmp1);
9156 notq(tmp2);
9157 kmovql(k1, tmp2);
9158
9159 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9160 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9161
9162 ktestql(k7, k1);
9163 // Restore k1
9164 kmovql(k1, k3);
9165 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9166
9167 bind(VECTOR64_NOT_EQUAL);
9168 kmovql(tmp1, k7);
9169 notq(tmp1);
9170 tzcntq(tmp1, tmp1);
9171 addq(result, tmp1);
9172 shrq(result);
9173 jmp(DONE);
9174 bind(VECTOR32_TAIL);
9175 clear_vector_masking(); // closing of the stub context for programming mask registers
9176 }
9177
9178 cmpq(length, 8);
9179 jcc(Assembler::equal, VECTOR8_LOOP);
9180 jcc(Assembler::less, VECTOR4_TAIL);
9181
9182 if (UseAVX >= 2) {
9183
9184 cmpq(length, 16);
9185 jcc(Assembler::equal, VECTOR16_LOOP);
9186 jcc(Assembler::less, VECTOR8_LOOP);
9187
9188 cmpq(length, 32);
9189 jccb(Assembler::less, VECTOR16_TAIL);
9190
9191 subq(length, 32);
9192 bind(VECTOR32_LOOP);
9193 vmovdqu(rymm0, Address(obja, result));
9194 vmovdqu(rymm1, Address(objb, result));
9195 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9196 vptest(rymm2, rymm2);
9197 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9198 addq(result, 32);
9199 subq(length, 32);
9200 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
9201 addq(length, 32);
9202 jcc(Assembler::equal, SAME_TILL_END);
9203 //falling through if less than 32 bytes left //close the branch here.
9204
9205 bind(VECTOR16_TAIL);
9206 cmpq(length, 16);
9207 jccb(Assembler::less, VECTOR8_TAIL);
9208 bind(VECTOR16_LOOP);
9209 movdqu(rymm0, Address(obja, result));
9210 movdqu(rymm1, Address(objb, result));
9211 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9212 ptest(rymm2, rymm2);
9213 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9214 addq(result, 16);
9215 subq(length, 16);
9216 jcc(Assembler::equal, SAME_TILL_END);
9217 //falling through if less than 16 bytes left
9218 } else {//regular intrinsics
9219
9220 cmpq(length, 16);
9221 jccb(Assembler::less, VECTOR8_TAIL);
9222
9223 subq(length, 16);
9224 bind(VECTOR16_LOOP);
9225 movdqu(rymm0, Address(obja, result));
9226 movdqu(rymm1, Address(objb, result));
9227 pxor(rymm0, rymm1);
9228 ptest(rymm0, rymm0);
9229 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9230 addq(result, 16);
9231 subq(length, 16);
9232 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9233 addq(length, 16);
9234 jcc(Assembler::equal, SAME_TILL_END);
9235 //falling through if less than 16 bytes left
9236 }
9237
9238 bind(VECTOR8_TAIL);
9239 cmpq(length, 8);
9240 jccb(Assembler::less, VECTOR4_TAIL);
9241 bind(VECTOR8_LOOP);
9242 movq(tmp1, Address(obja, result));
9243 movq(tmp2, Address(objb, result));
9244 xorq(tmp1, tmp2);
9245 testq(tmp1, tmp1);
9246 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9247 addq(result, 8);
9248 subq(length, 8);
9249 jcc(Assembler::equal, SAME_TILL_END);
9250 //falling through if less than 8 bytes left
9251
9252 bind(VECTOR4_TAIL);
9253 cmpq(length, 4);
9254 jccb(Assembler::less, BYTES_TAIL);
9255 bind(VECTOR4_LOOP);
9256 movl(tmp1, Address(obja, result));
9257 xorl(tmp1, Address(objb, result));
9258 testl(tmp1, tmp1);
9259 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9260 addq(result, 4);
9261 subq(length, 4);
9262 jcc(Assembler::equal, SAME_TILL_END);
9263 //falling through if less than 4 bytes left
9264
9265 bind(BYTES_TAIL);
9266 bind(BYTES_LOOP);
9267 load_unsigned_byte(tmp1, Address(obja, result));
9268 load_unsigned_byte(tmp2, Address(objb, result));
9269 xorl(tmp1, tmp2);
9270 testl(tmp1, tmp1);
9271 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9272 decq(length);
9273 jcc(Assembler::zero, SAME_TILL_END);
9274 incq(result);
9275 load_unsigned_byte(tmp1, Address(obja, result));
9276 load_unsigned_byte(tmp2, Address(objb, result));
9277 xorl(tmp1, tmp2);
9278 testl(tmp1, tmp1);
9279 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9280 decq(length);
9281 jcc(Assembler::zero, SAME_TILL_END);
9282 incq(result);
9283 load_unsigned_byte(tmp1, Address(obja, result));
9284 load_unsigned_byte(tmp2, Address(objb, result));
9285 xorl(tmp1, tmp2);
9286 testl(tmp1, tmp1);
9287 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9288 jmp(SAME_TILL_END);
9289
9290 if (UseAVX >= 2) {
9291 bind(VECTOR32_NOT_EQUAL);
9292 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9293 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9294 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9295 vpmovmskb(tmp1, rymm0);
9296 bsfq(tmp1, tmp1);
9297 addq(result, tmp1);
9298 shrq(result);
9299 jmp(DONE);
9300 }
9301
9302 bind(VECTOR16_NOT_EQUAL);
9303 if (UseAVX >= 2) {
9304 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9305 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9306 pxor(rymm0, rymm2);
9307 } else {
9308 pcmpeqb(rymm2, rymm2);
9309 pxor(rymm0, rymm1);
9310 pcmpeqb(rymm0, rymm1);
9311 pxor(rymm0, rymm2);
9312 }
9313 pmovmskb(tmp1, rymm0);
9314 bsfq(tmp1, tmp1);
9315 addq(result, tmp1);
9316 shrq(result);
9317 jmpb(DONE);
9318
9319 bind(VECTOR8_NOT_EQUAL);
9320 bind(VECTOR4_NOT_EQUAL);
9321 bsfq(tmp1, tmp1);
9322 shrq(tmp1, 3);
9323 addq(result, tmp1);
9324 bind(BYTES_NOT_EQUAL);
9325 shrq(result);
9326 jmpb(DONE);
9327
9328 bind(SAME_TILL_END);
9329 mov64(result, -1);
9330
9331 bind(DONE);
9332 }
9333
9334 //Helper functions for square_to_len()
9335
9336 /**
9337 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9338 * Preserves x and z and modifies rest of the registers.
9339 */
9340 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9341 // Perform square and right shift by 1
9342 // Handle odd xlen case first, then for even xlen do the following
9343 // jlong carry = 0;
9344 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9345 // huge_128 product = x[j:j+1] * x[j:j+1];
9346 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9347 // z[i+2:i+3] = (jlong)(product >>> 1);
9348 // carry = (jlong)product;
9349 // }
9350
9351 xorq(tmp5, tmp5); // carry
9352 xorq(rdxReg, rdxReg);
9353 xorl(tmp1, tmp1); // index for x
9354 xorl(tmp4, tmp4); // index for z
9355
9356 Label L_first_loop, L_first_loop_exit;
9357
9358 testl(xlen, 1);
9359 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9360
9361 // Square and right shift by 1 the odd element using 32 bit multiply
9362 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9363 imulq(raxReg, raxReg);
9364 shrq(raxReg, 1);
9365 adcq(tmp5, 0);
9366 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9367 incrementl(tmp1);
9368 addl(tmp4, 2);
9369
9370 // Square and right shift by 1 the rest using 64 bit multiply
9371 bind(L_first_loop);
9372 cmpptr(tmp1, xlen);
9373 jccb(Assembler::equal, L_first_loop_exit);
9374
9375 // Square
9376 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9377 rorq(raxReg, 32); // convert big-endian to little-endian
9378 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9379
9380 // Right shift by 1 and save carry
9381 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9382 rcrq(rdxReg, 1);
9383 rcrq(raxReg, 1);
9384 adcq(tmp5, 0);
9385
9386 // Store result in z
9387 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9388 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9389
9390 // Update indices for x and z
9391 addl(tmp1, 2);
9392 addl(tmp4, 4);
9393 jmp(L_first_loop);
9394
9395 bind(L_first_loop_exit);
9396 }
9397
9398
9399 /**
9400 * Perform the following multiply add operation using BMI2 instructions
9401 * carry:sum = sum + op1*op2 + carry
9402 * op2 should be in rdx
9403 * op2 is preserved, all other registers are modified
9404 */
9405 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9406 // assert op2 is rdx
9407 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9408 addq(sum, carry);
9409 adcq(tmp2, 0);
9410 addq(sum, op1);
9411 adcq(tmp2, 0);
9412 movq(carry, tmp2);
9413 }
9414
9415 /**
9416 * Perform the following multiply add operation:
9417 * carry:sum = sum + op1*op2 + carry
9418 * Preserves op1, op2 and modifies rest of registers
9419 */
9420 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9421 // rdx:rax = op1 * op2
9422 movq(raxReg, op2);
9423 mulq(op1);
9424
9425 // rdx:rax = sum + carry + rdx:rax
9426 addq(sum, carry);
9427 adcq(rdxReg, 0);
9428 addq(sum, raxReg);
9429 adcq(rdxReg, 0);
9430
9431 // carry:sum = rdx:sum
9432 movq(carry, rdxReg);
9433 }
9434
9435 /**
9436 * Add 64 bit long carry into z[] with carry propogation.
9437 * Preserves z and carry register values and modifies rest of registers.
9438 *
9439 */
9440 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9441 Label L_fourth_loop, L_fourth_loop_exit;
9442
9443 movl(tmp1, 1);
9444 subl(zlen, 2);
9445 addq(Address(z, zlen, Address::times_4, 0), carry);
9446
9447 bind(L_fourth_loop);
9448 jccb(Assembler::carryClear, L_fourth_loop_exit);
9449 subl(zlen, 2);
9450 jccb(Assembler::negative, L_fourth_loop_exit);
9451 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9452 jmp(L_fourth_loop);
9453 bind(L_fourth_loop_exit);
9454 }
9455
9456 /**
9457 * Shift z[] left by 1 bit.
9458 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9459 *
9460 */
9461 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9462
9463 Label L_fifth_loop, L_fifth_loop_exit;
9464
9465 // Fifth loop
9466 // Perform primitiveLeftShift(z, zlen, 1)
9467
9468 const Register prev_carry = tmp1;
9469 const Register new_carry = tmp4;
9470 const Register value = tmp2;
9471 const Register zidx = tmp3;
9472
9473 // int zidx, carry;
9474 // long value;
9475 // carry = 0;
9476 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9477 // (carry:value) = (z[i] << 1) | carry ;
9478 // z[i] = value;
9479 // }
9480
9481 movl(zidx, zlen);
9482 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9483
9484 bind(L_fifth_loop);
9485 decl(zidx); // Use decl to preserve carry flag
9486 decl(zidx);
9487 jccb(Assembler::negative, L_fifth_loop_exit);
9488
9489 if (UseBMI2Instructions) {
9490 movq(value, Address(z, zidx, Address::times_4, 0));
9491 rclq(value, 1);
9492 rorxq(value, value, 32);
9493 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9494 }
9495 else {
9496 // clear new_carry
9497 xorl(new_carry, new_carry);
9498
9499 // Shift z[i] by 1, or in previous carry and save new carry
9500 movq(value, Address(z, zidx, Address::times_4, 0));
9501 shlq(value, 1);
9502 adcl(new_carry, 0);
9503
9504 orq(value, prev_carry);
9505 rorq(value, 0x20);
9506 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9507
9508 // Set previous carry = new carry
9509 movl(prev_carry, new_carry);
9510 }
9511 jmp(L_fifth_loop);
9512
9513 bind(L_fifth_loop_exit);
9514 }
9515
9516
9517 /**
9518 * Code for BigInteger::squareToLen() intrinsic
9519 *
9520 * rdi: x
9521 * rsi: len
9522 * r8: z
9523 * rcx: zlen
9524 * r12: tmp1
9525 * r13: tmp2
9526 * r14: tmp3
9527 * r15: tmp4
9528 * rbx: tmp5
9529 *
9530 */
9531 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9532
9533 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9534 push(tmp1);
9535 push(tmp2);
9536 push(tmp3);
9537 push(tmp4);
9538 push(tmp5);
9539
9540 // First loop
9541 // Store the squares, right shifted one bit (i.e., divided by 2).
9542 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9543
9544 // Add in off-diagonal sums.
9545 //
9546 // Second, third (nested) and fourth loops.
9547 // zlen +=2;
9548 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9549 // carry = 0;
9550 // long op2 = x[xidx:xidx+1];
9551 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9552 // k -= 2;
9553 // long op1 = x[j:j+1];
9554 // long sum = z[k:k+1];
9555 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9556 // z[k:k+1] = sum;
9557 // }
9558 // add_one_64(z, k, carry, tmp_regs);
9559 // }
9560
9561 const Register carry = tmp5;
9562 const Register sum = tmp3;
9563 const Register op1 = tmp4;
9564 Register op2 = tmp2;
9565
9566 push(zlen);
9567 push(len);
9568 addl(zlen,2);
9569 bind(L_second_loop);
9570 xorq(carry, carry);
9571 subl(zlen, 4);
9572 subl(len, 2);
9573 push(zlen);
9574 push(len);
9575 cmpl(len, 0);
9576 jccb(Assembler::lessEqual, L_second_loop_exit);
9577
9578 // Multiply an array by one 64 bit long.
9579 if (UseBMI2Instructions) {
9580 op2 = rdxReg;
9581 movq(op2, Address(x, len, Address::times_4, 0));
9582 rorxq(op2, op2, 32);
9583 }
9584 else {
9585 movq(op2, Address(x, len, Address::times_4, 0));
9586 rorq(op2, 32);
9587 }
9588
9589 bind(L_third_loop);
9590 decrementl(len);
9591 jccb(Assembler::negative, L_third_loop_exit);
9592 decrementl(len);
9593 jccb(Assembler::negative, L_last_x);
9594
9595 movq(op1, Address(x, len, Address::times_4, 0));
9596 rorq(op1, 32);
9597
9598 bind(L_multiply);
9599 subl(zlen, 2);
9600 movq(sum, Address(z, zlen, Address::times_4, 0));
9601
9602 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9603 if (UseBMI2Instructions) {
9604 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9605 }
9606 else {
9607 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9608 }
9609
9610 movq(Address(z, zlen, Address::times_4, 0), sum);
9611
9612 jmp(L_third_loop);
9613 bind(L_third_loop_exit);
9614
9615 // Fourth loop
9616 // Add 64 bit long carry into z with carry propogation.
9617 // Uses offsetted zlen.
9618 add_one_64(z, zlen, carry, tmp1);
9619
9620 pop(len);
9621 pop(zlen);
9622 jmp(L_second_loop);
9623
9624 // Next infrequent code is moved outside loops.
9625 bind(L_last_x);
9626 movl(op1, Address(x, 0));
9627 jmp(L_multiply);
9628
9629 bind(L_second_loop_exit);
9630 pop(len);
9631 pop(zlen);
9632 pop(len);
9633 pop(zlen);
9634
9635 // Fifth loop
9636 // Shift z left 1 bit.
9637 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9638
9639 // z[zlen-1] |= x[len-1] & 1;
9640 movl(tmp3, Address(x, len, Address::times_4, -4));
9641 andl(tmp3, 1);
9642 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9643
9644 pop(tmp5);
9645 pop(tmp4);
9646 pop(tmp3);
9647 pop(tmp2);
9648 pop(tmp1);
9649 }
9650
9651 /**
9652 * Helper function for mul_add()
9653 * Multiply the in[] by int k and add to out[] starting at offset offs using
9654 * 128 bit by 32 bit multiply and return the carry in tmp5.
9655 * Only quad int aligned length of in[] is operated on in this function.
9656 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9657 * This function preserves out, in and k registers.
9658 * len and offset point to the appropriate index in "in" & "out" correspondingly
9659 * tmp5 has the carry.
9660 * other registers are temporary and are modified.
9661 *
9662 */
9663 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9664 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9665 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9666
9667 Label L_first_loop, L_first_loop_exit;
9668
9669 movl(tmp1, len);
9670 shrl(tmp1, 2);
9671
9672 bind(L_first_loop);
9673 subl(tmp1, 1);
9674 jccb(Assembler::negative, L_first_loop_exit);
9675
9676 subl(len, 4);
9677 subl(offset, 4);
9678
9679 Register op2 = tmp2;
9680 const Register sum = tmp3;
9681 const Register op1 = tmp4;
9682 const Register carry = tmp5;
9683
9684 if (UseBMI2Instructions) {
9685 op2 = rdxReg;
9686 }
9687
9688 movq(op1, Address(in, len, Address::times_4, 8));
9689 rorq(op1, 32);
9690 movq(sum, Address(out, offset, Address::times_4, 8));
9691 rorq(sum, 32);
9692 if (UseBMI2Instructions) {
9693 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9694 }
9695 else {
9696 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9697 }
9698 // Store back in big endian from little endian
9699 rorq(sum, 0x20);
9700 movq(Address(out, offset, Address::times_4, 8), sum);
9701
9702 movq(op1, Address(in, len, Address::times_4, 0));
9703 rorq(op1, 32);
9704 movq(sum, Address(out, offset, Address::times_4, 0));
9705 rorq(sum, 32);
9706 if (UseBMI2Instructions) {
9707 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9708 }
9709 else {
9710 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9711 }
9712 // Store back in big endian from little endian
9713 rorq(sum, 0x20);
9714 movq(Address(out, offset, Address::times_4, 0), sum);
9715
9716 jmp(L_first_loop);
9717 bind(L_first_loop_exit);
9718 }
9719
9720 /**
9721 * Code for BigInteger::mulAdd() intrinsic
9722 *
9723 * rdi: out
9724 * rsi: in
9725 * r11: offs (out.length - offset)
9726 * rcx: len
9727 * r8: k
9728 * r12: tmp1
9729 * r13: tmp2
9730 * r14: tmp3
9731 * r15: tmp4
9732 * rbx: tmp5
9733 * Multiply the in[] by word k and add to out[], return the carry in rax
9734 */
9735 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9736 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9737 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9738
9739 Label L_carry, L_last_in, L_done;
9740
9741 // carry = 0;
9742 // for (int j=len-1; j >= 0; j--) {
9743 // long product = (in[j] & LONG_MASK) * kLong +
9744 // (out[offs] & LONG_MASK) + carry;
9745 // out[offs--] = (int)product;
9746 // carry = product >>> 32;
9747 // }
9748 //
9749 push(tmp1);
9750 push(tmp2);
9751 push(tmp3);
9752 push(tmp4);
9753 push(tmp5);
9754
9755 Register op2 = tmp2;
9756 const Register sum = tmp3;
9757 const Register op1 = tmp4;
9758 const Register carry = tmp5;
9759
9760 if (UseBMI2Instructions) {
9761 op2 = rdxReg;
9762 movl(op2, k);
9763 }
9764 else {
9765 movl(op2, k);
9766 }
9767
9768 xorq(carry, carry);
9769
9770 //First loop
9771
9772 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
9773 //The carry is in tmp5
9774 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
9775
9776 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
9777 decrementl(len);
9778 jccb(Assembler::negative, L_carry);
9779 decrementl(len);
9780 jccb(Assembler::negative, L_last_in);
9781
9782 movq(op1, Address(in, len, Address::times_4, 0));
9783 rorq(op1, 32);
9784
9785 subl(offs, 2);
9786 movq(sum, Address(out, offs, Address::times_4, 0));
9787 rorq(sum, 32);
9788
9789 if (UseBMI2Instructions) {
9790 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9791 }
9792 else {
9793 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9794 }
9795
9796 // Store back in big endian from little endian
9797 rorq(sum, 0x20);
9798 movq(Address(out, offs, Address::times_4, 0), sum);
9799
9800 testl(len, len);
9801 jccb(Assembler::zero, L_carry);
9802
9803 //Multiply the last in[] entry, if any
9804 bind(L_last_in);
9805 movl(op1, Address(in, 0));
9806 movl(sum, Address(out, offs, Address::times_4, -4));
9807
9808 movl(raxReg, k);
9809 mull(op1); //tmp4 * eax -> edx:eax
9810 addl(sum, carry);
9811 adcl(rdxReg, 0);
9812 addl(sum, raxReg);
9813 adcl(rdxReg, 0);
9814 movl(carry, rdxReg);
9815
9816 movl(Address(out, offs, Address::times_4, -4), sum);
9817
9818 bind(L_carry);
9819 //return tmp5/carry as carry in rax
9820 movl(rax, carry);
9821
9822 bind(L_done);
9823 pop(tmp5);
9824 pop(tmp4);
9825 pop(tmp3);
9826 pop(tmp2);
9827 pop(tmp1);
9828 }
9829 #endif
9830
9831 /**
9832 * Emits code to update CRC-32 with a byte value according to constants in table
9833 *
9834 * @param [in,out]crc Register containing the crc.
9835 * @param [in]val Register containing the byte to fold into the CRC.
9836 * @param [in]table Register containing the table of crc constants.
9837 *
9838 * uint32_t crc;
9839 * val = crc_table[(val ^ crc) & 0xFF];
9840 * crc = val ^ (crc >> 8);
9841 *
9842 */
9843 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
9844 xorl(val, crc);
9845 andl(val, 0xFF);
9846 shrl(crc, 8); // unsigned shift
9847 xorl(crc, Address(table, val, Address::times_4, 0));
9848 }
9849
9850 /**
9851 * Fold four 128-bit data chunks
9852 */
9853 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9854 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
9855 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
9856 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
9857 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
9858 }
9859
9860 /**
9861 * Fold 128-bit data chunk
9862 */
9863 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
9864 if (UseAVX > 0) {
9865 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
9866 vpclmulldq(xcrc, xK, xcrc); // [63:0]
9867 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
9868 pxor(xcrc, xtmp);
9869 } else {
9870 movdqa(xtmp, xcrc);
9871 pclmulhdq(xtmp, xK); // [123:64]
9872 pclmulldq(xcrc, xK); // [63:0]
9873 pxor(xcrc, xtmp);
9874 movdqu(xtmp, Address(buf, offset));
9875 pxor(xcrc, xtmp);
9876 }
9877 }
9878
9879 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
9880 if (UseAVX > 0) {
9881 vpclmulhdq(xtmp, xK, xcrc);
9882 vpclmulldq(xcrc, xK, xcrc);
9883 pxor(xcrc, xbuf);
9884 pxor(xcrc, xtmp);
9885 } else {
9886 movdqa(xtmp, xcrc);
9887 pclmulhdq(xtmp, xK);
9888 pclmulldq(xcrc, xK);
9889 pxor(xcrc, xbuf);
9890 pxor(xcrc, xtmp);
9891 }
9892 }
9893
9894 /**
9895 * 8-bit folds to compute 32-bit CRC
9896 *
9897 * uint64_t xcrc;
9898 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
9899 */
9900 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
9901 movdl(tmp, xcrc);
9902 andl(tmp, 0xFF);
9903 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
9904 psrldq(xcrc, 1); // unsigned shift one byte
9905 pxor(xcrc, xtmp);
9906 }
9907
9908 /**
9909 * uint32_t crc;
9910 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
9911 */
9912 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
9913 movl(tmp, crc);
9914 andl(tmp, 0xFF);
9915 shrl(crc, 8);
9916 xorl(crc, Address(table, tmp, Address::times_4, 0));
9917 }
9918
9919 /**
9920 * @param crc register containing existing CRC (32-bit)
9921 * @param buf register pointing to input byte buffer (byte*)
9922 * @param len register containing number of bytes
9923 * @param table register that will contain address of CRC table
9924 * @param tmp scratch register
9925 */
9926 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
9927 assert_different_registers(crc, buf, len, table, tmp, rax);
9928
9929 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
9930 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
9931
9932 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
9933 // context for the registers used, where all instructions below are using 128-bit mode
9934 // On EVEX without VL and BW, these instructions will all be AVX.
9935 if (VM_Version::supports_avx512vlbw()) {
9936 movl(tmp, 0xffff);
9937 kmovwl(k1, tmp);
9938 }
9939
9940 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
9941 notl(crc); // ~crc
9942 cmpl(len, 16);
9943 jcc(Assembler::less, L_tail);
9944
9945 // Align buffer to 16 bytes
9946 movl(tmp, buf);
9947 andl(tmp, 0xF);
9948 jccb(Assembler::zero, L_aligned);
9949 subl(tmp, 16);
9950 addl(len, tmp);
9951
9952 align(4);
9953 BIND(L_align_loop);
9954 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9955 update_byte_crc32(crc, rax, table);
9956 increment(buf);
9957 incrementl(tmp);
9958 jccb(Assembler::less, L_align_loop);
9959
9960 BIND(L_aligned);
9961 movl(tmp, len); // save
9962 shrl(len, 4);
9963 jcc(Assembler::zero, L_tail_restore);
9964
9965 // Fold total 512 bits of polynomial on each iteration
9966 if (VM_Version::supports_vpclmulqdq()) {
9967 Label Parallel_loop, L_No_Parallel;
9968
9969 cmpl(len, 8);
9970 jccb(Assembler::less, L_No_Parallel);
9971
9972 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
9973 evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
9974 movdl(xmm5, crc);
9975 evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
9976 addptr(buf, 64);
9977 subl(len, 7);
9978 evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
9979
9980 BIND(Parallel_loop);
9981 fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
9982 addptr(buf, 64);
9983 subl(len, 4);
9984 jcc(Assembler::greater, Parallel_loop);
9985
9986 vextracti64x2(xmm2, xmm1, 0x01);
9987 vextracti64x2(xmm3, xmm1, 0x02);
9988 vextracti64x2(xmm4, xmm1, 0x03);
9989 jmp(L_fold_512b);
9990
9991 BIND(L_No_Parallel);
9992 }
9993 // Fold crc into first bytes of vector
9994 movdqa(xmm1, Address(buf, 0));
9995 movdl(rax, xmm1);
9996 xorl(crc, rax);
9997 if (VM_Version::supports_sse4_1()) {
9998 pinsrd(xmm1, crc, 0);
9999 } else {
10000 pinsrw(xmm1, crc, 0);
10001 shrl(crc, 16);
10002 pinsrw(xmm1, crc, 1);
10003 }
10004 addptr(buf, 16);
10005 subl(len, 4); // len > 0
10006 jcc(Assembler::less, L_fold_tail);
10007
10008 movdqa(xmm2, Address(buf, 0));
10009 movdqa(xmm3, Address(buf, 16));
10010 movdqa(xmm4, Address(buf, 32));
10011 addptr(buf, 48);
10012 subl(len, 3);
10013 jcc(Assembler::lessEqual, L_fold_512b);
10014
10015 // Fold total 512 bits of polynomial on each iteration,
10016 // 128 bits per each of 4 parallel streams.
10017 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10018
10019 align(32);
10020 BIND(L_fold_512b_loop);
10021 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10022 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10023 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10024 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10025 addptr(buf, 64);
10026 subl(len, 4);
10027 jcc(Assembler::greater, L_fold_512b_loop);
10028
10029 // Fold 512 bits to 128 bits.
10030 BIND(L_fold_512b);
10031 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10032 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10033 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10034 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10035
10036 // Fold the rest of 128 bits data chunks
10037 BIND(L_fold_tail);
10038 addl(len, 3);
10039 jccb(Assembler::lessEqual, L_fold_128b);
10040 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10041
10042 BIND(L_fold_tail_loop);
10043 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10044 addptr(buf, 16);
10045 decrementl(len);
10046 jccb(Assembler::greater, L_fold_tail_loop);
10047
10048 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10049 BIND(L_fold_128b);
10050 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10051 if (UseAVX > 0) {
10052 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10053 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10054 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10055 } else {
10056 movdqa(xmm2, xmm0);
10057 pclmulqdq(xmm2, xmm1, 0x1);
10058 movdqa(xmm3, xmm0);
10059 pand(xmm3, xmm2);
10060 pclmulqdq(xmm0, xmm3, 0x1);
10061 }
10062 psrldq(xmm1, 8);
10063 psrldq(xmm2, 4);
10064 pxor(xmm0, xmm1);
10065 pxor(xmm0, xmm2);
10066
10067 // 8 8-bit folds to compute 32-bit CRC.
10068 for (int j = 0; j < 4; j++) {
10069 fold_8bit_crc32(xmm0, table, xmm1, rax);
10070 }
10071 movdl(crc, xmm0); // mov 32 bits to general register
10072 for (int j = 0; j < 4; j++) {
10073 fold_8bit_crc32(crc, table, rax);
10074 }
10075
10076 BIND(L_tail_restore);
10077 movl(len, tmp); // restore
10078 BIND(L_tail);
10079 andl(len, 0xf);
10080 jccb(Assembler::zero, L_exit);
10081
10082 // Fold the rest of bytes
10083 align(4);
10084 BIND(L_tail_loop);
10085 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10086 update_byte_crc32(crc, rax, table);
10087 increment(buf);
10088 decrementl(len);
10089 jccb(Assembler::greater, L_tail_loop);
10090
10091 BIND(L_exit);
10092 notl(crc); // ~c
10093 }
10094
10095 #ifdef _LP64
10096 // S. Gueron / Information Processing Letters 112 (2012) 184
10097 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10098 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10099 // Output: the 64-bit carry-less product of B * CONST
10100 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10101 Register tmp1, Register tmp2, Register tmp3) {
10102 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10103 if (n > 0) {
10104 addq(tmp3, n * 256 * 8);
10105 }
10106 // Q1 = TABLEExt[n][B & 0xFF];
10107 movl(tmp1, in);
10108 andl(tmp1, 0x000000FF);
10109 shll(tmp1, 3);
10110 addq(tmp1, tmp3);
10111 movq(tmp1, Address(tmp1, 0));
10112
10113 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10114 movl(tmp2, in);
10115 shrl(tmp2, 8);
10116 andl(tmp2, 0x000000FF);
10117 shll(tmp2, 3);
10118 addq(tmp2, tmp3);
10119 movq(tmp2, Address(tmp2, 0));
10120
10121 shlq(tmp2, 8);
10122 xorq(tmp1, tmp2);
10123
10124 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10125 movl(tmp2, in);
10126 shrl(tmp2, 16);
10127 andl(tmp2, 0x000000FF);
10128 shll(tmp2, 3);
10129 addq(tmp2, tmp3);
10130 movq(tmp2, Address(tmp2, 0));
10131
10132 shlq(tmp2, 16);
10133 xorq(tmp1, tmp2);
10134
10135 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10136 shrl(in, 24);
10137 andl(in, 0x000000FF);
10138 shll(in, 3);
10139 addq(in, tmp3);
10140 movq(in, Address(in, 0));
10141
10142 shlq(in, 24);
10143 xorq(in, tmp1);
10144 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10145 }
10146
10147 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10148 Register in_out,
10149 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10150 XMMRegister w_xtmp2,
10151 Register tmp1,
10152 Register n_tmp2, Register n_tmp3) {
10153 if (is_pclmulqdq_supported) {
10154 movdl(w_xtmp1, in_out); // modified blindly
10155
10156 movl(tmp1, const_or_pre_comp_const_index);
10157 movdl(w_xtmp2, tmp1);
10158 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10159
10160 movdq(in_out, w_xtmp1);
10161 } else {
10162 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10163 }
10164 }
10165
10166 // Recombination Alternative 2: No bit-reflections
10167 // T1 = (CRC_A * U1) << 1
10168 // T2 = (CRC_B * U2) << 1
10169 // C1 = T1 >> 32
10170 // C2 = T2 >> 32
10171 // T1 = T1 & 0xFFFFFFFF
10172 // T2 = T2 & 0xFFFFFFFF
10173 // T1 = CRC32(0, T1)
10174 // T2 = CRC32(0, T2)
10175 // C1 = C1 ^ T1
10176 // C2 = C2 ^ T2
10177 // CRC = C1 ^ C2 ^ CRC_C
10178 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10179 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10180 Register tmp1, Register tmp2,
10181 Register n_tmp3) {
10182 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10183 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10184 shlq(in_out, 1);
10185 movl(tmp1, in_out);
10186 shrq(in_out, 32);
10187 xorl(tmp2, tmp2);
10188 crc32(tmp2, tmp1, 4);
10189 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10190 shlq(in1, 1);
10191 movl(tmp1, in1);
10192 shrq(in1, 32);
10193 xorl(tmp2, tmp2);
10194 crc32(tmp2, tmp1, 4);
10195 xorl(in1, tmp2);
10196 xorl(in_out, in1);
10197 xorl(in_out, in2);
10198 }
10199
10200 // Set N to predefined value
10201 // Subtract from a lenght of a buffer
10202 // execute in a loop:
10203 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10204 // for i = 1 to N do
10205 // CRC_A = CRC32(CRC_A, A[i])
10206 // CRC_B = CRC32(CRC_B, B[i])
10207 // CRC_C = CRC32(CRC_C, C[i])
10208 // end for
10209 // Recombine
10210 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10211 Register in_out1, Register in_out2, Register in_out3,
10212 Register tmp1, Register tmp2, Register tmp3,
10213 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10214 Register tmp4, Register tmp5,
10215 Register n_tmp6) {
10216 Label L_processPartitions;
10217 Label L_processPartition;
10218 Label L_exit;
10219
10220 bind(L_processPartitions);
10221 cmpl(in_out1, 3 * size);
10222 jcc(Assembler::less, L_exit);
10223 xorl(tmp1, tmp1);
10224 xorl(tmp2, tmp2);
10225 movq(tmp3, in_out2);
10226 addq(tmp3, size);
10227
10228 bind(L_processPartition);
10229 crc32(in_out3, Address(in_out2, 0), 8);
10230 crc32(tmp1, Address(in_out2, size), 8);
10231 crc32(tmp2, Address(in_out2, size * 2), 8);
10232 addq(in_out2, 8);
10233 cmpq(in_out2, tmp3);
10234 jcc(Assembler::less, L_processPartition);
10235 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10236 w_xtmp1, w_xtmp2, w_xtmp3,
10237 tmp4, tmp5,
10238 n_tmp6);
10239 addq(in_out2, 2 * size);
10240 subl(in_out1, 3 * size);
10241 jmp(L_processPartitions);
10242
10243 bind(L_exit);
10244 }
10245 #else
10246 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10247 Register tmp1, Register tmp2, Register tmp3,
10248 XMMRegister xtmp1, XMMRegister xtmp2) {
10249 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10250 if (n > 0) {
10251 addl(tmp3, n * 256 * 8);
10252 }
10253 // Q1 = TABLEExt[n][B & 0xFF];
10254 movl(tmp1, in_out);
10255 andl(tmp1, 0x000000FF);
10256 shll(tmp1, 3);
10257 addl(tmp1, tmp3);
10258 movq(xtmp1, Address(tmp1, 0));
10259
10260 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10261 movl(tmp2, in_out);
10262 shrl(tmp2, 8);
10263 andl(tmp2, 0x000000FF);
10264 shll(tmp2, 3);
10265 addl(tmp2, tmp3);
10266 movq(xtmp2, Address(tmp2, 0));
10267
10268 psllq(xtmp2, 8);
10269 pxor(xtmp1, xtmp2);
10270
10271 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10272 movl(tmp2, in_out);
10273 shrl(tmp2, 16);
10274 andl(tmp2, 0x000000FF);
10275 shll(tmp2, 3);
10276 addl(tmp2, tmp3);
10277 movq(xtmp2, Address(tmp2, 0));
10278
10279 psllq(xtmp2, 16);
10280 pxor(xtmp1, xtmp2);
10281
10282 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10283 shrl(in_out, 24);
10284 andl(in_out, 0x000000FF);
10285 shll(in_out, 3);
10286 addl(in_out, tmp3);
10287 movq(xtmp2, Address(in_out, 0));
10288
10289 psllq(xtmp2, 24);
10290 pxor(xtmp1, xtmp2); // Result in CXMM
10291 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10292 }
10293
10294 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10295 Register in_out,
10296 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10297 XMMRegister w_xtmp2,
10298 Register tmp1,
10299 Register n_tmp2, Register n_tmp3) {
10300 if (is_pclmulqdq_supported) {
10301 movdl(w_xtmp1, in_out);
10302
10303 movl(tmp1, const_or_pre_comp_const_index);
10304 movdl(w_xtmp2, tmp1);
10305 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10306 // Keep result in XMM since GPR is 32 bit in length
10307 } else {
10308 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10309 }
10310 }
10311
10312 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10313 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10314 Register tmp1, Register tmp2,
10315 Register n_tmp3) {
10316 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10317 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10318
10319 psllq(w_xtmp1, 1);
10320 movdl(tmp1, w_xtmp1);
10321 psrlq(w_xtmp1, 32);
10322 movdl(in_out, w_xtmp1);
10323
10324 xorl(tmp2, tmp2);
10325 crc32(tmp2, tmp1, 4);
10326 xorl(in_out, tmp2);
10327
10328 psllq(w_xtmp2, 1);
10329 movdl(tmp1, w_xtmp2);
10330 psrlq(w_xtmp2, 32);
10331 movdl(in1, w_xtmp2);
10332
10333 xorl(tmp2, tmp2);
10334 crc32(tmp2, tmp1, 4);
10335 xorl(in1, tmp2);
10336 xorl(in_out, in1);
10337 xorl(in_out, in2);
10338 }
10339
10340 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10341 Register in_out1, Register in_out2, Register in_out3,
10342 Register tmp1, Register tmp2, Register tmp3,
10343 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10344 Register tmp4, Register tmp5,
10345 Register n_tmp6) {
10346 Label L_processPartitions;
10347 Label L_processPartition;
10348 Label L_exit;
10349
10350 bind(L_processPartitions);
10351 cmpl(in_out1, 3 * size);
10352 jcc(Assembler::less, L_exit);
10353 xorl(tmp1, tmp1);
10354 xorl(tmp2, tmp2);
10355 movl(tmp3, in_out2);
10356 addl(tmp3, size);
10357
10358 bind(L_processPartition);
10359 crc32(in_out3, Address(in_out2, 0), 4);
10360 crc32(tmp1, Address(in_out2, size), 4);
10361 crc32(tmp2, Address(in_out2, size*2), 4);
10362 crc32(in_out3, Address(in_out2, 0+4), 4);
10363 crc32(tmp1, Address(in_out2, size+4), 4);
10364 crc32(tmp2, Address(in_out2, size*2+4), 4);
10365 addl(in_out2, 8);
10366 cmpl(in_out2, tmp3);
10367 jcc(Assembler::less, L_processPartition);
10368
10369 push(tmp3);
10370 push(in_out1);
10371 push(in_out2);
10372 tmp4 = tmp3;
10373 tmp5 = in_out1;
10374 n_tmp6 = in_out2;
10375
10376 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10377 w_xtmp1, w_xtmp2, w_xtmp3,
10378 tmp4, tmp5,
10379 n_tmp6);
10380
10381 pop(in_out2);
10382 pop(in_out1);
10383 pop(tmp3);
10384
10385 addl(in_out2, 2 * size);
10386 subl(in_out1, 3 * size);
10387 jmp(L_processPartitions);
10388
10389 bind(L_exit);
10390 }
10391 #endif //LP64
10392
10393 #ifdef _LP64
10394 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10395 // Input: A buffer I of L bytes.
10396 // Output: the CRC32C value of the buffer.
10397 // Notations:
10398 // Write L = 24N + r, with N = floor (L/24).
10399 // r = L mod 24 (0 <= r < 24).
10400 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10401 // N quadwords, and R consists of r bytes.
10402 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10403 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10404 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10405 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10406 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10407 Register tmp1, Register tmp2, Register tmp3,
10408 Register tmp4, Register tmp5, Register tmp6,
10409 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10410 bool is_pclmulqdq_supported) {
10411 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10412 Label L_wordByWord;
10413 Label L_byteByByteProlog;
10414 Label L_byteByByte;
10415 Label L_exit;
10416
10417 if (is_pclmulqdq_supported ) {
10418 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10419 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10420
10421 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10422 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10423
10424 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10425 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10426 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10427 } else {
10428 const_or_pre_comp_const_index[0] = 1;
10429 const_or_pre_comp_const_index[1] = 0;
10430
10431 const_or_pre_comp_const_index[2] = 3;
10432 const_or_pre_comp_const_index[3] = 2;
10433
10434 const_or_pre_comp_const_index[4] = 5;
10435 const_or_pre_comp_const_index[5] = 4;
10436 }
10437 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10438 in2, in1, in_out,
10439 tmp1, tmp2, tmp3,
10440 w_xtmp1, w_xtmp2, w_xtmp3,
10441 tmp4, tmp5,
10442 tmp6);
10443 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10444 in2, in1, in_out,
10445 tmp1, tmp2, tmp3,
10446 w_xtmp1, w_xtmp2, w_xtmp3,
10447 tmp4, tmp5,
10448 tmp6);
10449 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10450 in2, in1, in_out,
10451 tmp1, tmp2, tmp3,
10452 w_xtmp1, w_xtmp2, w_xtmp3,
10453 tmp4, tmp5,
10454 tmp6);
10455 movl(tmp1, in2);
10456 andl(tmp1, 0x00000007);
10457 negl(tmp1);
10458 addl(tmp1, in2);
10459 addq(tmp1, in1);
10460
10461 BIND(L_wordByWord);
10462 cmpq(in1, tmp1);
10463 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10464 crc32(in_out, Address(in1, 0), 4);
10465 addq(in1, 4);
10466 jmp(L_wordByWord);
10467
10468 BIND(L_byteByByteProlog);
10469 andl(in2, 0x00000007);
10470 movl(tmp2, 1);
10471
10472 BIND(L_byteByByte);
10473 cmpl(tmp2, in2);
10474 jccb(Assembler::greater, L_exit);
10475 crc32(in_out, Address(in1, 0), 1);
10476 incq(in1);
10477 incl(tmp2);
10478 jmp(L_byteByByte);
10479
10480 BIND(L_exit);
10481 }
10482 #else
10483 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10484 Register tmp1, Register tmp2, Register tmp3,
10485 Register tmp4, Register tmp5, Register tmp6,
10486 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10487 bool is_pclmulqdq_supported) {
10488 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10489 Label L_wordByWord;
10490 Label L_byteByByteProlog;
10491 Label L_byteByByte;
10492 Label L_exit;
10493
10494 if (is_pclmulqdq_supported) {
10495 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10496 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10497
10498 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10499 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10500
10501 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10502 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10503 } else {
10504 const_or_pre_comp_const_index[0] = 1;
10505 const_or_pre_comp_const_index[1] = 0;
10506
10507 const_or_pre_comp_const_index[2] = 3;
10508 const_or_pre_comp_const_index[3] = 2;
10509
10510 const_or_pre_comp_const_index[4] = 5;
10511 const_or_pre_comp_const_index[5] = 4;
10512 }
10513 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10514 in2, in1, in_out,
10515 tmp1, tmp2, tmp3,
10516 w_xtmp1, w_xtmp2, w_xtmp3,
10517 tmp4, tmp5,
10518 tmp6);
10519 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10520 in2, in1, in_out,
10521 tmp1, tmp2, tmp3,
10522 w_xtmp1, w_xtmp2, w_xtmp3,
10523 tmp4, tmp5,
10524 tmp6);
10525 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10526 in2, in1, in_out,
10527 tmp1, tmp2, tmp3,
10528 w_xtmp1, w_xtmp2, w_xtmp3,
10529 tmp4, tmp5,
10530 tmp6);
10531 movl(tmp1, in2);
10532 andl(tmp1, 0x00000007);
10533 negl(tmp1);
10534 addl(tmp1, in2);
10535 addl(tmp1, in1);
10536
10537 BIND(L_wordByWord);
10538 cmpl(in1, tmp1);
10539 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10540 crc32(in_out, Address(in1,0), 4);
10541 addl(in1, 4);
10542 jmp(L_wordByWord);
10543
10544 BIND(L_byteByByteProlog);
10545 andl(in2, 0x00000007);
10546 movl(tmp2, 1);
10547
10548 BIND(L_byteByByte);
10549 cmpl(tmp2, in2);
10550 jccb(Assembler::greater, L_exit);
10551 movb(tmp1, Address(in1, 0));
10552 crc32(in_out, tmp1, 1);
10553 incl(in1);
10554 incl(tmp2);
10555 jmp(L_byteByByte);
10556
10557 BIND(L_exit);
10558 }
10559 #endif // LP64
10560 #undef BIND
10561 #undef BLOCK_COMMENT
10562
10563 // Compress char[] array to byte[].
10564 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10565 // @HotSpotIntrinsicCandidate
10566 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10567 // for (int i = 0; i < len; i++) {
10568 // int c = src[srcOff++];
10569 // if (c >>> 8 != 0) {
10570 // return 0;
10571 // }
10572 // dst[dstOff++] = (byte)c;
10573 // }
10574 // return len;
10575 // }
10576 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10577 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10578 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10579 Register tmp5, Register result) {
10580 Label copy_chars_loop, return_length, return_zero, done;
10581
10582 // rsi: src
10583 // rdi: dst
10584 // rdx: len
10585 // rcx: tmp5
10586 // rax: result
10587
10588 // rsi holds start addr of source char[] to be compressed
10589 // rdi holds start addr of destination byte[]
10590 // rdx holds length
10591
10592 assert(len != result, "");
10593
10594 // save length for return
10595 push(len);
10596
10597 if ((UseAVX > 2) && // AVX512
10598 VM_Version::supports_avx512vlbw() &&
10599 VM_Version::supports_bmi2()) {
10600
10601 set_vector_masking(); // opening of the stub context for programming mask registers
10602
10603 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero, below_threshold;
10604
10605 // alignment
10606 Label post_alignment;
10607
10608 // if length of the string is less than 16, handle it in an old fashioned way
10609 testl(len, -32);
10610 jcc(Assembler::zero, below_threshold);
10611
10612 // First check whether a character is compressable ( <= 0xFF).
10613 // Create mask to test for Unicode chars inside zmm vector
10614 movl(result, 0x00FF);
10615 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10616
10617 // Save k1
10618 kmovql(k3, k1);
10619
10620 testl(len, -64);
10621 jcc(Assembler::zero, post_alignment);
10622
10623 movl(tmp5, dst);
10624 andl(tmp5, (32 - 1));
10625 negl(tmp5);
10626 andl(tmp5, (32 - 1));
10627
10628 // bail out when there is nothing to be done
10629 testl(tmp5, 0xFFFFFFFF);
10630 jcc(Assembler::zero, post_alignment);
10631
10632 // ~(~0 << len), where len is the # of remaining elements to process
10633 movl(result, 0xFFFFFFFF);
10634 shlxl(result, result, tmp5);
10635 notl(result);
10636 kmovdl(k1, result);
10637
10638 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10639 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10640 ktestd(k2, k1);
10641 jcc(Assembler::carryClear, restore_k1_return_zero);
10642
10643 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10644
10645 addptr(src, tmp5);
10646 addptr(src, tmp5);
10647 addptr(dst, tmp5);
10648 subl(len, tmp5);
10649
10650 bind(post_alignment);
10651 // end of alignment
10652
10653 movl(tmp5, len);
10654 andl(tmp5, (32 - 1)); // tail count (in chars)
10655 andl(len, ~(32 - 1)); // vector count (in chars)
10656 jcc(Assembler::zero, copy_loop_tail);
10657
10658 lea(src, Address(src, len, Address::times_2));
10659 lea(dst, Address(dst, len, Address::times_1));
10660 negptr(len);
10661
10662 bind(copy_32_loop);
10663 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10664 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10665 kortestdl(k2, k2);
10666 jcc(Assembler::carryClear, restore_k1_return_zero);
10667
10668 // All elements in current processed chunk are valid candidates for
10669 // compression. Write a truncated byte elements to the memory.
10670 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10671 addptr(len, 32);
10672 jcc(Assembler::notZero, copy_32_loop);
10673
10674 bind(copy_loop_tail);
10675 // bail out when there is nothing to be done
10676 testl(tmp5, 0xFFFFFFFF);
10677 // Restore k1
10678 kmovql(k1, k3);
10679 jcc(Assembler::zero, return_length);
10680
10681 movl(len, tmp5);
10682
10683 // ~(~0 << len), where len is the # of remaining elements to process
10684 movl(result, 0xFFFFFFFF);
10685 shlxl(result, result, len);
10686 notl(result);
10687
10688 kmovdl(k1, result);
10689
10690 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10691 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10692 ktestd(k2, k1);
10693 jcc(Assembler::carryClear, restore_k1_return_zero);
10694
10695 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10696 // Restore k1
10697 kmovql(k1, k3);
10698 jmp(return_length);
10699
10700 bind(restore_k1_return_zero);
10701 // Restore k1
10702 kmovql(k1, k3);
10703 jmp(return_zero);
10704
10705 clear_vector_masking(); // closing of the stub context for programming mask registers
10706
10707 bind(below_threshold);
10708 }
10709
10710 if (UseSSE42Intrinsics) {
10711 Label copy_32_loop, copy_16, copy_tail;
10712
10713 movl(result, len);
10714
10715 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10716
10717 // vectored compression
10718 andl(len, 0xfffffff0); // vector count (in chars)
10719 andl(result, 0x0000000f); // tail count (in chars)
10720 testl(len, len);
10721 jcc(Assembler::zero, copy_16);
10722
10723 // compress 16 chars per iter
10724 movdl(tmp1Reg, tmp5);
10725 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10726 pxor(tmp4Reg, tmp4Reg);
10727
10728 lea(src, Address(src, len, Address::times_2));
10729 lea(dst, Address(dst, len, Address::times_1));
10730 negptr(len);
10731
10732 bind(copy_32_loop);
10733 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10734 por(tmp4Reg, tmp2Reg);
10735 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10736 por(tmp4Reg, tmp3Reg);
10737 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10738 jcc(Assembler::notZero, return_zero);
10739 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10740 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10741 addptr(len, 16);
10742 jcc(Assembler::notZero, copy_32_loop);
10743
10744 // compress next vector of 8 chars (if any)
10745 bind(copy_16);
10746 movl(len, result);
10747 andl(len, 0xfffffff8); // vector count (in chars)
10748 andl(result, 0x00000007); // tail count (in chars)
10749 testl(len, len);
10750 jccb(Assembler::zero, copy_tail);
10751
10752 movdl(tmp1Reg, tmp5);
10753 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10754 pxor(tmp3Reg, tmp3Reg);
10755
10756 movdqu(tmp2Reg, Address(src, 0));
10757 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10758 jccb(Assembler::notZero, return_zero);
10759 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10760 movq(Address(dst, 0), tmp2Reg);
10761 addptr(src, 16);
10762 addptr(dst, 8);
10763
10764 bind(copy_tail);
10765 movl(len, result);
10766 }
10767 // compress 1 char per iter
10768 testl(len, len);
10769 jccb(Assembler::zero, return_length);
10770 lea(src, Address(src, len, Address::times_2));
10771 lea(dst, Address(dst, len, Address::times_1));
10772 negptr(len);
10773
10774 bind(copy_chars_loop);
10775 load_unsigned_short(result, Address(src, len, Address::times_2));
10776 testl(result, 0xff00); // check if Unicode char
10777 jccb(Assembler::notZero, return_zero);
10778 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10779 increment(len);
10780 jcc(Assembler::notZero, copy_chars_loop);
10781
10782 // if compression succeeded, return length
10783 bind(return_length);
10784 pop(result);
10785 jmpb(done);
10786
10787 // if compression failed, return 0
10788 bind(return_zero);
10789 xorl(result, result);
10790 addptr(rsp, wordSize);
10791
10792 bind(done);
10793 }
10794
10795 // Inflate byte[] array to char[].
10796 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
10797 // @HotSpotIntrinsicCandidate
10798 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
10799 // for (int i = 0; i < len; i++) {
10800 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
10801 // }
10802 // }
10803 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10804 XMMRegister tmp1, Register tmp2) {
10805 Label copy_chars_loop, done, below_threshold;
10806 // rsi: src
10807 // rdi: dst
10808 // rdx: len
10809 // rcx: tmp2
10810
10811 // rsi holds start addr of source byte[] to be inflated
10812 // rdi holds start addr of destination char[]
10813 // rdx holds length
10814 assert_different_registers(src, dst, len, tmp2);
10815
10816 if ((UseAVX > 2) && // AVX512
10817 VM_Version::supports_avx512vlbw() &&
10818 VM_Version::supports_bmi2()) {
10819
10820 set_vector_masking(); // opening of the stub context for programming mask registers
10821
10822 Label copy_32_loop, copy_tail;
10823 Register tmp3_aliased = len;
10824
10825 // if length of the string is less than 16, handle it in an old fashioned way
10826 testl(len, -16);
10827 jcc(Assembler::zero, below_threshold);
10828
10829 // In order to use only one arithmetic operation for the main loop we use
10830 // this pre-calculation
10831 movl(tmp2, len);
10832 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
10833 andl(len, -32); // vector count
10834 jccb(Assembler::zero, copy_tail);
10835
10836 lea(src, Address(src, len, Address::times_1));
10837 lea(dst, Address(dst, len, Address::times_2));
10838 negptr(len);
10839
10840
10841 // inflate 32 chars per iter
10842 bind(copy_32_loop);
10843 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
10844 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
10845 addptr(len, 32);
10846 jcc(Assembler::notZero, copy_32_loop);
10847
10848 bind(copy_tail);
10849 // bail out when there is nothing to be done
10850 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
10851 jcc(Assembler::zero, done);
10852
10853 // Save k1
10854 kmovql(k2, k1);
10855
10856 // ~(~0 << length), where length is the # of remaining elements to process
10857 movl(tmp3_aliased, -1);
10858 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
10859 notl(tmp3_aliased);
10860 kmovdl(k1, tmp3_aliased);
10861 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
10862 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
10863
10864 // Restore k1
10865 kmovql(k1, k2);
10866 jmp(done);
10867
10868 clear_vector_masking(); // closing of the stub context for programming mask registers
10869 }
10870 if (UseSSE42Intrinsics) {
10871 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
10872
10873 movl(tmp2, len);
10874
10875 if (UseAVX > 1) {
10876 andl(tmp2, (16 - 1));
10877 andl(len, -16);
10878 jccb(Assembler::zero, copy_new_tail);
10879 } else {
10880 andl(tmp2, 0x00000007); // tail count (in chars)
10881 andl(len, 0xfffffff8); // vector count (in chars)
10882 jccb(Assembler::zero, copy_tail);
10883 }
10884
10885 // vectored inflation
10886 lea(src, Address(src, len, Address::times_1));
10887 lea(dst, Address(dst, len, Address::times_2));
10888 negptr(len);
10889
10890 if (UseAVX > 1) {
10891 bind(copy_16_loop);
10892 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
10893 vmovdqu(Address(dst, len, Address::times_2), tmp1);
10894 addptr(len, 16);
10895 jcc(Assembler::notZero, copy_16_loop);
10896
10897 bind(below_threshold);
10898 bind(copy_new_tail);
10899 if ((UseAVX > 2) &&
10900 VM_Version::supports_avx512vlbw() &&
10901 VM_Version::supports_bmi2()) {
10902 movl(tmp2, len);
10903 } else {
10904 movl(len, tmp2);
10905 }
10906 andl(tmp2, 0x00000007);
10907 andl(len, 0xFFFFFFF8);
10908 jccb(Assembler::zero, copy_tail);
10909
10910 pmovzxbw(tmp1, Address(src, 0));
10911 movdqu(Address(dst, 0), tmp1);
10912 addptr(src, 8);
10913 addptr(dst, 2 * 8);
10914
10915 jmp(copy_tail, true);
10916 }
10917
10918 // inflate 8 chars per iter
10919 bind(copy_8_loop);
10920 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10921 movdqu(Address(dst, len, Address::times_2), tmp1);
10922 addptr(len, 8);
10923 jcc(Assembler::notZero, copy_8_loop);
10924
10925 bind(copy_tail);
10926 movl(len, tmp2);
10927
10928 cmpl(len, 4);
10929 jccb(Assembler::less, copy_bytes);
10930
10931 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10932 pmovzxbw(tmp1, tmp1);
10933 movq(Address(dst, 0), tmp1);
10934 subptr(len, 4);
10935 addptr(src, 4);
10936 addptr(dst, 8);
10937
10938 bind(copy_bytes);
10939 } else {
10940 bind(below_threshold);
10941 }
10942
10943 testl(len, len);
10944 jccb(Assembler::zero, done);
10945 lea(src, Address(src, len, Address::times_1));
10946 lea(dst, Address(dst, len, Address::times_2));
10947 negptr(len);
10948
10949 // inflate 1 char per iter
10950 bind(copy_chars_loop);
10951 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10952 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10953 increment(len);
10954 jcc(Assembler::notZero, copy_chars_loop);
10955
10956 bind(done);
10957 }
10958
10959 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10960 switch (cond) {
10961 // Note some conditions are synonyms for others
10962 case Assembler::zero: return Assembler::notZero;
10963 case Assembler::notZero: return Assembler::zero;
10964 case Assembler::less: return Assembler::greaterEqual;
10965 case Assembler::lessEqual: return Assembler::greater;
10966 case Assembler::greater: return Assembler::lessEqual;
10967 case Assembler::greaterEqual: return Assembler::less;
10968 case Assembler::below: return Assembler::aboveEqual;
10969 case Assembler::belowEqual: return Assembler::above;
10970 case Assembler::above: return Assembler::belowEqual;
10971 case Assembler::aboveEqual: return Assembler::below;
10972 case Assembler::overflow: return Assembler::noOverflow;
10973 case Assembler::noOverflow: return Assembler::overflow;
10974 case Assembler::negative: return Assembler::positive;
10975 case Assembler::positive: return Assembler::negative;
10976 case Assembler::parity: return Assembler::noParity;
10977 case Assembler::noParity: return Assembler::parity;
10978 }
10979 ShouldNotReachHere(); return Assembler::overflow;
10980 }
10981
10982 SkipIfEqual::SkipIfEqual(
10983 MacroAssembler* masm, const bool* flag_addr, bool value) {
10984 _masm = masm;
10985 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10986 _masm->jcc(Assembler::equal, _label);
10987 }
10988
10989 SkipIfEqual::~SkipIfEqual() {
10990 _masm->bind(_label);
10991 }
10992
10993 // 32-bit Windows has its own fast-path implementation
10994 // of get_thread
10995 #if !defined(WIN32) || defined(_LP64)
10996
10997 // This is simply a call to Thread::current()
10998 void MacroAssembler::get_thread(Register thread) {
10999 if (thread != rax) {
11000 push(rax);
11001 }
11002 LP64_ONLY(push(rdi);)
11003 LP64_ONLY(push(rsi);)
11004 push(rdx);
11005 push(rcx);
11006 #ifdef _LP64
11007 push(r8);
11008 push(r9);
11009 push(r10);
11010 push(r11);
11011 #endif
11012
11013 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11014
11015 #ifdef _LP64
11016 pop(r11);
11017 pop(r10);
11018 pop(r9);
11019 pop(r8);
11020 #endif
11021 pop(rcx);
11022 pop(rdx);
11023 LP64_ONLY(pop(rsi);)
11024 LP64_ONLY(pop(rdi);)
11025 if (thread != rax) {
11026 mov(thread, rax);
11027 pop(rax);
11028 }
11029 }
11030
11031 #endif