1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 public:
42 // Support for VM calls
43 //
44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
45 // may customize this version by overriding it for its purposes (e.g., to save/restore
46 // additional registers when doing a VM call).
47
48 virtual void call_VM_leaf_base(
49 address entry_point, // the entry point
50 int number_of_arguments // the number of arguments to pop after the call
51 );
52
53 protected:
54 // This is the base routine called by the different versions of call_VM. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 //
58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
59 // returns the register which contains the thread upon return. If a thread register has been
60 // specified, the return value will correspond to that register. If no last_java_sp is specified
61 // (noreg) than rsp will be used instead.
62 virtual void call_VM_base( // returns the register containing the thread upon return
63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
64 Register java_thread, // the thread if computed before ; use noreg otherwise
65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
68 bool check_exceptions // whether to check for pending exceptions after return
69 );
70
71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
72
73 // helpers for FPU flag access
74 // tmp is a temporary register, if none is available use noreg
75 void save_rax (Register tmp);
76 void restore_rax(Register tmp);
77
78 public:
79 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 Address as_Address(AddressLiteral adr);
88 Address as_Address(ArrayAddress adr);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value);
101
102 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable);
103 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable);
104 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened);
105 void test_value_is_not_buffered(Register value, Register temp_reg, Label& not_buffered);
106
107 // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit)
108 void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array);
109 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
110
111 // Required platform-specific helpers for Label::patch_instructions.
112 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
113 void pd_patch_instruction(address branch, address target, const char* file, int line) {
114 unsigned char op = branch[0];
115 assert(op == 0xE8 /* call */ ||
116 op == 0xE9 /* jmp */ ||
117 op == 0xEB /* short jmp */ ||
118 (op & 0xF0) == 0x70 /* short jcc */ ||
119 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
120 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
121 "Invalid opcode at patch point");
122
123 if (op == 0xEB || (op & 0xF0) == 0x70) {
124 // short offset operators (jmp and jcc)
125 char* disp = (char*) &branch[1];
126 int imm8 = target - (address) &disp[1];
127 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
128 *disp = imm8;
129 } else {
130 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
131 int imm32 = target - (address) &disp[1];
132 *disp = imm32;
133 }
134 }
135
136 // The following 4 methods return the offset of the appropriate move instruction
137
138 // Support for fast byte/short loading with zero extension (depending on particular CPU)
139 int load_unsigned_byte(Register dst, Address src);
140 int load_unsigned_short(Register dst, Address src);
141
142 // Support for fast byte/short loading with sign extension (depending on particular CPU)
143 int load_signed_byte(Register dst, Address src);
144 int load_signed_short(Register dst, Address src);
145
146 // Support for sign-extension (hi:lo = extend_sign(lo))
147 void extend_sign(Register hi, Register lo);
148
149 // Load and store values by size and signed-ness
150 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
151 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
152
153 // Support for inc/dec with optimal instruction selection depending on value
154
155 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
156 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
157
158 void decrementl(Address dst, int value = 1);
159 void decrementl(Register reg, int value = 1);
160
161 void decrementq(Register reg, int value = 1);
162 void decrementq(Address dst, int value = 1);
163
164 void incrementl(Address dst, int value = 1);
165 void incrementl(Register reg, int value = 1);
166
167 void incrementq(Register reg, int value = 1);
168 void incrementq(Address dst, int value = 1);
169
170 // special instructions for EVEX
171 void setvectmask(Register dst, Register src);
172 void restorevectmask();
173
174 // Support optimal SSE move instructions.
175 void movflt(XMMRegister dst, XMMRegister src) {
176 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
177 else { movss (dst, src); return; }
178 }
179 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
180 void movflt(XMMRegister dst, AddressLiteral src);
181 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
182
183 void movdbl(XMMRegister dst, XMMRegister src) {
184 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
185 else { movsd (dst, src); return; }
186 }
187
188 void movdbl(XMMRegister dst, AddressLiteral src);
189
190 void movdbl(XMMRegister dst, Address src) {
191 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
192 else { movlpd(dst, src); return; }
193 }
194 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
195
196 void incrementl(AddressLiteral dst);
197 void incrementl(ArrayAddress dst);
198
199 void incrementq(AddressLiteral dst);
200
201 // Alignment
202 void align(int modulus);
203 void align(int modulus, int target);
204
205 // A 5 byte nop that is safe for patching (see patch_verified_entry)
206 void fat_nop();
207
208 // Stack frame creation/removal
209 void enter();
210 void leave();
211
212 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
213 // The pointer will be loaded into the thread register.
214 void get_thread(Register thread);
215
216
217 // Support for VM calls
218 //
219 // It is imperative that all calls into the VM are handled via the call_VM macros.
220 // They make sure that the stack linkage is setup correctly. call_VM's correspond
221 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
222
223
224 void call_VM(Register oop_result,
225 address entry_point,
226 bool check_exceptions = true);
227 void call_VM(Register oop_result,
228 address entry_point,
229 Register arg_1,
230 bool check_exceptions = true);
231 void call_VM(Register oop_result,
232 address entry_point,
233 Register arg_1, Register arg_2,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 address entry_point,
237 Register arg_1, Register arg_2, Register arg_3,
238 bool check_exceptions = true);
239
240 // Overloadings with last_Java_sp
241 void call_VM(Register oop_result,
242 Register last_java_sp,
243 address entry_point,
244 int number_of_arguments = 0,
245 bool check_exceptions = true);
246 void call_VM(Register oop_result,
247 Register last_java_sp,
248 address entry_point,
249 Register arg_1, bool
250 check_exceptions = true);
251 void call_VM(Register oop_result,
252 Register last_java_sp,
253 address entry_point,
254 Register arg_1, Register arg_2,
255 bool check_exceptions = true);
256 void call_VM(Register oop_result,
257 Register last_java_sp,
258 address entry_point,
259 Register arg_1, Register arg_2, Register arg_3,
260 bool check_exceptions = true);
261
262 void get_vm_result (Register oop_result, Register thread);
263 void get_vm_result_2(Register metadata_result, Register thread);
264
265 // These always tightly bind to MacroAssembler::call_VM_base
266 // bypassing the virtual implementation
267 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
268 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
269 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
270 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
271 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
272
273 void call_VM_leaf0(address entry_point);
274 void call_VM_leaf(address entry_point,
275 int number_of_arguments = 0);
276 void call_VM_leaf(address entry_point,
277 Register arg_1);
278 void call_VM_leaf(address entry_point,
279 Register arg_1, Register arg_2);
280 void call_VM_leaf(address entry_point,
281 Register arg_1, Register arg_2, Register arg_3);
282
283 // These always tightly bind to MacroAssembler::call_VM_leaf_base
284 // bypassing the virtual implementation
285 void super_call_VM_leaf(address entry_point);
286 void super_call_VM_leaf(address entry_point, Register arg_1);
287 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
288 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
289 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
290
291 // last Java Frame (fills frame anchor)
292 void set_last_Java_frame(Register thread,
293 Register last_java_sp,
294 Register last_java_fp,
295 address last_java_pc);
296
297 // thread in the default location (r15_thread on 64bit)
298 void set_last_Java_frame(Register last_java_sp,
299 Register last_java_fp,
300 address last_java_pc);
301
302 void reset_last_Java_frame(Register thread, bool clear_fp);
303
304 // thread in the default location (r15_thread on 64bit)
305 void reset_last_Java_frame(bool clear_fp);
306
307 // jobjects
308 void clear_jweak_tag(Register possibly_jweak);
309 void resolve_jobject(Register value, Register thread, Register tmp);
310
311 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
312 void c2bool(Register x);
313
314 // C++ bool manipulation
315
316 void movbool(Register dst, Address src);
317 void movbool(Address dst, bool boolconst);
318 void movbool(Address dst, Register src);
319 void testbool(Register dst);
320
321 void resolve_oop_handle(Register result, Register tmp = rscratch2);
322 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
323
324 // oop manipulations
325 void load_klass(Register dst, Register src);
326 void store_klass(Register dst, Register src);
327
328 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
329 Register tmp1, Register thread_tmp);
330 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
331 Register tmp1, Register tmp2);
332
333 // Resolves obj access. Result is placed in the same register.
334 // All other registers are preserved.
335 void resolve(DecoratorSet decorators, Register obj);
336
337 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
338 Register thread_tmp = noreg, DecoratorSet decorators = 0);
339 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
340 Register thread_tmp = noreg, DecoratorSet decorators = 0);
341 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
342 Register tmp2 = noreg, DecoratorSet decorators = 0);
343
344 // Used for storing NULL. All other oop constants should be
345 // stored using routines that take a jobject.
346 void store_heap_oop_null(Address dst);
347
348 void load_prototype_header(Register dst, Register src);
349
350 #ifdef _LP64
351 void store_klass_gap(Register dst, Register src);
352
353 // This dummy is to prevent a call to store_heap_oop from
354 // converting a zero (like NULL) into a Register by giving
355 // the compiler two choices it can't resolve
356
357 void store_heap_oop(Address dst, void* dummy);
358
359 void encode_heap_oop(Register r);
360 void decode_heap_oop(Register r);
361 void encode_heap_oop_not_null(Register r);
362 void decode_heap_oop_not_null(Register r);
363 void encode_heap_oop_not_null(Register dst, Register src);
364 void decode_heap_oop_not_null(Register dst, Register src);
365
366 void set_narrow_oop(Register dst, jobject obj);
367 void set_narrow_oop(Address dst, jobject obj);
368 void cmp_narrow_oop(Register dst, jobject obj);
369 void cmp_narrow_oop(Address dst, jobject obj);
370
371 void encode_klass_not_null(Register r);
372 void decode_klass_not_null(Register r);
373 void encode_klass_not_null(Register dst, Register src);
374 void decode_klass_not_null(Register dst, Register src);
375 void set_narrow_klass(Register dst, Klass* k);
376 void set_narrow_klass(Address dst, Klass* k);
377 void cmp_narrow_klass(Register dst, Klass* k);
378 void cmp_narrow_klass(Address dst, Klass* k);
379
380 // Returns the byte size of the instructions generated by decode_klass_not_null()
381 // when compressed klass pointers are being used.
382 static int instr_size_for_decode_klass_not_null();
383
384 // if heap base register is used - reinit it with the correct value
385 void reinit_heapbase();
386
387 DEBUG_ONLY(void verify_heapbase(const char* msg);)
388
389 #endif // _LP64
390
391 // Int division/remainder for Java
392 // (as idivl, but checks for special case as described in JVM spec.)
393 // returns idivl instruction offset for implicit exception handling
394 int corrected_idivl(Register reg);
395
396 // Long division/remainder for Java
397 // (as idivq, but checks for special case as described in JVM spec.)
398 // returns idivq instruction offset for implicit exception handling
399 int corrected_idivq(Register reg);
400
401 void int3();
402
403 // Long operation macros for a 32bit cpu
404 // Long negation for Java
405 void lneg(Register hi, Register lo);
406
407 // Long multiplication for Java
408 // (destroys contents of eax, ebx, ecx and edx)
409 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
410
411 // Long shifts for Java
412 // (semantics as described in JVM spec.)
413 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
414 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
415
416 // Long compare for Java
417 // (semantics as described in JVM spec.)
418 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
419
420
421 // misc
422
423 // Sign extension
424 void sign_extend_short(Register reg);
425 void sign_extend_byte(Register reg);
426
427 // Division by power of 2, rounding towards 0
428 void division_with_shift(Register reg, int shift_value);
429
430 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
431 //
432 // CF (corresponds to C0) if x < y
433 // PF (corresponds to C2) if unordered
434 // ZF (corresponds to C3) if x = y
435 //
436 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
437 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
438 void fcmp(Register tmp);
439 // Variant of the above which allows y to be further down the stack
440 // and which only pops x and y if specified. If pop_right is
441 // specified then pop_left must also be specified.
442 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
443
444 // Floating-point comparison for Java
445 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
446 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
447 // (semantics as described in JVM spec.)
448 void fcmp2int(Register dst, bool unordered_is_less);
449 // Variant of the above which allows y to be further down the stack
450 // and which only pops x and y if specified. If pop_right is
451 // specified then pop_left must also be specified.
452 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
453
454 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
455 // tmp is a temporary register, if none is available use noreg
456 void fremr(Register tmp);
457
458 // dst = c = a * b + c
459 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
460 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
461
462 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
463 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
464 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
465 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
466
467
468 // same as fcmp2int, but using SSE2
469 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
470 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
471
472 // branch to L if FPU flag C2 is set/not set
473 // tmp is a temporary register, if none is available use noreg
474 void jC2 (Register tmp, Label& L);
475 void jnC2(Register tmp, Label& L);
476
477 // Pop ST (ffree & fincstp combined)
478 void fpop();
479
480 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
481 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
482 void load_float(Address src);
483
484 // Store float value to 'address'. If UseSSE >= 1, the value is stored
485 // from register xmm0. Otherwise, the value is stored from the FPU stack.
486 void store_float(Address dst);
487
488 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
489 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
490 void load_double(Address src);
491
492 // Store double value to 'address'. If UseSSE >= 2, the value is stored
493 // from register xmm0. Otherwise, the value is stored from the FPU stack.
494 void store_double(Address dst);
495
496 // Save/restore ZMM (512bit) register on stack.
497 void push_zmm(XMMRegister reg);
498 void pop_zmm(XMMRegister reg);
499
500 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
501 void push_fTOS();
502
503 // pops double TOS element from CPU stack and pushes on FPU stack
504 void pop_fTOS();
505
506 void empty_FPU_stack();
507
508 void push_IU_state();
509 void pop_IU_state();
510
511 void push_FPU_state();
512 void pop_FPU_state();
513
514 void push_CPU_state();
515 void pop_CPU_state();
516
517 // Round up to a power of two
518 void round_to(Register reg, int modulus);
519
520 // Callee saved registers handling
521 void push_callee_saved_registers();
522 void pop_callee_saved_registers();
523
524 // allocation
525 void eden_allocate(
526 Register thread, // Current thread
527 Register obj, // result: pointer to object after successful allocation
528 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
529 int con_size_in_bytes, // object size in bytes if known at compile time
530 Register t1, // temp register
531 Label& slow_case // continuation point if fast allocation fails
532 );
533 void tlab_allocate(
534 Register thread, // Current thread
535 Register obj, // result: pointer to object after successful allocation
536 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
537 int con_size_in_bytes, // object size in bytes if known at compile time
538 Register t1, // temp register
539 Register t2, // temp register
540 Label& slow_case // continuation point if fast allocation fails
541 );
542 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
543
544 // interface method calling
545 void lookup_interface_method(Register recv_klass,
546 Register intf_klass,
547 RegisterOrConstant itable_index,
548 Register method_result,
549 Register scan_temp,
550 Label& no_such_interface,
551 bool return_method = true);
552
553 // virtual method calling
554 void lookup_virtual_method(Register recv_klass,
555 RegisterOrConstant vtable_index,
556 Register method_result);
557
558 // Test sub_klass against super_klass, with fast and slow paths.
559
560 // The fast path produces a tri-state answer: yes / no / maybe-slow.
561 // One of the three labels can be NULL, meaning take the fall-through.
562 // If super_check_offset is -1, the value is loaded up from super_klass.
563 // No registers are killed, except temp_reg.
564 void check_klass_subtype_fast_path(Register sub_klass,
565 Register super_klass,
566 Register temp_reg,
567 Label* L_success,
568 Label* L_failure,
569 Label* L_slow_path,
570 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
571
572 // The rest of the type check; must be wired to a corresponding fast path.
573 // It does not repeat the fast path logic, so don't use it standalone.
574 // The temp_reg and temp2_reg can be noreg, if no temps are available.
575 // Updates the sub's secondary super cache as necessary.
576 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
577 void check_klass_subtype_slow_path(Register sub_klass,
578 Register super_klass,
579 Register temp_reg,
580 Register temp2_reg,
581 Label* L_success,
582 Label* L_failure,
583 bool set_cond_codes = false);
584
585 // Simplified, combined version, good for typical uses.
586 // Falls through on failure.
587 void check_klass_subtype(Register sub_klass,
588 Register super_klass,
589 Register temp_reg,
590 Label& L_success);
591
592 // method handles (JSR 292)
593 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
594
595 //----
596 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
597
598 // Debugging
599
600 // only if +VerifyOops
601 // TODO: Make these macros with file and line like sparc version!
602 void verify_oop(Register reg, const char* s = "broken oop");
603 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
604
605 // TODO: verify method and klass metadata (compare against vptr?)
606 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
607 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
608
609 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
610 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
611
612 // only if +VerifyFPU
613 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
614
615 // Verify or restore cpu control state after JNI call
616 void restore_cpu_control_state_after_jni();
617
618 // prints msg, dumps registers and stops execution
619 void stop(const char* msg);
620
621 // prints msg and continues
622 void warn(const char* msg);
623
624 // dumps registers and other state
625 void print_state();
626
627 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
628 static void debug64(char* msg, int64_t pc, int64_t regs[]);
629 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
630 static void print_state64(int64_t pc, int64_t regs[]);
631
632 void os_breakpoint();
633
634 void untested() { stop("untested"); }
635
636 void unimplemented(const char* what = "");
637
638 void should_not_reach_here() { stop("should not reach here"); }
639
640 void print_CPU_state();
641
642 // Stack overflow checking
643 void bang_stack_with_offset(int offset) {
644 // stack grows down, caller passes positive offset
645 assert(offset > 0, "must bang with negative offset");
646 movl(Address(rsp, (-offset)), rax);
647 }
648
649 // Writes to stack successive pages until offset reached to check for
650 // stack overflow + shadow pages. Also, clobbers tmp
651 void bang_stack_size(Register size, Register tmp);
652
653 // Check for reserved stack access in method being exited (for JIT)
654 void reserved_stack_check();
655
656 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
657 Register tmp,
658 int offset);
659
660 // Support for serializing memory accesses between threads
661 void serialize_memory(Register thread, Register tmp);
662
663 // If thread_reg is != noreg the code assumes the register passed contains
664 // the thread (required on 64 bit).
665 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
666
667 void verify_tlab();
668
669 // Biased locking support
670 // lock_reg and obj_reg must be loaded up with the appropriate values.
671 // swap_reg must be rax, and is killed.
672 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
673 // be killed; if not supplied, push/pop will be used internally to
674 // allocate a temporary (inefficient, avoid if possible).
675 // Optional slow case is for implementations (interpreter and C1) which branch to
676 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
677 // Returns offset of first potentially-faulting instruction for null
678 // check info (currently consumed only by C1). If
679 // swap_reg_contains_mark is true then returns -1 as it is assumed
680 // the calling code has already passed any potential faults.
681 int biased_locking_enter(Register lock_reg, Register obj_reg,
682 Register swap_reg, Register tmp_reg,
683 bool swap_reg_contains_mark,
684 Label& done, Label* slow_case = NULL,
685 BiasedLockingCounters* counters = NULL);
686 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
687 #ifdef COMPILER2
688 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
689 // See full desription in macroAssembler_x86.cpp.
690 void fast_lock(Register obj, Register box, Register tmp,
691 Register scr, Register cx1, Register cx2,
692 BiasedLockingCounters* counters,
693 RTMLockingCounters* rtm_counters,
694 RTMLockingCounters* stack_rtm_counters,
695 Metadata* method_data,
696 bool use_rtm, bool profile_rtm);
697 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
698 #if INCLUDE_RTM_OPT
699 void rtm_counters_update(Register abort_status, Register rtm_counters);
700 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
701 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
702 RTMLockingCounters* rtm_counters,
703 Metadata* method_data);
704 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
705 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
706 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
707 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
708 void rtm_stack_locking(Register obj, Register tmp, Register scr,
709 Register retry_on_abort_count,
710 RTMLockingCounters* stack_rtm_counters,
711 Metadata* method_data, bool profile_rtm,
712 Label& DONE_LABEL, Label& IsInflated);
713 void rtm_inflated_locking(Register obj, Register box, Register tmp,
714 Register scr, Register retry_on_busy_count,
715 Register retry_on_abort_count,
716 RTMLockingCounters* rtm_counters,
717 Metadata* method_data, bool profile_rtm,
718 Label& DONE_LABEL);
719 #endif
720 #endif
721
722 Condition negate_condition(Condition cond);
723
724 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
725 // operands. In general the names are modified to avoid hiding the instruction in Assembler
726 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
727 // here in MacroAssembler. The major exception to this rule is call
728
729 // Arithmetics
730
731
732 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
733 void addptr(Address dst, Register src);
734
735 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
736 void addptr(Register dst, int32_t src);
737 void addptr(Register dst, Register src);
738 void addptr(Register dst, RegisterOrConstant src) {
739 if (src.is_constant()) addptr(dst, (int) src.as_constant());
740 else addptr(dst, src.as_register());
741 }
742
743 void andptr(Register dst, int32_t src);
744 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
745
746 void cmp8(AddressLiteral src1, int imm);
747
748 // renamed to drag out the casting of address to int32_t/intptr_t
749 void cmp32(Register src1, int32_t imm);
750
751 void cmp32(AddressLiteral src1, int32_t imm);
752 // compare reg - mem, or reg - &mem
753 void cmp32(Register src1, AddressLiteral src2);
754
755 void cmp32(Register src1, Address src2);
756
757 #ifndef _LP64
758 void cmpklass(Address dst, Metadata* obj);
759 void cmpklass(Register dst, Metadata* obj);
760 void cmpoop(Address dst, jobject obj);
761 void cmpoop_raw(Address dst, jobject obj);
762 #endif // _LP64
763
764 void cmpoop(Register src1, Register src2);
765 void cmpoop(Register src1, Address src2);
766 void cmpoop(Register dst, jobject obj);
767 void cmpoop_raw(Register dst, jobject obj);
768
769 // NOTE src2 must be the lval. This is NOT an mem-mem compare
770 void cmpptr(Address src1, AddressLiteral src2);
771
772 void cmpptr(Register src1, AddressLiteral src2);
773
774 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
775 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
776 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
777
778 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
779 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
780
781 // cmp64 to avoild hiding cmpq
782 void cmp64(Register src1, AddressLiteral src);
783
784 void cmpxchgptr(Register reg, Address adr);
785
786 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
787
788
789 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
790 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
791
792
793 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
794
795 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
796
797 void shlptr(Register dst, int32_t shift);
798 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
799
800 void shrptr(Register dst, int32_t shift);
801 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
802
803 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
804 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
805
806 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
807
808 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
809 void subptr(Register dst, int32_t src);
810 // Force generation of a 4 byte immediate value even if it fits into 8bit
811 void subptr_imm32(Register dst, int32_t src);
812 void subptr(Register dst, Register src);
813 void subptr(Register dst, RegisterOrConstant src) {
814 if (src.is_constant()) subptr(dst, (int) src.as_constant());
815 else subptr(dst, src.as_register());
816 }
817
818 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
819 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
820
821 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
822 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
823
824 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
825
826
827
828 // Helper functions for statistics gathering.
829 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
830 void cond_inc32(Condition cond, AddressLiteral counter_addr);
831 // Unconditional atomic increment.
832 void atomic_incl(Address counter_addr);
833 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
834 #ifdef _LP64
835 void atomic_incq(Address counter_addr);
836 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
837 #endif
838 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
839 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
840
841 void lea(Register dst, AddressLiteral adr);
842 void lea(Address dst, AddressLiteral adr);
843 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
844
845 void leal32(Register dst, Address src) { leal(dst, src); }
846
847 // Import other testl() methods from the parent class or else
848 // they will be hidden by the following overriding declaration.
849 using Assembler::testl;
850 void testl(Register dst, AddressLiteral src);
851
852 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
853 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
854 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
855 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
856
857 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
858 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
859 void testptr(Register src1, Register src2);
860
861 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
862 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
863
864 // Calls
865
866 void call(Label& L, relocInfo::relocType rtype);
867 void call(Register entry);
868
869 // NOTE: this call transfers to the effective address of entry NOT
870 // the address contained by entry. This is because this is more natural
871 // for jumps/calls.
872 void call(AddressLiteral entry);
873
874 // Emit the CompiledIC call idiom
875 void ic_call(address entry, jint method_index = 0);
876
877 // Jumps
878
879 // NOTE: these jumps tranfer to the effective address of dst NOT
880 // the address contained by dst. This is because this is more natural
881 // for jumps/calls.
882 void jump(AddressLiteral dst);
883 void jump_cc(Condition cc, AddressLiteral dst);
884
885 // 32bit can do a case table jump in one instruction but we no longer allow the base
886 // to be installed in the Address class. This jump will tranfers to the address
887 // contained in the location described by entry (not the address of entry)
888 void jump(ArrayAddress entry);
889
890 // Floating
891
892 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
893 void andpd(XMMRegister dst, AddressLiteral src);
894 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
895
896 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
897 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
898 void andps(XMMRegister dst, AddressLiteral src);
899
900 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
901 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
902 void comiss(XMMRegister dst, AddressLiteral src);
903
904 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
905 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
906 void comisd(XMMRegister dst, AddressLiteral src);
907
908 void fadd_s(Address src) { Assembler::fadd_s(src); }
909 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
910
911 void fldcw(Address src) { Assembler::fldcw(src); }
912 void fldcw(AddressLiteral src);
913
914 void fld_s(int index) { Assembler::fld_s(index); }
915 void fld_s(Address src) { Assembler::fld_s(src); }
916 void fld_s(AddressLiteral src);
917
918 void fld_d(Address src) { Assembler::fld_d(src); }
919 void fld_d(AddressLiteral src);
920
921 void fld_x(Address src) { Assembler::fld_x(src); }
922 void fld_x(AddressLiteral src);
923
924 void fmul_s(Address src) { Assembler::fmul_s(src); }
925 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
926
927 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
928 void ldmxcsr(AddressLiteral src);
929
930 #ifdef _LP64
931 private:
932 void sha256_AVX2_one_round_compute(
933 Register reg_old_h,
934 Register reg_a,
935 Register reg_b,
936 Register reg_c,
937 Register reg_d,
938 Register reg_e,
939 Register reg_f,
940 Register reg_g,
941 Register reg_h,
942 int iter);
943 void sha256_AVX2_four_rounds_compute_first(int start);
944 void sha256_AVX2_four_rounds_compute_last(int start);
945 void sha256_AVX2_one_round_and_sched(
946 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
947 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
948 XMMRegister xmm_2, /* ymm6 */
949 XMMRegister xmm_3, /* ymm7 */
950 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
951 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
952 Register reg_c, /* edi */
953 Register reg_d, /* esi */
954 Register reg_e, /* r8d */
955 Register reg_f, /* r9d */
956 Register reg_g, /* r10d */
957 Register reg_h, /* r11d */
958 int iter);
959
960 void addm(int disp, Register r1, Register r2);
961
962 public:
963 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
964 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
965 Register buf, Register state, Register ofs, Register limit, Register rsp,
966 bool multi_block, XMMRegister shuf_mask);
967 #endif
968
969 #ifdef _LP64
970 private:
971 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
972 Register e, Register f, Register g, Register h, int iteration);
973
974 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
975 Register a, Register b, Register c, Register d, Register e, Register f,
976 Register g, Register h, int iteration);
977
978 void addmq(int disp, Register r1, Register r2);
979 public:
980 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
981 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
982 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
983 XMMRegister shuf_mask);
984 #endif
985
986 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
987 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
988 Register buf, Register state, Register ofs, Register limit, Register rsp,
989 bool multi_block);
990
991 #ifdef _LP64
992 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
993 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
994 Register buf, Register state, Register ofs, Register limit, Register rsp,
995 bool multi_block, XMMRegister shuf_mask);
996 #else
997 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
998 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
999 Register buf, Register state, Register ofs, Register limit, Register rsp,
1000 bool multi_block);
1001 #endif
1002
1003 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1004 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1005 Register rax, Register rcx, Register rdx, Register tmp);
1006
1007 #ifdef _LP64
1008 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1009 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1010 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1011
1012 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1013 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1014 Register rax, Register rcx, Register rdx, Register r11);
1015
1016 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1017 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1018 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1019
1020 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1021 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1022 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1023 Register tmp3, Register tmp4);
1024
1025 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1026 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1027 Register rax, Register rcx, Register rdx, Register tmp1,
1028 Register tmp2, Register tmp3, Register tmp4);
1029 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1030 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1031 Register rax, Register rcx, Register rdx, Register tmp1,
1032 Register tmp2, Register tmp3, Register tmp4);
1033 #else
1034 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1035 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1036 Register rax, Register rcx, Register rdx, Register tmp1);
1037
1038 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1039 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1040 Register rax, Register rcx, Register rdx, Register tmp);
1041
1042 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1043 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1044 Register rdx, Register tmp);
1045
1046 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1047 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1048 Register rax, Register rbx, Register rdx);
1049
1050 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1051 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1052 Register rax, Register rcx, Register rdx, Register tmp);
1053
1054 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1055 Register edx, Register ebx, Register esi, Register edi,
1056 Register ebp, Register esp);
1057
1058 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1059 Register esi, Register edi, Register ebp, Register esp);
1060
1061 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1062 Register edx, Register ebx, Register esi, Register edi,
1063 Register ebp, Register esp);
1064
1065 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1066 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1067 Register rax, Register rcx, Register rdx, Register tmp);
1068 #endif
1069
1070 void increase_precision();
1071 void restore_precision();
1072
1073 private:
1074
1075 // these are private because users should be doing movflt/movdbl
1076
1077 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1078 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1079 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1080 void movss(XMMRegister dst, AddressLiteral src);
1081
1082 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1083 void movlpd(XMMRegister dst, AddressLiteral src);
1084
1085 public:
1086
1087 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1088 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1089 void addsd(XMMRegister dst, AddressLiteral src);
1090
1091 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1092 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1093 void addss(XMMRegister dst, AddressLiteral src);
1094
1095 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1096 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1097 void addpd(XMMRegister dst, AddressLiteral src);
1098
1099 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1100 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1101 void divsd(XMMRegister dst, AddressLiteral src);
1102
1103 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1104 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1105 void divss(XMMRegister dst, AddressLiteral src);
1106
1107 // Move Unaligned Double Quadword
1108 void movdqu(Address dst, XMMRegister src);
1109 void movdqu(XMMRegister dst, Address src);
1110 void movdqu(XMMRegister dst, XMMRegister src);
1111 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1112 // AVX Unaligned forms
1113 void vmovdqu(Address dst, XMMRegister src);
1114 void vmovdqu(XMMRegister dst, Address src);
1115 void vmovdqu(XMMRegister dst, XMMRegister src);
1116 void vmovdqu(XMMRegister dst, AddressLiteral src);
1117 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1118 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1119 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1120 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1121
1122 // Move Aligned Double Quadword
1123 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1124 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1125 void movdqa(XMMRegister dst, AddressLiteral src);
1126
1127 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1128 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1129 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1130 void movsd(XMMRegister dst, AddressLiteral src);
1131
1132 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1133 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1134 void mulpd(XMMRegister dst, AddressLiteral src);
1135
1136 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1137 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1138 void mulsd(XMMRegister dst, AddressLiteral src);
1139
1140 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1141 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1142 void mulss(XMMRegister dst, AddressLiteral src);
1143
1144 // Carry-Less Multiplication Quadword
1145 void pclmulldq(XMMRegister dst, XMMRegister src) {
1146 // 0x00 - multiply lower 64 bits [0:63]
1147 Assembler::pclmulqdq(dst, src, 0x00);
1148 }
1149 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1150 // 0x11 - multiply upper 64 bits [64:127]
1151 Assembler::pclmulqdq(dst, src, 0x11);
1152 }
1153
1154 void pcmpeqb(XMMRegister dst, XMMRegister src);
1155 void pcmpeqw(XMMRegister dst, XMMRegister src);
1156
1157 void pcmpestri(XMMRegister dst, Address src, int imm8);
1158 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1159
1160 void pmovzxbw(XMMRegister dst, XMMRegister src);
1161 void pmovzxbw(XMMRegister dst, Address src);
1162
1163 void pmovmskb(Register dst, XMMRegister src);
1164
1165 void ptest(XMMRegister dst, XMMRegister src);
1166
1167 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1168 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1169 void sqrtsd(XMMRegister dst, AddressLiteral src);
1170
1171 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1172 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1173 void sqrtss(XMMRegister dst, AddressLiteral src);
1174
1175 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1176 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1177 void subsd(XMMRegister dst, AddressLiteral src);
1178
1179 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1180 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1181 void subss(XMMRegister dst, AddressLiteral src);
1182
1183 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1184 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1185 void ucomiss(XMMRegister dst, AddressLiteral src);
1186
1187 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1188 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1189 void ucomisd(XMMRegister dst, AddressLiteral src);
1190
1191 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1192 void xorpd(XMMRegister dst, XMMRegister src);
1193 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1194 void xorpd(XMMRegister dst, AddressLiteral src);
1195
1196 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1197 void xorps(XMMRegister dst, XMMRegister src);
1198 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1199 void xorps(XMMRegister dst, AddressLiteral src);
1200
1201 // Shuffle Bytes
1202 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1203 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1204 void pshufb(XMMRegister dst, AddressLiteral src);
1205 // AVX 3-operands instructions
1206
1207 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1208 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1209 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1210
1211 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1212 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1213 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1214
1215 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1216 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1217
1218 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1219 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1220
1221 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1222 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1223
1224 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1225 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1226 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1227
1228 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1229
1230 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1231 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1232
1233 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1234 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1235
1236 void vpmovmskb(Register dst, XMMRegister src);
1237
1238 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1239 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1240
1241 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1242 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1243
1244 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1245 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1246
1247 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1248 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1249
1250 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1251 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1252
1253 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1254 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1255
1256 void vptest(XMMRegister dst, XMMRegister src);
1257
1258 void punpcklbw(XMMRegister dst, XMMRegister src);
1259 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1260
1261 void pshufd(XMMRegister dst, Address src, int mode);
1262 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1263
1264 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1265 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1266
1267 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1268 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1269 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1270
1271 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1272 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1273 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1274
1275 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1276 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1277 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1278
1279 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1280 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1281 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1282
1283 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1284 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1285 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1286
1287 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1288 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1289 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1290
1291 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1292 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1293 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1294
1295 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1296 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1297 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1298
1299 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1300 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1301
1302 // AVX Vector instructions
1303
1304 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1305 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1306 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1307
1308 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1309 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1310 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1311
1312 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1313 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1314 Assembler::vpxor(dst, nds, src, vector_len);
1315 else
1316 Assembler::vxorpd(dst, nds, src, vector_len);
1317 }
1318 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1319 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1320 Assembler::vpxor(dst, nds, src, vector_len);
1321 else
1322 Assembler::vxorpd(dst, nds, src, vector_len);
1323 }
1324
1325 // Simple version for AVX2 256bit vectors
1326 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1327 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1328
1329 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1330 if (UseAVX > 2) {
1331 Assembler::vinserti32x4(dst, dst, src, imm8);
1332 } else if (UseAVX > 1) {
1333 // vinserti128 is available only in AVX2
1334 Assembler::vinserti128(dst, nds, src, imm8);
1335 } else {
1336 Assembler::vinsertf128(dst, nds, src, imm8);
1337 }
1338 }
1339
1340 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1341 if (UseAVX > 2) {
1342 Assembler::vinserti32x4(dst, dst, src, imm8);
1343 } else if (UseAVX > 1) {
1344 // vinserti128 is available only in AVX2
1345 Assembler::vinserti128(dst, nds, src, imm8);
1346 } else {
1347 Assembler::vinsertf128(dst, nds, src, imm8);
1348 }
1349 }
1350
1351 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1352 if (UseAVX > 2) {
1353 Assembler::vextracti32x4(dst, src, imm8);
1354 } else if (UseAVX > 1) {
1355 // vextracti128 is available only in AVX2
1356 Assembler::vextracti128(dst, src, imm8);
1357 } else {
1358 Assembler::vextractf128(dst, src, imm8);
1359 }
1360 }
1361
1362 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1363 if (UseAVX > 2) {
1364 Assembler::vextracti32x4(dst, src, imm8);
1365 } else if (UseAVX > 1) {
1366 // vextracti128 is available only in AVX2
1367 Assembler::vextracti128(dst, src, imm8);
1368 } else {
1369 Assembler::vextractf128(dst, src, imm8);
1370 }
1371 }
1372
1373 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1374 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1375 vinserti128(dst, dst, src, 1);
1376 }
1377 void vinserti128_high(XMMRegister dst, Address src) {
1378 vinserti128(dst, dst, src, 1);
1379 }
1380 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1381 vextracti128(dst, src, 1);
1382 }
1383 void vextracti128_high(Address dst, XMMRegister src) {
1384 vextracti128(dst, src, 1);
1385 }
1386
1387 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1388 if (UseAVX > 2) {
1389 Assembler::vinsertf32x4(dst, dst, src, 1);
1390 } else {
1391 Assembler::vinsertf128(dst, dst, src, 1);
1392 }
1393 }
1394
1395 void vinsertf128_high(XMMRegister dst, Address src) {
1396 if (UseAVX > 2) {
1397 Assembler::vinsertf32x4(dst, dst, src, 1);
1398 } else {
1399 Assembler::vinsertf128(dst, dst, src, 1);
1400 }
1401 }
1402
1403 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1404 if (UseAVX > 2) {
1405 Assembler::vextractf32x4(dst, src, 1);
1406 } else {
1407 Assembler::vextractf128(dst, src, 1);
1408 }
1409 }
1410
1411 void vextractf128_high(Address dst, XMMRegister src) {
1412 if (UseAVX > 2) {
1413 Assembler::vextractf32x4(dst, src, 1);
1414 } else {
1415 Assembler::vextractf128(dst, src, 1);
1416 }
1417 }
1418
1419 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1420 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1421 Assembler::vinserti64x4(dst, dst, src, 1);
1422 }
1423 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1424 Assembler::vinsertf64x4(dst, dst, src, 1);
1425 }
1426 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1427 Assembler::vextracti64x4(dst, src, 1);
1428 }
1429 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1430 Assembler::vextractf64x4(dst, src, 1);
1431 }
1432 void vextractf64x4_high(Address dst, XMMRegister src) {
1433 Assembler::vextractf64x4(dst, src, 1);
1434 }
1435 void vinsertf64x4_high(XMMRegister dst, Address src) {
1436 Assembler::vinsertf64x4(dst, dst, src, 1);
1437 }
1438
1439 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1440 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1441 vinserti128(dst, dst, src, 0);
1442 }
1443 void vinserti128_low(XMMRegister dst, Address src) {
1444 vinserti128(dst, dst, src, 0);
1445 }
1446 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1447 vextracti128(dst, src, 0);
1448 }
1449 void vextracti128_low(Address dst, XMMRegister src) {
1450 vextracti128(dst, src, 0);
1451 }
1452
1453 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1454 if (UseAVX > 2) {
1455 Assembler::vinsertf32x4(dst, dst, src, 0);
1456 } else {
1457 Assembler::vinsertf128(dst, dst, src, 0);
1458 }
1459 }
1460
1461 void vinsertf128_low(XMMRegister dst, Address src) {
1462 if (UseAVX > 2) {
1463 Assembler::vinsertf32x4(dst, dst, src, 0);
1464 } else {
1465 Assembler::vinsertf128(dst, dst, src, 0);
1466 }
1467 }
1468
1469 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1470 if (UseAVX > 2) {
1471 Assembler::vextractf32x4(dst, src, 0);
1472 } else {
1473 Assembler::vextractf128(dst, src, 0);
1474 }
1475 }
1476
1477 void vextractf128_low(Address dst, XMMRegister src) {
1478 if (UseAVX > 2) {
1479 Assembler::vextractf32x4(dst, src, 0);
1480 } else {
1481 Assembler::vextractf128(dst, src, 0);
1482 }
1483 }
1484
1485 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1486 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1487 Assembler::vinserti64x4(dst, dst, src, 0);
1488 }
1489 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1490 Assembler::vinsertf64x4(dst, dst, src, 0);
1491 }
1492 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1493 Assembler::vextracti64x4(dst, src, 0);
1494 }
1495 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1496 Assembler::vextractf64x4(dst, src, 0);
1497 }
1498 void vextractf64x4_low(Address dst, XMMRegister src) {
1499 Assembler::vextractf64x4(dst, src, 0);
1500 }
1501 void vinsertf64x4_low(XMMRegister dst, Address src) {
1502 Assembler::vinsertf64x4(dst, dst, src, 0);
1503 }
1504
1505 // Carry-Less Multiplication Quadword
1506 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1507 // 0x00 - multiply lower 64 bits [0:63]
1508 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1509 }
1510 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1511 // 0x11 - multiply upper 64 bits [64:127]
1512 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1513 }
1514 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1515 // 0x00 - multiply lower 64 bits [0:63]
1516 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1517 }
1518 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1519 // 0x11 - multiply upper 64 bits [64:127]
1520 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1521 }
1522
1523 // Data
1524
1525 void cmov32( Condition cc, Register dst, Address src);
1526 void cmov32( Condition cc, Register dst, Register src);
1527
1528 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1529
1530 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1531 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1532
1533 void movoop(Register dst, jobject obj);
1534 void movoop(Address dst, jobject obj);
1535
1536 void mov_metadata(Register dst, Metadata* obj);
1537 void mov_metadata(Address dst, Metadata* obj);
1538
1539 void movptr(ArrayAddress dst, Register src);
1540 // can this do an lea?
1541 void movptr(Register dst, ArrayAddress src);
1542
1543 void movptr(Register dst, Address src);
1544
1545 #ifdef _LP64
1546 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1547 #else
1548 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1549 #endif
1550
1551 void movptr(Register dst, intptr_t src);
1552 void movptr(Register dst, Register src);
1553 void movptr(Address dst, intptr_t src);
1554
1555 void movptr(Address dst, Register src);
1556
1557 void movptr(Register dst, RegisterOrConstant src) {
1558 if (src.is_constant()) movptr(dst, src.as_constant());
1559 else movptr(dst, src.as_register());
1560 }
1561
1562 #ifdef _LP64
1563 // Generally the next two are only used for moving NULL
1564 // Although there are situations in initializing the mark word where
1565 // they could be used. They are dangerous.
1566
1567 // They only exist on LP64 so that int32_t and intptr_t are not the same
1568 // and we have ambiguous declarations.
1569
1570 void movptr(Address dst, int32_t imm32);
1571 void movptr(Register dst, int32_t imm32);
1572 #endif // _LP64
1573
1574 // to avoid hiding movl
1575 void mov32(AddressLiteral dst, Register src);
1576 void mov32(Register dst, AddressLiteral src);
1577
1578 // to avoid hiding movb
1579 void movbyte(ArrayAddress dst, int src);
1580
1581 // Import other mov() methods from the parent class or else
1582 // they will be hidden by the following overriding declaration.
1583 using Assembler::movdl;
1584 using Assembler::movq;
1585 void movdl(XMMRegister dst, AddressLiteral src);
1586 void movq(XMMRegister dst, AddressLiteral src);
1587
1588 // Can push value or effective address
1589 void pushptr(AddressLiteral src);
1590
1591 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1592 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1593
1594 void pushoop(jobject obj);
1595 void pushklass(Metadata* obj);
1596
1597 // sign extend as need a l to ptr sized element
1598 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1599 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1600
1601 // C2 compiled method's prolog code.
1602 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1603
1604 // Add null checks for all value type arguments
1605 void null_check_value_args(Method* method);
1606
1607 // clear memory of size 'cnt' qwords, starting at 'base';
1608 // if 'is_large' is set, do not try to produce short loop
1609 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only);
1610
1611 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1612 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp);
1613
1614 #ifdef COMPILER2
1615 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1616 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1617
1618 // IndexOf strings.
1619 // Small strings are loaded through stack if they cross page boundary.
1620 void string_indexof(Register str1, Register str2,
1621 Register cnt1, Register cnt2,
1622 int int_cnt2, Register result,
1623 XMMRegister vec, Register tmp,
1624 int ae);
1625
1626 // IndexOf for constant substrings with size >= 8 elements
1627 // which don't need to be loaded through stack.
1628 void string_indexofC8(Register str1, Register str2,
1629 Register cnt1, Register cnt2,
1630 int int_cnt2, Register result,
1631 XMMRegister vec, Register tmp,
1632 int ae);
1633
1634 // Smallest code: we don't need to load through stack,
1635 // check string tail.
1636
1637 // helper function for string_compare
1638 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1639 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1640 Address::ScaleFactor scale2, Register index, int ae);
1641 // Compare strings.
1642 void string_compare(Register str1, Register str2,
1643 Register cnt1, Register cnt2, Register result,
1644 XMMRegister vec1, int ae);
1645
1646 // Search for Non-ASCII character (Negative byte value) in a byte array,
1647 // return true if it has any and false otherwise.
1648 void has_negatives(Register ary1, Register len,
1649 Register result, Register tmp1,
1650 XMMRegister vec1, XMMRegister vec2);
1651
1652 // Compare char[] or byte[] arrays.
1653 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1654 Register limit, Register result, Register chr,
1655 XMMRegister vec1, XMMRegister vec2, bool is_char);
1656
1657 #endif
1658
1659 // Fill primitive arrays
1660 void generate_fill(BasicType t, bool aligned,
1661 Register to, Register value, Register count,
1662 Register rtmp, XMMRegister xtmp);
1663
1664 void encode_iso_array(Register src, Register dst, Register len,
1665 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1666 XMMRegister tmp4, Register tmp5, Register result);
1667
1668 #ifdef _LP64
1669 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1670 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1671 Register y, Register y_idx, Register z,
1672 Register carry, Register product,
1673 Register idx, Register kdx);
1674 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1675 Register yz_idx, Register idx,
1676 Register carry, Register product, int offset);
1677 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1678 Register carry, Register carry2,
1679 Register idx, Register jdx,
1680 Register yz_idx1, Register yz_idx2,
1681 Register tmp, Register tmp3, Register tmp4);
1682 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1683 Register yz_idx, Register idx, Register jdx,
1684 Register carry, Register product,
1685 Register carry2);
1686 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1687 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1688 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1689 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1690 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1691 Register tmp2);
1692 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1693 Register rdxReg, Register raxReg);
1694 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1695 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1696 Register tmp3, Register tmp4);
1697 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1698 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1699
1700 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1701 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1702 Register raxReg);
1703 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1704 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1705 Register raxReg);
1706 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1707 Register result, Register tmp1, Register tmp2,
1708 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1709 #endif
1710
1711 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1712 void update_byte_crc32(Register crc, Register val, Register table);
1713 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1714 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1715 // Note on a naming convention:
1716 // Prefix w = register only used on a Westmere+ architecture
1717 // Prefix n = register only used on a Nehalem architecture
1718 #ifdef _LP64
1719 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1720 Register tmp1, Register tmp2, Register tmp3);
1721 #else
1722 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1723 Register tmp1, Register tmp2, Register tmp3,
1724 XMMRegister xtmp1, XMMRegister xtmp2);
1725 #endif
1726 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1727 Register in_out,
1728 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1729 XMMRegister w_xtmp2,
1730 Register tmp1,
1731 Register n_tmp2, Register n_tmp3);
1732 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1733 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1734 Register tmp1, Register tmp2,
1735 Register n_tmp3);
1736 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1737 Register in_out1, Register in_out2, Register in_out3,
1738 Register tmp1, Register tmp2, Register tmp3,
1739 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1740 Register tmp4, Register tmp5,
1741 Register n_tmp6);
1742 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1743 Register tmp1, Register tmp2, Register tmp3,
1744 Register tmp4, Register tmp5, Register tmp6,
1745 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1746 bool is_pclmulqdq_supported);
1747 // Fold 128-bit data chunk
1748 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1749 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1750 // Fold 8-bit data
1751 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1752 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1753 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1754
1755 // Compress char[] array to byte[].
1756 void char_array_compress(Register src, Register dst, Register len,
1757 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1758 XMMRegister tmp4, Register tmp5, Register result);
1759
1760 // Inflate byte[] array to char[].
1761 void byte_array_inflate(Register src, Register dst, Register len,
1762 XMMRegister tmp1, Register tmp2);
1763
1764 };
1765
1766 /**
1767 * class SkipIfEqual:
1768 *
1769 * Instantiating this class will result in assembly code being output that will
1770 * jump around any code emitted between the creation of the instance and it's
1771 * automatic destruction at the end of a scope block, depending on the value of
1772 * the flag passed to the constructor, which will be checked at run-time.
1773 */
1774 class SkipIfEqual {
1775 private:
1776 MacroAssembler* _masm;
1777 Label _label;
1778
1779 public:
1780 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1781 ~SkipIfEqual();
1782 };
1783
1784 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP