1 /* 2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP 26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP 27 28 #include "asm/assembler.hpp" 29 #include "utilities/macros.hpp" 30 #include "runtime/rtmLocking.hpp" 31 32 // MacroAssembler extends Assembler by frequently used macros. 33 // 34 // Instructions for which a 'better' code sequence exists depending 35 // on arguments should also go in here. 36 37 class MacroAssembler: public Assembler { 38 friend class LIR_Assembler; 39 friend class Runtime1; // as_Address() 40 41 public: 42 // Support for VM calls 43 // 44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 45 // may customize this version by overriding it for its purposes (e.g., to save/restore 46 // additional registers when doing a VM call). 47 48 virtual void call_VM_leaf_base( 49 address entry_point, // the entry point 50 int number_of_arguments // the number of arguments to pop after the call 51 ); 52 53 protected: 54 // This is the base routine called by the different versions of call_VM. The interpreter 55 // may customize this version by overriding it for its purposes (e.g., to save/restore 56 // additional registers when doing a VM call). 57 // 58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 59 // returns the register which contains the thread upon return. If a thread register has been 60 // specified, the return value will correspond to that register. If no last_java_sp is specified 61 // (noreg) than rsp will be used instead. 62 virtual void call_VM_base( // returns the register containing the thread upon return 63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 64 Register java_thread, // the thread if computed before ; use noreg otherwise 65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 66 address entry_point, // the entry point 67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 68 bool check_exceptions // whether to check for pending exceptions after return 69 ); 70 71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 72 73 // helpers for FPU flag access 74 // tmp is a temporary register, if none is available use noreg 75 void save_rax (Register tmp); 76 void restore_rax(Register tmp); 77 78 public: 79 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 80 81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 82 // The implementation is only non-empty for the InterpreterMacroAssembler, 83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 84 virtual void check_and_handle_popframe(Register java_thread); 85 virtual void check_and_handle_earlyret(Register java_thread); 86 87 Address as_Address(AddressLiteral adr); 88 Address as_Address(ArrayAddress adr); 89 90 // Support for NULL-checks 91 // 92 // Generates code that causes a NULL OS exception if the content of reg is NULL. 93 // If the accessed location is M[reg + offset] and the offset is known, provide the 94 // offset. No explicit code generation is needed if the offset is within a certain 95 // range (0 <= offset <= page_size). 96 97 void null_check(Register reg, int offset = -1); 98 static bool needs_explicit_null_check(intptr_t offset); 99 100 void test_klass_is_value(Register klass, Register temp_reg, Label& is_value); 101 102 void test_field_is_flattenable(Register flags, Register temp_reg, Label& is_flattenable); 103 void test_field_is_not_flattenable(Register flags, Register temp_reg, Label& notFlattenable); 104 void test_field_is_flattened(Register flags, Register temp_reg, Label& is_flattened); 105 106 // Check klass/oops is flat value type array (oop->_klass->_layout_helper & vt_bit) 107 void test_flat_array_klass(Register klass, Register temp_reg, Label& is_flat_array); 108 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array); 109 110 // Required platform-specific helpers for Label::patch_instructions. 111 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 112 void pd_patch_instruction(address branch, address target, const char* file, int line) { 113 unsigned char op = branch[0]; 114 assert(op == 0xE8 /* call */ || 115 op == 0xE9 /* jmp */ || 116 op == 0xEB /* short jmp */ || 117 (op & 0xF0) == 0x70 /* short jcc */ || 118 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ || 119 op == 0xC7 && branch[1] == 0xF8 /* xbegin */, 120 "Invalid opcode at patch point"); 121 122 if (op == 0xEB || (op & 0xF0) == 0x70) { 123 // short offset operators (jmp and jcc) 124 char* disp = (char*) &branch[1]; 125 int imm8 = target - (address) &disp[1]; 126 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line); 127 *disp = imm8; 128 } else { 129 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1]; 130 int imm32 = target - (address) &disp[1]; 131 *disp = imm32; 132 } 133 } 134 135 // The following 4 methods return the offset of the appropriate move instruction 136 137 // Support for fast byte/short loading with zero extension (depending on particular CPU) 138 int load_unsigned_byte(Register dst, Address src); 139 int load_unsigned_short(Register dst, Address src); 140 141 // Support for fast byte/short loading with sign extension (depending on particular CPU) 142 int load_signed_byte(Register dst, Address src); 143 int load_signed_short(Register dst, Address src); 144 145 // Support for sign-extension (hi:lo = extend_sign(lo)) 146 void extend_sign(Register hi, Register lo); 147 148 // Load and store values by size and signed-ness 149 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 150 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 151 152 // Support for inc/dec with optimal instruction selection depending on value 153 154 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 155 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 156 157 void decrementl(Address dst, int value = 1); 158 void decrementl(Register reg, int value = 1); 159 160 void decrementq(Register reg, int value = 1); 161 void decrementq(Address dst, int value = 1); 162 163 void incrementl(Address dst, int value = 1); 164 void incrementl(Register reg, int value = 1); 165 166 void incrementq(Register reg, int value = 1); 167 void incrementq(Address dst, int value = 1); 168 169 // special instructions for EVEX 170 void setvectmask(Register dst, Register src); 171 void restorevectmask(); 172 173 // Support optimal SSE move instructions. 174 void movflt(XMMRegister dst, XMMRegister src) { 175 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 176 else { movss (dst, src); return; } 177 } 178 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 179 void movflt(XMMRegister dst, AddressLiteral src); 180 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 181 182 void movdbl(XMMRegister dst, XMMRegister src) { 183 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 184 else { movsd (dst, src); return; } 185 } 186 187 void movdbl(XMMRegister dst, AddressLiteral src); 188 189 void movdbl(XMMRegister dst, Address src) { 190 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 191 else { movlpd(dst, src); return; } 192 } 193 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 194 195 void incrementl(AddressLiteral dst); 196 void incrementl(ArrayAddress dst); 197 198 void incrementq(AddressLiteral dst); 199 200 // Alignment 201 void align(int modulus); 202 void align(int modulus, int target); 203 204 // A 5 byte nop that is safe for patching (see patch_verified_entry) 205 void fat_nop(); 206 207 // Stack frame creation/removal 208 void enter(); 209 void leave(); 210 211 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 212 // The pointer will be loaded into the thread register. 213 void get_thread(Register thread); 214 215 216 // Support for VM calls 217 // 218 // It is imperative that all calls into the VM are handled via the call_VM macros. 219 // They make sure that the stack linkage is setup correctly. call_VM's correspond 220 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 221 222 223 void call_VM(Register oop_result, 224 address entry_point, 225 bool check_exceptions = true); 226 void call_VM(Register oop_result, 227 address entry_point, 228 Register arg_1, 229 bool check_exceptions = true); 230 void call_VM(Register oop_result, 231 address entry_point, 232 Register arg_1, Register arg_2, 233 bool check_exceptions = true); 234 void call_VM(Register oop_result, 235 address entry_point, 236 Register arg_1, Register arg_2, Register arg_3, 237 bool check_exceptions = true); 238 239 // Overloadings with last_Java_sp 240 void call_VM(Register oop_result, 241 Register last_java_sp, 242 address entry_point, 243 int number_of_arguments = 0, 244 bool check_exceptions = true); 245 void call_VM(Register oop_result, 246 Register last_java_sp, 247 address entry_point, 248 Register arg_1, bool 249 check_exceptions = true); 250 void call_VM(Register oop_result, 251 Register last_java_sp, 252 address entry_point, 253 Register arg_1, Register arg_2, 254 bool check_exceptions = true); 255 void call_VM(Register oop_result, 256 Register last_java_sp, 257 address entry_point, 258 Register arg_1, Register arg_2, Register arg_3, 259 bool check_exceptions = true); 260 261 void get_vm_result (Register oop_result, Register thread); 262 void get_vm_result_2(Register metadata_result, Register thread); 263 264 // These always tightly bind to MacroAssembler::call_VM_base 265 // bypassing the virtual implementation 266 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 267 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 268 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 269 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 270 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 271 272 void call_VM_leaf0(address entry_point); 273 void call_VM_leaf(address entry_point, 274 int number_of_arguments = 0); 275 void call_VM_leaf(address entry_point, 276 Register arg_1); 277 void call_VM_leaf(address entry_point, 278 Register arg_1, Register arg_2); 279 void call_VM_leaf(address entry_point, 280 Register arg_1, Register arg_2, Register arg_3); 281 282 // These always tightly bind to MacroAssembler::call_VM_leaf_base 283 // bypassing the virtual implementation 284 void super_call_VM_leaf(address entry_point); 285 void super_call_VM_leaf(address entry_point, Register arg_1); 286 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 287 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 288 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 289 290 // last Java Frame (fills frame anchor) 291 void set_last_Java_frame(Register thread, 292 Register last_java_sp, 293 Register last_java_fp, 294 address last_java_pc); 295 296 // thread in the default location (r15_thread on 64bit) 297 void set_last_Java_frame(Register last_java_sp, 298 Register last_java_fp, 299 address last_java_pc); 300 301 void reset_last_Java_frame(Register thread, bool clear_fp); 302 303 // thread in the default location (r15_thread on 64bit) 304 void reset_last_Java_frame(bool clear_fp); 305 306 // jobjects 307 void clear_jweak_tag(Register possibly_jweak); 308 void resolve_jobject(Register value, Register thread, Register tmp); 309 310 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 311 void c2bool(Register x); 312 313 // C++ bool manipulation 314 315 void movbool(Register dst, Address src); 316 void movbool(Address dst, bool boolconst); 317 void movbool(Address dst, Register src); 318 void testbool(Register dst); 319 320 void resolve_oop_handle(Register result, Register tmp = rscratch2); 321 void load_mirror(Register mirror, Register method, Register tmp = rscratch2); 322 323 // oop manipulations 324 void load_klass(Register dst, Register src); 325 void store_klass(Register dst, Register src); 326 327 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 328 Register tmp1, Register thread_tmp); 329 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src, 330 Register tmp1, Register tmp2); 331 332 // Resolves obj access. Result is placed in the same register. 333 // All other registers are preserved. 334 void resolve(DecoratorSet decorators, Register obj); 335 336 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg, 337 Register thread_tmp = noreg, DecoratorSet decorators = 0); 338 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg, 339 Register thread_tmp = noreg, DecoratorSet decorators = 0); 340 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg, 341 Register tmp2 = noreg, DecoratorSet decorators = 0); 342 343 // Used for storing NULL. All other oop constants should be 344 // stored using routines that take a jobject. 345 void store_heap_oop_null(Address dst); 346 347 void load_prototype_header(Register dst, Register src); 348 349 #ifdef _LP64 350 void store_klass_gap(Register dst, Register src); 351 352 // This dummy is to prevent a call to store_heap_oop from 353 // converting a zero (like NULL) into a Register by giving 354 // the compiler two choices it can't resolve 355 356 void store_heap_oop(Address dst, void* dummy); 357 358 void encode_heap_oop(Register r); 359 void decode_heap_oop(Register r); 360 void encode_heap_oop_not_null(Register r); 361 void decode_heap_oop_not_null(Register r); 362 void encode_heap_oop_not_null(Register dst, Register src); 363 void decode_heap_oop_not_null(Register dst, Register src); 364 365 void set_narrow_oop(Register dst, jobject obj); 366 void set_narrow_oop(Address dst, jobject obj); 367 void cmp_narrow_oop(Register dst, jobject obj); 368 void cmp_narrow_oop(Address dst, jobject obj); 369 370 void encode_klass_not_null(Register r); 371 void decode_klass_not_null(Register r); 372 void encode_klass_not_null(Register dst, Register src); 373 void decode_klass_not_null(Register dst, Register src); 374 void set_narrow_klass(Register dst, Klass* k); 375 void set_narrow_klass(Address dst, Klass* k); 376 void cmp_narrow_klass(Register dst, Klass* k); 377 void cmp_narrow_klass(Address dst, Klass* k); 378 379 // Returns the byte size of the instructions generated by decode_klass_not_null() 380 // when compressed klass pointers are being used. 381 static int instr_size_for_decode_klass_not_null(); 382 383 // if heap base register is used - reinit it with the correct value 384 void reinit_heapbase(); 385 386 DEBUG_ONLY(void verify_heapbase(const char* msg);) 387 388 #endif // _LP64 389 390 // Int division/remainder for Java 391 // (as idivl, but checks for special case as described in JVM spec.) 392 // returns idivl instruction offset for implicit exception handling 393 int corrected_idivl(Register reg); 394 395 // Long division/remainder for Java 396 // (as idivq, but checks for special case as described in JVM spec.) 397 // returns idivq instruction offset for implicit exception handling 398 int corrected_idivq(Register reg); 399 400 void int3(); 401 402 // Long operation macros for a 32bit cpu 403 // Long negation for Java 404 void lneg(Register hi, Register lo); 405 406 // Long multiplication for Java 407 // (destroys contents of eax, ebx, ecx and edx) 408 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 409 410 // Long shifts for Java 411 // (semantics as described in JVM spec.) 412 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 413 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 414 415 // Long compare for Java 416 // (semantics as described in JVM spec.) 417 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 418 419 420 // misc 421 422 // Sign extension 423 void sign_extend_short(Register reg); 424 void sign_extend_byte(Register reg); 425 426 // Division by power of 2, rounding towards 0 427 void division_with_shift(Register reg, int shift_value); 428 429 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 430 // 431 // CF (corresponds to C0) if x < y 432 // PF (corresponds to C2) if unordered 433 // ZF (corresponds to C3) if x = y 434 // 435 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 436 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 437 void fcmp(Register tmp); 438 // Variant of the above which allows y to be further down the stack 439 // and which only pops x and y if specified. If pop_right is 440 // specified then pop_left must also be specified. 441 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 442 443 // Floating-point comparison for Java 444 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 445 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 446 // (semantics as described in JVM spec.) 447 void fcmp2int(Register dst, bool unordered_is_less); 448 // Variant of the above which allows y to be further down the stack 449 // and which only pops x and y if specified. If pop_right is 450 // specified then pop_left must also be specified. 451 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 452 453 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 454 // tmp is a temporary register, if none is available use noreg 455 void fremr(Register tmp); 456 457 // dst = c = a * b + c 458 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c); 459 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c); 460 461 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len); 462 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len); 463 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len); 464 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len); 465 466 467 // same as fcmp2int, but using SSE2 468 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 469 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 470 471 // branch to L if FPU flag C2 is set/not set 472 // tmp is a temporary register, if none is available use noreg 473 void jC2 (Register tmp, Label& L); 474 void jnC2(Register tmp, Label& L); 475 476 // Pop ST (ffree & fincstp combined) 477 void fpop(); 478 479 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into 480 // register xmm0. Otherwise, the value is loaded onto the FPU stack. 481 void load_float(Address src); 482 483 // Store float value to 'address'. If UseSSE >= 1, the value is stored 484 // from register xmm0. Otherwise, the value is stored from the FPU stack. 485 void store_float(Address dst); 486 487 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into 488 // register xmm0. Otherwise, the value is loaded onto the FPU stack. 489 void load_double(Address src); 490 491 // Store double value to 'address'. If UseSSE >= 2, the value is stored 492 // from register xmm0. Otherwise, the value is stored from the FPU stack. 493 void store_double(Address dst); 494 495 // Save/restore ZMM (512bit) register on stack. 496 void push_zmm(XMMRegister reg); 497 void pop_zmm(XMMRegister reg); 498 499 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 500 void push_fTOS(); 501 502 // pops double TOS element from CPU stack and pushes on FPU stack 503 void pop_fTOS(); 504 505 void empty_FPU_stack(); 506 507 void push_IU_state(); 508 void pop_IU_state(); 509 510 void push_FPU_state(); 511 void pop_FPU_state(); 512 513 void push_CPU_state(); 514 void pop_CPU_state(); 515 516 // Round up to a power of two 517 void round_to(Register reg, int modulus); 518 519 // Callee saved registers handling 520 void push_callee_saved_registers(); 521 void pop_callee_saved_registers(); 522 523 // allocation 524 void eden_allocate( 525 Register thread, // Current thread 526 Register obj, // result: pointer to object after successful allocation 527 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 528 int con_size_in_bytes, // object size in bytes if known at compile time 529 Register t1, // temp register 530 Label& slow_case // continuation point if fast allocation fails 531 ); 532 void tlab_allocate( 533 Register thread, // Current thread 534 Register obj, // result: pointer to object after successful allocation 535 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 536 int con_size_in_bytes, // object size in bytes if known at compile time 537 Register t1, // temp register 538 Register t2, // temp register 539 Label& slow_case // continuation point if fast allocation fails 540 ); 541 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp); 542 543 // interface method calling 544 void lookup_interface_method(Register recv_klass, 545 Register intf_klass, 546 RegisterOrConstant itable_index, 547 Register method_result, 548 Register scan_temp, 549 Label& no_such_interface, 550 bool return_method = true); 551 552 // virtual method calling 553 void lookup_virtual_method(Register recv_klass, 554 RegisterOrConstant vtable_index, 555 Register method_result); 556 557 // Test sub_klass against super_klass, with fast and slow paths. 558 559 // The fast path produces a tri-state answer: yes / no / maybe-slow. 560 // One of the three labels can be NULL, meaning take the fall-through. 561 // If super_check_offset is -1, the value is loaded up from super_klass. 562 // No registers are killed, except temp_reg. 563 void check_klass_subtype_fast_path(Register sub_klass, 564 Register super_klass, 565 Register temp_reg, 566 Label* L_success, 567 Label* L_failure, 568 Label* L_slow_path, 569 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 570 571 // The rest of the type check; must be wired to a corresponding fast path. 572 // It does not repeat the fast path logic, so don't use it standalone. 573 // The temp_reg and temp2_reg can be noreg, if no temps are available. 574 // Updates the sub's secondary super cache as necessary. 575 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 576 void check_klass_subtype_slow_path(Register sub_klass, 577 Register super_klass, 578 Register temp_reg, 579 Register temp2_reg, 580 Label* L_success, 581 Label* L_failure, 582 bool set_cond_codes = false); 583 584 // Simplified, combined version, good for typical uses. 585 // Falls through on failure. 586 void check_klass_subtype(Register sub_klass, 587 Register super_klass, 588 Register temp_reg, 589 Label& L_success); 590 591 // method handles (JSR 292) 592 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 593 594 //---- 595 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 596 597 // Debugging 598 599 // only if +VerifyOops 600 // TODO: Make these macros with file and line like sparc version! 601 void verify_oop(Register reg, const char* s = "broken oop"); 602 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 603 604 // TODO: verify method and klass metadata (compare against vptr?) 605 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 606 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 607 608 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 609 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 610 611 // only if +VerifyFPU 612 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 613 614 // Verify or restore cpu control state after JNI call 615 void restore_cpu_control_state_after_jni(); 616 617 // prints msg, dumps registers and stops execution 618 void stop(const char* msg); 619 620 // prints msg and continues 621 void warn(const char* msg); 622 623 // dumps registers and other state 624 void print_state(); 625 626 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 627 static void debug64(char* msg, int64_t pc, int64_t regs[]); 628 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); 629 static void print_state64(int64_t pc, int64_t regs[]); 630 631 void os_breakpoint(); 632 633 void untested() { stop("untested"); } 634 635 void unimplemented(const char* what = ""); 636 637 void should_not_reach_here() { stop("should not reach here"); } 638 639 void print_CPU_state(); 640 641 // Stack overflow checking 642 void bang_stack_with_offset(int offset) { 643 // stack grows down, caller passes positive offset 644 assert(offset > 0, "must bang with negative offset"); 645 movl(Address(rsp, (-offset)), rax); 646 } 647 648 // Writes to stack successive pages until offset reached to check for 649 // stack overflow + shadow pages. Also, clobbers tmp 650 void bang_stack_size(Register size, Register tmp); 651 652 // Check for reserved stack access in method being exited (for JIT) 653 void reserved_stack_check(); 654 655 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 656 Register tmp, 657 int offset); 658 659 // Support for serializing memory accesses between threads 660 void serialize_memory(Register thread, Register tmp); 661 662 // If thread_reg is != noreg the code assumes the register passed contains 663 // the thread (required on 64 bit). 664 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg); 665 666 void verify_tlab(); 667 668 // Biased locking support 669 // lock_reg and obj_reg must be loaded up with the appropriate values. 670 // swap_reg must be rax, and is killed. 671 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 672 // be killed; if not supplied, push/pop will be used internally to 673 // allocate a temporary (inefficient, avoid if possible). 674 // Optional slow case is for implementations (interpreter and C1) which branch to 675 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 676 // Returns offset of first potentially-faulting instruction for null 677 // check info (currently consumed only by C1). If 678 // swap_reg_contains_mark is true then returns -1 as it is assumed 679 // the calling code has already passed any potential faults. 680 int biased_locking_enter(Register lock_reg, Register obj_reg, 681 Register swap_reg, Register tmp_reg, 682 bool swap_reg_contains_mark, 683 Label& done, Label* slow_case = NULL, 684 BiasedLockingCounters* counters = NULL); 685 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 686 #ifdef COMPILER2 687 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file. 688 // See full desription in macroAssembler_x86.cpp. 689 void fast_lock(Register obj, Register box, Register tmp, 690 Register scr, Register cx1, Register cx2, 691 BiasedLockingCounters* counters, 692 RTMLockingCounters* rtm_counters, 693 RTMLockingCounters* stack_rtm_counters, 694 Metadata* method_data, 695 bool use_rtm, bool profile_rtm); 696 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm); 697 #if INCLUDE_RTM_OPT 698 void rtm_counters_update(Register abort_status, Register rtm_counters); 699 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel); 700 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg, 701 RTMLockingCounters* rtm_counters, 702 Metadata* method_data); 703 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg, 704 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm); 705 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel); 706 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel); 707 void rtm_stack_locking(Register obj, Register tmp, Register scr, 708 Register retry_on_abort_count, 709 RTMLockingCounters* stack_rtm_counters, 710 Metadata* method_data, bool profile_rtm, 711 Label& DONE_LABEL, Label& IsInflated); 712 void rtm_inflated_locking(Register obj, Register box, Register tmp, 713 Register scr, Register retry_on_busy_count, 714 Register retry_on_abort_count, 715 RTMLockingCounters* rtm_counters, 716 Metadata* method_data, bool profile_rtm, 717 Label& DONE_LABEL); 718 #endif 719 #endif 720 721 Condition negate_condition(Condition cond); 722 723 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 724 // operands. In general the names are modified to avoid hiding the instruction in Assembler 725 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 726 // here in MacroAssembler. The major exception to this rule is call 727 728 // Arithmetics 729 730 731 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 732 void addptr(Address dst, Register src); 733 734 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 735 void addptr(Register dst, int32_t src); 736 void addptr(Register dst, Register src); 737 void addptr(Register dst, RegisterOrConstant src) { 738 if (src.is_constant()) addptr(dst, (int) src.as_constant()); 739 else addptr(dst, src.as_register()); 740 } 741 742 void andptr(Register dst, int32_t src); 743 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 744 745 void cmp8(AddressLiteral src1, int imm); 746 747 // renamed to drag out the casting of address to int32_t/intptr_t 748 void cmp32(Register src1, int32_t imm); 749 750 void cmp32(AddressLiteral src1, int32_t imm); 751 // compare reg - mem, or reg - &mem 752 void cmp32(Register src1, AddressLiteral src2); 753 754 void cmp32(Register src1, Address src2); 755 756 #ifndef _LP64 757 void cmpklass(Address dst, Metadata* obj); 758 void cmpklass(Register dst, Metadata* obj); 759 void cmpoop(Address dst, jobject obj); 760 void cmpoop_raw(Address dst, jobject obj); 761 #endif // _LP64 762 763 void cmpoop(Register src1, Register src2); 764 void cmpoop(Register src1, Address src2); 765 void cmpoop(Register dst, jobject obj); 766 void cmpoop_raw(Register dst, jobject obj); 767 768 // NOTE src2 must be the lval. This is NOT an mem-mem compare 769 void cmpptr(Address src1, AddressLiteral src2); 770 771 void cmpptr(Register src1, AddressLiteral src2); 772 773 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 774 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 775 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 776 777 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 778 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 779 780 // cmp64 to avoild hiding cmpq 781 void cmp64(Register src1, AddressLiteral src); 782 783 void cmpxchgptr(Register reg, Address adr); 784 785 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 786 787 788 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 789 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); } 790 791 792 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 793 794 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 795 796 void shlptr(Register dst, int32_t shift); 797 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 798 799 void shrptr(Register dst, int32_t shift); 800 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 801 802 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 803 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 804 805 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 806 807 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 808 void subptr(Register dst, int32_t src); 809 // Force generation of a 4 byte immediate value even if it fits into 8bit 810 void subptr_imm32(Register dst, int32_t src); 811 void subptr(Register dst, Register src); 812 void subptr(Register dst, RegisterOrConstant src) { 813 if (src.is_constant()) subptr(dst, (int) src.as_constant()); 814 else subptr(dst, src.as_register()); 815 } 816 817 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 818 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 819 820 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 821 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 822 823 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 824 825 826 827 // Helper functions for statistics gathering. 828 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 829 void cond_inc32(Condition cond, AddressLiteral counter_addr); 830 // Unconditional atomic increment. 831 void atomic_incl(Address counter_addr); 832 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1); 833 #ifdef _LP64 834 void atomic_incq(Address counter_addr); 835 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1); 836 #endif 837 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; } 838 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; } 839 840 void lea(Register dst, AddressLiteral adr); 841 void lea(Address dst, AddressLiteral adr); 842 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 843 844 void leal32(Register dst, Address src) { leal(dst, src); } 845 846 // Import other testl() methods from the parent class or else 847 // they will be hidden by the following overriding declaration. 848 using Assembler::testl; 849 void testl(Register dst, AddressLiteral src); 850 851 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 852 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 853 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 854 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); } 855 856 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 857 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); } 858 void testptr(Register src1, Register src2); 859 860 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 861 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 862 863 // Calls 864 865 void call(Label& L, relocInfo::relocType rtype); 866 void call(Register entry); 867 868 // NOTE: this call transfers to the effective address of entry NOT 869 // the address contained by entry. This is because this is more natural 870 // for jumps/calls. 871 void call(AddressLiteral entry); 872 873 // Emit the CompiledIC call idiom 874 void ic_call(address entry, jint method_index = 0); 875 876 // Jumps 877 878 // NOTE: these jumps tranfer to the effective address of dst NOT 879 // the address contained by dst. This is because this is more natural 880 // for jumps/calls. 881 void jump(AddressLiteral dst); 882 void jump_cc(Condition cc, AddressLiteral dst); 883 884 // 32bit can do a case table jump in one instruction but we no longer allow the base 885 // to be installed in the Address class. This jump will tranfers to the address 886 // contained in the location described by entry (not the address of entry) 887 void jump(ArrayAddress entry); 888 889 // Floating 890 891 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 892 void andpd(XMMRegister dst, AddressLiteral src); 893 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); } 894 895 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } 896 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } 897 void andps(XMMRegister dst, AddressLiteral src); 898 899 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } 900 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 901 void comiss(XMMRegister dst, AddressLiteral src); 902 903 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } 904 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 905 void comisd(XMMRegister dst, AddressLiteral src); 906 907 void fadd_s(Address src) { Assembler::fadd_s(src); } 908 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 909 910 void fldcw(Address src) { Assembler::fldcw(src); } 911 void fldcw(AddressLiteral src); 912 913 void fld_s(int index) { Assembler::fld_s(index); } 914 void fld_s(Address src) { Assembler::fld_s(src); } 915 void fld_s(AddressLiteral src); 916 917 void fld_d(Address src) { Assembler::fld_d(src); } 918 void fld_d(AddressLiteral src); 919 920 void fld_x(Address src) { Assembler::fld_x(src); } 921 void fld_x(AddressLiteral src); 922 923 void fmul_s(Address src) { Assembler::fmul_s(src); } 924 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 925 926 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 927 void ldmxcsr(AddressLiteral src); 928 929 #ifdef _LP64 930 private: 931 void sha256_AVX2_one_round_compute( 932 Register reg_old_h, 933 Register reg_a, 934 Register reg_b, 935 Register reg_c, 936 Register reg_d, 937 Register reg_e, 938 Register reg_f, 939 Register reg_g, 940 Register reg_h, 941 int iter); 942 void sha256_AVX2_four_rounds_compute_first(int start); 943 void sha256_AVX2_four_rounds_compute_last(int start); 944 void sha256_AVX2_one_round_and_sched( 945 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */ 946 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */ 947 XMMRegister xmm_2, /* ymm6 */ 948 XMMRegister xmm_3, /* ymm7 */ 949 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */ 950 Register reg_b, /* ebx */ /* full cycle is 8 iterations */ 951 Register reg_c, /* edi */ 952 Register reg_d, /* esi */ 953 Register reg_e, /* r8d */ 954 Register reg_f, /* r9d */ 955 Register reg_g, /* r10d */ 956 Register reg_h, /* r11d */ 957 int iter); 958 959 void addm(int disp, Register r1, Register r2); 960 961 public: 962 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 963 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 964 Register buf, Register state, Register ofs, Register limit, Register rsp, 965 bool multi_block, XMMRegister shuf_mask); 966 #endif 967 968 #ifdef _LP64 969 private: 970 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d, 971 Register e, Register f, Register g, Register h, int iteration); 972 973 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 974 Register a, Register b, Register c, Register d, Register e, Register f, 975 Register g, Register h, int iteration); 976 977 void addmq(int disp, Register r1, Register r2); 978 public: 979 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 980 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 981 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block, 982 XMMRegister shuf_mask); 983 #endif 984 985 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0, 986 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask, 987 Register buf, Register state, Register ofs, Register limit, Register rsp, 988 bool multi_block); 989 990 #ifdef _LP64 991 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 992 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 993 Register buf, Register state, Register ofs, Register limit, Register rsp, 994 bool multi_block, XMMRegister shuf_mask); 995 #else 996 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 997 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 998 Register buf, Register state, Register ofs, Register limit, Register rsp, 999 bool multi_block); 1000 #endif 1001 1002 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1003 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1004 Register rax, Register rcx, Register rdx, Register tmp); 1005 1006 #ifdef _LP64 1007 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1008 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1009 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2); 1010 1011 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1012 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1013 Register rax, Register rcx, Register rdx, Register r11); 1014 1015 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, 1016 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx, 1017 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4); 1018 1019 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1020 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1021 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2, 1022 Register tmp3, Register tmp4); 1023 1024 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1025 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1026 Register rax, Register rcx, Register rdx, Register tmp1, 1027 Register tmp2, Register tmp3, Register tmp4); 1028 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1029 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1030 Register rax, Register rcx, Register rdx, Register tmp1, 1031 Register tmp2, Register tmp3, Register tmp4); 1032 #else 1033 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1034 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1035 Register rax, Register rcx, Register rdx, Register tmp1); 1036 1037 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1038 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1039 Register rax, Register rcx, Register rdx, Register tmp); 1040 1041 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, 1042 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx, 1043 Register rdx, Register tmp); 1044 1045 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1046 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1047 Register rax, Register rbx, Register rdx); 1048 1049 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1050 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1051 Register rax, Register rcx, Register rdx, Register tmp); 1052 1053 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx, 1054 Register edx, Register ebx, Register esi, Register edi, 1055 Register ebp, Register esp); 1056 1057 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx, 1058 Register esi, Register edi, Register ebp, Register esp); 1059 1060 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx, 1061 Register edx, Register ebx, Register esi, Register edi, 1062 Register ebp, Register esp); 1063 1064 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1065 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1066 Register rax, Register rcx, Register rdx, Register tmp); 1067 #endif 1068 1069 void increase_precision(); 1070 void restore_precision(); 1071 1072 private: 1073 1074 // these are private because users should be doing movflt/movdbl 1075 1076 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 1077 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 1078 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 1079 void movss(XMMRegister dst, AddressLiteral src); 1080 1081 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 1082 void movlpd(XMMRegister dst, AddressLiteral src); 1083 1084 public: 1085 1086 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } 1087 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 1088 void addsd(XMMRegister dst, AddressLiteral src); 1089 1090 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } 1091 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 1092 void addss(XMMRegister dst, AddressLiteral src); 1093 1094 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); } 1095 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); } 1096 void addpd(XMMRegister dst, AddressLiteral src); 1097 1098 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } 1099 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 1100 void divsd(XMMRegister dst, AddressLiteral src); 1101 1102 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } 1103 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 1104 void divss(XMMRegister dst, AddressLiteral src); 1105 1106 // Move Unaligned Double Quadword 1107 void movdqu(Address dst, XMMRegister src); 1108 void movdqu(XMMRegister dst, Address src); 1109 void movdqu(XMMRegister dst, XMMRegister src); 1110 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1); 1111 // AVX Unaligned forms 1112 void vmovdqu(Address dst, XMMRegister src); 1113 void vmovdqu(XMMRegister dst, Address src); 1114 void vmovdqu(XMMRegister dst, XMMRegister src); 1115 void vmovdqu(XMMRegister dst, AddressLiteral src); 1116 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); } 1117 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); } 1118 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); } 1119 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch); 1120 1121 // Move Aligned Double Quadword 1122 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); } 1123 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); } 1124 void movdqa(XMMRegister dst, AddressLiteral src); 1125 1126 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 1127 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 1128 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 1129 void movsd(XMMRegister dst, AddressLiteral src); 1130 1131 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); } 1132 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); } 1133 void mulpd(XMMRegister dst, AddressLiteral src); 1134 1135 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } 1136 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 1137 void mulsd(XMMRegister dst, AddressLiteral src); 1138 1139 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } 1140 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 1141 void mulss(XMMRegister dst, AddressLiteral src); 1142 1143 // Carry-Less Multiplication Quadword 1144 void pclmulldq(XMMRegister dst, XMMRegister src) { 1145 // 0x00 - multiply lower 64 bits [0:63] 1146 Assembler::pclmulqdq(dst, src, 0x00); 1147 } 1148 void pclmulhdq(XMMRegister dst, XMMRegister src) { 1149 // 0x11 - multiply upper 64 bits [64:127] 1150 Assembler::pclmulqdq(dst, src, 0x11); 1151 } 1152 1153 void pcmpeqb(XMMRegister dst, XMMRegister src); 1154 void pcmpeqw(XMMRegister dst, XMMRegister src); 1155 1156 void pcmpestri(XMMRegister dst, Address src, int imm8); 1157 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8); 1158 1159 void pmovzxbw(XMMRegister dst, XMMRegister src); 1160 void pmovzxbw(XMMRegister dst, Address src); 1161 1162 void pmovmskb(Register dst, XMMRegister src); 1163 1164 void ptest(XMMRegister dst, XMMRegister src); 1165 1166 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } 1167 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 1168 void sqrtsd(XMMRegister dst, AddressLiteral src); 1169 1170 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } 1171 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 1172 void sqrtss(XMMRegister dst, AddressLiteral src); 1173 1174 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } 1175 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 1176 void subsd(XMMRegister dst, AddressLiteral src); 1177 1178 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } 1179 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 1180 void subss(XMMRegister dst, AddressLiteral src); 1181 1182 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 1183 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 1184 void ucomiss(XMMRegister dst, AddressLiteral src); 1185 1186 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 1187 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 1188 void ucomisd(XMMRegister dst, AddressLiteral src); 1189 1190 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 1191 void xorpd(XMMRegister dst, XMMRegister src); 1192 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 1193 void xorpd(XMMRegister dst, AddressLiteral src); 1194 1195 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 1196 void xorps(XMMRegister dst, XMMRegister src); 1197 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 1198 void xorps(XMMRegister dst, AddressLiteral src); 1199 1200 // Shuffle Bytes 1201 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } 1202 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); } 1203 void pshufb(XMMRegister dst, AddressLiteral src); 1204 // AVX 3-operands instructions 1205 1206 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } 1207 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } 1208 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1209 1210 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } 1211 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 1212 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1213 1214 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len); 1215 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len); 1216 1217 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1218 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1219 1220 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1221 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1222 1223 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); } 1224 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); } 1225 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1226 1227 void vpbroadcastw(XMMRegister dst, XMMRegister src); 1228 1229 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1230 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1231 1232 void vpmovzxbw(XMMRegister dst, Address src, int vector_len); 1233 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); } 1234 1235 void vpmovmskb(Register dst, XMMRegister src); 1236 1237 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1238 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1239 1240 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1241 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1242 1243 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1244 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1245 1246 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); 1247 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); 1248 1249 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); 1250 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); 1251 1252 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); 1253 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); 1254 1255 void vptest(XMMRegister dst, XMMRegister src); 1256 1257 void punpcklbw(XMMRegister dst, XMMRegister src); 1258 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); } 1259 1260 void pshufd(XMMRegister dst, Address src, int mode); 1261 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); } 1262 1263 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1264 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); } 1265 1266 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } 1267 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } 1268 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1269 1270 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } 1271 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } 1272 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1273 1274 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } 1275 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 1276 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1277 1278 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } 1279 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } 1280 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1281 1282 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } 1283 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } 1284 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1285 1286 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } 1287 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } 1288 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1289 1290 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } 1291 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } 1292 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1293 1294 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } 1295 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } 1296 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1297 1298 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1299 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1300 1301 // AVX Vector instructions 1302 1303 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } 1304 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } 1305 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1306 1307 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } 1308 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } 1309 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1310 1311 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1312 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 1313 Assembler::vpxor(dst, nds, src, vector_len); 1314 else 1315 Assembler::vxorpd(dst, nds, src, vector_len); 1316 } 1317 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 1318 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 1319 Assembler::vpxor(dst, nds, src, vector_len); 1320 else 1321 Assembler::vxorpd(dst, nds, src, vector_len); 1322 } 1323 1324 // Simple version for AVX2 256bit vectors 1325 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } 1326 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } 1327 1328 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 1329 if (UseAVX > 2) { 1330 Assembler::vinserti32x4(dst, dst, src, imm8); 1331 } else if (UseAVX > 1) { 1332 // vinserti128 is available only in AVX2 1333 Assembler::vinserti128(dst, nds, src, imm8); 1334 } else { 1335 Assembler::vinsertf128(dst, nds, src, imm8); 1336 } 1337 } 1338 1339 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 1340 if (UseAVX > 2) { 1341 Assembler::vinserti32x4(dst, dst, src, imm8); 1342 } else if (UseAVX > 1) { 1343 // vinserti128 is available only in AVX2 1344 Assembler::vinserti128(dst, nds, src, imm8); 1345 } else { 1346 Assembler::vinsertf128(dst, nds, src, imm8); 1347 } 1348 } 1349 1350 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 1351 if (UseAVX > 2) { 1352 Assembler::vextracti32x4(dst, src, imm8); 1353 } else if (UseAVX > 1) { 1354 // vextracti128 is available only in AVX2 1355 Assembler::vextracti128(dst, src, imm8); 1356 } else { 1357 Assembler::vextractf128(dst, src, imm8); 1358 } 1359 } 1360 1361 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 1362 if (UseAVX > 2) { 1363 Assembler::vextracti32x4(dst, src, imm8); 1364 } else if (UseAVX > 1) { 1365 // vextracti128 is available only in AVX2 1366 Assembler::vextracti128(dst, src, imm8); 1367 } else { 1368 Assembler::vextractf128(dst, src, imm8); 1369 } 1370 } 1371 1372 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers 1373 void vinserti128_high(XMMRegister dst, XMMRegister src) { 1374 vinserti128(dst, dst, src, 1); 1375 } 1376 void vinserti128_high(XMMRegister dst, Address src) { 1377 vinserti128(dst, dst, src, 1); 1378 } 1379 void vextracti128_high(XMMRegister dst, XMMRegister src) { 1380 vextracti128(dst, src, 1); 1381 } 1382 void vextracti128_high(Address dst, XMMRegister src) { 1383 vextracti128(dst, src, 1); 1384 } 1385 1386 void vinsertf128_high(XMMRegister dst, XMMRegister src) { 1387 if (UseAVX > 2) { 1388 Assembler::vinsertf32x4(dst, dst, src, 1); 1389 } else { 1390 Assembler::vinsertf128(dst, dst, src, 1); 1391 } 1392 } 1393 1394 void vinsertf128_high(XMMRegister dst, Address src) { 1395 if (UseAVX > 2) { 1396 Assembler::vinsertf32x4(dst, dst, src, 1); 1397 } else { 1398 Assembler::vinsertf128(dst, dst, src, 1); 1399 } 1400 } 1401 1402 void vextractf128_high(XMMRegister dst, XMMRegister src) { 1403 if (UseAVX > 2) { 1404 Assembler::vextractf32x4(dst, src, 1); 1405 } else { 1406 Assembler::vextractf128(dst, src, 1); 1407 } 1408 } 1409 1410 void vextractf128_high(Address dst, XMMRegister src) { 1411 if (UseAVX > 2) { 1412 Assembler::vextractf32x4(dst, src, 1); 1413 } else { 1414 Assembler::vextractf128(dst, src, 1); 1415 } 1416 } 1417 1418 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers 1419 void vinserti64x4_high(XMMRegister dst, XMMRegister src) { 1420 Assembler::vinserti64x4(dst, dst, src, 1); 1421 } 1422 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) { 1423 Assembler::vinsertf64x4(dst, dst, src, 1); 1424 } 1425 void vextracti64x4_high(XMMRegister dst, XMMRegister src) { 1426 Assembler::vextracti64x4(dst, src, 1); 1427 } 1428 void vextractf64x4_high(XMMRegister dst, XMMRegister src) { 1429 Assembler::vextractf64x4(dst, src, 1); 1430 } 1431 void vextractf64x4_high(Address dst, XMMRegister src) { 1432 Assembler::vextractf64x4(dst, src, 1); 1433 } 1434 void vinsertf64x4_high(XMMRegister dst, Address src) { 1435 Assembler::vinsertf64x4(dst, dst, src, 1); 1436 } 1437 1438 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers 1439 void vinserti128_low(XMMRegister dst, XMMRegister src) { 1440 vinserti128(dst, dst, src, 0); 1441 } 1442 void vinserti128_low(XMMRegister dst, Address src) { 1443 vinserti128(dst, dst, src, 0); 1444 } 1445 void vextracti128_low(XMMRegister dst, XMMRegister src) { 1446 vextracti128(dst, src, 0); 1447 } 1448 void vextracti128_low(Address dst, XMMRegister src) { 1449 vextracti128(dst, src, 0); 1450 } 1451 1452 void vinsertf128_low(XMMRegister dst, XMMRegister src) { 1453 if (UseAVX > 2) { 1454 Assembler::vinsertf32x4(dst, dst, src, 0); 1455 } else { 1456 Assembler::vinsertf128(dst, dst, src, 0); 1457 } 1458 } 1459 1460 void vinsertf128_low(XMMRegister dst, Address src) { 1461 if (UseAVX > 2) { 1462 Assembler::vinsertf32x4(dst, dst, src, 0); 1463 } else { 1464 Assembler::vinsertf128(dst, dst, src, 0); 1465 } 1466 } 1467 1468 void vextractf128_low(XMMRegister dst, XMMRegister src) { 1469 if (UseAVX > 2) { 1470 Assembler::vextractf32x4(dst, src, 0); 1471 } else { 1472 Assembler::vextractf128(dst, src, 0); 1473 } 1474 } 1475 1476 void vextractf128_low(Address dst, XMMRegister src) { 1477 if (UseAVX > 2) { 1478 Assembler::vextractf32x4(dst, src, 0); 1479 } else { 1480 Assembler::vextractf128(dst, src, 0); 1481 } 1482 } 1483 1484 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers 1485 void vinserti64x4_low(XMMRegister dst, XMMRegister src) { 1486 Assembler::vinserti64x4(dst, dst, src, 0); 1487 } 1488 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) { 1489 Assembler::vinsertf64x4(dst, dst, src, 0); 1490 } 1491 void vextracti64x4_low(XMMRegister dst, XMMRegister src) { 1492 Assembler::vextracti64x4(dst, src, 0); 1493 } 1494 void vextractf64x4_low(XMMRegister dst, XMMRegister src) { 1495 Assembler::vextractf64x4(dst, src, 0); 1496 } 1497 void vextractf64x4_low(Address dst, XMMRegister src) { 1498 Assembler::vextractf64x4(dst, src, 0); 1499 } 1500 void vinsertf64x4_low(XMMRegister dst, Address src) { 1501 Assembler::vinsertf64x4(dst, dst, src, 0); 1502 } 1503 1504 // Carry-Less Multiplication Quadword 1505 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1506 // 0x00 - multiply lower 64 bits [0:63] 1507 Assembler::vpclmulqdq(dst, nds, src, 0x00); 1508 } 1509 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1510 // 0x11 - multiply upper 64 bits [64:127] 1511 Assembler::vpclmulqdq(dst, nds, src, 0x11); 1512 } 1513 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1514 // 0x00 - multiply lower 64 bits [0:63] 1515 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len); 1516 } 1517 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1518 // 0x11 - multiply upper 64 bits [64:127] 1519 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len); 1520 } 1521 1522 // Data 1523 1524 void cmov32( Condition cc, Register dst, Address src); 1525 void cmov32( Condition cc, Register dst, Register src); 1526 1527 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } 1528 1529 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1530 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1531 1532 void movoop(Register dst, jobject obj); 1533 void movoop(Address dst, jobject obj); 1534 1535 void mov_metadata(Register dst, Metadata* obj); 1536 void mov_metadata(Address dst, Metadata* obj); 1537 1538 void movptr(ArrayAddress dst, Register src); 1539 // can this do an lea? 1540 void movptr(Register dst, ArrayAddress src); 1541 1542 void movptr(Register dst, Address src); 1543 1544 #ifdef _LP64 1545 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1); 1546 #else 1547 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit 1548 #endif 1549 1550 void movptr(Register dst, intptr_t src); 1551 void movptr(Register dst, Register src); 1552 void movptr(Address dst, intptr_t src); 1553 1554 void movptr(Address dst, Register src); 1555 1556 void movptr(Register dst, RegisterOrConstant src) { 1557 if (src.is_constant()) movptr(dst, src.as_constant()); 1558 else movptr(dst, src.as_register()); 1559 } 1560 1561 #ifdef _LP64 1562 // Generally the next two are only used for moving NULL 1563 // Although there are situations in initializing the mark word where 1564 // they could be used. They are dangerous. 1565 1566 // They only exist on LP64 so that int32_t and intptr_t are not the same 1567 // and we have ambiguous declarations. 1568 1569 void movptr(Address dst, int32_t imm32); 1570 void movptr(Register dst, int32_t imm32); 1571 #endif // _LP64 1572 1573 // to avoid hiding movl 1574 void mov32(AddressLiteral dst, Register src); 1575 void mov32(Register dst, AddressLiteral src); 1576 1577 // to avoid hiding movb 1578 void movbyte(ArrayAddress dst, int src); 1579 1580 // Import other mov() methods from the parent class or else 1581 // they will be hidden by the following overriding declaration. 1582 using Assembler::movdl; 1583 using Assembler::movq; 1584 void movdl(XMMRegister dst, AddressLiteral src); 1585 void movq(XMMRegister dst, AddressLiteral src); 1586 1587 // Can push value or effective address 1588 void pushptr(AddressLiteral src); 1589 1590 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 1591 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 1592 1593 void pushoop(jobject obj); 1594 void pushklass(Metadata* obj); 1595 1596 // sign extend as need a l to ptr sized element 1597 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 1598 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 1599 1600 // C2 compiled method's prolog code. 1601 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b); 1602 1603 // Add null checks for all value type arguments 1604 void null_check_value_args(Method* method); 1605 1606 // clear memory of size 'cnt' qwords, starting at 'base'; 1607 // if 'is_large' is set, do not try to produce short loop 1608 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only); 1609 1610 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers 1611 void xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp); 1612 1613 #ifdef COMPILER2 1614 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 1615 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp); 1616 1617 // IndexOf strings. 1618 // Small strings are loaded through stack if they cross page boundary. 1619 void string_indexof(Register str1, Register str2, 1620 Register cnt1, Register cnt2, 1621 int int_cnt2, Register result, 1622 XMMRegister vec, Register tmp, 1623 int ae); 1624 1625 // IndexOf for constant substrings with size >= 8 elements 1626 // which don't need to be loaded through stack. 1627 void string_indexofC8(Register str1, Register str2, 1628 Register cnt1, Register cnt2, 1629 int int_cnt2, Register result, 1630 XMMRegister vec, Register tmp, 1631 int ae); 1632 1633 // Smallest code: we don't need to load through stack, 1634 // check string tail. 1635 1636 // helper function for string_compare 1637 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 1638 Address::ScaleFactor scale, Address::ScaleFactor scale1, 1639 Address::ScaleFactor scale2, Register index, int ae); 1640 // Compare strings. 1641 void string_compare(Register str1, Register str2, 1642 Register cnt1, Register cnt2, Register result, 1643 XMMRegister vec1, int ae); 1644 1645 // Search for Non-ASCII character (Negative byte value) in a byte array, 1646 // return true if it has any and false otherwise. 1647 void has_negatives(Register ary1, Register len, 1648 Register result, Register tmp1, 1649 XMMRegister vec1, XMMRegister vec2); 1650 1651 // Compare char[] or byte[] arrays. 1652 void arrays_equals(bool is_array_equ, Register ary1, Register ary2, 1653 Register limit, Register result, Register chr, 1654 XMMRegister vec1, XMMRegister vec2, bool is_char); 1655 1656 #endif 1657 1658 // Fill primitive arrays 1659 void generate_fill(BasicType t, bool aligned, 1660 Register to, Register value, Register count, 1661 Register rtmp, XMMRegister xtmp); 1662 1663 void encode_iso_array(Register src, Register dst, Register len, 1664 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1665 XMMRegister tmp4, Register tmp5, Register result); 1666 1667 #ifdef _LP64 1668 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2); 1669 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1670 Register y, Register y_idx, Register z, 1671 Register carry, Register product, 1672 Register idx, Register kdx); 1673 void multiply_add_128_x_128(Register x_xstart, Register y, Register z, 1674 Register yz_idx, Register idx, 1675 Register carry, Register product, int offset); 1676 void multiply_128_x_128_bmi2_loop(Register y, Register z, 1677 Register carry, Register carry2, 1678 Register idx, Register jdx, 1679 Register yz_idx1, Register yz_idx2, 1680 Register tmp, Register tmp3, Register tmp4); 1681 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 1682 Register yz_idx, Register idx, Register jdx, 1683 Register carry, Register product, 1684 Register carry2); 1685 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 1686 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5); 1687 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3, 1688 Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1689 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, 1690 Register tmp2); 1691 void multiply_add_64(Register sum, Register op1, Register op2, Register carry, 1692 Register rdxReg, Register raxReg); 1693 void add_one_64(Register z, Register zlen, Register carry, Register tmp1); 1694 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1695 Register tmp3, Register tmp4); 1696 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1697 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1698 1699 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1, 1700 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1701 Register raxReg); 1702 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1, 1703 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1704 Register raxReg); 1705 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 1706 Register result, Register tmp1, Register tmp2, 1707 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3); 1708 #endif 1709 1710 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1711 void update_byte_crc32(Register crc, Register val, Register table); 1712 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp); 1713 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic 1714 // Note on a naming convention: 1715 // Prefix w = register only used on a Westmere+ architecture 1716 // Prefix n = register only used on a Nehalem architecture 1717 #ifdef _LP64 1718 void crc32c_ipl_alg4(Register in_out, uint32_t n, 1719 Register tmp1, Register tmp2, Register tmp3); 1720 #else 1721 void crc32c_ipl_alg4(Register in_out, uint32_t n, 1722 Register tmp1, Register tmp2, Register tmp3, 1723 XMMRegister xtmp1, XMMRegister xtmp2); 1724 #endif 1725 void crc32c_pclmulqdq(XMMRegister w_xtmp1, 1726 Register in_out, 1727 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 1728 XMMRegister w_xtmp2, 1729 Register tmp1, 1730 Register n_tmp2, Register n_tmp3); 1731 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 1732 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1733 Register tmp1, Register tmp2, 1734 Register n_tmp3); 1735 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 1736 Register in_out1, Register in_out2, Register in_out3, 1737 Register tmp1, Register tmp2, Register tmp3, 1738 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1739 Register tmp4, Register tmp5, 1740 Register n_tmp6); 1741 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 1742 Register tmp1, Register tmp2, Register tmp3, 1743 Register tmp4, Register tmp5, Register tmp6, 1744 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1745 bool is_pclmulqdq_supported); 1746 // Fold 128-bit data chunk 1747 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); 1748 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf); 1749 // Fold 8-bit data 1750 void fold_8bit_crc32(Register crc, Register table, Register tmp); 1751 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp); 1752 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); 1753 1754 // Compress char[] array to byte[]. 1755 void char_array_compress(Register src, Register dst, Register len, 1756 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1757 XMMRegister tmp4, Register tmp5, Register result); 1758 1759 // Inflate byte[] array to char[]. 1760 void byte_array_inflate(Register src, Register dst, Register len, 1761 XMMRegister tmp1, Register tmp2); 1762 1763 }; 1764 1765 /** 1766 * class SkipIfEqual: 1767 * 1768 * Instantiating this class will result in assembly code being output that will 1769 * jump around any code emitted between the creation of the instance and it's 1770 * automatic destruction at the end of a scope block, depending on the value of 1771 * the flag passed to the constructor, which will be checked at run-time. 1772 */ 1773 class SkipIfEqual { 1774 private: 1775 MacroAssembler* _masm; 1776 Label _label; 1777 1778 public: 1779 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1780 ~SkipIfEqual(); 1781 }; 1782 1783 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP