src/cpu/aarch64/vm/aarch64.ad

rev 10235 : 8150229: aarch64: pipeline class for several instructions is not set correctly
Summary: aarch64: c2 fix pipeline class for several instructions.
Reviewed-by: duke
Contributed-by: felix.yang@linaro.org

@@ -13407,11 +13407,11 @@
 
   ins_encode %{
     __ fmovs($dst$$Register, as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(fp_f2i);
 
 %}
 
 instruct MoveI2F_reg_reg(vRegF dst, iRegI src) %{
 

@@ -13425,11 +13425,11 @@
 
   ins_encode %{
     __ fmovs(as_FloatRegister($dst$$reg), $src$$Register);
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(fp_i2f);
 
 %}
 
 instruct MoveD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
 

@@ -13443,11 +13443,11 @@
 
   ins_encode %{
     __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(fp_d2l);
 
 %}
 
 instruct MoveL2D_reg_reg(vRegD dst, iRegL src) %{
 

@@ -13461,11 +13461,11 @@
 
   ins_encode %{
     __ fmovd(as_FloatRegister($dst$$reg), $src$$Register);
   %}
 
-  ins_pipe(pipe_class_memory);
+  ins_pipe(fp_l2d);
 
 %}
 
 // ============================================================================
 // clearing of an array

@@ -16606,11 +16606,11 @@
   ins_encode %{
     __ sshl(as_FloatRegister($dst$$reg), __ T2S,
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(vshift64_imm);
+  ins_pipe(vshift64);
 %}
 
 instruct vsll4I(vecX dst, vecX src, vecX shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (LShiftVI src shift));

@@ -16620,11 +16620,11 @@
   ins_encode %{
     __ sshl(as_FloatRegister($dst$$reg), __ T4S,
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(vshift128_imm);
+  ins_pipe(vshift128);
 %}
 
 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (URShiftVI src shift));

@@ -16633,11 +16633,11 @@
   ins_encode %{
     __ ushl(as_FloatRegister($dst$$reg), __ T2S,
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(vshift64_imm);
+  ins_pipe(vshift64);
 %}
 
 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (URShiftVI src shift));

@@ -16646,11 +16646,11 @@
   ins_encode %{
     __ ushl(as_FloatRegister($dst$$reg), __ T4S,
             as_FloatRegister($src$$reg),
             as_FloatRegister($shift$$reg));
   %}
-  ins_pipe(vshift128_imm);
+  ins_pipe(vshift128);
 %}
 
 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (LShiftVI src shift));

@@ -16764,11 +16764,11 @@
   ins_encode %{
     __ shl(as_FloatRegister($dst$$reg), __ T2D,
            as_FloatRegister($src$$reg),
            (int)$shift$$constant & 63);
   %}
-  ins_pipe(vshift128);
+  ins_pipe(vshift128_imm);
 %}
 
 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (RShiftVL src shift));