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src/cpu/aarch64/vm/aarch64.ad

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rev 10586 : 8153837: aarch64: handle special cases for MaxINode & MinINode
Summary: aarch64: handle special cases for MaxINode & MinINode
Reviewed-by: duke

@@ -14030,20 +14030,20 @@
 %}
 
 // ============================================================================
 // Max and Min
 
-instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+instruct minI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
 %{
   match(Set dst (MinI src1 src2));
 
   effect(DEF dst, USE src1, USE src2, KILL cr);
   size(8);
 
   ins_cost(INSN_COST * 3);
   format %{
-    "cmpw $src1 $src2\t signed int\n\t"
+    "cmpw $src1, $src2\t signed int\n\t"
     "cselw $dst, $src1, $src2 lt\t"
   %}
 
   ins_encode %{
     __ cmpw(as_Register($src1$$reg),

@@ -14054,22 +14054,96 @@
              Assembler::LT);
   %}
 
   ins_pipe(ialu_reg_reg);
 %}
-// FROM HERE
 
-instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
+instruct minI_reg_imm0(iRegINoSp dst, iRegI src1, immI0 src2, rFlagsReg cr)
+%{
+  match(Set dst (MinI src1 src2));
+
+  effect(DEF dst, USE src1, USE src2, KILL cr);
+  size(8);
+
+  ins_cost(INSN_COST * 3);
+  format %{
+    "cmpw $src1, zr\t signed int\n\t"
+    "cselw $dst, $src1, zr, lt\t"
+  %}
+
+  ins_encode %{
+    __ cmpw(as_Register($src1$$reg),
+            zr);
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             zr,
+             Assembler::LT);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
+instruct minI_reg_imm1(iRegINoSp dst, iRegI src1, immI_1 src2, rFlagsReg cr)
+%{
+  match(Set dst (MinI src1 src2));
+
+  effect(DEF dst, USE src1, USE src2, KILL cr);
+  size(8);
+
+  ins_cost(INSN_COST * 3);
+  format %{
+    "cmpw $src1, zr\t signed int\n\t"
+    "csincw $dst, $src1, zr, le\t"
+  %}
+
+  ins_encode %{
+    __ cmpw(as_Register($src1$$reg),
+            zr);
+    __ csincw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              zr,
+              Assembler::LE);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
+instruct minI_reg_immM1(iRegINoSp dst, iRegI src1, immI_M1 src2, rFlagsReg cr)
+%{
+  match(Set dst (MinI src1 src2));
+
+  effect(DEF dst, USE src1, USE src2, KILL cr);
+  size(8);
+
+  ins_cost(INSN_COST * 3);
+  format %{
+    "cmpw $src1, zr\t signed int\n\t"
+    "csinvw $dst, $src1, zr, lt\t"
+  %}
+
+  ins_encode %{
+    __ cmpw(as_Register($src1$$reg),
+            zr);
+    __ csinvw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              zr,
+              Assembler::LT);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
+instruct maxI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
 %{
   match(Set dst (MaxI src1 src2));
 
   effect(DEF dst, USE src1, USE src2, KILL cr);
   size(8);
 
   ins_cost(INSN_COST * 3);
   format %{
-    "cmpw $src1 $src2\t signed int\n\t"
+    "cmpw $src1, $src2\t signed int\n\t"
     "cselw $dst, $src1, $src2 gt\t"
   %}
 
   ins_encode %{
     __ cmpw(as_Register($src1$$reg),

@@ -14081,10 +14155,85 @@
   %}
 
   ins_pipe(ialu_reg_reg);
 %}
 
+instruct maxI_reg_imm0(iRegINoSp dst, iRegI src1, immI0 src2, rFlagsReg cr)
+%{
+  match(Set dst (MaxI src1 src2));
+
+  effect(DEF dst, USE src1, USE src2, KILL cr);
+  size(8);
+
+  ins_cost(INSN_COST * 3);
+  format %{
+    "cmpw $src1, zr\t signed int\n\t"
+    "cselw $dst, $src1, zr, gt\t"
+  %}
+
+  ins_encode %{
+    __ cmpw(as_Register($src1$$reg),
+            zr);
+    __ cselw(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             zr,
+             Assembler::GT);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
+instruct maxI_reg_imm1(iRegINoSp dst, iRegI src1, immI_1 src2, rFlagsReg cr)
+%{
+  match(Set dst (MaxI src1 src2));
+
+  effect(DEF dst, USE src1, USE src2, KILL cr);
+  size(8);
+
+  ins_cost(INSN_COST * 3);
+  format %{
+    "cmpw $src1, zr\t signed int\n\t"
+    "csincw $dst, $src1, zr, gt\t"
+  %}
+
+  ins_encode %{
+    __ cmpw(as_Register($src1$$reg),
+            zr);
+    __ csincw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              zr,
+              Assembler::GT);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
+instruct maxI_reg_immM1(iRegINoSp dst, iRegI src1, immI_M1 src2, rFlagsReg cr)
+%{
+  match(Set dst (MaxI src1 src2));
+
+  effect(DEF dst, USE src1, USE src2, KILL cr);
+  size(8);
+
+  ins_cost(INSN_COST * 3);
+  format %{
+    "cmpw $src1, zr\t signed int\n\t"
+    "csinvw $dst, $src1, zr, ge\t"
+  %}
+
+  ins_encode %{
+    __ cmpw(as_Register($src1$$reg),
+            zr);
+    __ csinvw(as_Register($dst$$reg),
+              as_Register($src1$$reg),
+              zr,
+              Assembler::GE);
+  %}
+
+  ins_pipe(ialu_reg_reg);
+%}
+
 // ============================================================================
 // Branch Instructions
 
 // Direct Branch.
 instruct branch(label lbl)
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