rev 12409 : 8169177: aarch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
Summary: Add zero-initialization to C1 for fast TLAB refills
Reviewed-by: aph, drwhite
Contributed-by: kavitha.natarajan@linaro.org

   1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 
  31 // MacroAssembler extends Assembler by frequently used macros.
  32 //
  33 // Instructions for which a 'better' code sequence exists depending
  34 // on arguments should also go in here.
  35 
  36 class MacroAssembler: public Assembler {
  37   friend class LIR_Assembler;
  38 
  39  public:
  40   using Assembler::mov;
  41   using Assembler::movi;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50   virtual void call_VM_leaf_base(
  51     address entry_point,               // the entry point
  52     int     number_of_arguments,        // the number of arguments to pop after the call
  53     Label *retaddr = NULL
  54   );
  55 
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label &retaddr) {
  60     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  61   }
  62 
  63   // This is the base routine called by the different versions of call_VM. The interpreter
  64   // may customize this version by overriding it for its purposes (e.g., to save/restore
  65   // additional registers when doing a VM call).
  66   //
  67   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  68   // returns the register which contains the thread upon return. If a thread register has been
  69   // specified, the return value will correspond to that register. If no last_java_sp is specified
  70   // (noreg) than rsp will be used instead.
  71   virtual void call_VM_base(           // returns the register containing the thread upon return
  72     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  73     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  74     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  75     address  entry_point,              // the entry point
  76     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  77     bool     check_exceptions          // whether to check for pending exceptions after return
  78   );
  79 
  80   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  81   // The implementation is only non-empty for the InterpreterMacroAssembler,
  82   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  83   virtual void check_and_handle_popframe(Register java_thread);
  84   virtual void check_and_handle_earlyret(Register java_thread);
  85 
  86   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  87 
  88   // Maximum size of class area in Metaspace when compressed
  89   uint64_t use_XOR_for_compressed_class_base;
  90 
  91  public:
  92   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  93     use_XOR_for_compressed_class_base
  94       = (operand_valid_for_logical_immediate(false /*is32*/,
  95                                              (uint64_t)Universe::narrow_klass_base())
  96          && ((uint64_t)Universe::narrow_klass_base()
  97              > (1u << log2_intptr(CompressedClassSpaceSize))));
  98   }
  99 
 100   // Biased locking support
 101   // lock_reg and obj_reg must be loaded up with the appropriate values.
 102   // swap_reg is killed.
 103   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 104   // Optional slow case is for implementations (interpreter and C1) which branch to
 105   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 106   // Returns offset of first potentially-faulting instruction for null
 107   // check info (currently consumed only by C1). If
 108   // swap_reg_contains_mark is true then returns -1 as it is assumed
 109   // the calling code has already passed any potential faults.
 110   int biased_locking_enter(Register lock_reg, Register obj_reg,
 111                            Register swap_reg, Register tmp_reg,
 112                            bool swap_reg_contains_mark,
 113                            Label& done, Label* slow_case = NULL,
 114                            BiasedLockingCounters* counters = NULL);
 115   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 116 
 117 
 118   // Helper functions for statistics gathering.
 119   // Unconditional atomic increment.
 120   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 121   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 122     lea(tmp1, counter_addr);
 123     atomic_incw(tmp1, tmp2, tmp3);
 124   }
 125   // Load Effective Address
 126   void lea(Register r, const Address &a) {
 127     InstructionMark im(this);
 128     code_section()->relocate(inst_mark(), a.rspec());
 129     a.lea(this, r);
 130   }
 131 
 132   void addmw(Address a, Register incr, Register scratch) {
 133     ldrw(scratch, a);
 134     addw(scratch, scratch, incr);
 135     strw(scratch, a);
 136   }
 137 
 138   // Add constant to memory word
 139   void addmw(Address a, int imm, Register scratch) {
 140     ldrw(scratch, a);
 141     if (imm > 0)
 142       addw(scratch, scratch, (unsigned)imm);
 143     else
 144       subw(scratch, scratch, (unsigned)-imm);
 145     strw(scratch, a);
 146   }
 147 
 148   void bind(Label& L) {
 149     Assembler::bind(L);
 150     code()->clear_last_membar();
 151   }
 152 
 153   void membar(Membar_mask_bits order_constraint);
 154 
 155   // Frame creation and destruction shared between JITs.
 156   void build_frame(int framesize);
 157   void remove_frame(int framesize);
 158 
 159   virtual void _call_Unimplemented(address call_site) {
 160     mov(rscratch2, call_site);
 161     haltsim();
 162   }
 163 
 164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 165 
 166   virtual void notify(int type);
 167 
 168   // aliases defined in AARCH64 spec
 169 
 170   template<class T>
 171   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 172   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 173 
 174   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 175   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 176 
 177   void cset(Register Rd, Assembler::Condition cond) {
 178     csinc(Rd, zr, zr, ~cond);
 179   }
 180   void csetw(Register Rd, Assembler::Condition cond) {
 181     csincw(Rd, zr, zr, ~cond);
 182   }
 183 
 184   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 185     csneg(Rd, Rn, Rn, ~cond);
 186   }
 187   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 188     csnegw(Rd, Rn, Rn, ~cond);
 189   }
 190 
 191   inline void movw(Register Rd, Register Rn) {
 192     if (Rd == sp || Rn == sp) {
 193       addw(Rd, Rn, 0U);
 194     } else {
 195       orrw(Rd, zr, Rn);
 196     }
 197   }
 198   inline void mov(Register Rd, Register Rn) {
 199     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 200     if (Rd == Rn) {
 201     } else if (Rd == sp || Rn == sp) {
 202       add(Rd, Rn, 0U);
 203     } else {
 204       orr(Rd, zr, Rn);
 205     }
 206   }
 207 
 208   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 209   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 210 
 211   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 212   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 213 
 214   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 215   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 216 
 217   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 218     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 219   }
 220   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 221     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 222   }
 223 
 224   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 225     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 226   }
 227   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 228     bfm(Rd, Rn, lsb , (lsb + width - 1));
 229   }
 230 
 231   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 232     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 233   }
 234   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 235     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 236   }
 237 
 238   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 239     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 240   }
 241   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 242     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 243   }
 244 
 245   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 246     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 247   }
 248   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 249     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 250   }
 251 
 252   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 254   }
 255   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 256     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 257   }
 258 
 259   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 260     sbfmw(Rd, Rn, imm, 31);
 261   }
 262 
 263   inline void asr(Register Rd, Register Rn, unsigned imm) {
 264     sbfm(Rd, Rn, imm, 63);
 265   }
 266 
 267   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 268     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 269   }
 270 
 271   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 272     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 273   }
 274 
 275   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 276     ubfmw(Rd, Rn, imm, 31);
 277   }
 278 
 279   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 280     ubfm(Rd, Rn, imm, 63);
 281   }
 282 
 283   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 284     extrw(Rd, Rn, Rn, imm);
 285   }
 286 
 287   inline void ror(Register Rd, Register Rn, unsigned imm) {
 288     extr(Rd, Rn, Rn, imm);
 289   }
 290 
 291   inline void sxtbw(Register Rd, Register Rn) {
 292     sbfmw(Rd, Rn, 0, 7);
 293   }
 294   inline void sxthw(Register Rd, Register Rn) {
 295     sbfmw(Rd, Rn, 0, 15);
 296   }
 297   inline void sxtb(Register Rd, Register Rn) {
 298     sbfm(Rd, Rn, 0, 7);
 299   }
 300   inline void sxth(Register Rd, Register Rn) {
 301     sbfm(Rd, Rn, 0, 15);
 302   }
 303   inline void sxtw(Register Rd, Register Rn) {
 304     sbfm(Rd, Rn, 0, 31);
 305   }
 306 
 307   inline void uxtbw(Register Rd, Register Rn) {
 308     ubfmw(Rd, Rn, 0, 7);
 309   }
 310   inline void uxthw(Register Rd, Register Rn) {
 311     ubfmw(Rd, Rn, 0, 15);
 312   }
 313   inline void uxtb(Register Rd, Register Rn) {
 314     ubfm(Rd, Rn, 0, 7);
 315   }
 316   inline void uxth(Register Rd, Register Rn) {
 317     ubfm(Rd, Rn, 0, 15);
 318   }
 319   inline void uxtw(Register Rd, Register Rn) {
 320     ubfm(Rd, Rn, 0, 31);
 321   }
 322 
 323   inline void cmnw(Register Rn, Register Rm) {
 324     addsw(zr, Rn, Rm);
 325   }
 326   inline void cmn(Register Rn, Register Rm) {
 327     adds(zr, Rn, Rm);
 328   }
 329 
 330   inline void cmpw(Register Rn, Register Rm) {
 331     subsw(zr, Rn, Rm);
 332   }
 333   inline void cmp(Register Rn, Register Rm) {
 334     subs(zr, Rn, Rm);
 335   }
 336 
 337   inline void negw(Register Rd, Register Rn) {
 338     subw(Rd, zr, Rn);
 339   }
 340 
 341   inline void neg(Register Rd, Register Rn) {
 342     sub(Rd, zr, Rn);
 343   }
 344 
 345   inline void negsw(Register Rd, Register Rn) {
 346     subsw(Rd, zr, Rn);
 347   }
 348 
 349   inline void negs(Register Rd, Register Rn) {
 350     subs(Rd, zr, Rn);
 351   }
 352 
 353   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 354     addsw(zr, Rn, Rm, kind, shift);
 355   }
 356   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 357     adds(zr, Rn, Rm, kind, shift);
 358   }
 359 
 360   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 361     subsw(zr, Rn, Rm, kind, shift);
 362   }
 363   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 364     subs(zr, Rn, Rm, kind, shift);
 365   }
 366 
 367   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 368     subw(Rd, zr, Rn, kind, shift);
 369   }
 370 
 371   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 372     sub(Rd, zr, Rn, kind, shift);
 373   }
 374 
 375   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 376     subsw(Rd, zr, Rn, kind, shift);
 377   }
 378 
 379   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 380     subs(Rd, zr, Rn, kind, shift);
 381   }
 382 
 383   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 384     msubw(Rd, Rn, Rm, zr);
 385   }
 386   inline void mneg(Register Rd, Register Rn, Register Rm) {
 387     msub(Rd, Rn, Rm, zr);
 388   }
 389 
 390   inline void mulw(Register Rd, Register Rn, Register Rm) {
 391     maddw(Rd, Rn, Rm, zr);
 392   }
 393   inline void mul(Register Rd, Register Rn, Register Rm) {
 394     madd(Rd, Rn, Rm, zr);
 395   }
 396 
 397   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 398     smsubl(Rd, Rn, Rm, zr);
 399   }
 400   inline void smull(Register Rd, Register Rn, Register Rm) {
 401     smaddl(Rd, Rn, Rm, zr);
 402   }
 403 
 404   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 405     umsubl(Rd, Rn, Rm, zr);
 406   }
 407   inline void umull(Register Rd, Register Rn, Register Rm) {
 408     umaddl(Rd, Rn, Rm, zr);
 409   }
 410 
 411 #define WRAP(INSN)                                                            \
 412   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 413     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 414       nop();                                                                  \
 415     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 416   }
 417 
 418   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 419   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 420 #undef WRAP
 421 
 422 
 423   // macro assembly operations needed for aarch64
 424 
 425   // first two private routines for loading 32 bit or 64 bit constants
 426 private:
 427 
 428   void mov_immediate64(Register dst, u_int64_t imm64);
 429   void mov_immediate32(Register dst, u_int32_t imm32);
 430 
 431   int push(unsigned int bitset, Register stack);
 432   int pop(unsigned int bitset, Register stack);
 433 
 434   void mov(Register dst, Address a);
 435 
 436 public:
 437   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 438   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 439 
 440   // Push and pop everything that might be clobbered by a native
 441   // runtime call except rscratch1 and rscratch2.  (They are always
 442   // scratch, so we don't have to protect them.)  Only save the lower
 443   // 64 bits of each vector register.
 444   void push_call_clobbered_registers();
 445   void pop_call_clobbered_registers();
 446 
 447   // now mov instructions for loading absolute addresses and 32 or
 448   // 64 bit integers
 449 
 450   inline void mov(Register dst, address addr)
 451   {
 452     mov_immediate64(dst, (u_int64_t)addr);
 453   }
 454 
 455   inline void mov(Register dst, u_int64_t imm64)
 456   {
 457     mov_immediate64(dst, imm64);
 458   }
 459 
 460   inline void movw(Register dst, u_int32_t imm32)
 461   {
 462     mov_immediate32(dst, imm32);
 463   }
 464 
 465   inline void mov(Register dst, long l)
 466   {
 467     mov(dst, (u_int64_t)l);
 468   }
 469 
 470   inline void mov(Register dst, int i)
 471   {
 472     mov(dst, (long)i);
 473   }
 474 
 475   void mov(Register dst, RegisterOrConstant src) {
 476     if (src.is_register())
 477       mov(dst, src.as_register());
 478     else
 479       mov(dst, src.as_constant());
 480   }
 481 
 482   void movptr(Register r, uintptr_t imm64);
 483 
 484   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 485 
 486   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 487     orr(Vd, T, Vn, Vn);
 488   }
 489 
 490 public:
 491 
 492   // Generalized Test Bit And Branch, including a "far" variety which
 493   // spans more than 32KiB.
 494   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 495     assert(cond == EQ || cond == NE, "must be");
 496 
 497     if (far)
 498       cond = ~cond;
 499 
 500     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 501     if (cond == Assembler::EQ)
 502       branch = &Assembler::tbz;
 503     else
 504       branch = &Assembler::tbnz;
 505 
 506     if (far) {
 507       Label L;
 508       (this->*branch)(Rt, bitpos, L);
 509       b(dest);
 510       bind(L);
 511     } else {
 512       (this->*branch)(Rt, bitpos, dest);
 513     }
 514   }
 515 
 516   // macro instructions for accessing and updating floating point
 517   // status register
 518   //
 519   // FPSR : op1 == 011
 520   //        CRn == 0100
 521   //        CRm == 0100
 522   //        op2 == 001
 523 
 524   inline void get_fpsr(Register reg)
 525   {
 526     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 527   }
 528 
 529   inline void set_fpsr(Register reg)
 530   {
 531     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 532   }
 533 
 534   inline void clear_fpsr()
 535   {
 536     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 537   }
 538 
 539   // DCZID_EL0: op1 == 011
 540   //            CRn == 0000
 541   //            CRm == 0000
 542   //            op2 == 111
 543   inline void get_dczid_el0(Register reg)
 544   {
 545     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 546   }
 547 
 548   // CTR_EL0:   op1 == 011
 549   //            CRn == 0000
 550   //            CRm == 0000
 551   //            op2 == 001
 552   inline void get_ctr_el0(Register reg)
 553   {
 554     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 555   }
 556 
 557   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 558   int corrected_idivl(Register result, Register ra, Register rb,
 559                       bool want_remainder, Register tmp = rscratch1);
 560   int corrected_idivq(Register result, Register ra, Register rb,
 561                       bool want_remainder, Register tmp = rscratch1);
 562 
 563   // Support for NULL-checks
 564   //
 565   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 566   // If the accessed location is M[reg + offset] and the offset is known, provide the
 567   // offset. No explicit code generation is needed if the offset is within a certain
 568   // range (0 <= offset <= page_size).
 569 
 570   virtual void null_check(Register reg, int offset = -1);
 571   static bool needs_explicit_null_check(intptr_t offset);
 572 
 573   static address target_addr_for_insn(address insn_addr, unsigned insn);
 574   static address target_addr_for_insn(address insn_addr) {
 575     unsigned insn = *(unsigned*)insn_addr;
 576     return target_addr_for_insn(insn_addr, insn);
 577   }
 578 
 579   // Required platform-specific helpers for Label::patch_instructions.
 580   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 581   static int pd_patch_instruction_size(address branch, address target);
 582   static void pd_patch_instruction(address branch, address target) {
 583     pd_patch_instruction_size(branch, target);
 584   }
 585   static address pd_call_destination(address branch) {
 586     return target_addr_for_insn(branch);
 587   }
 588 #ifndef PRODUCT
 589   static void pd_print_patched_instruction(address branch);
 590 #endif
 591 
 592   static int patch_oop(address insn_addr, address o);
 593   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 594 
 595   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 596 
 597   // The following 4 methods return the offset of the appropriate move instruction
 598 
 599   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 600   int load_unsigned_byte(Register dst, Address src);
 601   int load_unsigned_short(Register dst, Address src);
 602 
 603   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 604   int load_signed_byte(Register dst, Address src);
 605   int load_signed_short(Register dst, Address src);
 606 
 607   int load_signed_byte32(Register dst, Address src);
 608   int load_signed_short32(Register dst, Address src);
 609 
 610   // Support for sign-extension (hi:lo = extend_sign(lo))
 611   void extend_sign(Register hi, Register lo);
 612 
 613   // Load and store values by size and signed-ness
 614   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 615   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 616 
 617   // Support for inc/dec with optimal instruction selection depending on value
 618 
 619   // x86_64 aliases an unqualified register/address increment and
 620   // decrement to call incrementq and decrementq but also supports
 621   // explicitly sized calls to incrementq/decrementq or
 622   // incrementl/decrementl
 623 
 624   // for aarch64 the proper convention would be to use
 625   // increment/decrement for 64 bit operatons and
 626   // incrementw/decrementw for 32 bit operations. so when porting
 627   // x86_64 code we can leave calls to increment/decrement as is,
 628   // replace incrementq/decrementq with increment/decrement and
 629   // replace incrementl/decrementl with incrementw/decrementw.
 630 
 631   // n.b. increment/decrement calls with an Address destination will
 632   // need to use a scratch register to load the value to be
 633   // incremented. increment/decrement calls which add or subtract a
 634   // constant value greater than 2^12 will need to use a 2nd scratch
 635   // register to hold the constant. so, a register increment/decrement
 636   // may trash rscratch2 and an address increment/decrement trash
 637   // rscratch and rscratch2
 638 
 639   void decrementw(Address dst, int value = 1);
 640   void decrementw(Register reg, int value = 1);
 641 
 642   void decrement(Register reg, int value = 1);
 643   void decrement(Address dst, int value = 1);
 644 
 645   void incrementw(Address dst, int value = 1);
 646   void incrementw(Register reg, int value = 1);
 647 
 648   void increment(Register reg, int value = 1);
 649   void increment(Address dst, int value = 1);
 650 
 651 
 652   // Alignment
 653   void align(int modulus);
 654 
 655   // Stack frame creation/removal
 656   void enter()
 657   {
 658     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 659     mov(rfp, sp);
 660   }
 661   void leave()
 662   {
 663     mov(sp, rfp);
 664     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 665   }
 666 
 667   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 668   // The pointer will be loaded into the thread register.
 669   void get_thread(Register thread);
 670 
 671 
 672   // Support for VM calls
 673   //
 674   // It is imperative that all calls into the VM are handled via the call_VM macros.
 675   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 676   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 677 
 678 
 679   void call_VM(Register oop_result,
 680                address entry_point,
 681                bool check_exceptions = true);
 682   void call_VM(Register oop_result,
 683                address entry_point,
 684                Register arg_1,
 685                bool check_exceptions = true);
 686   void call_VM(Register oop_result,
 687                address entry_point,
 688                Register arg_1, Register arg_2,
 689                bool check_exceptions = true);
 690   void call_VM(Register oop_result,
 691                address entry_point,
 692                Register arg_1, Register arg_2, Register arg_3,
 693                bool check_exceptions = true);
 694 
 695   // Overloadings with last_Java_sp
 696   void call_VM(Register oop_result,
 697                Register last_java_sp,
 698                address entry_point,
 699                int number_of_arguments = 0,
 700                bool check_exceptions = true);
 701   void call_VM(Register oop_result,
 702                Register last_java_sp,
 703                address entry_point,
 704                Register arg_1, bool
 705                check_exceptions = true);
 706   void call_VM(Register oop_result,
 707                Register last_java_sp,
 708                address entry_point,
 709                Register arg_1, Register arg_2,
 710                bool check_exceptions = true);
 711   void call_VM(Register oop_result,
 712                Register last_java_sp,
 713                address entry_point,
 714                Register arg_1, Register arg_2, Register arg_3,
 715                bool check_exceptions = true);
 716 
 717   void get_vm_result  (Register oop_result, Register thread);
 718   void get_vm_result_2(Register metadata_result, Register thread);
 719 
 720   // These always tightly bind to MacroAssembler::call_VM_base
 721   // bypassing the virtual implementation
 722   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 723   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 724   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 725   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 726   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 727 
 728   void call_VM_leaf(address entry_point,
 729                     int number_of_arguments = 0);
 730   void call_VM_leaf(address entry_point,
 731                     Register arg_1);
 732   void call_VM_leaf(address entry_point,
 733                     Register arg_1, Register arg_2);
 734   void call_VM_leaf(address entry_point,
 735                     Register arg_1, Register arg_2, Register arg_3);
 736 
 737   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 738   // bypassing the virtual implementation
 739   void super_call_VM_leaf(address entry_point);
 740   void super_call_VM_leaf(address entry_point, Register arg_1);
 741   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 742   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 743   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 744 
 745   // last Java Frame (fills frame anchor)
 746   void set_last_Java_frame(Register last_java_sp,
 747                            Register last_java_fp,
 748                            address last_java_pc,
 749                            Register scratch);
 750 
 751   void set_last_Java_frame(Register last_java_sp,
 752                            Register last_java_fp,
 753                            Label &last_java_pc,
 754                            Register scratch);
 755 
 756   void set_last_Java_frame(Register last_java_sp,
 757                            Register last_java_fp,
 758                            Register last_java_pc,
 759                            Register scratch);
 760 
 761   void reset_last_Java_frame(Register thread);
 762 
 763   // thread in the default location (rthread)
 764   void reset_last_Java_frame(bool clear_fp);
 765 
 766   // Stores
 767   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 768   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 769 
 770 #if INCLUDE_ALL_GCS
 771 
 772   void g1_write_barrier_pre(Register obj,
 773                             Register pre_val,
 774                             Register thread,
 775                             Register tmp,
 776                             bool tosca_live,
 777                             bool expand_call);
 778 
 779   void g1_write_barrier_post(Register store_addr,
 780                              Register new_val,
 781                              Register thread,
 782                              Register tmp,
 783                              Register tmp2);
 784 
 785 #endif // INCLUDE_ALL_GCS
 786 
 787   // oop manipulations
 788   void load_klass(Register dst, Register src);
 789   void store_klass(Register dst, Register src);
 790   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 791 
 792   void load_mirror(Register dst, Register method);
 793 
 794   void load_heap_oop(Register dst, Address src);
 795 
 796   void load_heap_oop_not_null(Register dst, Address src);
 797   void store_heap_oop(Address dst, Register src);
 798 
 799   // currently unimplemented
 800   // Used for storing NULL. All other oop constants should be
 801   // stored using routines that take a jobject.
 802   void store_heap_oop_null(Address dst);
 803 
 804   void load_prototype_header(Register dst, Register src);
 805 
 806   void store_klass_gap(Register dst, Register src);
 807 
 808   // This dummy is to prevent a call to store_heap_oop from
 809   // converting a zero (like NULL) into a Register by giving
 810   // the compiler two choices it can't resolve
 811 
 812   void store_heap_oop(Address dst, void* dummy);
 813 
 814   void encode_heap_oop(Register d, Register s);
 815   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 816   void decode_heap_oop(Register d, Register s);
 817   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 818   void encode_heap_oop_not_null(Register r);
 819   void decode_heap_oop_not_null(Register r);
 820   void encode_heap_oop_not_null(Register dst, Register src);
 821   void decode_heap_oop_not_null(Register dst, Register src);
 822 
 823   void set_narrow_oop(Register dst, jobject obj);
 824 
 825   void encode_klass_not_null(Register r);
 826   void decode_klass_not_null(Register r);
 827   void encode_klass_not_null(Register dst, Register src);
 828   void decode_klass_not_null(Register dst, Register src);
 829 
 830   void set_narrow_klass(Register dst, Klass* k);
 831 
 832   // if heap base register is used - reinit it with the correct value
 833   void reinit_heapbase();
 834 
 835   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 836 
 837   void push_CPU_state(bool save_vectors = false);
 838   void pop_CPU_state(bool restore_vectors = false) ;
 839 
 840   // Round up to a power of two
 841   void round_to(Register reg, int modulus);
 842 
 843   // allocation
 844   void eden_allocate(
 845     Register obj,                      // result: pointer to object after successful allocation
 846     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 847     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 848     Register t1,                       // temp register
 849     Label&   slow_case                 // continuation point if fast allocation fails
 850   );
 851   void tlab_allocate(
 852     Register obj,                      // result: pointer to object after successful allocation
 853     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 854     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 855     Register t1,                       // temp register
 856     Register t2,                       // temp register
 857     Label&   slow_case                 // continuation point if fast allocation fails
 858   );
 859   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address

 860   void verify_tlab();
 861 
 862   void incr_allocated_bytes(Register thread,
 863                             Register var_size_in_bytes, int con_size_in_bytes,
 864                             Register t1 = noreg);
 865 
 866   // interface method calling
 867   void lookup_interface_method(Register recv_klass,
 868                                Register intf_klass,
 869                                RegisterOrConstant itable_index,
 870                                Register method_result,
 871                                Register scan_temp,
 872                                Label& no_such_interface);
 873 
 874   // virtual method calling
 875   // n.b. x86 allows RegisterOrConstant for vtable_index
 876   void lookup_virtual_method(Register recv_klass,
 877                              RegisterOrConstant vtable_index,
 878                              Register method_result);
 879 
 880   // Test sub_klass against super_klass, with fast and slow paths.
 881 
 882   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 883   // One of the three labels can be NULL, meaning take the fall-through.
 884   // If super_check_offset is -1, the value is loaded up from super_klass.
 885   // No registers are killed, except temp_reg.
 886   void check_klass_subtype_fast_path(Register sub_klass,
 887                                      Register super_klass,
 888                                      Register temp_reg,
 889                                      Label* L_success,
 890                                      Label* L_failure,
 891                                      Label* L_slow_path,
 892                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 893 
 894   // The rest of the type check; must be wired to a corresponding fast path.
 895   // It does not repeat the fast path logic, so don't use it standalone.
 896   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 897   // Updates the sub's secondary super cache as necessary.
 898   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 899   void check_klass_subtype_slow_path(Register sub_klass,
 900                                      Register super_klass,
 901                                      Register temp_reg,
 902                                      Register temp2_reg,
 903                                      Label* L_success,
 904                                      Label* L_failure,
 905                                      bool set_cond_codes = false);
 906 
 907   // Simplified, combined version, good for typical uses.
 908   // Falls through on failure.
 909   void check_klass_subtype(Register sub_klass,
 910                            Register super_klass,
 911                            Register temp_reg,
 912                            Label& L_success);
 913 
 914   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 915 
 916 
 917   // Debugging
 918 
 919   // only if +VerifyOops
 920   void verify_oop(Register reg, const char* s = "broken oop");
 921   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 922 
 923 // TODO: verify method and klass metadata (compare against vptr?)
 924   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 925   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 926 
 927 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 928 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 929 
 930   // only if +VerifyFPU
 931   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 932 
 933   // prints msg, dumps registers and stops execution
 934   void stop(const char* msg);
 935 
 936   // prints msg and continues
 937   void warn(const char* msg);
 938 
 939   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 940 
 941   void untested()                                { stop("untested"); }
 942 
 943   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
 944 
 945   void should_not_reach_here()                   { stop("should not reach here"); }
 946 
 947   // Stack overflow checking
 948   void bang_stack_with_offset(int offset) {
 949     // stack grows down, caller passes positive offset
 950     assert(offset > 0, "must bang with negative offset");
 951     mov(rscratch2, -offset);
 952     str(zr, Address(sp, rscratch2));
 953   }
 954 
 955   // Writes to stack successive pages until offset reached to check for
 956   // stack overflow + shadow pages.  Also, clobbers tmp
 957   void bang_stack_size(Register size, Register tmp);
 958 
 959   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 960                                                 Register tmp,
 961                                                 int offset);
 962 
 963   // Support for serializing memory accesses between threads
 964   void serialize_memory(Register thread, Register tmp);
 965 
 966   // Arithmetics
 967 
 968   void addptr(const Address &dst, int32_t src);
 969   void cmpptr(Register src1, Address src2);
 970 
 971   // Various forms of CAS
 972 
 973   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 974                   Label &suceed, Label *fail);
 975 
 976   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 977                   Label &suceed, Label *fail);
 978 
 979   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 980   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 981   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
 982   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
 983 
 984   void atomic_xchg(Register prev, Register newv, Register addr);
 985   void atomic_xchgw(Register prev, Register newv, Register addr);
 986   void atomic_xchgal(Register prev, Register newv, Register addr);
 987   void atomic_xchgalw(Register prev, Register newv, Register addr);
 988 
 989   void orptr(Address adr, RegisterOrConstant src) {
 990     ldr(rscratch2, adr);
 991     if (src.is_register())
 992       orr(rscratch2, rscratch2, src.as_register());
 993     else
 994       orr(rscratch2, rscratch2, src.as_constant());
 995     str(rscratch2, adr);
 996   }
 997 
 998   // A generic CAS; success or failure is in the EQ flag.
 999   // Clobbers rscratch1
1000   void cmpxchg(Register addr, Register expected, Register new_val,
1001                enum operand_size size,
1002                bool acquire, bool release, bool weak,
1003                Register result);
1004 
1005   // Calls
1006 
1007   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1008 
1009   static bool far_branches() {
1010     return ReservedCodeCacheSize > branch_range;
1011   }
1012 
1013   // Jumps that can reach anywhere in the code cache.
1014   // Trashes tmp.
1015   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1016   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1017 
1018   static int far_branch_size() {
1019     if (far_branches()) {
1020       return 3 * 4;  // adrp, add, br
1021     } else {
1022       return 4;
1023     }
1024   }
1025 
1026   // Emit the CompiledIC call idiom
1027   address ic_call(address entry, jint method_index = 0);
1028 
1029 public:
1030 
1031   // Data
1032 
1033   void mov_metadata(Register dst, Metadata* obj);
1034   Address allocate_metadata_address(Metadata* obj);
1035   Address constant_oop_address(jobject obj);
1036 
1037   void movoop(Register dst, jobject obj, bool immediate = false);
1038 
1039   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1040   void kernel_crc32(Register crc, Register buf, Register len,
1041         Register table0, Register table1, Register table2, Register table3,
1042         Register tmp, Register tmp2, Register tmp3);
1043   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1044   void kernel_crc32c(Register crc, Register buf, Register len,
1045         Register table0, Register table1, Register table2, Register table3,
1046         Register tmp, Register tmp2, Register tmp3);
1047 
1048   // Stack push and pop individual 64 bit registers
1049   void push(Register src);
1050   void pop(Register dst);
1051 
1052   // push all registers onto the stack
1053   void pusha();
1054   void popa();
1055 
1056   void repne_scan(Register addr, Register value, Register count,
1057                   Register scratch);
1058   void repne_scanw(Register addr, Register value, Register count,
1059                    Register scratch);
1060 
1061   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1062   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1063 
1064   // If a constant does not fit in an immediate field, generate some
1065   // number of MOV instructions and then perform the operation
1066   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1067                              add_sub_imm_insn insn1,
1068                              add_sub_reg_insn insn2);
1069   // Seperate vsn which sets the flags
1070   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1071                              add_sub_imm_insn insn1,
1072                              add_sub_reg_insn insn2);
1073 
1074 #define WRAP(INSN)                                                      \
1075   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1076     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1077   }                                                                     \
1078                                                                         \
1079   void INSN(Register Rd, Register Rn, Register Rm,                      \
1080              enum shift_kind kind, unsigned shift = 0) {                \
1081     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1082   }                                                                     \
1083                                                                         \
1084   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1085     Assembler::INSN(Rd, Rn, Rm);                                        \
1086   }                                                                     \
1087                                                                         \
1088   void INSN(Register Rd, Register Rn, Register Rm,                      \
1089            ext::operation option, int amount = 0) {                     \
1090     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1091   }
1092 
1093   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1094 
1095 #undef WRAP
1096 #define WRAP(INSN)                                                      \
1097   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1098     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1099   }                                                                     \
1100                                                                         \
1101   void INSN(Register Rd, Register Rn, Register Rm,                      \
1102              enum shift_kind kind, unsigned shift = 0) {                \
1103     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1104   }                                                                     \
1105                                                                         \
1106   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1107     Assembler::INSN(Rd, Rn, Rm);                                        \
1108   }                                                                     \
1109                                                                         \
1110   void INSN(Register Rd, Register Rn, Register Rm,                      \
1111            ext::operation option, int amount = 0) {                     \
1112     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1113   }
1114 
1115   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1116 
1117   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1118   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1119   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1120   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1121 
1122   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1123 
1124   void tableswitch(Register index, jint lowbound, jint highbound,
1125                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1126     adr(rscratch1, jumptable);
1127     subsw(rscratch2, index, lowbound);
1128     subsw(zr, rscratch2, highbound - lowbound);
1129     br(Assembler::HS, jumptable_end);
1130     add(rscratch1, rscratch1, rscratch2,
1131         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1132     br(rscratch1);
1133   }
1134 
1135   // Form an address from base + offset in Rd.  Rd may or may not
1136   // actually be used: you must use the Address that is returned.  It
1137   // is up to you to ensure that the shift provided matches the size
1138   // of your data.
1139   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1140 
1141   // Return true iff an address is within the 48-bit AArch64 address
1142   // space.
1143   bool is_valid_AArch64_address(address a) {
1144     return ((uint64_t)a >> 48) == 0;
1145   }
1146 
1147   // Load the base of the cardtable byte map into reg.
1148   void load_byte_map_base(Register reg);
1149 
1150   // Prolog generator routines to support switch between x86 code and
1151   // generated ARM code
1152 
1153   // routine to generate an x86 prolog for a stub function which
1154   // bootstraps into the generated ARM code which directly follows the
1155   // stub
1156   //
1157 
1158   public:
1159   // enum used for aarch64--x86 linkage to define return type of x86 function
1160   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1161 
1162 #ifdef BUILTIN_SIM
1163   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1164 #else
1165   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1166 #endif
1167 
1168   // special version of call_VM_leaf_base needed for aarch64 simulator
1169   // where we need to specify both the gp and fp arg counts and the
1170   // return type so that the linkage routine from aarch64 to x86 and
1171   // back knows which aarch64 registers to copy to x86 registers and
1172   // which x86 result register to copy back to an aarch64 register
1173 
1174   void call_VM_leaf_base1(
1175     address  entry_point,             // the entry point
1176     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1177     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1178     ret_type type,                    // the return type for the call
1179     Label*   retaddr = NULL
1180   );
1181 
1182   void ldr_constant(Register dest, const Address &const_addr) {
1183     if (NearCpool) {
1184       ldr(dest, const_addr);
1185     } else {
1186       unsigned long offset;
1187       adrp(dest, InternalAddress(const_addr.target()), offset);
1188       ldr(dest, Address(dest, offset));
1189     }
1190   }
1191 
1192   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1193   address read_polling_page(Register r, relocInfo::relocType rtype);
1194 
1195   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1196   void update_byte_crc32(Register crc, Register val, Register table);
1197   void update_word_crc32(Register crc, Register v, Register tmp,
1198         Register table0, Register table1, Register table2, Register table3,
1199         bool upper = false);
1200 
1201   void string_compare(Register str1, Register str2,
1202                       Register cnt1, Register cnt2, Register result,
1203                       Register tmp1,
1204                       FloatRegister vtmp, FloatRegister vtmpZ, int ae);
1205 
1206   void arrays_equals(Register a1, Register a2,
1207                      Register result, Register cnt1,
1208                      int elem_size, bool is_string);
1209 
1210   void fill_words(Register base, Register cnt, Register value);
1211   void zero_words(Register base, u_int64_t cnt);
1212   void zero_words(Register base, Register cnt);
1213   void block_zero(Register base, Register cnt, bool is_large = false);
1214 
1215   void byte_array_inflate(Register src, Register dst, Register len,
1216                           FloatRegister vtmp1, FloatRegister vtmp2,
1217                           FloatRegister vtmp3, Register tmp4);
1218 
1219   void char_array_compress(Register src, Register dst, Register len,
1220                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1221                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1222                            Register result);
1223 
1224   void encode_iso_array(Register src, Register dst,
1225                         Register len, Register result,
1226                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1227                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1228   void string_indexof(Register str1, Register str2,
1229                       Register cnt1, Register cnt2,
1230                       Register tmp1, Register tmp2,
1231                       Register tmp3, Register tmp4,
1232                       int int_cnt1, Register result, int ae);
1233   void string_indexof_char(Register str1, Register cnt1,
1234                            Register ch, Register result,
1235                            Register tmp1, Register tmp2, Register tmp3);
1236 private:
1237   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1238                        Register src1, Register src2);
1239   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1240     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1241   }
1242   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1243                              Register y, Register y_idx, Register z,
1244                              Register carry, Register product,
1245                              Register idx, Register kdx);
1246   void multiply_128_x_128_loop(Register y, Register z,
1247                                Register carry, Register carry2,
1248                                Register idx, Register jdx,
1249                                Register yz_idx1, Register yz_idx2,
1250                                Register tmp, Register tmp3, Register tmp4,
1251                                Register tmp7, Register product_hi);
1252 public:
1253   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1254                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1255                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1256   // ISB may be needed because of a safepoint
1257   void maybe_isb() { isb(); }
1258 
1259 private:
1260   // Return the effective address r + (r1 << ext) + offset.
1261   // Uses rscratch2.
1262   Address offsetted_address(Register r, Register r1, Address::extend ext,
1263                             int offset, int size);
1264 
1265 private:
1266   // Returns an address on the stack which is reachable with a ldr/str of size
1267   // Uses rscratch2 if the address is not directly reachable
1268   Address spill_address(int size, int offset, Register tmp=rscratch2);
1269 
1270 public:
1271   void spill(Register Rx, bool is64, int offset) {
1272     if (is64) {
1273       str(Rx, spill_address(8, offset));
1274     } else {
1275       strw(Rx, spill_address(4, offset));
1276     }
1277   }
1278   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1279     str(Vx, T, spill_address(1 << (int)T, offset));
1280   }
1281   void unspill(Register Rx, bool is64, int offset) {
1282     if (is64) {
1283       ldr(Rx, spill_address(8, offset));
1284     } else {
1285       ldrw(Rx, spill_address(4, offset));
1286     }
1287   }
1288   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1289     ldr(Vx, T, spill_address(1 << (int)T, offset));
1290   }
1291   void spill_copy128(int src_offset, int dst_offset,
1292                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1293     if (src_offset < 512 && (src_offset & 7) == 0 &&
1294         dst_offset < 512 && (dst_offset & 7) == 0) {
1295       ldp(tmp1, tmp2, Address(sp, src_offset));
1296       stp(tmp1, tmp2, Address(sp, dst_offset));
1297     } else {
1298       unspill(tmp1, true, src_offset);
1299       spill(tmp1, true, dst_offset);
1300       unspill(tmp1, true, src_offset+8);
1301       spill(tmp1, true, dst_offset+8);
1302     }
1303   }
1304 };
1305 
1306 #ifdef ASSERT
1307 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1308 #endif
1309 
1310 /**
1311  * class SkipIfEqual:
1312  *
1313  * Instantiating this class will result in assembly code being output that will
1314  * jump around any code emitted between the creation of the instance and it's
1315  * automatic destruction at the end of a scope block, depending on the value of
1316  * the flag passed to the constructor, which will be checked at run-time.
1317  */
1318 class SkipIfEqual {
1319  private:
1320   MacroAssembler* _masm;
1321   Label _label;
1322 
1323  public:
1324    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1325    ~SkipIfEqual();
1326 };
1327 
1328 struct tableswitch {
1329   Register _reg;
1330   int _insn_index; jint _first_key; jint _last_key;
1331   Label _after;
1332   Label _branches;
1333 };
1334 
1335 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
--- EOF ---