# HG changeset patch
# User fyang
# Date 1593989939 -28800
#      Mon Jul 06 06:58:59 2020 +0800
# Node ID 311225d8a41780869ffc21ae8e95fe49477b6604
# Parent  93cfec0cf41749b38c43e4d7c15b34303e8a5601
8248219: aarch64: missing memory barrier in fast_storefield and fast_accessfield
Reviewed-by: aph
Contributed-by: songyaofei2@huawei.com

diff --git a/src/cpu/aarch64/vm/templateTable_aarch64.cpp b/src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp
@@ -2922,6 +2922,9 @@
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
 
+  // Must prevent reordering of the following cp cache loads with bytecode load
+  __ membar(MacroAssembler::LoadLoad);
+
   // test for volatile with r3
   __ ldrw(r3, Address(r2, in_bytes(base +
 				   ConstantPoolCacheEntry::flags_offset())));
@@ -3013,6 +3016,10 @@
 
   // access constant pool cache
   __ get_cache_and_index_at_bcp(r2, r1, 1);
+
+  // Must prevent reordering of the following cp cache loads with bytecode load
+  __ membar(MacroAssembler::LoadLoad);
+
   __ ldr(r1, Address(r2, in_bytes(ConstantPoolCache::base_offset() +
                                   ConstantPoolCacheEntry::f2_offset())));
   __ ldrw(r3, Address(r2, in_bytes(ConstantPoolCache::base_offset() +