1 /* 2 * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_CFGPrinter.hpp" 27 #include "c1/c1_CodeStubs.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_FrameMap.hpp" 30 #include "c1/c1_IR.hpp" 31 #include "c1/c1_LIRGenerator.hpp" 32 #include "c1/c1_LinearScan.hpp" 33 #include "c1/c1_ValueStack.hpp" 34 #include "code/vmreg.inline.hpp" 35 #include "utilities/bitMap.inline.hpp" 36 37 #ifndef PRODUCT 38 39 static LinearScanStatistic _stat_before_alloc; 40 static LinearScanStatistic _stat_after_asign; 41 static LinearScanStatistic _stat_final; 42 43 static LinearScanTimers _total_timer; 44 45 // helper macro for short definition of timer 46 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose); 47 48 // helper macro for short definition of trace-output inside code 49 #define TRACE_LINEAR_SCAN(level, code) \ 50 if (TraceLinearScanLevel >= level) { \ 51 code; \ 52 } 53 54 #else 55 56 #define TIME_LINEAR_SCAN(timer_name) 57 #define TRACE_LINEAR_SCAN(level, code) 58 59 #endif 60 61 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words 62 #ifdef _LP64 63 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1}; 64 #else 65 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1}; 66 #endif 67 68 69 // Implementation of LinearScan 70 71 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) 72 : _compilation(ir->compilation()) 73 , _ir(ir) 74 , _gen(gen) 75 , _frame_map(frame_map) 76 , _num_virtual_regs(gen->max_virtual_register_number()) 77 , _has_fpu_registers(false) 78 , _num_calls(-1) 79 , _max_spills(0) 80 , _unused_spill_slot(-1) 81 , _intervals(0) // initialized later with correct length 82 , _new_intervals_from_allocation(new GrowableArray<Interval*>()) 83 , _sorted_intervals(NULL) 84 , _needs_full_resort(false) 85 , _lir_ops(0) // initialized later with correct length 86 , _block_of_op(0) // initialized later with correct length 87 , _has_info(0) 88 , _has_call(0) 89 , _scope_value_cache(0) // initialized later with correct length 90 , _interval_in_loop(0, 0) // initialized later with correct length 91 , _cached_blocks(*ir->linear_scan_order()) 92 #ifdef X86 93 , _fpu_stack_allocator(NULL) 94 #endif 95 { 96 assert(this->ir() != NULL, "check if valid"); 97 assert(this->compilation() != NULL, "check if valid"); 98 assert(this->gen() != NULL, "check if valid"); 99 assert(this->frame_map() != NULL, "check if valid"); 100 } 101 102 103 // ********** functions for converting LIR-Operands to register numbers 104 // 105 // Emulate a flat register file comprising physical integer registers, 106 // physical floating-point registers and virtual registers, in that order. 107 // Virtual registers already have appropriate numbers, since V0 is 108 // the number of physical registers. 109 // Returns -1 for hi word if opr is a single word operand. 110 // 111 // Note: the inverse operation (calculating an operand for register numbers) 112 // is done in calc_operand_for_interval() 113 114 int LinearScan::reg_num(LIR_Opr opr) { 115 assert(opr->is_register(), "should not call this otherwise"); 116 117 if (opr->is_virtual_register()) { 118 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number"); 119 return opr->vreg_number(); 120 } else if (opr->is_single_cpu()) { 121 return opr->cpu_regnr(); 122 } else if (opr->is_double_cpu()) { 123 return opr->cpu_regnrLo(); 124 #ifdef X86 125 } else if (opr->is_single_xmm()) { 126 return opr->fpu_regnr() + pd_first_xmm_reg; 127 } else if (opr->is_double_xmm()) { 128 return opr->fpu_regnrLo() + pd_first_xmm_reg; 129 #endif 130 } else if (opr->is_single_fpu()) { 131 return opr->fpu_regnr() + pd_first_fpu_reg; 132 } else if (opr->is_double_fpu()) { 133 return opr->fpu_regnrLo() + pd_first_fpu_reg; 134 } else { 135 ShouldNotReachHere(); 136 return -1; 137 } 138 } 139 140 int LinearScan::reg_numHi(LIR_Opr opr) { 141 assert(opr->is_register(), "should not call this otherwise"); 142 143 if (opr->is_virtual_register()) { 144 return -1; 145 } else if (opr->is_single_cpu()) { 146 return -1; 147 } else if (opr->is_double_cpu()) { 148 return opr->cpu_regnrHi(); 149 #ifdef X86 150 } else if (opr->is_single_xmm()) { 151 return -1; 152 } else if (opr->is_double_xmm()) { 153 return -1; 154 #endif 155 } else if (opr->is_single_fpu()) { 156 return -1; 157 } else if (opr->is_double_fpu()) { 158 return opr->fpu_regnrHi() + pd_first_fpu_reg; 159 } else { 160 ShouldNotReachHere(); 161 return -1; 162 } 163 } 164 165 166 // ********** functions for classification of intervals 167 168 bool LinearScan::is_precolored_interval(const Interval* i) { 169 return i->reg_num() < LinearScan::nof_regs; 170 } 171 172 bool LinearScan::is_virtual_interval(const Interval* i) { 173 return i->reg_num() >= LIR_OprDesc::vreg_base; 174 } 175 176 bool LinearScan::is_precolored_cpu_interval(const Interval* i) { 177 return i->reg_num() < LinearScan::nof_cpu_regs; 178 } 179 180 bool LinearScan::is_virtual_cpu_interval(const Interval* i) { 181 #if defined(__SOFTFP__) || defined(E500V2) 182 return i->reg_num() >= LIR_OprDesc::vreg_base; 183 #else 184 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); 185 #endif // __SOFTFP__ or E500V2 186 } 187 188 bool LinearScan::is_precolored_fpu_interval(const Interval* i) { 189 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; 190 } 191 192 bool LinearScan::is_virtual_fpu_interval(const Interval* i) { 193 #if defined(__SOFTFP__) || defined(E500V2) 194 return false; 195 #else 196 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); 197 #endif // __SOFTFP__ or E500V2 198 } 199 200 bool LinearScan::is_in_fpu_register(const Interval* i) { 201 // fixed intervals not needed for FPU stack allocation 202 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg; 203 } 204 205 bool LinearScan::is_oop_interval(const Interval* i) { 206 // fixed intervals never contain oops 207 return i->reg_num() >= nof_regs && i->type() == T_OBJECT; 208 } 209 210 211 // ********** General helper functions 212 213 // compute next unused stack index that can be used for spilling 214 int LinearScan::allocate_spill_slot(bool double_word) { 215 int spill_slot; 216 if (double_word) { 217 if ((_max_spills & 1) == 1) { 218 // alignment of double-word values 219 // the hole because of the alignment is filled with the next single-word value 220 assert(_unused_spill_slot == -1, "wasting a spill slot"); 221 _unused_spill_slot = _max_spills; 222 _max_spills++; 223 } 224 spill_slot = _max_spills; 225 _max_spills += 2; 226 227 } else if (_unused_spill_slot != -1) { 228 // re-use hole that was the result of a previous double-word alignment 229 spill_slot = _unused_spill_slot; 230 _unused_spill_slot = -1; 231 232 } else { 233 spill_slot = _max_spills; 234 _max_spills++; 235 } 236 237 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount(); 238 239 // the class OopMapValue uses only 11 bits for storing the name of the 240 // oop location. So a stack slot bigger than 2^11 leads to an overflow 241 // that is not reported in product builds. Prevent this by checking the 242 // spill slot here (altough this value and the later used location name 243 // are slightly different) 244 if (result > 2000) { 245 bailout("too many stack slots used"); 246 } 247 248 return result; 249 } 250 251 void LinearScan::assign_spill_slot(Interval* it) { 252 // assign the canonical spill slot of the parent (if a part of the interval 253 // is already spilled) or allocate a new spill slot 254 if (it->canonical_spill_slot() >= 0) { 255 it->assign_reg(it->canonical_spill_slot()); 256 } else { 257 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2); 258 it->set_canonical_spill_slot(spill); 259 it->assign_reg(spill); 260 } 261 } 262 263 void LinearScan::propagate_spill_slots() { 264 if (!frame_map()->finalize_frame(max_spills())) { 265 bailout("frame too large"); 266 } 267 } 268 269 // create a new interval with a predefined reg_num 270 // (only used for parent intervals that are created during the building phase) 271 Interval* LinearScan::create_interval(int reg_num) { 272 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval"); 273 274 Interval* interval = new Interval(reg_num); 275 _intervals.at_put(reg_num, interval); 276 277 // assign register number for precolored intervals 278 if (reg_num < LIR_OprDesc::vreg_base) { 279 interval->assign_reg(reg_num); 280 } 281 return interval; 282 } 283 284 // assign a new reg_num to the interval and append it to the list of intervals 285 // (only used for child intervals that are created during register allocation) 286 void LinearScan::append_interval(Interval* it) { 287 it->set_reg_num(_intervals.length()); 288 _intervals.append(it); 289 _new_intervals_from_allocation->append(it); 290 } 291 292 // copy the vreg-flags if an interval is split 293 void LinearScan::copy_register_flags(Interval* from, Interval* to) { 294 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) { 295 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg); 296 } 297 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) { 298 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved); 299 } 300 301 // Note: do not copy the must_start_in_memory flag because it is not necessary for child 302 // intervals (only the very beginning of the interval must be in memory) 303 } 304 305 306 // ********** spill move optimization 307 // eliminate moves from register to stack if stack slot is known to be correct 308 309 // called during building of intervals 310 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) { 311 assert(interval->is_split_parent(), "can only be called for split parents"); 312 313 switch (interval->spill_state()) { 314 case noDefinitionFound: 315 assert(interval->spill_definition_pos() == -1, "must no be set before"); 316 interval->set_spill_definition_pos(def_pos); 317 interval->set_spill_state(oneDefinitionFound); 318 break; 319 320 case oneDefinitionFound: 321 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created"); 322 if (def_pos < interval->spill_definition_pos() - 2) { 323 // second definition found, so no spill optimization possible for this interval 324 interval->set_spill_state(noOptimization); 325 } else { 326 // two consecutive definitions (because of two-operand LIR form) 327 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal"); 328 } 329 break; 330 331 case noOptimization: 332 // nothing to do 333 break; 334 335 default: 336 assert(false, "other states not allowed at this time"); 337 } 338 } 339 340 // called during register allocation 341 void LinearScan::change_spill_state(Interval* interval, int spill_pos) { 342 switch (interval->spill_state()) { 343 case oneDefinitionFound: { 344 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth(); 345 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth(); 346 347 if (def_loop_depth < spill_loop_depth) { 348 // the loop depth of the spilling position is higher then the loop depth 349 // at the definition of the interval -> move write to memory out of loop 350 // by storing at definitin of the interval 351 interval->set_spill_state(storeAtDefinition); 352 } else { 353 // the interval is currently spilled only once, so for now there is no 354 // reason to store the interval at the definition 355 interval->set_spill_state(oneMoveInserted); 356 } 357 break; 358 } 359 360 case oneMoveInserted: { 361 // the interval is spilled more then once, so it is better to store it to 362 // memory at the definition 363 interval->set_spill_state(storeAtDefinition); 364 break; 365 } 366 367 case storeAtDefinition: 368 case startInMemory: 369 case noOptimization: 370 case noDefinitionFound: 371 // nothing to do 372 break; 373 374 default: 375 assert(false, "other states not allowed at this time"); 376 } 377 } 378 379 380 bool LinearScan::must_store_at_definition(const Interval* i) { 381 return i->is_split_parent() && i->spill_state() == storeAtDefinition; 382 } 383 384 // called once before asignment of register numbers 385 void LinearScan::eliminate_spill_moves() { 386 TIME_LINEAR_SCAN(timer_eliminate_spill_moves); 387 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves")); 388 389 // collect all intervals that must be stored after their definion. 390 // the list is sorted by Interval::spill_definition_pos 391 Interval* interval; 392 Interval* temp_list; 393 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL); 394 395 #ifdef ASSERT 396 Interval* prev = NULL; 397 Interval* temp = interval; 398 while (temp != Interval::end()) { 399 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos"); 400 if (prev != NULL) { 401 assert(temp->from() >= prev->from(), "intervals not sorted"); 402 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos"); 403 } 404 405 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned"); 406 assert(temp->spill_definition_pos() >= temp->from(), "invalid order"); 407 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized"); 408 409 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos())); 410 411 temp = temp->next(); 412 } 413 #endif 414 415 LIR_InsertionBuffer insertion_buffer; 416 int num_blocks = block_count(); 417 for (int i = 0; i < num_blocks; i++) { 418 BlockBegin* block = block_at(i); 419 LIR_OpList* instructions = block->lir()->instructions_list(); 420 int num_inst = instructions->length(); 421 bool has_new = false; 422 423 // iterate all instructions of the block. skip the first because it is always a label 424 for (int j = 1; j < num_inst; j++) { 425 LIR_Op* op = instructions->at(j); 426 int op_id = op->id(); 427 428 if (op_id == -1) { 429 // remove move from register to stack if the stack slot is guaranteed to be correct. 430 // only moves that have been inserted by LinearScan can be removed. 431 assert(op->code() == lir_move, "only moves can have a op_id of -1"); 432 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 433 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers"); 434 435 LIR_Op1* op1 = (LIR_Op1*)op; 436 Interval* interval = interval_at(op1->result_opr()->vreg_number()); 437 438 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) { 439 // move target is a stack slot that is always correct, so eliminate instruction 440 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number())); 441 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num 442 } 443 444 } else { 445 // insert move from register to stack just after the beginning of the interval 446 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order"); 447 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval"); 448 449 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) { 450 if (!has_new) { 451 // prepare insertion buffer (appended when all instructions of the block are processed) 452 insertion_buffer.init(block->lir()); 453 has_new = true; 454 } 455 456 LIR_Opr from_opr = operand_for_interval(interval); 457 LIR_Opr to_opr = canonical_spill_opr(interval); 458 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register"); 459 assert(to_opr->is_stack(), "to operand must be a stack slot"); 460 461 insertion_buffer.move(j, from_opr, to_opr); 462 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id)); 463 464 interval = interval->next(); 465 } 466 } 467 } // end of instruction iteration 468 469 if (has_new) { 470 block->lir()->append(&insertion_buffer); 471 } 472 } // end of block iteration 473 474 assert(interval == Interval::end(), "missed an interval"); 475 } 476 477 478 // ********** Phase 1: number all instructions in all blocks 479 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan. 480 481 void LinearScan::number_instructions() { 482 { 483 // dummy-timer to measure the cost of the timer itself 484 // (this time is then subtracted from all other timers to get the real value) 485 TIME_LINEAR_SCAN(timer_do_nothing); 486 } 487 TIME_LINEAR_SCAN(timer_number_instructions); 488 489 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node. 490 int num_blocks = block_count(); 491 int num_instructions = 0; 492 int i; 493 for (i = 0; i < num_blocks; i++) { 494 num_instructions += block_at(i)->lir()->instructions_list()->length(); 495 } 496 497 // initialize with correct length 498 _lir_ops = LIR_OpArray(num_instructions); 499 _block_of_op = BlockBeginArray(num_instructions); 500 501 int op_id = 0; 502 int idx = 0; 503 504 for (i = 0; i < num_blocks; i++) { 505 BlockBegin* block = block_at(i); 506 block->set_first_lir_instruction_id(op_id); 507 LIR_OpList* instructions = block->lir()->instructions_list(); 508 509 int num_inst = instructions->length(); 510 for (int j = 0; j < num_inst; j++) { 511 LIR_Op* op = instructions->at(j); 512 op->set_id(op_id); 513 514 _lir_ops.at_put(idx, op); 515 _block_of_op.at_put(idx, block); 516 assert(lir_op_with_id(op_id) == op, "must match"); 517 518 idx++; 519 op_id += 2; // numbering of lir_ops by two 520 } 521 block->set_last_lir_instruction_id(op_id - 2); 522 } 523 assert(idx == num_instructions, "must match"); 524 assert(idx * 2 == op_id, "must match"); 525 526 _has_call = BitMap(num_instructions); _has_call.clear(); 527 _has_info = BitMap(num_instructions); _has_info.clear(); 528 } 529 530 531 // ********** Phase 2: compute local live sets separately for each block 532 // (sets live_gen and live_kill for each block) 533 534 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) { 535 LIR_Opr opr = value->operand(); 536 Constant* con = value->as_Constant(); 537 538 // check some asumptions about debug information 539 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type"); 540 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands"); 541 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); 542 543 if ((con == NULL || con->is_pinned()) && opr->is_register()) { 544 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 545 int reg = opr->vreg_number(); 546 if (!live_kill.at(reg)) { 547 live_gen.set_bit(reg); 548 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg)); 549 } 550 } 551 } 552 553 554 void LinearScan::compute_local_live_sets() { 555 TIME_LINEAR_SCAN(timer_compute_local_live_sets); 556 557 int num_blocks = block_count(); 558 int live_size = live_set_size(); 559 bool local_has_fpu_registers = false; 560 int local_num_calls = 0; 561 LIR_OpVisitState visitor; 562 563 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops()); 564 local_interval_in_loop.clear(); 565 566 // iterate all blocks 567 for (int i = 0; i < num_blocks; i++) { 568 BlockBegin* block = block_at(i); 569 570 BitMap live_gen(live_size); live_gen.clear(); 571 BitMap live_kill(live_size); live_kill.clear(); 572 573 if (block->is_set(BlockBegin::exception_entry_flag)) { 574 // Phi functions at the begin of an exception handler are 575 // implicitly defined (= killed) at the beginning of the block. 576 for_each_phi_fun(block, phi, 577 live_kill.set_bit(phi->operand()->vreg_number()) 578 ); 579 } 580 581 LIR_OpList* instructions = block->lir()->instructions_list(); 582 int num_inst = instructions->length(); 583 584 // iterate all instructions of the block. skip the first because it is always a label 585 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); 586 for (int j = 1; j < num_inst; j++) { 587 LIR_Op* op = instructions->at(j); 588 589 // visit operation to collect all operands 590 visitor.visit(op); 591 592 if (visitor.has_call()) { 593 _has_call.set_bit(op->id() >> 1); 594 local_num_calls++; 595 } 596 if (visitor.info_count() > 0) { 597 _has_info.set_bit(op->id() >> 1); 598 } 599 600 // iterate input operands of instruction 601 int k, n, reg; 602 n = visitor.opr_count(LIR_OpVisitState::inputMode); 603 for (k = 0; k < n; k++) { 604 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); 605 assert(opr->is_register(), "visitor should only return register operands"); 606 607 if (opr->is_virtual_register()) { 608 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 609 reg = opr->vreg_number(); 610 if (!live_kill.at(reg)) { 611 live_gen.set_bit(reg); 612 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id())); 613 } 614 if (block->loop_index() >= 0) { 615 local_interval_in_loop.set_bit(reg, block->loop_index()); 616 } 617 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 618 } 619 620 #ifdef ASSERT 621 // fixed intervals are never live at block boundaries, so 622 // they need not be processed in live sets. 623 // this is checked by these assertions to be sure about it. 624 // the entry block may have incoming values in registers, which is ok. 625 if (!opr->is_virtual_register() && block != ir()->start()) { 626 reg = reg_num(opr); 627 if (is_processed_reg_num(reg)) { 628 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); 629 } 630 reg = reg_numHi(opr); 631 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 632 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); 633 } 634 } 635 #endif 636 } 637 638 // Add uses of live locals from interpreter's point of view for proper debug information generation 639 n = visitor.info_count(); 640 for (k = 0; k < n; k++) { 641 CodeEmitInfo* info = visitor.info_at(k); 642 ValueStack* stack = info->stack(); 643 for_each_state_value(stack, value, 644 set_live_gen_kill(value, op, live_gen, live_kill) 645 ); 646 } 647 648 // iterate temp operands of instruction 649 n = visitor.opr_count(LIR_OpVisitState::tempMode); 650 for (k = 0; k < n; k++) { 651 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); 652 assert(opr->is_register(), "visitor should only return register operands"); 653 654 if (opr->is_virtual_register()) { 655 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 656 reg = opr->vreg_number(); 657 live_kill.set_bit(reg); 658 if (block->loop_index() >= 0) { 659 local_interval_in_loop.set_bit(reg, block->loop_index()); 660 } 661 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 662 } 663 664 #ifdef ASSERT 665 // fixed intervals are never live at block boundaries, so 666 // they need not be processed in live sets 667 // process them only in debug mode so that this can be checked 668 if (!opr->is_virtual_register()) { 669 reg = reg_num(opr); 670 if (is_processed_reg_num(reg)) { 671 live_kill.set_bit(reg_num(opr)); 672 } 673 reg = reg_numHi(opr); 674 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 675 live_kill.set_bit(reg); 676 } 677 } 678 #endif 679 } 680 681 // iterate output operands of instruction 682 n = visitor.opr_count(LIR_OpVisitState::outputMode); 683 for (k = 0; k < n; k++) { 684 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); 685 assert(opr->is_register(), "visitor should only return register operands"); 686 687 if (opr->is_virtual_register()) { 688 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 689 reg = opr->vreg_number(); 690 live_kill.set_bit(reg); 691 if (block->loop_index() >= 0) { 692 local_interval_in_loop.set_bit(reg, block->loop_index()); 693 } 694 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 695 } 696 697 #ifdef ASSERT 698 // fixed intervals are never live at block boundaries, so 699 // they need not be processed in live sets 700 // process them only in debug mode so that this can be checked 701 if (!opr->is_virtual_register()) { 702 reg = reg_num(opr); 703 if (is_processed_reg_num(reg)) { 704 live_kill.set_bit(reg_num(opr)); 705 } 706 reg = reg_numHi(opr); 707 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 708 live_kill.set_bit(reg); 709 } 710 } 711 #endif 712 } 713 } // end of instruction iteration 714 715 block->set_live_gen (live_gen); 716 block->set_live_kill(live_kill); 717 block->set_live_in (BitMap(live_size)); block->live_in().clear(); 718 block->set_live_out (BitMap(live_size)); block->live_out().clear(); 719 720 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen())); 721 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill())); 722 } // end of block iteration 723 724 // propagate local calculated information into LinearScan object 725 _has_fpu_registers = local_has_fpu_registers; 726 compilation()->set_has_fpu_code(local_has_fpu_registers); 727 728 _num_calls = local_num_calls; 729 _interval_in_loop = local_interval_in_loop; 730 } 731 732 733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets 734 // (sets live_in and live_out for each block) 735 736 void LinearScan::compute_global_live_sets() { 737 TIME_LINEAR_SCAN(timer_compute_global_live_sets); 738 739 int num_blocks = block_count(); 740 bool change_occurred; 741 bool change_occurred_in_block; 742 int iteration_count = 0; 743 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations 744 745 // Perform a backward dataflow analysis to compute live_out and live_in for each block. 746 // The loop is executed until a fixpoint is reached (no changes in an iteration) 747 // Exception handlers must be processed because not all live values are 748 // present in the state array, e.g. because of global value numbering 749 do { 750 change_occurred = false; 751 752 // iterate all blocks in reverse order 753 for (int i = num_blocks - 1; i >= 0; i--) { 754 BlockBegin* block = block_at(i); 755 756 change_occurred_in_block = false; 757 758 // live_out(block) is the union of live_in(sux), for successors sux of block 759 int n = block->number_of_sux(); 760 int e = block->number_of_exception_handlers(); 761 if (n + e > 0) { 762 // block has successors 763 if (n > 0) { 764 live_out.set_from(block->sux_at(0)->live_in()); 765 for (int j = 1; j < n; j++) { 766 live_out.set_union(block->sux_at(j)->live_in()); 767 } 768 } else { 769 live_out.clear(); 770 } 771 for (int j = 0; j < e; j++) { 772 live_out.set_union(block->exception_handler_at(j)->live_in()); 773 } 774 775 if (!block->live_out().is_same(live_out)) { 776 // A change occurred. Swap the old and new live out sets to avoid copying. 777 BitMap temp = block->live_out(); 778 block->set_live_out(live_out); 779 live_out = temp; 780 781 change_occurred = true; 782 change_occurred_in_block = true; 783 } 784 } 785 786 if (iteration_count == 0 || change_occurred_in_block) { 787 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block)) 788 // note: live_in has to be computed only in first iteration or if live_out has changed! 789 BitMap live_in = block->live_in(); 790 live_in.set_from(block->live_out()); 791 live_in.set_difference(block->live_kill()); 792 live_in.set_union(block->live_gen()); 793 } 794 795 #ifndef PRODUCT 796 if (TraceLinearScanLevel >= 4) { 797 char c = ' '; 798 if (iteration_count == 0 || change_occurred_in_block) { 799 c = '*'; 800 } 801 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in()); 802 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out()); 803 } 804 #endif 805 } 806 iteration_count++; 807 808 if (change_occurred && iteration_count > 50) { 809 BAILOUT("too many iterations in compute_global_live_sets"); 810 } 811 } while (change_occurred); 812 813 814 #ifdef ASSERT 815 // check that fixed intervals are not live at block boundaries 816 // (live set must be empty at fixed intervals) 817 for (int i = 0; i < num_blocks; i++) { 818 BlockBegin* block = block_at(i); 819 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) { 820 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty"); 821 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty"); 822 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty"); 823 } 824 } 825 #endif 826 827 // check that the live_in set of the first block is empty 828 BitMap live_in_args(ir()->start()->live_in().size()); 829 live_in_args.clear(); 830 if (!ir()->start()->live_in().is_same(live_in_args)) { 831 #ifdef ASSERT 832 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)"); 833 tty->print_cr("affected registers:"); 834 print_bitmap(ir()->start()->live_in()); 835 836 // print some additional information to simplify debugging 837 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) { 838 if (ir()->start()->live_in().at(i)) { 839 Instruction* instr = gen()->instruction_for_vreg(i); 840 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id()); 841 842 for (int j = 0; j < num_blocks; j++) { 843 BlockBegin* block = block_at(j); 844 if (block->live_gen().at(i)) { 845 tty->print_cr(" used in block B%d", block->block_id()); 846 } 847 if (block->live_kill().at(i)) { 848 tty->print_cr(" defined in block B%d", block->block_id()); 849 } 850 } 851 } 852 } 853 854 #endif 855 // when this fails, virtual registers are used before they are defined. 856 assert(false, "live_in set of first block must be empty"); 857 // bailout of if this occurs in product mode. 858 bailout("live_in set of first block not empty"); 859 } 860 } 861 862 863 // ********** Phase 4: build intervals 864 // (fills the list _intervals) 865 866 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) { 867 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type"); 868 LIR_Opr opr = value->operand(); 869 Constant* con = value->as_Constant(); 870 871 if ((con == NULL || con->is_pinned()) && opr->is_register()) { 872 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 873 add_use(opr, from, to, use_kind); 874 } 875 } 876 877 878 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) { 879 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind)); 880 assert(opr->is_register(), "should not be called otherwise"); 881 882 if (opr->is_virtual_register()) { 883 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 884 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register()); 885 886 } else { 887 int reg = reg_num(opr); 888 if (is_processed_reg_num(reg)) { 889 add_def(reg, def_pos, use_kind, opr->type_register()); 890 } 891 reg = reg_numHi(opr); 892 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 893 add_def(reg, def_pos, use_kind, opr->type_register()); 894 } 895 } 896 } 897 898 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) { 899 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind)); 900 assert(opr->is_register(), "should not be called otherwise"); 901 902 if (opr->is_virtual_register()) { 903 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 904 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register()); 905 906 } else { 907 int reg = reg_num(opr); 908 if (is_processed_reg_num(reg)) { 909 add_use(reg, from, to, use_kind, opr->type_register()); 910 } 911 reg = reg_numHi(opr); 912 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 913 add_use(reg, from, to, use_kind, opr->type_register()); 914 } 915 } 916 } 917 918 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) { 919 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind)); 920 assert(opr->is_register(), "should not be called otherwise"); 921 922 if (opr->is_virtual_register()) { 923 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 924 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register()); 925 926 } else { 927 int reg = reg_num(opr); 928 if (is_processed_reg_num(reg)) { 929 add_temp(reg, temp_pos, use_kind, opr->type_register()); 930 } 931 reg = reg_numHi(opr); 932 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 933 add_temp(reg, temp_pos, use_kind, opr->type_register()); 934 } 935 } 936 } 937 938 939 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) { 940 Interval* interval = interval_at(reg_num); 941 if (interval != NULL) { 942 assert(interval->reg_num() == reg_num, "wrong interval"); 943 944 if (type != T_ILLEGAL) { 945 interval->set_type(type); 946 } 947 948 Range* r = interval->first(); 949 if (r->from() <= def_pos) { 950 // Update the starting point (when a range is first created for a use, its 951 // start is the beginning of the current block until a def is encountered.) 952 r->set_from(def_pos); 953 interval->add_use_pos(def_pos, use_kind); 954 955 } else { 956 // Dead value - make vacuous interval 957 // also add use_kind for dead intervals 958 interval->add_range(def_pos, def_pos + 1); 959 interval->add_use_pos(def_pos, use_kind); 960 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos)); 961 } 962 963 } else { 964 // Dead value - make vacuous interval 965 // also add use_kind for dead intervals 966 interval = create_interval(reg_num); 967 if (type != T_ILLEGAL) { 968 interval->set_type(type); 969 } 970 971 interval->add_range(def_pos, def_pos + 1); 972 interval->add_use_pos(def_pos, use_kind); 973 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos)); 974 } 975 976 change_spill_definition_pos(interval, def_pos); 977 if (use_kind == noUse && interval->spill_state() <= startInMemory) { 978 // detection of method-parameters and roundfp-results 979 // TODO: move this directly to position where use-kind is computed 980 interval->set_spill_state(startInMemory); 981 } 982 } 983 984 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) { 985 Interval* interval = interval_at(reg_num); 986 if (interval == NULL) { 987 interval = create_interval(reg_num); 988 } 989 assert(interval->reg_num() == reg_num, "wrong interval"); 990 991 if (type != T_ILLEGAL) { 992 interval->set_type(type); 993 } 994 995 interval->add_range(from, to); 996 interval->add_use_pos(to, use_kind); 997 } 998 999 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) { 1000 Interval* interval = interval_at(reg_num); 1001 if (interval == NULL) { 1002 interval = create_interval(reg_num); 1003 } 1004 assert(interval->reg_num() == reg_num, "wrong interval"); 1005 1006 if (type != T_ILLEGAL) { 1007 interval->set_type(type); 1008 } 1009 1010 interval->add_range(temp_pos, temp_pos + 1); 1011 interval->add_use_pos(temp_pos, use_kind); 1012 } 1013 1014 1015 // the results of this functions are used for optimizing spilling and reloading 1016 // if the functions return shouldHaveRegister and the interval is spilled, 1017 // it is not reloaded to a register. 1018 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) { 1019 if (op->code() == lir_move) { 1020 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); 1021 LIR_Op1* move = (LIR_Op1*)op; 1022 LIR_Opr res = move->result_opr(); 1023 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); 1024 1025 if (result_in_memory) { 1026 // Begin of an interval with must_start_in_memory set. 1027 // This interval will always get a stack slot first, so return noUse. 1028 return noUse; 1029 1030 } else if (move->in_opr()->is_stack()) { 1031 // method argument (condition must be equal to handle_method_arguments) 1032 return noUse; 1033 1034 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { 1035 // Move from register to register 1036 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { 1037 // special handling of phi-function moves inside osr-entry blocks 1038 // input operand must have a register instead of output operand (leads to better register allocation) 1039 return shouldHaveRegister; 1040 } 1041 } 1042 } 1043 1044 if (opr->is_virtual() && 1045 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) { 1046 // result is a stack-slot, so prevent immediate reloading 1047 return noUse; 1048 } 1049 1050 // all other operands require a register 1051 return mustHaveRegister; 1052 } 1053 1054 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) { 1055 if (op->code() == lir_move) { 1056 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); 1057 LIR_Op1* move = (LIR_Op1*)op; 1058 LIR_Opr res = move->result_opr(); 1059 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); 1060 1061 if (result_in_memory) { 1062 // Move to an interval with must_start_in_memory set. 1063 // To avoid moves from stack to stack (not allowed) force the input operand to a register 1064 return mustHaveRegister; 1065 1066 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { 1067 // Move from register to register 1068 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { 1069 // special handling of phi-function moves inside osr-entry blocks 1070 // input operand must have a register instead of output operand (leads to better register allocation) 1071 return mustHaveRegister; 1072 } 1073 1074 // The input operand is not forced to a register (moves from stack to register are allowed), 1075 // but it is faster if the input operand is in a register 1076 return shouldHaveRegister; 1077 } 1078 } 1079 1080 1081 #ifdef X86 1082 if (op->code() == lir_cmove) { 1083 // conditional moves can handle stack operands 1084 assert(op->result_opr()->is_register(), "result must always be in a register"); 1085 return shouldHaveRegister; 1086 } 1087 1088 // optimizations for second input operand of arithmehtic operations on Intel 1089 // this operand is allowed to be on the stack in some cases 1090 BasicType opr_type = opr->type_register(); 1091 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) { 1092 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) { 1093 // SSE float instruction (T_DOUBLE only supported with SSE2) 1094 switch (op->code()) { 1095 case lir_cmp: 1096 case lir_add: 1097 case lir_sub: 1098 case lir_mul: 1099 case lir_div: 1100 { 1101 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1102 LIR_Op2* op2 = (LIR_Op2*)op; 1103 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1104 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1105 return shouldHaveRegister; 1106 } 1107 } 1108 } 1109 } else { 1110 // FPU stack float instruction 1111 switch (op->code()) { 1112 case lir_add: 1113 case lir_sub: 1114 case lir_mul: 1115 case lir_div: 1116 { 1117 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1118 LIR_Op2* op2 = (LIR_Op2*)op; 1119 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1120 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1121 return shouldHaveRegister; 1122 } 1123 } 1124 } 1125 } 1126 // We want to sometimes use logical operations on pointers, in particular in GC barriers. 1127 // Since 64bit logical operations do not current support operands on stack, we have to make sure 1128 // T_OBJECT doesn't get spilled along with T_LONG. 1129 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) { 1130 // integer instruction (note: long operands must always be in register) 1131 switch (op->code()) { 1132 case lir_cmp: 1133 case lir_add: 1134 case lir_sub: 1135 case lir_logic_and: 1136 case lir_logic_or: 1137 case lir_logic_xor: 1138 { 1139 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1140 LIR_Op2* op2 = (LIR_Op2*)op; 1141 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1142 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1143 return shouldHaveRegister; 1144 } 1145 } 1146 } 1147 } 1148 #endif // X86 1149 1150 // all other operands require a register 1151 return mustHaveRegister; 1152 } 1153 1154 1155 void LinearScan::handle_method_arguments(LIR_Op* op) { 1156 // special handling for method arguments (moves from stack to virtual register): 1157 // the interval gets no register assigned, but the stack slot. 1158 // it is split before the first use by the register allocator. 1159 1160 if (op->code() == lir_move) { 1161 assert(op->as_Op1() != NULL, "must be LIR_Op1"); 1162 LIR_Op1* move = (LIR_Op1*)op; 1163 1164 if (move->in_opr()->is_stack()) { 1165 #ifdef ASSERT 1166 int arg_size = compilation()->method()->arg_size(); 1167 LIR_Opr o = move->in_opr(); 1168 if (o->is_single_stack()) { 1169 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range"); 1170 } else if (o->is_double_stack()) { 1171 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range"); 1172 } else { 1173 ShouldNotReachHere(); 1174 } 1175 1176 assert(move->id() > 0, "invalid id"); 1177 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block"); 1178 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register"); 1179 1180 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr()))); 1181 #endif 1182 1183 Interval* interval = interval_at(reg_num(move->result_opr())); 1184 1185 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix()); 1186 interval->set_canonical_spill_slot(stack_slot); 1187 interval->assign_reg(stack_slot); 1188 } 1189 } 1190 } 1191 1192 void LinearScan::handle_doubleword_moves(LIR_Op* op) { 1193 // special handling for doubleword move from memory to register: 1194 // in this case the registers of the input address and the result 1195 // registers must not overlap -> add a temp range for the input registers 1196 if (op->code() == lir_move) { 1197 assert(op->as_Op1() != NULL, "must be LIR_Op1"); 1198 LIR_Op1* move = (LIR_Op1*)op; 1199 1200 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) { 1201 LIR_Address* address = move->in_opr()->as_address_ptr(); 1202 if (address != NULL) { 1203 if (address->base()->is_valid()) { 1204 add_temp(address->base(), op->id(), noUse); 1205 } 1206 if (address->index()->is_valid()) { 1207 add_temp(address->index(), op->id(), noUse); 1208 } 1209 } 1210 } 1211 } 1212 } 1213 1214 void LinearScan::add_register_hints(LIR_Op* op) { 1215 switch (op->code()) { 1216 case lir_move: // fall through 1217 case lir_convert: { 1218 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1"); 1219 LIR_Op1* move = (LIR_Op1*)op; 1220 1221 LIR_Opr move_from = move->in_opr(); 1222 LIR_Opr move_to = move->result_opr(); 1223 1224 if (move_to->is_register() && move_from->is_register()) { 1225 Interval* from = interval_at(reg_num(move_from)); 1226 Interval* to = interval_at(reg_num(move_to)); 1227 if (from != NULL && to != NULL) { 1228 to->set_register_hint(from); 1229 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num())); 1230 } 1231 } 1232 break; 1233 } 1234 case lir_cmove: { 1235 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2"); 1236 LIR_Op2* cmove = (LIR_Op2*)op; 1237 1238 LIR_Opr move_from = cmove->in_opr1(); 1239 LIR_Opr move_to = cmove->result_opr(); 1240 1241 if (move_to->is_register() && move_from->is_register()) { 1242 Interval* from = interval_at(reg_num(move_from)); 1243 Interval* to = interval_at(reg_num(move_to)); 1244 if (from != NULL && to != NULL) { 1245 to->set_register_hint(from); 1246 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); 1247 } 1248 } 1249 break; 1250 } 1251 } 1252 } 1253 1254 1255 void LinearScan::build_intervals() { 1256 TIME_LINEAR_SCAN(timer_build_intervals); 1257 1258 // initialize interval list with expected number of intervals 1259 // (32 is added to have some space for split children without having to resize the list) 1260 _intervals = GrowableArray<Interval*>(num_virtual_regs() + 32); 1261 // initialize all slots that are used by build_intervals 1262 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL); 1263 1264 // create a list with all caller-save registers (cpu, fpu, xmm) 1265 // when an instruction is a call, a temp range is created for all these registers 1266 int num_caller_save_registers = 0; 1267 int caller_save_registers[LinearScan::nof_regs]; 1268 1269 int i; 1270 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) { 1271 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i); 1272 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1273 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1274 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1275 } 1276 1277 // temp ranges for fpu registers are only created when the method has 1278 // virtual fpu operands. Otherwise no allocation for fpu registers is 1279 // perfomed and so the temp ranges would be useless 1280 if (has_fpu_registers()) { 1281 #ifdef X86 1282 if (UseSSE < 2) { 1283 #endif 1284 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) { 1285 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i); 1286 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1287 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1288 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1289 } 1290 #ifdef X86 1291 } 1292 if (UseSSE > 0) { 1293 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms(); 1294 for (i = 0; i < num_caller_save_xmm_regs; i ++) { 1295 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i); 1296 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1297 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1298 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1299 } 1300 } 1301 #endif 1302 } 1303 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds"); 1304 1305 1306 LIR_OpVisitState visitor; 1307 1308 // iterate all blocks in reverse order 1309 for (i = block_count() - 1; i >= 0; i--) { 1310 BlockBegin* block = block_at(i); 1311 LIR_OpList* instructions = block->lir()->instructions_list(); 1312 int block_from = block->first_lir_instruction_id(); 1313 int block_to = block->last_lir_instruction_id(); 1314 1315 assert(block_from == instructions->at(0)->id(), "must be"); 1316 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be"); 1317 1318 // Update intervals for registers live at the end of this block; 1319 BitMap live = block->live_out(); 1320 int size = (int)live.size(); 1321 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) { 1322 assert(live.at(number), "should not stop here otherwise"); 1323 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds"); 1324 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2)); 1325 1326 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL); 1327 1328 // add special use positions for loop-end blocks when the 1329 // interval is used anywhere inside this loop. It's possible 1330 // that the block was part of a non-natural loop, so it might 1331 // have an invalid loop index. 1332 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) && 1333 block->loop_index() != -1 && 1334 is_interval_in_loop(number, block->loop_index())) { 1335 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker); 1336 } 1337 } 1338 1339 // iterate all instructions of the block in reverse order. 1340 // skip the first instruction because it is always a label 1341 // definitions of intervals are processed before uses 1342 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); 1343 for (int j = instructions->length() - 1; j >= 1; j--) { 1344 LIR_Op* op = instructions->at(j); 1345 int op_id = op->id(); 1346 1347 // visit operation to collect all operands 1348 visitor.visit(op); 1349 1350 // add a temp range for each register if operation destroys caller-save registers 1351 if (visitor.has_call()) { 1352 for (int k = 0; k < num_caller_save_registers; k++) { 1353 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL); 1354 } 1355 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers")); 1356 } 1357 1358 // Add any platform dependent temps 1359 pd_add_temps(op); 1360 1361 // visit definitions (output and temp operands) 1362 int k, n; 1363 n = visitor.opr_count(LIR_OpVisitState::outputMode); 1364 for (k = 0; k < n; k++) { 1365 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); 1366 assert(opr->is_register(), "visitor should only return register operands"); 1367 add_def(opr, op_id, use_kind_of_output_operand(op, opr)); 1368 } 1369 1370 n = visitor.opr_count(LIR_OpVisitState::tempMode); 1371 for (k = 0; k < n; k++) { 1372 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); 1373 assert(opr->is_register(), "visitor should only return register operands"); 1374 add_temp(opr, op_id, mustHaveRegister); 1375 } 1376 1377 // visit uses (input operands) 1378 n = visitor.opr_count(LIR_OpVisitState::inputMode); 1379 for (k = 0; k < n; k++) { 1380 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); 1381 assert(opr->is_register(), "visitor should only return register operands"); 1382 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr)); 1383 } 1384 1385 // Add uses of live locals from interpreter's point of view for proper 1386 // debug information generation 1387 // Treat these operands as temp values (if the life range is extended 1388 // to a call site, the value would be in a register at the call otherwise) 1389 n = visitor.info_count(); 1390 for (k = 0; k < n; k++) { 1391 CodeEmitInfo* info = visitor.info_at(k); 1392 ValueStack* stack = info->stack(); 1393 for_each_state_value(stack, value, 1394 add_use(value, block_from, op_id + 1, noUse); 1395 ); 1396 } 1397 1398 // special steps for some instructions (especially moves) 1399 handle_method_arguments(op); 1400 handle_doubleword_moves(op); 1401 add_register_hints(op); 1402 1403 } // end of instruction iteration 1404 } // end of block iteration 1405 1406 1407 // add the range [0, 1[ to all fixed intervals 1408 // -> the register allocator need not handle unhandled fixed intervals 1409 for (int n = 0; n < LinearScan::nof_regs; n++) { 1410 Interval* interval = interval_at(n); 1411 if (interval != NULL) { 1412 interval->add_range(0, 1); 1413 } 1414 } 1415 } 1416 1417 1418 // ********** Phase 5: actual register allocation 1419 1420 int LinearScan::interval_cmp(Interval** a, Interval** b) { 1421 if (*a != NULL) { 1422 if (*b != NULL) { 1423 return (*a)->from() - (*b)->from(); 1424 } else { 1425 return -1; 1426 } 1427 } else { 1428 if (*b != NULL) { 1429 return 1; 1430 } else { 1431 return 0; 1432 } 1433 } 1434 } 1435 1436 #ifndef PRODUCT 1437 int interval_cmp(Interval* const& l, Interval* const& r) { 1438 return l->from() - r->from(); 1439 } 1440 1441 bool find_interval(Interval* interval, GrowableArray<Interval*>* intervals) { 1442 bool found; 1443 int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found); 1444 1445 if (!found) { 1446 return false; 1447 } 1448 1449 int from = interval->from(); 1450 1451 // The index we've found using binary search is pointing to an interval 1452 // that is defined in the same place as the interval we were looking for. 1453 // So now we have to look around that index and find exact interval. 1454 for (int i = idx; i >= 0; i--) { 1455 if (intervals->at(i) == interval) { 1456 return true; 1457 } 1458 if (intervals->at(i)->from() != from) { 1459 break; 1460 } 1461 } 1462 1463 for (int i = idx + 1; i < intervals->length(); i++) { 1464 if (intervals->at(i) == interval) { 1465 return true; 1466 } 1467 if (intervals->at(i)->from() != from) { 1468 break; 1469 } 1470 } 1471 1472 return false; 1473 } 1474 1475 bool LinearScan::is_sorted(GrowableArray<Interval*>* intervals) { 1476 int from = -1; 1477 int null_count = 0; 1478 1479 for (int i = 0; i < intervals->length(); i++) { 1480 Interval* it = intervals->at(i); 1481 if (it != NULL) { 1482 assert(from <= it->from(), "Intervals are unordered"); 1483 from = it->from(); 1484 } else { 1485 null_count++; 1486 } 1487 } 1488 1489 assert(null_count == 0, "Sorted intervals should not contain nulls"); 1490 1491 null_count = 0; 1492 1493 for (int i = 0; i < interval_count(); i++) { 1494 Interval* interval = interval_at(i); 1495 if (interval != NULL) { 1496 assert(find_interval(interval, intervals), "Lists do not contain same intervals"); 1497 } else { 1498 null_count++; 1499 } 1500 } 1501 1502 assert(interval_count() - null_count == intervals->length(), 1503 "Sorted list should contain the same amount of non-NULL intervals as unsorted list"); 1504 1505 return true; 1506 } 1507 #endif 1508 1509 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) { 1510 if (*prev != NULL) { 1511 (*prev)->set_next(interval); 1512 } else { 1513 *first = interval; 1514 } 1515 *prev = interval; 1516 } 1517 1518 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) { 1519 assert(is_sorted(_sorted_intervals), "interval list is not sorted"); 1520 1521 *list1 = *list2 = Interval::end(); 1522 1523 Interval* list1_prev = NULL; 1524 Interval* list2_prev = NULL; 1525 Interval* v; 1526 1527 const int n = _sorted_intervals->length(); 1528 for (int i = 0; i < n; i++) { 1529 v = _sorted_intervals->at(i); 1530 if (v == NULL) continue; 1531 1532 if (is_list1(v)) { 1533 add_to_list(list1, &list1_prev, v); 1534 } else if (is_list2 == NULL || is_list2(v)) { 1535 add_to_list(list2, &list2_prev, v); 1536 } 1537 } 1538 1539 if (list1_prev != NULL) list1_prev->set_next(Interval::end()); 1540 if (list2_prev != NULL) list2_prev->set_next(Interval::end()); 1541 1542 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel"); 1543 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel"); 1544 } 1545 1546 1547 void LinearScan::sort_intervals_before_allocation() { 1548 TIME_LINEAR_SCAN(timer_sort_intervals_before); 1549 1550 if (_needs_full_resort) { 1551 // There is no known reason why this should occur but just in case... 1552 assert(false, "should never occur"); 1553 // Re-sort existing interval list because an Interval::from() has changed 1554 _sorted_intervals->sort(interval_cmp); 1555 _needs_full_resort = false; 1556 } 1557 1558 GrowableArray<Interval*>* unsorted_list = &_intervals; 1559 int unsorted_len = unsorted_list->length(); 1560 int sorted_len = 0; 1561 int unsorted_idx; 1562 int sorted_idx = 0; 1563 int sorted_from_max = -1; 1564 1565 // calc number of items for sorted list (sorted list must not contain NULL values) 1566 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { 1567 if (unsorted_list->at(unsorted_idx) != NULL) { 1568 sorted_len++; 1569 } 1570 } 1571 GrowableArray<Interval*>* sorted_list = new GrowableArray<Interval*>(sorted_len, sorted_len, NULL); 1572 1573 // special sorting algorithm: the original interval-list is almost sorted, 1574 // only some intervals are swapped. So this is much faster than a complete QuickSort 1575 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { 1576 Interval* cur_interval = unsorted_list->at(unsorted_idx); 1577 1578 if (cur_interval != NULL) { 1579 int cur_from = cur_interval->from(); 1580 1581 if (sorted_from_max <= cur_from) { 1582 sorted_list->at_put(sorted_idx++, cur_interval); 1583 sorted_from_max = cur_interval->from(); 1584 } else { 1585 // the asumption that the intervals are already sorted failed, 1586 // so this interval must be sorted in manually 1587 int j; 1588 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) { 1589 sorted_list->at_put(j + 1, sorted_list->at(j)); 1590 } 1591 sorted_list->at_put(j + 1, cur_interval); 1592 sorted_idx++; 1593 } 1594 } 1595 } 1596 _sorted_intervals = sorted_list; 1597 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1598 } 1599 1600 void LinearScan::sort_intervals_after_allocation() { 1601 TIME_LINEAR_SCAN(timer_sort_intervals_after); 1602 1603 if (_needs_full_resort) { 1604 // Re-sort existing interval list because an Interval::from() has changed 1605 _sorted_intervals->sort(interval_cmp); 1606 _needs_full_resort = false; 1607 } 1608 1609 GrowableArray<Interval*>* old_list = _sorted_intervals; 1610 GrowableArray<Interval*>* new_list = _new_intervals_from_allocation; 1611 int old_len = old_list->length(); 1612 int new_len = new_list->length(); 1613 1614 if (new_len == 0) { 1615 // no intervals have been added during allocation, so sorted list is already up to date 1616 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1617 return; 1618 } 1619 1620 // conventional sort-algorithm for new intervals 1621 new_list->sort(interval_cmp); 1622 1623 // merge old and new list (both already sorted) into one combined list 1624 int combined_list_len = old_len + new_len; 1625 GrowableArray<Interval*>* combined_list = new GrowableArray<Interval*>(combined_list_len, combined_list_len, NULL); 1626 int old_idx = 0; 1627 int new_idx = 0; 1628 1629 while (old_idx + new_idx < old_len + new_len) { 1630 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) { 1631 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx)); 1632 old_idx++; 1633 } else { 1634 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx)); 1635 new_idx++; 1636 } 1637 } 1638 1639 _sorted_intervals = combined_list; 1640 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1641 } 1642 1643 1644 void LinearScan::allocate_registers() { 1645 TIME_LINEAR_SCAN(timer_allocate_registers); 1646 1647 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals; 1648 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals; 1649 1650 // allocate cpu registers 1651 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, 1652 is_precolored_cpu_interval, is_virtual_cpu_interval); 1653 1654 // allocate fpu registers 1655 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, 1656 is_precolored_fpu_interval, is_virtual_fpu_interval); 1657 1658 // the fpu interval allocation cannot be moved down below with the fpu section as 1659 // the cpu_lsw.walk() changes interval positions. 1660 1661 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals); 1662 cpu_lsw.walk(); 1663 cpu_lsw.finish_allocation(); 1664 1665 if (has_fpu_registers()) { 1666 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals); 1667 fpu_lsw.walk(); 1668 fpu_lsw.finish_allocation(); 1669 } 1670 } 1671 1672 1673 // ********** Phase 6: resolve data flow 1674 // (insert moves at edges between blocks if intervals have been split) 1675 1676 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode 1677 // instead of returning NULL 1678 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) { 1679 Interval* result = interval->split_child_at_op_id(op_id, mode); 1680 if (result != NULL) { 1681 return result; 1682 } 1683 1684 assert(false, "must find an interval, but do a clean bailout in product mode"); 1685 result = new Interval(LIR_OprDesc::vreg_base); 1686 result->assign_reg(0); 1687 result->set_type(T_INT); 1688 BAILOUT_("LinearScan: interval is NULL", result); 1689 } 1690 1691 1692 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) { 1693 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1694 assert(interval_at(reg_num) != NULL, "no interval found"); 1695 1696 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode); 1697 } 1698 1699 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) { 1700 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1701 assert(interval_at(reg_num) != NULL, "no interval found"); 1702 1703 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode); 1704 } 1705 1706 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) { 1707 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1708 assert(interval_at(reg_num) != NULL, "no interval found"); 1709 1710 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode); 1711 } 1712 1713 1714 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { 1715 DEBUG_ONLY(move_resolver.check_empty()); 1716 1717 const int num_regs = num_virtual_regs(); 1718 const int size = live_set_size(); 1719 const BitMap live_at_edge = to_block->live_in(); 1720 1721 // visit all registers where the live_at_edge bit is set 1722 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { 1723 assert(r < num_regs, "live information set for not exisiting interval"); 1724 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge"); 1725 1726 Interval* from_interval = interval_at_block_end(from_block, r); 1727 Interval* to_interval = interval_at_block_begin(to_block, r); 1728 1729 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) { 1730 // need to insert move instruction 1731 move_resolver.add_mapping(from_interval, to_interval); 1732 } 1733 } 1734 } 1735 1736 1737 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { 1738 if (from_block->number_of_sux() <= 1) { 1739 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id())); 1740 1741 LIR_OpList* instructions = from_block->lir()->instructions_list(); 1742 LIR_OpBranch* branch = instructions->last()->as_OpBranch(); 1743 if (branch != NULL) { 1744 // insert moves before branch 1745 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); 1746 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2); 1747 } else { 1748 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1); 1749 } 1750 1751 } else { 1752 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id())); 1753 #ifdef ASSERT 1754 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label"); 1755 1756 // because the number of predecessor edges matches the number of 1757 // successor edges, blocks which are reached by switch statements 1758 // may have be more than one predecessor but it will be guaranteed 1759 // that all predecessors will be the same. 1760 for (int i = 0; i < to_block->number_of_preds(); i++) { 1761 assert(from_block == to_block->pred_at(i), "all critical edges must be broken"); 1762 } 1763 #endif 1764 1765 move_resolver.set_insert_position(to_block->lir(), 0); 1766 } 1767 } 1768 1769 1770 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split 1771 void LinearScan::resolve_data_flow() { 1772 TIME_LINEAR_SCAN(timer_resolve_data_flow); 1773 1774 int num_blocks = block_count(); 1775 MoveResolver move_resolver(this); 1776 BitMap block_completed(num_blocks); block_completed.clear(); 1777 BitMap already_resolved(num_blocks); already_resolved.clear(); 1778 1779 int i; 1780 for (i = 0; i < num_blocks; i++) { 1781 BlockBegin* block = block_at(i); 1782 1783 // check if block has only one predecessor and only one successor 1784 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) { 1785 LIR_OpList* instructions = block->lir()->instructions_list(); 1786 assert(instructions->at(0)->code() == lir_label, "block must start with label"); 1787 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch"); 1788 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch"); 1789 1790 // check if block is empty (only label and branch) 1791 if (instructions->length() == 2) { 1792 BlockBegin* pred = block->pred_at(0); 1793 BlockBegin* sux = block->sux_at(0); 1794 1795 // prevent optimization of two consecutive blocks 1796 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) { 1797 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id())); 1798 block_completed.set_bit(block->linear_scan_number()); 1799 1800 // directly resolve between pred and sux (without looking at the empty block between) 1801 resolve_collect_mappings(pred, sux, move_resolver); 1802 if (move_resolver.has_mappings()) { 1803 move_resolver.set_insert_position(block->lir(), 0); 1804 move_resolver.resolve_and_append_moves(); 1805 } 1806 } 1807 } 1808 } 1809 } 1810 1811 1812 for (i = 0; i < num_blocks; i++) { 1813 if (!block_completed.at(i)) { 1814 BlockBegin* from_block = block_at(i); 1815 already_resolved.set_from(block_completed); 1816 1817 int num_sux = from_block->number_of_sux(); 1818 for (int s = 0; s < num_sux; s++) { 1819 BlockBegin* to_block = from_block->sux_at(s); 1820 1821 // check for duplicate edges between the same blocks (can happen with switch blocks) 1822 if (!already_resolved.at(to_block->linear_scan_number())) { 1823 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id())); 1824 already_resolved.set_bit(to_block->linear_scan_number()); 1825 1826 // collect all intervals that have been split between from_block and to_block 1827 resolve_collect_mappings(from_block, to_block, move_resolver); 1828 if (move_resolver.has_mappings()) { 1829 resolve_find_insert_pos(from_block, to_block, move_resolver); 1830 move_resolver.resolve_and_append_moves(); 1831 } 1832 } 1833 } 1834 } 1835 } 1836 } 1837 1838 1839 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) { 1840 if (interval_at(reg_num) == NULL) { 1841 // if a phi function is never used, no interval is created -> ignore this 1842 return; 1843 } 1844 1845 Interval* interval = interval_at_block_begin(block, reg_num); 1846 int reg = interval->assigned_reg(); 1847 int regHi = interval->assigned_regHi(); 1848 1849 if ((reg < nof_regs && interval->always_in_memory()) || 1850 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { 1851 // the interval is split to get a short range that is located on the stack 1852 // in the following two cases: 1853 // * the interval started in memory (e.g. method parameter), but is currently in a register 1854 // this is an optimization for exception handling that reduces the number of moves that 1855 // are necessary for resolving the states when an exception uses this exception handler 1856 // * the interval would be on the fpu stack at the begin of the exception handler 1857 // this is not allowed because of the complicated fpu stack handling on Intel 1858 1859 // range that will be spilled to memory 1860 int from_op_id = block->first_lir_instruction_id(); 1861 int to_op_id = from_op_id + 1; // short live range of length 1 1862 assert(interval->from() <= from_op_id && interval->to() >= to_op_id, 1863 "no split allowed between exception entry and first instruction"); 1864 1865 if (interval->from() != from_op_id) { 1866 // the part before from_op_id is unchanged 1867 interval = interval->split(from_op_id); 1868 interval->assign_reg(reg, regHi); 1869 append_interval(interval); 1870 } else { 1871 _needs_full_resort = true; 1872 } 1873 assert(interval->from() == from_op_id, "must be true now"); 1874 1875 Interval* spilled_part = interval; 1876 if (interval->to() != to_op_id) { 1877 // the part after to_op_id is unchanged 1878 spilled_part = interval->split_from_start(to_op_id); 1879 append_interval(spilled_part); 1880 move_resolver.add_mapping(spilled_part, interval); 1881 } 1882 assign_spill_slot(spilled_part); 1883 1884 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking"); 1885 } 1886 } 1887 1888 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) { 1889 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise"); 1890 DEBUG_ONLY(move_resolver.check_empty()); 1891 1892 // visit all registers where the live_in bit is set 1893 int size = live_set_size(); 1894 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { 1895 resolve_exception_entry(block, r, move_resolver); 1896 } 1897 1898 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately 1899 for_each_phi_fun(block, phi, 1900 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver) 1901 ); 1902 1903 if (move_resolver.has_mappings()) { 1904 // insert moves after first instruction 1905 move_resolver.set_insert_position(block->lir(), 0); 1906 move_resolver.resolve_and_append_moves(); 1907 } 1908 } 1909 1910 1911 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) { 1912 if (interval_at(reg_num) == NULL) { 1913 // if a phi function is never used, no interval is created -> ignore this 1914 return; 1915 } 1916 1917 // the computation of to_interval is equal to resolve_collect_mappings, 1918 // but from_interval is more complicated because of phi functions 1919 BlockBegin* to_block = handler->entry_block(); 1920 Interval* to_interval = interval_at_block_begin(to_block, reg_num); 1921 1922 if (phi != NULL) { 1923 // phi function of the exception entry block 1924 // no moves are created for this phi function in the LIR_Generator, so the 1925 // interval at the throwing instruction must be searched using the operands 1926 // of the phi function 1927 Value from_value = phi->operand_at(handler->phi_operand()); 1928 1929 // with phi functions it can happen that the same from_value is used in 1930 // multiple mappings, so notify move-resolver that this is allowed 1931 move_resolver.set_multiple_reads_allowed(); 1932 1933 Constant* con = from_value->as_Constant(); 1934 if (con != NULL && !con->is_pinned()) { 1935 // unpinned constants may have no register, so add mapping from constant to interval 1936 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval); 1937 } else { 1938 // search split child at the throwing op_id 1939 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id); 1940 move_resolver.add_mapping(from_interval, to_interval); 1941 } 1942 1943 } else { 1944 // no phi function, so use reg_num also for from_interval 1945 // search split child at the throwing op_id 1946 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id); 1947 if (from_interval != to_interval) { 1948 // optimization to reduce number of moves: when to_interval is on stack and 1949 // the stack slot is known to be always correct, then no move is necessary 1950 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) { 1951 move_resolver.add_mapping(from_interval, to_interval); 1952 } 1953 } 1954 } 1955 } 1956 1957 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) { 1958 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id)); 1959 1960 DEBUG_ONLY(move_resolver.check_empty()); 1961 assert(handler->lir_op_id() == -1, "already processed this xhandler"); 1962 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id)); 1963 assert(handler->entry_code() == NULL, "code already present"); 1964 1965 // visit all registers where the live_in bit is set 1966 BlockBegin* block = handler->entry_block(); 1967 int size = live_set_size(); 1968 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { 1969 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver); 1970 } 1971 1972 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately 1973 for_each_phi_fun(block, phi, 1974 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver) 1975 ); 1976 1977 if (move_resolver.has_mappings()) { 1978 LIR_List* entry_code = new LIR_List(compilation()); 1979 move_resolver.set_insert_position(entry_code, 0); 1980 move_resolver.resolve_and_append_moves(); 1981 1982 entry_code->jump(handler->entry_block()); 1983 handler->set_entry_code(entry_code); 1984 } 1985 } 1986 1987 1988 void LinearScan::resolve_exception_handlers() { 1989 MoveResolver move_resolver(this); 1990 LIR_OpVisitState visitor; 1991 int num_blocks = block_count(); 1992 1993 int i; 1994 for (i = 0; i < num_blocks; i++) { 1995 BlockBegin* block = block_at(i); 1996 if (block->is_set(BlockBegin::exception_entry_flag)) { 1997 resolve_exception_entry(block, move_resolver); 1998 } 1999 } 2000 2001 for (i = 0; i < num_blocks; i++) { 2002 BlockBegin* block = block_at(i); 2003 LIR_List* ops = block->lir(); 2004 int num_ops = ops->length(); 2005 2006 // iterate all instructions of the block. skip the first because it is always a label 2007 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label"); 2008 for (int j = 1; j < num_ops; j++) { 2009 LIR_Op* op = ops->at(j); 2010 int op_id = op->id(); 2011 2012 if (op_id != -1 && has_info(op_id)) { 2013 // visit operation to collect all operands 2014 visitor.visit(op); 2015 assert(visitor.info_count() > 0, "should not visit otherwise"); 2016 2017 XHandlers* xhandlers = visitor.all_xhandler(); 2018 int n = xhandlers->length(); 2019 for (int k = 0; k < n; k++) { 2020 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver); 2021 } 2022 2023 #ifdef ASSERT 2024 } else { 2025 visitor.visit(op); 2026 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); 2027 #endif 2028 } 2029 } 2030 } 2031 } 2032 2033 2034 // ********** Phase 7: assign register numbers back to LIR 2035 // (includes computation of debug information and oop maps) 2036 2037 VMReg LinearScan::vm_reg_for_interval(Interval* interval) { 2038 VMReg reg = interval->cached_vm_reg(); 2039 if (!reg->is_valid() ) { 2040 reg = vm_reg_for_operand(operand_for_interval(interval)); 2041 interval->set_cached_vm_reg(reg); 2042 } 2043 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value"); 2044 return reg; 2045 } 2046 2047 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) { 2048 assert(opr->is_oop(), "currently only implemented for oop operands"); 2049 return frame_map()->regname(opr); 2050 } 2051 2052 2053 LIR_Opr LinearScan::operand_for_interval(Interval* interval) { 2054 LIR_Opr opr = interval->cached_opr(); 2055 if (opr->is_illegal()) { 2056 opr = calc_operand_for_interval(interval); 2057 interval->set_cached_opr(opr); 2058 } 2059 2060 assert(opr == calc_operand_for_interval(interval), "wrong cached value"); 2061 return opr; 2062 } 2063 2064 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) { 2065 int assigned_reg = interval->assigned_reg(); 2066 BasicType type = interval->type(); 2067 2068 if (assigned_reg >= nof_regs) { 2069 // stack slot 2070 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2071 return LIR_OprFact::stack(assigned_reg - nof_regs, type); 2072 2073 } else { 2074 // register 2075 switch (type) { 2076 case T_OBJECT: { 2077 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2078 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2079 return LIR_OprFact::single_cpu_oop(assigned_reg); 2080 } 2081 2082 case T_ADDRESS: { 2083 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2084 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2085 return LIR_OprFact::single_cpu_address(assigned_reg); 2086 } 2087 2088 case T_METADATA: { 2089 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2090 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2091 return LIR_OprFact::single_cpu_metadata(assigned_reg); 2092 } 2093 2094 #ifdef __SOFTFP__ 2095 case T_FLOAT: // fall through 2096 #endif // __SOFTFP__ 2097 case T_INT: { 2098 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2099 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2100 return LIR_OprFact::single_cpu(assigned_reg); 2101 } 2102 2103 #ifdef __SOFTFP__ 2104 case T_DOUBLE: // fall through 2105 #endif // __SOFTFP__ 2106 case T_LONG: { 2107 int assigned_regHi = interval->assigned_regHi(); 2108 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2109 assert(num_physical_regs(T_LONG) == 1 || 2110 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); 2111 2112 assert(assigned_reg != assigned_regHi, "invalid allocation"); 2113 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi, 2114 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)"); 2115 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match"); 2116 if (requires_adjacent_regs(T_LONG)) { 2117 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even"); 2118 } 2119 2120 #ifdef _LP64 2121 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); 2122 #else 2123 #if defined(SPARC) || defined(PPC32) 2124 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); 2125 #else 2126 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); 2127 #endif // SPARC 2128 #endif // LP64 2129 } 2130 2131 #ifndef __SOFTFP__ 2132 case T_FLOAT: { 2133 #ifdef X86 2134 if (UseSSE >= 1) { 2135 int last_xmm_reg = pd_last_xmm_reg; 2136 #ifdef _LP64 2137 if (UseAVX < 3) { 2138 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; 2139 } 2140 #endif 2141 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register"); 2142 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2143 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg); 2144 } 2145 #endif 2146 2147 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2148 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2149 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); 2150 } 2151 2152 case T_DOUBLE: { 2153 #ifdef X86 2154 if (UseSSE >= 2) { 2155 int last_xmm_reg = pd_last_xmm_reg; 2156 #ifdef _LP64 2157 if (UseAVX < 3) { 2158 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; 2159 } 2160 #endif 2161 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register"); 2162 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)"); 2163 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg); 2164 } 2165 #endif 2166 2167 #ifdef SPARC 2168 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2169 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); 2170 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); 2171 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); 2172 #elif defined(ARM32) 2173 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2174 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); 2175 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); 2176 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); 2177 #else 2178 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2179 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)"); 2180 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg); 2181 #endif 2182 return result; 2183 } 2184 #endif // __SOFTFP__ 2185 2186 default: { 2187 ShouldNotReachHere(); 2188 return LIR_OprFact::illegalOpr; 2189 } 2190 } 2191 } 2192 } 2193 2194 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) { 2195 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set"); 2196 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type()); 2197 } 2198 2199 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) { 2200 assert(opr->is_virtual(), "should not call this otherwise"); 2201 2202 Interval* interval = interval_at(opr->vreg_number()); 2203 assert(interval != NULL, "interval must exist"); 2204 2205 if (op_id != -1) { 2206 #ifdef ASSERT 2207 BlockBegin* block = block_of_op_with_id(op_id); 2208 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) { 2209 // check if spill moves could have been appended at the end of this block, but 2210 // before the branch instruction. So the split child information for this branch would 2211 // be incorrect. 2212 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch(); 2213 if (branch != NULL) { 2214 if (block->live_out().at(opr->vreg_number())) { 2215 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); 2216 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)"); 2217 } 2218 } 2219 } 2220 #endif 2221 2222 // operands are not changed when an interval is split during allocation, 2223 // so search the right interval here 2224 interval = split_child_at_op_id(interval, op_id, mode); 2225 } 2226 2227 LIR_Opr res = operand_for_interval(interval); 2228 2229 #ifdef X86 2230 // new semantic for is_last_use: not only set on definite end of interval, 2231 // but also before hole 2232 // This may still miss some cases (e.g. for dead values), but it is not necessary that the 2233 // last use information is completely correct 2234 // information is only needed for fpu stack allocation 2235 if (res->is_fpu_register()) { 2236 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) { 2237 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow"); 2238 res = res->make_last_use(); 2239 } 2240 } 2241 #endif 2242 2243 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation"); 2244 2245 return res; 2246 } 2247 2248 2249 #ifdef ASSERT 2250 // some methods used to check correctness of debug information 2251 2252 void assert_no_register_values(GrowableArray<ScopeValue*>* values) { 2253 if (values == NULL) { 2254 return; 2255 } 2256 2257 for (int i = 0; i < values->length(); i++) { 2258 ScopeValue* value = values->at(i); 2259 2260 if (value->is_location()) { 2261 Location location = ((LocationValue*)value)->location(); 2262 assert(location.where() == Location::on_stack, "value is in register"); 2263 } 2264 } 2265 } 2266 2267 void assert_no_register_values(GrowableArray<MonitorValue*>* values) { 2268 if (values == NULL) { 2269 return; 2270 } 2271 2272 for (int i = 0; i < values->length(); i++) { 2273 MonitorValue* value = values->at(i); 2274 2275 if (value->owner()->is_location()) { 2276 Location location = ((LocationValue*)value->owner())->location(); 2277 assert(location.where() == Location::on_stack, "owner is in register"); 2278 } 2279 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register"); 2280 } 2281 } 2282 2283 void assert_equal(Location l1, Location l2) { 2284 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), ""); 2285 } 2286 2287 void assert_equal(ScopeValue* v1, ScopeValue* v2) { 2288 if (v1->is_location()) { 2289 assert(v2->is_location(), ""); 2290 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location()); 2291 } else if (v1->is_constant_int()) { 2292 assert(v2->is_constant_int(), ""); 2293 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), ""); 2294 } else if (v1->is_constant_double()) { 2295 assert(v2->is_constant_double(), ""); 2296 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), ""); 2297 } else if (v1->is_constant_long()) { 2298 assert(v2->is_constant_long(), ""); 2299 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), ""); 2300 } else if (v1->is_constant_oop()) { 2301 assert(v2->is_constant_oop(), ""); 2302 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), ""); 2303 } else { 2304 ShouldNotReachHere(); 2305 } 2306 } 2307 2308 void assert_equal(MonitorValue* m1, MonitorValue* m2) { 2309 assert_equal(m1->owner(), m2->owner()); 2310 assert_equal(m1->basic_lock(), m2->basic_lock()); 2311 } 2312 2313 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) { 2314 assert(d1->scope() == d2->scope(), "not equal"); 2315 assert(d1->bci() == d2->bci(), "not equal"); 2316 2317 if (d1->locals() != NULL) { 2318 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal"); 2319 assert(d1->locals()->length() == d2->locals()->length(), "not equal"); 2320 for (int i = 0; i < d1->locals()->length(); i++) { 2321 assert_equal(d1->locals()->at(i), d2->locals()->at(i)); 2322 } 2323 } else { 2324 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal"); 2325 } 2326 2327 if (d1->expressions() != NULL) { 2328 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal"); 2329 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal"); 2330 for (int i = 0; i < d1->expressions()->length(); i++) { 2331 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i)); 2332 } 2333 } else { 2334 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal"); 2335 } 2336 2337 if (d1->monitors() != NULL) { 2338 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal"); 2339 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal"); 2340 for (int i = 0; i < d1->monitors()->length(); i++) { 2341 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i)); 2342 } 2343 } else { 2344 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal"); 2345 } 2346 2347 if (d1->caller() != NULL) { 2348 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal"); 2349 assert_equal(d1->caller(), d2->caller()); 2350 } else { 2351 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal"); 2352 } 2353 } 2354 2355 void check_stack_depth(CodeEmitInfo* info, int stack_end) { 2356 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) { 2357 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci()); 2358 switch (code) { 2359 case Bytecodes::_ifnull : // fall through 2360 case Bytecodes::_ifnonnull : // fall through 2361 case Bytecodes::_ifeq : // fall through 2362 case Bytecodes::_ifne : // fall through 2363 case Bytecodes::_iflt : // fall through 2364 case Bytecodes::_ifge : // fall through 2365 case Bytecodes::_ifgt : // fall through 2366 case Bytecodes::_ifle : // fall through 2367 case Bytecodes::_if_icmpeq : // fall through 2368 case Bytecodes::_if_icmpne : // fall through 2369 case Bytecodes::_if_icmplt : // fall through 2370 case Bytecodes::_if_icmpge : // fall through 2371 case Bytecodes::_if_icmpgt : // fall through 2372 case Bytecodes::_if_icmple : // fall through 2373 case Bytecodes::_if_acmpeq : // fall through 2374 case Bytecodes::_if_acmpne : 2375 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode"); 2376 break; 2377 } 2378 } 2379 } 2380 2381 #endif // ASSERT 2382 2383 2384 IntervalWalker* LinearScan::init_compute_oop_maps() { 2385 // setup lists of potential oops for walking 2386 Interval* oop_intervals; 2387 Interval* non_oop_intervals; 2388 2389 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL); 2390 2391 // intervals that have no oops inside need not to be processed 2392 // to ensure a walking until the last instruction id, add a dummy interval 2393 // with a high operation id 2394 non_oop_intervals = new Interval(any_reg); 2395 non_oop_intervals->add_range(max_jint - 2, max_jint - 1); 2396 2397 return new IntervalWalker(this, oop_intervals, non_oop_intervals); 2398 } 2399 2400 2401 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) { 2402 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id())); 2403 2404 // walk before the current operation -> intervals that start at 2405 // the operation (= output operands of the operation) are not 2406 // included in the oop map 2407 iw->walk_before(op->id()); 2408 2409 int frame_size = frame_map()->framesize(); 2410 int arg_count = frame_map()->oop_map_arg_count(); 2411 OopMap* map = new OopMap(frame_size, arg_count); 2412 2413 // Iterate through active intervals 2414 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) { 2415 int assigned_reg = interval->assigned_reg(); 2416 2417 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise"); 2418 assert(interval->assigned_regHi() == any_reg, "oop must be single word"); 2419 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found"); 2420 2421 // Check if this range covers the instruction. Intervals that 2422 // start or end at the current operation are not included in the 2423 // oop map, except in the case of patching moves. For patching 2424 // moves, any intervals which end at this instruction are included 2425 // in the oop map since we may safepoint while doing the patch 2426 // before we've consumed the inputs. 2427 if (op->is_patching() || op->id() < interval->current_to()) { 2428 2429 // caller-save registers must not be included into oop-maps at calls 2430 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten"); 2431 2432 VMReg name = vm_reg_for_interval(interval); 2433 set_oop(map, name); 2434 2435 // Spill optimization: when the stack value is guaranteed to be always correct, 2436 // then it must be added to the oop map even if the interval is currently in a register 2437 if (interval->always_in_memory() && 2438 op->id() > interval->spill_definition_pos() && 2439 interval->assigned_reg() != interval->canonical_spill_slot()) { 2440 assert(interval->spill_definition_pos() > 0, "position not set correctly"); 2441 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned"); 2442 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice"); 2443 2444 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs)); 2445 } 2446 } 2447 } 2448 2449 // add oops from lock stack 2450 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack"); 2451 int locks_count = info->stack()->total_locks_size(); 2452 for (int i = 0; i < locks_count; i++) { 2453 set_oop(map, frame_map()->monitor_object_regname(i)); 2454 } 2455 2456 return map; 2457 } 2458 2459 2460 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) { 2461 assert(visitor.info_count() > 0, "no oop map needed"); 2462 2463 // compute oop_map only for first CodeEmitInfo 2464 // because it is (in most cases) equal for all other infos of the same operation 2465 CodeEmitInfo* first_info = visitor.info_at(0); 2466 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call()); 2467 2468 for (int i = 0; i < visitor.info_count(); i++) { 2469 CodeEmitInfo* info = visitor.info_at(i); 2470 OopMap* oop_map = first_oop_map; 2471 2472 // compute worst case interpreter size in case of a deoptimization 2473 _compilation->update_interpreter_frame_size(info->interpreter_frame_size()); 2474 2475 if (info->stack()->locks_size() != first_info->stack()->locks_size()) { 2476 // this info has a different number of locks then the precomputed oop map 2477 // (possible for lock and unlock instructions) -> compute oop map with 2478 // correct lock information 2479 oop_map = compute_oop_map(iw, op, info, visitor.has_call()); 2480 } 2481 2482 if (info->_oop_map == NULL) { 2483 info->_oop_map = oop_map; 2484 } else { 2485 // a CodeEmitInfo can not be shared between different LIR-instructions 2486 // because interval splitting can occur anywhere between two instructions 2487 // and so the oop maps must be different 2488 // -> check if the already set oop_map is exactly the one calculated for this operation 2489 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions"); 2490 } 2491 } 2492 } 2493 2494 2495 // frequently used constants 2496 // Allocate them with new so they are never destroyed (otherwise, a 2497 // forced exit could destroy these objects while they are still in 2498 // use). 2499 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL); 2500 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1); 2501 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0); 2502 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1); 2503 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2); 2504 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location()); 2505 2506 void LinearScan::init_compute_debug_info() { 2507 // cache for frequently used scope values 2508 // (cpu registers and stack slots) 2509 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL); 2510 } 2511 2512 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) { 2513 Location loc; 2514 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) { 2515 bailout("too large frame"); 2516 } 2517 ScopeValue* object_scope_value = new LocationValue(loc); 2518 2519 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) { 2520 bailout("too large frame"); 2521 } 2522 return new MonitorValue(object_scope_value, loc); 2523 } 2524 2525 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) { 2526 Location loc; 2527 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) { 2528 bailout("too large frame"); 2529 } 2530 return new LocationValue(loc); 2531 } 2532 2533 2534 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { 2535 assert(opr->is_constant(), "should not be called otherwise"); 2536 2537 LIR_Const* c = opr->as_constant_ptr(); 2538 BasicType t = c->type(); 2539 switch (t) { 2540 case T_OBJECT: { 2541 jobject value = c->as_jobject(); 2542 if (value == NULL) { 2543 scope_values->append(_oop_null_scope_value); 2544 } else { 2545 scope_values->append(new ConstantOopWriteValue(c->as_jobject())); 2546 } 2547 return 1; 2548 } 2549 2550 case T_INT: // fall through 2551 case T_FLOAT: { 2552 int value = c->as_jint_bits(); 2553 switch (value) { 2554 case -1: scope_values->append(_int_m1_scope_value); break; 2555 case 0: scope_values->append(_int_0_scope_value); break; 2556 case 1: scope_values->append(_int_1_scope_value); break; 2557 case 2: scope_values->append(_int_2_scope_value); break; 2558 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break; 2559 } 2560 return 1; 2561 } 2562 2563 case T_LONG: // fall through 2564 case T_DOUBLE: { 2565 #ifdef _LP64 2566 scope_values->append(_int_0_scope_value); 2567 scope_values->append(new ConstantLongValue(c->as_jlong_bits())); 2568 #else 2569 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) { 2570 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); 2571 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); 2572 } else { 2573 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); 2574 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); 2575 } 2576 #endif 2577 return 2; 2578 } 2579 2580 case T_ADDRESS: { 2581 #ifdef _LP64 2582 scope_values->append(new ConstantLongValue(c->as_jint())); 2583 #else 2584 scope_values->append(new ConstantIntValue(c->as_jint())); 2585 #endif 2586 return 1; 2587 } 2588 2589 default: 2590 ShouldNotReachHere(); 2591 return -1; 2592 } 2593 } 2594 2595 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { 2596 if (opr->is_single_stack()) { 2597 int stack_idx = opr->single_stack_ix(); 2598 bool is_oop = opr->is_oop_register(); 2599 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0); 2600 2601 ScopeValue* sv = _scope_value_cache.at(cache_idx); 2602 if (sv == NULL) { 2603 Location::Type loc_type = is_oop ? Location::oop : Location::normal; 2604 sv = location_for_name(stack_idx, loc_type); 2605 _scope_value_cache.at_put(cache_idx, sv); 2606 } 2607 2608 // check if cached value is correct 2609 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal))); 2610 2611 scope_values->append(sv); 2612 return 1; 2613 2614 } else if (opr->is_single_cpu()) { 2615 bool is_oop = opr->is_oop_register(); 2616 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0); 2617 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long); 2618 2619 ScopeValue* sv = _scope_value_cache.at(cache_idx); 2620 if (sv == NULL) { 2621 Location::Type loc_type = is_oop ? Location::oop : int_loc_type; 2622 VMReg rname = frame_map()->regname(opr); 2623 sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); 2624 _scope_value_cache.at_put(cache_idx, sv); 2625 } 2626 2627 // check if cached value is correct 2628 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr))))); 2629 2630 scope_values->append(sv); 2631 return 1; 2632 2633 #ifdef X86 2634 } else if (opr->is_single_xmm()) { 2635 VMReg rname = opr->as_xmm_float_reg()->as_VMReg(); 2636 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname)); 2637 2638 scope_values->append(sv); 2639 return 1; 2640 #endif 2641 2642 } else if (opr->is_single_fpu()) { 2643 #ifdef X86 2644 // the exact location of fpu stack values is only known 2645 // during fpu stack allocation, so the stack allocator object 2646 // must be present 2647 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 2648 assert(_fpu_stack_allocator != NULL, "must be present"); 2649 opr = _fpu_stack_allocator->to_fpu_stack(opr); 2650 #endif 2651 2652 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; 2653 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); 2654 #ifndef __SOFTFP__ 2655 #ifndef VM_LITTLE_ENDIAN 2656 if (! float_saved_as_double) { 2657 // On big endian system, we may have an issue if float registers use only 2658 // the low half of the (same) double registers. 2659 // Both the float and the double could have the same regnr but would correspond 2660 // to two different addresses once saved. 2661 2662 // get next safely (no assertion checks) 2663 VMReg next = VMRegImpl::as_VMReg(1+rname->value()); 2664 if (next->is_reg() && 2665 (next->as_FloatRegister() == rname->as_FloatRegister())) { 2666 // the back-end does use the same numbering for the double and the float 2667 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float 2668 } 2669 } 2670 #endif 2671 #endif 2672 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); 2673 2674 scope_values->append(sv); 2675 return 1; 2676 2677 } else { 2678 // double-size operands 2679 2680 ScopeValue* first; 2681 ScopeValue* second; 2682 2683 if (opr->is_double_stack()) { 2684 #ifdef _LP64 2685 Location loc1; 2686 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl; 2687 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) { 2688 bailout("too large frame"); 2689 } 2690 // Does this reverse on x86 vs. sparc? 2691 first = new LocationValue(loc1); 2692 second = _int_0_scope_value; 2693 #else 2694 Location loc1, loc2; 2695 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) { 2696 bailout("too large frame"); 2697 } 2698 first = new LocationValue(loc1); 2699 second = new LocationValue(loc2); 2700 #endif // _LP64 2701 2702 } else if (opr->is_double_cpu()) { 2703 #ifdef _LP64 2704 VMReg rname_first = opr->as_register_lo()->as_VMReg(); 2705 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first)); 2706 second = _int_0_scope_value; 2707 #else 2708 VMReg rname_first = opr->as_register_lo()->as_VMReg(); 2709 VMReg rname_second = opr->as_register_hi()->as_VMReg(); 2710 2711 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) { 2712 // lo/hi and swapped relative to first and second, so swap them 2713 VMReg tmp = rname_first; 2714 rname_first = rname_second; 2715 rname_second = tmp; 2716 } 2717 2718 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2719 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2720 #endif //_LP64 2721 2722 2723 #ifdef X86 2724 } else if (opr->is_double_xmm()) { 2725 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); 2726 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); 2727 # ifdef _LP64 2728 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 2729 second = _int_0_scope_value; 2730 # else 2731 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2732 // %%% This is probably a waste but we'll keep things as they were for now 2733 if (true) { 2734 VMReg rname_second = rname_first->next(); 2735 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2736 } 2737 # endif 2738 #endif 2739 2740 } else if (opr->is_double_fpu()) { 2741 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of 2742 // the double as float registers in the native ordering. On X86, 2743 // fpu_regnrLo is a FPU stack slot whose VMReg represents 2744 // the low-order word of the double and fpu_regnrLo + 1 is the 2745 // name for the other half. *first and *second must represent the 2746 // least and most significant words, respectively. 2747 2748 #ifdef X86 2749 // the exact location of fpu stack values is only known 2750 // during fpu stack allocation, so the stack allocator object 2751 // must be present 2752 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 2753 assert(_fpu_stack_allocator != NULL, "must be present"); 2754 opr = _fpu_stack_allocator->to_fpu_stack(opr); 2755 2756 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); 2757 #endif 2758 #ifdef SPARC 2759 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); 2760 #endif 2761 #ifdef ARM32 2762 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); 2763 #endif 2764 #ifdef PPC32 2765 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); 2766 #endif 2767 2768 #ifdef VM_LITTLE_ENDIAN 2769 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo()); 2770 #else 2771 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); 2772 #endif 2773 2774 #ifdef _LP64 2775 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 2776 second = _int_0_scope_value; 2777 #else 2778 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2779 // %%% This is probably a waste but we'll keep things as they were for now 2780 if (true) { 2781 VMReg rname_second = rname_first->next(); 2782 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2783 } 2784 #endif 2785 2786 } else { 2787 ShouldNotReachHere(); 2788 first = NULL; 2789 second = NULL; 2790 } 2791 2792 assert(first != NULL && second != NULL, "must be set"); 2793 // The convention the interpreter uses is that the second local 2794 // holds the first raw word of the native double representation. 2795 // This is actually reasonable, since locals and stack arrays 2796 // grow downwards in all implementations. 2797 // (If, on some machine, the interpreter's Java locals or stack 2798 // were to grow upwards, the embedded doubles would be word-swapped.) 2799 scope_values->append(second); 2800 scope_values->append(first); 2801 return 2; 2802 } 2803 } 2804 2805 2806 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) { 2807 if (value != NULL) { 2808 LIR_Opr opr = value->operand(); 2809 Constant* con = value->as_Constant(); 2810 2811 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)"); 2812 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); 2813 2814 if (con != NULL && !con->is_pinned() && !opr->is_constant()) { 2815 // Unpinned constants may have a virtual operand for a part of the lifetime 2816 // or may be illegal when it was optimized away, 2817 // so always use a constant operand 2818 opr = LIR_OprFact::value_type(con->type()); 2819 } 2820 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here"); 2821 2822 if (opr->is_virtual()) { 2823 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode; 2824 2825 BlockBegin* block = block_of_op_with_id(op_id); 2826 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) { 2827 // generating debug information for the last instruction of a block. 2828 // if this instruction is a branch, spill moves are inserted before this branch 2829 // and so the wrong operand would be returned (spill moves at block boundaries are not 2830 // considered in the live ranges of intervals) 2831 // Solution: use the first op_id of the branch target block instead. 2832 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) { 2833 if (block->live_out().at(opr->vreg_number())) { 2834 op_id = block->sux_at(0)->first_lir_instruction_id(); 2835 mode = LIR_OpVisitState::outputMode; 2836 } 2837 } 2838 } 2839 2840 // Get current location of operand 2841 // The operand must be live because debug information is considered when building the intervals 2842 // if the interval is not live, color_lir_opr will cause an assertion failure 2843 opr = color_lir_opr(opr, op_id, mode); 2844 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls"); 2845 2846 // Append to ScopeValue array 2847 return append_scope_value_for_operand(opr, scope_values); 2848 2849 } else { 2850 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands"); 2851 assert(opr->is_constant(), "operand must be constant"); 2852 2853 return append_scope_value_for_constant(opr, scope_values); 2854 } 2855 } else { 2856 // append a dummy value because real value not needed 2857 scope_values->append(_illegal_value); 2858 return 1; 2859 } 2860 } 2861 2862 2863 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) { 2864 IRScopeDebugInfo* caller_debug_info = NULL; 2865 2866 ValueStack* caller_state = cur_state->caller_state(); 2867 if (caller_state != NULL) { 2868 // process recursively to compute outermost scope first 2869 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state); 2870 } 2871 2872 // initialize these to null. 2873 // If we don't need deopt info or there are no locals, expressions or monitors, 2874 // then these get recorded as no information and avoids the allocation of 0 length arrays. 2875 GrowableArray<ScopeValue*>* locals = NULL; 2876 GrowableArray<ScopeValue*>* expressions = NULL; 2877 GrowableArray<MonitorValue*>* monitors = NULL; 2878 2879 // describe local variable values 2880 int nof_locals = cur_state->locals_size(); 2881 if (nof_locals > 0) { 2882 locals = new GrowableArray<ScopeValue*>(nof_locals); 2883 2884 int pos = 0; 2885 while (pos < nof_locals) { 2886 assert(pos < cur_state->locals_size(), "why not?"); 2887 2888 Value local = cur_state->local_at(pos); 2889 pos += append_scope_value(op_id, local, locals); 2890 2891 assert(locals->length() == pos, "must match"); 2892 } 2893 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals"); 2894 assert(locals->length() == cur_state->locals_size(), "wrong number of locals"); 2895 } else if (cur_scope->method()->max_locals() > 0) { 2896 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be"); 2897 nof_locals = cur_scope->method()->max_locals(); 2898 locals = new GrowableArray<ScopeValue*>(nof_locals); 2899 for(int i = 0; i < nof_locals; i++) { 2900 locals->append(_illegal_value); 2901 } 2902 } 2903 2904 // describe expression stack 2905 int nof_stack = cur_state->stack_size(); 2906 if (nof_stack > 0) { 2907 expressions = new GrowableArray<ScopeValue*>(nof_stack); 2908 2909 int pos = 0; 2910 while (pos < nof_stack) { 2911 Value expression = cur_state->stack_at_inc(pos); 2912 append_scope_value(op_id, expression, expressions); 2913 2914 assert(expressions->length() == pos, "must match"); 2915 } 2916 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries"); 2917 } 2918 2919 // describe monitors 2920 int nof_locks = cur_state->locks_size(); 2921 if (nof_locks > 0) { 2922 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0; 2923 monitors = new GrowableArray<MonitorValue*>(nof_locks); 2924 for (int i = 0; i < nof_locks; i++) { 2925 monitors->append(location_for_monitor_index(lock_offset + i)); 2926 } 2927 } 2928 2929 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info); 2930 } 2931 2932 2933 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) { 2934 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id)); 2935 2936 IRScope* innermost_scope = info->scope(); 2937 ValueStack* innermost_state = info->stack(); 2938 2939 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?"); 2940 2941 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size())); 2942 2943 if (info->_scope_debug_info == NULL) { 2944 // compute debug information 2945 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state); 2946 } else { 2947 // debug information already set. Check that it is correct from the current point of view 2948 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state))); 2949 } 2950 } 2951 2952 2953 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { 2954 LIR_OpVisitState visitor; 2955 int num_inst = instructions->length(); 2956 bool has_dead = false; 2957 2958 for (int j = 0; j < num_inst; j++) { 2959 LIR_Op* op = instructions->at(j); 2960 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves 2961 has_dead = true; 2962 continue; 2963 } 2964 int op_id = op->id(); 2965 2966 // visit instruction to get list of operands 2967 visitor.visit(op); 2968 2969 // iterate all modes of the visitor and process all virtual operands 2970 for_each_visitor_mode(mode) { 2971 int n = visitor.opr_count(mode); 2972 for (int k = 0; k < n; k++) { 2973 LIR_Opr opr = visitor.opr_at(mode, k); 2974 if (opr->is_virtual_register()) { 2975 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode)); 2976 } 2977 } 2978 } 2979 2980 if (visitor.info_count() > 0) { 2981 // exception handling 2982 if (compilation()->has_exception_handlers()) { 2983 XHandlers* xhandlers = visitor.all_xhandler(); 2984 int n = xhandlers->length(); 2985 for (int k = 0; k < n; k++) { 2986 XHandler* handler = xhandlers->handler_at(k); 2987 if (handler->entry_code() != NULL) { 2988 assign_reg_num(handler->entry_code()->instructions_list(), NULL); 2989 } 2990 } 2991 } else { 2992 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); 2993 } 2994 2995 // compute oop map 2996 assert(iw != NULL, "needed for compute_oop_map"); 2997 compute_oop_map(iw, visitor, op); 2998 2999 // compute debug information 3000 if (!use_fpu_stack_allocation()) { 3001 // compute debug information if fpu stack allocation is not needed. 3002 // when fpu stack allocation is needed, the debug information can not 3003 // be computed here because the exact location of fpu operands is not known 3004 // -> debug information is created inside the fpu stack allocator 3005 int n = visitor.info_count(); 3006 for (int k = 0; k < n; k++) { 3007 compute_debug_info(visitor.info_at(k), op_id); 3008 } 3009 } 3010 } 3011 3012 #ifdef ASSERT 3013 // make sure we haven't made the op invalid. 3014 op->verify(); 3015 #endif 3016 3017 // remove useless moves 3018 if (op->code() == lir_move) { 3019 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 3020 LIR_Op1* move = (LIR_Op1*)op; 3021 LIR_Opr src = move->in_opr(); 3022 LIR_Opr dst = move->result_opr(); 3023 if (dst == src || 3024 !dst->is_pointer() && !src->is_pointer() && 3025 src->is_same_register(dst)) { 3026 instructions->at_put(j, NULL); 3027 has_dead = true; 3028 } 3029 } 3030 } 3031 3032 if (has_dead) { 3033 // iterate all instructions of the block and remove all null-values. 3034 int insert_point = 0; 3035 for (int j = 0; j < num_inst; j++) { 3036 LIR_Op* op = instructions->at(j); 3037 if (op != NULL) { 3038 if (insert_point != j) { 3039 instructions->at_put(insert_point, op); 3040 } 3041 insert_point++; 3042 } 3043 } 3044 instructions->truncate(insert_point); 3045 } 3046 } 3047 3048 void LinearScan::assign_reg_num() { 3049 TIME_LINEAR_SCAN(timer_assign_reg_num); 3050 3051 init_compute_debug_info(); 3052 IntervalWalker* iw = init_compute_oop_maps(); 3053 3054 int num_blocks = block_count(); 3055 for (int i = 0; i < num_blocks; i++) { 3056 BlockBegin* block = block_at(i); 3057 assign_reg_num(block->lir()->instructions_list(), iw); 3058 } 3059 } 3060 3061 3062 void LinearScan::do_linear_scan() { 3063 NOT_PRODUCT(_total_timer.begin_method()); 3064 3065 number_instructions(); 3066 3067 NOT_PRODUCT(print_lir(1, "Before Register Allocation")); 3068 3069 compute_local_live_sets(); 3070 compute_global_live_sets(); 3071 CHECK_BAILOUT(); 3072 3073 build_intervals(); 3074 CHECK_BAILOUT(); 3075 sort_intervals_before_allocation(); 3076 3077 NOT_PRODUCT(print_intervals("Before Register Allocation")); 3078 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc)); 3079 3080 allocate_registers(); 3081 CHECK_BAILOUT(); 3082 3083 resolve_data_flow(); 3084 if (compilation()->has_exception_handlers()) { 3085 resolve_exception_handlers(); 3086 } 3087 // fill in number of spill slots into frame_map 3088 propagate_spill_slots(); 3089 CHECK_BAILOUT(); 3090 3091 NOT_PRODUCT(print_intervals("After Register Allocation")); 3092 NOT_PRODUCT(print_lir(2, "LIR after register allocation:")); 3093 3094 sort_intervals_after_allocation(); 3095 3096 DEBUG_ONLY(verify()); 3097 3098 eliminate_spill_moves(); 3099 assign_reg_num(); 3100 CHECK_BAILOUT(); 3101 3102 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); 3103 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); 3104 3105 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); 3106 3107 if (use_fpu_stack_allocation()) { 3108 allocate_fpu_stack(); // Only has effect on Intel 3109 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); 3110 } 3111 } 3112 3113 { TIME_LINEAR_SCAN(timer_optimize_lir); 3114 3115 EdgeMoveOptimizer::optimize(ir()->code()); 3116 ControlFlowOptimizer::optimize(ir()->code()); 3117 // check that cfg is still correct after optimizations 3118 ir()->verify(); 3119 } 3120 3121 NOT_PRODUCT(print_lir(1, "Before Code Generation", false)); 3122 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final)); 3123 NOT_PRODUCT(_total_timer.end_method(this)); 3124 } 3125 3126 3127 // ********** Printing functions 3128 3129 #ifndef PRODUCT 3130 3131 void LinearScan::print_timers(double total) { 3132 _total_timer.print(total); 3133 } 3134 3135 void LinearScan::print_statistics() { 3136 _stat_before_alloc.print("before allocation"); 3137 _stat_after_asign.print("after assignment of register"); 3138 _stat_final.print("after optimization"); 3139 } 3140 3141 void LinearScan::print_bitmap(BitMap& b) { 3142 for (unsigned int i = 0; i < b.size(); i++) { 3143 if (b.at(i)) tty->print("%d ", i); 3144 } 3145 tty->cr(); 3146 } 3147 3148 void LinearScan::print_intervals(const char* label) { 3149 if (TraceLinearScanLevel >= 1) { 3150 int i; 3151 tty->cr(); 3152 tty->print_cr("%s", label); 3153 3154 for (i = 0; i < interval_count(); i++) { 3155 Interval* interval = interval_at(i); 3156 if (interval != NULL) { 3157 interval->print(); 3158 } 3159 } 3160 3161 tty->cr(); 3162 tty->print_cr("--- Basic Blocks ---"); 3163 for (i = 0; i < block_count(); i++) { 3164 BlockBegin* block = block_at(i); 3165 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth()); 3166 } 3167 tty->cr(); 3168 tty->cr(); 3169 } 3170 3171 if (PrintCFGToFile) { 3172 CFGPrinter::print_intervals(&_intervals, label); 3173 } 3174 } 3175 3176 void LinearScan::print_lir(int level, const char* label, bool hir_valid) { 3177 if (TraceLinearScanLevel >= level) { 3178 tty->cr(); 3179 tty->print_cr("%s", label); 3180 print_LIR(ir()->linear_scan_order()); 3181 tty->cr(); 3182 } 3183 3184 if (level == 1 && PrintCFGToFile) { 3185 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true); 3186 } 3187 } 3188 3189 #endif //PRODUCT 3190 3191 3192 // ********** verification functions for allocation 3193 // (check that all intervals have a correct register and that no registers are overwritten) 3194 #ifdef ASSERT 3195 3196 void LinearScan::verify() { 3197 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************")); 3198 verify_intervals(); 3199 3200 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************")); 3201 verify_no_oops_in_fixed_intervals(); 3202 3203 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries")); 3204 verify_constants(); 3205 3206 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************")); 3207 verify_registers(); 3208 3209 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************")); 3210 } 3211 3212 void LinearScan::verify_intervals() { 3213 int len = interval_count(); 3214 bool has_error = false; 3215 3216 for (int i = 0; i < len; i++) { 3217 Interval* i1 = interval_at(i); 3218 if (i1 == NULL) continue; 3219 3220 i1->check_split_children(); 3221 3222 if (i1->reg_num() != i) { 3223 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr(); 3224 has_error = true; 3225 } 3226 3227 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) { 3228 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr(); 3229 has_error = true; 3230 } 3231 3232 if (i1->assigned_reg() == any_reg) { 3233 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr(); 3234 has_error = true; 3235 } 3236 3237 if (i1->assigned_reg() == i1->assigned_regHi()) { 3238 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr(); 3239 has_error = true; 3240 } 3241 3242 if (!is_processed_reg_num(i1->assigned_reg())) { 3243 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr(); 3244 has_error = true; 3245 } 3246 3247 if (i1->first() == Range::end()) { 3248 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr(); 3249 has_error = true; 3250 } 3251 3252 for (Range* r = i1->first(); r != Range::end(); r = r->next()) { 3253 if (r->from() >= r->to()) { 3254 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr(); 3255 has_error = true; 3256 } 3257 } 3258 3259 for (int j = i + 1; j < len; j++) { 3260 Interval* i2 = interval_at(j); 3261 if (i2 == NULL) continue; 3262 3263 // special intervals that are created in MoveResolver 3264 // -> ignore them because the range information has no meaning there 3265 if (i1->from() == 1 && i1->to() == 2) continue; 3266 if (i2->from() == 1 && i2->to() == 2) continue; 3267 3268 int r1 = i1->assigned_reg(); 3269 int r1Hi = i1->assigned_regHi(); 3270 int r2 = i2->assigned_reg(); 3271 int r2Hi = i2->assigned_regHi(); 3272 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) { 3273 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num()); 3274 i1->print(); tty->cr(); 3275 i2->print(); tty->cr(); 3276 has_error = true; 3277 } 3278 } 3279 } 3280 3281 assert(has_error == false, "register allocation invalid"); 3282 } 3283 3284 3285 void LinearScan::verify_no_oops_in_fixed_intervals() { 3286 Interval* fixed_intervals; 3287 Interval* other_intervals; 3288 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL); 3289 3290 // to ensure a walking until the last instruction id, add a dummy interval 3291 // with a high operation id 3292 other_intervals = new Interval(any_reg); 3293 other_intervals->add_range(max_jint - 2, max_jint - 1); 3294 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals); 3295 3296 LIR_OpVisitState visitor; 3297 for (int i = 0; i < block_count(); i++) { 3298 BlockBegin* block = block_at(i); 3299 3300 LIR_OpList* instructions = block->lir()->instructions_list(); 3301 3302 for (int j = 0; j < instructions->length(); j++) { 3303 LIR_Op* op = instructions->at(j); 3304 int op_id = op->id(); 3305 3306 visitor.visit(op); 3307 3308 if (visitor.info_count() > 0) { 3309 iw->walk_before(op->id()); 3310 bool check_live = true; 3311 if (op->code() == lir_move) { 3312 LIR_Op1* move = (LIR_Op1*)op; 3313 check_live = (move->patch_code() == lir_patch_none); 3314 } 3315 LIR_OpBranch* branch = op->as_OpBranch(); 3316 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { 3317 // Don't bother checking the stub in this case since the 3318 // exception stub will never return to normal control flow. 3319 check_live = false; 3320 } 3321 3322 // Make sure none of the fixed registers is live across an 3323 // oopmap since we can't handle that correctly. 3324 if (check_live) { 3325 for (Interval* interval = iw->active_first(fixedKind); 3326 interval != Interval::end(); 3327 interval = interval->next()) { 3328 if (interval->current_to() > op->id() + 1) { 3329 // This interval is live out of this op so make sure 3330 // that this interval represents some value that's 3331 // referenced by this op either as an input or output. 3332 bool ok = false; 3333 for_each_visitor_mode(mode) { 3334 int n = visitor.opr_count(mode); 3335 for (int k = 0; k < n; k++) { 3336 LIR_Opr opr = visitor.opr_at(mode, k); 3337 if (opr->is_fixed_cpu()) { 3338 if (interval_at(reg_num(opr)) == interval) { 3339 ok = true; 3340 break; 3341 } 3342 int hi = reg_numHi(opr); 3343 if (hi != -1 && interval_at(hi) == interval) { 3344 ok = true; 3345 break; 3346 } 3347 } 3348 } 3349 } 3350 assert(ok, "fixed intervals should never be live across an oopmap point"); 3351 } 3352 } 3353 } 3354 } 3355 3356 // oop-maps at calls do not contain registers, so check is not needed 3357 if (!visitor.has_call()) { 3358 3359 for_each_visitor_mode(mode) { 3360 int n = visitor.opr_count(mode); 3361 for (int k = 0; k < n; k++) { 3362 LIR_Opr opr = visitor.opr_at(mode, k); 3363 3364 if (opr->is_fixed_cpu() && opr->is_oop()) { 3365 // operand is a non-virtual cpu register and contains an oop 3366 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr()); 3367 3368 Interval* interval = interval_at(reg_num(opr)); 3369 assert(interval != NULL, "no interval"); 3370 3371 if (mode == LIR_OpVisitState::inputMode) { 3372 if (interval->to() >= op_id + 1) { 3373 assert(interval->to() < op_id + 2 || 3374 interval->has_hole_between(op_id, op_id + 2), 3375 "oop input operand live after instruction"); 3376 } 3377 } else if (mode == LIR_OpVisitState::outputMode) { 3378 if (interval->from() <= op_id - 1) { 3379 assert(interval->has_hole_between(op_id - 1, op_id), 3380 "oop input operand live after instruction"); 3381 } 3382 } 3383 } 3384 } 3385 } 3386 } 3387 } 3388 } 3389 } 3390 3391 3392 void LinearScan::verify_constants() { 3393 int num_regs = num_virtual_regs(); 3394 int size = live_set_size(); 3395 int num_blocks = block_count(); 3396 3397 for (int i = 0; i < num_blocks; i++) { 3398 BlockBegin* block = block_at(i); 3399 BitMap live_at_edge = block->live_in(); 3400 3401 // visit all registers where the live_at_edge bit is set 3402 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { 3403 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id())); 3404 3405 Value value = gen()->instruction_for_vreg(r); 3406 3407 assert(value != NULL, "all intervals live across block boundaries must have Value"); 3408 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand"); 3409 assert(value->operand()->vreg_number() == r, "register number must match"); 3410 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries"); 3411 } 3412 } 3413 } 3414 3415 3416 class RegisterVerifier: public StackObj { 3417 private: 3418 LinearScan* _allocator; 3419 BlockList _work_list; // all blocks that must be processed 3420 IntervalsList _saved_states; // saved information of previous check 3421 3422 // simplified access to methods of LinearScan 3423 Compilation* compilation() const { return _allocator->compilation(); } 3424 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); } 3425 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); } 3426 3427 // currently, only registers are processed 3428 int state_size() { return LinearScan::nof_regs; } 3429 3430 // accessors 3431 GrowableArray<Interval*>* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); } 3432 void set_state_for_block(BlockBegin* block, GrowableArray<Interval*>* saved_state) { _saved_states.at_put(block->block_id(), saved_state); } 3433 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); } 3434 3435 // helper functions 3436 GrowableArray<Interval*>* copy(GrowableArray<Interval*>* input_state); 3437 void state_put(GrowableArray<Interval*>* input_state, int reg, Interval* interval); 3438 bool check_state(GrowableArray<Interval*>* input_state, int reg, Interval* interval); 3439 3440 void process_block(BlockBegin* block); 3441 void process_xhandler(XHandler* xhandler, GrowableArray<Interval*>* input_state); 3442 void process_successor(BlockBegin* block, GrowableArray<Interval*>* input_state); 3443 void process_operations(LIR_List* ops, GrowableArray<Interval*>* input_state); 3444 3445 public: 3446 RegisterVerifier(LinearScan* allocator) 3447 : _allocator(allocator) 3448 , _work_list(16) 3449 , _saved_states(BlockBegin::number_of_blocks(), NULL) 3450 { } 3451 3452 void verify(BlockBegin* start); 3453 }; 3454 3455 3456 // entry function from LinearScan that starts the verification 3457 void LinearScan::verify_registers() { 3458 RegisterVerifier verifier(this); 3459 verifier.verify(block_at(0)); 3460 } 3461 3462 3463 void RegisterVerifier::verify(BlockBegin* start) { 3464 // setup input registers (method arguments) for first block 3465 int input_state_len = state_size(); 3466 GrowableArray<Interval*>* input_state = new GrowableArray<Interval*>(input_state_len, input_state_len, NULL); 3467 CallingConvention* args = compilation()->frame_map()->incoming_arguments(); 3468 for (int n = 0; n < args->length(); n++) { 3469 LIR_Opr opr = args->at(n); 3470 if (opr->is_register()) { 3471 Interval* interval = interval_at(reg_num(opr)); 3472 3473 if (interval->assigned_reg() < state_size()) { 3474 input_state->at_put(interval->assigned_reg(), interval); 3475 } 3476 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) { 3477 input_state->at_put(interval->assigned_regHi(), interval); 3478 } 3479 } 3480 } 3481 3482 set_state_for_block(start, input_state); 3483 add_to_work_list(start); 3484 3485 // main loop for verification 3486 do { 3487 BlockBegin* block = _work_list.at(0); 3488 _work_list.remove_at(0); 3489 3490 process_block(block); 3491 } while (!_work_list.is_empty()); 3492 } 3493 3494 void RegisterVerifier::process_block(BlockBegin* block) { 3495 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id())); 3496 3497 // must copy state because it is modified 3498 GrowableArray<Interval*>* input_state = copy(state_for_block(block)); 3499 3500 if (TraceLinearScanLevel >= 4) { 3501 tty->print_cr("Input-State of intervals:"); 3502 tty->print(" "); 3503 for (int i = 0; i < state_size(); i++) { 3504 if (input_state->at(i) != NULL) { 3505 tty->print(" %4d", input_state->at(i)->reg_num()); 3506 } else { 3507 tty->print(" __"); 3508 } 3509 } 3510 tty->cr(); 3511 tty->cr(); 3512 } 3513 3514 // process all operations of the block 3515 process_operations(block->lir(), input_state); 3516 3517 // iterate all successors 3518 for (int i = 0; i < block->number_of_sux(); i++) { 3519 process_successor(block->sux_at(i), input_state); 3520 } 3521 } 3522 3523 void RegisterVerifier::process_xhandler(XHandler* xhandler, GrowableArray<Interval*>* input_state) { 3524 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id())); 3525 3526 // must copy state because it is modified 3527 input_state = copy(input_state); 3528 3529 if (xhandler->entry_code() != NULL) { 3530 process_operations(xhandler->entry_code(), input_state); 3531 } 3532 process_successor(xhandler->entry_block(), input_state); 3533 } 3534 3535 void RegisterVerifier::process_successor(BlockBegin* block, GrowableArray<Interval*>* input_state) { 3536 GrowableArray<Interval*>* saved_state = state_for_block(block); 3537 3538 if (saved_state != NULL) { 3539 // this block was already processed before. 3540 // check if new input_state is consistent with saved_state 3541 3542 bool saved_state_correct = true; 3543 for (int i = 0; i < state_size(); i++) { 3544 if (input_state->at(i) != saved_state->at(i)) { 3545 // current input_state and previous saved_state assume a different 3546 // interval in this register -> assume that this register is invalid 3547 if (saved_state->at(i) != NULL) { 3548 // invalidate old calculation only if it assumed that 3549 // register was valid. when the register was already invalid, 3550 // then the old calculation was correct. 3551 saved_state_correct = false; 3552 saved_state->at_put(i, NULL); 3553 3554 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i)); 3555 } 3556 } 3557 } 3558 3559 if (saved_state_correct) { 3560 // already processed block with correct input_state 3561 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id())); 3562 } else { 3563 // must re-visit this block 3564 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id())); 3565 add_to_work_list(block); 3566 } 3567 3568 } else { 3569 // block was not processed before, so set initial input_state 3570 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id())); 3571 3572 set_state_for_block(block, copy(input_state)); 3573 add_to_work_list(block); 3574 } 3575 } 3576 3577 3578 GrowableArray<Interval*>* RegisterVerifier::copy(GrowableArray<Interval*>* input_state) { 3579 GrowableArray<Interval*>* copy_state = new GrowableArray<Interval*>(input_state->length()); 3580 copy_state->appendAll(input_state); 3581 return copy_state; 3582 } 3583 3584 void RegisterVerifier::state_put(GrowableArray<Interval*>* input_state, int reg, Interval* interval) { 3585 if (reg != LinearScan::any_reg && reg < state_size()) { 3586 if (interval != NULL) { 3587 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num())); 3588 } else if (input_state->at(reg) != NULL) { 3589 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg)); 3590 } 3591 3592 input_state->at_put(reg, interval); 3593 } 3594 } 3595 3596 bool RegisterVerifier::check_state(GrowableArray<Interval*>* input_state, int reg, Interval* interval) { 3597 if (reg != LinearScan::any_reg && reg < state_size()) { 3598 if (input_state->at(reg) != interval) { 3599 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num()); 3600 return true; 3601 } 3602 } 3603 return false; 3604 } 3605 3606 void RegisterVerifier::process_operations(LIR_List* ops, GrowableArray<Interval*>* input_state) { 3607 // visit all instructions of the block 3608 LIR_OpVisitState visitor; 3609 bool has_error = false; 3610 3611 for (int i = 0; i < ops->length(); i++) { 3612 LIR_Op* op = ops->at(i); 3613 visitor.visit(op); 3614 3615 TRACE_LINEAR_SCAN(4, op->print_on(tty)); 3616 3617 // check if input operands are correct 3618 int j; 3619 int n = visitor.opr_count(LIR_OpVisitState::inputMode); 3620 for (j = 0; j < n; j++) { 3621 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j); 3622 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3623 Interval* interval = interval_at(reg_num(opr)); 3624 if (op->id() != -1) { 3625 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode); 3626 } 3627 3628 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent()); 3629 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent()); 3630 3631 // When an operand is marked with is_last_use, then the fpu stack allocator 3632 // removes the register from the fpu stack -> the register contains no value 3633 if (opr->is_last_use()) { 3634 state_put(input_state, interval->assigned_reg(), NULL); 3635 state_put(input_state, interval->assigned_regHi(), NULL); 3636 } 3637 } 3638 } 3639 3640 // invalidate all caller save registers at calls 3641 if (visitor.has_call()) { 3642 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) { 3643 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL); 3644 } 3645 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) { 3646 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL); 3647 } 3648 3649 #ifdef X86 3650 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms(); 3651 for (j = 0; j < num_caller_save_xmm_regs; j++) { 3652 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL); 3653 } 3654 #endif 3655 } 3656 3657 // process xhandler before output and temp operands 3658 XHandlers* xhandlers = visitor.all_xhandler(); 3659 n = xhandlers->length(); 3660 for (int k = 0; k < n; k++) { 3661 process_xhandler(xhandlers->handler_at(k), input_state); 3662 } 3663 3664 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL) 3665 n = visitor.opr_count(LIR_OpVisitState::tempMode); 3666 for (j = 0; j < n; j++) { 3667 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j); 3668 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3669 Interval* interval = interval_at(reg_num(opr)); 3670 if (op->id() != -1) { 3671 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode); 3672 } 3673 3674 state_put(input_state, interval->assigned_reg(), interval->split_parent()); 3675 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); 3676 } 3677 } 3678 3679 // set output operands 3680 n = visitor.opr_count(LIR_OpVisitState::outputMode); 3681 for (j = 0; j < n; j++) { 3682 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j); 3683 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3684 Interval* interval = interval_at(reg_num(opr)); 3685 if (op->id() != -1) { 3686 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode); 3687 } 3688 3689 state_put(input_state, interval->assigned_reg(), interval->split_parent()); 3690 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); 3691 } 3692 } 3693 } 3694 assert(has_error == false, "Error in register allocation"); 3695 } 3696 3697 #endif // ASSERT 3698 3699 3700 3701 // **** Implementation of MoveResolver ****************************** 3702 3703 MoveResolver::MoveResolver(LinearScan* allocator) : 3704 _allocator(allocator), 3705 _multiple_reads_allowed(false), 3706 _mapping_from(8), 3707 _mapping_from_opr(8), 3708 _mapping_to(8), 3709 _insert_list(NULL), 3710 _insert_idx(-1), 3711 _insertion_buffer() 3712 { 3713 for (int i = 0; i < LinearScan::nof_regs; i++) { 3714 _register_blocked[i] = 0; 3715 } 3716 DEBUG_ONLY(check_empty()); 3717 } 3718 3719 3720 #ifdef ASSERT 3721 3722 void MoveResolver::check_empty() { 3723 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing"); 3724 for (int i = 0; i < LinearScan::nof_regs; i++) { 3725 assert(register_blocked(i) == 0, "register map must be empty before and after processing"); 3726 } 3727 assert(_multiple_reads_allowed == false, "must have default value"); 3728 } 3729 3730 void MoveResolver::verify_before_resolve() { 3731 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal"); 3732 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal"); 3733 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set"); 3734 3735 int i, j; 3736 if (!_multiple_reads_allowed) { 3737 for (i = 0; i < _mapping_from.length(); i++) { 3738 for (j = i + 1; j < _mapping_from.length(); j++) { 3739 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice"); 3740 } 3741 } 3742 } 3743 3744 for (i = 0; i < _mapping_to.length(); i++) { 3745 for (j = i + 1; j < _mapping_to.length(); j++) { 3746 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice"); 3747 } 3748 } 3749 3750 3751 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills()); 3752 used_regs.clear(); 3753 if (!_multiple_reads_allowed) { 3754 for (i = 0; i < _mapping_from.length(); i++) { 3755 Interval* it = _mapping_from.at(i); 3756 if (it != NULL) { 3757 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice"); 3758 used_regs.set_bit(it->assigned_reg()); 3759 3760 if (it->assigned_regHi() != LinearScan::any_reg) { 3761 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice"); 3762 used_regs.set_bit(it->assigned_regHi()); 3763 } 3764 } 3765 } 3766 } 3767 3768 used_regs.clear(); 3769 for (i = 0; i < _mapping_to.length(); i++) { 3770 Interval* it = _mapping_to.at(i); 3771 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice"); 3772 used_regs.set_bit(it->assigned_reg()); 3773 3774 if (it->assigned_regHi() != LinearScan::any_reg) { 3775 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice"); 3776 used_regs.set_bit(it->assigned_regHi()); 3777 } 3778 } 3779 3780 used_regs.clear(); 3781 for (i = 0; i < _mapping_from.length(); i++) { 3782 Interval* it = _mapping_from.at(i); 3783 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) { 3784 used_regs.set_bit(it->assigned_reg()); 3785 } 3786 } 3787 for (i = 0; i < _mapping_to.length(); i++) { 3788 Interval* it = _mapping_to.at(i); 3789 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to"); 3790 } 3791 } 3792 3793 #endif // ASSERT 3794 3795 3796 // mark assigned_reg and assigned_regHi of the interval as blocked 3797 void MoveResolver::block_registers(Interval* it) { 3798 int reg = it->assigned_reg(); 3799 if (reg < LinearScan::nof_regs) { 3800 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); 3801 set_register_blocked(reg, 1); 3802 } 3803 reg = it->assigned_regHi(); 3804 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3805 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); 3806 set_register_blocked(reg, 1); 3807 } 3808 } 3809 3810 // mark assigned_reg and assigned_regHi of the interval as unblocked 3811 void MoveResolver::unblock_registers(Interval* it) { 3812 int reg = it->assigned_reg(); 3813 if (reg < LinearScan::nof_regs) { 3814 assert(register_blocked(reg) > 0, "register already marked as unused"); 3815 set_register_blocked(reg, -1); 3816 } 3817 reg = it->assigned_regHi(); 3818 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3819 assert(register_blocked(reg) > 0, "register already marked as unused"); 3820 set_register_blocked(reg, -1); 3821 } 3822 } 3823 3824 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from) 3825 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) { 3826 int from_reg = -1; 3827 int from_regHi = -1; 3828 if (from != NULL) { 3829 from_reg = from->assigned_reg(); 3830 from_regHi = from->assigned_regHi(); 3831 } 3832 3833 int reg = to->assigned_reg(); 3834 if (reg < LinearScan::nof_regs) { 3835 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { 3836 return false; 3837 } 3838 } 3839 reg = to->assigned_regHi(); 3840 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3841 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { 3842 return false; 3843 } 3844 } 3845 3846 return true; 3847 } 3848 3849 3850 void MoveResolver::create_insertion_buffer(LIR_List* list) { 3851 assert(!_insertion_buffer.initialized(), "overwriting existing buffer"); 3852 _insertion_buffer.init(list); 3853 } 3854 3855 void MoveResolver::append_insertion_buffer() { 3856 if (_insertion_buffer.initialized()) { 3857 _insertion_buffer.lir_list()->append(&_insertion_buffer); 3858 } 3859 assert(!_insertion_buffer.initialized(), "must be uninitialized now"); 3860 3861 _insert_list = NULL; 3862 _insert_idx = -1; 3863 } 3864 3865 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) { 3866 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal"); 3867 assert(from_interval->type() == to_interval->type(), "move between different types"); 3868 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); 3869 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); 3870 3871 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type()); 3872 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); 3873 3874 if (!_multiple_reads_allowed) { 3875 // the last_use flag is an optimization for FPU stack allocation. When the same 3876 // input interval is used in more than one move, then it is too difficult to determine 3877 // if this move is really the last use. 3878 from_opr = from_opr->make_last_use(); 3879 } 3880 _insertion_buffer.move(_insert_idx, from_opr, to_opr); 3881 3882 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3883 } 3884 3885 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) { 3886 assert(from_opr->type() == to_interval->type(), "move between different types"); 3887 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); 3888 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); 3889 3890 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); 3891 _insertion_buffer.move(_insert_idx, from_opr, to_opr); 3892 3893 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3894 } 3895 3896 3897 void MoveResolver::resolve_mappings() { 3898 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx)); 3899 DEBUG_ONLY(verify_before_resolve()); 3900 3901 // Block all registers that are used as input operands of a move. 3902 // When a register is blocked, no move to this register is emitted. 3903 // This is necessary for detecting cycles in moves. 3904 int i; 3905 for (i = _mapping_from.length() - 1; i >= 0; i--) { 3906 Interval* from_interval = _mapping_from.at(i); 3907 if (from_interval != NULL) { 3908 block_registers(from_interval); 3909 } 3910 } 3911 3912 int spill_candidate = -1; 3913 while (_mapping_from.length() > 0) { 3914 bool processed_interval = false; 3915 3916 for (i = _mapping_from.length() - 1; i >= 0; i--) { 3917 Interval* from_interval = _mapping_from.at(i); 3918 Interval* to_interval = _mapping_to.at(i); 3919 3920 if (save_to_process_move(from_interval, to_interval)) { 3921 // this inverval can be processed because target is free 3922 if (from_interval != NULL) { 3923 insert_move(from_interval, to_interval); 3924 unblock_registers(from_interval); 3925 } else { 3926 insert_move(_mapping_from_opr.at(i), to_interval); 3927 } 3928 _mapping_from.remove_at(i); 3929 _mapping_from_opr.remove_at(i); 3930 _mapping_to.remove_at(i); 3931 3932 processed_interval = true; 3933 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) { 3934 // this interval cannot be processed now because target is not free 3935 // it starts in a register, so it is a possible candidate for spilling 3936 spill_candidate = i; 3937 } 3938 } 3939 3940 if (!processed_interval) { 3941 // no move could be processed because there is a cycle in the move list 3942 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory 3943 assert(spill_candidate != -1, "no interval in register for spilling found"); 3944 3945 // create a new spill interval and assign a stack slot to it 3946 Interval* from_interval = _mapping_from.at(spill_candidate); 3947 Interval* spill_interval = new Interval(-1); 3948 spill_interval->set_type(from_interval->type()); 3949 3950 // add a dummy range because real position is difficult to calculate 3951 // Note: this range is a special case when the integrity of the allocation is checked 3952 spill_interval->add_range(1, 2); 3953 3954 // do not allocate a new spill slot for temporary interval, but 3955 // use spill slot assigned to from_interval. Otherwise moves from 3956 // one stack slot to another can happen (not allowed by LIR_Assembler 3957 int spill_slot = from_interval->canonical_spill_slot(); 3958 if (spill_slot < 0) { 3959 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2); 3960 from_interval->set_canonical_spill_slot(spill_slot); 3961 } 3962 spill_interval->assign_reg(spill_slot); 3963 allocator()->append_interval(spill_interval); 3964 3965 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num())); 3966 3967 // insert a move from register to stack and update the mapping 3968 insert_move(from_interval, spill_interval); 3969 _mapping_from.at_put(spill_candidate, spill_interval); 3970 unblock_registers(from_interval); 3971 } 3972 } 3973 3974 // reset to default value 3975 _multiple_reads_allowed = false; 3976 3977 // check that all intervals have been processed 3978 DEBUG_ONLY(check_empty()); 3979 } 3980 3981 3982 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) { 3983 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); 3984 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set"); 3985 3986 create_insertion_buffer(insert_list); 3987 _insert_list = insert_list; 3988 _insert_idx = insert_idx; 3989 } 3990 3991 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) { 3992 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); 3993 3994 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) { 3995 // insert position changed -> resolve current mappings 3996 resolve_mappings(); 3997 } 3998 3999 if (insert_list != _insert_list) { 4000 // block changed -> append insertion_buffer because it is 4001 // bound to a specific block and create a new insertion_buffer 4002 append_insertion_buffer(); 4003 create_insertion_buffer(insert_list); 4004 } 4005 4006 _insert_list = insert_list; 4007 _insert_idx = insert_idx; 4008 } 4009 4010 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) { 4011 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 4012 4013 _mapping_from.append(from_interval); 4014 _mapping_from_opr.append(LIR_OprFact::illegalOpr); 4015 _mapping_to.append(to_interval); 4016 } 4017 4018 4019 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) { 4020 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 4021 assert(from_opr->is_constant(), "only for constants"); 4022 4023 _mapping_from.append(NULL); 4024 _mapping_from_opr.append(from_opr); 4025 _mapping_to.append(to_interval); 4026 } 4027 4028 void MoveResolver::resolve_and_append_moves() { 4029 if (has_mappings()) { 4030 resolve_mappings(); 4031 } 4032 append_insertion_buffer(); 4033 } 4034 4035 4036 4037 // **** Implementation of Range ************************************* 4038 4039 Range::Range(int from, int to, Range* next) : 4040 _from(from), 4041 _to(to), 4042 _next(next) 4043 { 4044 } 4045 4046 // initialize sentinel 4047 Range* Range::_end = NULL; 4048 void Range::initialize(Arena* arena) { 4049 _end = new (arena) Range(max_jint, max_jint, NULL); 4050 } 4051 4052 int Range::intersects_at(Range* r2) const { 4053 const Range* r1 = this; 4054 4055 assert(r1 != NULL && r2 != NULL, "null ranges not allowed"); 4056 assert(r1 != _end && r2 != _end, "empty ranges not allowed"); 4057 4058 do { 4059 if (r1->from() < r2->from()) { 4060 if (r1->to() <= r2->from()) { 4061 r1 = r1->next(); if (r1 == _end) return -1; 4062 } else { 4063 return r2->from(); 4064 } 4065 } else if (r2->from() < r1->from()) { 4066 if (r2->to() <= r1->from()) { 4067 r2 = r2->next(); if (r2 == _end) return -1; 4068 } else { 4069 return r1->from(); 4070 } 4071 } else { // r1->from() == r2->from() 4072 if (r1->from() == r1->to()) { 4073 r1 = r1->next(); if (r1 == _end) return -1; 4074 } else if (r2->from() == r2->to()) { 4075 r2 = r2->next(); if (r2 == _end) return -1; 4076 } else { 4077 return r1->from(); 4078 } 4079 } 4080 } while (true); 4081 } 4082 4083 #ifndef PRODUCT 4084 void Range::print(outputStream* out) const { 4085 out->print("[%d, %d[ ", _from, _to); 4086 } 4087 #endif 4088 4089 4090 4091 // **** Implementation of Interval ********************************** 4092 4093 // initialize sentinel 4094 Interval* Interval::_end = NULL; 4095 void Interval::initialize(Arena* arena) { 4096 Range::initialize(arena); 4097 _end = new (arena) Interval(-1); 4098 } 4099 4100 Interval::Interval(int reg_num) : 4101 _reg_num(reg_num), 4102 _type(T_ILLEGAL), 4103 _first(Range::end()), 4104 _use_pos_and_kinds(12), 4105 _current(Range::end()), 4106 _next(_end), 4107 _state(invalidState), 4108 _assigned_reg(LinearScan::any_reg), 4109 _assigned_regHi(LinearScan::any_reg), 4110 _cached_to(-1), 4111 _cached_opr(LIR_OprFact::illegalOpr), 4112 _cached_vm_reg(VMRegImpl::Bad()), 4113 _split_children(0), 4114 _canonical_spill_slot(-1), 4115 _insert_move_when_activated(false), 4116 _register_hint(NULL), 4117 _spill_state(noDefinitionFound), 4118 _spill_definition_pos(-1) 4119 { 4120 _split_parent = this; 4121 _current_split_child = this; 4122 } 4123 4124 int Interval::calc_to() { 4125 assert(_first != Range::end(), "interval has no range"); 4126 4127 Range* r = _first; 4128 while (r->next() != Range::end()) { 4129 r = r->next(); 4130 } 4131 return r->to(); 4132 } 4133 4134 4135 #ifdef ASSERT 4136 // consistency check of split-children 4137 void Interval::check_split_children() { 4138 if (_split_children.length() > 0) { 4139 assert(is_split_parent(), "only split parents can have children"); 4140 4141 for (int i = 0; i < _split_children.length(); i++) { 4142 Interval* i1 = _split_children.at(i); 4143 4144 assert(i1->split_parent() == this, "not a split child of this interval"); 4145 assert(i1->type() == type(), "must be equal for all split children"); 4146 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children"); 4147 4148 for (int j = i + 1; j < _split_children.length(); j++) { 4149 Interval* i2 = _split_children.at(j); 4150 4151 assert(i1->reg_num() != i2->reg_num(), "same register number"); 4152 4153 if (i1->from() < i2->from()) { 4154 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping"); 4155 } else { 4156 assert(i2->from() < i1->from(), "intervals start at same op_id"); 4157 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping"); 4158 } 4159 } 4160 } 4161 } 4162 } 4163 #endif // ASSERT 4164 4165 Interval* Interval::register_hint(bool search_split_child) const { 4166 if (!search_split_child) { 4167 return _register_hint; 4168 } 4169 4170 if (_register_hint != NULL) { 4171 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers"); 4172 4173 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) { 4174 return _register_hint; 4175 4176 } else if (_register_hint->_split_children.length() > 0) { 4177 // search the first split child that has a register assigned 4178 int len = _register_hint->_split_children.length(); 4179 for (int i = 0; i < len; i++) { 4180 Interval* cur = _register_hint->_split_children.at(i); 4181 4182 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) { 4183 return cur; 4184 } 4185 } 4186 } 4187 } 4188 4189 // no hint interval found that has a register assigned 4190 return NULL; 4191 } 4192 4193 4194 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) { 4195 assert(is_split_parent(), "can only be called for split parents"); 4196 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); 4197 4198 Interval* result; 4199 if (_split_children.length() == 0) { 4200 result = this; 4201 } else { 4202 result = NULL; 4203 int len = _split_children.length(); 4204 4205 // in outputMode, the end of the interval (op_id == cur->to()) is not valid 4206 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1); 4207 4208 int i; 4209 for (i = 0; i < len; i++) { 4210 Interval* cur = _split_children.at(i); 4211 if (cur->from() <= op_id && op_id < cur->to() + to_offset) { 4212 if (i > 0) { 4213 // exchange current split child to start of list (faster access for next call) 4214 _split_children.at_put(i, _split_children.at(0)); 4215 _split_children.at_put(0, cur); 4216 } 4217 4218 // interval found 4219 result = cur; 4220 break; 4221 } 4222 } 4223 4224 #ifdef ASSERT 4225 for (i = 0; i < len; i++) { 4226 Interval* tmp = _split_children.at(i); 4227 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) { 4228 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num()); 4229 result->print(); 4230 tmp->print(); 4231 assert(false, "two valid result intervals found"); 4232 } 4233 } 4234 #endif 4235 } 4236 4237 assert(result != NULL, "no matching interval found"); 4238 assert(result->covers(op_id, mode), "op_id not covered by interval"); 4239 4240 return result; 4241 } 4242 4243 4244 // returns the last split child that ends before the given op_id 4245 Interval* Interval::split_child_before_op_id(int op_id) { 4246 assert(op_id >= 0, "invalid op_id"); 4247 4248 Interval* parent = split_parent(); 4249 Interval* result = NULL; 4250 4251 int len = parent->_split_children.length(); 4252 assert(len > 0, "no split children available"); 4253 4254 for (int i = len - 1; i >= 0; i--) { 4255 Interval* cur = parent->_split_children.at(i); 4256 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) { 4257 result = cur; 4258 } 4259 } 4260 4261 assert(result != NULL, "no split child found"); 4262 return result; 4263 } 4264 4265 4266 // checks if op_id is covered by any split child 4267 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) { 4268 assert(is_split_parent(), "can only be called for split parents"); 4269 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); 4270 4271 if (_split_children.length() == 0) { 4272 // simple case if interval was not split 4273 return covers(op_id, mode); 4274 4275 } else { 4276 // extended case: check all split children 4277 int len = _split_children.length(); 4278 for (int i = 0; i < len; i++) { 4279 Interval* cur = _split_children.at(i); 4280 if (cur->covers(op_id, mode)) { 4281 return true; 4282 } 4283 } 4284 return false; 4285 } 4286 } 4287 4288 4289 // Note: use positions are sorted descending -> first use has highest index 4290 int Interval::first_usage(IntervalUseKind min_use_kind) const { 4291 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4292 4293 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4294 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4295 return _use_pos_and_kinds.at(i); 4296 } 4297 } 4298 return max_jint; 4299 } 4300 4301 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const { 4302 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4303 4304 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4305 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4306 return _use_pos_and_kinds.at(i); 4307 } 4308 } 4309 return max_jint; 4310 } 4311 4312 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const { 4313 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4314 4315 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4316 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) { 4317 return _use_pos_and_kinds.at(i); 4318 } 4319 } 4320 return max_jint; 4321 } 4322 4323 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const { 4324 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4325 4326 int prev = 0; 4327 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4328 if (_use_pos_and_kinds.at(i) > from) { 4329 return prev; 4330 } 4331 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4332 prev = _use_pos_and_kinds.at(i); 4333 } 4334 } 4335 return prev; 4336 } 4337 4338 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) { 4339 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range"); 4340 4341 // do not add use positions for precolored intervals because 4342 // they are never used 4343 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) { 4344 #ifdef ASSERT 4345 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); 4346 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) { 4347 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position"); 4348 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4349 if (i > 0) { 4350 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending"); 4351 } 4352 } 4353 #endif 4354 4355 // Note: add_use is called in descending order, so list gets sorted 4356 // automatically by just appending new use positions 4357 int len = _use_pos_and_kinds.length(); 4358 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) { 4359 _use_pos_and_kinds.append(pos); 4360 _use_pos_and_kinds.append(use_kind); 4361 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) { 4362 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly"); 4363 _use_pos_and_kinds.at_put(len - 1, use_kind); 4364 } 4365 } 4366 } 4367 4368 void Interval::add_range(int from, int to) { 4369 assert(from < to, "invalid range"); 4370 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval"); 4371 assert(from <= first()->to(), "not inserting at begin of interval"); 4372 4373 if (first()->from() <= to) { 4374 // join intersecting ranges 4375 first()->set_from(MIN2(from, first()->from())); 4376 first()->set_to (MAX2(to, first()->to())); 4377 } else { 4378 // insert new range 4379 _first = new Range(from, to, first()); 4380 } 4381 } 4382 4383 Interval* Interval::new_split_child() { 4384 // allocate new interval 4385 Interval* result = new Interval(-1); 4386 result->set_type(type()); 4387 4388 Interval* parent = split_parent(); 4389 result->_split_parent = parent; 4390 result->set_register_hint(parent); 4391 4392 // insert new interval in children-list of parent 4393 if (parent->_split_children.length() == 0) { 4394 assert(is_split_parent(), "list must be initialized at first split"); 4395 4396 parent->_split_children = GrowableArray<Interval*>(4); 4397 parent->_split_children.append(this); 4398 } 4399 parent->_split_children.append(result); 4400 4401 return result; 4402 } 4403 4404 // split this interval at the specified position and return 4405 // the remainder as a new interval. 4406 // 4407 // when an interval is split, a bi-directional link is established between the original interval 4408 // (the split parent) and the intervals that are split off this interval (the split children) 4409 // When a split child is split again, the new created interval is also a direct child 4410 // of the original parent (there is no tree of split children stored, but a flat list) 4411 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot) 4412 // 4413 // Note: The new interval has no valid reg_num 4414 Interval* Interval::split(int split_pos) { 4415 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); 4416 4417 // allocate new interval 4418 Interval* result = new_split_child(); 4419 4420 // split the ranges 4421 Range* prev = NULL; 4422 Range* cur = _first; 4423 while (cur != Range::end() && cur->to() <= split_pos) { 4424 prev = cur; 4425 cur = cur->next(); 4426 } 4427 assert(cur != Range::end(), "split interval after end of last range"); 4428 4429 if (cur->from() < split_pos) { 4430 result->_first = new Range(split_pos, cur->to(), cur->next()); 4431 cur->set_to(split_pos); 4432 cur->set_next(Range::end()); 4433 4434 } else { 4435 assert(prev != NULL, "split before start of first range"); 4436 result->_first = cur; 4437 prev->set_next(Range::end()); 4438 } 4439 result->_current = result->_first; 4440 _cached_to = -1; // clear cached value 4441 4442 // split list of use positions 4443 int total_len = _use_pos_and_kinds.length(); 4444 int start_idx = total_len - 2; 4445 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) { 4446 start_idx -= 2; 4447 } 4448 4449 intStack new_use_pos_and_kinds(total_len - start_idx); 4450 int i; 4451 for (i = start_idx + 2; i < total_len; i++) { 4452 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i)); 4453 } 4454 4455 _use_pos_and_kinds.truncate(start_idx + 2); 4456 result->_use_pos_and_kinds = _use_pos_and_kinds; 4457 _use_pos_and_kinds = new_use_pos_and_kinds; 4458 4459 #ifdef ASSERT 4460 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); 4461 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); 4462 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries"); 4463 4464 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) { 4465 assert(_use_pos_and_kinds.at(i) < split_pos, "must be"); 4466 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4467 } 4468 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) { 4469 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be"); 4470 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4471 } 4472 #endif 4473 4474 return result; 4475 } 4476 4477 // split this interval at the specified position and return 4478 // the head as a new interval (the original interval is the tail) 4479 // 4480 // Currently, only the first range can be split, and the new interval 4481 // must not have split positions 4482 Interval* Interval::split_from_start(int split_pos) { 4483 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); 4484 assert(split_pos > from() && split_pos < to(), "can only split inside interval"); 4485 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range"); 4486 assert(first_usage(noUse) > split_pos, "can not split when use positions are present"); 4487 4488 // allocate new interval 4489 Interval* result = new_split_child(); 4490 4491 // the new created interval has only one range (checked by assertion above), 4492 // so the splitting of the ranges is very simple 4493 result->add_range(_first->from(), split_pos); 4494 4495 if (split_pos == _first->to()) { 4496 assert(_first->next() != Range::end(), "must not be at end"); 4497 _first = _first->next(); 4498 } else { 4499 _first->set_from(split_pos); 4500 } 4501 4502 return result; 4503 } 4504 4505 4506 // returns true if the op_id is inside the interval 4507 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const { 4508 Range* cur = _first; 4509 4510 while (cur != Range::end() && cur->to() < op_id) { 4511 cur = cur->next(); 4512 } 4513 if (cur != Range::end()) { 4514 assert(cur->to() != cur->next()->from(), "ranges not separated"); 4515 4516 if (mode == LIR_OpVisitState::outputMode) { 4517 return cur->from() <= op_id && op_id < cur->to(); 4518 } else { 4519 return cur->from() <= op_id && op_id <= cur->to(); 4520 } 4521 } 4522 return false; 4523 } 4524 4525 // returns true if the interval has any hole between hole_from and hole_to 4526 // (even if the hole has only the length 1) 4527 bool Interval::has_hole_between(int hole_from, int hole_to) { 4528 assert(hole_from < hole_to, "check"); 4529 assert(from() <= hole_from && hole_to <= to(), "index out of interval"); 4530 4531 Range* cur = _first; 4532 while (cur != Range::end()) { 4533 assert(cur->to() < cur->next()->from(), "no space between ranges"); 4534 4535 // hole-range starts before this range -> hole 4536 if (hole_from < cur->from()) { 4537 return true; 4538 4539 // hole-range completely inside this range -> no hole 4540 } else if (hole_to <= cur->to()) { 4541 return false; 4542 4543 // overlapping of hole-range with this range -> hole 4544 } else if (hole_from <= cur->to()) { 4545 return true; 4546 } 4547 4548 cur = cur->next(); 4549 } 4550 4551 return false; 4552 } 4553 4554 4555 #ifndef PRODUCT 4556 void Interval::print(outputStream* out) const { 4557 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" }; 4558 const char* UseKind2Name[] = { "N", "L", "S", "M" }; 4559 4560 const char* type_name; 4561 LIR_Opr opr = LIR_OprFact::illegal(); 4562 if (reg_num() < LIR_OprDesc::vreg_base) { 4563 type_name = "fixed"; 4564 // need a temporary operand for fixed intervals because type() cannot be called 4565 #ifdef X86 4566 int last_xmm_reg = pd_last_xmm_reg; 4567 #ifdef _LP64 4568 if (UseAVX < 3) { 4569 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1; 4570 } 4571 #endif 4572 #endif 4573 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) { 4574 opr = LIR_OprFact::single_cpu(assigned_reg()); 4575 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) { 4576 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg); 4577 #ifdef X86 4578 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) { 4579 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg); 4580 #endif 4581 } else { 4582 ShouldNotReachHere(); 4583 } 4584 } else { 4585 type_name = type2name(type()); 4586 if (assigned_reg() != -1 && 4587 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) { 4588 opr = LinearScan::calc_operand_for_interval(this); 4589 } 4590 } 4591 4592 out->print("%d %s ", reg_num(), type_name); 4593 if (opr->is_valid()) { 4594 out->print("\""); 4595 opr->print(out); 4596 out->print("\" "); 4597 } 4598 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1)); 4599 4600 // print ranges 4601 Range* cur = _first; 4602 while (cur != Range::end()) { 4603 cur->print(out); 4604 cur = cur->next(); 4605 assert(cur != NULL, "range list not closed with range sentinel"); 4606 } 4607 4608 // print use positions 4609 int prev = 0; 4610 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); 4611 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4612 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4613 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted"); 4614 4615 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]); 4616 prev = _use_pos_and_kinds.at(i); 4617 } 4618 4619 out->print(" \"%s\"", SpillState2Name[spill_state()]); 4620 out->cr(); 4621 } 4622 #endif 4623 4624 4625 4626 // **** Implementation of IntervalWalker **************************** 4627 4628 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) 4629 : _compilation(allocator->compilation()) 4630 , _allocator(allocator) 4631 { 4632 _unhandled_first[fixedKind] = unhandled_fixed_first; 4633 _unhandled_first[anyKind] = unhandled_any_first; 4634 _active_first[fixedKind] = Interval::end(); 4635 _inactive_first[fixedKind] = Interval::end(); 4636 _active_first[anyKind] = Interval::end(); 4637 _inactive_first[anyKind] = Interval::end(); 4638 _current_position = -1; 4639 _current = NULL; 4640 next_interval(); 4641 } 4642 4643 4644 // append interval at top of list 4645 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) { 4646 interval->set_next(*list); *list = interval; 4647 } 4648 4649 4650 // append interval in order of current range from() 4651 void IntervalWalker::append_sorted(Interval** list, Interval* interval) { 4652 Interval* prev = NULL; 4653 Interval* cur = *list; 4654 while (cur->current_from() < interval->current_from()) { 4655 prev = cur; cur = cur->next(); 4656 } 4657 if (prev == NULL) { 4658 *list = interval; 4659 } else { 4660 prev->set_next(interval); 4661 } 4662 interval->set_next(cur); 4663 } 4664 4665 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) { 4666 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position"); 4667 4668 Interval* prev = NULL; 4669 Interval* cur = *list; 4670 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) { 4671 prev = cur; cur = cur->next(); 4672 } 4673 if (prev == NULL) { 4674 *list = interval; 4675 } else { 4676 prev->set_next(interval); 4677 } 4678 interval->set_next(cur); 4679 } 4680 4681 4682 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) { 4683 while (*list != Interval::end() && *list != i) { 4684 list = (*list)->next_addr(); 4685 } 4686 if (*list != Interval::end()) { 4687 assert(*list == i, "check"); 4688 *list = (*list)->next(); 4689 return true; 4690 } else { 4691 return false; 4692 } 4693 } 4694 4695 void IntervalWalker::remove_from_list(Interval* i) { 4696 bool deleted; 4697 4698 if (i->state() == activeState) { 4699 deleted = remove_from_list(active_first_addr(anyKind), i); 4700 } else { 4701 assert(i->state() == inactiveState, "invalid state"); 4702 deleted = remove_from_list(inactive_first_addr(anyKind), i); 4703 } 4704 4705 assert(deleted, "interval has not been found in list"); 4706 } 4707 4708 4709 void IntervalWalker::walk_to(IntervalState state, int from) { 4710 assert (state == activeState || state == inactiveState, "wrong state"); 4711 for_each_interval_kind(kind) { 4712 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind); 4713 Interval* next = *prev; 4714 while (next->current_from() <= from) { 4715 Interval* cur = next; 4716 next = cur->next(); 4717 4718 bool range_has_changed = false; 4719 while (cur->current_to() <= from) { 4720 cur->next_range(); 4721 range_has_changed = true; 4722 } 4723 4724 // also handle move from inactive list to active list 4725 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from); 4726 4727 if (range_has_changed) { 4728 // remove cur from list 4729 *prev = next; 4730 if (cur->current_at_end()) { 4731 // move to handled state (not maintained as a list) 4732 cur->set_state(handledState); 4733 interval_moved(cur, kind, state, handledState); 4734 } else if (cur->current_from() <= from){ 4735 // sort into active list 4736 append_sorted(active_first_addr(kind), cur); 4737 cur->set_state(activeState); 4738 if (*prev == cur) { 4739 assert(state == activeState, "check"); 4740 prev = cur->next_addr(); 4741 } 4742 interval_moved(cur, kind, state, activeState); 4743 } else { 4744 // sort into inactive list 4745 append_sorted(inactive_first_addr(kind), cur); 4746 cur->set_state(inactiveState); 4747 if (*prev == cur) { 4748 assert(state == inactiveState, "check"); 4749 prev = cur->next_addr(); 4750 } 4751 interval_moved(cur, kind, state, inactiveState); 4752 } 4753 } else { 4754 prev = cur->next_addr(); 4755 continue; 4756 } 4757 } 4758 } 4759 } 4760 4761 4762 void IntervalWalker::next_interval() { 4763 IntervalKind kind; 4764 Interval* any = _unhandled_first[anyKind]; 4765 Interval* fixed = _unhandled_first[fixedKind]; 4766 4767 if (any != Interval::end()) { 4768 // intervals may start at same position -> prefer fixed interval 4769 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind; 4770 4771 assert (kind == fixedKind && fixed->from() <= any->from() || 4772 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!"); 4773 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first"); 4774 4775 } else if (fixed != Interval::end()) { 4776 kind = fixedKind; 4777 } else { 4778 _current = NULL; return; 4779 } 4780 _current_kind = kind; 4781 _current = _unhandled_first[kind]; 4782 _unhandled_first[kind] = _current->next(); 4783 _current->set_next(Interval::end()); 4784 _current->rewind_range(); 4785 } 4786 4787 4788 void IntervalWalker::walk_to(int lir_op_id) { 4789 assert(_current_position <= lir_op_id, "can not walk backwards"); 4790 while (current() != NULL) { 4791 bool is_active = current()->from() <= lir_op_id; 4792 int id = is_active ? current()->from() : lir_op_id; 4793 4794 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); }) 4795 4796 // set _current_position prior to call of walk_to 4797 _current_position = id; 4798 4799 // call walk_to even if _current_position == id 4800 walk_to(activeState, id); 4801 walk_to(inactiveState, id); 4802 4803 if (is_active) { 4804 current()->set_state(activeState); 4805 if (activate_current()) { 4806 append_sorted(active_first_addr(current_kind()), current()); 4807 interval_moved(current(), current_kind(), unhandledState, activeState); 4808 } 4809 4810 next_interval(); 4811 } else { 4812 return; 4813 } 4814 } 4815 } 4816 4817 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) { 4818 #ifndef PRODUCT 4819 if (TraceLinearScanLevel >= 4) { 4820 #define print_state(state) \ 4821 switch(state) {\ 4822 case unhandledState: tty->print("unhandled"); break;\ 4823 case activeState: tty->print("active"); break;\ 4824 case inactiveState: tty->print("inactive"); break;\ 4825 case handledState: tty->print("handled"); break;\ 4826 default: ShouldNotReachHere(); \ 4827 } 4828 4829 print_state(from); tty->print(" to "); print_state(to); 4830 tty->fill_to(23); 4831 interval->print(); 4832 4833 #undef print_state 4834 } 4835 #endif 4836 } 4837 4838 4839 4840 // **** Implementation of LinearScanWalker ************************** 4841 4842 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) 4843 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first) 4844 , _move_resolver(allocator) 4845 { 4846 for (int i = 0; i < LinearScan::nof_regs; i++) { 4847 _spill_intervals[i] = new GrowableArray<Interval*>(2); 4848 } 4849 } 4850 4851 4852 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) { 4853 for (int i = _first_reg; i <= _last_reg; i++) { 4854 _use_pos[i] = max_jint; 4855 4856 if (!only_process_use_pos) { 4857 _block_pos[i] = max_jint; 4858 _spill_intervals[i]->clear(); 4859 } 4860 } 4861 } 4862 4863 inline void LinearScanWalker::exclude_from_use(int reg) { 4864 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)"); 4865 if (reg >= _first_reg && reg <= _last_reg) { 4866 _use_pos[reg] = 0; 4867 } 4868 } 4869 inline void LinearScanWalker::exclude_from_use(Interval* i) { 4870 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4871 4872 exclude_from_use(i->assigned_reg()); 4873 exclude_from_use(i->assigned_regHi()); 4874 } 4875 4876 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) { 4877 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0"); 4878 4879 if (reg >= _first_reg && reg <= _last_reg) { 4880 if (_use_pos[reg] > use_pos) { 4881 _use_pos[reg] = use_pos; 4882 } 4883 if (!only_process_use_pos) { 4884 _spill_intervals[reg]->append(i); 4885 } 4886 } 4887 } 4888 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) { 4889 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4890 if (use_pos != -1) { 4891 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos); 4892 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos); 4893 } 4894 } 4895 4896 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) { 4897 if (reg >= _first_reg && reg <= _last_reg) { 4898 if (_block_pos[reg] > block_pos) { 4899 _block_pos[reg] = block_pos; 4900 } 4901 if (_use_pos[reg] > block_pos) { 4902 _use_pos[reg] = block_pos; 4903 } 4904 } 4905 } 4906 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) { 4907 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4908 if (block_pos != -1) { 4909 set_block_pos(i->assigned_reg(), i, block_pos); 4910 set_block_pos(i->assigned_regHi(), i, block_pos); 4911 } 4912 } 4913 4914 4915 void LinearScanWalker::free_exclude_active_fixed() { 4916 Interval* list = active_first(fixedKind); 4917 while (list != Interval::end()) { 4918 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned"); 4919 exclude_from_use(list); 4920 list = list->next(); 4921 } 4922 } 4923 4924 void LinearScanWalker::free_exclude_active_any() { 4925 Interval* list = active_first(anyKind); 4926 while (list != Interval::end()) { 4927 exclude_from_use(list); 4928 list = list->next(); 4929 } 4930 } 4931 4932 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) { 4933 Interval* list = inactive_first(fixedKind); 4934 while (list != Interval::end()) { 4935 if (cur->to() <= list->current_from()) { 4936 assert(list->current_intersects_at(cur) == -1, "must not intersect"); 4937 set_use_pos(list, list->current_from(), true); 4938 } else { 4939 set_use_pos(list, list->current_intersects_at(cur), true); 4940 } 4941 list = list->next(); 4942 } 4943 } 4944 4945 void LinearScanWalker::free_collect_inactive_any(Interval* cur) { 4946 Interval* list = inactive_first(anyKind); 4947 while (list != Interval::end()) { 4948 set_use_pos(list, list->current_intersects_at(cur), true); 4949 list = list->next(); 4950 } 4951 } 4952 4953 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) { 4954 Interval* list = unhandled_first(kind); 4955 while (list != Interval::end()) { 4956 set_use_pos(list, list->intersects_at(cur), true); 4957 if (kind == fixedKind && cur->to() <= list->from()) { 4958 set_use_pos(list, list->from(), true); 4959 } 4960 list = list->next(); 4961 } 4962 } 4963 4964 void LinearScanWalker::spill_exclude_active_fixed() { 4965 Interval* list = active_first(fixedKind); 4966 while (list != Interval::end()) { 4967 exclude_from_use(list); 4968 list = list->next(); 4969 } 4970 } 4971 4972 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) { 4973 Interval* list = unhandled_first(fixedKind); 4974 while (list != Interval::end()) { 4975 set_block_pos(list, list->intersects_at(cur)); 4976 list = list->next(); 4977 } 4978 } 4979 4980 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) { 4981 Interval* list = inactive_first(fixedKind); 4982 while (list != Interval::end()) { 4983 if (cur->to() > list->current_from()) { 4984 set_block_pos(list, list->current_intersects_at(cur)); 4985 } else { 4986 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect"); 4987 } 4988 4989 list = list->next(); 4990 } 4991 } 4992 4993 void LinearScanWalker::spill_collect_active_any() { 4994 Interval* list = active_first(anyKind); 4995 while (list != Interval::end()) { 4996 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); 4997 list = list->next(); 4998 } 4999 } 5000 5001 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) { 5002 Interval* list = inactive_first(anyKind); 5003 while (list != Interval::end()) { 5004 if (list->current_intersects(cur)) { 5005 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); 5006 } 5007 list = list->next(); 5008 } 5009 } 5010 5011 5012 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) { 5013 // output all moves here. When source and target are equal, the move is 5014 // optimized away later in assign_reg_nums 5015 5016 op_id = (op_id + 1) & ~1; 5017 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id); 5018 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary"); 5019 5020 // calculate index of instruction inside instruction list of current block 5021 // the minimal index (for a block with no spill moves) can be calculated because the 5022 // numbering of instructions is known. 5023 // When the block already contains spill moves, the index must be increased until the 5024 // correct index is reached. 5025 LIR_OpList* list = op_block->lir()->instructions_list(); 5026 int index = (op_id - list->at(0)->id()) / 2; 5027 assert(list->at(index)->id() <= op_id, "error in calculation"); 5028 5029 while (list->at(index)->id() != op_id) { 5030 index++; 5031 assert(0 <= index && index < list->length(), "index out of bounds"); 5032 } 5033 assert(1 <= index && index < list->length(), "index out of bounds"); 5034 assert(list->at(index)->id() == op_id, "error in calculation"); 5035 5036 // insert new instruction before instruction at position index 5037 _move_resolver.move_insert_position(op_block->lir(), index - 1); 5038 _move_resolver.add_mapping(src_it, dst_it); 5039 } 5040 5041 5042 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) { 5043 int from_block_nr = min_block->linear_scan_number(); 5044 int to_block_nr = max_block->linear_scan_number(); 5045 5046 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range"); 5047 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range"); 5048 assert(from_block_nr < to_block_nr, "must cross block boundary"); 5049 5050 // Try to split at end of max_block. If this would be after 5051 // max_split_pos, then use the begin of max_block 5052 int optimal_split_pos = max_block->last_lir_instruction_id() + 2; 5053 if (optimal_split_pos > max_split_pos) { 5054 optimal_split_pos = max_block->first_lir_instruction_id(); 5055 } 5056 5057 int min_loop_depth = max_block->loop_depth(); 5058 for (int i = to_block_nr - 1; i >= from_block_nr; i--) { 5059 BlockBegin* cur = block_at(i); 5060 5061 if (cur->loop_depth() < min_loop_depth) { 5062 // block with lower loop-depth found -> split at the end of this block 5063 min_loop_depth = cur->loop_depth(); 5064 optimal_split_pos = cur->last_lir_instruction_id() + 2; 5065 } 5066 } 5067 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary"); 5068 5069 return optimal_split_pos; 5070 } 5071 5072 5073 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) { 5074 int optimal_split_pos = -1; 5075 if (min_split_pos == max_split_pos) { 5076 // trivial case, no optimization of split position possible 5077 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible")); 5078 optimal_split_pos = min_split_pos; 5079 5080 } else { 5081 assert(min_split_pos < max_split_pos, "must be true then"); 5082 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise"); 5083 5084 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the 5085 // beginning of a block, then min_split_pos is also a possible split position. 5086 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos 5087 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1); 5088 5089 // reason for using max_split_pos - 1: otherwise there would be an assertion failure 5090 // when an interval ends at the end of the last block of the method 5091 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no 5092 // block at this op_id) 5093 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1); 5094 5095 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order"); 5096 if (min_block == max_block) { 5097 // split position cannot be moved to block boundary, so split as late as possible 5098 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block")); 5099 optimal_split_pos = max_split_pos; 5100 5101 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) { 5102 // Do not move split position if the interval has a hole before max_split_pos. 5103 // Intervals resulting from Phi-Functions have more than one definition (marked 5104 // as mustHaveRegister) with a hole before each definition. When the register is needed 5105 // for the second definition, an earlier reloading is unnecessary. 5106 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos")); 5107 optimal_split_pos = max_split_pos; 5108 5109 } else { 5110 // seach optimal block boundary between min_split_pos and max_split_pos 5111 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id())); 5112 5113 if (do_loop_optimization) { 5114 // Loop optimization: if a loop-end marker is found between min- and max-position, 5115 // then split before this loop 5116 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2); 5117 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos)); 5118 5119 assert(loop_end_pos > min_split_pos, "invalid order"); 5120 if (loop_end_pos < max_split_pos) { 5121 // loop-end marker found between min- and max-position 5122 // if it is not the end marker for the same loop as the min-position, then move 5123 // the max-position to this loop block. 5124 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading 5125 // of the interval (normally, only mustHaveRegister causes a reloading) 5126 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos); 5127 5128 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id())); 5129 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between"); 5130 5131 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2); 5132 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) { 5133 optimal_split_pos = -1; 5134 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary")); 5135 } else { 5136 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful")); 5137 } 5138 } 5139 } 5140 5141 if (optimal_split_pos == -1) { 5142 // not calculated by loop optimization 5143 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos); 5144 } 5145 } 5146 } 5147 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos)); 5148 5149 return optimal_split_pos; 5150 } 5151 5152 5153 /* 5154 split an interval at the optimal position between min_split_pos and 5155 max_split_pos in two parts: 5156 1) the left part has already a location assigned 5157 2) the right part is sorted into to the unhandled-list 5158 */ 5159 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) { 5160 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print()); 5161 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); 5162 5163 assert(it->from() < min_split_pos, "cannot split at start of interval"); 5164 assert(current_position() < min_split_pos, "cannot split before current position"); 5165 assert(min_split_pos <= max_split_pos, "invalid order"); 5166 assert(max_split_pos <= it->to(), "cannot split after end of interval"); 5167 5168 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true); 5169 5170 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); 5171 assert(optimal_split_pos <= it->to(), "cannot split after end of interval"); 5172 assert(optimal_split_pos > it->from(), "cannot split at start of interval"); 5173 5174 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) { 5175 // the split position would be just before the end of the interval 5176 // -> no split at all necessary 5177 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval")); 5178 return; 5179 } 5180 5181 // must calculate this before the actual split is performed and before split position is moved to odd op_id 5182 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos); 5183 5184 if (!allocator()->is_block_begin(optimal_split_pos)) { 5185 // move position before actual instruction (odd op_id) 5186 optimal_split_pos = (optimal_split_pos - 1) | 1; 5187 } 5188 5189 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); 5190 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); 5191 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); 5192 5193 Interval* split_part = it->split(optimal_split_pos); 5194 5195 allocator()->append_interval(split_part); 5196 allocator()->copy_register_flags(it, split_part); 5197 split_part->set_insert_move_when_activated(move_necessary); 5198 append_to_unhandled(unhandled_first_addr(anyKind), split_part); 5199 5200 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary)); 5201 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); 5202 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print()); 5203 } 5204 5205 /* 5206 split an interval at the optimal position between min_split_pos and 5207 max_split_pos in two parts: 5208 1) the left part has already a location assigned 5209 2) the right part is always on the stack and therefore ignored in further processing 5210 */ 5211 void LinearScanWalker::split_for_spilling(Interval* it) { 5212 // calculate allowed range of splitting position 5213 int max_split_pos = current_position(); 5214 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from()); 5215 5216 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print()); 5217 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); 5218 5219 assert(it->state() == activeState, "why spill interval that is not active?"); 5220 assert(it->from() <= min_split_pos, "cannot split before start of interval"); 5221 assert(min_split_pos <= max_split_pos, "invalid order"); 5222 assert(max_split_pos < it->to(), "cannot split at end end of interval"); 5223 assert(current_position() < it->to(), "interval must not end before current position"); 5224 5225 if (min_split_pos == it->from()) { 5226 // the whole interval is never used, so spill it entirely to memory 5227 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval")); 5228 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position"); 5229 5230 allocator()->assign_spill_slot(it); 5231 allocator()->change_spill_state(it, min_split_pos); 5232 5233 // Also kick parent intervals out of register to memory when they have no use 5234 // position. This avoids short interval in register surrounded by intervals in 5235 // memory -> avoid useless moves from memory to register and back 5236 Interval* parent = it; 5237 while (parent != NULL && parent->is_split_child()) { 5238 parent = parent->split_child_before_op_id(parent->from()); 5239 5240 if (parent->assigned_reg() < LinearScan::nof_regs) { 5241 if (parent->first_usage(shouldHaveRegister) == max_jint) { 5242 // parent is never used, so kick it out of its assigned register 5243 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num())); 5244 allocator()->assign_spill_slot(parent); 5245 } else { 5246 // do not go further back because the register is actually used by the interval 5247 parent = NULL; 5248 } 5249 } 5250 } 5251 5252 } else { 5253 // search optimal split pos, split interval and spill only the right hand part 5254 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false); 5255 5256 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); 5257 assert(optimal_split_pos < it->to(), "cannot split at end of interval"); 5258 assert(optimal_split_pos >= it->from(), "cannot split before start of interval"); 5259 5260 if (!allocator()->is_block_begin(optimal_split_pos)) { 5261 // move position before actual instruction (odd op_id) 5262 optimal_split_pos = (optimal_split_pos - 1) | 1; 5263 } 5264 5265 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); 5266 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); 5267 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); 5268 5269 Interval* spilled_part = it->split(optimal_split_pos); 5270 allocator()->append_interval(spilled_part); 5271 allocator()->assign_spill_slot(spilled_part); 5272 allocator()->change_spill_state(spilled_part, optimal_split_pos); 5273 5274 if (!allocator()->is_block_begin(optimal_split_pos)) { 5275 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num())); 5276 insert_move(optimal_split_pos, it, spilled_part); 5277 } 5278 5279 // the current_split_child is needed later when moves are inserted for reloading 5280 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child"); 5281 spilled_part->make_current_split_child(); 5282 5283 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts")); 5284 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); 5285 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print()); 5286 } 5287 } 5288 5289 5290 void LinearScanWalker::split_stack_interval(Interval* it) { 5291 int min_split_pos = current_position() + 1; 5292 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to()); 5293 5294 split_before_usage(it, min_split_pos, max_split_pos); 5295 } 5296 5297 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) { 5298 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1); 5299 int max_split_pos = register_available_until; 5300 5301 split_before_usage(it, min_split_pos, max_split_pos); 5302 } 5303 5304 void LinearScanWalker::split_and_spill_interval(Interval* it) { 5305 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed"); 5306 5307 int current_pos = current_position(); 5308 if (it->state() == inactiveState) { 5309 // the interval is currently inactive, so no spill slot is needed for now. 5310 // when the split part is activated, the interval has a new chance to get a register, 5311 // so in the best case no stack slot is necessary 5312 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise"); 5313 split_before_usage(it, current_pos + 1, current_pos + 1); 5314 5315 } else { 5316 // search the position where the interval must have a register and split 5317 // at the optimal position before. 5318 // The new created part is added to the unhandled list and will get a register 5319 // when it is activated 5320 int min_split_pos = current_pos + 1; 5321 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to()); 5322 5323 split_before_usage(it, min_split_pos, max_split_pos); 5324 5325 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register"); 5326 split_for_spilling(it); 5327 } 5328 } 5329 5330 5331 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { 5332 int min_full_reg = any_reg; 5333 int max_partial_reg = any_reg; 5334 5335 for (int i = _first_reg; i <= _last_reg; i++) { 5336 if (i == ignore_reg) { 5337 // this register must be ignored 5338 5339 } else if (_use_pos[i] >= interval_to) { 5340 // this register is free for the full interval 5341 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { 5342 min_full_reg = i; 5343 } 5344 } else if (_use_pos[i] > reg_needed_until) { 5345 // this register is at least free until reg_needed_until 5346 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { 5347 max_partial_reg = i; 5348 } 5349 } 5350 } 5351 5352 if (min_full_reg != any_reg) { 5353 return min_full_reg; 5354 } else if (max_partial_reg != any_reg) { 5355 *need_split = true; 5356 return max_partial_reg; 5357 } else { 5358 return any_reg; 5359 } 5360 } 5361 5362 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { 5363 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); 5364 5365 int min_full_reg = any_reg; 5366 int max_partial_reg = any_reg; 5367 5368 for (int i = _first_reg; i < _last_reg; i+=2) { 5369 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) { 5370 // this register is free for the full interval 5371 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { 5372 min_full_reg = i; 5373 } 5374 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { 5375 // this register is at least free until reg_needed_until 5376 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { 5377 max_partial_reg = i; 5378 } 5379 } 5380 } 5381 5382 if (min_full_reg != any_reg) { 5383 return min_full_reg; 5384 } else if (max_partial_reg != any_reg) { 5385 *need_split = true; 5386 return max_partial_reg; 5387 } else { 5388 return any_reg; 5389 } 5390 } 5391 5392 5393 bool LinearScanWalker::alloc_free_reg(Interval* cur) { 5394 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print()); 5395 5396 init_use_lists(true); 5397 free_exclude_active_fixed(); 5398 free_exclude_active_any(); 5399 free_collect_inactive_fixed(cur); 5400 free_collect_inactive_any(cur); 5401 // free_collect_unhandled(fixedKind, cur); 5402 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); 5403 5404 // _use_pos contains the start of the next interval that has this register assigned 5405 // (either as a fixed register or a normal allocated register in the past) 5406 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely 5407 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:")); 5408 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i])); 5409 5410 int hint_reg, hint_regHi; 5411 Interval* register_hint = cur->register_hint(); 5412 if (register_hint != NULL) { 5413 hint_reg = register_hint->assigned_reg(); 5414 hint_regHi = register_hint->assigned_regHi(); 5415 5416 if (allocator()->is_precolored_cpu_interval(register_hint)) { 5417 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals"); 5418 hint_regHi = hint_reg + 1; // connect e.g. eax-edx 5419 } 5420 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print()); 5421 5422 } else { 5423 hint_reg = any_reg; 5424 hint_regHi = any_reg; 5425 } 5426 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal"); 5427 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval"); 5428 5429 // the register must be free at least until this position 5430 int reg_needed_until = cur->from() + 1; 5431 int interval_to = cur->to(); 5432 5433 bool need_split = false; 5434 int split_pos = -1; 5435 int reg = any_reg; 5436 int regHi = any_reg; 5437 5438 if (_adjacent_regs) { 5439 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split); 5440 regHi = reg + 1; 5441 if (reg == any_reg) { 5442 return false; 5443 } 5444 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]); 5445 5446 } else { 5447 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split); 5448 if (reg == any_reg) { 5449 return false; 5450 } 5451 split_pos = _use_pos[reg]; 5452 5453 if (_num_phys_regs == 2) { 5454 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split); 5455 5456 if (_use_pos[reg] < interval_to && regHi == any_reg) { 5457 // do not split interval if only one register can be assigned until the split pos 5458 // (when one register is found for the whole interval, split&spill is only 5459 // performed for the hi register) 5460 return false; 5461 5462 } else if (regHi != any_reg) { 5463 split_pos = MIN2(split_pos, _use_pos[regHi]); 5464 5465 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax 5466 if (reg > regHi) { 5467 int temp = reg; 5468 reg = regHi; 5469 regHi = temp; 5470 } 5471 } 5472 } 5473 } 5474 5475 cur->assign_reg(reg, regHi); 5476 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi)); 5477 5478 assert(split_pos > 0, "invalid split_pos"); 5479 if (need_split) { 5480 // register not available for full interval, so split it 5481 split_when_partial_register_available(cur, split_pos); 5482 } 5483 5484 // only return true if interval is completely assigned 5485 return _num_phys_regs == 1 || regHi != any_reg; 5486 } 5487 5488 5489 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { 5490 int max_reg = any_reg; 5491 5492 for (int i = _first_reg; i <= _last_reg; i++) { 5493 if (i == ignore_reg) { 5494 // this register must be ignored 5495 5496 } else if (_use_pos[i] > reg_needed_until) { 5497 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) { 5498 max_reg = i; 5499 } 5500 } 5501 } 5502 5503 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) { 5504 *need_split = true; 5505 } 5506 5507 return max_reg; 5508 } 5509 5510 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { 5511 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); 5512 5513 int max_reg = any_reg; 5514 5515 for (int i = _first_reg; i < _last_reg; i+=2) { 5516 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { 5517 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) { 5518 max_reg = i; 5519 } 5520 } 5521 } 5522 5523 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) { 5524 *need_split = true; 5525 } 5526 5527 return max_reg; 5528 } 5529 5530 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) { 5531 assert(reg != any_reg, "no register assigned"); 5532 5533 for (int i = 0; i < _spill_intervals[reg]->length(); i++) { 5534 Interval* it = _spill_intervals[reg]->at(i); 5535 remove_from_list(it); 5536 split_and_spill_interval(it); 5537 } 5538 5539 if (regHi != any_reg) { 5540 GrowableArray<Interval*>* processed = _spill_intervals[reg]; 5541 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) { 5542 Interval* it = _spill_intervals[regHi]->at(i); 5543 if (processed->find_from_end(it) == -1) { 5544 remove_from_list(it); 5545 split_and_spill_interval(it); 5546 } 5547 } 5548 } 5549 } 5550 5551 5552 // Split an Interval and spill it to memory so that cur can be placed in a register 5553 void LinearScanWalker::alloc_locked_reg(Interval* cur) { 5554 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print()); 5555 5556 // collect current usage of registers 5557 init_use_lists(false); 5558 spill_exclude_active_fixed(); 5559 // spill_block_unhandled_fixed(cur); 5560 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); 5561 spill_block_inactive_fixed(cur); 5562 spill_collect_active_any(); 5563 spill_collect_inactive_any(cur); 5564 5565 #ifndef PRODUCT 5566 if (TraceLinearScanLevel >= 4) { 5567 tty->print_cr(" state of registers:"); 5568 for (int i = _first_reg; i <= _last_reg; i++) { 5569 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]); 5570 for (int j = 0; j < _spill_intervals[i]->length(); j++) { 5571 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num()); 5572 } 5573 tty->cr(); 5574 } 5575 } 5576 #endif 5577 5578 // the register must be free at least until this position 5579 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1); 5580 int interval_to = cur->to(); 5581 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use"); 5582 5583 int split_pos = 0; 5584 int use_pos = 0; 5585 bool need_split = false; 5586 int reg, regHi; 5587 5588 if (_adjacent_regs) { 5589 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split); 5590 regHi = reg + 1; 5591 5592 if (reg != any_reg) { 5593 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]); 5594 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]); 5595 } 5596 } else { 5597 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split); 5598 regHi = any_reg; 5599 5600 if (reg != any_reg) { 5601 use_pos = _use_pos[reg]; 5602 split_pos = _block_pos[reg]; 5603 5604 if (_num_phys_regs == 2) { 5605 if (cur->assigned_reg() != any_reg) { 5606 regHi = reg; 5607 reg = cur->assigned_reg(); 5608 } else { 5609 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split); 5610 if (regHi != any_reg) { 5611 use_pos = MIN2(use_pos, _use_pos[regHi]); 5612 split_pos = MIN2(split_pos, _block_pos[regHi]); 5613 } 5614 } 5615 5616 if (regHi != any_reg && reg > regHi) { 5617 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax 5618 int temp = reg; 5619 reg = regHi; 5620 regHi = temp; 5621 } 5622 } 5623 } 5624 } 5625 5626 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) { 5627 // the first use of cur is later than the spilling position -> spill cur 5628 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos)); 5629 5630 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) { 5631 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)"); 5632 // assign a reasonable register and do a bailout in product mode to avoid errors 5633 allocator()->assign_spill_slot(cur); 5634 BAILOUT("LinearScan: no register found"); 5635 } 5636 5637 split_and_spill_interval(cur); 5638 } else { 5639 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi)); 5640 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found"); 5641 assert(split_pos > 0, "invalid split_pos"); 5642 assert(need_split == false || split_pos > cur->from(), "splitting interval at from"); 5643 5644 cur->assign_reg(reg, regHi); 5645 if (need_split) { 5646 // register not available for full interval, so split it 5647 split_when_partial_register_available(cur, split_pos); 5648 } 5649 5650 // perform splitting and spilling for all affected intervalls 5651 split_and_spill_intersecting_intervals(reg, regHi); 5652 } 5653 } 5654 5655 bool LinearScanWalker::no_allocation_possible(Interval* cur) { 5656 #ifdef X86 5657 // fast calculation of intervals that can never get a register because the 5658 // the next instruction is a call that blocks all registers 5659 // Note: this does not work if callee-saved registers are available (e.g. on Sparc) 5660 5661 // check if this interval is the result of a split operation 5662 // (an interval got a register until this position) 5663 int pos = cur->from(); 5664 if ((pos & 1) == 1) { 5665 // the current instruction is a call that blocks all registers 5666 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) { 5667 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call")); 5668 5669 // safety check that there is really no register available 5670 assert(alloc_free_reg(cur) == false, "found a register for this interval"); 5671 return true; 5672 } 5673 5674 } 5675 #endif 5676 return false; 5677 } 5678 5679 void LinearScanWalker::init_vars_for_alloc(Interval* cur) { 5680 BasicType type = cur->type(); 5681 _num_phys_regs = LinearScan::num_physical_regs(type); 5682 _adjacent_regs = LinearScan::requires_adjacent_regs(type); 5683 5684 if (pd_init_regs_for_alloc(cur)) { 5685 // the appropriate register range was selected. 5686 } else if (type == T_FLOAT || type == T_DOUBLE) { 5687 _first_reg = pd_first_fpu_reg; 5688 _last_reg = pd_last_fpu_reg; 5689 } else { 5690 _first_reg = pd_first_cpu_reg; 5691 _last_reg = FrameMap::last_cpu_reg(); 5692 } 5693 5694 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range"); 5695 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range"); 5696 } 5697 5698 5699 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) { 5700 if (op->code() != lir_move) { 5701 return false; 5702 } 5703 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 5704 5705 LIR_Opr in = ((LIR_Op1*)op)->in_opr(); 5706 LIR_Opr res = ((LIR_Op1*)op)->result_opr(); 5707 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num(); 5708 } 5709 5710 // optimization (especially for phi functions of nested loops): 5711 // assign same spill slot to non-intersecting intervals 5712 void LinearScanWalker::combine_spilled_intervals(Interval* cur) { 5713 if (cur->is_split_child()) { 5714 // optimization is only suitable for split parents 5715 return; 5716 } 5717 5718 Interval* register_hint = cur->register_hint(false); 5719 if (register_hint == NULL) { 5720 // cur is not the target of a move, otherwise register_hint would be set 5721 return; 5722 } 5723 assert(register_hint->is_split_parent(), "register hint must be split parent"); 5724 5725 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) { 5726 // combining the stack slots for intervals where spill move optimization is applied 5727 // is not benefitial and would cause problems 5728 return; 5729 } 5730 5731 int begin_pos = cur->from(); 5732 int end_pos = cur->to(); 5733 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) { 5734 // safety check that lir_op_with_id is allowed 5735 return; 5736 } 5737 5738 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) { 5739 // cur and register_hint are not connected with two moves 5740 return; 5741 } 5742 5743 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode); 5744 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode); 5745 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) { 5746 // register_hint must be split, otherwise the re-writing of use positions does not work 5747 return; 5748 } 5749 5750 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned"); 5751 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned"); 5752 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move"); 5753 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move"); 5754 5755 if (begin_hint->assigned_reg() < LinearScan::nof_regs) { 5756 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur 5757 return; 5758 } 5759 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled"); 5760 5761 // modify intervals such that cur gets the same stack slot as register_hint 5762 // delete use positions to prevent the intervals to get a register at beginning 5763 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot()); 5764 cur->remove_first_use_pos(); 5765 end_hint->remove_first_use_pos(); 5766 } 5767 5768 5769 // allocate a physical register or memory location to an interval 5770 bool LinearScanWalker::activate_current() { 5771 Interval* cur = current(); 5772 bool result = true; 5773 5774 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print()); 5775 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated())); 5776 5777 if (cur->assigned_reg() >= LinearScan::nof_regs) { 5778 // activating an interval that has a stack slot assigned -> split it at first use position 5779 // used for method parameters 5780 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use")); 5781 5782 split_stack_interval(cur); 5783 result = false; 5784 5785 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) { 5786 // activating an interval that must start in a stack slot, but may get a register later 5787 // used for lir_roundfp: rounding is done by store to stack and reload later 5788 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use")); 5789 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned"); 5790 5791 allocator()->assign_spill_slot(cur); 5792 split_stack_interval(cur); 5793 result = false; 5794 5795 } else if (cur->assigned_reg() == any_reg) { 5796 // interval has not assigned register -> normal allocation 5797 // (this is the normal case for most intervals) 5798 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register")); 5799 5800 // assign same spill slot to non-intersecting intervals 5801 combine_spilled_intervals(cur); 5802 5803 init_vars_for_alloc(cur); 5804 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) { 5805 // no empty register available. 5806 // split and spill another interval so that this interval gets a register 5807 alloc_locked_reg(cur); 5808 } 5809 5810 // spilled intervals need not be move to active-list 5811 if (cur->assigned_reg() >= LinearScan::nof_regs) { 5812 result = false; 5813 } 5814 } 5815 5816 // load spilled values that become active from stack slot to register 5817 if (cur->insert_move_when_activated()) { 5818 assert(cur->is_split_child(), "must be"); 5819 assert(cur->current_split_child() != NULL, "must be"); 5820 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval"); 5821 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num())); 5822 5823 insert_move(cur->from(), cur->current_split_child(), cur); 5824 } 5825 cur->make_current_split_child(); 5826 5827 return result; // true = interval is moved to active list 5828 } 5829 5830 5831 // Implementation of EdgeMoveOptimizer 5832 5833 EdgeMoveOptimizer::EdgeMoveOptimizer() : 5834 _edge_instructions(4), 5835 _edge_instructions_idx(4) 5836 { 5837 } 5838 5839 void EdgeMoveOptimizer::optimize(BlockList* code) { 5840 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer(); 5841 5842 // ignore the first block in the list (index 0 is not processed) 5843 for (int i = code->length() - 1; i >= 1; i--) { 5844 BlockBegin* block = code->at(i); 5845 5846 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) { 5847 optimizer.optimize_moves_at_block_end(block); 5848 } 5849 if (block->number_of_sux() == 2) { 5850 optimizer.optimize_moves_at_block_begin(block); 5851 } 5852 } 5853 } 5854 5855 5856 // clear all internal data structures 5857 void EdgeMoveOptimizer::init_instructions() { 5858 _edge_instructions.clear(); 5859 _edge_instructions_idx.clear(); 5860 } 5861 5862 // append a lir-instruction-list and the index of the current operation in to the list 5863 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) { 5864 _edge_instructions.append(instructions); 5865 _edge_instructions_idx.append(instructions_idx); 5866 } 5867 5868 // return the current operation of the given edge (predecessor or successor) 5869 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) { 5870 LIR_OpList* instructions = _edge_instructions.at(edge); 5871 int idx = _edge_instructions_idx.at(edge); 5872 5873 if (idx < instructions->length()) { 5874 return instructions->at(idx); 5875 } else { 5876 return NULL; 5877 } 5878 } 5879 5880 // removes the current operation of the given edge (predecessor or successor) 5881 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) { 5882 LIR_OpList* instructions = _edge_instructions.at(edge); 5883 int idx = _edge_instructions_idx.at(edge); 5884 instructions->remove_at(idx); 5885 5886 if (decrement_index) { 5887 _edge_instructions_idx.at_put(edge, idx - 1); 5888 } 5889 } 5890 5891 5892 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { 5893 if (op1 == NULL || op2 == NULL) { 5894 // at least one block is already empty -> no optimization possible 5895 return true; 5896 } 5897 5898 if (op1->code() == lir_move && op2->code() == lir_move) { 5899 assert(op1->as_Op1() != NULL, "move must be LIR_Op1"); 5900 assert(op2->as_Op1() != NULL, "move must be LIR_Op1"); 5901 LIR_Op1* move1 = (LIR_Op1*)op1; 5902 LIR_Op1* move2 = (LIR_Op1*)op2; 5903 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) { 5904 // these moves are exactly equal and can be optimized 5905 return false; 5906 } 5907 5908 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { 5909 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1"); 5910 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1"); 5911 LIR_Op1* fxch1 = (LIR_Op1*)op1; 5912 LIR_Op1* fxch2 = (LIR_Op1*)op2; 5913 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { 5914 // equal FPU stack operations can be optimized 5915 return false; 5916 } 5917 5918 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { 5919 // equal FPU stack operations can be optimized 5920 return false; 5921 } 5922 5923 // no optimization possible 5924 return true; 5925 } 5926 5927 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) { 5928 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id())); 5929 5930 if (block->is_predecessor(block)) { 5931 // currently we can't handle this correctly. 5932 return; 5933 } 5934 5935 init_instructions(); 5936 int num_preds = block->number_of_preds(); 5937 assert(num_preds > 1, "do not call otherwise"); 5938 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); 5939 5940 // setup a list with the lir-instructions of all predecessors 5941 int i; 5942 for (i = 0; i < num_preds; i++) { 5943 BlockBegin* pred = block->pred_at(i); 5944 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); 5945 5946 if (pred->number_of_sux() != 1) { 5947 // this can happen with switch-statements where multiple edges are between 5948 // the same blocks. 5949 return; 5950 } 5951 5952 assert(pred->number_of_sux() == 1, "can handle only one successor"); 5953 assert(pred->sux_at(0) == block, "invalid control flow"); 5954 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch"); 5955 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 5956 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); 5957 5958 if (pred_instructions->last()->info() != NULL) { 5959 // can not optimize instructions when debug info is needed 5960 return; 5961 } 5962 5963 // ignore the unconditional branch at the end of the block 5964 append_instructions(pred_instructions, pred_instructions->length() - 2); 5965 } 5966 5967 5968 // process lir-instructions while all predecessors end with the same instruction 5969 while (true) { 5970 LIR_Op* op = instruction_at(0); 5971 for (i = 1; i < num_preds; i++) { 5972 if (operations_different(op, instruction_at(i))) { 5973 // these instructions are different and cannot be optimized -> 5974 // no further optimization possible 5975 return; 5976 } 5977 } 5978 5979 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print()); 5980 5981 // insert the instruction at the beginning of the current block 5982 block->lir()->insert_before(1, op); 5983 5984 // delete the instruction at the end of all predecessors 5985 for (i = 0; i < num_preds; i++) { 5986 remove_cur_instruction(i, true); 5987 } 5988 } 5989 } 5990 5991 5992 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) { 5993 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id())); 5994 5995 init_instructions(); 5996 int num_sux = block->number_of_sux(); 5997 5998 LIR_OpList* cur_instructions = block->lir()->instructions_list(); 5999 6000 assert(num_sux == 2, "method should not be called otherwise"); 6001 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch"); 6002 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 6003 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); 6004 6005 if (cur_instructions->last()->info() != NULL) { 6006 // can no optimize instructions when debug info is needed 6007 return; 6008 } 6009 6010 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2); 6011 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) { 6012 // not a valid case for optimization 6013 // currently, only blocks that end with two branches (conditional branch followed 6014 // by unconditional branch) are optimized 6015 return; 6016 } 6017 6018 // now it is guaranteed that the block ends with two branch instructions. 6019 // the instructions are inserted at the end of the block before these two branches 6020 int insert_idx = cur_instructions->length() - 2; 6021 6022 int i; 6023 #ifdef ASSERT 6024 for (i = insert_idx - 1; i >= 0; i--) { 6025 LIR_Op* op = cur_instructions->at(i); 6026 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) { 6027 assert(false, "block with two successors can have only two branch instructions"); 6028 } 6029 } 6030 #endif 6031 6032 // setup a list with the lir-instructions of all successors 6033 for (i = 0; i < num_sux; i++) { 6034 BlockBegin* sux = block->sux_at(i); 6035 LIR_OpList* sux_instructions = sux->lir()->instructions_list(); 6036 6037 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label"); 6038 6039 if (sux->number_of_preds() != 1) { 6040 // this can happen with switch-statements where multiple edges are between 6041 // the same blocks. 6042 return; 6043 } 6044 assert(sux->pred_at(0) == block, "invalid control flow"); 6045 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); 6046 6047 // ignore the label at the beginning of the block 6048 append_instructions(sux_instructions, 1); 6049 } 6050 6051 // process lir-instructions while all successors begin with the same instruction 6052 while (true) { 6053 LIR_Op* op = instruction_at(0); 6054 for (i = 1; i < num_sux; i++) { 6055 if (operations_different(op, instruction_at(i))) { 6056 // these instructions are different and cannot be optimized -> 6057 // no further optimization possible 6058 return; 6059 } 6060 } 6061 6062 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print()); 6063 6064 // insert instruction at end of current block 6065 block->lir()->insert_before(insert_idx, op); 6066 insert_idx++; 6067 6068 // delete the instructions at the beginning of all successors 6069 for (i = 0; i < num_sux; i++) { 6070 remove_cur_instruction(i, false); 6071 } 6072 } 6073 } 6074 6075 6076 // Implementation of ControlFlowOptimizer 6077 6078 ControlFlowOptimizer::ControlFlowOptimizer() : 6079 _original_preds(4) 6080 { 6081 } 6082 6083 void ControlFlowOptimizer::optimize(BlockList* code) { 6084 ControlFlowOptimizer optimizer = ControlFlowOptimizer(); 6085 6086 // push the OSR entry block to the end so that we're not jumping over it. 6087 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry(); 6088 if (osr_entry) { 6089 int index = osr_entry->linear_scan_number(); 6090 assert(code->at(index) == osr_entry, "wrong index"); 6091 code->remove_at(index); 6092 code->append(osr_entry); 6093 } 6094 6095 optimizer.reorder_short_loops(code); 6096 optimizer.delete_empty_blocks(code); 6097 optimizer.delete_unnecessary_jumps(code); 6098 optimizer.delete_jumps_to_return(code); 6099 } 6100 6101 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) { 6102 int i = header_idx + 1; 6103 int max_end = MIN2(header_idx + ShortLoopSize, code->length()); 6104 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) { 6105 i++; 6106 } 6107 6108 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) { 6109 int end_idx = i - 1; 6110 BlockBegin* end_block = code->at(end_idx); 6111 6112 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) { 6113 // short loop from header_idx to end_idx found -> reorder blocks such that 6114 // the header_block is the last block instead of the first block of the loop 6115 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d", 6116 end_idx - header_idx + 1, 6117 header_block->block_id(), end_block->block_id())); 6118 6119 for (int j = header_idx; j < end_idx; j++) { 6120 code->at_put(j, code->at(j + 1)); 6121 } 6122 code->at_put(end_idx, header_block); 6123 6124 // correct the flags so that any loop alignment occurs in the right place. 6125 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target"); 6126 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag); 6127 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag); 6128 } 6129 } 6130 } 6131 6132 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) { 6133 for (int i = code->length() - 1; i >= 0; i--) { 6134 BlockBegin* block = code->at(i); 6135 6136 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) { 6137 reorder_short_loop(code, block, i); 6138 } 6139 } 6140 6141 DEBUG_ONLY(verify(code)); 6142 } 6143 6144 // only blocks with exactly one successor can be deleted. Such blocks 6145 // must always end with an unconditional branch to this successor 6146 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) { 6147 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) { 6148 return false; 6149 } 6150 6151 LIR_OpList* instructions = block->lir()->instructions_list(); 6152 6153 assert(instructions->length() >= 2, "block must have label and branch"); 6154 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6155 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch"); 6156 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional"); 6157 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor"); 6158 6159 // block must have exactly one successor 6160 6161 if (instructions->length() == 2 && instructions->last()->info() == NULL) { 6162 return true; 6163 } 6164 return false; 6165 } 6166 6167 // substitute branch targets in all branch-instructions of this blocks 6168 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) { 6169 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id())); 6170 6171 LIR_OpList* instructions = block->lir()->instructions_list(); 6172 6173 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6174 for (int i = instructions->length() - 1; i >= 1; i--) { 6175 LIR_Op* op = instructions->at(i); 6176 6177 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) { 6178 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6179 LIR_OpBranch* branch = (LIR_OpBranch*)op; 6180 6181 if (branch->block() == target_from) { 6182 branch->change_block(target_to); 6183 } 6184 if (branch->ublock() == target_from) { 6185 branch->change_ublock(target_to); 6186 } 6187 } 6188 } 6189 } 6190 6191 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) { 6192 int old_pos = 0; 6193 int new_pos = 0; 6194 int num_blocks = code->length(); 6195 6196 while (old_pos < num_blocks) { 6197 BlockBegin* block = code->at(old_pos); 6198 6199 if (can_delete_block(block)) { 6200 BlockBegin* new_target = block->sux_at(0); 6201 6202 // propagate backward branch target flag for correct code alignment 6203 if (block->is_set(BlockBegin::backward_branch_target_flag)) { 6204 new_target->set(BlockBegin::backward_branch_target_flag); 6205 } 6206 6207 // collect a list with all predecessors that contains each predecessor only once 6208 // the predecessors of cur are changed during the substitution, so a copy of the 6209 // predecessor list is necessary 6210 int j; 6211 _original_preds.clear(); 6212 for (j = block->number_of_preds() - 1; j >= 0; j--) { 6213 BlockBegin* pred = block->pred_at(j); 6214 if (_original_preds.index_of(pred) == -1) { 6215 _original_preds.append(pred); 6216 } 6217 } 6218 6219 for (j = _original_preds.length() - 1; j >= 0; j--) { 6220 BlockBegin* pred = _original_preds.at(j); 6221 substitute_branch_target(pred, block, new_target); 6222 pred->substitute_sux(block, new_target); 6223 } 6224 } else { 6225 // adjust position of this block in the block list if blocks before 6226 // have been deleted 6227 if (new_pos != old_pos) { 6228 code->at_put(new_pos, code->at(old_pos)); 6229 } 6230 new_pos++; 6231 } 6232 old_pos++; 6233 } 6234 code->truncate(new_pos); 6235 6236 DEBUG_ONLY(verify(code)); 6237 } 6238 6239 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { 6240 // skip the last block because there a branch is always necessary 6241 for (int i = code->length() - 2; i >= 0; i--) { 6242 BlockBegin* block = code->at(i); 6243 LIR_OpList* instructions = block->lir()->instructions_list(); 6244 6245 LIR_Op* last_op = instructions->last(); 6246 if (last_op->code() == lir_branch) { 6247 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6248 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op; 6249 6250 assert(last_branch->block() != NULL, "last branch must always have a block as target"); 6251 assert(last_branch->label() == last_branch->block()->label(), "must be equal"); 6252 6253 if (last_branch->info() == NULL) { 6254 if (last_branch->block() == code->at(i + 1)) { 6255 6256 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id())); 6257 6258 // delete last branch instruction 6259 instructions->truncate(instructions->length() - 1); 6260 6261 } else { 6262 LIR_Op* prev_op = instructions->at(instructions->length() - 2); 6263 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) { 6264 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6265 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op; 6266 6267 if (prev_branch->stub() == NULL) { 6268 6269 LIR_Op2* prev_cmp = NULL; 6270 // There might be a cmove inserted for profiling which depends on the same 6271 // compare. If we change the condition of the respective compare, we have 6272 // to take care of this cmove as well. 6273 LIR_Op2* prev_cmove = NULL; 6274 6275 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) { 6276 prev_op = instructions->at(j); 6277 // check for the cmove 6278 if (prev_op->code() == lir_cmove) { 6279 assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2"); 6280 prev_cmove = (LIR_Op2*)prev_op; 6281 assert(prev_branch->cond() == prev_cmove->condition(), "should be the same"); 6282 } 6283 if (prev_op->code() == lir_cmp) { 6284 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2"); 6285 prev_cmp = (LIR_Op2*)prev_op; 6286 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same"); 6287 } 6288 } 6289 assert(prev_cmp != NULL, "should have found comp instruction for branch"); 6290 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { 6291 6292 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); 6293 6294 // eliminate a conditional branch to the immediate successor 6295 prev_branch->change_block(last_branch->block()); 6296 prev_branch->negate_cond(); 6297 prev_cmp->set_condition(prev_branch->cond()); 6298 instructions->truncate(instructions->length() - 1); 6299 // if we do change the condition, we have to change the cmove as well 6300 if (prev_cmove != NULL) { 6301 prev_cmove->set_condition(prev_branch->cond()); 6302 LIR_Opr t = prev_cmove->in_opr1(); 6303 prev_cmove->set_in_opr1(prev_cmove->in_opr2()); 6304 prev_cmove->set_in_opr2(t); 6305 } 6306 } 6307 } 6308 } 6309 } 6310 } 6311 } 6312 } 6313 6314 DEBUG_ONLY(verify(code)); 6315 } 6316 6317 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) { 6318 #ifdef ASSERT 6319 BitMap return_converted(BlockBegin::number_of_blocks()); 6320 return_converted.clear(); 6321 #endif 6322 6323 for (int i = code->length() - 1; i >= 0; i--) { 6324 BlockBegin* block = code->at(i); 6325 LIR_OpList* cur_instructions = block->lir()->instructions_list(); 6326 LIR_Op* cur_last_op = cur_instructions->last(); 6327 6328 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6329 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) { 6330 // the block contains only a label and a return 6331 // if a predecessor ends with an unconditional jump to this block, then the jump 6332 // can be replaced with a return instruction 6333 // 6334 // Note: the original block with only a return statement cannot be deleted completely 6335 // because the predecessors might have other (conditional) jumps to this block 6336 // -> this may lead to unnecesary return instructions in the final code 6337 6338 assert(cur_last_op->info() == NULL, "return instructions do not have debug information"); 6339 assert(block->number_of_sux() == 0 || 6340 (return_converted.at(block->block_id()) && block->number_of_sux() == 1), 6341 "blocks that end with return must not have successors"); 6342 6343 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1"); 6344 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr(); 6345 6346 for (int j = block->number_of_preds() - 1; j >= 0; j--) { 6347 BlockBegin* pred = block->pred_at(j); 6348 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); 6349 LIR_Op* pred_last_op = pred_instructions->last(); 6350 6351 if (pred_last_op->code() == lir_branch) { 6352 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 6353 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op; 6354 6355 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) { 6356 // replace the jump to a return with a direct return 6357 // Note: currently the edge between the blocks is not deleted 6358 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr)); 6359 #ifdef ASSERT 6360 return_converted.set_bit(pred->block_id()); 6361 #endif 6362 } 6363 } 6364 } 6365 } 6366 } 6367 } 6368 6369 6370 #ifdef ASSERT 6371 void ControlFlowOptimizer::verify(BlockList* code) { 6372 for (int i = 0; i < code->length(); i++) { 6373 BlockBegin* block = code->at(i); 6374 LIR_OpList* instructions = block->lir()->instructions_list(); 6375 6376 int j; 6377 for (j = 0; j < instructions->length(); j++) { 6378 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch(); 6379 6380 if (op_branch != NULL) { 6381 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid"); 6382 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid"); 6383 } 6384 } 6385 6386 for (j = 0; j < block->number_of_sux() - 1; j++) { 6387 BlockBegin* sux = block->sux_at(j); 6388 assert(code->index_of(sux) != -1, "successor not valid"); 6389 } 6390 6391 for (j = 0; j < block->number_of_preds() - 1; j++) { 6392 BlockBegin* pred = block->pred_at(j); 6393 assert(code->index_of(pred) != -1, "successor not valid"); 6394 } 6395 } 6396 } 6397 #endif 6398 6399 6400 #ifndef PRODUCT 6401 6402 // Implementation of LinearStatistic 6403 6404 const char* LinearScanStatistic::counter_name(int counter_idx) { 6405 switch (counter_idx) { 6406 case counter_method: return "compiled methods"; 6407 case counter_fpu_method: return "methods using fpu"; 6408 case counter_loop_method: return "methods with loops"; 6409 case counter_exception_method:return "methods with xhandler"; 6410 6411 case counter_loop: return "loops"; 6412 case counter_block: return "blocks"; 6413 case counter_loop_block: return "blocks inside loop"; 6414 case counter_exception_block: return "exception handler entries"; 6415 case counter_interval: return "intervals"; 6416 case counter_fixed_interval: return "fixed intervals"; 6417 case counter_range: return "ranges"; 6418 case counter_fixed_range: return "fixed ranges"; 6419 case counter_use_pos: return "use positions"; 6420 case counter_fixed_use_pos: return "fixed use positions"; 6421 case counter_spill_slots: return "spill slots"; 6422 6423 // counter for classes of lir instructions 6424 case counter_instruction: return "total instructions"; 6425 case counter_label: return "labels"; 6426 case counter_entry: return "method entries"; 6427 case counter_return: return "method returns"; 6428 case counter_call: return "method calls"; 6429 case counter_move: return "moves"; 6430 case counter_cmp: return "compare"; 6431 case counter_cond_branch: return "conditional branches"; 6432 case counter_uncond_branch: return "unconditional branches"; 6433 case counter_stub_branch: return "branches to stub"; 6434 case counter_alu: return "artithmetic + logic"; 6435 case counter_alloc: return "allocations"; 6436 case counter_sync: return "synchronisation"; 6437 case counter_throw: return "throw"; 6438 case counter_unwind: return "unwind"; 6439 case counter_typecheck: return "type+null-checks"; 6440 case counter_fpu_stack: return "fpu-stack"; 6441 case counter_misc_inst: return "other instructions"; 6442 case counter_other_inst: return "misc. instructions"; 6443 6444 // counter for different types of moves 6445 case counter_move_total: return "total moves"; 6446 case counter_move_reg_reg: return "register->register"; 6447 case counter_move_reg_stack: return "register->stack"; 6448 case counter_move_stack_reg: return "stack->register"; 6449 case counter_move_stack_stack:return "stack->stack"; 6450 case counter_move_reg_mem: return "register->memory"; 6451 case counter_move_mem_reg: return "memory->register"; 6452 case counter_move_const_any: return "constant->any"; 6453 6454 case blank_line_1: return ""; 6455 case blank_line_2: return ""; 6456 6457 default: ShouldNotReachHere(); return ""; 6458 } 6459 } 6460 6461 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) { 6462 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) { 6463 return counter_method; 6464 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) { 6465 return counter_block; 6466 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) { 6467 return counter_instruction; 6468 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) { 6469 return counter_move_total; 6470 } 6471 return invalid_counter; 6472 } 6473 6474 LinearScanStatistic::LinearScanStatistic() { 6475 for (int i = 0; i < number_of_counters; i++) { 6476 _counters_sum[i] = 0; 6477 _counters_max[i] = -1; 6478 } 6479 6480 } 6481 6482 // add the method-local numbers to the total sum 6483 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) { 6484 for (int i = 0; i < number_of_counters; i++) { 6485 _counters_sum[i] += method_statistic._counters_sum[i]; 6486 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]); 6487 } 6488 } 6489 6490 void LinearScanStatistic::print(const char* title) { 6491 if (CountLinearScan || TraceLinearScanLevel > 0) { 6492 tty->cr(); 6493 tty->print_cr("***** LinearScan statistic - %s *****", title); 6494 6495 for (int i = 0; i < number_of_counters; i++) { 6496 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) { 6497 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]); 6498 6499 if (base_counter(i) != invalid_counter) { 6500 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]); 6501 } else { 6502 tty->print(" "); 6503 } 6504 6505 if (_counters_max[i] >= 0) { 6506 tty->print("%8d", _counters_max[i]); 6507 } 6508 } 6509 tty->cr(); 6510 } 6511 } 6512 } 6513 6514 void LinearScanStatistic::collect(LinearScan* allocator) { 6515 inc_counter(counter_method); 6516 if (allocator->has_fpu_registers()) { 6517 inc_counter(counter_fpu_method); 6518 } 6519 if (allocator->num_loops() > 0) { 6520 inc_counter(counter_loop_method); 6521 } 6522 inc_counter(counter_loop, allocator->num_loops()); 6523 inc_counter(counter_spill_slots, allocator->max_spills()); 6524 6525 int i; 6526 for (i = 0; i < allocator->interval_count(); i++) { 6527 Interval* cur = allocator->interval_at(i); 6528 6529 if (cur != NULL) { 6530 inc_counter(counter_interval); 6531 inc_counter(counter_use_pos, cur->num_use_positions()); 6532 if (LinearScan::is_precolored_interval(cur)) { 6533 inc_counter(counter_fixed_interval); 6534 inc_counter(counter_fixed_use_pos, cur->num_use_positions()); 6535 } 6536 6537 Range* range = cur->first(); 6538 while (range != Range::end()) { 6539 inc_counter(counter_range); 6540 if (LinearScan::is_precolored_interval(cur)) { 6541 inc_counter(counter_fixed_range); 6542 } 6543 range = range->next(); 6544 } 6545 } 6546 } 6547 6548 bool has_xhandlers = false; 6549 // Note: only count blocks that are in code-emit order 6550 for (i = 0; i < allocator->ir()->code()->length(); i++) { 6551 BlockBegin* cur = allocator->ir()->code()->at(i); 6552 6553 inc_counter(counter_block); 6554 if (cur->loop_depth() > 0) { 6555 inc_counter(counter_loop_block); 6556 } 6557 if (cur->is_set(BlockBegin::exception_entry_flag)) { 6558 inc_counter(counter_exception_block); 6559 has_xhandlers = true; 6560 } 6561 6562 LIR_OpList* instructions = cur->lir()->instructions_list(); 6563 for (int j = 0; j < instructions->length(); j++) { 6564 LIR_Op* op = instructions->at(j); 6565 6566 inc_counter(counter_instruction); 6567 6568 switch (op->code()) { 6569 case lir_label: inc_counter(counter_label); break; 6570 case lir_std_entry: 6571 case lir_osr_entry: inc_counter(counter_entry); break; 6572 case lir_return: inc_counter(counter_return); break; 6573 6574 case lir_rtcall: 6575 case lir_static_call: 6576 case lir_optvirtual_call: 6577 case lir_virtual_call: inc_counter(counter_call); break; 6578 6579 case lir_move: { 6580 inc_counter(counter_move); 6581 inc_counter(counter_move_total); 6582 6583 LIR_Opr in = op->as_Op1()->in_opr(); 6584 LIR_Opr res = op->as_Op1()->result_opr(); 6585 if (in->is_register()) { 6586 if (res->is_register()) { 6587 inc_counter(counter_move_reg_reg); 6588 } else if (res->is_stack()) { 6589 inc_counter(counter_move_reg_stack); 6590 } else if (res->is_address()) { 6591 inc_counter(counter_move_reg_mem); 6592 } else { 6593 ShouldNotReachHere(); 6594 } 6595 } else if (in->is_stack()) { 6596 if (res->is_register()) { 6597 inc_counter(counter_move_stack_reg); 6598 } else { 6599 inc_counter(counter_move_stack_stack); 6600 } 6601 } else if (in->is_address()) { 6602 assert(res->is_register(), "must be"); 6603 inc_counter(counter_move_mem_reg); 6604 } else if (in->is_constant()) { 6605 inc_counter(counter_move_const_any); 6606 } else { 6607 ShouldNotReachHere(); 6608 } 6609 break; 6610 } 6611 6612 case lir_cmp: inc_counter(counter_cmp); break; 6613 6614 case lir_branch: 6615 case lir_cond_float_branch: { 6616 LIR_OpBranch* branch = op->as_OpBranch(); 6617 if (branch->block() == NULL) { 6618 inc_counter(counter_stub_branch); 6619 } else if (branch->cond() == lir_cond_always) { 6620 inc_counter(counter_uncond_branch); 6621 } else { 6622 inc_counter(counter_cond_branch); 6623 } 6624 break; 6625 } 6626 6627 case lir_neg: 6628 case lir_add: 6629 case lir_sub: 6630 case lir_mul: 6631 case lir_mul_strictfp: 6632 case lir_div: 6633 case lir_div_strictfp: 6634 case lir_rem: 6635 case lir_sqrt: 6636 case lir_abs: 6637 case lir_log10: 6638 case lir_logic_and: 6639 case lir_logic_or: 6640 case lir_logic_xor: 6641 case lir_shl: 6642 case lir_shr: 6643 case lir_ushr: inc_counter(counter_alu); break; 6644 6645 case lir_alloc_object: 6646 case lir_alloc_array: inc_counter(counter_alloc); break; 6647 6648 case lir_monaddr: 6649 case lir_lock: 6650 case lir_unlock: inc_counter(counter_sync); break; 6651 6652 case lir_throw: inc_counter(counter_throw); break; 6653 6654 case lir_unwind: inc_counter(counter_unwind); break; 6655 6656 case lir_null_check: 6657 case lir_leal: 6658 case lir_instanceof: 6659 case lir_checkcast: 6660 case lir_store_check: inc_counter(counter_typecheck); break; 6661 6662 case lir_fpop_raw: 6663 case lir_fxch: 6664 case lir_fld: inc_counter(counter_fpu_stack); break; 6665 6666 case lir_nop: 6667 case lir_push: 6668 case lir_pop: 6669 case lir_convert: 6670 case lir_roundfp: 6671 case lir_cmove: inc_counter(counter_misc_inst); break; 6672 6673 default: inc_counter(counter_other_inst); break; 6674 } 6675 } 6676 } 6677 6678 if (has_xhandlers) { 6679 inc_counter(counter_exception_method); 6680 } 6681 } 6682 6683 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) { 6684 if (CountLinearScan || TraceLinearScanLevel > 0) { 6685 6686 LinearScanStatistic local_statistic = LinearScanStatistic(); 6687 6688 local_statistic.collect(allocator); 6689 global_statistic.sum_up(local_statistic); 6690 6691 if (TraceLinearScanLevel > 2) { 6692 local_statistic.print("current local statistic"); 6693 } 6694 } 6695 } 6696 6697 6698 // Implementation of LinearTimers 6699 6700 LinearScanTimers::LinearScanTimers() { 6701 for (int i = 0; i < number_of_timers; i++) { 6702 timer(i)->reset(); 6703 } 6704 } 6705 6706 const char* LinearScanTimers::timer_name(int idx) { 6707 switch (idx) { 6708 case timer_do_nothing: return "Nothing (Time Check)"; 6709 case timer_number_instructions: return "Number Instructions"; 6710 case timer_compute_local_live_sets: return "Local Live Sets"; 6711 case timer_compute_global_live_sets: return "Global Live Sets"; 6712 case timer_build_intervals: return "Build Intervals"; 6713 case timer_sort_intervals_before: return "Sort Intervals Before"; 6714 case timer_allocate_registers: return "Allocate Registers"; 6715 case timer_resolve_data_flow: return "Resolve Data Flow"; 6716 case timer_sort_intervals_after: return "Sort Intervals After"; 6717 case timer_eliminate_spill_moves: return "Spill optimization"; 6718 case timer_assign_reg_num: return "Assign Reg Num"; 6719 case timer_allocate_fpu_stack: return "Allocate FPU Stack"; 6720 case timer_optimize_lir: return "Optimize LIR"; 6721 default: ShouldNotReachHere(); return ""; 6722 } 6723 } 6724 6725 void LinearScanTimers::begin_method() { 6726 if (TimeEachLinearScan) { 6727 // reset all timers to measure only current method 6728 for (int i = 0; i < number_of_timers; i++) { 6729 timer(i)->reset(); 6730 } 6731 } 6732 } 6733 6734 void LinearScanTimers::end_method(LinearScan* allocator) { 6735 if (TimeEachLinearScan) { 6736 6737 double c = timer(timer_do_nothing)->seconds(); 6738 double total = 0; 6739 for (int i = 1; i < number_of_timers; i++) { 6740 total += timer(i)->seconds() - c; 6741 } 6742 6743 if (total >= 0.0005) { 6744 // print all information in one line for automatic processing 6745 tty->print("@"); allocator->compilation()->method()->print_name(); 6746 6747 tty->print("@ %d ", allocator->compilation()->method()->code_size()); 6748 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2); 6749 tty->print("@ %d ", allocator->block_count()); 6750 tty->print("@ %d ", allocator->num_virtual_regs()); 6751 tty->print("@ %d ", allocator->interval_count()); 6752 tty->print("@ %d ", allocator->_num_calls); 6753 tty->print("@ %d ", allocator->num_loops()); 6754 6755 tty->print("@ %6.6f ", total); 6756 for (int i = 1; i < number_of_timers; i++) { 6757 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100); 6758 } 6759 tty->cr(); 6760 } 6761 } 6762 } 6763 6764 void LinearScanTimers::print(double total_time) { 6765 if (TimeLinearScan) { 6766 // correction value: sum of dummy-timer that only measures the time that 6767 // is necesary to start and stop itself 6768 double c = timer(timer_do_nothing)->seconds(); 6769 6770 for (int i = 0; i < number_of_timers; i++) { 6771 double t = timer(i)->seconds(); 6772 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100); 6773 } 6774 } 6775 } 6776 6777 #endif // #ifndef PRODUCT