1 /* 2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_InstructionPrinter.hpp" 27 #include "c1/c1_LIR.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_ValueStack.hpp" 30 #include "ci/ciInstance.hpp" 31 #include "runtime/sharedRuntime.hpp" 32 33 Register LIR_OprDesc::as_register() const { 34 return FrameMap::cpu_rnr2reg(cpu_regnr()); 35 } 36 37 Register LIR_OprDesc::as_register_lo() const { 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 39 } 40 41 Register LIR_OprDesc::as_register_hi() const { 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 43 } 44 45 #if defined(X86) 46 47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 48 return FrameMap::nr2xmmreg(xmm_regnr()); 49 } 50 51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 53 return FrameMap::nr2xmmreg(xmm_regnrLo()); 54 } 55 56 #endif // X86 57 58 #if defined(SPARC) || defined(PPC) 59 60 FloatRegister LIR_OprDesc::as_float_reg() const { 61 return FrameMap::nr2floatreg(fpu_regnr()); 62 } 63 64 FloatRegister LIR_OprDesc::as_double_reg() const { 65 return FrameMap::nr2floatreg(fpu_regnrHi()); 66 } 67 68 #endif 69 70 #ifdef ARM 71 72 FloatRegister LIR_OprDesc::as_float_reg() const { 73 return as_FloatRegister(fpu_regnr()); 74 } 75 76 FloatRegister LIR_OprDesc::as_double_reg() const { 77 return as_FloatRegister(fpu_regnrLo()); 78 } 79 80 #endif 81 82 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 84 85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { 86 ValueTag tag = type->tag(); 87 switch (tag) { 88 case metaDataTag : { 89 ClassConstant* c = type->as_ClassConstant(); 90 if (c != NULL && !c->value()->is_loaded()) { 91 return LIR_OprFact::metadataConst(NULL); 92 } else if (c != NULL) { 93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); 94 } else { 95 MethodConstant* m = type->as_MethodConstant(); 96 assert (m != NULL, "not a class or a method?"); 97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); 98 } 99 } 100 case objectTag : { 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 102 } 103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 109 } 110 } 111 112 113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 114 switch (type->tag()) { 115 case objectTag: return LIR_OprFact::oopConst(NULL); 116 case addressTag:return LIR_OprFact::addressConst(0); 117 case intTag: return LIR_OprFact::intConst(0); 118 case floatTag: return LIR_OprFact::floatConst(0.0); 119 case longTag: return LIR_OprFact::longConst(0); 120 case doubleTag: return LIR_OprFact::doubleConst(0.0); 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 122 } 123 return illegalOpr; 124 } 125 126 127 128 //--------------------------------------------------- 129 130 131 LIR_Address::Scale LIR_Address::scale(BasicType type) { 132 int elem_size = type2aelembytes(type); 133 switch (elem_size) { 134 case 1: return LIR_Address::times_1; 135 case 2: return LIR_Address::times_2; 136 case 4: return LIR_Address::times_4; 137 case 8: return LIR_Address::times_8; 138 } 139 ShouldNotReachHere(); 140 return LIR_Address::times_1; 141 } 142 143 144 #ifndef PRODUCT 145 void LIR_Address::verify() const { 146 #if defined(SPARC) || defined(PPC) 147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 149 #endif 150 #ifdef ARM 151 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 152 // Note: offsets higher than 4096 must not be rejected here. They can 153 // be handled by the back-end or will be rejected if not. 154 #endif 155 #ifdef _LP64 156 assert(base()->is_cpu_register(), "wrong base operand"); 157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 159 "wrong type for addresses"); 160 #else 161 assert(base()->is_single_cpu(), "wrong base operand"); 162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 164 "wrong type for addresses"); 165 #endif 166 } 167 #endif 168 169 170 //--------------------------------------------------- 171 172 char LIR_OprDesc::type_char(BasicType t) { 173 switch (t) { 174 case T_ARRAY: 175 t = T_OBJECT; 176 case T_BOOLEAN: 177 case T_CHAR: 178 case T_FLOAT: 179 case T_DOUBLE: 180 case T_BYTE: 181 case T_SHORT: 182 case T_INT: 183 case T_LONG: 184 case T_OBJECT: 185 case T_ADDRESS: 186 case T_VOID: 187 return ::type2char(t); 188 case T_METADATA: 189 return 'M'; 190 case T_ILLEGAL: 191 return '?'; 192 193 default: 194 ShouldNotReachHere(); 195 return '?'; 196 } 197 } 198 199 #ifndef PRODUCT 200 void LIR_OprDesc::validate_type() const { 201 202 #ifdef ASSERT 203 if (!is_pointer() && !is_illegal()) { 204 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 205 switch (as_BasicType(type_field())) { 206 case T_LONG: 207 assert((kindfield == cpu_register || kindfield == stack_value) && 208 size_field() == double_size, "must match"); 209 break; 210 case T_FLOAT: 211 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 212 assert((kindfield == fpu_register || kindfield == stack_value 213 ARM_ONLY(|| kindfield == cpu_register) 214 PPC_ONLY(|| kindfield == cpu_register) ) && 215 size_field() == single_size, "must match"); 216 break; 217 case T_DOUBLE: 218 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 219 assert((kindfield == fpu_register || kindfield == stack_value 220 ARM_ONLY(|| kindfield == cpu_register) 221 PPC_ONLY(|| kindfield == cpu_register) ) && 222 size_field() == double_size, "must match"); 223 break; 224 case T_BOOLEAN: 225 case T_CHAR: 226 case T_BYTE: 227 case T_SHORT: 228 case T_INT: 229 case T_ADDRESS: 230 case T_OBJECT: 231 case T_METADATA: 232 case T_ARRAY: 233 assert((kindfield == cpu_register || kindfield == stack_value) && 234 size_field() == single_size, "must match"); 235 break; 236 237 case T_ILLEGAL: 238 // XXX TKR also means unknown right now 239 // assert(is_illegal(), "must match"); 240 break; 241 242 default: 243 ShouldNotReachHere(); 244 } 245 } 246 #endif 247 248 } 249 #endif // PRODUCT 250 251 252 bool LIR_OprDesc::is_oop() const { 253 if (is_pointer()) { 254 return pointer()->is_oop_pointer(); 255 } else { 256 OprType t= type_field(); 257 assert(t != unknown_type, "not set"); 258 return t == object_type; 259 } 260 } 261 262 263 264 void LIR_Op2::verify() const { 265 #ifdef ASSERT 266 switch (code()) { 267 case lir_cmove: 268 case lir_xchg: 269 break; 270 271 default: 272 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 273 "can't produce oops from arith"); 274 } 275 276 if (TwoOperandLIRForm) { 277 switch (code()) { 278 case lir_add: 279 case lir_sub: 280 case lir_mul: 281 case lir_mul_strictfp: 282 case lir_div: 283 case lir_div_strictfp: 284 case lir_rem: 285 case lir_logic_and: 286 case lir_logic_or: 287 case lir_logic_xor: 288 case lir_shl: 289 case lir_shr: 290 assert(in_opr1() == result_opr(), "opr1 and result must match"); 291 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 292 break; 293 294 // special handling for lir_ushr because of write barriers 295 case lir_ushr: 296 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 297 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 298 break; 299 300 } 301 } 302 #endif 303 } 304 305 306 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 307 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 308 , _cond(cond) 309 , _type(type) 310 , _label(block->label()) 311 , _block(block) 312 , _ublock(NULL) 313 , _stub(NULL) { 314 } 315 316 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 317 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 318 , _cond(cond) 319 , _type(type) 320 , _label(stub->entry()) 321 , _block(NULL) 322 , _ublock(NULL) 323 , _stub(stub) { 324 } 325 326 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 327 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 328 , _cond(cond) 329 , _type(type) 330 , _label(block->label()) 331 , _block(block) 332 , _ublock(ublock) 333 , _stub(NULL) 334 { 335 } 336 337 void LIR_OpBranch::change_block(BlockBegin* b) { 338 assert(_block != NULL, "must have old block"); 339 assert(_block->label() == label(), "must be equal"); 340 341 _block = b; 342 _label = b->label(); 343 } 344 345 void LIR_OpBranch::change_ublock(BlockBegin* b) { 346 assert(_ublock != NULL, "must have old block"); 347 _ublock = b; 348 } 349 350 void LIR_OpBranch::negate_cond() { 351 switch (_cond) { 352 case lir_cond_equal: _cond = lir_cond_notEqual; break; 353 case lir_cond_notEqual: _cond = lir_cond_equal; break; 354 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 355 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 356 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 357 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 358 default: ShouldNotReachHere(); 359 } 360 } 361 362 363 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 364 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 365 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 366 CodeStub* stub) 367 368 : LIR_Op(code, result, NULL) 369 , _object(object) 370 , _array(LIR_OprFact::illegalOpr) 371 , _klass(klass) 372 , _tmp1(tmp1) 373 , _tmp2(tmp2) 374 , _tmp3(tmp3) 375 , _fast_check(fast_check) 376 , _stub(stub) 377 , _info_for_patch(info_for_patch) 378 , _info_for_exception(info_for_exception) 379 , _profiled_method(NULL) 380 , _profiled_bci(-1) 381 , _should_profile(false) 382 { 383 if (code == lir_checkcast) { 384 assert(info_for_exception != NULL, "checkcast throws exceptions"); 385 } else if (code == lir_instanceof) { 386 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 387 } else { 388 ShouldNotReachHere(); 389 } 390 } 391 392 393 394 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) 395 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 396 , _object(object) 397 , _array(array) 398 , _klass(NULL) 399 , _tmp1(tmp1) 400 , _tmp2(tmp2) 401 , _tmp3(tmp3) 402 , _fast_check(false) 403 , _stub(NULL) 404 , _info_for_patch(NULL) 405 , _info_for_exception(info_for_exception) 406 , _profiled_method(NULL) 407 , _profiled_bci(-1) 408 , _should_profile(false) 409 { 410 if (code == lir_store_check) { 411 _stub = new ArrayStoreExceptionStub(object, info_for_exception); 412 assert(info_for_exception != NULL, "store_check throws exceptions"); 413 } else { 414 ShouldNotReachHere(); 415 } 416 } 417 418 419 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 420 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 421 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 422 , _tmp(tmp) 423 , _src(src) 424 , _src_pos(src_pos) 425 , _dst(dst) 426 , _dst_pos(dst_pos) 427 , _flags(flags) 428 , _expected_type(expected_type) 429 , _length(length) { 430 _stub = new ArrayCopyStub(this); 431 } 432 433 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) 434 : LIR_Op(lir_updatecrc32, res, NULL) 435 , _crc(crc) 436 , _val(val) { 437 } 438 439 //-------------------verify-------------------------- 440 441 void LIR_Op1::verify() const { 442 switch(code()) { 443 case lir_move: 444 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 445 break; 446 case lir_null_check: 447 assert(in_opr()->is_register(), "must be"); 448 break; 449 case lir_return: 450 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 451 break; 452 } 453 } 454 455 void LIR_OpRTCall::verify() const { 456 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 457 } 458 459 //-------------------visits-------------------------- 460 461 // complete rework of LIR instruction visitor. 462 // The virtual calls for each instruction type is replaced by a big 463 // switch that adds the operands for each instruction 464 465 void LIR_OpVisitState::visit(LIR_Op* op) { 466 // copy information from the LIR_Op 467 reset(); 468 set_op(op); 469 470 switch (op->code()) { 471 472 // LIR_Op0 473 case lir_word_align: // result and info always invalid 474 case lir_backwardbranch_target: // result and info always invalid 475 case lir_build_frame: // result and info always invalid 476 case lir_fpop_raw: // result and info always invalid 477 case lir_24bit_FPU: // result and info always invalid 478 case lir_reset_FPU: // result and info always invalid 479 case lir_breakpoint: // result and info always invalid 480 case lir_membar: // result and info always invalid 481 case lir_membar_acquire: // result and info always invalid 482 case lir_membar_release: // result and info always invalid 483 case lir_membar_loadload: // result and info always invalid 484 case lir_membar_storestore: // result and info always invalid 485 case lir_membar_loadstore: // result and info always invalid 486 case lir_membar_storeload: // result and info always invalid 487 { 488 assert(op->as_Op0() != NULL, "must be"); 489 assert(op->_info == NULL, "info not used by this instruction"); 490 assert(op->_result->is_illegal(), "not used"); 491 break; 492 } 493 494 case lir_nop: // may have info, result always invalid 495 case lir_std_entry: // may have result, info always invalid 496 case lir_osr_entry: // may have result, info always invalid 497 case lir_get_thread: // may have result, info always invalid 498 { 499 assert(op->as_Op0() != NULL, "must be"); 500 if (op->_info != NULL) do_info(op->_info); 501 if (op->_result->is_valid()) do_output(op->_result); 502 break; 503 } 504 505 506 // LIR_OpLabel 507 case lir_label: // result and info always invalid 508 { 509 assert(op->as_OpLabel() != NULL, "must be"); 510 assert(op->_info == NULL, "info not used by this instruction"); 511 assert(op->_result->is_illegal(), "not used"); 512 break; 513 } 514 515 516 // LIR_Op1 517 case lir_fxch: // input always valid, result and info always invalid 518 case lir_fld: // input always valid, result and info always invalid 519 case lir_ffree: // input always valid, result and info always invalid 520 case lir_push: // input always valid, result and info always invalid 521 case lir_pop: // input always valid, result and info always invalid 522 case lir_return: // input always valid, result and info always invalid 523 case lir_leal: // input and result always valid, info always invalid 524 case lir_neg: // input and result always valid, info always invalid 525 case lir_monaddr: // input and result always valid, info always invalid 526 case lir_null_check: // input and info always valid, result always invalid 527 case lir_move: // input and result always valid, may have info 528 case lir_pack64: // input and result always valid 529 case lir_unpack64: // input and result always valid 530 { 531 assert(op->as_Op1() != NULL, "must be"); 532 LIR_Op1* op1 = (LIR_Op1*)op; 533 534 if (op1->_info) do_info(op1->_info); 535 if (op1->_opr->is_valid()) do_input(op1->_opr); 536 if (op1->_result->is_valid()) do_output(op1->_result); 537 538 break; 539 } 540 541 case lir_safepoint: 542 { 543 assert(op->as_Op1() != NULL, "must be"); 544 LIR_Op1* op1 = (LIR_Op1*)op; 545 546 assert(op1->_info != NULL, ""); do_info(op1->_info); 547 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 548 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 549 550 break; 551 } 552 553 // LIR_OpConvert; 554 case lir_convert: // input and result always valid, info always invalid 555 { 556 assert(op->as_OpConvert() != NULL, "must be"); 557 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 558 559 assert(opConvert->_info == NULL, "must be"); 560 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 561 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 562 #ifdef PPC 563 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); 564 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); 565 #endif 566 do_stub(opConvert->_stub); 567 568 break; 569 } 570 571 // LIR_OpBranch; 572 case lir_branch: // may have info, input and result register always invalid 573 case lir_cond_float_branch: // may have info, input and result register always invalid 574 { 575 assert(op->as_OpBranch() != NULL, "must be"); 576 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 577 578 if (opBranch->_info != NULL) do_info(opBranch->_info); 579 assert(opBranch->_result->is_illegal(), "not used"); 580 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 581 582 break; 583 } 584 585 586 // LIR_OpAllocObj 587 case lir_alloc_object: 588 { 589 assert(op->as_OpAllocObj() != NULL, "must be"); 590 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 591 592 if (opAllocObj->_info) do_info(opAllocObj->_info); 593 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); 594 do_temp(opAllocObj->_opr); 595 } 596 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 597 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 598 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 599 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 600 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 601 do_stub(opAllocObj->_stub); 602 break; 603 } 604 605 606 // LIR_OpRoundFP; 607 case lir_roundfp: { 608 assert(op->as_OpRoundFP() != NULL, "must be"); 609 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 610 611 assert(op->_info == NULL, "info not used by this instruction"); 612 assert(opRoundFP->_tmp->is_illegal(), "not used"); 613 do_input(opRoundFP->_opr); 614 do_output(opRoundFP->_result); 615 616 break; 617 } 618 619 620 // LIR_Op2 621 case lir_cmp: 622 case lir_cmp_l2i: 623 case lir_ucmp_fd2i: 624 case lir_cmp_fd2i: 625 case lir_add: 626 case lir_sub: 627 case lir_mul: 628 case lir_div: 629 case lir_rem: 630 case lir_sqrt: 631 case lir_abs: 632 case lir_logic_and: 633 case lir_logic_or: 634 case lir_logic_xor: 635 case lir_shl: 636 case lir_shr: 637 case lir_ushr: 638 case lir_xadd: 639 case lir_xchg: 640 case lir_assert: 641 { 642 assert(op->as_Op2() != NULL, "must be"); 643 LIR_Op2* op2 = (LIR_Op2*)op; 644 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 645 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 646 647 if (op2->_info) do_info(op2->_info); 648 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 649 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 650 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 651 if (op2->_result->is_valid()) do_output(op2->_result); 652 if (op->code() == lir_xchg || op->code() == lir_xadd) { 653 // on ARM and PPC, return value is loaded first so could 654 // destroy inputs. On other platforms that implement those 655 // (x86, sparc), the extra constrainsts are harmless. 656 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 657 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 658 } 659 660 break; 661 } 662 663 // special handling for cmove: right input operand must not be equal 664 // to the result operand, otherwise the backend fails 665 case lir_cmove: 666 { 667 assert(op->as_Op2() != NULL, "must be"); 668 LIR_Op2* op2 = (LIR_Op2*)op; 669 670 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && 671 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 672 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 673 674 do_input(op2->_opr1); 675 do_input(op2->_opr2); 676 do_temp(op2->_opr2); 677 do_output(op2->_result); 678 679 break; 680 } 681 682 // vspecial handling for strict operations: register input operands 683 // as temp to guarantee that they do not overlap with other 684 // registers 685 case lir_mul_strictfp: 686 case lir_div_strictfp: 687 { 688 assert(op->as_Op2() != NULL, "must be"); 689 LIR_Op2* op2 = (LIR_Op2*)op; 690 691 assert(op2->_info == NULL, "not used"); 692 assert(op2->_opr1->is_valid(), "used"); 693 assert(op2->_opr2->is_valid(), "used"); 694 assert(op2->_result->is_valid(), "used"); 695 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 696 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 697 698 do_input(op2->_opr1); do_temp(op2->_opr1); 699 do_input(op2->_opr2); do_temp(op2->_opr2); 700 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 701 do_output(op2->_result); 702 703 break; 704 } 705 706 case lir_throw: { 707 assert(op->as_Op2() != NULL, "must be"); 708 LIR_Op2* op2 = (LIR_Op2*)op; 709 710 if (op2->_info) do_info(op2->_info); 711 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 712 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 713 assert(op2->_result->is_illegal(), "no result"); 714 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 715 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 716 717 break; 718 } 719 720 case lir_unwind: { 721 assert(op->as_Op1() != NULL, "must be"); 722 LIR_Op1* op1 = (LIR_Op1*)op; 723 724 assert(op1->_info == NULL, "no info"); 725 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 726 assert(op1->_result->is_illegal(), "no result"); 727 728 break; 729 } 730 731 732 case lir_tan: 733 case lir_sin: 734 case lir_cos: 735 case lir_log: 736 case lir_log10: 737 case lir_exp: { 738 assert(op->as_Op2() != NULL, "must be"); 739 LIR_Op2* op2 = (LIR_Op2*)op; 740 741 // On x86 tan/sin/cos need two temporary fpu stack slots and 742 // log/log10 need one so handle opr2 and tmp as temp inputs. 743 // Register input operand as temp to guarantee that it doesn't 744 // overlap with the input. 745 assert(op2->_info == NULL, "not used"); 746 assert(op2->_tmp5->is_illegal(), "not used"); 747 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); 748 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); 749 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); 750 assert(op2->_opr1->is_valid(), "used"); 751 do_input(op2->_opr1); do_temp(op2->_opr1); 752 753 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 754 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 755 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); 756 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); 757 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); 758 if (op2->_result->is_valid()) do_output(op2->_result); 759 760 break; 761 } 762 763 case lir_pow: { 764 assert(op->as_Op2() != NULL, "must be"); 765 LIR_Op2* op2 = (LIR_Op2*)op; 766 767 // On x86 pow needs two temporary fpu stack slots: tmp1 and 768 // tmp2. Register input operands as temps to guarantee that it 769 // doesn't overlap with the temporary slots. 770 assert(op2->_info == NULL, "not used"); 771 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); 772 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() 773 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); 774 assert(op2->_result->is_valid(), "used"); 775 776 do_input(op2->_opr1); do_temp(op2->_opr1); 777 do_input(op2->_opr2); do_temp(op2->_opr2); 778 do_temp(op2->_tmp1); 779 do_temp(op2->_tmp2); 780 do_temp(op2->_tmp3); 781 do_temp(op2->_tmp4); 782 do_temp(op2->_tmp5); 783 do_output(op2->_result); 784 785 break; 786 } 787 788 // LIR_Op3 789 case lir_idiv: 790 case lir_irem: { 791 assert(op->as_Op3() != NULL, "must be"); 792 LIR_Op3* op3= (LIR_Op3*)op; 793 794 if (op3->_info) do_info(op3->_info); 795 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 796 797 // second operand is input and temp, so ensure that second operand 798 // and third operand get not the same register 799 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 800 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 801 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 802 803 if (op3->_result->is_valid()) do_output(op3->_result); 804 805 break; 806 } 807 808 809 // LIR_OpJavaCall 810 case lir_static_call: 811 case lir_optvirtual_call: 812 case lir_icvirtual_call: 813 case lir_virtual_call: 814 case lir_dynamic_call: { 815 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 816 assert(opJavaCall != NULL, "must be"); 817 818 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 819 820 // only visit register parameters 821 int n = opJavaCall->_arguments->length(); 822 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { 823 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 824 do_input(*opJavaCall->_arguments->adr_at(i)); 825 } 826 } 827 828 if (opJavaCall->_info) do_info(opJavaCall->_info); 829 if (opJavaCall->is_method_handle_invoke()) { 830 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); 831 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); 832 } 833 do_call(); 834 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 835 836 break; 837 } 838 839 840 // LIR_OpRTCall 841 case lir_rtcall: { 842 assert(op->as_OpRTCall() != NULL, "must be"); 843 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 844 845 // only visit register parameters 846 int n = opRTCall->_arguments->length(); 847 for (int i = 0; i < n; i++) { 848 if (!opRTCall->_arguments->at(i)->is_pointer()) { 849 do_input(*opRTCall->_arguments->adr_at(i)); 850 } 851 } 852 if (opRTCall->_info) do_info(opRTCall->_info); 853 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 854 do_call(); 855 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 856 857 break; 858 } 859 860 861 // LIR_OpArrayCopy 862 case lir_arraycopy: { 863 assert(op->as_OpArrayCopy() != NULL, "must be"); 864 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 865 866 assert(opArrayCopy->_result->is_illegal(), "unused"); 867 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 868 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 869 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 870 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 871 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 872 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 873 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 874 875 // the implementation of arraycopy always has a call into the runtime 876 do_call(); 877 878 break; 879 } 880 881 882 // LIR_OpUpdateCRC32 883 case lir_updatecrc32: { 884 assert(op->as_OpUpdateCRC32() != NULL, "must be"); 885 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; 886 887 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); 888 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); 889 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); 890 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); 891 892 break; 893 } 894 895 896 // LIR_OpLock 897 case lir_lock: 898 case lir_unlock: { 899 assert(op->as_OpLock() != NULL, "must be"); 900 LIR_OpLock* opLock = (LIR_OpLock*)op; 901 902 if (opLock->_info) do_info(opLock->_info); 903 904 // TODO: check if these operands really have to be temp 905 // (or if input is sufficient). This may have influence on the oop map! 906 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 907 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 908 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 909 910 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 911 assert(opLock->_result->is_illegal(), "unused"); 912 913 do_stub(opLock->_stub); 914 915 break; 916 } 917 918 919 // LIR_OpDelay 920 case lir_delay_slot: { 921 assert(op->as_OpDelay() != NULL, "must be"); 922 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 923 924 visit(opDelay->delay_op()); 925 break; 926 } 927 928 // LIR_OpTypeCheck 929 case lir_instanceof: 930 case lir_checkcast: 931 case lir_store_check: { 932 assert(op->as_OpTypeCheck() != NULL, "must be"); 933 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 934 935 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 936 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 937 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 938 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { 939 do_temp(opTypeCheck->_object); 940 } 941 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 942 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 943 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 944 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 945 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 946 do_stub(opTypeCheck->_stub); 947 break; 948 } 949 950 // LIR_OpCompareAndSwap 951 case lir_cas_long: 952 case lir_cas_obj: 953 case lir_cas_int: { 954 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 955 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 956 957 assert(opCompareAndSwap->_addr->is_valid(), "used"); 958 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); 959 assert(opCompareAndSwap->_new_value->is_valid(), "used"); 960 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 961 do_input(opCompareAndSwap->_addr); 962 do_temp(opCompareAndSwap->_addr); 963 do_input(opCompareAndSwap->_cmp_value); 964 do_temp(opCompareAndSwap->_cmp_value); 965 do_input(opCompareAndSwap->_new_value); 966 do_temp(opCompareAndSwap->_new_value); 967 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 968 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 969 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 970 971 break; 972 } 973 974 975 // LIR_OpAllocArray; 976 case lir_alloc_array: { 977 assert(op->as_OpAllocArray() != NULL, "must be"); 978 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 979 980 if (opAllocArray->_info) do_info(opAllocArray->_info); 981 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 982 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 983 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 984 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 985 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 986 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 987 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 988 do_stub(opAllocArray->_stub); 989 break; 990 } 991 992 // LIR_OpProfileCall: 993 case lir_profile_call: { 994 assert(op->as_OpProfileCall() != NULL, "must be"); 995 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 996 997 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 998 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 999 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 1000 break; 1001 } 1002 1003 // LIR_OpProfileType: 1004 case lir_profile_type: { 1005 assert(op->as_OpProfileType() != NULL, "must be"); 1006 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; 1007 1008 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); 1009 do_input(opProfileType->_obj); 1010 do_temp(opProfileType->_tmp); 1011 break; 1012 } 1013 default: 1014 ShouldNotReachHere(); 1015 } 1016 } 1017 1018 1019 void LIR_OpVisitState::do_stub(CodeStub* stub) { 1020 if (stub != NULL) { 1021 stub->visit(this); 1022 } 1023 } 1024 1025 XHandlers* LIR_OpVisitState::all_xhandler() { 1026 XHandlers* result = NULL; 1027 1028 int i; 1029 for (i = 0; i < info_count(); i++) { 1030 if (info_at(i)->exception_handlers() != NULL) { 1031 result = info_at(i)->exception_handlers(); 1032 break; 1033 } 1034 } 1035 1036 #ifdef ASSERT 1037 for (i = 0; i < info_count(); i++) { 1038 assert(info_at(i)->exception_handlers() == NULL || 1039 info_at(i)->exception_handlers() == result, 1040 "only one xhandler list allowed per LIR-operation"); 1041 } 1042 #endif 1043 1044 if (result != NULL) { 1045 return result; 1046 } else { 1047 return new XHandlers(); 1048 } 1049 1050 return result; 1051 } 1052 1053 1054 #ifdef ASSERT 1055 bool LIR_OpVisitState::no_operands(LIR_Op* op) { 1056 visit(op); 1057 1058 return opr_count(inputMode) == 0 && 1059 opr_count(outputMode) == 0 && 1060 opr_count(tempMode) == 0 && 1061 info_count() == 0 && 1062 !has_call() && 1063 !has_slow_case(); 1064 } 1065 #endif 1066 1067 //--------------------------------------------------- 1068 1069 1070 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 1071 masm->emit_call(this); 1072 } 1073 1074 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 1075 masm->emit_rtcall(this); 1076 } 1077 1078 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 1079 masm->emit_opLabel(this); 1080 } 1081 1082 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 1083 masm->emit_arraycopy(this); 1084 masm->append_code_stub(stub()); 1085 } 1086 1087 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { 1088 masm->emit_updatecrc32(this); 1089 } 1090 1091 void LIR_Op0::emit_code(LIR_Assembler* masm) { 1092 masm->emit_op0(this); 1093 } 1094 1095 void LIR_Op1::emit_code(LIR_Assembler* masm) { 1096 masm->emit_op1(this); 1097 } 1098 1099 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 1100 masm->emit_alloc_obj(this); 1101 masm->append_code_stub(stub()); 1102 } 1103 1104 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 1105 masm->emit_opBranch(this); 1106 if (stub()) { 1107 masm->append_code_stub(stub()); 1108 } 1109 } 1110 1111 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 1112 masm->emit_opConvert(this); 1113 if (stub() != NULL) { 1114 masm->append_code_stub(stub()); 1115 } 1116 } 1117 1118 void LIR_Op2::emit_code(LIR_Assembler* masm) { 1119 masm->emit_op2(this); 1120 } 1121 1122 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 1123 masm->emit_alloc_array(this); 1124 masm->append_code_stub(stub()); 1125 } 1126 1127 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 1128 masm->emit_opTypeCheck(this); 1129 if (stub()) { 1130 masm->append_code_stub(stub()); 1131 } 1132 } 1133 1134 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 1135 masm->emit_compare_and_swap(this); 1136 } 1137 1138 void LIR_Op3::emit_code(LIR_Assembler* masm) { 1139 masm->emit_op3(this); 1140 } 1141 1142 void LIR_OpLock::emit_code(LIR_Assembler* masm) { 1143 masm->emit_lock(this); 1144 if (stub()) { 1145 masm->append_code_stub(stub()); 1146 } 1147 } 1148 1149 #ifdef ASSERT 1150 void LIR_OpAssert::emit_code(LIR_Assembler* masm) { 1151 masm->emit_assert(this); 1152 } 1153 #endif 1154 1155 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1156 masm->emit_delay(this); 1157 } 1158 1159 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1160 masm->emit_profile_call(this); 1161 } 1162 1163 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { 1164 masm->emit_profile_type(this); 1165 } 1166 1167 // LIR_List 1168 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1169 : _operations(8) 1170 , _compilation(compilation) 1171 #ifndef PRODUCT 1172 , _block(block) 1173 #endif 1174 #ifdef ASSERT 1175 , _file(NULL) 1176 , _line(0) 1177 #endif 1178 { } 1179 1180 1181 #ifdef ASSERT 1182 void LIR_List::set_file_and_line(const char * file, int line) { 1183 const char * f = strrchr(file, '/'); 1184 if (f == NULL) f = strrchr(file, '\\'); 1185 if (f == NULL) { 1186 f = file; 1187 } else { 1188 f++; 1189 } 1190 _file = f; 1191 _line = line; 1192 } 1193 #endif 1194 1195 1196 void LIR_List::append(LIR_InsertionBuffer* buffer) { 1197 assert(this == buffer->lir_list(), "wrong lir list"); 1198 const int n = _operations.length(); 1199 1200 if (buffer->number_of_ops() > 0) { 1201 // increase size of instructions list 1202 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1203 // insert ops from buffer into instructions list 1204 int op_index = buffer->number_of_ops() - 1; 1205 int ip_index = buffer->number_of_insertion_points() - 1; 1206 int from_index = n - 1; 1207 int to_index = _operations.length() - 1; 1208 for (; ip_index >= 0; ip_index --) { 1209 int index = buffer->index_at(ip_index); 1210 // make room after insertion point 1211 while (index < from_index) { 1212 _operations.at_put(to_index --, _operations.at(from_index --)); 1213 } 1214 // insert ops from buffer 1215 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1216 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1217 } 1218 } 1219 } 1220 1221 buffer->finish(); 1222 } 1223 1224 1225 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1226 assert(reg->type() == T_OBJECT, "bad reg"); 1227 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1228 } 1229 1230 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { 1231 assert(reg->type() == T_METADATA, "bad reg"); 1232 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); 1233 } 1234 1235 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1236 append(new LIR_Op1( 1237 lir_move, 1238 LIR_OprFact::address(addr), 1239 src, 1240 addr->type(), 1241 patch_code, 1242 info)); 1243 } 1244 1245 1246 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1247 append(new LIR_Op1( 1248 lir_move, 1249 LIR_OprFact::address(address), 1250 dst, 1251 address->type(), 1252 patch_code, 1253 info, lir_move_volatile)); 1254 } 1255 1256 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1257 append(new LIR_Op1( 1258 lir_move, 1259 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1260 dst, 1261 type, 1262 patch_code, 1263 info, lir_move_volatile)); 1264 } 1265 1266 1267 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1268 append(new LIR_Op1( 1269 lir_move, 1270 LIR_OprFact::intConst(v), 1271 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1272 type, 1273 patch_code, 1274 info)); 1275 } 1276 1277 1278 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1279 append(new LIR_Op1( 1280 lir_move, 1281 LIR_OprFact::oopConst(o), 1282 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1283 type, 1284 patch_code, 1285 info)); 1286 } 1287 1288 1289 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1290 append(new LIR_Op1( 1291 lir_move, 1292 src, 1293 LIR_OprFact::address(addr), 1294 addr->type(), 1295 patch_code, 1296 info)); 1297 } 1298 1299 1300 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1301 append(new LIR_Op1( 1302 lir_move, 1303 src, 1304 LIR_OprFact::address(addr), 1305 addr->type(), 1306 patch_code, 1307 info, 1308 lir_move_volatile)); 1309 } 1310 1311 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1312 append(new LIR_Op1( 1313 lir_move, 1314 src, 1315 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1316 type, 1317 patch_code, 1318 info, lir_move_volatile)); 1319 } 1320 1321 1322 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1323 append(new LIR_Op3( 1324 lir_idiv, 1325 left, 1326 right, 1327 tmp, 1328 res, 1329 info)); 1330 } 1331 1332 1333 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1334 append(new LIR_Op3( 1335 lir_idiv, 1336 left, 1337 LIR_OprFact::intConst(right), 1338 tmp, 1339 res, 1340 info)); 1341 } 1342 1343 1344 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1345 append(new LIR_Op3( 1346 lir_irem, 1347 left, 1348 right, 1349 tmp, 1350 res, 1351 info)); 1352 } 1353 1354 1355 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1356 append(new LIR_Op3( 1357 lir_irem, 1358 left, 1359 LIR_OprFact::intConst(right), 1360 tmp, 1361 res, 1362 info)); 1363 } 1364 1365 1366 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1367 append(new LIR_Op2( 1368 lir_cmp, 1369 condition, 1370 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1371 LIR_OprFact::intConst(c), 1372 info)); 1373 } 1374 1375 1376 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1377 append(new LIR_Op2( 1378 lir_cmp, 1379 condition, 1380 reg, 1381 LIR_OprFact::address(addr), 1382 info)); 1383 } 1384 1385 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1386 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1387 append(new LIR_OpAllocObj( 1388 klass, 1389 dst, 1390 t1, 1391 t2, 1392 t3, 1393 t4, 1394 header_size, 1395 object_size, 1396 init_check, 1397 stub)); 1398 } 1399 1400 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1401 append(new LIR_OpAllocArray( 1402 klass, 1403 len, 1404 dst, 1405 t1, 1406 t2, 1407 t3, 1408 t4, 1409 type, 1410 stub)); 1411 } 1412 1413 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1414 append(new LIR_Op2( 1415 lir_shl, 1416 value, 1417 count, 1418 dst, 1419 tmp)); 1420 } 1421 1422 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1423 append(new LIR_Op2( 1424 lir_shr, 1425 value, 1426 count, 1427 dst, 1428 tmp)); 1429 } 1430 1431 1432 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1433 append(new LIR_Op2( 1434 lir_ushr, 1435 value, 1436 count, 1437 dst, 1438 tmp)); 1439 } 1440 1441 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1442 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1443 left, 1444 right, 1445 dst)); 1446 } 1447 1448 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1449 append(new LIR_OpLock( 1450 lir_lock, 1451 hdr, 1452 obj, 1453 lock, 1454 scratch, 1455 stub, 1456 info)); 1457 } 1458 1459 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { 1460 append(new LIR_OpLock( 1461 lir_unlock, 1462 hdr, 1463 obj, 1464 lock, 1465 scratch, 1466 stub, 1467 NULL)); 1468 } 1469 1470 1471 void check_LIR() { 1472 // cannot do the proper checking as PRODUCT and other modes return different results 1473 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1474 } 1475 1476 1477 1478 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1479 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1480 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1481 ciMethod* profiled_method, int profiled_bci) { 1482 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1483 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); 1484 if (profiled_method != NULL) { 1485 c->set_profiled_method(profiled_method); 1486 c->set_profiled_bci(profiled_bci); 1487 c->set_should_profile(true); 1488 } 1489 append(c); 1490 } 1491 1492 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { 1493 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); 1494 if (profiled_method != NULL) { 1495 c->set_profiled_method(profiled_method); 1496 c->set_profiled_bci(profiled_bci); 1497 c->set_should_profile(true); 1498 } 1499 append(c); 1500 } 1501 1502 1503 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1504 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1505 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1506 if (profiled_method != NULL) { 1507 c->set_profiled_method(profiled_method); 1508 c->set_profiled_bci(profiled_bci); 1509 c->set_should_profile(true); 1510 } 1511 append(c); 1512 } 1513 1514 1515 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1516 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1517 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1518 } 1519 1520 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1521 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1522 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); 1523 } 1524 1525 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1526 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1527 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1528 } 1529 1530 1531 #ifdef PRODUCT 1532 1533 void print_LIR(BlockList* blocks) { 1534 } 1535 1536 #else 1537 // LIR_OprDesc 1538 void LIR_OprDesc::print() const { 1539 print(tty); 1540 } 1541 1542 void LIR_OprDesc::print(outputStream* out) const { 1543 if (is_illegal()) { 1544 return; 1545 } 1546 1547 out->print("["); 1548 if (is_pointer()) { 1549 pointer()->print_value_on(out); 1550 } else if (is_single_stack()) { 1551 out->print("stack:%d", single_stack_ix()); 1552 } else if (is_double_stack()) { 1553 out->print("dbl_stack:%d",double_stack_ix()); 1554 } else if (is_virtual()) { 1555 out->print("R%d", vreg_number()); 1556 } else if (is_single_cpu()) { 1557 out->print("%s", as_register()->name()); 1558 } else if (is_double_cpu()) { 1559 out->print("%s", as_register_hi()->name()); 1560 out->print("%s", as_register_lo()->name()); 1561 #if defined(X86) 1562 } else if (is_single_xmm()) { 1563 out->print("%s", as_xmm_float_reg()->name()); 1564 } else if (is_double_xmm()) { 1565 out->print("%s", as_xmm_double_reg()->name()); 1566 } else if (is_single_fpu()) { 1567 out->print("fpu%d", fpu_regnr()); 1568 } else if (is_double_fpu()) { 1569 out->print("fpu%d", fpu_regnrLo()); 1570 #elif defined(ARM) 1571 } else if (is_single_fpu()) { 1572 out->print("s%d", fpu_regnr()); 1573 } else if (is_double_fpu()) { 1574 out->print("d%d", fpu_regnrLo() >> 1); 1575 #else 1576 } else if (is_single_fpu()) { 1577 out->print("%s", as_float_reg()->name()); 1578 } else if (is_double_fpu()) { 1579 out->print("%s", as_double_reg()->name()); 1580 #endif 1581 1582 } else if (is_illegal()) { 1583 out->print("-"); 1584 } else { 1585 out->print("Unknown Operand"); 1586 } 1587 if (!is_illegal()) { 1588 out->print("|%c", type_char()); 1589 } 1590 if (is_register() && is_last_use()) { 1591 out->print("(last_use)"); 1592 } 1593 out->print("]"); 1594 } 1595 1596 1597 // LIR_Address 1598 void LIR_Const::print_value_on(outputStream* out) const { 1599 switch (type()) { 1600 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1601 case T_INT: out->print("int:%d", as_jint()); break; 1602 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; 1603 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1604 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1605 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; 1606 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; 1607 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; 1608 } 1609 } 1610 1611 // LIR_Address 1612 void LIR_Address::print_value_on(outputStream* out) const { 1613 out->print("Base:"); _base->print(out); 1614 if (!_index->is_illegal()) { 1615 out->print(" Index:"); _index->print(out); 1616 switch (scale()) { 1617 case times_1: break; 1618 case times_2: out->print(" * 2"); break; 1619 case times_4: out->print(" * 4"); break; 1620 case times_8: out->print(" * 8"); break; 1621 } 1622 } 1623 out->print(" Disp: " INTX_FORMAT, _disp); 1624 } 1625 1626 // debug output of block header without InstructionPrinter 1627 // (because phi functions are not necessary for LIR) 1628 static void print_block(BlockBegin* x) { 1629 // print block id 1630 BlockEnd* end = x->end(); 1631 tty->print("B%d ", x->block_id()); 1632 1633 // print flags 1634 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1635 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1636 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1637 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1638 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1639 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1640 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1641 1642 // print block bci range 1643 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); 1644 1645 // print predecessors and successors 1646 if (x->number_of_preds() > 0) { 1647 tty->print("preds: "); 1648 for (int i = 0; i < x->number_of_preds(); i ++) { 1649 tty->print("B%d ", x->pred_at(i)->block_id()); 1650 } 1651 } 1652 1653 if (x->number_of_sux() > 0) { 1654 tty->print("sux: "); 1655 for (int i = 0; i < x->number_of_sux(); i ++) { 1656 tty->print("B%d ", x->sux_at(i)->block_id()); 1657 } 1658 } 1659 1660 // print exception handlers 1661 if (x->number_of_exception_handlers() > 0) { 1662 tty->print("xhandler: "); 1663 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1664 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1665 } 1666 } 1667 1668 tty->cr(); 1669 } 1670 1671 void print_LIR(BlockList* blocks) { 1672 tty->print_cr("LIR:"); 1673 int i; 1674 for (i = 0; i < blocks->length(); i++) { 1675 BlockBegin* bb = blocks->at(i); 1676 print_block(bb); 1677 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1678 bb->lir()->print_instructions(); 1679 } 1680 } 1681 1682 void LIR_List::print_instructions() { 1683 for (int i = 0; i < _operations.length(); i++) { 1684 _operations.at(i)->print(); tty->cr(); 1685 } 1686 tty->cr(); 1687 } 1688 1689 // LIR_Ops printing routines 1690 // LIR_Op 1691 void LIR_Op::print_on(outputStream* out) const { 1692 if (id() != -1 || PrintCFGToFile) { 1693 out->print("%4d ", id()); 1694 } else { 1695 out->print(" "); 1696 } 1697 out->print("%s ", name()); 1698 print_instr(out); 1699 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); 1700 #ifdef ASSERT 1701 if (Verbose && _file != NULL) { 1702 out->print(" (%s:%d)", _file, _line); 1703 } 1704 #endif 1705 } 1706 1707 const char * LIR_Op::name() const { 1708 const char* s = NULL; 1709 switch(code()) { 1710 // LIR_Op0 1711 case lir_membar: s = "membar"; break; 1712 case lir_membar_acquire: s = "membar_acquire"; break; 1713 case lir_membar_release: s = "membar_release"; break; 1714 case lir_membar_loadload: s = "membar_loadload"; break; 1715 case lir_membar_storestore: s = "membar_storestore"; break; 1716 case lir_membar_loadstore: s = "membar_loadstore"; break; 1717 case lir_membar_storeload: s = "membar_storeload"; break; 1718 case lir_word_align: s = "word_align"; break; 1719 case lir_label: s = "label"; break; 1720 case lir_nop: s = "nop"; break; 1721 case lir_backwardbranch_target: s = "backbranch"; break; 1722 case lir_std_entry: s = "std_entry"; break; 1723 case lir_osr_entry: s = "osr_entry"; break; 1724 case lir_build_frame: s = "build_frm"; break; 1725 case lir_fpop_raw: s = "fpop_raw"; break; 1726 case lir_24bit_FPU: s = "24bit_FPU"; break; 1727 case lir_reset_FPU: s = "reset_FPU"; break; 1728 case lir_breakpoint: s = "breakpoint"; break; 1729 case lir_get_thread: s = "get_thread"; break; 1730 // LIR_Op1 1731 case lir_fxch: s = "fxch"; break; 1732 case lir_fld: s = "fld"; break; 1733 case lir_ffree: s = "ffree"; break; 1734 case lir_push: s = "push"; break; 1735 case lir_pop: s = "pop"; break; 1736 case lir_null_check: s = "null_check"; break; 1737 case lir_return: s = "return"; break; 1738 case lir_safepoint: s = "safepoint"; break; 1739 case lir_neg: s = "neg"; break; 1740 case lir_leal: s = "leal"; break; 1741 case lir_branch: s = "branch"; break; 1742 case lir_cond_float_branch: s = "flt_cond_br"; break; 1743 case lir_move: s = "move"; break; 1744 case lir_roundfp: s = "roundfp"; break; 1745 case lir_rtcall: s = "rtcall"; break; 1746 case lir_throw: s = "throw"; break; 1747 case lir_unwind: s = "unwind"; break; 1748 case lir_convert: s = "convert"; break; 1749 case lir_alloc_object: s = "alloc_obj"; break; 1750 case lir_monaddr: s = "mon_addr"; break; 1751 case lir_pack64: s = "pack64"; break; 1752 case lir_unpack64: s = "unpack64"; break; 1753 // LIR_Op2 1754 case lir_cmp: s = "cmp"; break; 1755 case lir_cmp_l2i: s = "cmp_l2i"; break; 1756 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1757 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1758 case lir_cmove: s = "cmove"; break; 1759 case lir_add: s = "add"; break; 1760 case lir_sub: s = "sub"; break; 1761 case lir_mul: s = "mul"; break; 1762 case lir_mul_strictfp: s = "mul_strictfp"; break; 1763 case lir_div: s = "div"; break; 1764 case lir_div_strictfp: s = "div_strictfp"; break; 1765 case lir_rem: s = "rem"; break; 1766 case lir_abs: s = "abs"; break; 1767 case lir_sqrt: s = "sqrt"; break; 1768 case lir_sin: s = "sin"; break; 1769 case lir_cos: s = "cos"; break; 1770 case lir_tan: s = "tan"; break; 1771 case lir_log: s = "log"; break; 1772 case lir_log10: s = "log10"; break; 1773 case lir_exp: s = "exp"; break; 1774 case lir_pow: s = "pow"; break; 1775 case lir_logic_and: s = "logic_and"; break; 1776 case lir_logic_or: s = "logic_or"; break; 1777 case lir_logic_xor: s = "logic_xor"; break; 1778 case lir_shl: s = "shift_left"; break; 1779 case lir_shr: s = "shift_right"; break; 1780 case lir_ushr: s = "ushift_right"; break; 1781 case lir_alloc_array: s = "alloc_array"; break; 1782 case lir_xadd: s = "xadd"; break; 1783 case lir_xchg: s = "xchg"; break; 1784 // LIR_Op3 1785 case lir_idiv: s = "idiv"; break; 1786 case lir_irem: s = "irem"; break; 1787 // LIR_OpJavaCall 1788 case lir_static_call: s = "static"; break; 1789 case lir_optvirtual_call: s = "optvirtual"; break; 1790 case lir_icvirtual_call: s = "icvirtual"; break; 1791 case lir_virtual_call: s = "virtual"; break; 1792 case lir_dynamic_call: s = "dynamic"; break; 1793 // LIR_OpArrayCopy 1794 case lir_arraycopy: s = "arraycopy"; break; 1795 // LIR_OpUpdateCRC32 1796 case lir_updatecrc32: s = "updatecrc32"; break; 1797 // LIR_OpLock 1798 case lir_lock: s = "lock"; break; 1799 case lir_unlock: s = "unlock"; break; 1800 // LIR_OpDelay 1801 case lir_delay_slot: s = "delay"; break; 1802 // LIR_OpTypeCheck 1803 case lir_instanceof: s = "instanceof"; break; 1804 case lir_checkcast: s = "checkcast"; break; 1805 case lir_store_check: s = "store_check"; break; 1806 // LIR_OpCompareAndSwap 1807 case lir_cas_long: s = "cas_long"; break; 1808 case lir_cas_obj: s = "cas_obj"; break; 1809 case lir_cas_int: s = "cas_int"; break; 1810 // LIR_OpProfileCall 1811 case lir_profile_call: s = "profile_call"; break; 1812 // LIR_OpProfileType 1813 case lir_profile_type: s = "profile_type"; break; 1814 // LIR_OpAssert 1815 #ifdef ASSERT 1816 case lir_assert: s = "assert"; break; 1817 #endif 1818 case lir_none: ShouldNotReachHere();break; 1819 default: s = "illegal_op"; break; 1820 } 1821 return s; 1822 } 1823 1824 // LIR_OpJavaCall 1825 void LIR_OpJavaCall::print_instr(outputStream* out) const { 1826 out->print("call: "); 1827 out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); 1828 if (receiver()->is_valid()) { 1829 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1830 } 1831 if (result_opr()->is_valid()) { 1832 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1833 } 1834 } 1835 1836 // LIR_OpLabel 1837 void LIR_OpLabel::print_instr(outputStream* out) const { 1838 out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); 1839 } 1840 1841 // LIR_OpArrayCopy 1842 void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1843 src()->print(out); out->print(" "); 1844 src_pos()->print(out); out->print(" "); 1845 dst()->print(out); out->print(" "); 1846 dst_pos()->print(out); out->print(" "); 1847 length()->print(out); out->print(" "); 1848 tmp()->print(out); out->print(" "); 1849 } 1850 1851 // LIR_OpUpdateCRC32 1852 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { 1853 crc()->print(out); out->print(" "); 1854 val()->print(out); out->print(" "); 1855 result_opr()->print(out); out->print(" "); 1856 } 1857 1858 // LIR_OpCompareAndSwap 1859 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1860 addr()->print(out); out->print(" "); 1861 cmp_value()->print(out); out->print(" "); 1862 new_value()->print(out); out->print(" "); 1863 tmp1()->print(out); out->print(" "); 1864 tmp2()->print(out); out->print(" "); 1865 1866 } 1867 1868 // LIR_Op0 1869 void LIR_Op0::print_instr(outputStream* out) const { 1870 result_opr()->print(out); 1871 } 1872 1873 // LIR_Op1 1874 const char * LIR_Op1::name() const { 1875 if (code() == lir_move) { 1876 switch (move_kind()) { 1877 case lir_move_normal: 1878 return "move"; 1879 case lir_move_unaligned: 1880 return "unaligned move"; 1881 case lir_move_volatile: 1882 return "volatile_move"; 1883 case lir_move_wide: 1884 return "wide_move"; 1885 default: 1886 ShouldNotReachHere(); 1887 return "illegal_op"; 1888 } 1889 } else { 1890 return LIR_Op::name(); 1891 } 1892 } 1893 1894 1895 void LIR_Op1::print_instr(outputStream* out) const { 1896 _opr->print(out); out->print(" "); 1897 result_opr()->print(out); out->print(" "); 1898 print_patch_code(out, patch_code()); 1899 } 1900 1901 1902 // LIR_Op1 1903 void LIR_OpRTCall::print_instr(outputStream* out) const { 1904 intx a = (intx)addr(); 1905 out->print("%s", Runtime1::name_for_address(addr())); 1906 out->print(" "); 1907 tmp()->print(out); 1908 } 1909 1910 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1911 switch(code) { 1912 case lir_patch_none: break; 1913 case lir_patch_low: out->print("[patch_low]"); break; 1914 case lir_patch_high: out->print("[patch_high]"); break; 1915 case lir_patch_normal: out->print("[patch_normal]"); break; 1916 default: ShouldNotReachHere(); 1917 } 1918 } 1919 1920 // LIR_OpBranch 1921 void LIR_OpBranch::print_instr(outputStream* out) const { 1922 print_condition(out, cond()); out->print(" "); 1923 if (block() != NULL) { 1924 out->print("[B%d] ", block()->block_id()); 1925 } else if (stub() != NULL) { 1926 out->print("["); 1927 stub()->print_name(out); 1928 out->print(": " INTPTR_FORMAT "]", p2i(stub())); 1929 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); 1930 } else { 1931 out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); 1932 } 1933 if (ublock() != NULL) { 1934 out->print("unordered: [B%d] ", ublock()->block_id()); 1935 } 1936 } 1937 1938 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1939 switch(cond) { 1940 case lir_cond_equal: out->print("[EQ]"); break; 1941 case lir_cond_notEqual: out->print("[NE]"); break; 1942 case lir_cond_less: out->print("[LT]"); break; 1943 case lir_cond_lessEqual: out->print("[LE]"); break; 1944 case lir_cond_greaterEqual: out->print("[GE]"); break; 1945 case lir_cond_greater: out->print("[GT]"); break; 1946 case lir_cond_belowEqual: out->print("[BE]"); break; 1947 case lir_cond_aboveEqual: out->print("[AE]"); break; 1948 case lir_cond_always: out->print("[AL]"); break; 1949 default: out->print("[%d]",cond); break; 1950 } 1951 } 1952 1953 // LIR_OpConvert 1954 void LIR_OpConvert::print_instr(outputStream* out) const { 1955 print_bytecode(out, bytecode()); 1956 in_opr()->print(out); out->print(" "); 1957 result_opr()->print(out); out->print(" "); 1958 #ifdef PPC 1959 if(tmp1()->is_valid()) { 1960 tmp1()->print(out); out->print(" "); 1961 tmp2()->print(out); out->print(" "); 1962 } 1963 #endif 1964 } 1965 1966 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1967 switch(code) { 1968 case Bytecodes::_d2f: out->print("[d2f] "); break; 1969 case Bytecodes::_d2i: out->print("[d2i] "); break; 1970 case Bytecodes::_d2l: out->print("[d2l] "); break; 1971 case Bytecodes::_f2d: out->print("[f2d] "); break; 1972 case Bytecodes::_f2i: out->print("[f2i] "); break; 1973 case Bytecodes::_f2l: out->print("[f2l] "); break; 1974 case Bytecodes::_i2b: out->print("[i2b] "); break; 1975 case Bytecodes::_i2c: out->print("[i2c] "); break; 1976 case Bytecodes::_i2d: out->print("[i2d] "); break; 1977 case Bytecodes::_i2f: out->print("[i2f] "); break; 1978 case Bytecodes::_i2l: out->print("[i2l] "); break; 1979 case Bytecodes::_i2s: out->print("[i2s] "); break; 1980 case Bytecodes::_l2i: out->print("[l2i] "); break; 1981 case Bytecodes::_l2f: out->print("[l2f] "); break; 1982 case Bytecodes::_l2d: out->print("[l2d] "); break; 1983 default: 1984 out->print("[?%d]",code); 1985 break; 1986 } 1987 } 1988 1989 void LIR_OpAllocObj::print_instr(outputStream* out) const { 1990 klass()->print(out); out->print(" "); 1991 obj()->print(out); out->print(" "); 1992 tmp1()->print(out); out->print(" "); 1993 tmp2()->print(out); out->print(" "); 1994 tmp3()->print(out); out->print(" "); 1995 tmp4()->print(out); out->print(" "); 1996 out->print("[hdr:%d]", header_size()); out->print(" "); 1997 out->print("[obj:%d]", object_size()); out->print(" "); 1998 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 1999 } 2000 2001 void LIR_OpRoundFP::print_instr(outputStream* out) const { 2002 _opr->print(out); out->print(" "); 2003 tmp()->print(out); out->print(" "); 2004 result_opr()->print(out); out->print(" "); 2005 } 2006 2007 // LIR_Op2 2008 void LIR_Op2::print_instr(outputStream* out) const { 2009 if (code() == lir_cmove) { 2010 print_condition(out, condition()); out->print(" "); 2011 } 2012 in_opr1()->print(out); out->print(" "); 2013 in_opr2()->print(out); out->print(" "); 2014 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 2015 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 2016 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 2017 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } 2018 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } 2019 result_opr()->print(out); 2020 } 2021 2022 void LIR_OpAllocArray::print_instr(outputStream* out) const { 2023 klass()->print(out); out->print(" "); 2024 len()->print(out); out->print(" "); 2025 obj()->print(out); out->print(" "); 2026 tmp1()->print(out); out->print(" "); 2027 tmp2()->print(out); out->print(" "); 2028 tmp3()->print(out); out->print(" "); 2029 tmp4()->print(out); out->print(" "); 2030 out->print("[type:0x%x]", type()); out->print(" "); 2031 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2032 } 2033 2034 2035 void LIR_OpTypeCheck::print_instr(outputStream* out) const { 2036 object()->print(out); out->print(" "); 2037 if (code() == lir_store_check) { 2038 array()->print(out); out->print(" "); 2039 } 2040 if (code() != lir_store_check) { 2041 klass()->print_name_on(out); out->print(" "); 2042 if (fast_check()) out->print("fast_check "); 2043 } 2044 tmp1()->print(out); out->print(" "); 2045 tmp2()->print(out); out->print(" "); 2046 tmp3()->print(out); out->print(" "); 2047 result_opr()->print(out); out->print(" "); 2048 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); 2049 } 2050 2051 2052 // LIR_Op3 2053 void LIR_Op3::print_instr(outputStream* out) const { 2054 in_opr1()->print(out); out->print(" "); 2055 in_opr2()->print(out); out->print(" "); 2056 in_opr3()->print(out); out->print(" "); 2057 result_opr()->print(out); 2058 } 2059 2060 2061 void LIR_OpLock::print_instr(outputStream* out) const { 2062 hdr_opr()->print(out); out->print(" "); 2063 obj_opr()->print(out); out->print(" "); 2064 lock_opr()->print(out); out->print(" "); 2065 if (_scratch->is_valid()) { 2066 _scratch->print(out); out->print(" "); 2067 } 2068 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2069 } 2070 2071 #ifdef ASSERT 2072 void LIR_OpAssert::print_instr(outputStream* out) const { 2073 print_condition(out, condition()); out->print(" "); 2074 in_opr1()->print(out); out->print(" "); 2075 in_opr2()->print(out); out->print(", \""); 2076 out->print("%s", msg()); out->print("\""); 2077 } 2078 #endif 2079 2080 2081 void LIR_OpDelay::print_instr(outputStream* out) const { 2082 _op->print_on(out); 2083 } 2084 2085 2086 // LIR_OpProfileCall 2087 void LIR_OpProfileCall::print_instr(outputStream* out) const { 2088 profiled_method()->name()->print_symbol_on(out); 2089 out->print("."); 2090 profiled_method()->holder()->name()->print_symbol_on(out); 2091 out->print(" @ %d ", profiled_bci()); 2092 mdo()->print(out); out->print(" "); 2093 recv()->print(out); out->print(" "); 2094 tmp1()->print(out); out->print(" "); 2095 } 2096 2097 // LIR_OpProfileType 2098 void LIR_OpProfileType::print_instr(outputStream* out) const { 2099 out->print("exact = "); exact_klass()->print_name_on(out); 2100 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass()); 2101 mdp()->print(out); out->print(" "); 2102 obj()->print(out); out->print(" "); 2103 tmp()->print(out); out->print(" "); 2104 } 2105 2106 #endif // PRODUCT 2107 2108 // Implementation of LIR_InsertionBuffer 2109 2110 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 2111 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 2112 2113 int i = number_of_insertion_points() - 1; 2114 if (i < 0 || index_at(i) < index) { 2115 append_new(index, 1); 2116 } else { 2117 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 2118 assert(count_at(i) > 0, "check"); 2119 set_count_at(i, count_at(i) + 1); 2120 } 2121 _ops.push(op); 2122 2123 DEBUG_ONLY(verify()); 2124 } 2125 2126 #ifdef ASSERT 2127 void LIR_InsertionBuffer::verify() { 2128 int sum = 0; 2129 int prev_idx = -1; 2130 2131 for (int i = 0; i < number_of_insertion_points(); i++) { 2132 assert(prev_idx < index_at(i), "index must be ordered ascending"); 2133 sum += count_at(i); 2134 } 2135 assert(sum == number_of_ops(), "wrong total sum"); 2136 } 2137 #endif