1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
491 // Empty encoding
492 }
493
494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
495 return 0;
496 }
497
498 #ifndef PRODUCT
499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
500 st->print("# MachConstantBaseNode (empty encoding)");
501 }
502 #endif
503
504
505 //=============================================================================
506 #ifndef PRODUCT
507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
508 Compile* C = ra_->C;
509
510 int framesize = C->frame_slots() << LogBytesPerInt;
511 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
512 // Remove wordSize for return addr which is already pushed.
513 framesize -= wordSize;
514
515 if (C->need_stack_bang(framesize)) {
516 framesize -= wordSize;
517 st->print("# stack bang");
518 st->print("\n\t");
519 st->print("PUSH EBP\t# Save EBP");
520 if (framesize) {
521 st->print("\n\t");
522 st->print("SUB ESP, #%d\t# Create frame",framesize);
523 }
524 } else {
525 st->print("SUB ESP, #%d\t# Create frame",framesize);
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
529 }
530
531 if (VerifyStackAtCalls) {
532 st->print("\n\t");
533 framesize -= wordSize;
534 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
535 }
536
537 if( C->in_24_bit_fp_mode() ) {
538 st->print("\n\t");
539 st->print("FLDCW \t# load 24 bit fpu control word");
540 }
541 if (UseSSE >= 2 && VerifyFPU) {
542 st->print("\n\t");
543 st->print("# verify FPU stack (must be clean on entry)");
544 }
545
546 #ifdef ASSERT
547 if (VerifyStackAtCalls) {
548 st->print("\n\t");
549 st->print("# stack alignment check");
550 }
551 #endif
552 st->cr();
553 }
554 #endif
555
556
557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
558 Compile* C = ra_->C;
559 MacroAssembler _masm(&cbuf);
560
561 int framesize = C->frame_slots() << LogBytesPerInt;
562
563 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
564
565 C->set_frame_complete(cbuf.insts_size());
566
567 if (C->has_mach_constant_base_node()) {
568 // NOTE: We set the table base offset here because users might be
569 // emitted before MachConstantBaseNode.
570 Compile::ConstantTable& constant_table = C->constant_table();
571 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
572 }
573 }
574
575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
576 return MachNode::size(ra_); // too many variables; just compute it the hard way
577 }
578
579 int MachPrologNode::reloc() const {
580 return 0; // a large enough number
581 }
582
583 //=============================================================================
584 #ifndef PRODUCT
585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
586 Compile *C = ra_->C;
587 int framesize = C->frame_slots() << LogBytesPerInt;
588 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
589 // Remove two words for return addr and rbp,
590 framesize -= 2*wordSize;
591
592 if (C->max_vector_size() > 16) {
593 st->print("VZEROUPPER");
594 st->cr(); st->print("\t");
595 }
596 if (C->in_24_bit_fp_mode()) {
597 st->print("FLDCW standard control word");
598 st->cr(); st->print("\t");
599 }
600 if (framesize) {
601 st->print("ADD ESP,%d\t# Destroy frame",framesize);
602 st->cr(); st->print("\t");
603 }
604 st->print_cr("POPL EBP"); st->print("\t");
605 if (do_polling() && C->is_method_compilation()) {
606 st->print("TEST PollPage,EAX\t! Poll Safepoint");
607 st->cr(); st->print("\t");
608 }
609 }
610 #endif
611
612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
613 Compile *C = ra_->C;
614
615 if (C->max_vector_size() > 16) {
616 // Clear upper bits of YMM registers when current compiled code uses
617 // wide vectors to avoid AVX <-> SSE transition penalty during call.
618 MacroAssembler masm(&cbuf);
619 masm.vzeroupper();
620 }
621 // If method set FPU control word, restore to standard control word
622 if (C->in_24_bit_fp_mode()) {
623 MacroAssembler masm(&cbuf);
624 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
625 }
626
627 int framesize = C->frame_slots() << LogBytesPerInt;
628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
629 // Remove two words for return addr and rbp,
630 framesize -= 2*wordSize;
631
632 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
633
634 if (framesize >= 128) {
635 emit_opcode(cbuf, 0x81); // add SP, #framesize
636 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
637 emit_d32(cbuf, framesize);
638 } else if (framesize) {
639 emit_opcode(cbuf, 0x83); // add SP, #framesize
640 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
641 emit_d8(cbuf, framesize);
642 }
643
644 emit_opcode(cbuf, 0x58 | EBP_enc);
645
646 if (do_polling() && C->is_method_compilation()) {
647 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
648 emit_opcode(cbuf,0x85);
649 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
650 emit_d32(cbuf, (intptr_t)os::get_polling_page());
651 }
652 }
653
654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
655 Compile *C = ra_->C;
656 // If method set FPU control word, restore to standard control word
657 int size = C->in_24_bit_fp_mode() ? 6 : 0;
658 if (C->max_vector_size() > 16) size += 3; // vzeroupper
659 if (do_polling() && C->is_method_compilation()) size += 6;
660
661 int framesize = C->frame_slots() << LogBytesPerInt;
662 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
663 // Remove two words for return addr and rbp,
664 framesize -= 2*wordSize;
665
666 size++; // popl rbp,
667
668 if (framesize >= 128) {
669 size += 6;
670 } else {
671 size += framesize ? 3 : 0;
672 }
673 return size;
674 }
675
676 int MachEpilogNode::reloc() const {
677 return 0; // a large enough number
678 }
679
680 const Pipeline * MachEpilogNode::pipeline() const {
681 return MachNode::pipeline_class();
682 }
683
684 int MachEpilogNode::safepoint_offset() const { return 0; }
685
686 //=============================================================================
687
688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
689 static enum RC rc_class( OptoReg::Name reg ) {
690
691 if( !OptoReg::is_valid(reg) ) return rc_bad;
692 if (OptoReg::is_stack(reg)) return rc_stack;
693
694 VMReg r = OptoReg::as_VMReg(reg);
695 if (r->is_Register()) return rc_int;
696 if (r->is_FloatRegister()) {
697 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
698 return rc_float;
699 }
700 assert(r->is_XMMRegister(), "must be");
701 return rc_xmm;
702 }
703
704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
705 int opcode, const char *op_str, int size, outputStream* st ) {
706 if( cbuf ) {
707 emit_opcode (*cbuf, opcode );
708 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
709 #ifndef PRODUCT
710 } else if( !do_size ) {
711 if( size != 0 ) st->print("\n\t");
712 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
713 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
714 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
715 } else { // FLD, FST, PUSH, POP
716 st->print("%s [ESP + #%d]",op_str,offset);
717 }
718 #endif
719 }
720 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
721 return size+3+offset_size;
722 }
723
724 // Helper for XMM registers. Extra opcode bits, limited syntax.
725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
726 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
727 if (cbuf) {
728 MacroAssembler _masm(cbuf);
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) {
731 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
732 } else {
733 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
734 }
735 } else {
736 if (is_load) {
737 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
738 } else {
739 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
740 }
741 }
742 #ifndef PRODUCT
743 } else if (!do_size) {
744 if (size != 0) st->print("\n\t");
745 if (reg_lo+1 == reg_hi) { // double move?
746 if (is_load) st->print("%s %s,[ESP + #%d]",
747 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
748 Matcher::regName[reg_lo], offset);
749 else st->print("MOVSD [ESP + #%d],%s",
750 offset, Matcher::regName[reg_lo]);
751 } else {
752 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSS [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 }
757 #endif
758 }
759 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
760 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
761 return size+5+offset_size;
762 }
763
764
765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
766 int src_hi, int dst_hi, int size, outputStream* st ) {
767 if (cbuf) {
768 MacroAssembler _masm(cbuf);
769 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
770 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
771 as_XMMRegister(Matcher::_regEncode[src_lo]));
772 } else {
773 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
774 as_XMMRegister(Matcher::_regEncode[src_lo]));
775 }
776 #ifndef PRODUCT
777 } else if (!do_size) {
778 if (size != 0) st->print("\n\t");
779 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
780 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
781 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
782 } else {
783 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
784 }
785 } else {
786 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
787 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
788 } else {
789 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
790 }
791 }
792 #endif
793 }
794 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
795 // Only MOVAPS SSE prefix uses 1 byte.
796 int sz = 4;
797 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
798 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
799 return size + sz;
800 }
801
802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
808 as_Register(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817
818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
819 int src_hi, int dst_hi, int size, outputStream* st ) {
820 // 32-bit
821 if (cbuf) {
822 MacroAssembler _masm(cbuf);
823 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
824 as_XMMRegister(Matcher::_regEncode[src_lo]));
825 #ifndef PRODUCT
826 } else if (!do_size) {
827 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
828 #endif
829 }
830 return 4;
831 }
832
833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
834 if( cbuf ) {
835 emit_opcode(*cbuf, 0x8B );
836 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
837 #ifndef PRODUCT
838 } else if( !do_size ) {
839 if( size != 0 ) st->print("\n\t");
840 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
841 #endif
842 }
843 return size+2;
844 }
845
846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
847 int offset, int size, outputStream* st ) {
848 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
849 if( cbuf ) {
850 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
851 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
852 #ifndef PRODUCT
853 } else if( !do_size ) {
854 if( size != 0 ) st->print("\n\t");
855 st->print("FLD %s",Matcher::regName[src_lo]);
856 #endif
857 }
858 size += 2;
859 }
860
861 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
862 const char *op_str;
863 int op;
864 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
865 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
866 op = 0xDD;
867 } else { // 32-bit store
868 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
869 op = 0xD9;
870 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
871 }
872
873 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
874 }
875
876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
878 int src_hi, int dst_hi, uint ireg, outputStream* st);
879
880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
881 int stack_offset, int reg, uint ireg, outputStream* st);
882
883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
884 int dst_offset, uint ireg, outputStream* st) {
885 int calc_size = 0;
886 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
887 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
888 switch (ireg) {
889 case Op_VecS:
890 calc_size = 3+src_offset_size + 3+dst_offset_size;
891 break;
892 case Op_VecD:
893 calc_size = 3+src_offset_size + 3+dst_offset_size;
894 src_offset += 4;
895 dst_offset += 4;
896 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
897 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
898 calc_size += 3+src_offset_size + 3+dst_offset_size;
899 break;
900 case Op_VecX:
901 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
902 break;
903 case Op_VecY:
904 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
905 break;
906 default:
907 ShouldNotReachHere();
908 }
909 if (cbuf) {
910 MacroAssembler _masm(cbuf);
911 int offset = __ offset();
912 switch (ireg) {
913 case Op_VecS:
914 __ pushl(Address(rsp, src_offset));
915 __ popl (Address(rsp, dst_offset));
916 break;
917 case Op_VecD:
918 __ pushl(Address(rsp, src_offset));
919 __ popl (Address(rsp, dst_offset));
920 __ pushl(Address(rsp, src_offset+4));
921 __ popl (Address(rsp, dst_offset+4));
922 break;
923 case Op_VecX:
924 __ movdqu(Address(rsp, -16), xmm0);
925 __ movdqu(xmm0, Address(rsp, src_offset));
926 __ movdqu(Address(rsp, dst_offset), xmm0);
927 __ movdqu(xmm0, Address(rsp, -16));
928 break;
929 case Op_VecY:
930 __ vmovdqu(Address(rsp, -32), xmm0);
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
933 __ vmovdqu(xmm0, Address(rsp, -32));
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 int size = __ offset() - offset;
939 assert(size == calc_size, "incorrect size calculattion");
940 return size;
941 #ifndef PRODUCT
942 } else if (!do_size) {
943 switch (ireg) {
944 case Op_VecS:
945 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
946 "popl [rsp + #%d]",
947 src_offset, dst_offset);
948 break;
949 case Op_VecD:
950 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
951 "popq [rsp + #%d]\n\t"
952 "pushl [rsp + #%d]\n\t"
953 "popq [rsp + #%d]",
954 src_offset, dst_offset, src_offset+4, dst_offset+4);
955 break;
956 case Op_VecX:
957 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
958 "movdqu xmm0, [rsp + #%d]\n\t"
959 "movdqu [rsp + #%d], xmm0\n\t"
960 "movdqu xmm0, [rsp - #16]",
961 src_offset, dst_offset);
962 break;
963 case Op_VecY:
964 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
965 "vmovdqu xmm0, [rsp + #%d]\n\t"
966 "vmovdqu [rsp + #%d], xmm0\n\t"
967 "vmovdqu xmm0, [rsp - #32]",
968 src_offset, dst_offset);
969 break;
970 default:
971 ShouldNotReachHere();
972 }
973 #endif
974 }
975 return calc_size;
976 }
977
978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
979 // Get registers to move
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
982 OptoReg::Name dst_second = ra_->get_reg_second(this );
983 OptoReg::Name dst_first = ra_->get_reg_first(this );
984
985 enum RC src_second_rc = rc_class(src_second);
986 enum RC src_first_rc = rc_class(src_first);
987 enum RC dst_second_rc = rc_class(dst_second);
988 enum RC dst_first_rc = rc_class(dst_first);
989
990 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
991
992 // Generate spill code!
993 int size = 0;
994
995 if( src_first == dst_first && src_second == dst_second )
996 return size; // Self copy, no move
997
998 if (bottom_type()->isa_vect() != NULL) {
999 uint ireg = ideal_reg();
1000 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004 // mem -> mem
1005 int src_offset = ra_->reg2offset(src_first);
1006 int dst_offset = ra_->reg2offset(dst_first);
1007 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011 int stack_offset = ra_->reg2offset(dst_first);
1012 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014 int stack_offset = ra_->reg2offset(src_first);
1015 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1016 } else {
1017 ShouldNotReachHere();
1018 }
1019 }
1020
1021 // --------------------------------------
1022 // Check for mem-mem move. push/pop to move.
1023 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024 if( src_second == dst_first ) { // overlapping stack copy ranges
1025 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1027 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1028 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1029 }
1030 // move low bits
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1033 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1035 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1036 }
1037 return size;
1038 }
1039
1040 // --------------------------------------
1041 // Check for integer reg-reg copy
1042 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1044
1045 // Check for integer store
1046 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1048
1049 // Check for integer load
1050 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1052
1053 // Check for integer reg-xmm reg copy
1054 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056 "no 64 bit integer-float reg moves" );
1057 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058 }
1059 // --------------------------------------
1060 // Check for float reg-reg copy
1061 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064 if( cbuf ) {
1065
1066 // Note the mucking with the register encode to compensate for the 0/1
1067 // indexing issue mentioned in a comment in the reg_def sections
1068 // for FPR registers many lines above here.
1069
1070 if( src_first != FPR1L_num ) {
1071 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1072 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1074 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075 } else {
1076 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1077 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078 }
1079 #ifndef PRODUCT
1080 } else if( !do_size ) {
1081 if( size != 0 ) st->print("\n\t");
1082 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083 else st->print( "FST %s", Matcher::regName[dst_first]);
1084 #endif
1085 }
1086 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087 }
1088
1089 // Check for float store
1090 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092 }
1093
1094 // Check for float load
1095 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096 int offset = ra_->reg2offset(src_first);
1097 const char *op_str;
1098 int op;
1099 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100 op_str = "FLD_D";
1101 op = 0xDD;
1102 } else { // 32-bit load
1103 op_str = "FLD_S";
1104 op = 0xD9;
1105 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106 }
1107 if( cbuf ) {
1108 emit_opcode (*cbuf, op );
1109 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1111 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113 } else if( !do_size ) {
1114 if( size != 0 ) st->print("\n\t");
1115 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117 }
1118 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119 return size + 3+offset_size+2;
1120 }
1121
1122 // Check for xmm reg-reg copy
1123 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125 (src_first+1 == src_second && dst_first+1 == dst_second),
1126 "no non-adjacent float-moves" );
1127 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128 }
1129
1130 // Check for xmm reg-integer reg copy
1131 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133 "no 64 bit float-integer reg moves" );
1134 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135 }
1136
1137 // Check for xmm store
1138 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140 }
1141
1142 // Check for float xmm load
1143 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145 }
1146
1147 // Copy from float reg to xmm reg
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149 // copy to the top of stack from floating point reg
1150 // and use LEA to preserve flags
1151 if( cbuf ) {
1152 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1153 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155 emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157 } else if( !do_size ) {
1158 if( size != 0 ) st->print("\n\t");
1159 st->print("LEA ESP,[ESP-8]");
1160 #endif
1161 }
1162 size += 4;
1163
1164 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1165
1166 // Copy from the temp memory to the xmm reg.
1167 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1168
1169 if( cbuf ) {
1170 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1171 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173 emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175 } else if( !do_size ) {
1176 if( size != 0 ) st->print("\n\t");
1177 st->print("LEA ESP,[ESP+8]");
1178 #endif
1179 }
1180 size += 4;
1181 return size;
1182 }
1183
1184 assert( size > 0, "missed a case" );
1185
1186 // --------------------------------------------------------------------
1187 // Check for second bits still needing moving.
1188 if( src_second == dst_second )
1189 return size; // Self copy; no move
1190 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1191
1192 // Check for second word int-int move
1193 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1195
1196 // Check for second word integer store
1197 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1199
1200 // Check for second word integer load
1201 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1203
1204
1205 Unimplemented();
1206 }
1207
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210 implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1213
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215 implementation( &cbuf, ra_, false, NULL );
1216 }
1217
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219 return implementation( NULL, ra_, true, NULL );
1220 }
1221
1222
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227 int reg = ra_->get_reg_first(this);
1228 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1231
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234 int reg = ra_->get_encode(this);
1235 if( offset >= 128 ) {
1236 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1237 emit_rm(cbuf, 0x2, reg, 0x04);
1238 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239 emit_d32(cbuf, offset);
1240 }
1241 else {
1242 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1243 emit_rm(cbuf, 0x1, reg, 0x04);
1244 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245 emit_d8(cbuf, offset);
1246 }
1247 }
1248
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251 if( offset >= 128 ) {
1252 return 7;
1253 }
1254 else {
1255 return 4;
1256 }
1257 }
1258
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1263 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1264 st->print_cr("\tNOP");
1265 st->print_cr("\tNOP");
1266 if( !OptoBreakpoint )
1267 st->print_cr("\tNOP");
1268 }
1269 #endif
1270
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272 MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274 uint insts_size = cbuf.insts_size();
1275 #endif
1276 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277 masm.jump_cc(Assembler::notEqual,
1278 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279 /* WARNING these NOPs are critical so that verified entry point is properly
1280 aligned for patching by NativeJump::patch_verified_entry() */
1281 int nops_cnt = 2;
1282 if( !OptoBreakpoint ) // Leave space for int3
1283 nops_cnt += 1;
1284 masm.nop(nops_cnt);
1285
1286 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1288
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290 return OptoBreakpoint ? 11 : 12;
1291 }
1292
1293
1294 //=============================================================================
1295 uint size_exception_handler() {
1296 // NativeCall instruction size is the same as NativeJump.
1297 // exception handler starts out as jump and can be patched to
1298 // a call be deoptimization. (4932387)
1299 // Note that this value is also credited (in output.cpp) to
1300 // the size of the code section.
1301 return NativeJump::instruction_size;
1302 }
1303
1304 // Emit exception handler code. Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1307
1308 // Note that the code buffer's insts_mark is always relative to insts.
1309 // That's why we must use the macroassembler to generate a handler.
1310 MacroAssembler _masm(&cbuf);
1311 address base =
1312 __ start_a_stub(size_exception_handler());
1313 if (base == NULL) return 0; // CodeBuffer::expand failed
1314 int offset = __ offset();
1315 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317 __ end_a_stub();
1318 return offset;
1319 }
1320
1321 uint size_deopt_handler() {
1322 // NativeCall instruction size is the same as NativeJump.
1323 // exception handler starts out as jump and can be patched to
1324 // a call be deoptimization. (4932387)
1325 // Note that this value is also credited (in output.cpp) to
1326 // the size of the code section.
1327 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1329
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1332
1333 // Note that the code buffer's insts_mark is always relative to insts.
1334 // That's why we must use the macroassembler to generate a handler.
1335 MacroAssembler _masm(&cbuf);
1336 address base =
1337 __ start_a_stub(size_exception_handler());
1338 if (base == NULL) return 0; // CodeBuffer::expand failed
1339 int offset = __ offset();
1340 InternalAddress here(__ pc());
1341 __ pushptr(here.addr());
1342
1343 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345 __ end_a_stub();
1346 return offset;
1347 }
1348
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1352
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1357
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 // this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363 // The passed offset is relative to address of the branch.
1364 // On 86 a branch displacement is calculated relative to address
1365 // of a next instruction.
1366 offset -= br_size;
1367
1368 // the short version of jmpConUCF2 contains multiple branches,
1369 // making the reach slightly less
1370 if (rule == jmpConUCF2_rule)
1371 return (-126 <= offset && offset <= 125);
1372 return (-128 <= offset && offset <= 127);
1373 }
1374
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377 return false;
1378 }
1379
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1382
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1385
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1388
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers? True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1396
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1400
1401 bool Matcher::narrow_oop_use_complex_address() {
1402 ShouldNotCallThis();
1403 return true;
1404 }
1405
1406 bool Matcher::narrow_klass_use_complex_address() {
1407 ShouldNotCallThis();
1408 return true;
1409 }
1410
1411
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers. Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1417
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed. Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece. Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1423
1424
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426 // Get the memory operand from the node
1427 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1428 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1429 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430 uint opcnt = 1; // First operand
1431 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432 while( idx >= skipped+num_edges ) {
1433 skipped += num_edges;
1434 opcnt++; // Bump operand count
1435 assert( opcnt < numopnds, "Accessing non-existent operand" );
1436 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437 }
1438
1439 MachOper *memory = node->_opnds[opcnt];
1440 MachOper *new_memory = NULL;
1441 switch (memory->opcode()) {
1442 case DIRECT:
1443 case INDOFFSET32X:
1444 // No transformation necessary.
1445 return;
1446 case INDIRECT:
1447 new_memory = new (C) indirect_win95_safeOper( );
1448 break;
1449 case INDOFFSET8:
1450 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451 break;
1452 case INDOFFSET32:
1453 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454 break;
1455 case INDINDEXOFFSET:
1456 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457 break;
1458 case INDINDEXSCALE:
1459 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460 break;
1461 case INDINDEXSCALEOFFSET:
1462 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463 break;
1464 case LOAD_LONG_INDIRECT:
1465 case LOAD_LONG_INDOFFSET32:
1466 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467 return;
1468 default:
1469 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470 return;
1471 }
1472 node->_opnds[opcnt] = new_memory;
1473 }
1474
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1478
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1482
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1485
1486 // Return whether or not this register is ever used as an argument. This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491 if( reg == ECX_num || reg == EDX_num ) return true;
1492 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494 return false;
1495 }
1496
1497 bool Matcher::is_spillable_arg( int reg ) {
1498 return can_be_java_arg(reg);
1499 }
1500
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502 // Use hardware integer DIV instruction when
1503 // it is faster than a code which use multiply.
1504 // Only when constant divisor fits into 32 bit
1505 // (min_jint is excluded to get only correct
1506 // positive 32 bit values from negative).
1507 return VM_Version::has_fast_idiv() &&
1508 (divisor == (int)divisor && divisor != min_jint);
1509 }
1510
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513 return EAX_REG_mask();
1514 }
1515
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518 return EDX_REG_mask();
1519 }
1520
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523 ShouldNotReachHere();
1524 return RegMask();
1525 }
1526
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529 ShouldNotReachHere();
1530 return RegMask();
1531 }
1532
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534 return EBP_REG_mask();
1535 }
1536
1537 // Returns true if the high 32 bits of the value is known to be zero.
1538 bool is_operand_hi32_zero(Node* n) {
1539 int opc = n->Opcode();
1540 if (opc == Op_AndL) {
1541 Node* o2 = n->in(2);
1542 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1543 return true;
1544 }
1545 }
1546 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1547 return true;
1548 }
1549 return false;
1550 }
1551
1552 %}
1553
1554 //----------ENCODING BLOCK-----------------------------------------------------
1555 // This block specifies the encoding classes used by the compiler to output
1556 // byte streams. Encoding classes generate functions which are called by
1557 // Machine Instruction Nodes in order to generate the bit encoding of the
1558 // instruction. Operands specify their base encoding interface with the
1559 // interface keyword. There are currently supported four interfaces,
1560 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1561 // operand to generate a function which returns its register number when
1562 // queried. CONST_INTER causes an operand to generate a function which
1563 // returns the value of the constant when queried. MEMORY_INTER causes an
1564 // operand to generate four functions which return the Base Register, the
1565 // Index Register, the Scale Value, and the Offset Value of the operand when
1566 // queried. COND_INTER causes an operand to generate six functions which
1567 // return the encoding code (ie - encoding bits for the instruction)
1568 // associated with each basic boolean condition for a conditional instruction.
1569 // Instructions specify two basic values for encoding. They use the
1570 // ins_encode keyword to specify their encoding class (which must be one of
1571 // the class names specified in the encoding block), and they use the
1572 // opcode keyword to specify, in order, their primary, secondary, and
1573 // tertiary opcode. Only the opcode sections which a particular instruction
1574 // needs for encoding need to be specified.
1575 encode %{
1576 // Build emit functions for each basic byte or larger field in the intel
1577 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1578 // code in the enc_class source block. Emit functions will live in the
1579 // main source block for now. In future, we can generalize this by
1580 // adding a syntax that specifies the sizes of fields in an order,
1581 // so that the adlc can build the emit functions automagically
1582
1583 // Emit primary opcode
1584 enc_class OpcP %{
1585 emit_opcode(cbuf, $primary);
1586 %}
1587
1588 // Emit secondary opcode
1589 enc_class OpcS %{
1590 emit_opcode(cbuf, $secondary);
1591 %}
1592
1593 // Emit opcode directly
1594 enc_class Opcode(immI d8) %{
1595 emit_opcode(cbuf, $d8$$constant);
1596 %}
1597
1598 enc_class SizePrefix %{
1599 emit_opcode(cbuf,0x66);
1600 %}
1601
1602 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1603 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1604 %}
1605
1606 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1607 emit_opcode(cbuf,$opcode$$constant);
1608 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1609 %}
1610
1611 enc_class mov_r32_imm0( rRegI dst ) %{
1612 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1613 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1614 %}
1615
1616 enc_class cdq_enc %{
1617 // Full implementation of Java idiv and irem; checks for
1618 // special case as described in JVM spec., p.243 & p.271.
1619 //
1620 // normal case special case
1621 //
1622 // input : rax,: dividend min_int
1623 // reg: divisor -1
1624 //
1625 // output: rax,: quotient (= rax, idiv reg) min_int
1626 // rdx: remainder (= rax, irem reg) 0
1627 //
1628 // Code sequnce:
1629 //
1630 // 81 F8 00 00 00 80 cmp rax,80000000h
1631 // 0F 85 0B 00 00 00 jne normal_case
1632 // 33 D2 xor rdx,edx
1633 // 83 F9 FF cmp rcx,0FFh
1634 // 0F 84 03 00 00 00 je done
1635 // normal_case:
1636 // 99 cdq
1637 // F7 F9 idiv rax,ecx
1638 // done:
1639 //
1640 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1641 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1642 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1643 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1644 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1645 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1646 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1647 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1648 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1649 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1651 // normal_case:
1652 emit_opcode(cbuf,0x99); // cdq
1653 // idiv (note: must be emitted by the user of this rule)
1654 // normal:
1655 %}
1656
1657 // Dense encoding for older common ops
1658 enc_class Opc_plus(immI opcode, rRegI reg) %{
1659 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1660 %}
1661
1662
1663 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1664 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1665 // Check for 8-bit immediate, and set sign extend bit in opcode
1666 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1667 emit_opcode(cbuf, $primary | 0x02);
1668 }
1669 else { // If 32-bit immediate
1670 emit_opcode(cbuf, $primary);
1671 }
1672 %}
1673
1674 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1675 // Emit primary opcode and set sign-extend bit
1676 // Check for 8-bit immediate, and set sign extend bit in opcode
1677 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1678 emit_opcode(cbuf, $primary | 0x02); }
1679 else { // If 32-bit immediate
1680 emit_opcode(cbuf, $primary);
1681 }
1682 // Emit r/m byte with secondary opcode, after primary opcode.
1683 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1684 %}
1685
1686 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1687 // Check for 8-bit immediate, and set sign extend bit in opcode
1688 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1689 $$$emit8$imm$$constant;
1690 }
1691 else { // If 32-bit immediate
1692 // Output immediate
1693 $$$emit32$imm$$constant;
1694 }
1695 %}
1696
1697 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1698 // Emit primary opcode and set sign-extend bit
1699 // Check for 8-bit immediate, and set sign extend bit in opcode
1700 int con = (int)$imm$$constant; // Throw away top bits
1701 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1702 // Emit r/m byte with secondary opcode, after primary opcode.
1703 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1704 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1705 else emit_d32(cbuf,con);
1706 %}
1707
1708 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1709 // Emit primary opcode and set sign-extend bit
1710 // Check for 8-bit immediate, and set sign extend bit in opcode
1711 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1712 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1713 // Emit r/m byte with tertiary opcode, after primary opcode.
1714 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1715 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1716 else emit_d32(cbuf,con);
1717 %}
1718
1719 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1720 emit_cc(cbuf, $secondary, $dst$$reg );
1721 %}
1722
1723 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1724 int destlo = $dst$$reg;
1725 int desthi = HIGH_FROM_LOW(destlo);
1726 // bswap lo
1727 emit_opcode(cbuf, 0x0F);
1728 emit_cc(cbuf, 0xC8, destlo);
1729 // bswap hi
1730 emit_opcode(cbuf, 0x0F);
1731 emit_cc(cbuf, 0xC8, desthi);
1732 // xchg lo and hi
1733 emit_opcode(cbuf, 0x87);
1734 emit_rm(cbuf, 0x3, destlo, desthi);
1735 %}
1736
1737 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1738 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1739 %}
1740
1741 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1742 $$$emit8$primary;
1743 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1744 %}
1745
1746 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1747 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1748 emit_d8(cbuf, op >> 8 );
1749 emit_d8(cbuf, op & 255);
1750 %}
1751
1752 // emulate a CMOV with a conditional branch around a MOV
1753 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1754 // Invert sense of branch from sense of CMOV
1755 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1756 emit_d8( cbuf, $brOffs$$constant );
1757 %}
1758
1759 enc_class enc_PartialSubtypeCheck( ) %{
1760 Register Redi = as_Register(EDI_enc); // result register
1761 Register Reax = as_Register(EAX_enc); // super class
1762 Register Recx = as_Register(ECX_enc); // killed
1763 Register Resi = as_Register(ESI_enc); // sub class
1764 Label miss;
1765
1766 MacroAssembler _masm(&cbuf);
1767 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1768 NULL, &miss,
1769 /*set_cond_codes:*/ true);
1770 if ($primary) {
1771 __ xorptr(Redi, Redi);
1772 }
1773 __ bind(miss);
1774 %}
1775
1776 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1777 MacroAssembler masm(&cbuf);
1778 int start = masm.offset();
1779 if (UseSSE >= 2) {
1780 if (VerifyFPU) {
1781 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1782 }
1783 } else {
1784 // External c_calling_convention expects the FPU stack to be 'clean'.
1785 // Compiled code leaves it dirty. Do cleanup now.
1786 masm.empty_FPU_stack();
1787 }
1788 if (sizeof_FFree_Float_Stack_All == -1) {
1789 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1790 } else {
1791 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1792 }
1793 %}
1794
1795 enc_class Verify_FPU_For_Leaf %{
1796 if( VerifyFPU ) {
1797 MacroAssembler masm(&cbuf);
1798 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1799 }
1800 %}
1801
1802 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1803 // This is the instruction starting address for relocation info.
1804 cbuf.set_insts_mark();
1805 $$$emit8$primary;
1806 // CALL directly to the runtime
1807 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1808 runtime_call_Relocation::spec(), RELOC_IMM32 );
1809
1810 if (UseSSE >= 2) {
1811 MacroAssembler _masm(&cbuf);
1812 BasicType rt = tf()->return_type();
1813
1814 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1815 // A C runtime call where the return value is unused. In SSE2+
1816 // mode the result needs to be removed from the FPU stack. It's
1817 // likely that this function call could be removed by the
1818 // optimizer if the C function is a pure function.
1819 __ ffree(0);
1820 } else if (rt == T_FLOAT) {
1821 __ lea(rsp, Address(rsp, -4));
1822 __ fstp_s(Address(rsp, 0));
1823 __ movflt(xmm0, Address(rsp, 0));
1824 __ lea(rsp, Address(rsp, 4));
1825 } else if (rt == T_DOUBLE) {
1826 __ lea(rsp, Address(rsp, -8));
1827 __ fstp_d(Address(rsp, 0));
1828 __ movdbl(xmm0, Address(rsp, 0));
1829 __ lea(rsp, Address(rsp, 8));
1830 }
1831 }
1832 %}
1833
1834
1835 enc_class pre_call_resets %{
1836 // If method sets FPU control word restore it here
1837 debug_only(int off0 = cbuf.insts_size());
1838 if (ra_->C->in_24_bit_fp_mode()) {
1839 MacroAssembler _masm(&cbuf);
1840 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1841 }
1842 if (ra_->C->max_vector_size() > 16) {
1843 // Clear upper bits of YMM registers when current compiled code uses
1844 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1845 MacroAssembler _masm(&cbuf);
1846 __ vzeroupper();
1847 }
1848 debug_only(int off1 = cbuf.insts_size());
1849 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1850 %}
1851
1852 enc_class post_call_FPU %{
1853 // If method sets FPU control word do it here also
1854 if (Compile::current()->in_24_bit_fp_mode()) {
1855 MacroAssembler masm(&cbuf);
1856 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1857 }
1858 %}
1859
1860 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1861 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1862 // who we intended to call.
1863 cbuf.set_insts_mark();
1864 $$$emit8$primary;
1865 if (!_method) {
1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1867 runtime_call_Relocation::spec(), RELOC_IMM32 );
1868 } else if (_optimized_virtual) {
1869 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1870 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1871 } else {
1872 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1873 static_call_Relocation::spec(), RELOC_IMM32 );
1874 }
1875 if (_method) { // Emit stub for static call.
1876 CompiledStaticCall::emit_to_interp_stub(cbuf);
1877 }
1878 %}
1879
1880 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1881 MacroAssembler _masm(&cbuf);
1882 __ ic_call((address)$meth$$method);
1883 %}
1884
1885 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1886 int disp = in_bytes(Method::from_compiled_offset());
1887 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1888
1889 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1890 cbuf.set_insts_mark();
1891 $$$emit8$primary;
1892 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1893 emit_d8(cbuf, disp); // Displacement
1894
1895 %}
1896
1897 // Following encoding is no longer used, but may be restored if calling
1898 // convention changes significantly.
1899 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1900 //
1901 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1902 // // int ic_reg = Matcher::inline_cache_reg();
1903 // // int ic_encode = Matcher::_regEncode[ic_reg];
1904 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1905 // // int imo_encode = Matcher::_regEncode[imo_reg];
1906 //
1907 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1908 // // // so we load it immediately before the call
1909 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1910 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1911 //
1912 // // xor rbp,ebp
1913 // emit_opcode(cbuf, 0x33);
1914 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1915 //
1916 // // CALL to interpreter.
1917 // cbuf.set_insts_mark();
1918 // $$$emit8$primary;
1919 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1920 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1921 // %}
1922
1923 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1924 $$$emit8$primary;
1925 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1926 $$$emit8$shift$$constant;
1927 %}
1928
1929 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1930 // Load immediate does not have a zero or sign extended version
1931 // for 8-bit immediates
1932 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1933 $$$emit32$src$$constant;
1934 %}
1935
1936 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1937 // Load immediate does not have a zero or sign extended version
1938 // for 8-bit immediates
1939 emit_opcode(cbuf, $primary + $dst$$reg);
1940 $$$emit32$src$$constant;
1941 %}
1942
1943 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1944 // Load immediate does not have a zero or sign extended version
1945 // for 8-bit immediates
1946 int dst_enc = $dst$$reg;
1947 int src_con = $src$$constant & 0x0FFFFFFFFL;
1948 if (src_con == 0) {
1949 // xor dst, dst
1950 emit_opcode(cbuf, 0x33);
1951 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1952 } else {
1953 emit_opcode(cbuf, $primary + dst_enc);
1954 emit_d32(cbuf, src_con);
1955 }
1956 %}
1957
1958 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1959 // Load immediate does not have a zero or sign extended version
1960 // for 8-bit immediates
1961 int dst_enc = $dst$$reg + 2;
1962 int src_con = ((julong)($src$$constant)) >> 32;
1963 if (src_con == 0) {
1964 // xor dst, dst
1965 emit_opcode(cbuf, 0x33);
1966 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1967 } else {
1968 emit_opcode(cbuf, $primary + dst_enc);
1969 emit_d32(cbuf, src_con);
1970 }
1971 %}
1972
1973
1974 // Encode a reg-reg copy. If it is useless, then empty encoding.
1975 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1976 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1977 %}
1978
1979 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1980 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1981 %}
1982
1983 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1988 $$$emit8$primary;
1989 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1990 %}
1991
1992 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
1993 $$$emit8$secondary;
1994 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1995 %}
1996
1997 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
1998 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1999 %}
2000
2001 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003 %}
2004
2005 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2006 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2007 %}
2008
2009 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2010 // Output immediate
2011 $$$emit32$src$$constant;
2012 %}
2013
2014 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2015 // Output Float immediate bits
2016 jfloat jf = $src$$constant;
2017 int jf_as_bits = jint_cast( jf );
2018 emit_d32(cbuf, jf_as_bits);
2019 %}
2020
2021 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2022 // Output Float immediate bits
2023 jfloat jf = $src$$constant;
2024 int jf_as_bits = jint_cast( jf );
2025 emit_d32(cbuf, jf_as_bits);
2026 %}
2027
2028 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2029 // Output immediate
2030 $$$emit16$src$$constant;
2031 %}
2032
2033 enc_class Con_d32(immI src) %{
2034 emit_d32(cbuf,$src$$constant);
2035 %}
2036
2037 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2038 // Output immediate memory reference
2039 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2040 emit_d32(cbuf, 0x00);
2041 %}
2042
2043 enc_class lock_prefix( ) %{
2044 if( os::is_MP() )
2045 emit_opcode(cbuf,0xF0); // [Lock]
2046 %}
2047
2048 // Cmp-xchg long value.
2049 // Note: we need to swap rbx, and rcx before and after the
2050 // cmpxchg8 instruction because the instruction uses
2051 // rcx as the high order word of the new value to store but
2052 // our register encoding uses rbx,.
2053 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2054
2055 // XCHG rbx,ecx
2056 emit_opcode(cbuf,0x87);
2057 emit_opcode(cbuf,0xD9);
2058 // [Lock]
2059 if( os::is_MP() )
2060 emit_opcode(cbuf,0xF0);
2061 // CMPXCHG8 [Eptr]
2062 emit_opcode(cbuf,0x0F);
2063 emit_opcode(cbuf,0xC7);
2064 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2065 // XCHG rbx,ecx
2066 emit_opcode(cbuf,0x87);
2067 emit_opcode(cbuf,0xD9);
2068 %}
2069
2070 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2071 // [Lock]
2072 if( os::is_MP() )
2073 emit_opcode(cbuf,0xF0);
2074
2075 // CMPXCHG [Eptr]
2076 emit_opcode(cbuf,0x0F);
2077 emit_opcode(cbuf,0xB1);
2078 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2079 %}
2080
2081 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2082 int res_encoding = $res$$reg;
2083
2084 // MOV res,0
2085 emit_opcode( cbuf, 0xB8 + res_encoding);
2086 emit_d32( cbuf, 0 );
2087 // JNE,s fail
2088 emit_opcode(cbuf,0x75);
2089 emit_d8(cbuf, 5 );
2090 // MOV res,1
2091 emit_opcode( cbuf, 0xB8 + res_encoding);
2092 emit_d32( cbuf, 1 );
2093 // fail:
2094 %}
2095
2096 enc_class set_instruction_start( ) %{
2097 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2098 %}
2099
2100 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2101 int reg_encoding = $ereg$$reg;
2102 int base = $mem$$base;
2103 int index = $mem$$index;
2104 int scale = $mem$$scale;
2105 int displace = $mem$$disp;
2106 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2107 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2108 %}
2109
2110 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2111 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2112 int base = $mem$$base;
2113 int index = $mem$$index;
2114 int scale = $mem$$scale;
2115 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2116 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2117 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2118 %}
2119
2120 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2121 int r1, r2;
2122 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2123 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,$tertiary);
2126 emit_rm(cbuf, 0x3, r1, r2);
2127 emit_d8(cbuf,$cnt$$constant);
2128 emit_d8(cbuf,$primary);
2129 emit_rm(cbuf, 0x3, $secondary, r1);
2130 emit_d8(cbuf,$cnt$$constant);
2131 %}
2132
2133 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2134 emit_opcode( cbuf, 0x8B ); // Move
2135 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2136 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2137 emit_d8(cbuf,$primary);
2138 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2139 emit_d8(cbuf,$cnt$$constant-32);
2140 }
2141 emit_d8(cbuf,$primary);
2142 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2143 emit_d8(cbuf,31);
2144 %}
2145
2146 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2147 int r1, r2;
2148 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2149 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2150
2151 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2152 emit_rm(cbuf, 0x3, r1, r2);
2153 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2154 emit_opcode(cbuf,$primary);
2155 emit_rm(cbuf, 0x3, $secondary, r1);
2156 emit_d8(cbuf,$cnt$$constant-32);
2157 }
2158 emit_opcode(cbuf,0x33); // XOR r2,r2
2159 emit_rm(cbuf, 0x3, r2, r2);
2160 %}
2161
2162 // Clone of RegMem but accepts an extra parameter to access each
2163 // half of a double in memory; it never needs relocation info.
2164 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2165 emit_opcode(cbuf,$opcode$$constant);
2166 int reg_encoding = $rm_reg$$reg;
2167 int base = $mem$$base;
2168 int index = $mem$$index;
2169 int scale = $mem$$scale;
2170 int displace = $mem$$disp + $disp_for_half$$constant;
2171 relocInfo::relocType disp_reloc = relocInfo::none;
2172 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2173 %}
2174
2175 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2176 //
2177 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2178 // and it never needs relocation information.
2179 // Frequently used to move data between FPU's Stack Top and memory.
2180 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2181 int rm_byte_opcode = $rm_opcode$$constant;
2182 int base = $mem$$base;
2183 int index = $mem$$index;
2184 int scale = $mem$$scale;
2185 int displace = $mem$$disp;
2186 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2187 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2188 %}
2189
2190 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2191 int rm_byte_opcode = $rm_opcode$$constant;
2192 int base = $mem$$base;
2193 int index = $mem$$index;
2194 int scale = $mem$$scale;
2195 int displace = $mem$$disp;
2196 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2197 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2198 %}
2199
2200 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2201 int reg_encoding = $dst$$reg;
2202 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2203 int index = 0x04; // 0x04 indicates no index
2204 int scale = 0x00; // 0x00 indicates no scale
2205 int displace = $src1$$constant; // 0x00 indicates no displacement
2206 relocInfo::relocType disp_reloc = relocInfo::none;
2207 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2208 %}
2209
2210 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2211 // Compare dst,src
2212 emit_opcode(cbuf,0x3B);
2213 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2214 // jmp dst < src around move
2215 emit_opcode(cbuf,0x7C);
2216 emit_d8(cbuf,2);
2217 // move dst,src
2218 emit_opcode(cbuf,0x8B);
2219 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2220 %}
2221
2222 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2223 // Compare dst,src
2224 emit_opcode(cbuf,0x3B);
2225 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2226 // jmp dst > src around move
2227 emit_opcode(cbuf,0x7F);
2228 emit_d8(cbuf,2);
2229 // move dst,src
2230 emit_opcode(cbuf,0x8B);
2231 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2232 %}
2233
2234 enc_class enc_FPR_store(memory mem, regDPR src) %{
2235 // If src is FPR1, we can just FST to store it.
2236 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2237 int reg_encoding = 0x2; // Just store
2238 int base = $mem$$base;
2239 int index = $mem$$index;
2240 int scale = $mem$$scale;
2241 int displace = $mem$$disp;
2242 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2243 if( $src$$reg != FPR1L_enc ) {
2244 reg_encoding = 0x3; // Store & pop
2245 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2246 emit_d8( cbuf, 0xC0-1+$src$$reg );
2247 }
2248 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2249 emit_opcode(cbuf,$primary);
2250 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2251 %}
2252
2253 enc_class neg_reg(rRegI dst) %{
2254 // NEG $dst
2255 emit_opcode(cbuf,0xF7);
2256 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2257 %}
2258
2259 enc_class setLT_reg(eCXRegI dst) %{
2260 // SETLT $dst
2261 emit_opcode(cbuf,0x0F);
2262 emit_opcode(cbuf,0x9C);
2263 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2264 %}
2265
2266 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2267 int tmpReg = $tmp$$reg;
2268
2269 // SUB $p,$q
2270 emit_opcode(cbuf,0x2B);
2271 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2272 // SBB $tmp,$tmp
2273 emit_opcode(cbuf,0x1B);
2274 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2275 // AND $tmp,$y
2276 emit_opcode(cbuf,0x23);
2277 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2278 // ADD $p,$tmp
2279 emit_opcode(cbuf,0x03);
2280 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2281 %}
2282
2283 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2284 int tmpReg = $tmp$$reg;
2285
2286 // SUB $p,$q
2287 emit_opcode(cbuf,0x2B);
2288 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2289 // SBB $tmp,$tmp
2290 emit_opcode(cbuf,0x1B);
2291 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2292 // AND $tmp,$y
2293 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2294 emit_opcode(cbuf,0x23);
2295 int reg_encoding = tmpReg;
2296 int base = $mem$$base;
2297 int index = $mem$$index;
2298 int scale = $mem$$scale;
2299 int displace = $mem$$disp;
2300 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2301 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2302 // ADD $p,$tmp
2303 emit_opcode(cbuf,0x03);
2304 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2305 %}
2306
2307 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2308 // TEST shift,32
2309 emit_opcode(cbuf,0xF7);
2310 emit_rm(cbuf, 0x3, 0, ECX_enc);
2311 emit_d32(cbuf,0x20);
2312 // JEQ,s small
2313 emit_opcode(cbuf, 0x74);
2314 emit_d8(cbuf, 0x04);
2315 // MOV $dst.hi,$dst.lo
2316 emit_opcode( cbuf, 0x8B );
2317 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2318 // CLR $dst.lo
2319 emit_opcode(cbuf, 0x33);
2320 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2321 // small:
2322 // SHLD $dst.hi,$dst.lo,$shift
2323 emit_opcode(cbuf,0x0F);
2324 emit_opcode(cbuf,0xA5);
2325 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2326 // SHL $dst.lo,$shift"
2327 emit_opcode(cbuf,0xD3);
2328 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2329 %}
2330
2331 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2332 // TEST shift,32
2333 emit_opcode(cbuf,0xF7);
2334 emit_rm(cbuf, 0x3, 0, ECX_enc);
2335 emit_d32(cbuf,0x20);
2336 // JEQ,s small
2337 emit_opcode(cbuf, 0x74);
2338 emit_d8(cbuf, 0x04);
2339 // MOV $dst.lo,$dst.hi
2340 emit_opcode( cbuf, 0x8B );
2341 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2342 // CLR $dst.hi
2343 emit_opcode(cbuf, 0x33);
2344 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2345 // small:
2346 // SHRD $dst.lo,$dst.hi,$shift
2347 emit_opcode(cbuf,0x0F);
2348 emit_opcode(cbuf,0xAD);
2349 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2350 // SHR $dst.hi,$shift"
2351 emit_opcode(cbuf,0xD3);
2352 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2353 %}
2354
2355 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2356 // TEST shift,32
2357 emit_opcode(cbuf,0xF7);
2358 emit_rm(cbuf, 0x3, 0, ECX_enc);
2359 emit_d32(cbuf,0x20);
2360 // JEQ,s small
2361 emit_opcode(cbuf, 0x74);
2362 emit_d8(cbuf, 0x05);
2363 // MOV $dst.lo,$dst.hi
2364 emit_opcode( cbuf, 0x8B );
2365 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2366 // SAR $dst.hi,31
2367 emit_opcode(cbuf, 0xC1);
2368 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2369 emit_d8(cbuf, 0x1F );
2370 // small:
2371 // SHRD $dst.lo,$dst.hi,$shift
2372 emit_opcode(cbuf,0x0F);
2373 emit_opcode(cbuf,0xAD);
2374 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2375 // SAR $dst.hi,$shift"
2376 emit_opcode(cbuf,0xD3);
2377 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2378 %}
2379
2380
2381 // ----------------- Encodings for floating point unit -----------------
2382 // May leave result in FPU-TOS or FPU reg depending on opcodes
2383 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2384 $$$emit8$primary;
2385 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2386 %}
2387
2388 // Pop argument in FPR0 with FSTP ST(0)
2389 enc_class PopFPU() %{
2390 emit_opcode( cbuf, 0xDD );
2391 emit_d8( cbuf, 0xD8 );
2392 %}
2393
2394 // !!!!! equivalent to Pop_Reg_F
2395 enc_class Pop_Reg_DPR( regDPR dst ) %{
2396 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2397 emit_d8( cbuf, 0xD8+$dst$$reg );
2398 %}
2399
2400 enc_class Push_Reg_DPR( regDPR dst ) %{
2401 emit_opcode( cbuf, 0xD9 );
2402 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2403 %}
2404
2405 enc_class strictfp_bias1( regDPR dst ) %{
2406 emit_opcode( cbuf, 0xDB ); // FLD m80real
2407 emit_opcode( cbuf, 0x2D );
2408 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2409 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2410 emit_opcode( cbuf, 0xC8+$dst$$reg );
2411 %}
2412
2413 enc_class strictfp_bias2( regDPR dst ) %{
2414 emit_opcode( cbuf, 0xDB ); // FLD m80real
2415 emit_opcode( cbuf, 0x2D );
2416 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2417 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2418 emit_opcode( cbuf, 0xC8+$dst$$reg );
2419 %}
2420
2421 // Special case for moving an integer register to a stack slot.
2422 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2423 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2424 %}
2425
2426 // Special case for moving a register to a stack slot.
2427 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2428 // Opcode already emitted
2429 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2430 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2431 emit_d32(cbuf, $dst$$disp); // Displacement
2432 %}
2433
2434 // Push the integer in stackSlot 'src' onto FP-stack
2435 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2436 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2437 %}
2438
2439 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2440 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2441 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2442 %}
2443
2444 // Same as Pop_Mem_F except for opcode
2445 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2446 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2447 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2448 %}
2449
2450 enc_class Pop_Reg_FPR( regFPR dst ) %{
2451 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2452 emit_d8( cbuf, 0xD8+$dst$$reg );
2453 %}
2454
2455 enc_class Push_Reg_FPR( regFPR dst ) %{
2456 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2457 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2458 %}
2459
2460 // Push FPU's float to a stack-slot, and pop FPU-stack
2461 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2462 int pop = 0x02;
2463 if ($src$$reg != FPR1L_enc) {
2464 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2465 emit_d8( cbuf, 0xC0-1+$src$$reg );
2466 pop = 0x03;
2467 }
2468 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2469 %}
2470
2471 // Push FPU's double to a stack-slot, and pop FPU-stack
2472 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2473 int pop = 0x02;
2474 if ($src$$reg != FPR1L_enc) {
2475 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2476 emit_d8( cbuf, 0xC0-1+$src$$reg );
2477 pop = 0x03;
2478 }
2479 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2480 %}
2481
2482 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2483 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2484 int pop = 0xD0 - 1; // -1 since we skip FLD
2485 if ($src$$reg != FPR1L_enc) {
2486 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2487 emit_d8( cbuf, 0xC0-1+$src$$reg );
2488 pop = 0xD8;
2489 }
2490 emit_opcode( cbuf, 0xDD );
2491 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2492 %}
2493
2494
2495 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2496 // load dst in FPR0
2497 emit_opcode( cbuf, 0xD9 );
2498 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2499 if ($src$$reg != FPR1L_enc) {
2500 // fincstp
2501 emit_opcode (cbuf, 0xD9);
2502 emit_opcode (cbuf, 0xF7);
2503 // swap src with FPR1:
2504 // FXCH FPR1 with src
2505 emit_opcode(cbuf, 0xD9);
2506 emit_d8(cbuf, 0xC8-1+$src$$reg );
2507 // fdecstp
2508 emit_opcode (cbuf, 0xD9);
2509 emit_opcode (cbuf, 0xF6);
2510 }
2511 %}
2512
2513 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2514 MacroAssembler _masm(&cbuf);
2515 __ subptr(rsp, 8);
2516 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2517 __ fld_d(Address(rsp, 0));
2518 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2519 __ fld_d(Address(rsp, 0));
2520 %}
2521
2522 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2523 MacroAssembler _masm(&cbuf);
2524 __ subptr(rsp, 4);
2525 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2526 __ fld_s(Address(rsp, 0));
2527 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2528 __ fld_s(Address(rsp, 0));
2529 %}
2530
2531 enc_class Push_ResultD(regD dst) %{
2532 MacroAssembler _masm(&cbuf);
2533 __ fstp_d(Address(rsp, 0));
2534 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2535 __ addptr(rsp, 8);
2536 %}
2537
2538 enc_class Push_ResultF(regF dst, immI d8) %{
2539 MacroAssembler _masm(&cbuf);
2540 __ fstp_s(Address(rsp, 0));
2541 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2542 __ addptr(rsp, $d8$$constant);
2543 %}
2544
2545 enc_class Push_SrcD(regD src) %{
2546 MacroAssembler _masm(&cbuf);
2547 __ subptr(rsp, 8);
2548 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2549 __ fld_d(Address(rsp, 0));
2550 %}
2551
2552 enc_class push_stack_temp_qword() %{
2553 MacroAssembler _masm(&cbuf);
2554 __ subptr(rsp, 8);
2555 %}
2556
2557 enc_class pop_stack_temp_qword() %{
2558 MacroAssembler _masm(&cbuf);
2559 __ addptr(rsp, 8);
2560 %}
2561
2562 enc_class push_xmm_to_fpr1(regD src) %{
2563 MacroAssembler _masm(&cbuf);
2564 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2565 __ fld_d(Address(rsp, 0));
2566 %}
2567
2568 enc_class Push_Result_Mod_DPR( regDPR src) %{
2569 if ($src$$reg != FPR1L_enc) {
2570 // fincstp
2571 emit_opcode (cbuf, 0xD9);
2572 emit_opcode (cbuf, 0xF7);
2573 // FXCH FPR1 with src
2574 emit_opcode(cbuf, 0xD9);
2575 emit_d8(cbuf, 0xC8-1+$src$$reg );
2576 // fdecstp
2577 emit_opcode (cbuf, 0xD9);
2578 emit_opcode (cbuf, 0xF6);
2579 }
2580 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2581 // // FSTP FPR$dst$$reg
2582 // emit_opcode( cbuf, 0xDD );
2583 // emit_d8( cbuf, 0xD8+$dst$$reg );
2584 %}
2585
2586 enc_class fnstsw_sahf_skip_parity() %{
2587 // fnstsw ax
2588 emit_opcode( cbuf, 0xDF );
2589 emit_opcode( cbuf, 0xE0 );
2590 // sahf
2591 emit_opcode( cbuf, 0x9E );
2592 // jnp ::skip
2593 emit_opcode( cbuf, 0x7B );
2594 emit_opcode( cbuf, 0x05 );
2595 %}
2596
2597 enc_class emitModDPR() %{
2598 // fprem must be iterative
2599 // :: loop
2600 // fprem
2601 emit_opcode( cbuf, 0xD9 );
2602 emit_opcode( cbuf, 0xF8 );
2603 // wait
2604 emit_opcode( cbuf, 0x9b );
2605 // fnstsw ax
2606 emit_opcode( cbuf, 0xDF );
2607 emit_opcode( cbuf, 0xE0 );
2608 // sahf
2609 emit_opcode( cbuf, 0x9E );
2610 // jp ::loop
2611 emit_opcode( cbuf, 0x0F );
2612 emit_opcode( cbuf, 0x8A );
2613 emit_opcode( cbuf, 0xF4 );
2614 emit_opcode( cbuf, 0xFF );
2615 emit_opcode( cbuf, 0xFF );
2616 emit_opcode( cbuf, 0xFF );
2617 %}
2618
2619 enc_class fpu_flags() %{
2620 // fnstsw_ax
2621 emit_opcode( cbuf, 0xDF);
2622 emit_opcode( cbuf, 0xE0);
2623 // test ax,0x0400
2624 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2625 emit_opcode( cbuf, 0xA9 );
2626 emit_d16 ( cbuf, 0x0400 );
2627 // // // This sequence works, but stalls for 12-16 cycles on PPro
2628 // // test rax,0x0400
2629 // emit_opcode( cbuf, 0xA9 );
2630 // emit_d32 ( cbuf, 0x00000400 );
2631 //
2632 // jz exit (no unordered comparison)
2633 emit_opcode( cbuf, 0x74 );
2634 emit_d8 ( cbuf, 0x02 );
2635 // mov ah,1 - treat as LT case (set carry flag)
2636 emit_opcode( cbuf, 0xB4 );
2637 emit_d8 ( cbuf, 0x01 );
2638 // sahf
2639 emit_opcode( cbuf, 0x9E);
2640 %}
2641
2642 enc_class cmpF_P6_fixup() %{
2643 // Fixup the integer flags in case comparison involved a NaN
2644 //
2645 // JNP exit (no unordered comparison, P-flag is set by NaN)
2646 emit_opcode( cbuf, 0x7B );
2647 emit_d8 ( cbuf, 0x03 );
2648 // MOV AH,1 - treat as LT case (set carry flag)
2649 emit_opcode( cbuf, 0xB4 );
2650 emit_d8 ( cbuf, 0x01 );
2651 // SAHF
2652 emit_opcode( cbuf, 0x9E);
2653 // NOP // target for branch to avoid branch to branch
2654 emit_opcode( cbuf, 0x90);
2655 %}
2656
2657 // fnstsw_ax();
2658 // sahf();
2659 // movl(dst, nan_result);
2660 // jcc(Assembler::parity, exit);
2661 // movl(dst, less_result);
2662 // jcc(Assembler::below, exit);
2663 // movl(dst, equal_result);
2664 // jcc(Assembler::equal, exit);
2665 // movl(dst, greater_result);
2666
2667 // less_result = 1;
2668 // greater_result = -1;
2669 // equal_result = 0;
2670 // nan_result = -1;
2671
2672 enc_class CmpF_Result(rRegI dst) %{
2673 // fnstsw_ax();
2674 emit_opcode( cbuf, 0xDF);
2675 emit_opcode( cbuf, 0xE0);
2676 // sahf
2677 emit_opcode( cbuf, 0x9E);
2678 // movl(dst, nan_result);
2679 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2680 emit_d32( cbuf, -1 );
2681 // jcc(Assembler::parity, exit);
2682 emit_opcode( cbuf, 0x7A );
2683 emit_d8 ( cbuf, 0x13 );
2684 // movl(dst, less_result);
2685 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2686 emit_d32( cbuf, -1 );
2687 // jcc(Assembler::below, exit);
2688 emit_opcode( cbuf, 0x72 );
2689 emit_d8 ( cbuf, 0x0C );
2690 // movl(dst, equal_result);
2691 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2692 emit_d32( cbuf, 0 );
2693 // jcc(Assembler::equal, exit);
2694 emit_opcode( cbuf, 0x74 );
2695 emit_d8 ( cbuf, 0x05 );
2696 // movl(dst, greater_result);
2697 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2698 emit_d32( cbuf, 1 );
2699 %}
2700
2701
2702 // Compare the longs and set flags
2703 // BROKEN! Do Not use as-is
2704 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2705 // CMP $src1.hi,$src2.hi
2706 emit_opcode( cbuf, 0x3B );
2707 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2708 // JNE,s done
2709 emit_opcode(cbuf,0x75);
2710 emit_d8(cbuf, 2 );
2711 // CMP $src1.lo,$src2.lo
2712 emit_opcode( cbuf, 0x3B );
2713 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2714 // done:
2715 %}
2716
2717 enc_class convert_int_long( regL dst, rRegI src ) %{
2718 // mov $dst.lo,$src
2719 int dst_encoding = $dst$$reg;
2720 int src_encoding = $src$$reg;
2721 encode_Copy( cbuf, dst_encoding , src_encoding );
2722 // mov $dst.hi,$src
2723 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2724 // sar $dst.hi,31
2725 emit_opcode( cbuf, 0xC1 );
2726 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2727 emit_d8(cbuf, 0x1F );
2728 %}
2729
2730 enc_class convert_long_double( eRegL src ) %{
2731 // push $src.hi
2732 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2733 // push $src.lo
2734 emit_opcode(cbuf, 0x50+$src$$reg );
2735 // fild 64-bits at [SP]
2736 emit_opcode(cbuf,0xdf);
2737 emit_d8(cbuf, 0x6C);
2738 emit_d8(cbuf, 0x24);
2739 emit_d8(cbuf, 0x00);
2740 // pop stack
2741 emit_opcode(cbuf, 0x83); // add SP, #8
2742 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2743 emit_d8(cbuf, 0x8);
2744 %}
2745
2746 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2747 // IMUL EDX:EAX,$src1
2748 emit_opcode( cbuf, 0xF7 );
2749 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2750 // SAR EDX,$cnt-32
2751 int shift_count = ((int)$cnt$$constant) - 32;
2752 if (shift_count > 0) {
2753 emit_opcode(cbuf, 0xC1);
2754 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2755 emit_d8(cbuf, shift_count);
2756 }
2757 %}
2758
2759 // this version doesn't have add sp, 8
2760 enc_class convert_long_double2( eRegL src ) %{
2761 // push $src.hi
2762 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2763 // push $src.lo
2764 emit_opcode(cbuf, 0x50+$src$$reg );
2765 // fild 64-bits at [SP]
2766 emit_opcode(cbuf,0xdf);
2767 emit_d8(cbuf, 0x6C);
2768 emit_d8(cbuf, 0x24);
2769 emit_d8(cbuf, 0x00);
2770 %}
2771
2772 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2773 // Basic idea: long = (long)int * (long)int
2774 // IMUL EDX:EAX, src
2775 emit_opcode( cbuf, 0xF7 );
2776 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2777 %}
2778
2779 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2780 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2781 // MUL EDX:EAX, src
2782 emit_opcode( cbuf, 0xF7 );
2783 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2784 %}
2785
2786 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2787 // Basic idea: lo(result) = lo(x_lo * y_lo)
2788 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2789 // MOV $tmp,$src.lo
2790 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2791 // IMUL $tmp,EDX
2792 emit_opcode( cbuf, 0x0F );
2793 emit_opcode( cbuf, 0xAF );
2794 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2795 // MOV EDX,$src.hi
2796 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2797 // IMUL EDX,EAX
2798 emit_opcode( cbuf, 0x0F );
2799 emit_opcode( cbuf, 0xAF );
2800 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2801 // ADD $tmp,EDX
2802 emit_opcode( cbuf, 0x03 );
2803 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2804 // MUL EDX:EAX,$src.lo
2805 emit_opcode( cbuf, 0xF7 );
2806 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2807 // ADD EDX,ESI
2808 emit_opcode( cbuf, 0x03 );
2809 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2810 %}
2811
2812 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2813 // Basic idea: lo(result) = lo(src * y_lo)
2814 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2815 // IMUL $tmp,EDX,$src
2816 emit_opcode( cbuf, 0x6B );
2817 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2818 emit_d8( cbuf, (int)$src$$constant );
2819 // MOV EDX,$src
2820 emit_opcode(cbuf, 0xB8 + EDX_enc);
2821 emit_d32( cbuf, (int)$src$$constant );
2822 // MUL EDX:EAX,EDX
2823 emit_opcode( cbuf, 0xF7 );
2824 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2825 // ADD EDX,ESI
2826 emit_opcode( cbuf, 0x03 );
2827 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2828 %}
2829
2830 enc_class long_div( eRegL src1, eRegL src2 ) %{
2831 // PUSH src1.hi
2832 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2833 // PUSH src1.lo
2834 emit_opcode(cbuf, 0x50+$src1$$reg );
2835 // PUSH src2.hi
2836 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2837 // PUSH src2.lo
2838 emit_opcode(cbuf, 0x50+$src2$$reg );
2839 // CALL directly to the runtime
2840 cbuf.set_insts_mark();
2841 emit_opcode(cbuf,0xE8); // Call into runtime
2842 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2843 // Restore stack
2844 emit_opcode(cbuf, 0x83); // add SP, #framesize
2845 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2846 emit_d8(cbuf, 4*4);
2847 %}
2848
2849 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2850 // PUSH src1.hi
2851 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2852 // PUSH src1.lo
2853 emit_opcode(cbuf, 0x50+$src1$$reg );
2854 // PUSH src2.hi
2855 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2856 // PUSH src2.lo
2857 emit_opcode(cbuf, 0x50+$src2$$reg );
2858 // CALL directly to the runtime
2859 cbuf.set_insts_mark();
2860 emit_opcode(cbuf,0xE8); // Call into runtime
2861 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2862 // Restore stack
2863 emit_opcode(cbuf, 0x83); // add SP, #framesize
2864 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2865 emit_d8(cbuf, 4*4);
2866 %}
2867
2868 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2869 // MOV $tmp,$src.lo
2870 emit_opcode(cbuf, 0x8B);
2871 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2872 // OR $tmp,$src.hi
2873 emit_opcode(cbuf, 0x0B);
2874 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2875 %}
2876
2877 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2878 // CMP $src1.lo,$src2.lo
2879 emit_opcode( cbuf, 0x3B );
2880 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2881 // JNE,s skip
2882 emit_cc(cbuf, 0x70, 0x5);
2883 emit_d8(cbuf,2);
2884 // CMP $src1.hi,$src2.hi
2885 emit_opcode( cbuf, 0x3B );
2886 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2887 %}
2888
2889 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2890 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2891 emit_opcode( cbuf, 0x3B );
2892 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2893 // MOV $tmp,$src1.hi
2894 emit_opcode( cbuf, 0x8B );
2895 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2896 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2897 emit_opcode( cbuf, 0x1B );
2898 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2899 %}
2900
2901 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2902 // XOR $tmp,$tmp
2903 emit_opcode(cbuf,0x33); // XOR
2904 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2905 // CMP $tmp,$src.lo
2906 emit_opcode( cbuf, 0x3B );
2907 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2908 // SBB $tmp,$src.hi
2909 emit_opcode( cbuf, 0x1B );
2910 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2911 %}
2912
2913 // Sniff, sniff... smells like Gnu Superoptimizer
2914 enc_class neg_long( eRegL dst ) %{
2915 emit_opcode(cbuf,0xF7); // NEG hi
2916 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2917 emit_opcode(cbuf,0xF7); // NEG lo
2918 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2919 emit_opcode(cbuf,0x83); // SBB hi,0
2920 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2921 emit_d8 (cbuf,0 );
2922 %}
2923
2924
2925 // Because the transitions from emitted code to the runtime
2926 // monitorenter/exit helper stubs are so slow it's critical that
2927 // we inline both the stack-locking fast-path and the inflated fast path.
2928 //
2929 // See also: cmpFastLock and cmpFastUnlock.
2930 //
2931 // What follows is a specialized inline transliteration of the code
2932 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2933 // another option would be to emit TrySlowEnter and TrySlowExit methods
2934 // at startup-time. These methods would accept arguments as
2935 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2936 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2937 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2938 // In practice, however, the # of lock sites is bounded and is usually small.
2939 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2940 // if the processor uses simple bimodal branch predictors keyed by EIP
2941 // Since the helper routines would be called from multiple synchronization
2942 // sites.
2943 //
2944 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2945 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2946 // to those specialized methods. That'd give us a mostly platform-independent
2947 // implementation that the JITs could optimize and inline at their pleasure.
2948 // Done correctly, the only time we'd need to cross to native could would be
2949 // to park() or unpark() threads. We'd also need a few more unsafe operators
2950 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2951 // (b) explicit barriers or fence operations.
2952 //
2953 // TODO:
2954 //
2955 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2956 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2957 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2958 // the lock operators would typically be faster than reifying Self.
2959 //
2960 // * Ideally I'd define the primitives as:
2961 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2962 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2963 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2964 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2965 // Furthermore the register assignments are overconstrained, possibly resulting in
2966 // sub-optimal code near the synchronization site.
2967 //
2968 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2969 // Alternately, use a better sp-proximity test.
2970 //
2971 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2972 // Either one is sufficient to uniquely identify a thread.
2973 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2974 //
2975 // * Intrinsify notify() and notifyAll() for the common cases where the
2976 // object is locked by the calling thread but the waitlist is empty.
2977 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2978 //
2979 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2980 // But beware of excessive branch density on AMD Opterons.
2981 //
2982 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2983 // or failure of the fast-path. If the fast-path fails then we pass
2984 // control to the slow-path, typically in C. In Fast_Lock and
2985 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2986 // will emit a conditional branch immediately after the node.
2987 // So we have branches to branches and lots of ICC.ZF games.
2988 // Instead, it might be better to have C2 pass a "FailureLabel"
2989 // into Fast_Lock and Fast_Unlock. In the case of success, control
2990 // will drop through the node. ICC.ZF is undefined at exit.
2991 // In the case of failure, the node will branch directly to the
2992 // FailureLabel
2993
2994
2995 // obj: object to lock
2996 // box: on-stack box address (displaced header location) - KILLED
2997 // rax,: tmp -- KILLED
2998 // scr: tmp -- KILLED
2999 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3000
3001 Register objReg = as_Register($obj$$reg);
3002 Register boxReg = as_Register($box$$reg);
3003 Register tmpReg = as_Register($tmp$$reg);
3004 Register scrReg = as_Register($scr$$reg);
3005
3006 // Ensure the register assignents are disjoint
3007 guarantee (objReg != boxReg, "") ;
3008 guarantee (objReg != tmpReg, "") ;
3009 guarantee (objReg != scrReg, "") ;
3010 guarantee (boxReg != tmpReg, "") ;
3011 guarantee (boxReg != scrReg, "") ;
3012 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3013
3014 MacroAssembler masm(&cbuf);
3015
3016 if (_counters != NULL) {
3017 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3018 }
3019 if (EmitSync & 1) {
3020 // set box->dhw = unused_mark (3)
3021 // Force all sync thru slow-path: slow_enter() and slow_exit()
3022 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3023 masm.cmpptr (rsp, (int32_t)0) ;
3024 } else
3025 if (EmitSync & 2) {
3026 Label DONE_LABEL ;
3027 if (UseBiasedLocking) {
3028 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3029 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3030 }
3031
3032 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3033 masm.orptr (tmpReg, 0x1);
3034 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3035 if (os::is_MP()) { masm.lock(); }
3036 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3037 masm.jcc(Assembler::equal, DONE_LABEL);
3038 // Recursive locking
3039 masm.subptr(tmpReg, rsp);
3040 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3041 masm.movptr(Address(boxReg, 0), tmpReg);
3042 masm.bind(DONE_LABEL) ;
3043 } else {
3044 // Possible cases that we'll encounter in fast_lock
3045 // ------------------------------------------------
3046 // * Inflated
3047 // -- unlocked
3048 // -- Locked
3049 // = by self
3050 // = by other
3051 // * biased
3052 // -- by Self
3053 // -- by other
3054 // * neutral
3055 // * stack-locked
3056 // -- by self
3057 // = sp-proximity test hits
3058 // = sp-proximity test generates false-negative
3059 // -- by other
3060 //
3061
3062 Label IsInflated, DONE_LABEL, PopDone ;
3063
3064 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3065 // order to reduce the number of conditional branches in the most common cases.
3066 // Beware -- there's a subtle invariant that fetch of the markword
3067 // at [FETCH], below, will never observe a biased encoding (*101b).
3068 // If this invariant is not held we risk exclusion (safety) failure.
3069 if (UseBiasedLocking && !UseOptoBiasInlining) {
3070 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3071 }
3072
3073 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3074 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3075 masm.jccb (Assembler::notZero, IsInflated) ;
3076
3077 // Attempt stack-locking ...
3078 masm.orptr (tmpReg, 0x1);
3079 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3080 if (os::is_MP()) { masm.lock(); }
3081 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3082 if (_counters != NULL) {
3083 masm.cond_inc32(Assembler::equal,
3084 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3085 }
3086 masm.jccb (Assembler::equal, DONE_LABEL);
3087
3088 // Recursive locking
3089 masm.subptr(tmpReg, rsp);
3090 masm.andptr(tmpReg, 0xFFFFF003 );
3091 masm.movptr(Address(boxReg, 0), tmpReg);
3092 if (_counters != NULL) {
3093 masm.cond_inc32(Assembler::equal,
3094 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3095 }
3096 masm.jmp (DONE_LABEL) ;
3097
3098 masm.bind (IsInflated) ;
3099
3100 // The object is inflated.
3101 //
3102 // TODO-FIXME: eliminate the ugly use of manifest constants:
3103 // Use markOopDesc::monitor_value instead of "2".
3104 // use markOop::unused_mark() instead of "3".
3105 // The tmpReg value is an objectMonitor reference ORed with
3106 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3107 // objectmonitor pointer by masking off the "2" bit or we can just
3108 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3109 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3110 //
3111 // I use the latter as it avoids AGI stalls.
3112 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3113 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3114 //
3115 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3116
3117 // boxReg refers to the on-stack BasicLock in the current frame.
3118 // We'd like to write:
3119 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3120 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3121 // additional latency as we have another ST in the store buffer that must drain.
3122
3123 if (EmitSync & 8192) {
3124 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3125 masm.get_thread (scrReg) ;
3126 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3127 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3128 if (os::is_MP()) { masm.lock(); }
3129 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3130 } else
3131 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3132 masm.movptr(scrReg, boxReg) ;
3133 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3134
3135 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3136 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3137 // prefetchw [eax + Offset(_owner)-2]
3138 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3139 }
3140
3141 if ((EmitSync & 64) == 0) {
3142 // Optimistic form: consider XORL tmpReg,tmpReg
3143 masm.movptr(tmpReg, NULL_WORD) ;
3144 } else {
3145 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3146 // Test-And-CAS instead of CAS
3147 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3148 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3149 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3150 }
3151
3152 // Appears unlocked - try to swing _owner from null to non-null.
3153 // Ideally, I'd manifest "Self" with get_thread and then attempt
3154 // to CAS the register containing Self into m->Owner.
3155 // But we don't have enough registers, so instead we can either try to CAS
3156 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3157 // we later store "Self" into m->Owner. Transiently storing a stack address
3158 // (rsp or the address of the box) into m->owner is harmless.
3159 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3160 if (os::is_MP()) { masm.lock(); }
3161 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3162 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3163 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3164 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3165 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3166 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3167
3168 // If the CAS fails we can either retry or pass control to the slow-path.
3169 // We use the latter tactic.
3170 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3171 // If the CAS was successful ...
3172 // Self has acquired the lock
3173 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3174 // Intentional fall-through into DONE_LABEL ...
3175 } else {
3176 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3177 masm.movptr(boxReg, tmpReg) ;
3178
3179 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3180 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3181 // prefetchw [eax + Offset(_owner)-2]
3182 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3183 }
3184
3185 if ((EmitSync & 64) == 0) {
3186 // Optimistic form
3187 masm.xorptr (tmpReg, tmpReg) ;
3188 } else {
3189 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3190 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3191 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3192 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3193 }
3194
3195 // Appears unlocked - try to swing _owner from null to non-null.
3196 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3197 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3198 masm.get_thread (scrReg) ;
3199 if (os::is_MP()) { masm.lock(); }
3200 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3201
3202 // If the CAS fails we can either retry or pass control to the slow-path.
3203 // We use the latter tactic.
3204 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3205 // If the CAS was successful ...
3206 // Self has acquired the lock
3207 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3208 // Intentional fall-through into DONE_LABEL ...
3209 }
3210
3211 // DONE_LABEL is a hot target - we'd really like to place it at the
3212 // start of cache line by padding with NOPs.
3213 // See the AMD and Intel software optimization manuals for the
3214 // most efficient "long" NOP encodings.
3215 // Unfortunately none of our alignment mechanisms suffice.
3216 masm.bind(DONE_LABEL);
3217
3218 // Avoid branch-to-branch on AMD processors
3219 // This appears to be superstition.
3220 if (EmitSync & 32) masm.nop() ;
3221
3222
3223 // At DONE_LABEL the icc ZFlag is set as follows ...
3224 // Fast_Unlock uses the same protocol.
3225 // ZFlag == 1 -> Success
3226 // ZFlag == 0 -> Failure - force control through the slow-path
3227 }
3228 %}
3229
3230 // obj: object to unlock
3231 // box: box address (displaced header location), killed. Must be EAX.
3232 // rbx,: killed tmp; cannot be obj nor box.
3233 //
3234 // Some commentary on balanced locking:
3235 //
3236 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3237 // Methods that don't have provably balanced locking are forced to run in the
3238 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3239 // The interpreter provides two properties:
3240 // I1: At return-time the interpreter automatically and quietly unlocks any
3241 // objects acquired the current activation (frame). Recall that the
3242 // interpreter maintains an on-stack list of locks currently held by
3243 // a frame.
3244 // I2: If a method attempts to unlock an object that is not held by the
3245 // the frame the interpreter throws IMSX.
3246 //
3247 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3248 // B() doesn't have provably balanced locking so it runs in the interpreter.
3249 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3250 // is still locked by A().
3251 //
3252 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3253 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3254 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3255 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3256
3257 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3258
3259 Register objReg = as_Register($obj$$reg);
3260 Register boxReg = as_Register($box$$reg);
3261 Register tmpReg = as_Register($tmp$$reg);
3262
3263 guarantee (objReg != boxReg, "") ;
3264 guarantee (objReg != tmpReg, "") ;
3265 guarantee (boxReg != tmpReg, "") ;
3266 guarantee (boxReg == as_Register(EAX_enc), "") ;
3267 MacroAssembler masm(&cbuf);
3268
3269 if (EmitSync & 4) {
3270 // Disable - inhibit all inlining. Force control through the slow-path
3271 masm.cmpptr (rsp, 0) ;
3272 } else
3273 if (EmitSync & 8) {
3274 Label DONE_LABEL ;
3275 if (UseBiasedLocking) {
3276 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3277 }
3278 // classic stack-locking code ...
3279 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3280 masm.testptr(tmpReg, tmpReg) ;
3281 masm.jcc (Assembler::zero, DONE_LABEL) ;
3282 if (os::is_MP()) { masm.lock(); }
3283 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3284 masm.bind(DONE_LABEL);
3285 } else {
3286 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3287
3288 // Critically, the biased locking test must have precedence over
3289 // and appear before the (box->dhw == 0) recursive stack-lock test.
3290 if (UseBiasedLocking && !UseOptoBiasInlining) {
3291 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3292 }
3293
3294 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3295 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3296 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3297
3298 masm.testptr(tmpReg, 0x02) ; // Inflated?
3299 masm.jccb (Assembler::zero, Stacked) ;
3300
3301 masm.bind (Inflated) ;
3302 // It's inflated.
3303 // Despite our balanced locking property we still check that m->_owner == Self
3304 // as java routines or native JNI code called by this thread might
3305 // have released the lock.
3306 // Refer to the comments in synchronizer.cpp for how we might encode extra
3307 // state in _succ so we can avoid fetching EntryList|cxq.
3308 //
3309 // I'd like to add more cases in fast_lock() and fast_unlock() --
3310 // such as recursive enter and exit -- but we have to be wary of
3311 // I$ bloat, T$ effects and BP$ effects.
3312 //
3313 // If there's no contention try a 1-0 exit. That is, exit without
3314 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3315 // we detect and recover from the race that the 1-0 exit admits.
3316 //
3317 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3318 // before it STs null into _owner, releasing the lock. Updates
3319 // to data protected by the critical section must be visible before
3320 // we drop the lock (and thus before any other thread could acquire
3321 // the lock and observe the fields protected by the lock).
3322 // IA32's memory-model is SPO, so STs are ordered with respect to
3323 // each other and there's no need for an explicit barrier (fence).
3324 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3325
3326 masm.get_thread (boxReg) ;
3327 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3328 // prefetchw [ebx + Offset(_owner)-2]
3329 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3330 }
3331
3332 // Note that we could employ various encoding schemes to reduce
3333 // the number of loads below (currently 4) to just 2 or 3.
3334 // Refer to the comments in synchronizer.cpp.
3335 // In practice the chain of fetches doesn't seem to impact performance, however.
3336 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3337 // Attempt to reduce branch density - AMD's branch predictor.
3338 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3339 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3340 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3341 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3342 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3343 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3344 masm.jmpb (DONE_LABEL) ;
3345 } else {
3346 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3347 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3348 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3349 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3350 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3351 masm.jccb (Assembler::notZero, CheckSucc) ;
3352 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3353 masm.jmpb (DONE_LABEL) ;
3354 }
3355
3356 // The Following code fragment (EmitSync & 65536) improves the performance of
3357 // contended applications and contended synchronization microbenchmarks.
3358 // Unfortunately the emission of the code - even though not executed - causes regressions
3359 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3360 // with an equal number of never-executed NOPs results in the same regression.
3361 // We leave it off by default.
3362
3363 if ((EmitSync & 65536) != 0) {
3364 Label LSuccess, LGoSlowPath ;
3365
3366 masm.bind (CheckSucc) ;
3367
3368 // Optional pre-test ... it's safe to elide this
3369 if ((EmitSync & 16) == 0) {
3370 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3371 masm.jccb (Assembler::zero, LGoSlowPath) ;
3372 }
3373
3374 // We have a classic Dekker-style idiom:
3375 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3376 // There are a number of ways to implement the barrier:
3377 // (1) lock:andl &m->_owner, 0
3378 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3379 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3380 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3381 // (2) If supported, an explicit MFENCE is appealing.
3382 // In older IA32 processors MFENCE is slower than lock:add or xchg
3383 // particularly if the write-buffer is full as might be the case if
3384 // if stores closely precede the fence or fence-equivalent instruction.
3385 // In more modern implementations MFENCE appears faster, however.
3386 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3387 // The $lines underlying the top-of-stack should be in M-state.
3388 // The locked add instruction is serializing, of course.
3389 // (4) Use xchg, which is serializing
3390 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3391 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3392 // The integer condition codes will tell us if succ was 0.
3393 // Since _succ and _owner should reside in the same $line and
3394 // we just stored into _owner, it's likely that the $line
3395 // remains in M-state for the lock:orl.
3396 //
3397 // We currently use (3), although it's likely that switching to (2)
3398 // is correct for the future.
3399
3400 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3401 if (os::is_MP()) {
3402 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3403 masm.mfence();
3404 } else {
3405 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3406 }
3407 }
3408 // Ratify _succ remains non-null
3409 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3410 masm.jccb (Assembler::notZero, LSuccess) ;
3411
3412 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3413 if (os::is_MP()) { masm.lock(); }
3414 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3415 masm.jccb (Assembler::notEqual, LSuccess) ;
3416 // Since we're low on registers we installed rsp as a placeholding in _owner.
3417 // Now install Self over rsp. This is safe as we're transitioning from
3418 // non-null to non=null
3419 masm.get_thread (boxReg) ;
3420 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3421 // Intentional fall-through into LGoSlowPath ...
3422
3423 masm.bind (LGoSlowPath) ;
3424 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3425 masm.jmpb (DONE_LABEL) ;
3426
3427 masm.bind (LSuccess) ;
3428 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3429 masm.jmpb (DONE_LABEL) ;
3430 }
3431
3432 masm.bind (Stacked) ;
3433 // It's not inflated and it's not recursively stack-locked and it's not biased.
3434 // It must be stack-locked.
3435 // Try to reset the header to displaced header.
3436 // The "box" value on the stack is stable, so we can reload
3437 // and be assured we observe the same value as above.
3438 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3439 if (os::is_MP()) { masm.lock(); }
3440 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3441 // Intention fall-thru into DONE_LABEL
3442
3443
3444 // DONE_LABEL is a hot target - we'd really like to place it at the
3445 // start of cache line by padding with NOPs.
3446 // See the AMD and Intel software optimization manuals for the
3447 // most efficient "long" NOP encodings.
3448 // Unfortunately none of our alignment mechanisms suffice.
3449 if ((EmitSync & 65536) == 0) {
3450 masm.bind (CheckSucc) ;
3451 }
3452 masm.bind(DONE_LABEL);
3453
3454 // Avoid branch to branch on AMD processors
3455 if (EmitSync & 32768) { masm.nop() ; }
3456 }
3457 %}
3458
3459
3460 enc_class enc_pop_rdx() %{
3461 emit_opcode(cbuf,0x5A);
3462 %}
3463
3464 enc_class enc_rethrow() %{
3465 cbuf.set_insts_mark();
3466 emit_opcode(cbuf, 0xE9); // jmp entry
3467 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3468 runtime_call_Relocation::spec(), RELOC_IMM32 );
3469 %}
3470
3471
3472 // Convert a double to an int. Java semantics require we do complex
3473 // manglelations in the corner cases. So we set the rounding mode to
3474 // 'zero', store the darned double down as an int, and reset the
3475 // rounding mode to 'nearest'. The hardware throws an exception which
3476 // patches up the correct value directly to the stack.
3477 enc_class DPR2I_encoding( regDPR src ) %{
3478 // Flip to round-to-zero mode. We attempted to allow invalid-op
3479 // exceptions here, so that a NAN or other corner-case value will
3480 // thrown an exception (but normal values get converted at full speed).
3481 // However, I2C adapters and other float-stack manglers leave pending
3482 // invalid-op exceptions hanging. We would have to clear them before
3483 // enabling them and that is more expensive than just testing for the
3484 // invalid value Intel stores down in the corner cases.
3485 emit_opcode(cbuf,0xD9); // FLDCW trunc
3486 emit_opcode(cbuf,0x2D);
3487 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3488 // Allocate a word
3489 emit_opcode(cbuf,0x83); // SUB ESP,4
3490 emit_opcode(cbuf,0xEC);
3491 emit_d8(cbuf,0x04);
3492 // Encoding assumes a double has been pushed into FPR0.
3493 // Store down the double as an int, popping the FPU stack
3494 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3495 emit_opcode(cbuf,0x1C);
3496 emit_d8(cbuf,0x24);
3497 // Restore the rounding mode; mask the exception
3498 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3499 emit_opcode(cbuf,0x2D);
3500 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3501 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3502 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3503
3504 // Load the converted int; adjust CPU stack
3505 emit_opcode(cbuf,0x58); // POP EAX
3506 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3507 emit_d32 (cbuf,0x80000000); // 0x80000000
3508 emit_opcode(cbuf,0x75); // JNE around_slow_call
3509 emit_d8 (cbuf,0x07); // Size of slow_call
3510 // Push src onto stack slow-path
3511 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3512 emit_d8 (cbuf,0xC0-1+$src$$reg );
3513 // CALL directly to the runtime
3514 cbuf.set_insts_mark();
3515 emit_opcode(cbuf,0xE8); // Call into runtime
3516 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3517 // Carry on here...
3518 %}
3519
3520 enc_class DPR2L_encoding( regDPR src ) %{
3521 emit_opcode(cbuf,0xD9); // FLDCW trunc
3522 emit_opcode(cbuf,0x2D);
3523 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3524 // Allocate a word
3525 emit_opcode(cbuf,0x83); // SUB ESP,8
3526 emit_opcode(cbuf,0xEC);
3527 emit_d8(cbuf,0x08);
3528 // Encoding assumes a double has been pushed into FPR0.
3529 // Store down the double as a long, popping the FPU stack
3530 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3531 emit_opcode(cbuf,0x3C);
3532 emit_d8(cbuf,0x24);
3533 // Restore the rounding mode; mask the exception
3534 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3535 emit_opcode(cbuf,0x2D);
3536 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3537 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3538 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3539
3540 // Load the converted int; adjust CPU stack
3541 emit_opcode(cbuf,0x58); // POP EAX
3542 emit_opcode(cbuf,0x5A); // POP EDX
3543 emit_opcode(cbuf,0x81); // CMP EDX,imm
3544 emit_d8 (cbuf,0xFA); // rdx
3545 emit_d32 (cbuf,0x80000000); // 0x80000000
3546 emit_opcode(cbuf,0x75); // JNE around_slow_call
3547 emit_d8 (cbuf,0x07+4); // Size of slow_call
3548 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3549 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3550 emit_opcode(cbuf,0x75); // JNE around_slow_call
3551 emit_d8 (cbuf,0x07); // Size of slow_call
3552 // Push src onto stack slow-path
3553 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3554 emit_d8 (cbuf,0xC0-1+$src$$reg );
3555 // CALL directly to the runtime
3556 cbuf.set_insts_mark();
3557 emit_opcode(cbuf,0xE8); // Call into runtime
3558 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3559 // Carry on here...
3560 %}
3561
3562 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3563 // Operand was loaded from memory into fp ST (stack top)
3564 // FMUL ST,$src /* D8 C8+i */
3565 emit_opcode(cbuf, 0xD8);
3566 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3567 %}
3568
3569 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3570 // FADDP ST,src2 /* D8 C0+i */
3571 emit_opcode(cbuf, 0xD8);
3572 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3573 //could use FADDP src2,fpST /* DE C0+i */
3574 %}
3575
3576 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3577 // FADDP src2,ST /* DE C0+i */
3578 emit_opcode(cbuf, 0xDE);
3579 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3580 %}
3581
3582 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3583 // Operand has been loaded into fp ST (stack top)
3584 // FSUB ST,$src1
3585 emit_opcode(cbuf, 0xD8);
3586 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3587
3588 // FDIV
3589 emit_opcode(cbuf, 0xD8);
3590 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3591 %}
3592
3593 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3594 // Operand was loaded from memory into fp ST (stack top)
3595 // FADD ST,$src /* D8 C0+i */
3596 emit_opcode(cbuf, 0xD8);
3597 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3598
3599 // FMUL ST,src2 /* D8 C*+i */
3600 emit_opcode(cbuf, 0xD8);
3601 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3602 %}
3603
3604
3605 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3606 // Operand was loaded from memory into fp ST (stack top)
3607 // FADD ST,$src /* D8 C0+i */
3608 emit_opcode(cbuf, 0xD8);
3609 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3610
3611 // FMULP src2,ST /* DE C8+i */
3612 emit_opcode(cbuf, 0xDE);
3613 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3614 %}
3615
3616 // Atomically load the volatile long
3617 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3618 emit_opcode(cbuf,0xDF);
3619 int rm_byte_opcode = 0x05;
3620 int base = $mem$$base;
3621 int index = $mem$$index;
3622 int scale = $mem$$scale;
3623 int displace = $mem$$disp;
3624 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3625 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3626 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3627 %}
3628
3629 // Volatile Store Long. Must be atomic, so move it into
3630 // the FP TOS and then do a 64-bit FIST. Has to probe the
3631 // target address before the store (for null-ptr checks)
3632 // so the memory operand is used twice in the encoding.
3633 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3634 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3635 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3636 emit_opcode(cbuf,0xDF);
3637 int rm_byte_opcode = 0x07;
3638 int base = $mem$$base;
3639 int index = $mem$$index;
3640 int scale = $mem$$scale;
3641 int displace = $mem$$disp;
3642 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3643 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3644 %}
3645
3646 // Safepoint Poll. This polls the safepoint page, and causes an
3647 // exception if it is not readable. Unfortunately, it kills the condition code
3648 // in the process
3649 // We current use TESTL [spp],EDI
3650 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3651
3652 enc_class Safepoint_Poll() %{
3653 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3654 emit_opcode(cbuf,0x85);
3655 emit_rm (cbuf, 0x0, 0x7, 0x5);
3656 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3657 %}
3658 %}
3659
3660
3661 //----------FRAME--------------------------------------------------------------
3662 // Definition of frame structure and management information.
3663 //
3664 // S T A C K L A Y O U T Allocators stack-slot number
3665 // | (to get allocators register number
3666 // G Owned by | | v add OptoReg::stack0())
3667 // r CALLER | |
3668 // o | +--------+ pad to even-align allocators stack-slot
3669 // w V | pad0 | numbers; owned by CALLER
3670 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3671 // h ^ | in | 5
3672 // | | args | 4 Holes in incoming args owned by SELF
3673 // | | | | 3
3674 // | | +--------+
3675 // V | | old out| Empty on Intel, window on Sparc
3676 // | old |preserve| Must be even aligned.
3677 // | SP-+--------+----> Matcher::_old_SP, even aligned
3678 // | | in | 3 area for Intel ret address
3679 // Owned by |preserve| Empty on Sparc.
3680 // SELF +--------+
3681 // | | pad2 | 2 pad to align old SP
3682 // | +--------+ 1
3683 // | | locks | 0
3684 // | +--------+----> OptoReg::stack0(), even aligned
3685 // | | pad1 | 11 pad to align new SP
3686 // | +--------+
3687 // | | | 10
3688 // | | spills | 9 spills
3689 // V | | 8 (pad0 slot for callee)
3690 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3691 // ^ | out | 7
3692 // | | args | 6 Holes in outgoing args owned by CALLEE
3693 // Owned by +--------+
3694 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3695 // | new |preserve| Must be even-aligned.
3696 // | SP-+--------+----> Matcher::_new_SP, even aligned
3697 // | | |
3698 //
3699 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3700 // known from SELF's arguments and the Java calling convention.
3701 // Region 6-7 is determined per call site.
3702 // Note 2: If the calling convention leaves holes in the incoming argument
3703 // area, those holes are owned by SELF. Holes in the outgoing area
3704 // are owned by the CALLEE. Holes should not be nessecary in the
3705 // incoming area, as the Java calling convention is completely under
3706 // the control of the AD file. Doubles can be sorted and packed to
3707 // avoid holes. Holes in the outgoing arguments may be nessecary for
3708 // varargs C calling conventions.
3709 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3710 // even aligned with pad0 as needed.
3711 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3712 // region 6-11 is even aligned; it may be padded out more so that
3713 // the region from SP to FP meets the minimum stack alignment.
3714
3715 frame %{
3716 // What direction does stack grow in (assumed to be same for C & Java)
3717 stack_direction(TOWARDS_LOW);
3718
3719 // These three registers define part of the calling convention
3720 // between compiled code and the interpreter.
3721 inline_cache_reg(EAX); // Inline Cache Register
3722 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3723
3724 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3725 cisc_spilling_operand_name(indOffset32);
3726
3727 // Number of stack slots consumed by locking an object
3728 sync_stack_slots(1);
3729
3730 // Compiled code's Frame Pointer
3731 frame_pointer(ESP);
3732 // Interpreter stores its frame pointer in a register which is
3733 // stored to the stack by I2CAdaptors.
3734 // I2CAdaptors convert from interpreted java to compiled java.
3735 interpreter_frame_pointer(EBP);
3736
3737 // Stack alignment requirement
3738 // Alignment size in bytes (128-bit -> 16 bytes)
3739 stack_alignment(StackAlignmentInBytes);
3740
3741 // Number of stack slots between incoming argument block and the start of
3742 // a new frame. The PROLOG must add this many slots to the stack. The
3743 // EPILOG must remove this many slots. Intel needs one slot for
3744 // return address and one for rbp, (must save rbp)
3745 in_preserve_stack_slots(2+VerifyStackAtCalls);
3746
3747 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3748 // for calls to C. Supports the var-args backing area for register parms.
3749 varargs_C_out_slots_killed(0);
3750
3751 // The after-PROLOG location of the return address. Location of
3752 // return address specifies a type (REG or STACK) and a number
3753 // representing the register number (i.e. - use a register name) or
3754 // stack slot.
3755 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3756 // Otherwise, it is above the locks and verification slot and alignment word
3757 return_addr(STACK - 1 +
3758 round_to((Compile::current()->in_preserve_stack_slots() +
3759 Compile::current()->fixed_slots()),
3760 stack_alignment_in_slots()));
3761
3762 // Body of function which returns an integer array locating
3763 // arguments either in registers or in stack slots. Passed an array
3764 // of ideal registers called "sig" and a "length" count. Stack-slot
3765 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3766 // arguments for a CALLEE. Incoming stack arguments are
3767 // automatically biased by the preserve_stack_slots field above.
3768 calling_convention %{
3769 // No difference between ingoing/outgoing just pass false
3770 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3771 %}
3772
3773
3774 // Body of function which returns an integer array locating
3775 // arguments either in registers or in stack slots. Passed an array
3776 // of ideal registers called "sig" and a "length" count. Stack-slot
3777 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3778 // arguments for a CALLEE. Incoming stack arguments are
3779 // automatically biased by the preserve_stack_slots field above.
3780 c_calling_convention %{
3781 // This is obviously always outgoing
3782 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3783 %}
3784
3785 // Location of C & interpreter return values
3786 c_return_value %{
3787 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3788 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3789 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3790
3791 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3792 // that C functions return float and double results in XMM0.
3793 if( ideal_reg == Op_RegD && UseSSE>=2 )
3794 return OptoRegPair(XMM0b_num,XMM0_num);
3795 if( ideal_reg == Op_RegF && UseSSE>=2 )
3796 return OptoRegPair(OptoReg::Bad,XMM0_num);
3797
3798 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3799 %}
3800
3801 // Location of return values
3802 return_value %{
3803 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3804 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3805 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3806 if( ideal_reg == Op_RegD && UseSSE>=2 )
3807 return OptoRegPair(XMM0b_num,XMM0_num);
3808 if( ideal_reg == Op_RegF && UseSSE>=1 )
3809 return OptoRegPair(OptoReg::Bad,XMM0_num);
3810 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3811 %}
3812
3813 %}
3814
3815 //----------ATTRIBUTES---------------------------------------------------------
3816 //----------Operand Attributes-------------------------------------------------
3817 op_attrib op_cost(0); // Required cost attribute
3818
3819 //----------Instruction Attributes---------------------------------------------
3820 ins_attrib ins_cost(100); // Required cost attribute
3821 ins_attrib ins_size(8); // Required size attribute (in bits)
3822 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3823 // non-matching short branch variant of some
3824 // long branch?
3825 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3826 // specifies the alignment that some part of the instruction (not
3827 // necessarily the start) requires. If > 1, a compute_padding()
3828 // function must be provided for the instruction
3829
3830 //----------OPERANDS-----------------------------------------------------------
3831 // Operand definitions must precede instruction definitions for correct parsing
3832 // in the ADLC because operands constitute user defined types which are used in
3833 // instruction definitions.
3834
3835 //----------Simple Operands----------------------------------------------------
3836 // Immediate Operands
3837 // Integer Immediate
3838 operand immI() %{
3839 match(ConI);
3840
3841 op_cost(10);
3842 format %{ %}
3843 interface(CONST_INTER);
3844 %}
3845
3846 // Constant for test vs zero
3847 operand immI0() %{
3848 predicate(n->get_int() == 0);
3849 match(ConI);
3850
3851 op_cost(0);
3852 format %{ %}
3853 interface(CONST_INTER);
3854 %}
3855
3856 // Constant for increment
3857 operand immI1() %{
3858 predicate(n->get_int() == 1);
3859 match(ConI);
3860
3861 op_cost(0);
3862 format %{ %}
3863 interface(CONST_INTER);
3864 %}
3865
3866 // Constant for decrement
3867 operand immI_M1() %{
3868 predicate(n->get_int() == -1);
3869 match(ConI);
3870
3871 op_cost(0);
3872 format %{ %}
3873 interface(CONST_INTER);
3874 %}
3875
3876 // Valid scale values for addressing modes
3877 operand immI2() %{
3878 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3879 match(ConI);
3880
3881 format %{ %}
3882 interface(CONST_INTER);
3883 %}
3884
3885 operand immI8() %{
3886 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3887 match(ConI);
3888
3889 op_cost(5);
3890 format %{ %}
3891 interface(CONST_INTER);
3892 %}
3893
3894 operand immI16() %{
3895 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3896 match(ConI);
3897
3898 op_cost(10);
3899 format %{ %}
3900 interface(CONST_INTER);
3901 %}
3902
3903 // Constant for long shifts
3904 operand immI_32() %{
3905 predicate( n->get_int() == 32 );
3906 match(ConI);
3907
3908 op_cost(0);
3909 format %{ %}
3910 interface(CONST_INTER);
3911 %}
3912
3913 operand immI_1_31() %{
3914 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3915 match(ConI);
3916
3917 op_cost(0);
3918 format %{ %}
3919 interface(CONST_INTER);
3920 %}
3921
3922 operand immI_32_63() %{
3923 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3924 match(ConI);
3925 op_cost(0);
3926
3927 format %{ %}
3928 interface(CONST_INTER);
3929 %}
3930
3931 operand immI_1() %{
3932 predicate( n->get_int() == 1 );
3933 match(ConI);
3934
3935 op_cost(0);
3936 format %{ %}
3937 interface(CONST_INTER);
3938 %}
3939
3940 operand immI_2() %{
3941 predicate( n->get_int() == 2 );
3942 match(ConI);
3943
3944 op_cost(0);
3945 format %{ %}
3946 interface(CONST_INTER);
3947 %}
3948
3949 operand immI_3() %{
3950 predicate( n->get_int() == 3 );
3951 match(ConI);
3952
3953 op_cost(0);
3954 format %{ %}
3955 interface(CONST_INTER);
3956 %}
3957
3958 // Pointer Immediate
3959 operand immP() %{
3960 match(ConP);
3961
3962 op_cost(10);
3963 format %{ %}
3964 interface(CONST_INTER);
3965 %}
3966
3967 // NULL Pointer Immediate
3968 operand immP0() %{
3969 predicate( n->get_ptr() == 0 );
3970 match(ConP);
3971 op_cost(0);
3972
3973 format %{ %}
3974 interface(CONST_INTER);
3975 %}
3976
3977 // Long Immediate
3978 operand immL() %{
3979 match(ConL);
3980
3981 op_cost(20);
3982 format %{ %}
3983 interface(CONST_INTER);
3984 %}
3985
3986 // Long Immediate zero
3987 operand immL0() %{
3988 predicate( n->get_long() == 0L );
3989 match(ConL);
3990 op_cost(0);
3991
3992 format %{ %}
3993 interface(CONST_INTER);
3994 %}
3995
3996 // Long Immediate zero
3997 operand immL_M1() %{
3998 predicate( n->get_long() == -1L );
3999 match(ConL);
4000 op_cost(0);
4001
4002 format %{ %}
4003 interface(CONST_INTER);
4004 %}
4005
4006 // Long immediate from 0 to 127.
4007 // Used for a shorter form of long mul by 10.
4008 operand immL_127() %{
4009 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4010 match(ConL);
4011 op_cost(0);
4012
4013 format %{ %}
4014 interface(CONST_INTER);
4015 %}
4016
4017 // Long Immediate: low 32-bit mask
4018 operand immL_32bits() %{
4019 predicate(n->get_long() == 0xFFFFFFFFL);
4020 match(ConL);
4021 op_cost(0);
4022
4023 format %{ %}
4024 interface(CONST_INTER);
4025 %}
4026
4027 // Long Immediate: low 32-bit mask
4028 operand immL32() %{
4029 predicate(n->get_long() == (int)(n->get_long()));
4030 match(ConL);
4031 op_cost(20);
4032
4033 format %{ %}
4034 interface(CONST_INTER);
4035 %}
4036
4037 //Double Immediate zero
4038 operand immDPR0() %{
4039 // Do additional (and counter-intuitive) test against NaN to work around VC++
4040 // bug that generates code such that NaNs compare equal to 0.0
4041 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4042 match(ConD);
4043
4044 op_cost(5);
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4048
4049 // Double Immediate one
4050 operand immDPR1() %{
4051 predicate( UseSSE<=1 && n->getd() == 1.0 );
4052 match(ConD);
4053
4054 op_cost(5);
4055 format %{ %}
4056 interface(CONST_INTER);
4057 %}
4058
4059 // Double Immediate
4060 operand immDPR() %{
4061 predicate(UseSSE<=1);
4062 match(ConD);
4063
4064 op_cost(5);
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4068
4069 operand immD() %{
4070 predicate(UseSSE>=2);
4071 match(ConD);
4072
4073 op_cost(5);
4074 format %{ %}
4075 interface(CONST_INTER);
4076 %}
4077
4078 // Double Immediate zero
4079 operand immD0() %{
4080 // Do additional (and counter-intuitive) test against NaN to work around VC++
4081 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4082 // compare equal to -0.0.
4083 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4084 match(ConD);
4085
4086 format %{ %}
4087 interface(CONST_INTER);
4088 %}
4089
4090 // Float Immediate zero
4091 operand immFPR0() %{
4092 predicate(UseSSE == 0 && n->getf() == 0.0F);
4093 match(ConF);
4094
4095 op_cost(5);
4096 format %{ %}
4097 interface(CONST_INTER);
4098 %}
4099
4100 // Float Immediate one
4101 operand immFPR1() %{
4102 predicate(UseSSE == 0 && n->getf() == 1.0F);
4103 match(ConF);
4104
4105 op_cost(5);
4106 format %{ %}
4107 interface(CONST_INTER);
4108 %}
4109
4110 // Float Immediate
4111 operand immFPR() %{
4112 predicate( UseSSE == 0 );
4113 match(ConF);
4114
4115 op_cost(5);
4116 format %{ %}
4117 interface(CONST_INTER);
4118 %}
4119
4120 // Float Immediate
4121 operand immF() %{
4122 predicate(UseSSE >= 1);
4123 match(ConF);
4124
4125 op_cost(5);
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4129
4130 // Float Immediate zero. Zero and not -0.0
4131 operand immF0() %{
4132 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4133 match(ConF);
4134
4135 op_cost(5);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Immediates for special shifts (sign extend)
4141
4142 // Constants for increment
4143 operand immI_16() %{
4144 predicate( n->get_int() == 16 );
4145 match(ConI);
4146
4147 format %{ %}
4148 interface(CONST_INTER);
4149 %}
4150
4151 operand immI_24() %{
4152 predicate( n->get_int() == 24 );
4153 match(ConI);
4154
4155 format %{ %}
4156 interface(CONST_INTER);
4157 %}
4158
4159 // Constant for byte-wide masking
4160 operand immI_255() %{
4161 predicate( n->get_int() == 255 );
4162 match(ConI);
4163
4164 format %{ %}
4165 interface(CONST_INTER);
4166 %}
4167
4168 // Constant for short-wide masking
4169 operand immI_65535() %{
4170 predicate(n->get_int() == 65535);
4171 match(ConI);
4172
4173 format %{ %}
4174 interface(CONST_INTER);
4175 %}
4176
4177 // Register Operands
4178 // Integer Register
4179 operand rRegI() %{
4180 constraint(ALLOC_IN_RC(int_reg));
4181 match(RegI);
4182 match(xRegI);
4183 match(eAXRegI);
4184 match(eBXRegI);
4185 match(eCXRegI);
4186 match(eDXRegI);
4187 match(eDIRegI);
4188 match(eSIRegI);
4189
4190 format %{ %}
4191 interface(REG_INTER);
4192 %}
4193
4194 // Subset of Integer Register
4195 operand xRegI(rRegI reg) %{
4196 constraint(ALLOC_IN_RC(int_x_reg));
4197 match(reg);
4198 match(eAXRegI);
4199 match(eBXRegI);
4200 match(eCXRegI);
4201 match(eDXRegI);
4202
4203 format %{ %}
4204 interface(REG_INTER);
4205 %}
4206
4207 // Special Registers
4208 operand eAXRegI(xRegI reg) %{
4209 constraint(ALLOC_IN_RC(eax_reg));
4210 match(reg);
4211 match(rRegI);
4212
4213 format %{ "EAX" %}
4214 interface(REG_INTER);
4215 %}
4216
4217 // Special Registers
4218 operand eBXRegI(xRegI reg) %{
4219 constraint(ALLOC_IN_RC(ebx_reg));
4220 match(reg);
4221 match(rRegI);
4222
4223 format %{ "EBX" %}
4224 interface(REG_INTER);
4225 %}
4226
4227 operand eCXRegI(xRegI reg) %{
4228 constraint(ALLOC_IN_RC(ecx_reg));
4229 match(reg);
4230 match(rRegI);
4231
4232 format %{ "ECX" %}
4233 interface(REG_INTER);
4234 %}
4235
4236 operand eDXRegI(xRegI reg) %{
4237 constraint(ALLOC_IN_RC(edx_reg));
4238 match(reg);
4239 match(rRegI);
4240
4241 format %{ "EDX" %}
4242 interface(REG_INTER);
4243 %}
4244
4245 operand eDIRegI(xRegI reg) %{
4246 constraint(ALLOC_IN_RC(edi_reg));
4247 match(reg);
4248 match(rRegI);
4249
4250 format %{ "EDI" %}
4251 interface(REG_INTER);
4252 %}
4253
4254 operand naxRegI() %{
4255 constraint(ALLOC_IN_RC(nax_reg));
4256 match(RegI);
4257 match(eCXRegI);
4258 match(eDXRegI);
4259 match(eSIRegI);
4260 match(eDIRegI);
4261
4262 format %{ %}
4263 interface(REG_INTER);
4264 %}
4265
4266 operand nadxRegI() %{
4267 constraint(ALLOC_IN_RC(nadx_reg));
4268 match(RegI);
4269 match(eBXRegI);
4270 match(eCXRegI);
4271 match(eSIRegI);
4272 match(eDIRegI);
4273
4274 format %{ %}
4275 interface(REG_INTER);
4276 %}
4277
4278 operand ncxRegI() %{
4279 constraint(ALLOC_IN_RC(ncx_reg));
4280 match(RegI);
4281 match(eAXRegI);
4282 match(eDXRegI);
4283 match(eSIRegI);
4284 match(eDIRegI);
4285
4286 format %{ %}
4287 interface(REG_INTER);
4288 %}
4289
4290 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4291 // //
4292 operand eSIRegI(xRegI reg) %{
4293 constraint(ALLOC_IN_RC(esi_reg));
4294 match(reg);
4295 match(rRegI);
4296
4297 format %{ "ESI" %}
4298 interface(REG_INTER);
4299 %}
4300
4301 // Pointer Register
4302 operand anyRegP() %{
4303 constraint(ALLOC_IN_RC(any_reg));
4304 match(RegP);
4305 match(eAXRegP);
4306 match(eBXRegP);
4307 match(eCXRegP);
4308 match(eDIRegP);
4309 match(eRegP);
4310
4311 format %{ %}
4312 interface(REG_INTER);
4313 %}
4314
4315 operand eRegP() %{
4316 constraint(ALLOC_IN_RC(int_reg));
4317 match(RegP);
4318 match(eAXRegP);
4319 match(eBXRegP);
4320 match(eCXRegP);
4321 match(eDIRegP);
4322
4323 format %{ %}
4324 interface(REG_INTER);
4325 %}
4326
4327 // On windows95, EBP is not safe to use for implicit null tests.
4328 operand eRegP_no_EBP() %{
4329 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4330 match(RegP);
4331 match(eAXRegP);
4332 match(eBXRegP);
4333 match(eCXRegP);
4334 match(eDIRegP);
4335
4336 op_cost(100);
4337 format %{ %}
4338 interface(REG_INTER);
4339 %}
4340
4341 operand naxRegP() %{
4342 constraint(ALLOC_IN_RC(nax_reg));
4343 match(RegP);
4344 match(eBXRegP);
4345 match(eDXRegP);
4346 match(eCXRegP);
4347 match(eSIRegP);
4348 match(eDIRegP);
4349
4350 format %{ %}
4351 interface(REG_INTER);
4352 %}
4353
4354 operand nabxRegP() %{
4355 constraint(ALLOC_IN_RC(nabx_reg));
4356 match(RegP);
4357 match(eCXRegP);
4358 match(eDXRegP);
4359 match(eSIRegP);
4360 match(eDIRegP);
4361
4362 format %{ %}
4363 interface(REG_INTER);
4364 %}
4365
4366 operand pRegP() %{
4367 constraint(ALLOC_IN_RC(p_reg));
4368 match(RegP);
4369 match(eBXRegP);
4370 match(eDXRegP);
4371 match(eSIRegP);
4372 match(eDIRegP);
4373
4374 format %{ %}
4375 interface(REG_INTER);
4376 %}
4377
4378 // Special Registers
4379 // Return a pointer value
4380 operand eAXRegP(eRegP reg) %{
4381 constraint(ALLOC_IN_RC(eax_reg));
4382 match(reg);
4383 format %{ "EAX" %}
4384 interface(REG_INTER);
4385 %}
4386
4387 // Used in AtomicAdd
4388 operand eBXRegP(eRegP reg) %{
4389 constraint(ALLOC_IN_RC(ebx_reg));
4390 match(reg);
4391 format %{ "EBX" %}
4392 interface(REG_INTER);
4393 %}
4394
4395 // Tail-call (interprocedural jump) to interpreter
4396 operand eCXRegP(eRegP reg) %{
4397 constraint(ALLOC_IN_RC(ecx_reg));
4398 match(reg);
4399 format %{ "ECX" %}
4400 interface(REG_INTER);
4401 %}
4402
4403 operand eSIRegP(eRegP reg) %{
4404 constraint(ALLOC_IN_RC(esi_reg));
4405 match(reg);
4406 format %{ "ESI" %}
4407 interface(REG_INTER);
4408 %}
4409
4410 // Used in rep stosw
4411 operand eDIRegP(eRegP reg) %{
4412 constraint(ALLOC_IN_RC(edi_reg));
4413 match(reg);
4414 format %{ "EDI" %}
4415 interface(REG_INTER);
4416 %}
4417
4418 operand eBPRegP() %{
4419 constraint(ALLOC_IN_RC(ebp_reg));
4420 match(RegP);
4421 format %{ "EBP" %}
4422 interface(REG_INTER);
4423 %}
4424
4425 operand eRegL() %{
4426 constraint(ALLOC_IN_RC(long_reg));
4427 match(RegL);
4428 match(eADXRegL);
4429
4430 format %{ %}
4431 interface(REG_INTER);
4432 %}
4433
4434 operand eADXRegL( eRegL reg ) %{
4435 constraint(ALLOC_IN_RC(eadx_reg));
4436 match(reg);
4437
4438 format %{ "EDX:EAX" %}
4439 interface(REG_INTER);
4440 %}
4441
4442 operand eBCXRegL( eRegL reg ) %{
4443 constraint(ALLOC_IN_RC(ebcx_reg));
4444 match(reg);
4445
4446 format %{ "EBX:ECX" %}
4447 interface(REG_INTER);
4448 %}
4449
4450 // Special case for integer high multiply
4451 operand eADXRegL_low_only() %{
4452 constraint(ALLOC_IN_RC(eadx_reg));
4453 match(RegL);
4454
4455 format %{ "EAX" %}
4456 interface(REG_INTER);
4457 %}
4458
4459 // Flags register, used as output of compare instructions
4460 operand eFlagsReg() %{
4461 constraint(ALLOC_IN_RC(int_flags));
4462 match(RegFlags);
4463
4464 format %{ "EFLAGS" %}
4465 interface(REG_INTER);
4466 %}
4467
4468 // Flags register, used as output of FLOATING POINT compare instructions
4469 operand eFlagsRegU() %{
4470 constraint(ALLOC_IN_RC(int_flags));
4471 match(RegFlags);
4472
4473 format %{ "EFLAGS_U" %}
4474 interface(REG_INTER);
4475 %}
4476
4477 operand eFlagsRegUCF() %{
4478 constraint(ALLOC_IN_RC(int_flags));
4479 match(RegFlags);
4480 predicate(false);
4481
4482 format %{ "EFLAGS_U_CF" %}
4483 interface(REG_INTER);
4484 %}
4485
4486 // Condition Code Register used by long compare
4487 operand flagsReg_long_LTGE() %{
4488 constraint(ALLOC_IN_RC(int_flags));
4489 match(RegFlags);
4490 format %{ "FLAGS_LTGE" %}
4491 interface(REG_INTER);
4492 %}
4493 operand flagsReg_long_EQNE() %{
4494 constraint(ALLOC_IN_RC(int_flags));
4495 match(RegFlags);
4496 format %{ "FLAGS_EQNE" %}
4497 interface(REG_INTER);
4498 %}
4499 operand flagsReg_long_LEGT() %{
4500 constraint(ALLOC_IN_RC(int_flags));
4501 match(RegFlags);
4502 format %{ "FLAGS_LEGT" %}
4503 interface(REG_INTER);
4504 %}
4505
4506 // Float register operands
4507 operand regDPR() %{
4508 predicate( UseSSE < 2 );
4509 constraint(ALLOC_IN_RC(fp_dbl_reg));
4510 match(RegD);
4511 match(regDPR1);
4512 match(regDPR2);
4513 format %{ %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand regDPR1(regDPR reg) %{
4518 predicate( UseSSE < 2 );
4519 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4520 match(reg);
4521 format %{ "FPR1" %}
4522 interface(REG_INTER);
4523 %}
4524
4525 operand regDPR2(regDPR reg) %{
4526 predicate( UseSSE < 2 );
4527 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4528 match(reg);
4529 format %{ "FPR2" %}
4530 interface(REG_INTER);
4531 %}
4532
4533 operand regnotDPR1(regDPR reg) %{
4534 predicate( UseSSE < 2 );
4535 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4536 match(reg);
4537 format %{ %}
4538 interface(REG_INTER);
4539 %}
4540
4541 // Float register operands
4542 operand regFPR() %{
4543 predicate( UseSSE < 2 );
4544 constraint(ALLOC_IN_RC(fp_flt_reg));
4545 match(RegF);
4546 match(regFPR1);
4547 format %{ %}
4548 interface(REG_INTER);
4549 %}
4550
4551 // Float register operands
4552 operand regFPR1(regFPR reg) %{
4553 predicate( UseSSE < 2 );
4554 constraint(ALLOC_IN_RC(fp_flt_reg0));
4555 match(reg);
4556 format %{ "FPR1" %}
4557 interface(REG_INTER);
4558 %}
4559
4560 // XMM Float register operands
4561 operand regF() %{
4562 predicate( UseSSE>=1 );
4563 constraint(ALLOC_IN_RC(float_reg));
4564 match(RegF);
4565 format %{ %}
4566 interface(REG_INTER);
4567 %}
4568
4569 // XMM Double register operands
4570 operand regD() %{
4571 predicate( UseSSE>=2 );
4572 constraint(ALLOC_IN_RC(double_reg));
4573 match(RegD);
4574 format %{ %}
4575 interface(REG_INTER);
4576 %}
4577
4578
4579 //----------Memory Operands----------------------------------------------------
4580 // Direct Memory Operand
4581 operand direct(immP addr) %{
4582 match(addr);
4583
4584 format %{ "[$addr]" %}
4585 interface(MEMORY_INTER) %{
4586 base(0xFFFFFFFF);
4587 index(0x4);
4588 scale(0x0);
4589 disp($addr);
4590 %}
4591 %}
4592
4593 // Indirect Memory Operand
4594 operand indirect(eRegP reg) %{
4595 constraint(ALLOC_IN_RC(int_reg));
4596 match(reg);
4597
4598 format %{ "[$reg]" %}
4599 interface(MEMORY_INTER) %{
4600 base($reg);
4601 index(0x4);
4602 scale(0x0);
4603 disp(0x0);
4604 %}
4605 %}
4606
4607 // Indirect Memory Plus Short Offset Operand
4608 operand indOffset8(eRegP reg, immI8 off) %{
4609 match(AddP reg off);
4610
4611 format %{ "[$reg + $off]" %}
4612 interface(MEMORY_INTER) %{
4613 base($reg);
4614 index(0x4);
4615 scale(0x0);
4616 disp($off);
4617 %}
4618 %}
4619
4620 // Indirect Memory Plus Long Offset Operand
4621 operand indOffset32(eRegP reg, immI off) %{
4622 match(AddP reg off);
4623
4624 format %{ "[$reg + $off]" %}
4625 interface(MEMORY_INTER) %{
4626 base($reg);
4627 index(0x4);
4628 scale(0x0);
4629 disp($off);
4630 %}
4631 %}
4632
4633 // Indirect Memory Plus Long Offset Operand
4634 operand indOffset32X(rRegI reg, immP off) %{
4635 match(AddP off reg);
4636
4637 format %{ "[$reg + $off]" %}
4638 interface(MEMORY_INTER) %{
4639 base($reg);
4640 index(0x4);
4641 scale(0x0);
4642 disp($off);
4643 %}
4644 %}
4645
4646 // Indirect Memory Plus Index Register Plus Offset Operand
4647 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4648 match(AddP (AddP reg ireg) off);
4649
4650 op_cost(10);
4651 format %{"[$reg + $off + $ireg]" %}
4652 interface(MEMORY_INTER) %{
4653 base($reg);
4654 index($ireg);
4655 scale(0x0);
4656 disp($off);
4657 %}
4658 %}
4659
4660 // Indirect Memory Plus Index Register Plus Offset Operand
4661 operand indIndex(eRegP reg, rRegI ireg) %{
4662 match(AddP reg ireg);
4663
4664 op_cost(10);
4665 format %{"[$reg + $ireg]" %}
4666 interface(MEMORY_INTER) %{
4667 base($reg);
4668 index($ireg);
4669 scale(0x0);
4670 disp(0x0);
4671 %}
4672 %}
4673
4674 // // -------------------------------------------------------------------------
4675 // // 486 architecture doesn't support "scale * index + offset" with out a base
4676 // // -------------------------------------------------------------------------
4677 // // Scaled Memory Operands
4678 // // Indirect Memory Times Scale Plus Offset Operand
4679 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4680 // match(AddP off (LShiftI ireg scale));
4681 //
4682 // op_cost(10);
4683 // format %{"[$off + $ireg << $scale]" %}
4684 // interface(MEMORY_INTER) %{
4685 // base(0x4);
4686 // index($ireg);
4687 // scale($scale);
4688 // disp($off);
4689 // %}
4690 // %}
4691
4692 // Indirect Memory Times Scale Plus Index Register
4693 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4694 match(AddP reg (LShiftI ireg scale));
4695
4696 op_cost(10);
4697 format %{"[$reg + $ireg << $scale]" %}
4698 interface(MEMORY_INTER) %{
4699 base($reg);
4700 index($ireg);
4701 scale($scale);
4702 disp(0x0);
4703 %}
4704 %}
4705
4706 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4707 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4708 match(AddP (AddP reg (LShiftI ireg scale)) off);
4709
4710 op_cost(10);
4711 format %{"[$reg + $off + $ireg << $scale]" %}
4712 interface(MEMORY_INTER) %{
4713 base($reg);
4714 index($ireg);
4715 scale($scale);
4716 disp($off);
4717 %}
4718 %}
4719
4720 //----------Load Long Memory Operands------------------------------------------
4721 // The load-long idiom will use it's address expression again after loading
4722 // the first word of the long. If the load-long destination overlaps with
4723 // registers used in the addressing expression, the 2nd half will be loaded
4724 // from a clobbered address. Fix this by requiring that load-long use
4725 // address registers that do not overlap with the load-long target.
4726
4727 // load-long support
4728 operand load_long_RegP() %{
4729 constraint(ALLOC_IN_RC(esi_reg));
4730 match(RegP);
4731 match(eSIRegP);
4732 op_cost(100);
4733 format %{ %}
4734 interface(REG_INTER);
4735 %}
4736
4737 // Indirect Memory Operand Long
4738 operand load_long_indirect(load_long_RegP reg) %{
4739 constraint(ALLOC_IN_RC(esi_reg));
4740 match(reg);
4741
4742 format %{ "[$reg]" %}
4743 interface(MEMORY_INTER) %{
4744 base($reg);
4745 index(0x4);
4746 scale(0x0);
4747 disp(0x0);
4748 %}
4749 %}
4750
4751 // Indirect Memory Plus Long Offset Operand
4752 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4753 match(AddP reg off);
4754
4755 format %{ "[$reg + $off]" %}
4756 interface(MEMORY_INTER) %{
4757 base($reg);
4758 index(0x4);
4759 scale(0x0);
4760 disp($off);
4761 %}
4762 %}
4763
4764 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4765
4766
4767 //----------Special Memory Operands--------------------------------------------
4768 // Stack Slot Operand - This operand is used for loading and storing temporary
4769 // values on the stack where a match requires a value to
4770 // flow through memory.
4771 operand stackSlotP(sRegP reg) %{
4772 constraint(ALLOC_IN_RC(stack_slots));
4773 // No match rule because this operand is only generated in matching
4774 format %{ "[$reg]" %}
4775 interface(MEMORY_INTER) %{
4776 base(0x4); // ESP
4777 index(0x4); // No Index
4778 scale(0x0); // No Scale
4779 disp($reg); // Stack Offset
4780 %}
4781 %}
4782
4783 operand stackSlotI(sRegI reg) %{
4784 constraint(ALLOC_IN_RC(stack_slots));
4785 // No match rule because this operand is only generated in matching
4786 format %{ "[$reg]" %}
4787 interface(MEMORY_INTER) %{
4788 base(0x4); // ESP
4789 index(0x4); // No Index
4790 scale(0x0); // No Scale
4791 disp($reg); // Stack Offset
4792 %}
4793 %}
4794
4795 operand stackSlotF(sRegF reg) %{
4796 constraint(ALLOC_IN_RC(stack_slots));
4797 // No match rule because this operand is only generated in matching
4798 format %{ "[$reg]" %}
4799 interface(MEMORY_INTER) %{
4800 base(0x4); // ESP
4801 index(0x4); // No Index
4802 scale(0x0); // No Scale
4803 disp($reg); // Stack Offset
4804 %}
4805 %}
4806
4807 operand stackSlotD(sRegD reg) %{
4808 constraint(ALLOC_IN_RC(stack_slots));
4809 // No match rule because this operand is only generated in matching
4810 format %{ "[$reg]" %}
4811 interface(MEMORY_INTER) %{
4812 base(0x4); // ESP
4813 index(0x4); // No Index
4814 scale(0x0); // No Scale
4815 disp($reg); // Stack Offset
4816 %}
4817 %}
4818
4819 operand stackSlotL(sRegL reg) %{
4820 constraint(ALLOC_IN_RC(stack_slots));
4821 // No match rule because this operand is only generated in matching
4822 format %{ "[$reg]" %}
4823 interface(MEMORY_INTER) %{
4824 base(0x4); // ESP
4825 index(0x4); // No Index
4826 scale(0x0); // No Scale
4827 disp($reg); // Stack Offset
4828 %}
4829 %}
4830
4831 //----------Memory Operands - Win95 Implicit Null Variants----------------
4832 // Indirect Memory Operand
4833 operand indirect_win95_safe(eRegP_no_EBP reg)
4834 %{
4835 constraint(ALLOC_IN_RC(int_reg));
4836 match(reg);
4837
4838 op_cost(100);
4839 format %{ "[$reg]" %}
4840 interface(MEMORY_INTER) %{
4841 base($reg);
4842 index(0x4);
4843 scale(0x0);
4844 disp(0x0);
4845 %}
4846 %}
4847
4848 // Indirect Memory Plus Short Offset Operand
4849 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4850 %{
4851 match(AddP reg off);
4852
4853 op_cost(100);
4854 format %{ "[$reg + $off]" %}
4855 interface(MEMORY_INTER) %{
4856 base($reg);
4857 index(0x4);
4858 scale(0x0);
4859 disp($off);
4860 %}
4861 %}
4862
4863 // Indirect Memory Plus Long Offset Operand
4864 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4865 %{
4866 match(AddP reg off);
4867
4868 op_cost(100);
4869 format %{ "[$reg + $off]" %}
4870 interface(MEMORY_INTER) %{
4871 base($reg);
4872 index(0x4);
4873 scale(0x0);
4874 disp($off);
4875 %}
4876 %}
4877
4878 // Indirect Memory Plus Index Register Plus Offset Operand
4879 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4880 %{
4881 match(AddP (AddP reg ireg) off);
4882
4883 op_cost(100);
4884 format %{"[$reg + $off + $ireg]" %}
4885 interface(MEMORY_INTER) %{
4886 base($reg);
4887 index($ireg);
4888 scale(0x0);
4889 disp($off);
4890 %}
4891 %}
4892
4893 // Indirect Memory Times Scale Plus Index Register
4894 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4895 %{
4896 match(AddP reg (LShiftI ireg scale));
4897
4898 op_cost(100);
4899 format %{"[$reg + $ireg << $scale]" %}
4900 interface(MEMORY_INTER) %{
4901 base($reg);
4902 index($ireg);
4903 scale($scale);
4904 disp(0x0);
4905 %}
4906 %}
4907
4908 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4909 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4910 %{
4911 match(AddP (AddP reg (LShiftI ireg scale)) off);
4912
4913 op_cost(100);
4914 format %{"[$reg + $off + $ireg << $scale]" %}
4915 interface(MEMORY_INTER) %{
4916 base($reg);
4917 index($ireg);
4918 scale($scale);
4919 disp($off);
4920 %}
4921 %}
4922
4923 //----------Conditional Branch Operands----------------------------------------
4924 // Comparison Op - This is the operation of the comparison, and is limited to
4925 // the following set of codes:
4926 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4927 //
4928 // Other attributes of the comparison, such as unsignedness, are specified
4929 // by the comparison instruction that sets a condition code flags register.
4930 // That result is represented by a flags operand whose subtype is appropriate
4931 // to the unsignedness (etc.) of the comparison.
4932 //
4933 // Later, the instruction which matches both the Comparison Op (a Bool) and
4934 // the flags (produced by the Cmp) specifies the coding of the comparison op
4935 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4936
4937 // Comparision Code
4938 operand cmpOp() %{
4939 match(Bool);
4940
4941 format %{ "" %}
4942 interface(COND_INTER) %{
4943 equal(0x4, "e");
4944 not_equal(0x5, "ne");
4945 less(0xC, "l");
4946 greater_equal(0xD, "ge");
4947 less_equal(0xE, "le");
4948 greater(0xF, "g");
4949 %}
4950 %}
4951
4952 // Comparison Code, unsigned compare. Used by FP also, with
4953 // C2 (unordered) turned into GT or LT already. The other bits
4954 // C0 and C3 are turned into Carry & Zero flags.
4955 operand cmpOpU() %{
4956 match(Bool);
4957
4958 format %{ "" %}
4959 interface(COND_INTER) %{
4960 equal(0x4, "e");
4961 not_equal(0x5, "ne");
4962 less(0x2, "b");
4963 greater_equal(0x3, "nb");
4964 less_equal(0x6, "be");
4965 greater(0x7, "nbe");
4966 %}
4967 %}
4968
4969 // Floating comparisons that don't require any fixup for the unordered case
4970 operand cmpOpUCF() %{
4971 match(Bool);
4972 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4973 n->as_Bool()->_test._test == BoolTest::ge ||
4974 n->as_Bool()->_test._test == BoolTest::le ||
4975 n->as_Bool()->_test._test == BoolTest::gt);
4976 format %{ "" %}
4977 interface(COND_INTER) %{
4978 equal(0x4, "e");
4979 not_equal(0x5, "ne");
4980 less(0x2, "b");
4981 greater_equal(0x3, "nb");
4982 less_equal(0x6, "be");
4983 greater(0x7, "nbe");
4984 %}
4985 %}
4986
4987
4988 // Floating comparisons that can be fixed up with extra conditional jumps
4989 operand cmpOpUCF2() %{
4990 match(Bool);
4991 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4992 n->as_Bool()->_test._test == BoolTest::eq);
4993 format %{ "" %}
4994 interface(COND_INTER) %{
4995 equal(0x4, "e");
4996 not_equal(0x5, "ne");
4997 less(0x2, "b");
4998 greater_equal(0x3, "nb");
4999 less_equal(0x6, "be");
5000 greater(0x7, "nbe");
5001 %}
5002 %}
5003
5004 // Comparison Code for FP conditional move
5005 operand cmpOp_fcmov() %{
5006 match(Bool);
5007
5008 format %{ "" %}
5009 interface(COND_INTER) %{
5010 equal (0x0C8);
5011 not_equal (0x1C8);
5012 less (0x0C0);
5013 greater_equal(0x1C0);
5014 less_equal (0x0D0);
5015 greater (0x1D0);
5016 %}
5017 %}
5018
5019 // Comparision Code used in long compares
5020 operand cmpOp_commute() %{
5021 match(Bool);
5022
5023 format %{ "" %}
5024 interface(COND_INTER) %{
5025 equal(0x4, "e");
5026 not_equal(0x5, "ne");
5027 less(0xF, "g");
5028 greater_equal(0xE, "le");
5029 less_equal(0xD, "ge");
5030 greater(0xC, "l");
5031 %}
5032 %}
5033
5034 //----------OPERAND CLASSES----------------------------------------------------
5035 // Operand Classes are groups of operands that are used as to simplify
5036 // instruction definitions by not requiring the AD writer to specify separate
5037 // instructions for every form of operand when the instruction accepts
5038 // multiple operand types with the same basic encoding and format. The classic
5039 // case of this is memory operands.
5040
5041 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5042 indIndex, indIndexScale, indIndexScaleOffset);
5043
5044 // Long memory operations are encoded in 2 instructions and a +4 offset.
5045 // This means some kind of offset is always required and you cannot use
5046 // an oop as the offset (done when working on static globals).
5047 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5048 indIndex, indIndexScale, indIndexScaleOffset);
5049
5050
5051 //----------PIPELINE-----------------------------------------------------------
5052 // Rules which define the behavior of the target architectures pipeline.
5053 pipeline %{
5054
5055 //----------ATTRIBUTES---------------------------------------------------------
5056 attributes %{
5057 variable_size_instructions; // Fixed size instructions
5058 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5059 instruction_unit_size = 1; // An instruction is 1 bytes long
5060 instruction_fetch_unit_size = 16; // The processor fetches one line
5061 instruction_fetch_units = 1; // of 16 bytes
5062
5063 // List of nop instructions
5064 nops( MachNop );
5065 %}
5066
5067 //----------RESOURCES----------------------------------------------------------
5068 // Resources are the functional units available to the machine
5069
5070 // Generic P2/P3 pipeline
5071 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5072 // 3 instructions decoded per cycle.
5073 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5074 // 2 ALU op, only ALU0 handles mul/div instructions.
5075 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5076 MS0, MS1, MEM = MS0 | MS1,
5077 BR, FPU,
5078 ALU0, ALU1, ALU = ALU0 | ALU1 );
5079
5080 //----------PIPELINE DESCRIPTION-----------------------------------------------
5081 // Pipeline Description specifies the stages in the machine's pipeline
5082
5083 // Generic P2/P3 pipeline
5084 pipe_desc(S0, S1, S2, S3, S4, S5);
5085
5086 //----------PIPELINE CLASSES---------------------------------------------------
5087 // Pipeline Classes describe the stages in which input and output are
5088 // referenced by the hardware pipeline.
5089
5090 // Naming convention: ialu or fpu
5091 // Then: _reg
5092 // Then: _reg if there is a 2nd register
5093 // Then: _long if it's a pair of instructions implementing a long
5094 // Then: _fat if it requires the big decoder
5095 // Or: _mem if it requires the big decoder and a memory unit.
5096
5097 // Integer ALU reg operation
5098 pipe_class ialu_reg(rRegI dst) %{
5099 single_instruction;
5100 dst : S4(write);
5101 dst : S3(read);
5102 DECODE : S0; // any decoder
5103 ALU : S3; // any alu
5104 %}
5105
5106 // Long ALU reg operation
5107 pipe_class ialu_reg_long(eRegL dst) %{
5108 instruction_count(2);
5109 dst : S4(write);
5110 dst : S3(read);
5111 DECODE : S0(2); // any 2 decoders
5112 ALU : S3(2); // both alus
5113 %}
5114
5115 // Integer ALU reg operation using big decoder
5116 pipe_class ialu_reg_fat(rRegI dst) %{
5117 single_instruction;
5118 dst : S4(write);
5119 dst : S3(read);
5120 D0 : S0; // big decoder only
5121 ALU : S3; // any alu
5122 %}
5123
5124 // Long ALU reg operation using big decoder
5125 pipe_class ialu_reg_long_fat(eRegL dst) %{
5126 instruction_count(2);
5127 dst : S4(write);
5128 dst : S3(read);
5129 D0 : S0(2); // big decoder only; twice
5130 ALU : S3(2); // any 2 alus
5131 %}
5132
5133 // Integer ALU reg-reg operation
5134 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5135 single_instruction;
5136 dst : S4(write);
5137 src : S3(read);
5138 DECODE : S0; // any decoder
5139 ALU : S3; // any alu
5140 %}
5141
5142 // Long ALU reg-reg operation
5143 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5144 instruction_count(2);
5145 dst : S4(write);
5146 src : S3(read);
5147 DECODE : S0(2); // any 2 decoders
5148 ALU : S3(2); // both alus
5149 %}
5150
5151 // Integer ALU reg-reg operation
5152 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5153 single_instruction;
5154 dst : S4(write);
5155 src : S3(read);
5156 D0 : S0; // big decoder only
5157 ALU : S3; // any alu
5158 %}
5159
5160 // Long ALU reg-reg operation
5161 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5162 instruction_count(2);
5163 dst : S4(write);
5164 src : S3(read);
5165 D0 : S0(2); // big decoder only; twice
5166 ALU : S3(2); // both alus
5167 %}
5168
5169 // Integer ALU reg-mem operation
5170 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5171 single_instruction;
5172 dst : S5(write);
5173 mem : S3(read);
5174 D0 : S0; // big decoder only
5175 ALU : S4; // any alu
5176 MEM : S3; // any mem
5177 %}
5178
5179 // Long ALU reg-mem operation
5180 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5181 instruction_count(2);
5182 dst : S5(write);
5183 mem : S3(read);
5184 D0 : S0(2); // big decoder only; twice
5185 ALU : S4(2); // any 2 alus
5186 MEM : S3(2); // both mems
5187 %}
5188
5189 // Integer mem operation (prefetch)
5190 pipe_class ialu_mem(memory mem)
5191 %{
5192 single_instruction;
5193 mem : S3(read);
5194 D0 : S0; // big decoder only
5195 MEM : S3; // any mem
5196 %}
5197
5198 // Integer Store to Memory
5199 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5200 single_instruction;
5201 mem : S3(read);
5202 src : S5(read);
5203 D0 : S0; // big decoder only
5204 ALU : S4; // any alu
5205 MEM : S3;
5206 %}
5207
5208 // Long Store to Memory
5209 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5210 instruction_count(2);
5211 mem : S3(read);
5212 src : S5(read);
5213 D0 : S0(2); // big decoder only; twice
5214 ALU : S4(2); // any 2 alus
5215 MEM : S3(2); // Both mems
5216 %}
5217
5218 // Integer Store to Memory
5219 pipe_class ialu_mem_imm(memory mem) %{
5220 single_instruction;
5221 mem : S3(read);
5222 D0 : S0; // big decoder only
5223 ALU : S4; // any alu
5224 MEM : S3;
5225 %}
5226
5227 // Integer ALU0 reg-reg operation
5228 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5229 single_instruction;
5230 dst : S4(write);
5231 src : S3(read);
5232 D0 : S0; // Big decoder only
5233 ALU0 : S3; // only alu0
5234 %}
5235
5236 // Integer ALU0 reg-mem operation
5237 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5238 single_instruction;
5239 dst : S5(write);
5240 mem : S3(read);
5241 D0 : S0; // big decoder only
5242 ALU0 : S4; // ALU0 only
5243 MEM : S3; // any mem
5244 %}
5245
5246 // Integer ALU reg-reg operation
5247 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5248 single_instruction;
5249 cr : S4(write);
5250 src1 : S3(read);
5251 src2 : S3(read);
5252 DECODE : S0; // any decoder
5253 ALU : S3; // any alu
5254 %}
5255
5256 // Integer ALU reg-imm operation
5257 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5258 single_instruction;
5259 cr : S4(write);
5260 src1 : S3(read);
5261 DECODE : S0; // any decoder
5262 ALU : S3; // any alu
5263 %}
5264
5265 // Integer ALU reg-mem operation
5266 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5267 single_instruction;
5268 cr : S4(write);
5269 src1 : S3(read);
5270 src2 : S3(read);
5271 D0 : S0; // big decoder only
5272 ALU : S4; // any alu
5273 MEM : S3;
5274 %}
5275
5276 // Conditional move reg-reg
5277 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5278 instruction_count(4);
5279 y : S4(read);
5280 q : S3(read);
5281 p : S3(read);
5282 DECODE : S0(4); // any decoder
5283 %}
5284
5285 // Conditional move reg-reg
5286 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5287 single_instruction;
5288 dst : S4(write);
5289 src : S3(read);
5290 cr : S3(read);
5291 DECODE : S0; // any decoder
5292 %}
5293
5294 // Conditional move reg-mem
5295 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5296 single_instruction;
5297 dst : S4(write);
5298 src : S3(read);
5299 cr : S3(read);
5300 DECODE : S0; // any decoder
5301 MEM : S3;
5302 %}
5303
5304 // Conditional move reg-reg long
5305 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5306 single_instruction;
5307 dst : S4(write);
5308 src : S3(read);
5309 cr : S3(read);
5310 DECODE : S0(2); // any 2 decoders
5311 %}
5312
5313 // Conditional move double reg-reg
5314 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5315 single_instruction;
5316 dst : S4(write);
5317 src : S3(read);
5318 cr : S3(read);
5319 DECODE : S0; // any decoder
5320 %}
5321
5322 // Float reg-reg operation
5323 pipe_class fpu_reg(regDPR dst) %{
5324 instruction_count(2);
5325 dst : S3(read);
5326 DECODE : S0(2); // any 2 decoders
5327 FPU : S3;
5328 %}
5329
5330 // Float reg-reg operation
5331 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5332 instruction_count(2);
5333 dst : S4(write);
5334 src : S3(read);
5335 DECODE : S0(2); // any 2 decoders
5336 FPU : S3;
5337 %}
5338
5339 // Float reg-reg operation
5340 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5341 instruction_count(3);
5342 dst : S4(write);
5343 src1 : S3(read);
5344 src2 : S3(read);
5345 DECODE : S0(3); // any 3 decoders
5346 FPU : S3(2);
5347 %}
5348
5349 // Float reg-reg operation
5350 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5351 instruction_count(4);
5352 dst : S4(write);
5353 src1 : S3(read);
5354 src2 : S3(read);
5355 src3 : S3(read);
5356 DECODE : S0(4); // any 3 decoders
5357 FPU : S3(2);
5358 %}
5359
5360 // Float reg-reg operation
5361 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5362 instruction_count(4);
5363 dst : S4(write);
5364 src1 : S3(read);
5365 src2 : S3(read);
5366 src3 : S3(read);
5367 DECODE : S1(3); // any 3 decoders
5368 D0 : S0; // Big decoder only
5369 FPU : S3(2);
5370 MEM : S3;
5371 %}
5372
5373 // Float reg-mem operation
5374 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5375 instruction_count(2);
5376 dst : S5(write);
5377 mem : S3(read);
5378 D0 : S0; // big decoder only
5379 DECODE : S1; // any decoder for FPU POP
5380 FPU : S4;
5381 MEM : S3; // any mem
5382 %}
5383
5384 // Float reg-mem operation
5385 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5386 instruction_count(3);
5387 dst : S5(write);
5388 src1 : S3(read);
5389 mem : S3(read);
5390 D0 : S0; // big decoder only
5391 DECODE : S1(2); // any decoder for FPU POP
5392 FPU : S4;
5393 MEM : S3; // any mem
5394 %}
5395
5396 // Float mem-reg operation
5397 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5398 instruction_count(2);
5399 src : S5(read);
5400 mem : S3(read);
5401 DECODE : S0; // any decoder for FPU PUSH
5402 D0 : S1; // big decoder only
5403 FPU : S4;
5404 MEM : S3; // any mem
5405 %}
5406
5407 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5408 instruction_count(3);
5409 src1 : S3(read);
5410 src2 : S3(read);
5411 mem : S3(read);
5412 DECODE : S0(2); // any decoder for FPU PUSH
5413 D0 : S1; // big decoder only
5414 FPU : S4;
5415 MEM : S3; // any mem
5416 %}
5417
5418 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5419 instruction_count(3);
5420 src1 : S3(read);
5421 src2 : S3(read);
5422 mem : S4(read);
5423 DECODE : S0; // any decoder for FPU PUSH
5424 D0 : S0(2); // big decoder only
5425 FPU : S4;
5426 MEM : S3(2); // any mem
5427 %}
5428
5429 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5430 instruction_count(2);
5431 src1 : S3(read);
5432 dst : S4(read);
5433 D0 : S0(2); // big decoder only
5434 MEM : S3(2); // any mem
5435 %}
5436
5437 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5438 instruction_count(3);
5439 src1 : S3(read);
5440 src2 : S3(read);
5441 dst : S4(read);
5442 D0 : S0(3); // big decoder only
5443 FPU : S4;
5444 MEM : S3(3); // any mem
5445 %}
5446
5447 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5448 instruction_count(3);
5449 src1 : S4(read);
5450 mem : S4(read);
5451 DECODE : S0; // any decoder for FPU PUSH
5452 D0 : S0(2); // big decoder only
5453 FPU : S4;
5454 MEM : S3(2); // any mem
5455 %}
5456
5457 // Float load constant
5458 pipe_class fpu_reg_con(regDPR dst) %{
5459 instruction_count(2);
5460 dst : S5(write);
5461 D0 : S0; // big decoder only for the load
5462 DECODE : S1; // any decoder for FPU POP
5463 FPU : S4;
5464 MEM : S3; // any mem
5465 %}
5466
5467 // Float load constant
5468 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5469 instruction_count(3);
5470 dst : S5(write);
5471 src : S3(read);
5472 D0 : S0; // big decoder only for the load
5473 DECODE : S1(2); // any decoder for FPU POP
5474 FPU : S4;
5475 MEM : S3; // any mem
5476 %}
5477
5478 // UnConditional branch
5479 pipe_class pipe_jmp( label labl ) %{
5480 single_instruction;
5481 BR : S3;
5482 %}
5483
5484 // Conditional branch
5485 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5486 single_instruction;
5487 cr : S1(read);
5488 BR : S3;
5489 %}
5490
5491 // Allocation idiom
5492 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5493 instruction_count(1); force_serialization;
5494 fixed_latency(6);
5495 heap_ptr : S3(read);
5496 DECODE : S0(3);
5497 D0 : S2;
5498 MEM : S3;
5499 ALU : S3(2);
5500 dst : S5(write);
5501 BR : S5;
5502 %}
5503
5504 // Generic big/slow expanded idiom
5505 pipe_class pipe_slow( ) %{
5506 instruction_count(10); multiple_bundles; force_serialization;
5507 fixed_latency(100);
5508 D0 : S0(2);
5509 MEM : S3(2);
5510 %}
5511
5512 // The real do-nothing guy
5513 pipe_class empty( ) %{
5514 instruction_count(0);
5515 %}
5516
5517 // Define the class for the Nop node
5518 define %{
5519 MachNop = empty;
5520 %}
5521
5522 %}
5523
5524 //----------INSTRUCTIONS-------------------------------------------------------
5525 //
5526 // match -- States which machine-independent subtree may be replaced
5527 // by this instruction.
5528 // ins_cost -- The estimated cost of this instruction is used by instruction
5529 // selection to identify a minimum cost tree of machine
5530 // instructions that matches a tree of machine-independent
5531 // instructions.
5532 // format -- A string providing the disassembly for this instruction.
5533 // The value of an instruction's operand may be inserted
5534 // by referring to it with a '$' prefix.
5535 // opcode -- Three instruction opcodes may be provided. These are referred
5536 // to within an encode class as $primary, $secondary, and $tertiary
5537 // respectively. The primary opcode is commonly used to
5538 // indicate the type of machine instruction, while secondary
5539 // and tertiary are often used for prefix options or addressing
5540 // modes.
5541 // ins_encode -- A list of encode classes with parameters. The encode class
5542 // name must have been defined in an 'enc_class' specification
5543 // in the encode section of the architecture description.
5544
5545 //----------BSWAP-Instruction--------------------------------------------------
5546 instruct bytes_reverse_int(rRegI dst) %{
5547 match(Set dst (ReverseBytesI dst));
5548
5549 format %{ "BSWAP $dst" %}
5550 opcode(0x0F, 0xC8);
5551 ins_encode( OpcP, OpcSReg(dst) );
5552 ins_pipe( ialu_reg );
5553 %}
5554
5555 instruct bytes_reverse_long(eRegL dst) %{
5556 match(Set dst (ReverseBytesL dst));
5557
5558 format %{ "BSWAP $dst.lo\n\t"
5559 "BSWAP $dst.hi\n\t"
5560 "XCHG $dst.lo $dst.hi" %}
5561
5562 ins_cost(125);
5563 ins_encode( bswap_long_bytes(dst) );
5564 ins_pipe( ialu_reg_reg);
5565 %}
5566
5567 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5568 match(Set dst (ReverseBytesUS dst));
5569 effect(KILL cr);
5570
5571 format %{ "BSWAP $dst\n\t"
5572 "SHR $dst,16\n\t" %}
5573 ins_encode %{
5574 __ bswapl($dst$$Register);
5575 __ shrl($dst$$Register, 16);
5576 %}
5577 ins_pipe( ialu_reg );
5578 %}
5579
5580 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5581 match(Set dst (ReverseBytesS dst));
5582 effect(KILL cr);
5583
5584 format %{ "BSWAP $dst\n\t"
5585 "SAR $dst,16\n\t" %}
5586 ins_encode %{
5587 __ bswapl($dst$$Register);
5588 __ sarl($dst$$Register, 16);
5589 %}
5590 ins_pipe( ialu_reg );
5591 %}
5592
5593
5594 //---------- Zeros Count Instructions ------------------------------------------
5595
5596 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5597 predicate(UseCountLeadingZerosInstruction);
5598 match(Set dst (CountLeadingZerosI src));
5599 effect(KILL cr);
5600
5601 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5602 ins_encode %{
5603 __ lzcntl($dst$$Register, $src$$Register);
5604 %}
5605 ins_pipe(ialu_reg);
5606 %}
5607
5608 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5609 predicate(!UseCountLeadingZerosInstruction);
5610 match(Set dst (CountLeadingZerosI src));
5611 effect(KILL cr);
5612
5613 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5614 "JNZ skip\n\t"
5615 "MOV $dst, -1\n"
5616 "skip:\n\t"
5617 "NEG $dst\n\t"
5618 "ADD $dst, 31" %}
5619 ins_encode %{
5620 Register Rdst = $dst$$Register;
5621 Register Rsrc = $src$$Register;
5622 Label skip;
5623 __ bsrl(Rdst, Rsrc);
5624 __ jccb(Assembler::notZero, skip);
5625 __ movl(Rdst, -1);
5626 __ bind(skip);
5627 __ negl(Rdst);
5628 __ addl(Rdst, BitsPerInt - 1);
5629 %}
5630 ins_pipe(ialu_reg);
5631 %}
5632
5633 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5634 predicate(UseCountLeadingZerosInstruction);
5635 match(Set dst (CountLeadingZerosL src));
5636 effect(TEMP dst, KILL cr);
5637
5638 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5639 "JNC done\n\t"
5640 "LZCNT $dst, $src.lo\n\t"
5641 "ADD $dst, 32\n"
5642 "done:" %}
5643 ins_encode %{
5644 Register Rdst = $dst$$Register;
5645 Register Rsrc = $src$$Register;
5646 Label done;
5647 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5648 __ jccb(Assembler::carryClear, done);
5649 __ lzcntl(Rdst, Rsrc);
5650 __ addl(Rdst, BitsPerInt);
5651 __ bind(done);
5652 %}
5653 ins_pipe(ialu_reg);
5654 %}
5655
5656 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5657 predicate(!UseCountLeadingZerosInstruction);
5658 match(Set dst (CountLeadingZerosL src));
5659 effect(TEMP dst, KILL cr);
5660
5661 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5662 "JZ msw_is_zero\n\t"
5663 "ADD $dst, 32\n\t"
5664 "JMP not_zero\n"
5665 "msw_is_zero:\n\t"
5666 "BSR $dst, $src.lo\n\t"
5667 "JNZ not_zero\n\t"
5668 "MOV $dst, -1\n"
5669 "not_zero:\n\t"
5670 "NEG $dst\n\t"
5671 "ADD $dst, 63\n" %}
5672 ins_encode %{
5673 Register Rdst = $dst$$Register;
5674 Register Rsrc = $src$$Register;
5675 Label msw_is_zero;
5676 Label not_zero;
5677 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5678 __ jccb(Assembler::zero, msw_is_zero);
5679 __ addl(Rdst, BitsPerInt);
5680 __ jmpb(not_zero);
5681 __ bind(msw_is_zero);
5682 __ bsrl(Rdst, Rsrc);
5683 __ jccb(Assembler::notZero, not_zero);
5684 __ movl(Rdst, -1);
5685 __ bind(not_zero);
5686 __ negl(Rdst);
5687 __ addl(Rdst, BitsPerLong - 1);
5688 %}
5689 ins_pipe(ialu_reg);
5690 %}
5691
5692 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5693 match(Set dst (CountTrailingZerosI src));
5694 effect(KILL cr);
5695
5696 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5697 "JNZ done\n\t"
5698 "MOV $dst, 32\n"
5699 "done:" %}
5700 ins_encode %{
5701 Register Rdst = $dst$$Register;
5702 Label done;
5703 __ bsfl(Rdst, $src$$Register);
5704 __ jccb(Assembler::notZero, done);
5705 __ movl(Rdst, BitsPerInt);
5706 __ bind(done);
5707 %}
5708 ins_pipe(ialu_reg);
5709 %}
5710
5711 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5712 match(Set dst (CountTrailingZerosL src));
5713 effect(TEMP dst, KILL cr);
5714
5715 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5716 "JNZ done\n\t"
5717 "BSF $dst, $src.hi\n\t"
5718 "JNZ msw_not_zero\n\t"
5719 "MOV $dst, 32\n"
5720 "msw_not_zero:\n\t"
5721 "ADD $dst, 32\n"
5722 "done:" %}
5723 ins_encode %{
5724 Register Rdst = $dst$$Register;
5725 Register Rsrc = $src$$Register;
5726 Label msw_not_zero;
5727 Label done;
5728 __ bsfl(Rdst, Rsrc);
5729 __ jccb(Assembler::notZero, done);
5730 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5731 __ jccb(Assembler::notZero, msw_not_zero);
5732 __ movl(Rdst, BitsPerInt);
5733 __ bind(msw_not_zero);
5734 __ addl(Rdst, BitsPerInt);
5735 __ bind(done);
5736 %}
5737 ins_pipe(ialu_reg);
5738 %}
5739
5740
5741 //---------- Population Count Instructions -------------------------------------
5742
5743 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5744 predicate(UsePopCountInstruction);
5745 match(Set dst (PopCountI src));
5746 effect(KILL cr);
5747
5748 format %{ "POPCNT $dst, $src" %}
5749 ins_encode %{
5750 __ popcntl($dst$$Register, $src$$Register);
5751 %}
5752 ins_pipe(ialu_reg);
5753 %}
5754
5755 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5756 predicate(UsePopCountInstruction);
5757 match(Set dst (PopCountI (LoadI mem)));
5758 effect(KILL cr);
5759
5760 format %{ "POPCNT $dst, $mem" %}
5761 ins_encode %{
5762 __ popcntl($dst$$Register, $mem$$Address);
5763 %}
5764 ins_pipe(ialu_reg);
5765 %}
5766
5767 // Note: Long.bitCount(long) returns an int.
5768 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5769 predicate(UsePopCountInstruction);
5770 match(Set dst (PopCountL src));
5771 effect(KILL cr, TEMP tmp, TEMP dst);
5772
5773 format %{ "POPCNT $dst, $src.lo\n\t"
5774 "POPCNT $tmp, $src.hi\n\t"
5775 "ADD $dst, $tmp" %}
5776 ins_encode %{
5777 __ popcntl($dst$$Register, $src$$Register);
5778 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5779 __ addl($dst$$Register, $tmp$$Register);
5780 %}
5781 ins_pipe(ialu_reg);
5782 %}
5783
5784 // Note: Long.bitCount(long) returns an int.
5785 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5786 predicate(UsePopCountInstruction);
5787 match(Set dst (PopCountL (LoadL mem)));
5788 effect(KILL cr, TEMP tmp, TEMP dst);
5789
5790 format %{ "POPCNT $dst, $mem\n\t"
5791 "POPCNT $tmp, $mem+4\n\t"
5792 "ADD $dst, $tmp" %}
5793 ins_encode %{
5794 //__ popcntl($dst$$Register, $mem$$Address$$first);
5795 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5796 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5797 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5798 __ addl($dst$$Register, $tmp$$Register);
5799 %}
5800 ins_pipe(ialu_reg);
5801 %}
5802
5803
5804 //----------Load/Store/Move Instructions---------------------------------------
5805 //----------Load Instructions--------------------------------------------------
5806 // Load Byte (8bit signed)
5807 instruct loadB(xRegI dst, memory mem) %{
5808 match(Set dst (LoadB mem));
5809
5810 ins_cost(125);
5811 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5812
5813 ins_encode %{
5814 __ movsbl($dst$$Register, $mem$$Address);
5815 %}
5816
5817 ins_pipe(ialu_reg_mem);
5818 %}
5819
5820 // Load Byte (8bit signed) into Long Register
5821 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5822 match(Set dst (ConvI2L (LoadB mem)));
5823 effect(KILL cr);
5824
5825 ins_cost(375);
5826 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5827 "MOV $dst.hi,$dst.lo\n\t"
5828 "SAR $dst.hi,7" %}
5829
5830 ins_encode %{
5831 __ movsbl($dst$$Register, $mem$$Address);
5832 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5833 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5834 %}
5835
5836 ins_pipe(ialu_reg_mem);
5837 %}
5838
5839 // Load Unsigned Byte (8bit UNsigned)
5840 instruct loadUB(xRegI dst, memory mem) %{
5841 match(Set dst (LoadUB mem));
5842
5843 ins_cost(125);
5844 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5845
5846 ins_encode %{
5847 __ movzbl($dst$$Register, $mem$$Address);
5848 %}
5849
5850 ins_pipe(ialu_reg_mem);
5851 %}
5852
5853 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5854 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5855 match(Set dst (ConvI2L (LoadUB mem)));
5856 effect(KILL cr);
5857
5858 ins_cost(250);
5859 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5860 "XOR $dst.hi,$dst.hi" %}
5861
5862 ins_encode %{
5863 Register Rdst = $dst$$Register;
5864 __ movzbl(Rdst, $mem$$Address);
5865 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5866 %}
5867
5868 ins_pipe(ialu_reg_mem);
5869 %}
5870
5871 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5872 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5873 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5874 effect(KILL cr);
5875
5876 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5877 "XOR $dst.hi,$dst.hi\n\t"
5878 "AND $dst.lo,$mask" %}
5879 ins_encode %{
5880 Register Rdst = $dst$$Register;
5881 __ movzbl(Rdst, $mem$$Address);
5882 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5883 __ andl(Rdst, $mask$$constant);
5884 %}
5885 ins_pipe(ialu_reg_mem);
5886 %}
5887
5888 // Load Short (16bit signed)
5889 instruct loadS(rRegI dst, memory mem) %{
5890 match(Set dst (LoadS mem));
5891
5892 ins_cost(125);
5893 format %{ "MOVSX $dst,$mem\t# short" %}
5894
5895 ins_encode %{
5896 __ movswl($dst$$Register, $mem$$Address);
5897 %}
5898
5899 ins_pipe(ialu_reg_mem);
5900 %}
5901
5902 // Load Short (16 bit signed) to Byte (8 bit signed)
5903 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5904 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5905
5906 ins_cost(125);
5907 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5908 ins_encode %{
5909 __ movsbl($dst$$Register, $mem$$Address);
5910 %}
5911 ins_pipe(ialu_reg_mem);
5912 %}
5913
5914 // Load Short (16bit signed) into Long Register
5915 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5916 match(Set dst (ConvI2L (LoadS mem)));
5917 effect(KILL cr);
5918
5919 ins_cost(375);
5920 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5921 "MOV $dst.hi,$dst.lo\n\t"
5922 "SAR $dst.hi,15" %}
5923
5924 ins_encode %{
5925 __ movswl($dst$$Register, $mem$$Address);
5926 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5927 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5928 %}
5929
5930 ins_pipe(ialu_reg_mem);
5931 %}
5932
5933 // Load Unsigned Short/Char (16bit unsigned)
5934 instruct loadUS(rRegI dst, memory mem) %{
5935 match(Set dst (LoadUS mem));
5936
5937 ins_cost(125);
5938 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5939
5940 ins_encode %{
5941 __ movzwl($dst$$Register, $mem$$Address);
5942 %}
5943
5944 ins_pipe(ialu_reg_mem);
5945 %}
5946
5947 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5948 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5949 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5950
5951 ins_cost(125);
5952 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5953 ins_encode %{
5954 __ movsbl($dst$$Register, $mem$$Address);
5955 %}
5956 ins_pipe(ialu_reg_mem);
5957 %}
5958
5959 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5960 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5961 match(Set dst (ConvI2L (LoadUS mem)));
5962 effect(KILL cr);
5963
5964 ins_cost(250);
5965 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5966 "XOR $dst.hi,$dst.hi" %}
5967
5968 ins_encode %{
5969 __ movzwl($dst$$Register, $mem$$Address);
5970 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5971 %}
5972
5973 ins_pipe(ialu_reg_mem);
5974 %}
5975
5976 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5977 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5978 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5979 effect(KILL cr);
5980
5981 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5982 "XOR $dst.hi,$dst.hi" %}
5983 ins_encode %{
5984 Register Rdst = $dst$$Register;
5985 __ movzbl(Rdst, $mem$$Address);
5986 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5987 %}
5988 ins_pipe(ialu_reg_mem);
5989 %}
5990
5991 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5992 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5993 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5994 effect(KILL cr);
5995
5996 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5997 "XOR $dst.hi,$dst.hi\n\t"
5998 "AND $dst.lo,$mask" %}
5999 ins_encode %{
6000 Register Rdst = $dst$$Register;
6001 __ movzwl(Rdst, $mem$$Address);
6002 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6003 __ andl(Rdst, $mask$$constant);
6004 %}
6005 ins_pipe(ialu_reg_mem);
6006 %}
6007
6008 // Load Integer
6009 instruct loadI(rRegI dst, memory mem) %{
6010 match(Set dst (LoadI mem));
6011
6012 ins_cost(125);
6013 format %{ "MOV $dst,$mem\t# int" %}
6014
6015 ins_encode %{
6016 __ movl($dst$$Register, $mem$$Address);
6017 %}
6018
6019 ins_pipe(ialu_reg_mem);
6020 %}
6021
6022 // Load Integer (32 bit signed) to Byte (8 bit signed)
6023 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6024 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6025
6026 ins_cost(125);
6027 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6028 ins_encode %{
6029 __ movsbl($dst$$Register, $mem$$Address);
6030 %}
6031 ins_pipe(ialu_reg_mem);
6032 %}
6033
6034 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6035 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6036 match(Set dst (AndI (LoadI mem) mask));
6037
6038 ins_cost(125);
6039 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6040 ins_encode %{
6041 __ movzbl($dst$$Register, $mem$$Address);
6042 %}
6043 ins_pipe(ialu_reg_mem);
6044 %}
6045
6046 // Load Integer (32 bit signed) to Short (16 bit signed)
6047 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6048 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6049
6050 ins_cost(125);
6051 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6052 ins_encode %{
6053 __ movswl($dst$$Register, $mem$$Address);
6054 %}
6055 ins_pipe(ialu_reg_mem);
6056 %}
6057
6058 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6059 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6060 match(Set dst (AndI (LoadI mem) mask));
6061
6062 ins_cost(125);
6063 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6064 ins_encode %{
6065 __ movzwl($dst$$Register, $mem$$Address);
6066 %}
6067 ins_pipe(ialu_reg_mem);
6068 %}
6069
6070 // Load Integer into Long Register
6071 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6072 match(Set dst (ConvI2L (LoadI mem)));
6073 effect(KILL cr);
6074
6075 ins_cost(375);
6076 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6077 "MOV $dst.hi,$dst.lo\n\t"
6078 "SAR $dst.hi,31" %}
6079
6080 ins_encode %{
6081 __ movl($dst$$Register, $mem$$Address);
6082 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6083 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6084 %}
6085
6086 ins_pipe(ialu_reg_mem);
6087 %}
6088
6089 // Load Integer with mask 0xFF into Long Register
6090 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6091 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6092 effect(KILL cr);
6093
6094 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6095 "XOR $dst.hi,$dst.hi" %}
6096 ins_encode %{
6097 Register Rdst = $dst$$Register;
6098 __ movzbl(Rdst, $mem$$Address);
6099 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6100 %}
6101 ins_pipe(ialu_reg_mem);
6102 %}
6103
6104 // Load Integer with mask 0xFFFF into Long Register
6105 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6106 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6107 effect(KILL cr);
6108
6109 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6110 "XOR $dst.hi,$dst.hi" %}
6111 ins_encode %{
6112 Register Rdst = $dst$$Register;
6113 __ movzwl(Rdst, $mem$$Address);
6114 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6115 %}
6116 ins_pipe(ialu_reg_mem);
6117 %}
6118
6119 // Load Integer with 32-bit mask into Long Register
6120 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6121 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6122 effect(KILL cr);
6123
6124 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6125 "XOR $dst.hi,$dst.hi\n\t"
6126 "AND $dst.lo,$mask" %}
6127 ins_encode %{
6128 Register Rdst = $dst$$Register;
6129 __ movl(Rdst, $mem$$Address);
6130 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6131 __ andl(Rdst, $mask$$constant);
6132 %}
6133 ins_pipe(ialu_reg_mem);
6134 %}
6135
6136 // Load Unsigned Integer into Long Register
6137 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6138 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6139 effect(KILL cr);
6140
6141 ins_cost(250);
6142 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6143 "XOR $dst.hi,$dst.hi" %}
6144
6145 ins_encode %{
6146 __ movl($dst$$Register, $mem$$Address);
6147 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6148 %}
6149
6150 ins_pipe(ialu_reg_mem);
6151 %}
6152
6153 // Load Long. Cannot clobber address while loading, so restrict address
6154 // register to ESI
6155 instruct loadL(eRegL dst, load_long_memory mem) %{
6156 predicate(!((LoadLNode*)n)->require_atomic_access());
6157 match(Set dst (LoadL mem));
6158
6159 ins_cost(250);
6160 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6161 "MOV $dst.hi,$mem+4" %}
6162
6163 ins_encode %{
6164 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6165 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6166 __ movl($dst$$Register, Amemlo);
6167 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6168 %}
6169
6170 ins_pipe(ialu_reg_long_mem);
6171 %}
6172
6173 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6174 // then store it down to the stack and reload on the int
6175 // side.
6176 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6177 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6178 match(Set dst (LoadL mem));
6179
6180 ins_cost(200);
6181 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6182 "FISTp $dst" %}
6183 ins_encode(enc_loadL_volatile(mem,dst));
6184 ins_pipe( fpu_reg_mem );
6185 %}
6186
6187 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6188 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6189 match(Set dst (LoadL mem));
6190 effect(TEMP tmp);
6191 ins_cost(180);
6192 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6193 "MOVSD $dst,$tmp" %}
6194 ins_encode %{
6195 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6196 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6197 %}
6198 ins_pipe( pipe_slow );
6199 %}
6200
6201 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6202 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6203 match(Set dst (LoadL mem));
6204 effect(TEMP tmp);
6205 ins_cost(160);
6206 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6207 "MOVD $dst.lo,$tmp\n\t"
6208 "PSRLQ $tmp,32\n\t"
6209 "MOVD $dst.hi,$tmp" %}
6210 ins_encode %{
6211 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6212 __ movdl($dst$$Register, $tmp$$XMMRegister);
6213 __ psrlq($tmp$$XMMRegister, 32);
6214 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6215 %}
6216 ins_pipe( pipe_slow );
6217 %}
6218
6219 // Load Range
6220 instruct loadRange(rRegI dst, memory mem) %{
6221 match(Set dst (LoadRange mem));
6222
6223 ins_cost(125);
6224 format %{ "MOV $dst,$mem" %}
6225 opcode(0x8B);
6226 ins_encode( OpcP, RegMem(dst,mem));
6227 ins_pipe( ialu_reg_mem );
6228 %}
6229
6230
6231 // Load Pointer
6232 instruct loadP(eRegP dst, memory mem) %{
6233 match(Set dst (LoadP mem));
6234
6235 ins_cost(125);
6236 format %{ "MOV $dst,$mem" %}
6237 opcode(0x8B);
6238 ins_encode( OpcP, RegMem(dst,mem));
6239 ins_pipe( ialu_reg_mem );
6240 %}
6241
6242 // Load Klass Pointer
6243 instruct loadKlass(eRegP dst, memory mem) %{
6244 match(Set dst (LoadKlass mem));
6245
6246 ins_cost(125);
6247 format %{ "MOV $dst,$mem" %}
6248 opcode(0x8B);
6249 ins_encode( OpcP, RegMem(dst,mem));
6250 ins_pipe( ialu_reg_mem );
6251 %}
6252
6253 // Load Double
6254 instruct loadDPR(regDPR dst, memory mem) %{
6255 predicate(UseSSE<=1);
6256 match(Set dst (LoadD mem));
6257
6258 ins_cost(150);
6259 format %{ "FLD_D ST,$mem\n\t"
6260 "FSTP $dst" %}
6261 opcode(0xDD); /* DD /0 */
6262 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6263 Pop_Reg_DPR(dst) );
6264 ins_pipe( fpu_reg_mem );
6265 %}
6266
6267 // Load Double to XMM
6268 instruct loadD(regD dst, memory mem) %{
6269 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6270 match(Set dst (LoadD mem));
6271 ins_cost(145);
6272 format %{ "MOVSD $dst,$mem" %}
6273 ins_encode %{
6274 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6275 %}
6276 ins_pipe( pipe_slow );
6277 %}
6278
6279 instruct loadD_partial(regD dst, memory mem) %{
6280 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6281 match(Set dst (LoadD mem));
6282 ins_cost(145);
6283 format %{ "MOVLPD $dst,$mem" %}
6284 ins_encode %{
6285 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6286 %}
6287 ins_pipe( pipe_slow );
6288 %}
6289
6290 // Load to XMM register (single-precision floating point)
6291 // MOVSS instruction
6292 instruct loadF(regF dst, memory mem) %{
6293 predicate(UseSSE>=1);
6294 match(Set dst (LoadF mem));
6295 ins_cost(145);
6296 format %{ "MOVSS $dst,$mem" %}
6297 ins_encode %{
6298 __ movflt ($dst$$XMMRegister, $mem$$Address);
6299 %}
6300 ins_pipe( pipe_slow );
6301 %}
6302
6303 // Load Float
6304 instruct loadFPR(regFPR dst, memory mem) %{
6305 predicate(UseSSE==0);
6306 match(Set dst (LoadF mem));
6307
6308 ins_cost(150);
6309 format %{ "FLD_S ST,$mem\n\t"
6310 "FSTP $dst" %}
6311 opcode(0xD9); /* D9 /0 */
6312 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6313 Pop_Reg_FPR(dst) );
6314 ins_pipe( fpu_reg_mem );
6315 %}
6316
6317 // Load Effective Address
6318 instruct leaP8(eRegP dst, indOffset8 mem) %{
6319 match(Set dst mem);
6320
6321 ins_cost(110);
6322 format %{ "LEA $dst,$mem" %}
6323 opcode(0x8D);
6324 ins_encode( OpcP, RegMem(dst,mem));
6325 ins_pipe( ialu_reg_reg_fat );
6326 %}
6327
6328 instruct leaP32(eRegP dst, indOffset32 mem) %{
6329 match(Set dst mem);
6330
6331 ins_cost(110);
6332 format %{ "LEA $dst,$mem" %}
6333 opcode(0x8D);
6334 ins_encode( OpcP, RegMem(dst,mem));
6335 ins_pipe( ialu_reg_reg_fat );
6336 %}
6337
6338 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6339 match(Set dst mem);
6340
6341 ins_cost(110);
6342 format %{ "LEA $dst,$mem" %}
6343 opcode(0x8D);
6344 ins_encode( OpcP, RegMem(dst,mem));
6345 ins_pipe( ialu_reg_reg_fat );
6346 %}
6347
6348 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6349 match(Set dst mem);
6350
6351 ins_cost(110);
6352 format %{ "LEA $dst,$mem" %}
6353 opcode(0x8D);
6354 ins_encode( OpcP, RegMem(dst,mem));
6355 ins_pipe( ialu_reg_reg_fat );
6356 %}
6357
6358 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6359 match(Set dst mem);
6360
6361 ins_cost(110);
6362 format %{ "LEA $dst,$mem" %}
6363 opcode(0x8D);
6364 ins_encode( OpcP, RegMem(dst,mem));
6365 ins_pipe( ialu_reg_reg_fat );
6366 %}
6367
6368 // Load Constant
6369 instruct loadConI(rRegI dst, immI src) %{
6370 match(Set dst src);
6371
6372 format %{ "MOV $dst,$src" %}
6373 ins_encode( LdImmI(dst, src) );
6374 ins_pipe( ialu_reg_fat );
6375 %}
6376
6377 // Load Constant zero
6378 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6379 match(Set dst src);
6380 effect(KILL cr);
6381
6382 ins_cost(50);
6383 format %{ "XOR $dst,$dst" %}
6384 opcode(0x33); /* + rd */
6385 ins_encode( OpcP, RegReg( dst, dst ) );
6386 ins_pipe( ialu_reg );
6387 %}
6388
6389 instruct loadConP(eRegP dst, immP src) %{
6390 match(Set dst src);
6391
6392 format %{ "MOV $dst,$src" %}
6393 opcode(0xB8); /* + rd */
6394 ins_encode( LdImmP(dst, src) );
6395 ins_pipe( ialu_reg_fat );
6396 %}
6397
6398 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6399 match(Set dst src);
6400 effect(KILL cr);
6401 ins_cost(200);
6402 format %{ "MOV $dst.lo,$src.lo\n\t"
6403 "MOV $dst.hi,$src.hi" %}
6404 opcode(0xB8);
6405 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6406 ins_pipe( ialu_reg_long_fat );
6407 %}
6408
6409 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6410 match(Set dst src);
6411 effect(KILL cr);
6412 ins_cost(150);
6413 format %{ "XOR $dst.lo,$dst.lo\n\t"
6414 "XOR $dst.hi,$dst.hi" %}
6415 opcode(0x33,0x33);
6416 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6417 ins_pipe( ialu_reg_long );
6418 %}
6419
6420 // The instruction usage is guarded by predicate in operand immFPR().
6421 instruct loadConFPR(regFPR dst, immFPR con) %{
6422 match(Set dst con);
6423 ins_cost(125);
6424 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6425 "FSTP $dst" %}
6426 ins_encode %{
6427 __ fld_s($constantaddress($con));
6428 __ fstp_d($dst$$reg);
6429 %}
6430 ins_pipe(fpu_reg_con);
6431 %}
6432
6433 // The instruction usage is guarded by predicate in operand immFPR0().
6434 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6435 match(Set dst con);
6436 ins_cost(125);
6437 format %{ "FLDZ ST\n\t"
6438 "FSTP $dst" %}
6439 ins_encode %{
6440 __ fldz();
6441 __ fstp_d($dst$$reg);
6442 %}
6443 ins_pipe(fpu_reg_con);
6444 %}
6445
6446 // The instruction usage is guarded by predicate in operand immFPR1().
6447 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6448 match(Set dst con);
6449 ins_cost(125);
6450 format %{ "FLD1 ST\n\t"
6451 "FSTP $dst" %}
6452 ins_encode %{
6453 __ fld1();
6454 __ fstp_d($dst$$reg);
6455 %}
6456 ins_pipe(fpu_reg_con);
6457 %}
6458
6459 // The instruction usage is guarded by predicate in operand immF().
6460 instruct loadConF(regF dst, immF con) %{
6461 match(Set dst con);
6462 ins_cost(125);
6463 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6464 ins_encode %{
6465 __ movflt($dst$$XMMRegister, $constantaddress($con));
6466 %}
6467 ins_pipe(pipe_slow);
6468 %}
6469
6470 // The instruction usage is guarded by predicate in operand immF0().
6471 instruct loadConF0(regF dst, immF0 src) %{
6472 match(Set dst src);
6473 ins_cost(100);
6474 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6475 ins_encode %{
6476 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6477 %}
6478 ins_pipe(pipe_slow);
6479 %}
6480
6481 // The instruction usage is guarded by predicate in operand immDPR().
6482 instruct loadConDPR(regDPR dst, immDPR con) %{
6483 match(Set dst con);
6484 ins_cost(125);
6485
6486 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6487 "FSTP $dst" %}
6488 ins_encode %{
6489 __ fld_d($constantaddress($con));
6490 __ fstp_d($dst$$reg);
6491 %}
6492 ins_pipe(fpu_reg_con);
6493 %}
6494
6495 // The instruction usage is guarded by predicate in operand immDPR0().
6496 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6497 match(Set dst con);
6498 ins_cost(125);
6499
6500 format %{ "FLDZ ST\n\t"
6501 "FSTP $dst" %}
6502 ins_encode %{
6503 __ fldz();
6504 __ fstp_d($dst$$reg);
6505 %}
6506 ins_pipe(fpu_reg_con);
6507 %}
6508
6509 // The instruction usage is guarded by predicate in operand immDPR1().
6510 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6511 match(Set dst con);
6512 ins_cost(125);
6513
6514 format %{ "FLD1 ST\n\t"
6515 "FSTP $dst" %}
6516 ins_encode %{
6517 __ fld1();
6518 __ fstp_d($dst$$reg);
6519 %}
6520 ins_pipe(fpu_reg_con);
6521 %}
6522
6523 // The instruction usage is guarded by predicate in operand immD().
6524 instruct loadConD(regD dst, immD con) %{
6525 match(Set dst con);
6526 ins_cost(125);
6527 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6528 ins_encode %{
6529 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6530 %}
6531 ins_pipe(pipe_slow);
6532 %}
6533
6534 // The instruction usage is guarded by predicate in operand immD0().
6535 instruct loadConD0(regD dst, immD0 src) %{
6536 match(Set dst src);
6537 ins_cost(100);
6538 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6539 ins_encode %{
6540 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6541 %}
6542 ins_pipe( pipe_slow );
6543 %}
6544
6545 // Load Stack Slot
6546 instruct loadSSI(rRegI dst, stackSlotI src) %{
6547 match(Set dst src);
6548 ins_cost(125);
6549
6550 format %{ "MOV $dst,$src" %}
6551 opcode(0x8B);
6552 ins_encode( OpcP, RegMem(dst,src));
6553 ins_pipe( ialu_reg_mem );
6554 %}
6555
6556 instruct loadSSL(eRegL dst, stackSlotL src) %{
6557 match(Set dst src);
6558
6559 ins_cost(200);
6560 format %{ "MOV $dst,$src.lo\n\t"
6561 "MOV $dst+4,$src.hi" %}
6562 opcode(0x8B, 0x8B);
6563 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6564 ins_pipe( ialu_mem_long_reg );
6565 %}
6566
6567 // Load Stack Slot
6568 instruct loadSSP(eRegP dst, stackSlotP src) %{
6569 match(Set dst src);
6570 ins_cost(125);
6571
6572 format %{ "MOV $dst,$src" %}
6573 opcode(0x8B);
6574 ins_encode( OpcP, RegMem(dst,src));
6575 ins_pipe( ialu_reg_mem );
6576 %}
6577
6578 // Load Stack Slot
6579 instruct loadSSF(regFPR dst, stackSlotF src) %{
6580 match(Set dst src);
6581 ins_cost(125);
6582
6583 format %{ "FLD_S $src\n\t"
6584 "FSTP $dst" %}
6585 opcode(0xD9); /* D9 /0, FLD m32real */
6586 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6587 Pop_Reg_FPR(dst) );
6588 ins_pipe( fpu_reg_mem );
6589 %}
6590
6591 // Load Stack Slot
6592 instruct loadSSD(regDPR dst, stackSlotD src) %{
6593 match(Set dst src);
6594 ins_cost(125);
6595
6596 format %{ "FLD_D $src\n\t"
6597 "FSTP $dst" %}
6598 opcode(0xDD); /* DD /0, FLD m64real */
6599 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6600 Pop_Reg_DPR(dst) );
6601 ins_pipe( fpu_reg_mem );
6602 %}
6603
6604 // Prefetch instructions.
6605 // Must be safe to execute with invalid address (cannot fault).
6606
6607 instruct prefetchr0( memory mem ) %{
6608 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6609 match(PrefetchRead mem);
6610 ins_cost(0);
6611 size(0);
6612 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6613 ins_encode();
6614 ins_pipe(empty);
6615 %}
6616
6617 instruct prefetchr( memory mem ) %{
6618 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6619 match(PrefetchRead mem);
6620 ins_cost(100);
6621
6622 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6623 ins_encode %{
6624 __ prefetchr($mem$$Address);
6625 %}
6626 ins_pipe(ialu_mem);
6627 %}
6628
6629 instruct prefetchrNTA( memory mem ) %{
6630 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6631 match(PrefetchRead mem);
6632 ins_cost(100);
6633
6634 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6635 ins_encode %{
6636 __ prefetchnta($mem$$Address);
6637 %}
6638 ins_pipe(ialu_mem);
6639 %}
6640
6641 instruct prefetchrT0( memory mem ) %{
6642 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6643 match(PrefetchRead mem);
6644 ins_cost(100);
6645
6646 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6647 ins_encode %{
6648 __ prefetcht0($mem$$Address);
6649 %}
6650 ins_pipe(ialu_mem);
6651 %}
6652
6653 instruct prefetchrT2( memory mem ) %{
6654 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6655 match(PrefetchRead mem);
6656 ins_cost(100);
6657
6658 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6659 ins_encode %{
6660 __ prefetcht2($mem$$Address);
6661 %}
6662 ins_pipe(ialu_mem);
6663 %}
6664
6665 instruct prefetchw0( memory mem ) %{
6666 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6667 match(PrefetchWrite mem);
6668 ins_cost(0);
6669 size(0);
6670 format %{ "Prefetch (non-SSE is empty encoding)" %}
6671 ins_encode();
6672 ins_pipe(empty);
6673 %}
6674
6675 instruct prefetchw( memory mem ) %{
6676 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6677 match( PrefetchWrite mem );
6678 ins_cost(100);
6679
6680 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6681 ins_encode %{
6682 __ prefetchw($mem$$Address);
6683 %}
6684 ins_pipe(ialu_mem);
6685 %}
6686
6687 instruct prefetchwNTA( memory mem ) %{
6688 predicate(UseSSE>=1);
6689 match(PrefetchWrite mem);
6690 ins_cost(100);
6691
6692 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6693 ins_encode %{
6694 __ prefetchnta($mem$$Address);
6695 %}
6696 ins_pipe(ialu_mem);
6697 %}
6698
6699 // Prefetch instructions for allocation.
6700
6701 instruct prefetchAlloc0( memory mem ) %{
6702 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6703 match(PrefetchAllocation mem);
6704 ins_cost(0);
6705 size(0);
6706 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6707 ins_encode();
6708 ins_pipe(empty);
6709 %}
6710
6711 instruct prefetchAlloc( memory mem ) %{
6712 predicate(AllocatePrefetchInstr==3);
6713 match( PrefetchAllocation mem );
6714 ins_cost(100);
6715
6716 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6717 ins_encode %{
6718 __ prefetchw($mem$$Address);
6719 %}
6720 ins_pipe(ialu_mem);
6721 %}
6722
6723 instruct prefetchAllocNTA( memory mem ) %{
6724 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6725 match(PrefetchAllocation mem);
6726 ins_cost(100);
6727
6728 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6729 ins_encode %{
6730 __ prefetchnta($mem$$Address);
6731 %}
6732 ins_pipe(ialu_mem);
6733 %}
6734
6735 instruct prefetchAllocT0( memory mem ) %{
6736 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6737 match(PrefetchAllocation mem);
6738 ins_cost(100);
6739
6740 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6741 ins_encode %{
6742 __ prefetcht0($mem$$Address);
6743 %}
6744 ins_pipe(ialu_mem);
6745 %}
6746
6747 instruct prefetchAllocT2( memory mem ) %{
6748 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6749 match(PrefetchAllocation mem);
6750 ins_cost(100);
6751
6752 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6753 ins_encode %{
6754 __ prefetcht2($mem$$Address);
6755 %}
6756 ins_pipe(ialu_mem);
6757 %}
6758
6759 //----------Store Instructions-------------------------------------------------
6760
6761 // Store Byte
6762 instruct storeB(memory mem, xRegI src) %{
6763 match(Set mem (StoreB mem src));
6764
6765 ins_cost(125);
6766 format %{ "MOV8 $mem,$src" %}
6767 opcode(0x88);
6768 ins_encode( OpcP, RegMem( src, mem ) );
6769 ins_pipe( ialu_mem_reg );
6770 %}
6771
6772 // Store Char/Short
6773 instruct storeC(memory mem, rRegI src) %{
6774 match(Set mem (StoreC mem src));
6775
6776 ins_cost(125);
6777 format %{ "MOV16 $mem,$src" %}
6778 opcode(0x89, 0x66);
6779 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6780 ins_pipe( ialu_mem_reg );
6781 %}
6782
6783 // Store Integer
6784 instruct storeI(memory mem, rRegI src) %{
6785 match(Set mem (StoreI mem src));
6786
6787 ins_cost(125);
6788 format %{ "MOV $mem,$src" %}
6789 opcode(0x89);
6790 ins_encode( OpcP, RegMem( src, mem ) );
6791 ins_pipe( ialu_mem_reg );
6792 %}
6793
6794 // Store Long
6795 instruct storeL(long_memory mem, eRegL src) %{
6796 predicate(!((StoreLNode*)n)->require_atomic_access());
6797 match(Set mem (StoreL mem src));
6798
6799 ins_cost(200);
6800 format %{ "MOV $mem,$src.lo\n\t"
6801 "MOV $mem+4,$src.hi" %}
6802 opcode(0x89, 0x89);
6803 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6804 ins_pipe( ialu_mem_long_reg );
6805 %}
6806
6807 // Store Long to Integer
6808 instruct storeL2I(memory mem, eRegL src) %{
6809 match(Set mem (StoreI mem (ConvL2I src)));
6810
6811 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6812 ins_encode %{
6813 __ movl($mem$$Address, $src$$Register);
6814 %}
6815 ins_pipe(ialu_mem_reg);
6816 %}
6817
6818 // Volatile Store Long. Must be atomic, so move it into
6819 // the FP TOS and then do a 64-bit FIST. Has to probe the
6820 // target address before the store (for null-ptr checks)
6821 // so the memory operand is used twice in the encoding.
6822 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6823 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6824 match(Set mem (StoreL mem src));
6825 effect( KILL cr );
6826 ins_cost(400);
6827 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6828 "FILD $src\n\t"
6829 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6830 opcode(0x3B);
6831 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6832 ins_pipe( fpu_reg_mem );
6833 %}
6834
6835 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6836 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6837 match(Set mem (StoreL mem src));
6838 effect( TEMP tmp, KILL cr );
6839 ins_cost(380);
6840 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6841 "MOVSD $tmp,$src\n\t"
6842 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6843 ins_encode %{
6844 __ cmpl(rax, $mem$$Address);
6845 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6846 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6847 %}
6848 ins_pipe( pipe_slow );
6849 %}
6850
6851 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6852 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6853 match(Set mem (StoreL mem src));
6854 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6855 ins_cost(360);
6856 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6857 "MOVD $tmp,$src.lo\n\t"
6858 "MOVD $tmp2,$src.hi\n\t"
6859 "PUNPCKLDQ $tmp,$tmp2\n\t"
6860 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6861 ins_encode %{
6862 __ cmpl(rax, $mem$$Address);
6863 __ movdl($tmp$$XMMRegister, $src$$Register);
6864 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6865 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6866 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6867 %}
6868 ins_pipe( pipe_slow );
6869 %}
6870
6871 // Store Pointer; for storing unknown oops and raw pointers
6872 instruct storeP(memory mem, anyRegP src) %{
6873 match(Set mem (StoreP mem src));
6874
6875 ins_cost(125);
6876 format %{ "MOV $mem,$src" %}
6877 opcode(0x89);
6878 ins_encode( OpcP, RegMem( src, mem ) );
6879 ins_pipe( ialu_mem_reg );
6880 %}
6881
6882 // Store Integer Immediate
6883 instruct storeImmI(memory mem, immI src) %{
6884 match(Set mem (StoreI mem src));
6885
6886 ins_cost(150);
6887 format %{ "MOV $mem,$src" %}
6888 opcode(0xC7); /* C7 /0 */
6889 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6890 ins_pipe( ialu_mem_imm );
6891 %}
6892
6893 // Store Short/Char Immediate
6894 instruct storeImmI16(memory mem, immI16 src) %{
6895 predicate(UseStoreImmI16);
6896 match(Set mem (StoreC mem src));
6897
6898 ins_cost(150);
6899 format %{ "MOV16 $mem,$src" %}
6900 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6901 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6902 ins_pipe( ialu_mem_imm );
6903 %}
6904
6905 // Store Pointer Immediate; null pointers or constant oops that do not
6906 // need card-mark barriers.
6907 instruct storeImmP(memory mem, immP src) %{
6908 match(Set mem (StoreP mem src));
6909
6910 ins_cost(150);
6911 format %{ "MOV $mem,$src" %}
6912 opcode(0xC7); /* C7 /0 */
6913 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6914 ins_pipe( ialu_mem_imm );
6915 %}
6916
6917 // Store Byte Immediate
6918 instruct storeImmB(memory mem, immI8 src) %{
6919 match(Set mem (StoreB mem src));
6920
6921 ins_cost(150);
6922 format %{ "MOV8 $mem,$src" %}
6923 opcode(0xC6); /* C6 /0 */
6924 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6925 ins_pipe( ialu_mem_imm );
6926 %}
6927
6928 // Store CMS card-mark Immediate
6929 instruct storeImmCM(memory mem, immI8 src) %{
6930 match(Set mem (StoreCM mem src));
6931
6932 ins_cost(150);
6933 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6934 opcode(0xC6); /* C6 /0 */
6935 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6936 ins_pipe( ialu_mem_imm );
6937 %}
6938
6939 // Store Double
6940 instruct storeDPR( memory mem, regDPR1 src) %{
6941 predicate(UseSSE<=1);
6942 match(Set mem (StoreD mem src));
6943
6944 ins_cost(100);
6945 format %{ "FST_D $mem,$src" %}
6946 opcode(0xDD); /* DD /2 */
6947 ins_encode( enc_FPR_store(mem,src) );
6948 ins_pipe( fpu_mem_reg );
6949 %}
6950
6951 // Store double does rounding on x86
6952 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6953 predicate(UseSSE<=1);
6954 match(Set mem (StoreD mem (RoundDouble src)));
6955
6956 ins_cost(100);
6957 format %{ "FST_D $mem,$src\t# round" %}
6958 opcode(0xDD); /* DD /2 */
6959 ins_encode( enc_FPR_store(mem,src) );
6960 ins_pipe( fpu_mem_reg );
6961 %}
6962
6963 // Store XMM register to memory (double-precision floating points)
6964 // MOVSD instruction
6965 instruct storeD(memory mem, regD src) %{
6966 predicate(UseSSE>=2);
6967 match(Set mem (StoreD mem src));
6968 ins_cost(95);
6969 format %{ "MOVSD $mem,$src" %}
6970 ins_encode %{
6971 __ movdbl($mem$$Address, $src$$XMMRegister);
6972 %}
6973 ins_pipe( pipe_slow );
6974 %}
6975
6976 // Store XMM register to memory (single-precision floating point)
6977 // MOVSS instruction
6978 instruct storeF(memory mem, regF src) %{
6979 predicate(UseSSE>=1);
6980 match(Set mem (StoreF mem src));
6981 ins_cost(95);
6982 format %{ "MOVSS $mem,$src" %}
6983 ins_encode %{
6984 __ movflt($mem$$Address, $src$$XMMRegister);
6985 %}
6986 ins_pipe( pipe_slow );
6987 %}
6988
6989 // Store Float
6990 instruct storeFPR( memory mem, regFPR1 src) %{
6991 predicate(UseSSE==0);
6992 match(Set mem (StoreF mem src));
6993
6994 ins_cost(100);
6995 format %{ "FST_S $mem,$src" %}
6996 opcode(0xD9); /* D9 /2 */
6997 ins_encode( enc_FPR_store(mem,src) );
6998 ins_pipe( fpu_mem_reg );
6999 %}
7000
7001 // Store Float does rounding on x86
7002 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7003 predicate(UseSSE==0);
7004 match(Set mem (StoreF mem (RoundFloat src)));
7005
7006 ins_cost(100);
7007 format %{ "FST_S $mem,$src\t# round" %}
7008 opcode(0xD9); /* D9 /2 */
7009 ins_encode( enc_FPR_store(mem,src) );
7010 ins_pipe( fpu_mem_reg );
7011 %}
7012
7013 // Store Float does rounding on x86
7014 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7015 predicate(UseSSE<=1);
7016 match(Set mem (StoreF mem (ConvD2F src)));
7017
7018 ins_cost(100);
7019 format %{ "FST_S $mem,$src\t# D-round" %}
7020 opcode(0xD9); /* D9 /2 */
7021 ins_encode( enc_FPR_store(mem,src) );
7022 ins_pipe( fpu_mem_reg );
7023 %}
7024
7025 // Store immediate Float value (it is faster than store from FPU register)
7026 // The instruction usage is guarded by predicate in operand immFPR().
7027 instruct storeFPR_imm( memory mem, immFPR src) %{
7028 match(Set mem (StoreF mem src));
7029
7030 ins_cost(50);
7031 format %{ "MOV $mem,$src\t# store float" %}
7032 opcode(0xC7); /* C7 /0 */
7033 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7034 ins_pipe( ialu_mem_imm );
7035 %}
7036
7037 // Store immediate Float value (it is faster than store from XMM register)
7038 // The instruction usage is guarded by predicate in operand immF().
7039 instruct storeF_imm( memory mem, immF src) %{
7040 match(Set mem (StoreF mem src));
7041
7042 ins_cost(50);
7043 format %{ "MOV $mem,$src\t# store float" %}
7044 opcode(0xC7); /* C7 /0 */
7045 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7046 ins_pipe( ialu_mem_imm );
7047 %}
7048
7049 // Store Integer to stack slot
7050 instruct storeSSI(stackSlotI dst, rRegI src) %{
7051 match(Set dst src);
7052
7053 ins_cost(100);
7054 format %{ "MOV $dst,$src" %}
7055 opcode(0x89);
7056 ins_encode( OpcPRegSS( dst, src ) );
7057 ins_pipe( ialu_mem_reg );
7058 %}
7059
7060 // Store Integer to stack slot
7061 instruct storeSSP(stackSlotP dst, eRegP src) %{
7062 match(Set dst src);
7063
7064 ins_cost(100);
7065 format %{ "MOV $dst,$src" %}
7066 opcode(0x89);
7067 ins_encode( OpcPRegSS( dst, src ) );
7068 ins_pipe( ialu_mem_reg );
7069 %}
7070
7071 // Store Long to stack slot
7072 instruct storeSSL(stackSlotL dst, eRegL src) %{
7073 match(Set dst src);
7074
7075 ins_cost(200);
7076 format %{ "MOV $dst,$src.lo\n\t"
7077 "MOV $dst+4,$src.hi" %}
7078 opcode(0x89, 0x89);
7079 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7080 ins_pipe( ialu_mem_long_reg );
7081 %}
7082
7083 //----------MemBar Instructions-----------------------------------------------
7084 // Memory barrier flavors
7085
7086 instruct membar_acquire() %{
7087 match(MemBarAcquire);
7088 ins_cost(400);
7089
7090 size(0);
7091 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7092 ins_encode();
7093 ins_pipe(empty);
7094 %}
7095
7096 instruct membar_acquire_lock() %{
7097 match(MemBarAcquireLock);
7098 ins_cost(0);
7099
7100 size(0);
7101 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7102 ins_encode( );
7103 ins_pipe(empty);
7104 %}
7105
7106 instruct membar_release() %{
7107 match(MemBarRelease);
7108 ins_cost(400);
7109
7110 size(0);
7111 format %{ "MEMBAR-release ! (empty encoding)" %}
7112 ins_encode( );
7113 ins_pipe(empty);
7114 %}
7115
7116 instruct membar_release_lock() %{
7117 match(MemBarReleaseLock);
7118 ins_cost(0);
7119
7120 size(0);
7121 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7122 ins_encode( );
7123 ins_pipe(empty);
7124 %}
7125
7126 instruct membar_volatile(eFlagsReg cr) %{
7127 match(MemBarVolatile);
7128 effect(KILL cr);
7129 ins_cost(400);
7130
7131 format %{
7132 $$template
7133 if (os::is_MP()) {
7134 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7135 } else {
7136 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7137 }
7138 %}
7139 ins_encode %{
7140 __ membar(Assembler::StoreLoad);
7141 %}
7142 ins_pipe(pipe_slow);
7143 %}
7144
7145 instruct unnecessary_membar_volatile() %{
7146 match(MemBarVolatile);
7147 predicate(Matcher::post_store_load_barrier(n));
7148 ins_cost(0);
7149
7150 size(0);
7151 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7152 ins_encode( );
7153 ins_pipe(empty);
7154 %}
7155
7156 instruct membar_storestore() %{
7157 match(MemBarStoreStore);
7158 ins_cost(0);
7159
7160 size(0);
7161 format %{ "MEMBAR-storestore (empty encoding)" %}
7162 ins_encode( );
7163 ins_pipe(empty);
7164 %}
7165
7166 //----------Move Instructions--------------------------------------------------
7167 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7168 match(Set dst (CastX2P src));
7169 format %{ "# X2P $dst, $src" %}
7170 ins_encode( /*empty encoding*/ );
7171 ins_cost(0);
7172 ins_pipe(empty);
7173 %}
7174
7175 instruct castP2X(rRegI dst, eRegP src ) %{
7176 match(Set dst (CastP2X src));
7177 ins_cost(50);
7178 format %{ "MOV $dst, $src\t# CastP2X" %}
7179 ins_encode( enc_Copy( dst, src) );
7180 ins_pipe( ialu_reg_reg );
7181 %}
7182
7183 //----------Conditional Move---------------------------------------------------
7184 // Conditional move
7185 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7186 predicate(!VM_Version::supports_cmov() );
7187 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7188 ins_cost(200);
7189 format %{ "J$cop,us skip\t# signed cmove\n\t"
7190 "MOV $dst,$src\n"
7191 "skip:" %}
7192 ins_encode %{
7193 Label Lskip;
7194 // Invert sense of branch from sense of CMOV
7195 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7196 __ movl($dst$$Register, $src$$Register);
7197 __ bind(Lskip);
7198 %}
7199 ins_pipe( pipe_cmov_reg );
7200 %}
7201
7202 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7203 predicate(!VM_Version::supports_cmov() );
7204 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7205 ins_cost(200);
7206 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7207 "MOV $dst,$src\n"
7208 "skip:" %}
7209 ins_encode %{
7210 Label Lskip;
7211 // Invert sense of branch from sense of CMOV
7212 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7213 __ movl($dst$$Register, $src$$Register);
7214 __ bind(Lskip);
7215 %}
7216 ins_pipe( pipe_cmov_reg );
7217 %}
7218
7219 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7220 predicate(VM_Version::supports_cmov() );
7221 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7222 ins_cost(200);
7223 format %{ "CMOV$cop $dst,$src" %}
7224 opcode(0x0F,0x40);
7225 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7226 ins_pipe( pipe_cmov_reg );
7227 %}
7228
7229 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7230 predicate(VM_Version::supports_cmov() );
7231 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7232 ins_cost(200);
7233 format %{ "CMOV$cop $dst,$src" %}
7234 opcode(0x0F,0x40);
7235 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7236 ins_pipe( pipe_cmov_reg );
7237 %}
7238
7239 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7240 predicate(VM_Version::supports_cmov() );
7241 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7242 ins_cost(200);
7243 expand %{
7244 cmovI_regU(cop, cr, dst, src);
7245 %}
7246 %}
7247
7248 // Conditional move
7249 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7250 predicate(VM_Version::supports_cmov() );
7251 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7252 ins_cost(250);
7253 format %{ "CMOV$cop $dst,$src" %}
7254 opcode(0x0F,0x40);
7255 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7256 ins_pipe( pipe_cmov_mem );
7257 %}
7258
7259 // Conditional move
7260 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7261 predicate(VM_Version::supports_cmov() );
7262 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7263 ins_cost(250);
7264 format %{ "CMOV$cop $dst,$src" %}
7265 opcode(0x0F,0x40);
7266 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7267 ins_pipe( pipe_cmov_mem );
7268 %}
7269
7270 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7271 predicate(VM_Version::supports_cmov() );
7272 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7273 ins_cost(250);
7274 expand %{
7275 cmovI_memU(cop, cr, dst, src);
7276 %}
7277 %}
7278
7279 // Conditional move
7280 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7281 predicate(VM_Version::supports_cmov() );
7282 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7283 ins_cost(200);
7284 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7285 opcode(0x0F,0x40);
7286 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7287 ins_pipe( pipe_cmov_reg );
7288 %}
7289
7290 // Conditional move (non-P6 version)
7291 // Note: a CMoveP is generated for stubs and native wrappers
7292 // regardless of whether we are on a P6, so we
7293 // emulate a cmov here
7294 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7295 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7296 ins_cost(300);
7297 format %{ "Jn$cop skip\n\t"
7298 "MOV $dst,$src\t# pointer\n"
7299 "skip:" %}
7300 opcode(0x8b);
7301 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7302 ins_pipe( pipe_cmov_reg );
7303 %}
7304
7305 // Conditional move
7306 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7307 predicate(VM_Version::supports_cmov() );
7308 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7309 ins_cost(200);
7310 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7311 opcode(0x0F,0x40);
7312 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7313 ins_pipe( pipe_cmov_reg );
7314 %}
7315
7316 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7317 predicate(VM_Version::supports_cmov() );
7318 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7319 ins_cost(200);
7320 expand %{
7321 cmovP_regU(cop, cr, dst, src);
7322 %}
7323 %}
7324
7325 // DISABLED: Requires the ADLC to emit a bottom_type call that
7326 // correctly meets the two pointer arguments; one is an incoming
7327 // register but the other is a memory operand. ALSO appears to
7328 // be buggy with implicit null checks.
7329 //
7330 //// Conditional move
7331 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7332 // predicate(VM_Version::supports_cmov() );
7333 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7334 // ins_cost(250);
7335 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7336 // opcode(0x0F,0x40);
7337 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7338 // ins_pipe( pipe_cmov_mem );
7339 //%}
7340 //
7341 //// Conditional move
7342 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7343 // predicate(VM_Version::supports_cmov() );
7344 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7345 // ins_cost(250);
7346 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7347 // opcode(0x0F,0x40);
7348 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7349 // ins_pipe( pipe_cmov_mem );
7350 //%}
7351
7352 // Conditional move
7353 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7354 predicate(UseSSE<=1);
7355 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7356 ins_cost(200);
7357 format %{ "FCMOV$cop $dst,$src\t# double" %}
7358 opcode(0xDA);
7359 ins_encode( enc_cmov_dpr(cop,src) );
7360 ins_pipe( pipe_cmovDPR_reg );
7361 %}
7362
7363 // Conditional move
7364 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7365 predicate(UseSSE==0);
7366 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7367 ins_cost(200);
7368 format %{ "FCMOV$cop $dst,$src\t# float" %}
7369 opcode(0xDA);
7370 ins_encode( enc_cmov_dpr(cop,src) );
7371 ins_pipe( pipe_cmovDPR_reg );
7372 %}
7373
7374 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7375 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7376 predicate(UseSSE<=1);
7377 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7378 ins_cost(200);
7379 format %{ "Jn$cop skip\n\t"
7380 "MOV $dst,$src\t# double\n"
7381 "skip:" %}
7382 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7383 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7384 ins_pipe( pipe_cmovDPR_reg );
7385 %}
7386
7387 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7388 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7389 predicate(UseSSE==0);
7390 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7391 ins_cost(200);
7392 format %{ "Jn$cop skip\n\t"
7393 "MOV $dst,$src\t# float\n"
7394 "skip:" %}
7395 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7396 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7397 ins_pipe( pipe_cmovDPR_reg );
7398 %}
7399
7400 // No CMOVE with SSE/SSE2
7401 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7402 predicate (UseSSE>=1);
7403 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7404 ins_cost(200);
7405 format %{ "Jn$cop skip\n\t"
7406 "MOVSS $dst,$src\t# float\n"
7407 "skip:" %}
7408 ins_encode %{
7409 Label skip;
7410 // Invert sense of branch from sense of CMOV
7411 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7412 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7413 __ bind(skip);
7414 %}
7415 ins_pipe( pipe_slow );
7416 %}
7417
7418 // No CMOVE with SSE/SSE2
7419 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7420 predicate (UseSSE>=2);
7421 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7422 ins_cost(200);
7423 format %{ "Jn$cop skip\n\t"
7424 "MOVSD $dst,$src\t# float\n"
7425 "skip:" %}
7426 ins_encode %{
7427 Label skip;
7428 // Invert sense of branch from sense of CMOV
7429 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7430 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7431 __ bind(skip);
7432 %}
7433 ins_pipe( pipe_slow );
7434 %}
7435
7436 // unsigned version
7437 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7438 predicate (UseSSE>=1);
7439 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7440 ins_cost(200);
7441 format %{ "Jn$cop skip\n\t"
7442 "MOVSS $dst,$src\t# float\n"
7443 "skip:" %}
7444 ins_encode %{
7445 Label skip;
7446 // Invert sense of branch from sense of CMOV
7447 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7448 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7449 __ bind(skip);
7450 %}
7451 ins_pipe( pipe_slow );
7452 %}
7453
7454 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7455 predicate (UseSSE>=1);
7456 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7457 ins_cost(200);
7458 expand %{
7459 fcmovF_regU(cop, cr, dst, src);
7460 %}
7461 %}
7462
7463 // unsigned version
7464 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7465 predicate (UseSSE>=2);
7466 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7467 ins_cost(200);
7468 format %{ "Jn$cop skip\n\t"
7469 "MOVSD $dst,$src\t# float\n"
7470 "skip:" %}
7471 ins_encode %{
7472 Label skip;
7473 // Invert sense of branch from sense of CMOV
7474 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7475 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7476 __ bind(skip);
7477 %}
7478 ins_pipe( pipe_slow );
7479 %}
7480
7481 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7482 predicate (UseSSE>=2);
7483 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7484 ins_cost(200);
7485 expand %{
7486 fcmovD_regU(cop, cr, dst, src);
7487 %}
7488 %}
7489
7490 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7491 predicate(VM_Version::supports_cmov() );
7492 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7493 ins_cost(200);
7494 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7495 "CMOV$cop $dst.hi,$src.hi" %}
7496 opcode(0x0F,0x40);
7497 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7498 ins_pipe( pipe_cmov_reg_long );
7499 %}
7500
7501 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7502 predicate(VM_Version::supports_cmov() );
7503 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7504 ins_cost(200);
7505 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7506 "CMOV$cop $dst.hi,$src.hi" %}
7507 opcode(0x0F,0x40);
7508 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7509 ins_pipe( pipe_cmov_reg_long );
7510 %}
7511
7512 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7513 predicate(VM_Version::supports_cmov() );
7514 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7515 ins_cost(200);
7516 expand %{
7517 cmovL_regU(cop, cr, dst, src);
7518 %}
7519 %}
7520
7521 //----------Arithmetic Instructions--------------------------------------------
7522 //----------Addition Instructions----------------------------------------------
7523 // Integer Addition Instructions
7524 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7525 match(Set dst (AddI dst src));
7526 effect(KILL cr);
7527
7528 size(2);
7529 format %{ "ADD $dst,$src" %}
7530 opcode(0x03);
7531 ins_encode( OpcP, RegReg( dst, src) );
7532 ins_pipe( ialu_reg_reg );
7533 %}
7534
7535 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7536 match(Set dst (AddI dst src));
7537 effect(KILL cr);
7538
7539 format %{ "ADD $dst,$src" %}
7540 opcode(0x81, 0x00); /* /0 id */
7541 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7542 ins_pipe( ialu_reg );
7543 %}
7544
7545 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7546 predicate(UseIncDec);
7547 match(Set dst (AddI dst src));
7548 effect(KILL cr);
7549
7550 size(1);
7551 format %{ "INC $dst" %}
7552 opcode(0x40); /* */
7553 ins_encode( Opc_plus( primary, dst ) );
7554 ins_pipe( ialu_reg );
7555 %}
7556
7557 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7558 match(Set dst (AddI src0 src1));
7559 ins_cost(110);
7560
7561 format %{ "LEA $dst,[$src0 + $src1]" %}
7562 opcode(0x8D); /* 0x8D /r */
7563 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7564 ins_pipe( ialu_reg_reg );
7565 %}
7566
7567 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7568 match(Set dst (AddP src0 src1));
7569 ins_cost(110);
7570
7571 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7572 opcode(0x8D); /* 0x8D /r */
7573 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7574 ins_pipe( ialu_reg_reg );
7575 %}
7576
7577 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7578 predicate(UseIncDec);
7579 match(Set dst (AddI dst src));
7580 effect(KILL cr);
7581
7582 size(1);
7583 format %{ "DEC $dst" %}
7584 opcode(0x48); /* */
7585 ins_encode( Opc_plus( primary, dst ) );
7586 ins_pipe( ialu_reg );
7587 %}
7588
7589 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7590 match(Set dst (AddP dst src));
7591 effect(KILL cr);
7592
7593 size(2);
7594 format %{ "ADD $dst,$src" %}
7595 opcode(0x03);
7596 ins_encode( OpcP, RegReg( dst, src) );
7597 ins_pipe( ialu_reg_reg );
7598 %}
7599
7600 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7601 match(Set dst (AddP dst src));
7602 effect(KILL cr);
7603
7604 format %{ "ADD $dst,$src" %}
7605 opcode(0x81,0x00); /* Opcode 81 /0 id */
7606 // ins_encode( RegImm( dst, src) );
7607 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7608 ins_pipe( ialu_reg );
7609 %}
7610
7611 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7612 match(Set dst (AddI dst (LoadI src)));
7613 effect(KILL cr);
7614
7615 ins_cost(125);
7616 format %{ "ADD $dst,$src" %}
7617 opcode(0x03);
7618 ins_encode( OpcP, RegMem( dst, src) );
7619 ins_pipe( ialu_reg_mem );
7620 %}
7621
7622 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7623 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7624 effect(KILL cr);
7625
7626 ins_cost(150);
7627 format %{ "ADD $dst,$src" %}
7628 opcode(0x01); /* Opcode 01 /r */
7629 ins_encode( OpcP, RegMem( src, dst ) );
7630 ins_pipe( ialu_mem_reg );
7631 %}
7632
7633 // Add Memory with Immediate
7634 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7635 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7636 effect(KILL cr);
7637
7638 ins_cost(125);
7639 format %{ "ADD $dst,$src" %}
7640 opcode(0x81); /* Opcode 81 /0 id */
7641 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7642 ins_pipe( ialu_mem_imm );
7643 %}
7644
7645 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7646 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7647 effect(KILL cr);
7648
7649 ins_cost(125);
7650 format %{ "INC $dst" %}
7651 opcode(0xFF); /* Opcode FF /0 */
7652 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7653 ins_pipe( ialu_mem_imm );
7654 %}
7655
7656 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7657 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7658 effect(KILL cr);
7659
7660 ins_cost(125);
7661 format %{ "DEC $dst" %}
7662 opcode(0xFF); /* Opcode FF /1 */
7663 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7664 ins_pipe( ialu_mem_imm );
7665 %}
7666
7667
7668 instruct checkCastPP( eRegP dst ) %{
7669 match(Set dst (CheckCastPP dst));
7670
7671 size(0);
7672 format %{ "#checkcastPP of $dst" %}
7673 ins_encode( /*empty encoding*/ );
7674 ins_pipe( empty );
7675 %}
7676
7677 instruct castPP( eRegP dst ) %{
7678 match(Set dst (CastPP dst));
7679 format %{ "#castPP of $dst" %}
7680 ins_encode( /*empty encoding*/ );
7681 ins_pipe( empty );
7682 %}
7683
7684 instruct castII( rRegI dst ) %{
7685 match(Set dst (CastII dst));
7686 format %{ "#castII of $dst" %}
7687 ins_encode( /*empty encoding*/ );
7688 ins_cost(0);
7689 ins_pipe( empty );
7690 %}
7691
7692
7693 // Load-locked - same as a regular pointer load when used with compare-swap
7694 instruct loadPLocked(eRegP dst, memory mem) %{
7695 match(Set dst (LoadPLocked mem));
7696
7697 ins_cost(125);
7698 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7699 opcode(0x8B);
7700 ins_encode( OpcP, RegMem(dst,mem));
7701 ins_pipe( ialu_reg_mem );
7702 %}
7703
7704 // Conditional-store of the updated heap-top.
7705 // Used during allocation of the shared heap.
7706 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7707 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7708 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7709 // EAX is killed if there is contention, but then it's also unused.
7710 // In the common case of no contention, EAX holds the new oop address.
7711 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7712 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7713 ins_pipe( pipe_cmpxchg );
7714 %}
7715
7716 // Conditional-store of an int value.
7717 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7718 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7719 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7720 effect(KILL oldval);
7721 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7722 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7723 ins_pipe( pipe_cmpxchg );
7724 %}
7725
7726 // Conditional-store of a long value.
7727 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7728 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7729 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7730 effect(KILL oldval);
7731 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7732 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7733 "XCHG EBX,ECX"
7734 %}
7735 ins_encode %{
7736 // Note: we need to swap rbx, and rcx before and after the
7737 // cmpxchg8 instruction because the instruction uses
7738 // rcx as the high order word of the new value to store but
7739 // our register encoding uses rbx.
7740 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7741 if( os::is_MP() )
7742 __ lock();
7743 __ cmpxchg8($mem$$Address);
7744 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7745 %}
7746 ins_pipe( pipe_cmpxchg );
7747 %}
7748
7749 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7750
7751 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7752 predicate(VM_Version::supports_cx8());
7753 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7754 effect(KILL cr, KILL oldval);
7755 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7756 "MOV $res,0\n\t"
7757 "JNE,s fail\n\t"
7758 "MOV $res,1\n"
7759 "fail:" %}
7760 ins_encode( enc_cmpxchg8(mem_ptr),
7761 enc_flags_ne_to_boolean(res) );
7762 ins_pipe( pipe_cmpxchg );
7763 %}
7764
7765 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7766 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7767 effect(KILL cr, KILL oldval);
7768 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7769 "MOV $res,0\n\t"
7770 "JNE,s fail\n\t"
7771 "MOV $res,1\n"
7772 "fail:" %}
7773 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7774 ins_pipe( pipe_cmpxchg );
7775 %}
7776
7777 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7778 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7779 effect(KILL cr, KILL oldval);
7780 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7781 "MOV $res,0\n\t"
7782 "JNE,s fail\n\t"
7783 "MOV $res,1\n"
7784 "fail:" %}
7785 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7786 ins_pipe( pipe_cmpxchg );
7787 %}
7788
7789 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7790 predicate(n->as_LoadStore()->result_not_used());
7791 match(Set dummy (GetAndAddI mem add));
7792 effect(KILL cr);
7793 format %{ "ADDL [$mem],$add" %}
7794 ins_encode %{
7795 if (os::is_MP()) { __ lock(); }
7796 __ addl($mem$$Address, $add$$constant);
7797 %}
7798 ins_pipe( pipe_cmpxchg );
7799 %}
7800
7801 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7802 match(Set newval (GetAndAddI mem newval));
7803 effect(KILL cr);
7804 format %{ "XADDL [$mem],$newval" %}
7805 ins_encode %{
7806 if (os::is_MP()) { __ lock(); }
7807 __ xaddl($mem$$Address, $newval$$Register);
7808 %}
7809 ins_pipe( pipe_cmpxchg );
7810 %}
7811
7812 instruct xchgI( memory mem, rRegI newval) %{
7813 match(Set newval (GetAndSetI mem newval));
7814 format %{ "XCHGL $newval,[$mem]" %}
7815 ins_encode %{
7816 __ xchgl($newval$$Register, $mem$$Address);
7817 %}
7818 ins_pipe( pipe_cmpxchg );
7819 %}
7820
7821 instruct xchgP( memory mem, pRegP newval) %{
7822 match(Set newval (GetAndSetP mem newval));
7823 format %{ "XCHGL $newval,[$mem]" %}
7824 ins_encode %{
7825 __ xchgl($newval$$Register, $mem$$Address);
7826 %}
7827 ins_pipe( pipe_cmpxchg );
7828 %}
7829
7830 //----------Subtraction Instructions-------------------------------------------
7831 // Integer Subtraction Instructions
7832 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7833 match(Set dst (SubI dst src));
7834 effect(KILL cr);
7835
7836 size(2);
7837 format %{ "SUB $dst,$src" %}
7838 opcode(0x2B);
7839 ins_encode( OpcP, RegReg( dst, src) );
7840 ins_pipe( ialu_reg_reg );
7841 %}
7842
7843 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7844 match(Set dst (SubI dst src));
7845 effect(KILL cr);
7846
7847 format %{ "SUB $dst,$src" %}
7848 opcode(0x81,0x05); /* Opcode 81 /5 */
7849 // ins_encode( RegImm( dst, src) );
7850 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7851 ins_pipe( ialu_reg );
7852 %}
7853
7854 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7855 match(Set dst (SubI dst (LoadI src)));
7856 effect(KILL cr);
7857
7858 ins_cost(125);
7859 format %{ "SUB $dst,$src" %}
7860 opcode(0x2B);
7861 ins_encode( OpcP, RegMem( dst, src) );
7862 ins_pipe( ialu_reg_mem );
7863 %}
7864
7865 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7866 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7867 effect(KILL cr);
7868
7869 ins_cost(150);
7870 format %{ "SUB $dst,$src" %}
7871 opcode(0x29); /* Opcode 29 /r */
7872 ins_encode( OpcP, RegMem( src, dst ) );
7873 ins_pipe( ialu_mem_reg );
7874 %}
7875
7876 // Subtract from a pointer
7877 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7878 match(Set dst (AddP dst (SubI zero src)));
7879 effect(KILL cr);
7880
7881 size(2);
7882 format %{ "SUB $dst,$src" %}
7883 opcode(0x2B);
7884 ins_encode( OpcP, RegReg( dst, src) );
7885 ins_pipe( ialu_reg_reg );
7886 %}
7887
7888 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7889 match(Set dst (SubI zero dst));
7890 effect(KILL cr);
7891
7892 size(2);
7893 format %{ "NEG $dst" %}
7894 opcode(0xF7,0x03); // Opcode F7 /3
7895 ins_encode( OpcP, RegOpc( dst ) );
7896 ins_pipe( ialu_reg );
7897 %}
7898
7899
7900 //----------Multiplication/Division Instructions-------------------------------
7901 // Integer Multiplication Instructions
7902 // Multiply Register
7903 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7904 match(Set dst (MulI dst src));
7905 effect(KILL cr);
7906
7907 size(3);
7908 ins_cost(300);
7909 format %{ "IMUL $dst,$src" %}
7910 opcode(0xAF, 0x0F);
7911 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7912 ins_pipe( ialu_reg_reg_alu0 );
7913 %}
7914
7915 // Multiply 32-bit Immediate
7916 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7917 match(Set dst (MulI src imm));
7918 effect(KILL cr);
7919
7920 ins_cost(300);
7921 format %{ "IMUL $dst,$src,$imm" %}
7922 opcode(0x69); /* 69 /r id */
7923 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7924 ins_pipe( ialu_reg_reg_alu0 );
7925 %}
7926
7927 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7928 match(Set dst src);
7929 effect(KILL cr);
7930
7931 // Note that this is artificially increased to make it more expensive than loadConL
7932 ins_cost(250);
7933 format %{ "MOV EAX,$src\t// low word only" %}
7934 opcode(0xB8);
7935 ins_encode( LdImmL_Lo(dst, src) );
7936 ins_pipe( ialu_reg_fat );
7937 %}
7938
7939 // Multiply by 32-bit Immediate, taking the shifted high order results
7940 // (special case for shift by 32)
7941 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7942 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7943 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7944 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7945 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7946 effect(USE src1, KILL cr);
7947
7948 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7949 ins_cost(0*100 + 1*400 - 150);
7950 format %{ "IMUL EDX:EAX,$src1" %}
7951 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7952 ins_pipe( pipe_slow );
7953 %}
7954
7955 // Multiply by 32-bit Immediate, taking the shifted high order results
7956 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7957 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7958 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7959 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7960 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7961 effect(USE src1, KILL cr);
7962
7963 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7964 ins_cost(1*100 + 1*400 - 150);
7965 format %{ "IMUL EDX:EAX,$src1\n\t"
7966 "SAR EDX,$cnt-32" %}
7967 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7968 ins_pipe( pipe_slow );
7969 %}
7970
7971 // Multiply Memory 32-bit Immediate
7972 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7973 match(Set dst (MulI (LoadI src) imm));
7974 effect(KILL cr);
7975
7976 ins_cost(300);
7977 format %{ "IMUL $dst,$src,$imm" %}
7978 opcode(0x69); /* 69 /r id */
7979 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7980 ins_pipe( ialu_reg_mem_alu0 );
7981 %}
7982
7983 // Multiply Memory
7984 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7985 match(Set dst (MulI dst (LoadI src)));
7986 effect(KILL cr);
7987
7988 ins_cost(350);
7989 format %{ "IMUL $dst,$src" %}
7990 opcode(0xAF, 0x0F);
7991 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7992 ins_pipe( ialu_reg_mem_alu0 );
7993 %}
7994
7995 // Multiply Register Int to Long
7996 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7997 // Basic Idea: long = (long)int * (long)int
7998 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7999 effect(DEF dst, USE src, USE src1, KILL flags);
8000
8001 ins_cost(300);
8002 format %{ "IMUL $dst,$src1" %}
8003
8004 ins_encode( long_int_multiply( dst, src1 ) );
8005 ins_pipe( ialu_reg_reg_alu0 );
8006 %}
8007
8008 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8009 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8010 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8011 effect(KILL flags);
8012
8013 ins_cost(300);
8014 format %{ "MUL $dst,$src1" %}
8015
8016 ins_encode( long_uint_multiply(dst, src1) );
8017 ins_pipe( ialu_reg_reg_alu0 );
8018 %}
8019
8020 // Multiply Register Long
8021 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8022 match(Set dst (MulL dst src));
8023 effect(KILL cr, TEMP tmp);
8024 ins_cost(4*100+3*400);
8025 // Basic idea: lo(result) = lo(x_lo * y_lo)
8026 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8027 format %{ "MOV $tmp,$src.lo\n\t"
8028 "IMUL $tmp,EDX\n\t"
8029 "MOV EDX,$src.hi\n\t"
8030 "IMUL EDX,EAX\n\t"
8031 "ADD $tmp,EDX\n\t"
8032 "MUL EDX:EAX,$src.lo\n\t"
8033 "ADD EDX,$tmp" %}
8034 ins_encode( long_multiply( dst, src, tmp ) );
8035 ins_pipe( pipe_slow );
8036 %}
8037
8038 // Multiply Register Long where the left operand's high 32 bits are zero
8039 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8040 predicate(is_operand_hi32_zero(n->in(1)));
8041 match(Set dst (MulL dst src));
8042 effect(KILL cr, TEMP tmp);
8043 ins_cost(2*100+2*400);
8044 // Basic idea: lo(result) = lo(x_lo * y_lo)
8045 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8046 format %{ "MOV $tmp,$src.hi\n\t"
8047 "IMUL $tmp,EAX\n\t"
8048 "MUL EDX:EAX,$src.lo\n\t"
8049 "ADD EDX,$tmp" %}
8050 ins_encode %{
8051 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8052 __ imull($tmp$$Register, rax);
8053 __ mull($src$$Register);
8054 __ addl(rdx, $tmp$$Register);
8055 %}
8056 ins_pipe( pipe_slow );
8057 %}
8058
8059 // Multiply Register Long where the right operand's high 32 bits are zero
8060 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8061 predicate(is_operand_hi32_zero(n->in(2)));
8062 match(Set dst (MulL dst src));
8063 effect(KILL cr, TEMP tmp);
8064 ins_cost(2*100+2*400);
8065 // Basic idea: lo(result) = lo(x_lo * y_lo)
8066 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8067 format %{ "MOV $tmp,$src.lo\n\t"
8068 "IMUL $tmp,EDX\n\t"
8069 "MUL EDX:EAX,$src.lo\n\t"
8070 "ADD EDX,$tmp" %}
8071 ins_encode %{
8072 __ movl($tmp$$Register, $src$$Register);
8073 __ imull($tmp$$Register, rdx);
8074 __ mull($src$$Register);
8075 __ addl(rdx, $tmp$$Register);
8076 %}
8077 ins_pipe( pipe_slow );
8078 %}
8079
8080 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8081 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8082 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8083 match(Set dst (MulL dst src));
8084 effect(KILL cr);
8085 ins_cost(1*400);
8086 // Basic idea: lo(result) = lo(x_lo * y_lo)
8087 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8088 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8089 ins_encode %{
8090 __ mull($src$$Register);
8091 %}
8092 ins_pipe( pipe_slow );
8093 %}
8094
8095 // Multiply Register Long by small constant
8096 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8097 match(Set dst (MulL dst src));
8098 effect(KILL cr, TEMP tmp);
8099 ins_cost(2*100+2*400);
8100 size(12);
8101 // Basic idea: lo(result) = lo(src * EAX)
8102 // hi(result) = hi(src * EAX) + lo(src * EDX)
8103 format %{ "IMUL $tmp,EDX,$src\n\t"
8104 "MOV EDX,$src\n\t"
8105 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8106 "ADD EDX,$tmp" %}
8107 ins_encode( long_multiply_con( dst, src, tmp ) );
8108 ins_pipe( pipe_slow );
8109 %}
8110
8111 // Integer DIV with Register
8112 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8113 match(Set rax (DivI rax div));
8114 effect(KILL rdx, KILL cr);
8115 size(26);
8116 ins_cost(30*100+10*100);
8117 format %{ "CMP EAX,0x80000000\n\t"
8118 "JNE,s normal\n\t"
8119 "XOR EDX,EDX\n\t"
8120 "CMP ECX,-1\n\t"
8121 "JE,s done\n"
8122 "normal: CDQ\n\t"
8123 "IDIV $div\n\t"
8124 "done:" %}
8125 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8126 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8127 ins_pipe( ialu_reg_reg_alu0 );
8128 %}
8129
8130 // Divide Register Long
8131 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8132 match(Set dst (DivL src1 src2));
8133 effect( KILL cr, KILL cx, KILL bx );
8134 ins_cost(10000);
8135 format %{ "PUSH $src1.hi\n\t"
8136 "PUSH $src1.lo\n\t"
8137 "PUSH $src2.hi\n\t"
8138 "PUSH $src2.lo\n\t"
8139 "CALL SharedRuntime::ldiv\n\t"
8140 "ADD ESP,16" %}
8141 ins_encode( long_div(src1,src2) );
8142 ins_pipe( pipe_slow );
8143 %}
8144
8145 // Integer DIVMOD with Register, both quotient and mod results
8146 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8147 match(DivModI rax div);
8148 effect(KILL cr);
8149 size(26);
8150 ins_cost(30*100+10*100);
8151 format %{ "CMP EAX,0x80000000\n\t"
8152 "JNE,s normal\n\t"
8153 "XOR EDX,EDX\n\t"
8154 "CMP ECX,-1\n\t"
8155 "JE,s done\n"
8156 "normal: CDQ\n\t"
8157 "IDIV $div\n\t"
8158 "done:" %}
8159 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8160 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8161 ins_pipe( pipe_slow );
8162 %}
8163
8164 // Integer MOD with Register
8165 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8166 match(Set rdx (ModI rax div));
8167 effect(KILL rax, KILL cr);
8168
8169 size(26);
8170 ins_cost(300);
8171 format %{ "CDQ\n\t"
8172 "IDIV $div" %}
8173 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8174 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8175 ins_pipe( ialu_reg_reg_alu0 );
8176 %}
8177
8178 // Remainder Register Long
8179 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8180 match(Set dst (ModL src1 src2));
8181 effect( KILL cr, KILL cx, KILL bx );
8182 ins_cost(10000);
8183 format %{ "PUSH $src1.hi\n\t"
8184 "PUSH $src1.lo\n\t"
8185 "PUSH $src2.hi\n\t"
8186 "PUSH $src2.lo\n\t"
8187 "CALL SharedRuntime::lrem\n\t"
8188 "ADD ESP,16" %}
8189 ins_encode( long_mod(src1,src2) );
8190 ins_pipe( pipe_slow );
8191 %}
8192
8193 // Divide Register Long (no special case since divisor != -1)
8194 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8195 match(Set dst (DivL dst imm));
8196 effect( TEMP tmp, TEMP tmp2, KILL cr );
8197 ins_cost(1000);
8198 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8199 "XOR $tmp2,$tmp2\n\t"
8200 "CMP $tmp,EDX\n\t"
8201 "JA,s fast\n\t"
8202 "MOV $tmp2,EAX\n\t"
8203 "MOV EAX,EDX\n\t"
8204 "MOV EDX,0\n\t"
8205 "JLE,s pos\n\t"
8206 "LNEG EAX : $tmp2\n\t"
8207 "DIV $tmp # unsigned division\n\t"
8208 "XCHG EAX,$tmp2\n\t"
8209 "DIV $tmp\n\t"
8210 "LNEG $tmp2 : EAX\n\t"
8211 "JMP,s done\n"
8212 "pos:\n\t"
8213 "DIV $tmp\n\t"
8214 "XCHG EAX,$tmp2\n"
8215 "fast:\n\t"
8216 "DIV $tmp\n"
8217 "done:\n\t"
8218 "MOV EDX,$tmp2\n\t"
8219 "NEG EDX:EAX # if $imm < 0" %}
8220 ins_encode %{
8221 int con = (int)$imm$$constant;
8222 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8223 int pcon = (con > 0) ? con : -con;
8224 Label Lfast, Lpos, Ldone;
8225
8226 __ movl($tmp$$Register, pcon);
8227 __ xorl($tmp2$$Register,$tmp2$$Register);
8228 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8229 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8230
8231 __ movl($tmp2$$Register, $dst$$Register); // save
8232 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8233 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8234 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8235
8236 // Negative dividend.
8237 // convert value to positive to use unsigned division
8238 __ lneg($dst$$Register, $tmp2$$Register);
8239 __ divl($tmp$$Register);
8240 __ xchgl($dst$$Register, $tmp2$$Register);
8241 __ divl($tmp$$Register);
8242 // revert result back to negative
8243 __ lneg($tmp2$$Register, $dst$$Register);
8244 __ jmpb(Ldone);
8245
8246 __ bind(Lpos);
8247 __ divl($tmp$$Register); // Use unsigned division
8248 __ xchgl($dst$$Register, $tmp2$$Register);
8249 // Fallthrow for final divide, tmp2 has 32 bit hi result
8250
8251 __ bind(Lfast);
8252 // fast path: src is positive
8253 __ divl($tmp$$Register); // Use unsigned division
8254
8255 __ bind(Ldone);
8256 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8257 if (con < 0) {
8258 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8259 }
8260 %}
8261 ins_pipe( pipe_slow );
8262 %}
8263
8264 // Remainder Register Long (remainder fit into 32 bits)
8265 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8266 match(Set dst (ModL dst imm));
8267 effect( TEMP tmp, TEMP tmp2, KILL cr );
8268 ins_cost(1000);
8269 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8270 "CMP $tmp,EDX\n\t"
8271 "JA,s fast\n\t"
8272 "MOV $tmp2,EAX\n\t"
8273 "MOV EAX,EDX\n\t"
8274 "MOV EDX,0\n\t"
8275 "JLE,s pos\n\t"
8276 "LNEG EAX : $tmp2\n\t"
8277 "DIV $tmp # unsigned division\n\t"
8278 "MOV EAX,$tmp2\n\t"
8279 "DIV $tmp\n\t"
8280 "NEG EDX\n\t"
8281 "JMP,s done\n"
8282 "pos:\n\t"
8283 "DIV $tmp\n\t"
8284 "MOV EAX,$tmp2\n"
8285 "fast:\n\t"
8286 "DIV $tmp\n"
8287 "done:\n\t"
8288 "MOV EAX,EDX\n\t"
8289 "SAR EDX,31\n\t" %}
8290 ins_encode %{
8291 int con = (int)$imm$$constant;
8292 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8293 int pcon = (con > 0) ? con : -con;
8294 Label Lfast, Lpos, Ldone;
8295
8296 __ movl($tmp$$Register, pcon);
8297 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8298 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8299
8300 __ movl($tmp2$$Register, $dst$$Register); // save
8301 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8302 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8303 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8304
8305 // Negative dividend.
8306 // convert value to positive to use unsigned division
8307 __ lneg($dst$$Register, $tmp2$$Register);
8308 __ divl($tmp$$Register);
8309 __ movl($dst$$Register, $tmp2$$Register);
8310 __ divl($tmp$$Register);
8311 // revert remainder back to negative
8312 __ negl(HIGH_FROM_LOW($dst$$Register));
8313 __ jmpb(Ldone);
8314
8315 __ bind(Lpos);
8316 __ divl($tmp$$Register);
8317 __ movl($dst$$Register, $tmp2$$Register);
8318
8319 __ bind(Lfast);
8320 // fast path: src is positive
8321 __ divl($tmp$$Register);
8322
8323 __ bind(Ldone);
8324 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8325 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8326
8327 %}
8328 ins_pipe( pipe_slow );
8329 %}
8330
8331 // Integer Shift Instructions
8332 // Shift Left by one
8333 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8334 match(Set dst (LShiftI dst shift));
8335 effect(KILL cr);
8336
8337 size(2);
8338 format %{ "SHL $dst,$shift" %}
8339 opcode(0xD1, 0x4); /* D1 /4 */
8340 ins_encode( OpcP, RegOpc( dst ) );
8341 ins_pipe( ialu_reg );
8342 %}
8343
8344 // Shift Left by 8-bit immediate
8345 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8346 match(Set dst (LShiftI dst shift));
8347 effect(KILL cr);
8348
8349 size(3);
8350 format %{ "SHL $dst,$shift" %}
8351 opcode(0xC1, 0x4); /* C1 /4 ib */
8352 ins_encode( RegOpcImm( dst, shift) );
8353 ins_pipe( ialu_reg );
8354 %}
8355
8356 // Shift Left by variable
8357 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8358 match(Set dst (LShiftI dst shift));
8359 effect(KILL cr);
8360
8361 size(2);
8362 format %{ "SHL $dst,$shift" %}
8363 opcode(0xD3, 0x4); /* D3 /4 */
8364 ins_encode( OpcP, RegOpc( dst ) );
8365 ins_pipe( ialu_reg_reg );
8366 %}
8367
8368 // Arithmetic shift right by one
8369 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8370 match(Set dst (RShiftI dst shift));
8371 effect(KILL cr);
8372
8373 size(2);
8374 format %{ "SAR $dst,$shift" %}
8375 opcode(0xD1, 0x7); /* D1 /7 */
8376 ins_encode( OpcP, RegOpc( dst ) );
8377 ins_pipe( ialu_reg );
8378 %}
8379
8380 // Arithmetic shift right by one
8381 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8382 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8383 effect(KILL cr);
8384 format %{ "SAR $dst,$shift" %}
8385 opcode(0xD1, 0x7); /* D1 /7 */
8386 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8387 ins_pipe( ialu_mem_imm );
8388 %}
8389
8390 // Arithmetic Shift Right by 8-bit immediate
8391 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8392 match(Set dst (RShiftI dst shift));
8393 effect(KILL cr);
8394
8395 size(3);
8396 format %{ "SAR $dst,$shift" %}
8397 opcode(0xC1, 0x7); /* C1 /7 ib */
8398 ins_encode( RegOpcImm( dst, shift ) );
8399 ins_pipe( ialu_mem_imm );
8400 %}
8401
8402 // Arithmetic Shift Right by 8-bit immediate
8403 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8404 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8405 effect(KILL cr);
8406
8407 format %{ "SAR $dst,$shift" %}
8408 opcode(0xC1, 0x7); /* C1 /7 ib */
8409 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8410 ins_pipe( ialu_mem_imm );
8411 %}
8412
8413 // Arithmetic Shift Right by variable
8414 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8415 match(Set dst (RShiftI dst shift));
8416 effect(KILL cr);
8417
8418 size(2);
8419 format %{ "SAR $dst,$shift" %}
8420 opcode(0xD3, 0x7); /* D3 /7 */
8421 ins_encode( OpcP, RegOpc( dst ) );
8422 ins_pipe( ialu_reg_reg );
8423 %}
8424
8425 // Logical shift right by one
8426 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8427 match(Set dst (URShiftI dst shift));
8428 effect(KILL cr);
8429
8430 size(2);
8431 format %{ "SHR $dst,$shift" %}
8432 opcode(0xD1, 0x5); /* D1 /5 */
8433 ins_encode( OpcP, RegOpc( dst ) );
8434 ins_pipe( ialu_reg );
8435 %}
8436
8437 // Logical Shift Right by 8-bit immediate
8438 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8439 match(Set dst (URShiftI dst shift));
8440 effect(KILL cr);
8441
8442 size(3);
8443 format %{ "SHR $dst,$shift" %}
8444 opcode(0xC1, 0x5); /* C1 /5 ib */
8445 ins_encode( RegOpcImm( dst, shift) );
8446 ins_pipe( ialu_reg );
8447 %}
8448
8449
8450 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8451 // This idiom is used by the compiler for the i2b bytecode.
8452 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8453 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8454
8455 size(3);
8456 format %{ "MOVSX $dst,$src :8" %}
8457 ins_encode %{
8458 __ movsbl($dst$$Register, $src$$Register);
8459 %}
8460 ins_pipe(ialu_reg_reg);
8461 %}
8462
8463 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8464 // This idiom is used by the compiler the i2s bytecode.
8465 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8466 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8467
8468 size(3);
8469 format %{ "MOVSX $dst,$src :16" %}
8470 ins_encode %{
8471 __ movswl($dst$$Register, $src$$Register);
8472 %}
8473 ins_pipe(ialu_reg_reg);
8474 %}
8475
8476
8477 // Logical Shift Right by variable
8478 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8479 match(Set dst (URShiftI dst shift));
8480 effect(KILL cr);
8481
8482 size(2);
8483 format %{ "SHR $dst,$shift" %}
8484 opcode(0xD3, 0x5); /* D3 /5 */
8485 ins_encode( OpcP, RegOpc( dst ) );
8486 ins_pipe( ialu_reg_reg );
8487 %}
8488
8489
8490 //----------Logical Instructions-----------------------------------------------
8491 //----------Integer Logical Instructions---------------------------------------
8492 // And Instructions
8493 // And Register with Register
8494 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8495 match(Set dst (AndI dst src));
8496 effect(KILL cr);
8497
8498 size(2);
8499 format %{ "AND $dst,$src" %}
8500 opcode(0x23);
8501 ins_encode( OpcP, RegReg( dst, src) );
8502 ins_pipe( ialu_reg_reg );
8503 %}
8504
8505 // And Register with Immediate
8506 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8507 match(Set dst (AndI dst src));
8508 effect(KILL cr);
8509
8510 format %{ "AND $dst,$src" %}
8511 opcode(0x81,0x04); /* Opcode 81 /4 */
8512 // ins_encode( RegImm( dst, src) );
8513 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8514 ins_pipe( ialu_reg );
8515 %}
8516
8517 // And Register with Memory
8518 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8519 match(Set dst (AndI dst (LoadI src)));
8520 effect(KILL cr);
8521
8522 ins_cost(125);
8523 format %{ "AND $dst,$src" %}
8524 opcode(0x23);
8525 ins_encode( OpcP, RegMem( dst, src) );
8526 ins_pipe( ialu_reg_mem );
8527 %}
8528
8529 // And Memory with Register
8530 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8531 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8532 effect(KILL cr);
8533
8534 ins_cost(150);
8535 format %{ "AND $dst,$src" %}
8536 opcode(0x21); /* Opcode 21 /r */
8537 ins_encode( OpcP, RegMem( src, dst ) );
8538 ins_pipe( ialu_mem_reg );
8539 %}
8540
8541 // And Memory with Immediate
8542 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8543 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8544 effect(KILL cr);
8545
8546 ins_cost(125);
8547 format %{ "AND $dst,$src" %}
8548 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8549 // ins_encode( MemImm( dst, src) );
8550 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8551 ins_pipe( ialu_mem_imm );
8552 %}
8553
8554 // Or Instructions
8555 // Or Register with Register
8556 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8557 match(Set dst (OrI dst src));
8558 effect(KILL cr);
8559
8560 size(2);
8561 format %{ "OR $dst,$src" %}
8562 opcode(0x0B);
8563 ins_encode( OpcP, RegReg( dst, src) );
8564 ins_pipe( ialu_reg_reg );
8565 %}
8566
8567 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8568 match(Set dst (OrI dst (CastP2X src)));
8569 effect(KILL cr);
8570
8571 size(2);
8572 format %{ "OR $dst,$src" %}
8573 opcode(0x0B);
8574 ins_encode( OpcP, RegReg( dst, src) );
8575 ins_pipe( ialu_reg_reg );
8576 %}
8577
8578
8579 // Or Register with Immediate
8580 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8581 match(Set dst (OrI dst src));
8582 effect(KILL cr);
8583
8584 format %{ "OR $dst,$src" %}
8585 opcode(0x81,0x01); /* Opcode 81 /1 id */
8586 // ins_encode( RegImm( dst, src) );
8587 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8588 ins_pipe( ialu_reg );
8589 %}
8590
8591 // Or Register with Memory
8592 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8593 match(Set dst (OrI dst (LoadI src)));
8594 effect(KILL cr);
8595
8596 ins_cost(125);
8597 format %{ "OR $dst,$src" %}
8598 opcode(0x0B);
8599 ins_encode( OpcP, RegMem( dst, src) );
8600 ins_pipe( ialu_reg_mem );
8601 %}
8602
8603 // Or Memory with Register
8604 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8605 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8606 effect(KILL cr);
8607
8608 ins_cost(150);
8609 format %{ "OR $dst,$src" %}
8610 opcode(0x09); /* Opcode 09 /r */
8611 ins_encode( OpcP, RegMem( src, dst ) );
8612 ins_pipe( ialu_mem_reg );
8613 %}
8614
8615 // Or Memory with Immediate
8616 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8617 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8618 effect(KILL cr);
8619
8620 ins_cost(125);
8621 format %{ "OR $dst,$src" %}
8622 opcode(0x81,0x1); /* Opcode 81 /1 id */
8623 // ins_encode( MemImm( dst, src) );
8624 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8625 ins_pipe( ialu_mem_imm );
8626 %}
8627
8628 // ROL/ROR
8629 // ROL expand
8630 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8631 effect(USE_DEF dst, USE shift, KILL cr);
8632
8633 format %{ "ROL $dst, $shift" %}
8634 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8635 ins_encode( OpcP, RegOpc( dst ));
8636 ins_pipe( ialu_reg );
8637 %}
8638
8639 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8640 effect(USE_DEF dst, USE shift, KILL cr);
8641
8642 format %{ "ROL $dst, $shift" %}
8643 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8644 ins_encode( RegOpcImm(dst, shift) );
8645 ins_pipe(ialu_reg);
8646 %}
8647
8648 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8649 effect(USE_DEF dst, USE shift, KILL cr);
8650
8651 format %{ "ROL $dst, $shift" %}
8652 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8653 ins_encode(OpcP, RegOpc(dst));
8654 ins_pipe( ialu_reg_reg );
8655 %}
8656 // end of ROL expand
8657
8658 // ROL 32bit by one once
8659 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8660 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8661
8662 expand %{
8663 rolI_eReg_imm1(dst, lshift, cr);
8664 %}
8665 %}
8666
8667 // ROL 32bit var by imm8 once
8668 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8669 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8670 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8671
8672 expand %{
8673 rolI_eReg_imm8(dst, lshift, cr);
8674 %}
8675 %}
8676
8677 // ROL 32bit var by var once
8678 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8679 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8680
8681 expand %{
8682 rolI_eReg_CL(dst, shift, cr);
8683 %}
8684 %}
8685
8686 // ROL 32bit var by var once
8687 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8688 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8689
8690 expand %{
8691 rolI_eReg_CL(dst, shift, cr);
8692 %}
8693 %}
8694
8695 // ROR expand
8696 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8697 effect(USE_DEF dst, USE shift, KILL cr);
8698
8699 format %{ "ROR $dst, $shift" %}
8700 opcode(0xD1,0x1); /* Opcode D1 /1 */
8701 ins_encode( OpcP, RegOpc( dst ) );
8702 ins_pipe( ialu_reg );
8703 %}
8704
8705 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8706 effect (USE_DEF dst, USE shift, KILL cr);
8707
8708 format %{ "ROR $dst, $shift" %}
8709 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8710 ins_encode( RegOpcImm(dst, shift) );
8711 ins_pipe( ialu_reg );
8712 %}
8713
8714 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8715 effect(USE_DEF dst, USE shift, KILL cr);
8716
8717 format %{ "ROR $dst, $shift" %}
8718 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8719 ins_encode(OpcP, RegOpc(dst));
8720 ins_pipe( ialu_reg_reg );
8721 %}
8722 // end of ROR expand
8723
8724 // ROR right once
8725 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8726 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8727
8728 expand %{
8729 rorI_eReg_imm1(dst, rshift, cr);
8730 %}
8731 %}
8732
8733 // ROR 32bit by immI8 once
8734 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8735 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8736 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8737
8738 expand %{
8739 rorI_eReg_imm8(dst, rshift, cr);
8740 %}
8741 %}
8742
8743 // ROR 32bit var by var once
8744 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8745 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8746
8747 expand %{
8748 rorI_eReg_CL(dst, shift, cr);
8749 %}
8750 %}
8751
8752 // ROR 32bit var by var once
8753 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8754 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8755
8756 expand %{
8757 rorI_eReg_CL(dst, shift, cr);
8758 %}
8759 %}
8760
8761 // Xor Instructions
8762 // Xor Register with Register
8763 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8764 match(Set dst (XorI dst src));
8765 effect(KILL cr);
8766
8767 size(2);
8768 format %{ "XOR $dst,$src" %}
8769 opcode(0x33);
8770 ins_encode( OpcP, RegReg( dst, src) );
8771 ins_pipe( ialu_reg_reg );
8772 %}
8773
8774 // Xor Register with Immediate -1
8775 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8776 match(Set dst (XorI dst imm));
8777
8778 size(2);
8779 format %{ "NOT $dst" %}
8780 ins_encode %{
8781 __ notl($dst$$Register);
8782 %}
8783 ins_pipe( ialu_reg );
8784 %}
8785
8786 // Xor Register with Immediate
8787 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8788 match(Set dst (XorI dst src));
8789 effect(KILL cr);
8790
8791 format %{ "XOR $dst,$src" %}
8792 opcode(0x81,0x06); /* Opcode 81 /6 id */
8793 // ins_encode( RegImm( dst, src) );
8794 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8795 ins_pipe( ialu_reg );
8796 %}
8797
8798 // Xor Register with Memory
8799 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8800 match(Set dst (XorI dst (LoadI src)));
8801 effect(KILL cr);
8802
8803 ins_cost(125);
8804 format %{ "XOR $dst,$src" %}
8805 opcode(0x33);
8806 ins_encode( OpcP, RegMem(dst, src) );
8807 ins_pipe( ialu_reg_mem );
8808 %}
8809
8810 // Xor Memory with Register
8811 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8812 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8813 effect(KILL cr);
8814
8815 ins_cost(150);
8816 format %{ "XOR $dst,$src" %}
8817 opcode(0x31); /* Opcode 31 /r */
8818 ins_encode( OpcP, RegMem( src, dst ) );
8819 ins_pipe( ialu_mem_reg );
8820 %}
8821
8822 // Xor Memory with Immediate
8823 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8824 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8825 effect(KILL cr);
8826
8827 ins_cost(125);
8828 format %{ "XOR $dst,$src" %}
8829 opcode(0x81,0x6); /* Opcode 81 /6 id */
8830 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8831 ins_pipe( ialu_mem_imm );
8832 %}
8833
8834 //----------Convert Int to Boolean---------------------------------------------
8835
8836 instruct movI_nocopy(rRegI dst, rRegI src) %{
8837 effect( DEF dst, USE src );
8838 format %{ "MOV $dst,$src" %}
8839 ins_encode( enc_Copy( dst, src) );
8840 ins_pipe( ialu_reg_reg );
8841 %}
8842
8843 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8844 effect( USE_DEF dst, USE src, KILL cr );
8845
8846 size(4);
8847 format %{ "NEG $dst\n\t"
8848 "ADC $dst,$src" %}
8849 ins_encode( neg_reg(dst),
8850 OpcRegReg(0x13,dst,src) );
8851 ins_pipe( ialu_reg_reg_long );
8852 %}
8853
8854 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8855 match(Set dst (Conv2B src));
8856
8857 expand %{
8858 movI_nocopy(dst,src);
8859 ci2b(dst,src,cr);
8860 %}
8861 %}
8862
8863 instruct movP_nocopy(rRegI dst, eRegP src) %{
8864 effect( DEF dst, USE src );
8865 format %{ "MOV $dst,$src" %}
8866 ins_encode( enc_Copy( dst, src) );
8867 ins_pipe( ialu_reg_reg );
8868 %}
8869
8870 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8871 effect( USE_DEF dst, USE src, KILL cr );
8872 format %{ "NEG $dst\n\t"
8873 "ADC $dst,$src" %}
8874 ins_encode( neg_reg(dst),
8875 OpcRegReg(0x13,dst,src) );
8876 ins_pipe( ialu_reg_reg_long );
8877 %}
8878
8879 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8880 match(Set dst (Conv2B src));
8881
8882 expand %{
8883 movP_nocopy(dst,src);
8884 cp2b(dst,src,cr);
8885 %}
8886 %}
8887
8888 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8889 match(Set dst (CmpLTMask p q));
8890 effect( KILL cr );
8891 ins_cost(400);
8892
8893 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8894 format %{ "XOR $dst,$dst\n\t"
8895 "CMP $p,$q\n\t"
8896 "SETlt $dst\n\t"
8897 "NEG $dst" %}
8898 ins_encode( OpcRegReg(0x33,dst,dst),
8899 OpcRegReg(0x3B,p,q),
8900 setLT_reg(dst), neg_reg(dst) );
8901 ins_pipe( pipe_slow );
8902 %}
8903
8904 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8905 match(Set dst (CmpLTMask dst zero));
8906 effect( DEF dst, KILL cr );
8907 ins_cost(100);
8908
8909 format %{ "SAR $dst,31" %}
8910 opcode(0xC1, 0x7); /* C1 /7 ib */
8911 ins_encode( RegOpcImm( dst, 0x1F ) );
8912 ins_pipe( ialu_reg );
8913 %}
8914
8915
8916 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8917 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8918 effect( KILL tmp, KILL cr );
8919 ins_cost(400);
8920 // annoyingly, $tmp has no edges so you cant ask for it in
8921 // any format or encoding
8922 format %{ "SUB $p,$q\n\t"
8923 "SBB ECX,ECX\n\t"
8924 "AND ECX,$y\n\t"
8925 "ADD $p,ECX" %}
8926 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8927 ins_pipe( pipe_cmplt );
8928 %}
8929
8930 /* If I enable this, I encourage spilling in the inner loop of compress.
8931 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8932 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8933 effect( USE_KILL tmp, KILL cr );
8934 ins_cost(400);
8935
8936 format %{ "SUB $p,$q\n\t"
8937 "SBB ECX,ECX\n\t"
8938 "AND ECX,$y\n\t"
8939 "ADD $p,ECX" %}
8940 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8941 %}
8942 */
8943
8944 //----------Long Instructions------------------------------------------------
8945 // Add Long Register with Register
8946 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8947 match(Set dst (AddL dst src));
8948 effect(KILL cr);
8949 ins_cost(200);
8950 format %{ "ADD $dst.lo,$src.lo\n\t"
8951 "ADC $dst.hi,$src.hi" %}
8952 opcode(0x03, 0x13);
8953 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8954 ins_pipe( ialu_reg_reg_long );
8955 %}
8956
8957 // Add Long Register with Immediate
8958 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8959 match(Set dst (AddL dst src));
8960 effect(KILL cr);
8961 format %{ "ADD $dst.lo,$src.lo\n\t"
8962 "ADC $dst.hi,$src.hi" %}
8963 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8964 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8965 ins_pipe( ialu_reg_long );
8966 %}
8967
8968 // Add Long Register with Memory
8969 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8970 match(Set dst (AddL dst (LoadL mem)));
8971 effect(KILL cr);
8972 ins_cost(125);
8973 format %{ "ADD $dst.lo,$mem\n\t"
8974 "ADC $dst.hi,$mem+4" %}
8975 opcode(0x03, 0x13);
8976 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8977 ins_pipe( ialu_reg_long_mem );
8978 %}
8979
8980 // Subtract Long Register with Register.
8981 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8982 match(Set dst (SubL dst src));
8983 effect(KILL cr);
8984 ins_cost(200);
8985 format %{ "SUB $dst.lo,$src.lo\n\t"
8986 "SBB $dst.hi,$src.hi" %}
8987 opcode(0x2B, 0x1B);
8988 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8989 ins_pipe( ialu_reg_reg_long );
8990 %}
8991
8992 // Subtract Long Register with Immediate
8993 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8994 match(Set dst (SubL dst src));
8995 effect(KILL cr);
8996 format %{ "SUB $dst.lo,$src.lo\n\t"
8997 "SBB $dst.hi,$src.hi" %}
8998 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8999 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9000 ins_pipe( ialu_reg_long );
9001 %}
9002
9003 // Subtract Long Register with Memory
9004 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9005 match(Set dst (SubL dst (LoadL mem)));
9006 effect(KILL cr);
9007 ins_cost(125);
9008 format %{ "SUB $dst.lo,$mem\n\t"
9009 "SBB $dst.hi,$mem+4" %}
9010 opcode(0x2B, 0x1B);
9011 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9012 ins_pipe( ialu_reg_long_mem );
9013 %}
9014
9015 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9016 match(Set dst (SubL zero dst));
9017 effect(KILL cr);
9018 ins_cost(300);
9019 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9020 ins_encode( neg_long(dst) );
9021 ins_pipe( ialu_reg_reg_long );
9022 %}
9023
9024 // And Long Register with Register
9025 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9026 match(Set dst (AndL dst src));
9027 effect(KILL cr);
9028 format %{ "AND $dst.lo,$src.lo\n\t"
9029 "AND $dst.hi,$src.hi" %}
9030 opcode(0x23,0x23);
9031 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9032 ins_pipe( ialu_reg_reg_long );
9033 %}
9034
9035 // And Long Register with Immediate
9036 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9037 match(Set dst (AndL dst src));
9038 effect(KILL cr);
9039 format %{ "AND $dst.lo,$src.lo\n\t"
9040 "AND $dst.hi,$src.hi" %}
9041 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9042 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9043 ins_pipe( ialu_reg_long );
9044 %}
9045
9046 // And Long Register with Memory
9047 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9048 match(Set dst (AndL dst (LoadL mem)));
9049 effect(KILL cr);
9050 ins_cost(125);
9051 format %{ "AND $dst.lo,$mem\n\t"
9052 "AND $dst.hi,$mem+4" %}
9053 opcode(0x23, 0x23);
9054 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9055 ins_pipe( ialu_reg_long_mem );
9056 %}
9057
9058 // Or Long Register with Register
9059 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9060 match(Set dst (OrL dst src));
9061 effect(KILL cr);
9062 format %{ "OR $dst.lo,$src.lo\n\t"
9063 "OR $dst.hi,$src.hi" %}
9064 opcode(0x0B,0x0B);
9065 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9066 ins_pipe( ialu_reg_reg_long );
9067 %}
9068
9069 // Or Long Register with Immediate
9070 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9071 match(Set dst (OrL dst src));
9072 effect(KILL cr);
9073 format %{ "OR $dst.lo,$src.lo\n\t"
9074 "OR $dst.hi,$src.hi" %}
9075 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9076 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9077 ins_pipe( ialu_reg_long );
9078 %}
9079
9080 // Or Long Register with Memory
9081 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9082 match(Set dst (OrL dst (LoadL mem)));
9083 effect(KILL cr);
9084 ins_cost(125);
9085 format %{ "OR $dst.lo,$mem\n\t"
9086 "OR $dst.hi,$mem+4" %}
9087 opcode(0x0B,0x0B);
9088 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9089 ins_pipe( ialu_reg_long_mem );
9090 %}
9091
9092 // Xor Long Register with Register
9093 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9094 match(Set dst (XorL dst src));
9095 effect(KILL cr);
9096 format %{ "XOR $dst.lo,$src.lo\n\t"
9097 "XOR $dst.hi,$src.hi" %}
9098 opcode(0x33,0x33);
9099 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9100 ins_pipe( ialu_reg_reg_long );
9101 %}
9102
9103 // Xor Long Register with Immediate -1
9104 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9105 match(Set dst (XorL dst imm));
9106 format %{ "NOT $dst.lo\n\t"
9107 "NOT $dst.hi" %}
9108 ins_encode %{
9109 __ notl($dst$$Register);
9110 __ notl(HIGH_FROM_LOW($dst$$Register));
9111 %}
9112 ins_pipe( ialu_reg_long );
9113 %}
9114
9115 // Xor Long Register with Immediate
9116 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9117 match(Set dst (XorL dst src));
9118 effect(KILL cr);
9119 format %{ "XOR $dst.lo,$src.lo\n\t"
9120 "XOR $dst.hi,$src.hi" %}
9121 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9122 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9123 ins_pipe( ialu_reg_long );
9124 %}
9125
9126 // Xor Long Register with Memory
9127 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9128 match(Set dst (XorL dst (LoadL mem)));
9129 effect(KILL cr);
9130 ins_cost(125);
9131 format %{ "XOR $dst.lo,$mem\n\t"
9132 "XOR $dst.hi,$mem+4" %}
9133 opcode(0x33,0x33);
9134 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9135 ins_pipe( ialu_reg_long_mem );
9136 %}
9137
9138 // Shift Left Long by 1
9139 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9140 predicate(UseNewLongLShift);
9141 match(Set dst (LShiftL dst cnt));
9142 effect(KILL cr);
9143 ins_cost(100);
9144 format %{ "ADD $dst.lo,$dst.lo\n\t"
9145 "ADC $dst.hi,$dst.hi" %}
9146 ins_encode %{
9147 __ addl($dst$$Register,$dst$$Register);
9148 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9149 %}
9150 ins_pipe( ialu_reg_long );
9151 %}
9152
9153 // Shift Left Long by 2
9154 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9155 predicate(UseNewLongLShift);
9156 match(Set dst (LShiftL dst cnt));
9157 effect(KILL cr);
9158 ins_cost(100);
9159 format %{ "ADD $dst.lo,$dst.lo\n\t"
9160 "ADC $dst.hi,$dst.hi\n\t"
9161 "ADD $dst.lo,$dst.lo\n\t"
9162 "ADC $dst.hi,$dst.hi" %}
9163 ins_encode %{
9164 __ addl($dst$$Register,$dst$$Register);
9165 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9166 __ addl($dst$$Register,$dst$$Register);
9167 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9168 %}
9169 ins_pipe( ialu_reg_long );
9170 %}
9171
9172 // Shift Left Long by 3
9173 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9174 predicate(UseNewLongLShift);
9175 match(Set dst (LShiftL dst cnt));
9176 effect(KILL cr);
9177 ins_cost(100);
9178 format %{ "ADD $dst.lo,$dst.lo\n\t"
9179 "ADC $dst.hi,$dst.hi\n\t"
9180 "ADD $dst.lo,$dst.lo\n\t"
9181 "ADC $dst.hi,$dst.hi\n\t"
9182 "ADD $dst.lo,$dst.lo\n\t"
9183 "ADC $dst.hi,$dst.hi" %}
9184 ins_encode %{
9185 __ addl($dst$$Register,$dst$$Register);
9186 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9187 __ addl($dst$$Register,$dst$$Register);
9188 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9189 __ addl($dst$$Register,$dst$$Register);
9190 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9191 %}
9192 ins_pipe( ialu_reg_long );
9193 %}
9194
9195 // Shift Left Long by 1-31
9196 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9197 match(Set dst (LShiftL dst cnt));
9198 effect(KILL cr);
9199 ins_cost(200);
9200 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9201 "SHL $dst.lo,$cnt" %}
9202 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9203 ins_encode( move_long_small_shift(dst,cnt) );
9204 ins_pipe( ialu_reg_long );
9205 %}
9206
9207 // Shift Left Long by 32-63
9208 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9209 match(Set dst (LShiftL dst cnt));
9210 effect(KILL cr);
9211 ins_cost(300);
9212 format %{ "MOV $dst.hi,$dst.lo\n"
9213 "\tSHL $dst.hi,$cnt-32\n"
9214 "\tXOR $dst.lo,$dst.lo" %}
9215 opcode(0xC1, 0x4); /* C1 /4 ib */
9216 ins_encode( move_long_big_shift_clr(dst,cnt) );
9217 ins_pipe( ialu_reg_long );
9218 %}
9219
9220 // Shift Left Long by variable
9221 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9222 match(Set dst (LShiftL dst shift));
9223 effect(KILL cr);
9224 ins_cost(500+200);
9225 size(17);
9226 format %{ "TEST $shift,32\n\t"
9227 "JEQ,s small\n\t"
9228 "MOV $dst.hi,$dst.lo\n\t"
9229 "XOR $dst.lo,$dst.lo\n"
9230 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9231 "SHL $dst.lo,$shift" %}
9232 ins_encode( shift_left_long( dst, shift ) );
9233 ins_pipe( pipe_slow );
9234 %}
9235
9236 // Shift Right Long by 1-31
9237 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9238 match(Set dst (URShiftL dst cnt));
9239 effect(KILL cr);
9240 ins_cost(200);
9241 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9242 "SHR $dst.hi,$cnt" %}
9243 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9244 ins_encode( move_long_small_shift(dst,cnt) );
9245 ins_pipe( ialu_reg_long );
9246 %}
9247
9248 // Shift Right Long by 32-63
9249 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9250 match(Set dst (URShiftL dst cnt));
9251 effect(KILL cr);
9252 ins_cost(300);
9253 format %{ "MOV $dst.lo,$dst.hi\n"
9254 "\tSHR $dst.lo,$cnt-32\n"
9255 "\tXOR $dst.hi,$dst.hi" %}
9256 opcode(0xC1, 0x5); /* C1 /5 ib */
9257 ins_encode( move_long_big_shift_clr(dst,cnt) );
9258 ins_pipe( ialu_reg_long );
9259 %}
9260
9261 // Shift Right Long by variable
9262 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9263 match(Set dst (URShiftL dst shift));
9264 effect(KILL cr);
9265 ins_cost(600);
9266 size(17);
9267 format %{ "TEST $shift,32\n\t"
9268 "JEQ,s small\n\t"
9269 "MOV $dst.lo,$dst.hi\n\t"
9270 "XOR $dst.hi,$dst.hi\n"
9271 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9272 "SHR $dst.hi,$shift" %}
9273 ins_encode( shift_right_long( dst, shift ) );
9274 ins_pipe( pipe_slow );
9275 %}
9276
9277 // Shift Right Long by 1-31
9278 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9279 match(Set dst (RShiftL dst cnt));
9280 effect(KILL cr);
9281 ins_cost(200);
9282 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9283 "SAR $dst.hi,$cnt" %}
9284 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9285 ins_encode( move_long_small_shift(dst,cnt) );
9286 ins_pipe( ialu_reg_long );
9287 %}
9288
9289 // Shift Right Long by 32-63
9290 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9291 match(Set dst (RShiftL dst cnt));
9292 effect(KILL cr);
9293 ins_cost(300);
9294 format %{ "MOV $dst.lo,$dst.hi\n"
9295 "\tSAR $dst.lo,$cnt-32\n"
9296 "\tSAR $dst.hi,31" %}
9297 opcode(0xC1, 0x7); /* C1 /7 ib */
9298 ins_encode( move_long_big_shift_sign(dst,cnt) );
9299 ins_pipe( ialu_reg_long );
9300 %}
9301
9302 // Shift Right arithmetic Long by variable
9303 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9304 match(Set dst (RShiftL dst shift));
9305 effect(KILL cr);
9306 ins_cost(600);
9307 size(18);
9308 format %{ "TEST $shift,32\n\t"
9309 "JEQ,s small\n\t"
9310 "MOV $dst.lo,$dst.hi\n\t"
9311 "SAR $dst.hi,31\n"
9312 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9313 "SAR $dst.hi,$shift" %}
9314 ins_encode( shift_right_arith_long( dst, shift ) );
9315 ins_pipe( pipe_slow );
9316 %}
9317
9318
9319 //----------Double Instructions------------------------------------------------
9320 // Double Math
9321
9322 // Compare & branch
9323
9324 // P6 version of float compare, sets condition codes in EFLAGS
9325 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9326 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9327 match(Set cr (CmpD src1 src2));
9328 effect(KILL rax);
9329 ins_cost(150);
9330 format %{ "FLD $src1\n\t"
9331 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9332 "JNP exit\n\t"
9333 "MOV ah,1 // saw a NaN, set CF\n\t"
9334 "SAHF\n"
9335 "exit:\tNOP // avoid branch to branch" %}
9336 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9337 ins_encode( Push_Reg_DPR(src1),
9338 OpcP, RegOpc(src2),
9339 cmpF_P6_fixup );
9340 ins_pipe( pipe_slow );
9341 %}
9342
9343 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9344 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9345 match(Set cr (CmpD src1 src2));
9346 ins_cost(150);
9347 format %{ "FLD $src1\n\t"
9348 "FUCOMIP ST,$src2 // P6 instruction" %}
9349 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9350 ins_encode( Push_Reg_DPR(src1),
9351 OpcP, RegOpc(src2));
9352 ins_pipe( pipe_slow );
9353 %}
9354
9355 // Compare & branch
9356 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9357 predicate(UseSSE<=1);
9358 match(Set cr (CmpD src1 src2));
9359 effect(KILL rax);
9360 ins_cost(200);
9361 format %{ "FLD $src1\n\t"
9362 "FCOMp $src2\n\t"
9363 "FNSTSW AX\n\t"
9364 "TEST AX,0x400\n\t"
9365 "JZ,s flags\n\t"
9366 "MOV AH,1\t# unordered treat as LT\n"
9367 "flags:\tSAHF" %}
9368 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9369 ins_encode( Push_Reg_DPR(src1),
9370 OpcP, RegOpc(src2),
9371 fpu_flags);
9372 ins_pipe( pipe_slow );
9373 %}
9374
9375 // Compare vs zero into -1,0,1
9376 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9377 predicate(UseSSE<=1);
9378 match(Set dst (CmpD3 src1 zero));
9379 effect(KILL cr, KILL rax);
9380 ins_cost(280);
9381 format %{ "FTSTD $dst,$src1" %}
9382 opcode(0xE4, 0xD9);
9383 ins_encode( Push_Reg_DPR(src1),
9384 OpcS, OpcP, PopFPU,
9385 CmpF_Result(dst));
9386 ins_pipe( pipe_slow );
9387 %}
9388
9389 // Compare into -1,0,1
9390 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9391 predicate(UseSSE<=1);
9392 match(Set dst (CmpD3 src1 src2));
9393 effect(KILL cr, KILL rax);
9394 ins_cost(300);
9395 format %{ "FCMPD $dst,$src1,$src2" %}
9396 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9397 ins_encode( Push_Reg_DPR(src1),
9398 OpcP, RegOpc(src2),
9399 CmpF_Result(dst));
9400 ins_pipe( pipe_slow );
9401 %}
9402
9403 // float compare and set condition codes in EFLAGS by XMM regs
9404 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9405 predicate(UseSSE>=2);
9406 match(Set cr (CmpD src1 src2));
9407 ins_cost(145);
9408 format %{ "UCOMISD $src1,$src2\n\t"
9409 "JNP,s exit\n\t"
9410 "PUSHF\t# saw NaN, set CF\n\t"
9411 "AND [rsp], #0xffffff2b\n\t"
9412 "POPF\n"
9413 "exit:" %}
9414 ins_encode %{
9415 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9416 emit_cmpfp_fixup(_masm);
9417 %}
9418 ins_pipe( pipe_slow );
9419 %}
9420
9421 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9422 predicate(UseSSE>=2);
9423 match(Set cr (CmpD src1 src2));
9424 ins_cost(100);
9425 format %{ "UCOMISD $src1,$src2" %}
9426 ins_encode %{
9427 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9428 %}
9429 ins_pipe( pipe_slow );
9430 %}
9431
9432 // float compare and set condition codes in EFLAGS by XMM regs
9433 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9434 predicate(UseSSE>=2);
9435 match(Set cr (CmpD src1 (LoadD src2)));
9436 ins_cost(145);
9437 format %{ "UCOMISD $src1,$src2\n\t"
9438 "JNP,s exit\n\t"
9439 "PUSHF\t# saw NaN, set CF\n\t"
9440 "AND [rsp], #0xffffff2b\n\t"
9441 "POPF\n"
9442 "exit:" %}
9443 ins_encode %{
9444 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9445 emit_cmpfp_fixup(_masm);
9446 %}
9447 ins_pipe( pipe_slow );
9448 %}
9449
9450 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9451 predicate(UseSSE>=2);
9452 match(Set cr (CmpD src1 (LoadD src2)));
9453 ins_cost(100);
9454 format %{ "UCOMISD $src1,$src2" %}
9455 ins_encode %{
9456 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9457 %}
9458 ins_pipe( pipe_slow );
9459 %}
9460
9461 // Compare into -1,0,1 in XMM
9462 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9463 predicate(UseSSE>=2);
9464 match(Set dst (CmpD3 src1 src2));
9465 effect(KILL cr);
9466 ins_cost(255);
9467 format %{ "UCOMISD $src1, $src2\n\t"
9468 "MOV $dst, #-1\n\t"
9469 "JP,s done\n\t"
9470 "JB,s done\n\t"
9471 "SETNE $dst\n\t"
9472 "MOVZB $dst, $dst\n"
9473 "done:" %}
9474 ins_encode %{
9475 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9476 emit_cmpfp3(_masm, $dst$$Register);
9477 %}
9478 ins_pipe( pipe_slow );
9479 %}
9480
9481 // Compare into -1,0,1 in XMM and memory
9482 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9483 predicate(UseSSE>=2);
9484 match(Set dst (CmpD3 src1 (LoadD src2)));
9485 effect(KILL cr);
9486 ins_cost(275);
9487 format %{ "UCOMISD $src1, $src2\n\t"
9488 "MOV $dst, #-1\n\t"
9489 "JP,s done\n\t"
9490 "JB,s done\n\t"
9491 "SETNE $dst\n\t"
9492 "MOVZB $dst, $dst\n"
9493 "done:" %}
9494 ins_encode %{
9495 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9496 emit_cmpfp3(_masm, $dst$$Register);
9497 %}
9498 ins_pipe( pipe_slow );
9499 %}
9500
9501
9502 instruct subDPR_reg(regDPR dst, regDPR src) %{
9503 predicate (UseSSE <=1);
9504 match(Set dst (SubD dst src));
9505
9506 format %{ "FLD $src\n\t"
9507 "DSUBp $dst,ST" %}
9508 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9509 ins_cost(150);
9510 ins_encode( Push_Reg_DPR(src),
9511 OpcP, RegOpc(dst) );
9512 ins_pipe( fpu_reg_reg );
9513 %}
9514
9515 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9516 predicate (UseSSE <=1);
9517 match(Set dst (RoundDouble (SubD src1 src2)));
9518 ins_cost(250);
9519
9520 format %{ "FLD $src2\n\t"
9521 "DSUB ST,$src1\n\t"
9522 "FSTP_D $dst\t# D-round" %}
9523 opcode(0xD8, 0x5);
9524 ins_encode( Push_Reg_DPR(src2),
9525 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9526 ins_pipe( fpu_mem_reg_reg );
9527 %}
9528
9529
9530 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9531 predicate (UseSSE <=1);
9532 match(Set dst (SubD dst (LoadD src)));
9533 ins_cost(150);
9534
9535 format %{ "FLD $src\n\t"
9536 "DSUBp $dst,ST" %}
9537 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9538 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9539 OpcP, RegOpc(dst) );
9540 ins_pipe( fpu_reg_mem );
9541 %}
9542
9543 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9544 predicate (UseSSE<=1);
9545 match(Set dst (AbsD src));
9546 ins_cost(100);
9547 format %{ "FABS" %}
9548 opcode(0xE1, 0xD9);
9549 ins_encode( OpcS, OpcP );
9550 ins_pipe( fpu_reg_reg );
9551 %}
9552
9553 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9554 predicate(UseSSE<=1);
9555 match(Set dst (NegD src));
9556 ins_cost(100);
9557 format %{ "FCHS" %}
9558 opcode(0xE0, 0xD9);
9559 ins_encode( OpcS, OpcP );
9560 ins_pipe( fpu_reg_reg );
9561 %}
9562
9563 instruct addDPR_reg(regDPR dst, regDPR src) %{
9564 predicate(UseSSE<=1);
9565 match(Set dst (AddD dst src));
9566 format %{ "FLD $src\n\t"
9567 "DADD $dst,ST" %}
9568 size(4);
9569 ins_cost(150);
9570 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9571 ins_encode( Push_Reg_DPR(src),
9572 OpcP, RegOpc(dst) );
9573 ins_pipe( fpu_reg_reg );
9574 %}
9575
9576
9577 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9578 predicate(UseSSE<=1);
9579 match(Set dst (RoundDouble (AddD src1 src2)));
9580 ins_cost(250);
9581
9582 format %{ "FLD $src2\n\t"
9583 "DADD ST,$src1\n\t"
9584 "FSTP_D $dst\t# D-round" %}
9585 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9586 ins_encode( Push_Reg_DPR(src2),
9587 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9588 ins_pipe( fpu_mem_reg_reg );
9589 %}
9590
9591
9592 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9593 predicate(UseSSE<=1);
9594 match(Set dst (AddD dst (LoadD src)));
9595 ins_cost(150);
9596
9597 format %{ "FLD $src\n\t"
9598 "DADDp $dst,ST" %}
9599 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9600 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9601 OpcP, RegOpc(dst) );
9602 ins_pipe( fpu_reg_mem );
9603 %}
9604
9605 // add-to-memory
9606 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9607 predicate(UseSSE<=1);
9608 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9609 ins_cost(150);
9610
9611 format %{ "FLD_D $dst\n\t"
9612 "DADD ST,$src\n\t"
9613 "FST_D $dst" %}
9614 opcode(0xDD, 0x0);
9615 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9616 Opcode(0xD8), RegOpc(src),
9617 set_instruction_start,
9618 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9619 ins_pipe( fpu_reg_mem );
9620 %}
9621
9622 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9623 predicate(UseSSE<=1);
9624 match(Set dst (AddD dst con));
9625 ins_cost(125);
9626 format %{ "FLD1\n\t"
9627 "DADDp $dst,ST" %}
9628 ins_encode %{
9629 __ fld1();
9630 __ faddp($dst$$reg);
9631 %}
9632 ins_pipe(fpu_reg);
9633 %}
9634
9635 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9636 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9637 match(Set dst (AddD dst con));
9638 ins_cost(200);
9639 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9640 "DADDp $dst,ST" %}
9641 ins_encode %{
9642 __ fld_d($constantaddress($con));
9643 __ faddp($dst$$reg);
9644 %}
9645 ins_pipe(fpu_reg_mem);
9646 %}
9647
9648 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9649 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9650 match(Set dst (RoundDouble (AddD src con)));
9651 ins_cost(200);
9652 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9653 "DADD ST,$src\n\t"
9654 "FSTP_D $dst\t# D-round" %}
9655 ins_encode %{
9656 __ fld_d($constantaddress($con));
9657 __ fadd($src$$reg);
9658 __ fstp_d(Address(rsp, $dst$$disp));
9659 %}
9660 ins_pipe(fpu_mem_reg_con);
9661 %}
9662
9663 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9664 predicate(UseSSE<=1);
9665 match(Set dst (MulD dst src));
9666 format %{ "FLD $src\n\t"
9667 "DMULp $dst,ST" %}
9668 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9669 ins_cost(150);
9670 ins_encode( Push_Reg_DPR(src),
9671 OpcP, RegOpc(dst) );
9672 ins_pipe( fpu_reg_reg );
9673 %}
9674
9675 // Strict FP instruction biases argument before multiply then
9676 // biases result to avoid double rounding of subnormals.
9677 //
9678 // scale arg1 by multiplying arg1 by 2^(-15360)
9679 // load arg2
9680 // multiply scaled arg1 by arg2
9681 // rescale product by 2^(15360)
9682 //
9683 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9684 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9685 match(Set dst (MulD dst src));
9686 ins_cost(1); // Select this instruction for all strict FP double multiplies
9687
9688 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9689 "DMULp $dst,ST\n\t"
9690 "FLD $src\n\t"
9691 "DMULp $dst,ST\n\t"
9692 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9693 "DMULp $dst,ST\n\t" %}
9694 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9695 ins_encode( strictfp_bias1(dst),
9696 Push_Reg_DPR(src),
9697 OpcP, RegOpc(dst),
9698 strictfp_bias2(dst) );
9699 ins_pipe( fpu_reg_reg );
9700 %}
9701
9702 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9703 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9704 match(Set dst (MulD dst con));
9705 ins_cost(200);
9706 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9707 "DMULp $dst,ST" %}
9708 ins_encode %{
9709 __ fld_d($constantaddress($con));
9710 __ fmulp($dst$$reg);
9711 %}
9712 ins_pipe(fpu_reg_mem);
9713 %}
9714
9715
9716 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9717 predicate( UseSSE<=1 );
9718 match(Set dst (MulD dst (LoadD src)));
9719 ins_cost(200);
9720 format %{ "FLD_D $src\n\t"
9721 "DMULp $dst,ST" %}
9722 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9723 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9724 OpcP, RegOpc(dst) );
9725 ins_pipe( fpu_reg_mem );
9726 %}
9727
9728 //
9729 // Cisc-alternate to reg-reg multiply
9730 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9731 predicate( UseSSE<=1 );
9732 match(Set dst (MulD src (LoadD mem)));
9733 ins_cost(250);
9734 format %{ "FLD_D $mem\n\t"
9735 "DMUL ST,$src\n\t"
9736 "FSTP_D $dst" %}
9737 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9738 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9739 OpcReg_FPR(src),
9740 Pop_Reg_DPR(dst) );
9741 ins_pipe( fpu_reg_reg_mem );
9742 %}
9743
9744
9745 // MACRO3 -- addDPR a mulDPR
9746 // This instruction is a '2-address' instruction in that the result goes
9747 // back to src2. This eliminates a move from the macro; possibly the
9748 // register allocator will have to add it back (and maybe not).
9749 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9750 predicate( UseSSE<=1 );
9751 match(Set src2 (AddD (MulD src0 src1) src2));
9752 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9753 "DMUL ST,$src1\n\t"
9754 "DADDp $src2,ST" %}
9755 ins_cost(250);
9756 opcode(0xDD); /* LoadD DD /0 */
9757 ins_encode( Push_Reg_FPR(src0),
9758 FMul_ST_reg(src1),
9759 FAddP_reg_ST(src2) );
9760 ins_pipe( fpu_reg_reg_reg );
9761 %}
9762
9763
9764 // MACRO3 -- subDPR a mulDPR
9765 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9766 predicate( UseSSE<=1 );
9767 match(Set src2 (SubD (MulD src0 src1) src2));
9768 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9769 "DMUL ST,$src1\n\t"
9770 "DSUBRp $src2,ST" %}
9771 ins_cost(250);
9772 ins_encode( Push_Reg_FPR(src0),
9773 FMul_ST_reg(src1),
9774 Opcode(0xDE), Opc_plus(0xE0,src2));
9775 ins_pipe( fpu_reg_reg_reg );
9776 %}
9777
9778
9779 instruct divDPR_reg(regDPR dst, regDPR src) %{
9780 predicate( UseSSE<=1 );
9781 match(Set dst (DivD dst src));
9782
9783 format %{ "FLD $src\n\t"
9784 "FDIVp $dst,ST" %}
9785 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9786 ins_cost(150);
9787 ins_encode( Push_Reg_DPR(src),
9788 OpcP, RegOpc(dst) );
9789 ins_pipe( fpu_reg_reg );
9790 %}
9791
9792 // Strict FP instruction biases argument before division then
9793 // biases result, to avoid double rounding of subnormals.
9794 //
9795 // scale dividend by multiplying dividend by 2^(-15360)
9796 // load divisor
9797 // divide scaled dividend by divisor
9798 // rescale quotient by 2^(15360)
9799 //
9800 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9801 predicate (UseSSE<=1);
9802 match(Set dst (DivD dst src));
9803 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9804 ins_cost(01);
9805
9806 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9807 "DMULp $dst,ST\n\t"
9808 "FLD $src\n\t"
9809 "FDIVp $dst,ST\n\t"
9810 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9811 "DMULp $dst,ST\n\t" %}
9812 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9813 ins_encode( strictfp_bias1(dst),
9814 Push_Reg_DPR(src),
9815 OpcP, RegOpc(dst),
9816 strictfp_bias2(dst) );
9817 ins_pipe( fpu_reg_reg );
9818 %}
9819
9820 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9821 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9822 match(Set dst (RoundDouble (DivD src1 src2)));
9823
9824 format %{ "FLD $src1\n\t"
9825 "FDIV ST,$src2\n\t"
9826 "FSTP_D $dst\t# D-round" %}
9827 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9828 ins_encode( Push_Reg_DPR(src1),
9829 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9830 ins_pipe( fpu_mem_reg_reg );
9831 %}
9832
9833
9834 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9835 predicate(UseSSE<=1);
9836 match(Set dst (ModD dst src));
9837 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9838
9839 format %{ "DMOD $dst,$src" %}
9840 ins_cost(250);
9841 ins_encode(Push_Reg_Mod_DPR(dst, src),
9842 emitModDPR(),
9843 Push_Result_Mod_DPR(src),
9844 Pop_Reg_DPR(dst));
9845 ins_pipe( pipe_slow );
9846 %}
9847
9848 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9849 predicate(UseSSE>=2);
9850 match(Set dst (ModD src0 src1));
9851 effect(KILL rax, KILL cr);
9852
9853 format %{ "SUB ESP,8\t # DMOD\n"
9854 "\tMOVSD [ESP+0],$src1\n"
9855 "\tFLD_D [ESP+0]\n"
9856 "\tMOVSD [ESP+0],$src0\n"
9857 "\tFLD_D [ESP+0]\n"
9858 "loop:\tFPREM\n"
9859 "\tFWAIT\n"
9860 "\tFNSTSW AX\n"
9861 "\tSAHF\n"
9862 "\tJP loop\n"
9863 "\tFSTP_D [ESP+0]\n"
9864 "\tMOVSD $dst,[ESP+0]\n"
9865 "\tADD ESP,8\n"
9866 "\tFSTP ST0\t # Restore FPU Stack"
9867 %}
9868 ins_cost(250);
9869 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9870 ins_pipe( pipe_slow );
9871 %}
9872
9873 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9874 predicate (UseSSE<=1);
9875 match(Set dst (SinD src));
9876 ins_cost(1800);
9877 format %{ "DSIN $dst" %}
9878 opcode(0xD9, 0xFE);
9879 ins_encode( OpcP, OpcS );
9880 ins_pipe( pipe_slow );
9881 %}
9882
9883 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9884 predicate (UseSSE>=2);
9885 match(Set dst (SinD dst));
9886 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9887 ins_cost(1800);
9888 format %{ "DSIN $dst" %}
9889 opcode(0xD9, 0xFE);
9890 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9891 ins_pipe( pipe_slow );
9892 %}
9893
9894 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9895 predicate (UseSSE<=1);
9896 match(Set dst (CosD src));
9897 ins_cost(1800);
9898 format %{ "DCOS $dst" %}
9899 opcode(0xD9, 0xFF);
9900 ins_encode( OpcP, OpcS );
9901 ins_pipe( pipe_slow );
9902 %}
9903
9904 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9905 predicate (UseSSE>=2);
9906 match(Set dst (CosD dst));
9907 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9908 ins_cost(1800);
9909 format %{ "DCOS $dst" %}
9910 opcode(0xD9, 0xFF);
9911 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9912 ins_pipe( pipe_slow );
9913 %}
9914
9915 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9916 predicate (UseSSE<=1);
9917 match(Set dst(TanD src));
9918 format %{ "DTAN $dst" %}
9919 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9920 Opcode(0xDD), Opcode(0xD8)); // fstp st
9921 ins_pipe( pipe_slow );
9922 %}
9923
9924 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9925 predicate (UseSSE>=2);
9926 match(Set dst(TanD dst));
9927 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9928 format %{ "DTAN $dst" %}
9929 ins_encode( Push_SrcD(dst),
9930 Opcode(0xD9), Opcode(0xF2), // fptan
9931 Opcode(0xDD), Opcode(0xD8), // fstp st
9932 Push_ResultD(dst) );
9933 ins_pipe( pipe_slow );
9934 %}
9935
9936 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9937 predicate (UseSSE<=1);
9938 match(Set dst(AtanD dst src));
9939 format %{ "DATA $dst,$src" %}
9940 opcode(0xD9, 0xF3);
9941 ins_encode( Push_Reg_DPR(src),
9942 OpcP, OpcS, RegOpc(dst) );
9943 ins_pipe( pipe_slow );
9944 %}
9945
9946 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9947 predicate (UseSSE>=2);
9948 match(Set dst(AtanD dst src));
9949 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9950 format %{ "DATA $dst,$src" %}
9951 opcode(0xD9, 0xF3);
9952 ins_encode( Push_SrcD(src),
9953 OpcP, OpcS, Push_ResultD(dst) );
9954 ins_pipe( pipe_slow );
9955 %}
9956
9957 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9958 predicate (UseSSE<=1);
9959 match(Set dst (SqrtD src));
9960 format %{ "DSQRT $dst,$src" %}
9961 opcode(0xFA, 0xD9);
9962 ins_encode( Push_Reg_DPR(src),
9963 OpcS, OpcP, Pop_Reg_DPR(dst) );
9964 ins_pipe( pipe_slow );
9965 %}
9966
9967 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9968 predicate (UseSSE<=1);
9969 match(Set Y (PowD X Y)); // Raise X to the Yth power
9970 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9971 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9972 ins_encode %{
9973 __ subptr(rsp, 8);
9974 __ fld_s($X$$reg - 1);
9975 __ fast_pow();
9976 __ addptr(rsp, 8);
9977 %}
9978 ins_pipe( pipe_slow );
9979 %}
9980
9981 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9982 predicate (UseSSE>=2);
9983 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9984 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9985 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9986 ins_encode %{
9987 __ subptr(rsp, 8);
9988 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9989 __ fld_d(Address(rsp, 0));
9990 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9991 __ fld_d(Address(rsp, 0));
9992 __ fast_pow();
9993 __ fstp_d(Address(rsp, 0));
9994 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9995 __ addptr(rsp, 8);
9996 %}
9997 ins_pipe( pipe_slow );
9998 %}
9999
10000
10001 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10002 predicate (UseSSE<=1);
10003 match(Set dpr1 (ExpD dpr1));
10004 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10005 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10006 ins_encode %{
10007 __ fast_exp();
10008 %}
10009 ins_pipe( pipe_slow );
10010 %}
10011
10012 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10013 predicate (UseSSE>=2);
10014 match(Set dst (ExpD src));
10015 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10016 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10017 ins_encode %{
10018 __ subptr(rsp, 8);
10019 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10020 __ fld_d(Address(rsp, 0));
10021 __ fast_exp();
10022 __ fstp_d(Address(rsp, 0));
10023 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10024 __ addptr(rsp, 8);
10025 %}
10026 ins_pipe( pipe_slow );
10027 %}
10028
10029 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10030 predicate (UseSSE<=1);
10031 // The source Double operand on FPU stack
10032 match(Set dst (Log10D src));
10033 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10034 // fxch ; swap ST(0) with ST(1)
10035 // fyl2x ; compute log_10(2) * log_2(x)
10036 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10037 "FXCH \n\t"
10038 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10039 %}
10040 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10041 Opcode(0xD9), Opcode(0xC9), // fxch
10042 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10043
10044 ins_pipe( pipe_slow );
10045 %}
10046
10047 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10048 predicate (UseSSE>=2);
10049 effect(KILL cr);
10050 match(Set dst (Log10D src));
10051 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10052 // fyl2x ; compute log_10(2) * log_2(x)
10053 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10054 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10055 %}
10056 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10057 Push_SrcD(src),
10058 Opcode(0xD9), Opcode(0xF1), // fyl2x
10059 Push_ResultD(dst));
10060
10061 ins_pipe( pipe_slow );
10062 %}
10063
10064 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10065 predicate (UseSSE<=1);
10066 // The source Double operand on FPU stack
10067 match(Set dst (LogD src));
10068 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10069 // fxch ; swap ST(0) with ST(1)
10070 // fyl2x ; compute log_e(2) * log_2(x)
10071 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10072 "FXCH \n\t"
10073 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10074 %}
10075 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10076 Opcode(0xD9), Opcode(0xC9), // fxch
10077 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10078
10079 ins_pipe( pipe_slow );
10080 %}
10081
10082 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10083 predicate (UseSSE>=2);
10084 effect(KILL cr);
10085 // The source and result Double operands in XMM registers
10086 match(Set dst (LogD src));
10087 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10088 // fyl2x ; compute log_e(2) * log_2(x)
10089 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10090 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10091 %}
10092 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10093 Push_SrcD(src),
10094 Opcode(0xD9), Opcode(0xF1), // fyl2x
10095 Push_ResultD(dst));
10096 ins_pipe( pipe_slow );
10097 %}
10098
10099 //-------------Float Instructions-------------------------------
10100 // Float Math
10101
10102 // Code for float compare:
10103 // fcompp();
10104 // fwait(); fnstsw_ax();
10105 // sahf();
10106 // movl(dst, unordered_result);
10107 // jcc(Assembler::parity, exit);
10108 // movl(dst, less_result);
10109 // jcc(Assembler::below, exit);
10110 // movl(dst, equal_result);
10111 // jcc(Assembler::equal, exit);
10112 // movl(dst, greater_result);
10113 // exit:
10114
10115 // P6 version of float compare, sets condition codes in EFLAGS
10116 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10117 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10118 match(Set cr (CmpF src1 src2));
10119 effect(KILL rax);
10120 ins_cost(150);
10121 format %{ "FLD $src1\n\t"
10122 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10123 "JNP exit\n\t"
10124 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10125 "SAHF\n"
10126 "exit:\tNOP // avoid branch to branch" %}
10127 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10128 ins_encode( Push_Reg_DPR(src1),
10129 OpcP, RegOpc(src2),
10130 cmpF_P6_fixup );
10131 ins_pipe( pipe_slow );
10132 %}
10133
10134 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10135 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10136 match(Set cr (CmpF src1 src2));
10137 ins_cost(100);
10138 format %{ "FLD $src1\n\t"
10139 "FUCOMIP ST,$src2 // P6 instruction" %}
10140 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10141 ins_encode( Push_Reg_DPR(src1),
10142 OpcP, RegOpc(src2));
10143 ins_pipe( pipe_slow );
10144 %}
10145
10146
10147 // Compare & branch
10148 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10149 predicate(UseSSE == 0);
10150 match(Set cr (CmpF src1 src2));
10151 effect(KILL rax);
10152 ins_cost(200);
10153 format %{ "FLD $src1\n\t"
10154 "FCOMp $src2\n\t"
10155 "FNSTSW AX\n\t"
10156 "TEST AX,0x400\n\t"
10157 "JZ,s flags\n\t"
10158 "MOV AH,1\t# unordered treat as LT\n"
10159 "flags:\tSAHF" %}
10160 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10161 ins_encode( Push_Reg_DPR(src1),
10162 OpcP, RegOpc(src2),
10163 fpu_flags);
10164 ins_pipe( pipe_slow );
10165 %}
10166
10167 // Compare vs zero into -1,0,1
10168 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10169 predicate(UseSSE == 0);
10170 match(Set dst (CmpF3 src1 zero));
10171 effect(KILL cr, KILL rax);
10172 ins_cost(280);
10173 format %{ "FTSTF $dst,$src1" %}
10174 opcode(0xE4, 0xD9);
10175 ins_encode( Push_Reg_DPR(src1),
10176 OpcS, OpcP, PopFPU,
10177 CmpF_Result(dst));
10178 ins_pipe( pipe_slow );
10179 %}
10180
10181 // Compare into -1,0,1
10182 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10183 predicate(UseSSE == 0);
10184 match(Set dst (CmpF3 src1 src2));
10185 effect(KILL cr, KILL rax);
10186 ins_cost(300);
10187 format %{ "FCMPF $dst,$src1,$src2" %}
10188 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10189 ins_encode( Push_Reg_DPR(src1),
10190 OpcP, RegOpc(src2),
10191 CmpF_Result(dst));
10192 ins_pipe( pipe_slow );
10193 %}
10194
10195 // float compare and set condition codes in EFLAGS by XMM regs
10196 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10197 predicate(UseSSE>=1);
10198 match(Set cr (CmpF src1 src2));
10199 ins_cost(145);
10200 format %{ "UCOMISS $src1,$src2\n\t"
10201 "JNP,s exit\n\t"
10202 "PUSHF\t# saw NaN, set CF\n\t"
10203 "AND [rsp], #0xffffff2b\n\t"
10204 "POPF\n"
10205 "exit:" %}
10206 ins_encode %{
10207 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10208 emit_cmpfp_fixup(_masm);
10209 %}
10210 ins_pipe( pipe_slow );
10211 %}
10212
10213 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10214 predicate(UseSSE>=1);
10215 match(Set cr (CmpF src1 src2));
10216 ins_cost(100);
10217 format %{ "UCOMISS $src1,$src2" %}
10218 ins_encode %{
10219 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10220 %}
10221 ins_pipe( pipe_slow );
10222 %}
10223
10224 // float compare and set condition codes in EFLAGS by XMM regs
10225 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10226 predicate(UseSSE>=1);
10227 match(Set cr (CmpF src1 (LoadF src2)));
10228 ins_cost(165);
10229 format %{ "UCOMISS $src1,$src2\n\t"
10230 "JNP,s exit\n\t"
10231 "PUSHF\t# saw NaN, set CF\n\t"
10232 "AND [rsp], #0xffffff2b\n\t"
10233 "POPF\n"
10234 "exit:" %}
10235 ins_encode %{
10236 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10237 emit_cmpfp_fixup(_masm);
10238 %}
10239 ins_pipe( pipe_slow );
10240 %}
10241
10242 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10243 predicate(UseSSE>=1);
10244 match(Set cr (CmpF src1 (LoadF src2)));
10245 ins_cost(100);
10246 format %{ "UCOMISS $src1,$src2" %}
10247 ins_encode %{
10248 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10249 %}
10250 ins_pipe( pipe_slow );
10251 %}
10252
10253 // Compare into -1,0,1 in XMM
10254 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10255 predicate(UseSSE>=1);
10256 match(Set dst (CmpF3 src1 src2));
10257 effect(KILL cr);
10258 ins_cost(255);
10259 format %{ "UCOMISS $src1, $src2\n\t"
10260 "MOV $dst, #-1\n\t"
10261 "JP,s done\n\t"
10262 "JB,s done\n\t"
10263 "SETNE $dst\n\t"
10264 "MOVZB $dst, $dst\n"
10265 "done:" %}
10266 ins_encode %{
10267 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10268 emit_cmpfp3(_masm, $dst$$Register);
10269 %}
10270 ins_pipe( pipe_slow );
10271 %}
10272
10273 // Compare into -1,0,1 in XMM and memory
10274 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10275 predicate(UseSSE>=1);
10276 match(Set dst (CmpF3 src1 (LoadF src2)));
10277 effect(KILL cr);
10278 ins_cost(275);
10279 format %{ "UCOMISS $src1, $src2\n\t"
10280 "MOV $dst, #-1\n\t"
10281 "JP,s done\n\t"
10282 "JB,s done\n\t"
10283 "SETNE $dst\n\t"
10284 "MOVZB $dst, $dst\n"
10285 "done:" %}
10286 ins_encode %{
10287 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10288 emit_cmpfp3(_masm, $dst$$Register);
10289 %}
10290 ins_pipe( pipe_slow );
10291 %}
10292
10293 // Spill to obtain 24-bit precision
10294 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10295 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10296 match(Set dst (SubF src1 src2));
10297
10298 format %{ "FSUB $dst,$src1 - $src2" %}
10299 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10300 ins_encode( Push_Reg_FPR(src1),
10301 OpcReg_FPR(src2),
10302 Pop_Mem_FPR(dst) );
10303 ins_pipe( fpu_mem_reg_reg );
10304 %}
10305 //
10306 // This instruction does not round to 24-bits
10307 instruct subFPR_reg(regFPR dst, regFPR src) %{
10308 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10309 match(Set dst (SubF dst src));
10310
10311 format %{ "FSUB $dst,$src" %}
10312 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10313 ins_encode( Push_Reg_FPR(src),
10314 OpcP, RegOpc(dst) );
10315 ins_pipe( fpu_reg_reg );
10316 %}
10317
10318 // Spill to obtain 24-bit precision
10319 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10320 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10321 match(Set dst (AddF src1 src2));
10322
10323 format %{ "FADD $dst,$src1,$src2" %}
10324 opcode(0xD8, 0x0); /* D8 C0+i */
10325 ins_encode( Push_Reg_FPR(src2),
10326 OpcReg_FPR(src1),
10327 Pop_Mem_FPR(dst) );
10328 ins_pipe( fpu_mem_reg_reg );
10329 %}
10330 //
10331 // This instruction does not round to 24-bits
10332 instruct addFPR_reg(regFPR dst, regFPR src) %{
10333 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10334 match(Set dst (AddF dst src));
10335
10336 format %{ "FLD $src\n\t"
10337 "FADDp $dst,ST" %}
10338 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10339 ins_encode( Push_Reg_FPR(src),
10340 OpcP, RegOpc(dst) );
10341 ins_pipe( fpu_reg_reg );
10342 %}
10343
10344 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10345 predicate(UseSSE==0);
10346 match(Set dst (AbsF src));
10347 ins_cost(100);
10348 format %{ "FABS" %}
10349 opcode(0xE1, 0xD9);
10350 ins_encode( OpcS, OpcP );
10351 ins_pipe( fpu_reg_reg );
10352 %}
10353
10354 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10355 predicate(UseSSE==0);
10356 match(Set dst (NegF src));
10357 ins_cost(100);
10358 format %{ "FCHS" %}
10359 opcode(0xE0, 0xD9);
10360 ins_encode( OpcS, OpcP );
10361 ins_pipe( fpu_reg_reg );
10362 %}
10363
10364 // Cisc-alternate to addFPR_reg
10365 // Spill to obtain 24-bit precision
10366 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10367 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10368 match(Set dst (AddF src1 (LoadF src2)));
10369
10370 format %{ "FLD $src2\n\t"
10371 "FADD ST,$src1\n\t"
10372 "FSTP_S $dst" %}
10373 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10374 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10375 OpcReg_FPR(src1),
10376 Pop_Mem_FPR(dst) );
10377 ins_pipe( fpu_mem_reg_mem );
10378 %}
10379 //
10380 // Cisc-alternate to addFPR_reg
10381 // This instruction does not round to 24-bits
10382 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10383 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10384 match(Set dst (AddF dst (LoadF src)));
10385
10386 format %{ "FADD $dst,$src" %}
10387 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10388 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10389 OpcP, RegOpc(dst) );
10390 ins_pipe( fpu_reg_mem );
10391 %}
10392
10393 // // Following two instructions for _222_mpegaudio
10394 // Spill to obtain 24-bit precision
10395 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10396 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10397 match(Set dst (AddF src1 src2));
10398
10399 format %{ "FADD $dst,$src1,$src2" %}
10400 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10401 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10402 OpcReg_FPR(src2),
10403 Pop_Mem_FPR(dst) );
10404 ins_pipe( fpu_mem_reg_mem );
10405 %}
10406
10407 // Cisc-spill variant
10408 // Spill to obtain 24-bit precision
10409 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10410 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10411 match(Set dst (AddF src1 (LoadF src2)));
10412
10413 format %{ "FADD $dst,$src1,$src2 cisc" %}
10414 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10415 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10416 set_instruction_start,
10417 OpcP, RMopc_Mem(secondary,src1),
10418 Pop_Mem_FPR(dst) );
10419 ins_pipe( fpu_mem_mem_mem );
10420 %}
10421
10422 // Spill to obtain 24-bit precision
10423 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10424 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10425 match(Set dst (AddF src1 src2));
10426
10427 format %{ "FADD $dst,$src1,$src2" %}
10428 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10429 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10430 set_instruction_start,
10431 OpcP, RMopc_Mem(secondary,src1),
10432 Pop_Mem_FPR(dst) );
10433 ins_pipe( fpu_mem_mem_mem );
10434 %}
10435
10436
10437 // Spill to obtain 24-bit precision
10438 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10439 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10440 match(Set dst (AddF src con));
10441 format %{ "FLD $src\n\t"
10442 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10443 "FSTP_S $dst" %}
10444 ins_encode %{
10445 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10446 __ fadd_s($constantaddress($con));
10447 __ fstp_s(Address(rsp, $dst$$disp));
10448 %}
10449 ins_pipe(fpu_mem_reg_con);
10450 %}
10451 //
10452 // This instruction does not round to 24-bits
10453 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10454 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10455 match(Set dst (AddF src con));
10456 format %{ "FLD $src\n\t"
10457 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10458 "FSTP $dst" %}
10459 ins_encode %{
10460 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10461 __ fadd_s($constantaddress($con));
10462 __ fstp_d($dst$$reg);
10463 %}
10464 ins_pipe(fpu_reg_reg_con);
10465 %}
10466
10467 // Spill to obtain 24-bit precision
10468 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10469 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10470 match(Set dst (MulF src1 src2));
10471
10472 format %{ "FLD $src1\n\t"
10473 "FMUL $src2\n\t"
10474 "FSTP_S $dst" %}
10475 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10476 ins_encode( Push_Reg_FPR(src1),
10477 OpcReg_FPR(src2),
10478 Pop_Mem_FPR(dst) );
10479 ins_pipe( fpu_mem_reg_reg );
10480 %}
10481 //
10482 // This instruction does not round to 24-bits
10483 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10484 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10485 match(Set dst (MulF src1 src2));
10486
10487 format %{ "FLD $src1\n\t"
10488 "FMUL $src2\n\t"
10489 "FSTP_S $dst" %}
10490 opcode(0xD8, 0x1); /* D8 C8+i */
10491 ins_encode( Push_Reg_FPR(src2),
10492 OpcReg_FPR(src1),
10493 Pop_Reg_FPR(dst) );
10494 ins_pipe( fpu_reg_reg_reg );
10495 %}
10496
10497
10498 // Spill to obtain 24-bit precision
10499 // Cisc-alternate to reg-reg multiply
10500 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10501 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10502 match(Set dst (MulF src1 (LoadF src2)));
10503
10504 format %{ "FLD_S $src2\n\t"
10505 "FMUL $src1\n\t"
10506 "FSTP_S $dst" %}
10507 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10508 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10509 OpcReg_FPR(src1),
10510 Pop_Mem_FPR(dst) );
10511 ins_pipe( fpu_mem_reg_mem );
10512 %}
10513 //
10514 // This instruction does not round to 24-bits
10515 // Cisc-alternate to reg-reg multiply
10516 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10517 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10518 match(Set dst (MulF src1 (LoadF src2)));
10519
10520 format %{ "FMUL $dst,$src1,$src2" %}
10521 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10522 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10523 OpcReg_FPR(src1),
10524 Pop_Reg_FPR(dst) );
10525 ins_pipe( fpu_reg_reg_mem );
10526 %}
10527
10528 // Spill to obtain 24-bit precision
10529 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10530 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10531 match(Set dst (MulF src1 src2));
10532
10533 format %{ "FMUL $dst,$src1,$src2" %}
10534 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10535 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10536 set_instruction_start,
10537 OpcP, RMopc_Mem(secondary,src1),
10538 Pop_Mem_FPR(dst) );
10539 ins_pipe( fpu_mem_mem_mem );
10540 %}
10541
10542 // Spill to obtain 24-bit precision
10543 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10544 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10545 match(Set dst (MulF src con));
10546
10547 format %{ "FLD $src\n\t"
10548 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10549 "FSTP_S $dst" %}
10550 ins_encode %{
10551 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10552 __ fmul_s($constantaddress($con));
10553 __ fstp_s(Address(rsp, $dst$$disp));
10554 %}
10555 ins_pipe(fpu_mem_reg_con);
10556 %}
10557 //
10558 // This instruction does not round to 24-bits
10559 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10560 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10561 match(Set dst (MulF src con));
10562
10563 format %{ "FLD $src\n\t"
10564 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10565 "FSTP $dst" %}
10566 ins_encode %{
10567 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10568 __ fmul_s($constantaddress($con));
10569 __ fstp_d($dst$$reg);
10570 %}
10571 ins_pipe(fpu_reg_reg_con);
10572 %}
10573
10574
10575 //
10576 // MACRO1 -- subsume unshared load into mulFPR
10577 // This instruction does not round to 24-bits
10578 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10579 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10580 match(Set dst (MulF (LoadF mem1) src));
10581
10582 format %{ "FLD $mem1 ===MACRO1===\n\t"
10583 "FMUL ST,$src\n\t"
10584 "FSTP $dst" %}
10585 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10586 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10587 OpcReg_FPR(src),
10588 Pop_Reg_FPR(dst) );
10589 ins_pipe( fpu_reg_reg_mem );
10590 %}
10591 //
10592 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10593 // This instruction does not round to 24-bits
10594 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10595 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10596 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10597 ins_cost(95);
10598
10599 format %{ "FLD $mem1 ===MACRO2===\n\t"
10600 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10601 "FADD ST,$src2\n\t"
10602 "FSTP $dst" %}
10603 opcode(0xD9); /* LoadF D9 /0 */
10604 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10605 FMul_ST_reg(src1),
10606 FAdd_ST_reg(src2),
10607 Pop_Reg_FPR(dst) );
10608 ins_pipe( fpu_reg_mem_reg_reg );
10609 %}
10610
10611 // MACRO3 -- addFPR a mulFPR
10612 // This instruction does not round to 24-bits. It is a '2-address'
10613 // instruction in that the result goes back to src2. This eliminates
10614 // a move from the macro; possibly the register allocator will have
10615 // to add it back (and maybe not).
10616 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10617 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10618 match(Set src2 (AddF (MulF src0 src1) src2));
10619
10620 format %{ "FLD $src0 ===MACRO3===\n\t"
10621 "FMUL ST,$src1\n\t"
10622 "FADDP $src2,ST" %}
10623 opcode(0xD9); /* LoadF D9 /0 */
10624 ins_encode( Push_Reg_FPR(src0),
10625 FMul_ST_reg(src1),
10626 FAddP_reg_ST(src2) );
10627 ins_pipe( fpu_reg_reg_reg );
10628 %}
10629
10630 // MACRO4 -- divFPR subFPR
10631 // This instruction does not round to 24-bits
10632 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10633 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10634 match(Set dst (DivF (SubF src2 src1) src3));
10635
10636 format %{ "FLD $src2 ===MACRO4===\n\t"
10637 "FSUB ST,$src1\n\t"
10638 "FDIV ST,$src3\n\t"
10639 "FSTP $dst" %}
10640 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10641 ins_encode( Push_Reg_FPR(src2),
10642 subFPR_divFPR_encode(src1,src3),
10643 Pop_Reg_FPR(dst) );
10644 ins_pipe( fpu_reg_reg_reg_reg );
10645 %}
10646
10647 // Spill to obtain 24-bit precision
10648 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10649 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10650 match(Set dst (DivF src1 src2));
10651
10652 format %{ "FDIV $dst,$src1,$src2" %}
10653 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10654 ins_encode( Push_Reg_FPR(src1),
10655 OpcReg_FPR(src2),
10656 Pop_Mem_FPR(dst) );
10657 ins_pipe( fpu_mem_reg_reg );
10658 %}
10659 //
10660 // This instruction does not round to 24-bits
10661 instruct divFPR_reg(regFPR dst, regFPR src) %{
10662 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10663 match(Set dst (DivF dst src));
10664
10665 format %{ "FDIV $dst,$src" %}
10666 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10667 ins_encode( Push_Reg_FPR(src),
10668 OpcP, RegOpc(dst) );
10669 ins_pipe( fpu_reg_reg );
10670 %}
10671
10672
10673 // Spill to obtain 24-bit precision
10674 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10675 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10676 match(Set dst (ModF src1 src2));
10677 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10678
10679 format %{ "FMOD $dst,$src1,$src2" %}
10680 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10681 emitModDPR(),
10682 Push_Result_Mod_DPR(src2),
10683 Pop_Mem_FPR(dst));
10684 ins_pipe( pipe_slow );
10685 %}
10686 //
10687 // This instruction does not round to 24-bits
10688 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10689 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10690 match(Set dst (ModF dst src));
10691 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10692
10693 format %{ "FMOD $dst,$src" %}
10694 ins_encode(Push_Reg_Mod_DPR(dst, src),
10695 emitModDPR(),
10696 Push_Result_Mod_DPR(src),
10697 Pop_Reg_FPR(dst));
10698 ins_pipe( pipe_slow );
10699 %}
10700
10701 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10702 predicate(UseSSE>=1);
10703 match(Set dst (ModF src0 src1));
10704 effect(KILL rax, KILL cr);
10705 format %{ "SUB ESP,4\t # FMOD\n"
10706 "\tMOVSS [ESP+0],$src1\n"
10707 "\tFLD_S [ESP+0]\n"
10708 "\tMOVSS [ESP+0],$src0\n"
10709 "\tFLD_S [ESP+0]\n"
10710 "loop:\tFPREM\n"
10711 "\tFWAIT\n"
10712 "\tFNSTSW AX\n"
10713 "\tSAHF\n"
10714 "\tJP loop\n"
10715 "\tFSTP_S [ESP+0]\n"
10716 "\tMOVSS $dst,[ESP+0]\n"
10717 "\tADD ESP,4\n"
10718 "\tFSTP ST0\t # Restore FPU Stack"
10719 %}
10720 ins_cost(250);
10721 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10722 ins_pipe( pipe_slow );
10723 %}
10724
10725
10726 //----------Arithmetic Conversion Instructions---------------------------------
10727 // The conversions operations are all Alpha sorted. Please keep it that way!
10728
10729 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10730 predicate(UseSSE==0);
10731 match(Set dst (RoundFloat src));
10732 ins_cost(125);
10733 format %{ "FST_S $dst,$src\t# F-round" %}
10734 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10735 ins_pipe( fpu_mem_reg );
10736 %}
10737
10738 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10739 predicate(UseSSE<=1);
10740 match(Set dst (RoundDouble src));
10741 ins_cost(125);
10742 format %{ "FST_D $dst,$src\t# D-round" %}
10743 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10744 ins_pipe( fpu_mem_reg );
10745 %}
10746
10747 // Force rounding to 24-bit precision and 6-bit exponent
10748 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10749 predicate(UseSSE==0);
10750 match(Set dst (ConvD2F src));
10751 format %{ "FST_S $dst,$src\t# F-round" %}
10752 expand %{
10753 roundFloat_mem_reg(dst,src);
10754 %}
10755 %}
10756
10757 // Force rounding to 24-bit precision and 6-bit exponent
10758 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10759 predicate(UseSSE==1);
10760 match(Set dst (ConvD2F src));
10761 effect( KILL cr );
10762 format %{ "SUB ESP,4\n\t"
10763 "FST_S [ESP],$src\t# F-round\n\t"
10764 "MOVSS $dst,[ESP]\n\t"
10765 "ADD ESP,4" %}
10766 ins_encode %{
10767 __ subptr(rsp, 4);
10768 if ($src$$reg != FPR1L_enc) {
10769 __ fld_s($src$$reg-1);
10770 __ fstp_s(Address(rsp, 0));
10771 } else {
10772 __ fst_s(Address(rsp, 0));
10773 }
10774 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10775 __ addptr(rsp, 4);
10776 %}
10777 ins_pipe( pipe_slow );
10778 %}
10779
10780 // Force rounding double precision to single precision
10781 instruct convD2F_reg(regF dst, regD src) %{
10782 predicate(UseSSE>=2);
10783 match(Set dst (ConvD2F src));
10784 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10785 ins_encode %{
10786 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10787 %}
10788 ins_pipe( pipe_slow );
10789 %}
10790
10791 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10792 predicate(UseSSE==0);
10793 match(Set dst (ConvF2D src));
10794 format %{ "FST_S $dst,$src\t# D-round" %}
10795 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10796 ins_pipe( fpu_reg_reg );
10797 %}
10798
10799 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10800 predicate(UseSSE==1);
10801 match(Set dst (ConvF2D src));
10802 format %{ "FST_D $dst,$src\t# D-round" %}
10803 expand %{
10804 roundDouble_mem_reg(dst,src);
10805 %}
10806 %}
10807
10808 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10809 predicate(UseSSE==1);
10810 match(Set dst (ConvF2D src));
10811 effect( KILL cr );
10812 format %{ "SUB ESP,4\n\t"
10813 "MOVSS [ESP] $src\n\t"
10814 "FLD_S [ESP]\n\t"
10815 "ADD ESP,4\n\t"
10816 "FSTP $dst\t# D-round" %}
10817 ins_encode %{
10818 __ subptr(rsp, 4);
10819 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10820 __ fld_s(Address(rsp, 0));
10821 __ addptr(rsp, 4);
10822 __ fstp_d($dst$$reg);
10823 %}
10824 ins_pipe( pipe_slow );
10825 %}
10826
10827 instruct convF2D_reg(regD dst, regF src) %{
10828 predicate(UseSSE>=2);
10829 match(Set dst (ConvF2D src));
10830 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10831 ins_encode %{
10832 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10833 %}
10834 ins_pipe( pipe_slow );
10835 %}
10836
10837 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10838 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10839 predicate(UseSSE<=1);
10840 match(Set dst (ConvD2I src));
10841 effect( KILL tmp, KILL cr );
10842 format %{ "FLD $src\t# Convert double to int \n\t"
10843 "FLDCW trunc mode\n\t"
10844 "SUB ESP,4\n\t"
10845 "FISTp [ESP + #0]\n\t"
10846 "FLDCW std/24-bit mode\n\t"
10847 "POP EAX\n\t"
10848 "CMP EAX,0x80000000\n\t"
10849 "JNE,s fast\n\t"
10850 "FLD_D $src\n\t"
10851 "CALL d2i_wrapper\n"
10852 "fast:" %}
10853 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10854 ins_pipe( pipe_slow );
10855 %}
10856
10857 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10858 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10859 predicate(UseSSE>=2);
10860 match(Set dst (ConvD2I src));
10861 effect( KILL tmp, KILL cr );
10862 format %{ "CVTTSD2SI $dst, $src\n\t"
10863 "CMP $dst,0x80000000\n\t"
10864 "JNE,s fast\n\t"
10865 "SUB ESP, 8\n\t"
10866 "MOVSD [ESP], $src\n\t"
10867 "FLD_D [ESP]\n\t"
10868 "ADD ESP, 8\n\t"
10869 "CALL d2i_wrapper\n"
10870 "fast:" %}
10871 ins_encode %{
10872 Label fast;
10873 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10874 __ cmpl($dst$$Register, 0x80000000);
10875 __ jccb(Assembler::notEqual, fast);
10876 __ subptr(rsp, 8);
10877 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10878 __ fld_d(Address(rsp, 0));
10879 __ addptr(rsp, 8);
10880 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10881 __ bind(fast);
10882 %}
10883 ins_pipe( pipe_slow );
10884 %}
10885
10886 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10887 predicate(UseSSE<=1);
10888 match(Set dst (ConvD2L src));
10889 effect( KILL cr );
10890 format %{ "FLD $src\t# Convert double to long\n\t"
10891 "FLDCW trunc mode\n\t"
10892 "SUB ESP,8\n\t"
10893 "FISTp [ESP + #0]\n\t"
10894 "FLDCW std/24-bit mode\n\t"
10895 "POP EAX\n\t"
10896 "POP EDX\n\t"
10897 "CMP EDX,0x80000000\n\t"
10898 "JNE,s fast\n\t"
10899 "TEST EAX,EAX\n\t"
10900 "JNE,s fast\n\t"
10901 "FLD $src\n\t"
10902 "CALL d2l_wrapper\n"
10903 "fast:" %}
10904 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10905 ins_pipe( pipe_slow );
10906 %}
10907
10908 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10909 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10910 predicate (UseSSE>=2);
10911 match(Set dst (ConvD2L src));
10912 effect( KILL cr );
10913 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10914 "MOVSD [ESP],$src\n\t"
10915 "FLD_D [ESP]\n\t"
10916 "FLDCW trunc mode\n\t"
10917 "FISTp [ESP + #0]\n\t"
10918 "FLDCW std/24-bit mode\n\t"
10919 "POP EAX\n\t"
10920 "POP EDX\n\t"
10921 "CMP EDX,0x80000000\n\t"
10922 "JNE,s fast\n\t"
10923 "TEST EAX,EAX\n\t"
10924 "JNE,s fast\n\t"
10925 "SUB ESP,8\n\t"
10926 "MOVSD [ESP],$src\n\t"
10927 "FLD_D [ESP]\n\t"
10928 "ADD ESP,8\n\t"
10929 "CALL d2l_wrapper\n"
10930 "fast:" %}
10931 ins_encode %{
10932 Label fast;
10933 __ subptr(rsp, 8);
10934 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10935 __ fld_d(Address(rsp, 0));
10936 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10937 __ fistp_d(Address(rsp, 0));
10938 // Restore the rounding mode, mask the exception
10939 if (Compile::current()->in_24_bit_fp_mode()) {
10940 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10941 } else {
10942 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10943 }
10944 // Load the converted long, adjust CPU stack
10945 __ pop(rax);
10946 __ pop(rdx);
10947 __ cmpl(rdx, 0x80000000);
10948 __ jccb(Assembler::notEqual, fast);
10949 __ testl(rax, rax);
10950 __ jccb(Assembler::notEqual, fast);
10951 __ subptr(rsp, 8);
10952 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10953 __ fld_d(Address(rsp, 0));
10954 __ addptr(rsp, 8);
10955 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10956 __ bind(fast);
10957 %}
10958 ins_pipe( pipe_slow );
10959 %}
10960
10961 // Convert a double to an int. Java semantics require we do complex
10962 // manglations in the corner cases. So we set the rounding mode to
10963 // 'zero', store the darned double down as an int, and reset the
10964 // rounding mode to 'nearest'. The hardware stores a flag value down
10965 // if we would overflow or converted a NAN; we check for this and
10966 // and go the slow path if needed.
10967 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10968 predicate(UseSSE==0);
10969 match(Set dst (ConvF2I src));
10970 effect( KILL tmp, KILL cr );
10971 format %{ "FLD $src\t# Convert float to int \n\t"
10972 "FLDCW trunc mode\n\t"
10973 "SUB ESP,4\n\t"
10974 "FISTp [ESP + #0]\n\t"
10975 "FLDCW std/24-bit mode\n\t"
10976 "POP EAX\n\t"
10977 "CMP EAX,0x80000000\n\t"
10978 "JNE,s fast\n\t"
10979 "FLD $src\n\t"
10980 "CALL d2i_wrapper\n"
10981 "fast:" %}
10982 // DPR2I_encoding works for FPR2I
10983 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10984 ins_pipe( pipe_slow );
10985 %}
10986
10987 // Convert a float in xmm to an int reg.
10988 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10989 predicate(UseSSE>=1);
10990 match(Set dst (ConvF2I src));
10991 effect( KILL tmp, KILL cr );
10992 format %{ "CVTTSS2SI $dst, $src\n\t"
10993 "CMP $dst,0x80000000\n\t"
10994 "JNE,s fast\n\t"
10995 "SUB ESP, 4\n\t"
10996 "MOVSS [ESP], $src\n\t"
10997 "FLD [ESP]\n\t"
10998 "ADD ESP, 4\n\t"
10999 "CALL d2i_wrapper\n"
11000 "fast:" %}
11001 ins_encode %{
11002 Label fast;
11003 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11004 __ cmpl($dst$$Register, 0x80000000);
11005 __ jccb(Assembler::notEqual, fast);
11006 __ subptr(rsp, 4);
11007 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11008 __ fld_s(Address(rsp, 0));
11009 __ addptr(rsp, 4);
11010 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11011 __ bind(fast);
11012 %}
11013 ins_pipe( pipe_slow );
11014 %}
11015
11016 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11017 predicate(UseSSE==0);
11018 match(Set dst (ConvF2L src));
11019 effect( KILL cr );
11020 format %{ "FLD $src\t# Convert float to long\n\t"
11021 "FLDCW trunc mode\n\t"
11022 "SUB ESP,8\n\t"
11023 "FISTp [ESP + #0]\n\t"
11024 "FLDCW std/24-bit mode\n\t"
11025 "POP EAX\n\t"
11026 "POP EDX\n\t"
11027 "CMP EDX,0x80000000\n\t"
11028 "JNE,s fast\n\t"
11029 "TEST EAX,EAX\n\t"
11030 "JNE,s fast\n\t"
11031 "FLD $src\n\t"
11032 "CALL d2l_wrapper\n"
11033 "fast:" %}
11034 // DPR2L_encoding works for FPR2L
11035 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11036 ins_pipe( pipe_slow );
11037 %}
11038
11039 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11040 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11041 predicate (UseSSE>=1);
11042 match(Set dst (ConvF2L src));
11043 effect( KILL cr );
11044 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11045 "MOVSS [ESP],$src\n\t"
11046 "FLD_S [ESP]\n\t"
11047 "FLDCW trunc mode\n\t"
11048 "FISTp [ESP + #0]\n\t"
11049 "FLDCW std/24-bit mode\n\t"
11050 "POP EAX\n\t"
11051 "POP EDX\n\t"
11052 "CMP EDX,0x80000000\n\t"
11053 "JNE,s fast\n\t"
11054 "TEST EAX,EAX\n\t"
11055 "JNE,s fast\n\t"
11056 "SUB ESP,4\t# Convert float to long\n\t"
11057 "MOVSS [ESP],$src\n\t"
11058 "FLD_S [ESP]\n\t"
11059 "ADD ESP,4\n\t"
11060 "CALL d2l_wrapper\n"
11061 "fast:" %}
11062 ins_encode %{
11063 Label fast;
11064 __ subptr(rsp, 8);
11065 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11066 __ fld_s(Address(rsp, 0));
11067 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11068 __ fistp_d(Address(rsp, 0));
11069 // Restore the rounding mode, mask the exception
11070 if (Compile::current()->in_24_bit_fp_mode()) {
11071 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11072 } else {
11073 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11074 }
11075 // Load the converted long, adjust CPU stack
11076 __ pop(rax);
11077 __ pop(rdx);
11078 __ cmpl(rdx, 0x80000000);
11079 __ jccb(Assembler::notEqual, fast);
11080 __ testl(rax, rax);
11081 __ jccb(Assembler::notEqual, fast);
11082 __ subptr(rsp, 4);
11083 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11084 __ fld_s(Address(rsp, 0));
11085 __ addptr(rsp, 4);
11086 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11087 __ bind(fast);
11088 %}
11089 ins_pipe( pipe_slow );
11090 %}
11091
11092 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11093 predicate( UseSSE<=1 );
11094 match(Set dst (ConvI2D src));
11095 format %{ "FILD $src\n\t"
11096 "FSTP $dst" %}
11097 opcode(0xDB, 0x0); /* DB /0 */
11098 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11099 ins_pipe( fpu_reg_mem );
11100 %}
11101
11102 instruct convI2D_reg(regD dst, rRegI src) %{
11103 predicate( UseSSE>=2 && !UseXmmI2D );
11104 match(Set dst (ConvI2D src));
11105 format %{ "CVTSI2SD $dst,$src" %}
11106 ins_encode %{
11107 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11108 %}
11109 ins_pipe( pipe_slow );
11110 %}
11111
11112 instruct convI2D_mem(regD dst, memory mem) %{
11113 predicate( UseSSE>=2 );
11114 match(Set dst (ConvI2D (LoadI mem)));
11115 format %{ "CVTSI2SD $dst,$mem" %}
11116 ins_encode %{
11117 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11118 %}
11119 ins_pipe( pipe_slow );
11120 %}
11121
11122 instruct convXI2D_reg(regD dst, rRegI src)
11123 %{
11124 predicate( UseSSE>=2 && UseXmmI2D );
11125 match(Set dst (ConvI2D src));
11126
11127 format %{ "MOVD $dst,$src\n\t"
11128 "CVTDQ2PD $dst,$dst\t# i2d" %}
11129 ins_encode %{
11130 __ movdl($dst$$XMMRegister, $src$$Register);
11131 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11132 %}
11133 ins_pipe(pipe_slow); // XXX
11134 %}
11135
11136 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11137 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11138 match(Set dst (ConvI2D (LoadI mem)));
11139 format %{ "FILD $mem\n\t"
11140 "FSTP $dst" %}
11141 opcode(0xDB); /* DB /0 */
11142 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11143 Pop_Reg_DPR(dst));
11144 ins_pipe( fpu_reg_mem );
11145 %}
11146
11147 // Convert a byte to a float; no rounding step needed.
11148 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11149 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11150 match(Set dst (ConvI2F src));
11151 format %{ "FILD $src\n\t"
11152 "FSTP $dst" %}
11153
11154 opcode(0xDB, 0x0); /* DB /0 */
11155 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11156 ins_pipe( fpu_reg_mem );
11157 %}
11158
11159 // In 24-bit mode, force exponent rounding by storing back out
11160 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11161 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11162 match(Set dst (ConvI2F src));
11163 ins_cost(200);
11164 format %{ "FILD $src\n\t"
11165 "FSTP_S $dst" %}
11166 opcode(0xDB, 0x0); /* DB /0 */
11167 ins_encode( Push_Mem_I(src),
11168 Pop_Mem_FPR(dst));
11169 ins_pipe( fpu_mem_mem );
11170 %}
11171
11172 // In 24-bit mode, force exponent rounding by storing back out
11173 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11174 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11175 match(Set dst (ConvI2F (LoadI mem)));
11176 ins_cost(200);
11177 format %{ "FILD $mem\n\t"
11178 "FSTP_S $dst" %}
11179 opcode(0xDB); /* DB /0 */
11180 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11181 Pop_Mem_FPR(dst));
11182 ins_pipe( fpu_mem_mem );
11183 %}
11184
11185 // This instruction does not round to 24-bits
11186 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11187 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11188 match(Set dst (ConvI2F src));
11189 format %{ "FILD $src\n\t"
11190 "FSTP $dst" %}
11191 opcode(0xDB, 0x0); /* DB /0 */
11192 ins_encode( Push_Mem_I(src),
11193 Pop_Reg_FPR(dst));
11194 ins_pipe( fpu_reg_mem );
11195 %}
11196
11197 // This instruction does not round to 24-bits
11198 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11199 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11200 match(Set dst (ConvI2F (LoadI mem)));
11201 format %{ "FILD $mem\n\t"
11202 "FSTP $dst" %}
11203 opcode(0xDB); /* DB /0 */
11204 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11205 Pop_Reg_FPR(dst));
11206 ins_pipe( fpu_reg_mem );
11207 %}
11208
11209 // Convert an int to a float in xmm; no rounding step needed.
11210 instruct convI2F_reg(regF dst, rRegI src) %{
11211 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11212 match(Set dst (ConvI2F src));
11213 format %{ "CVTSI2SS $dst, $src" %}
11214 ins_encode %{
11215 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11216 %}
11217 ins_pipe( pipe_slow );
11218 %}
11219
11220 instruct convXI2F_reg(regF dst, rRegI src)
11221 %{
11222 predicate( UseSSE>=2 && UseXmmI2F );
11223 match(Set dst (ConvI2F src));
11224
11225 format %{ "MOVD $dst,$src\n\t"
11226 "CVTDQ2PS $dst,$dst\t# i2f" %}
11227 ins_encode %{
11228 __ movdl($dst$$XMMRegister, $src$$Register);
11229 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11230 %}
11231 ins_pipe(pipe_slow); // XXX
11232 %}
11233
11234 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11235 match(Set dst (ConvI2L src));
11236 effect(KILL cr);
11237 ins_cost(375);
11238 format %{ "MOV $dst.lo,$src\n\t"
11239 "MOV $dst.hi,$src\n\t"
11240 "SAR $dst.hi,31" %}
11241 ins_encode(convert_int_long(dst,src));
11242 ins_pipe( ialu_reg_reg_long );
11243 %}
11244
11245 // Zero-extend convert int to long
11246 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11247 match(Set dst (AndL (ConvI2L src) mask) );
11248 effect( KILL flags );
11249 ins_cost(250);
11250 format %{ "MOV $dst.lo,$src\n\t"
11251 "XOR $dst.hi,$dst.hi" %}
11252 opcode(0x33); // XOR
11253 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11254 ins_pipe( ialu_reg_reg_long );
11255 %}
11256
11257 // Zero-extend long
11258 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11259 match(Set dst (AndL src mask) );
11260 effect( KILL flags );
11261 ins_cost(250);
11262 format %{ "MOV $dst.lo,$src.lo\n\t"
11263 "XOR $dst.hi,$dst.hi\n\t" %}
11264 opcode(0x33); // XOR
11265 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11266 ins_pipe( ialu_reg_reg_long );
11267 %}
11268
11269 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11270 predicate (UseSSE<=1);
11271 match(Set dst (ConvL2D src));
11272 effect( KILL cr );
11273 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11274 "PUSH $src.lo\n\t"
11275 "FILD ST,[ESP + #0]\n\t"
11276 "ADD ESP,8\n\t"
11277 "FSTP_D $dst\t# D-round" %}
11278 opcode(0xDF, 0x5); /* DF /5 */
11279 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11280 ins_pipe( pipe_slow );
11281 %}
11282
11283 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11284 predicate (UseSSE>=2);
11285 match(Set dst (ConvL2D src));
11286 effect( KILL cr );
11287 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11288 "PUSH $src.lo\n\t"
11289 "FILD_D [ESP]\n\t"
11290 "FSTP_D [ESP]\n\t"
11291 "MOVSD $dst,[ESP]\n\t"
11292 "ADD ESP,8" %}
11293 opcode(0xDF, 0x5); /* DF /5 */
11294 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11295 ins_pipe( pipe_slow );
11296 %}
11297
11298 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11299 predicate (UseSSE>=1);
11300 match(Set dst (ConvL2F src));
11301 effect( KILL cr );
11302 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11303 "PUSH $src.lo\n\t"
11304 "FILD_D [ESP]\n\t"
11305 "FSTP_S [ESP]\n\t"
11306 "MOVSS $dst,[ESP]\n\t"
11307 "ADD ESP,8" %}
11308 opcode(0xDF, 0x5); /* DF /5 */
11309 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11310 ins_pipe( pipe_slow );
11311 %}
11312
11313 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11314 match(Set dst (ConvL2F src));
11315 effect( KILL cr );
11316 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11317 "PUSH $src.lo\n\t"
11318 "FILD ST,[ESP + #0]\n\t"
11319 "ADD ESP,8\n\t"
11320 "FSTP_S $dst\t# F-round" %}
11321 opcode(0xDF, 0x5); /* DF /5 */
11322 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11323 ins_pipe( pipe_slow );
11324 %}
11325
11326 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11327 match(Set dst (ConvL2I src));
11328 effect( DEF dst, USE src );
11329 format %{ "MOV $dst,$src.lo" %}
11330 ins_encode(enc_CopyL_Lo(dst,src));
11331 ins_pipe( ialu_reg_reg );
11332 %}
11333
11334
11335 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11336 match(Set dst (MoveF2I src));
11337 effect( DEF dst, USE src );
11338 ins_cost(100);
11339 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11340 ins_encode %{
11341 __ movl($dst$$Register, Address(rsp, $src$$disp));
11342 %}
11343 ins_pipe( ialu_reg_mem );
11344 %}
11345
11346 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11347 predicate(UseSSE==0);
11348 match(Set dst (MoveF2I src));
11349 effect( DEF dst, USE src );
11350
11351 ins_cost(125);
11352 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11353 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11354 ins_pipe( fpu_mem_reg );
11355 %}
11356
11357 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11358 predicate(UseSSE>=1);
11359 match(Set dst (MoveF2I src));
11360 effect( DEF dst, USE src );
11361
11362 ins_cost(95);
11363 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11364 ins_encode %{
11365 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11366 %}
11367 ins_pipe( pipe_slow );
11368 %}
11369
11370 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11371 predicate(UseSSE>=2);
11372 match(Set dst (MoveF2I src));
11373 effect( DEF dst, USE src );
11374 ins_cost(85);
11375 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11376 ins_encode %{
11377 __ movdl($dst$$Register, $src$$XMMRegister);
11378 %}
11379 ins_pipe( pipe_slow );
11380 %}
11381
11382 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11383 match(Set dst (MoveI2F src));
11384 effect( DEF dst, USE src );
11385
11386 ins_cost(100);
11387 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11388 ins_encode %{
11389 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11390 %}
11391 ins_pipe( ialu_mem_reg );
11392 %}
11393
11394
11395 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11396 predicate(UseSSE==0);
11397 match(Set dst (MoveI2F src));
11398 effect(DEF dst, USE src);
11399
11400 ins_cost(125);
11401 format %{ "FLD_S $src\n\t"
11402 "FSTP $dst\t# MoveI2F_stack_reg" %}
11403 opcode(0xD9); /* D9 /0, FLD m32real */
11404 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11405 Pop_Reg_FPR(dst) );
11406 ins_pipe( fpu_reg_mem );
11407 %}
11408
11409 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11410 predicate(UseSSE>=1);
11411 match(Set dst (MoveI2F src));
11412 effect( DEF dst, USE src );
11413
11414 ins_cost(95);
11415 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11416 ins_encode %{
11417 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11418 %}
11419 ins_pipe( pipe_slow );
11420 %}
11421
11422 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11423 predicate(UseSSE>=2);
11424 match(Set dst (MoveI2F src));
11425 effect( DEF dst, USE src );
11426
11427 ins_cost(85);
11428 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11429 ins_encode %{
11430 __ movdl($dst$$XMMRegister, $src$$Register);
11431 %}
11432 ins_pipe( pipe_slow );
11433 %}
11434
11435 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11436 match(Set dst (MoveD2L src));
11437 effect(DEF dst, USE src);
11438
11439 ins_cost(250);
11440 format %{ "MOV $dst.lo,$src\n\t"
11441 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11442 opcode(0x8B, 0x8B);
11443 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11444 ins_pipe( ialu_mem_long_reg );
11445 %}
11446
11447 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11448 predicate(UseSSE<=1);
11449 match(Set dst (MoveD2L src));
11450 effect(DEF dst, USE src);
11451
11452 ins_cost(125);
11453 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11454 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11455 ins_pipe( fpu_mem_reg );
11456 %}
11457
11458 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11459 predicate(UseSSE>=2);
11460 match(Set dst (MoveD2L src));
11461 effect(DEF dst, USE src);
11462 ins_cost(95);
11463 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11464 ins_encode %{
11465 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11466 %}
11467 ins_pipe( pipe_slow );
11468 %}
11469
11470 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11471 predicate(UseSSE>=2);
11472 match(Set dst (MoveD2L src));
11473 effect(DEF dst, USE src, TEMP tmp);
11474 ins_cost(85);
11475 format %{ "MOVD $dst.lo,$src\n\t"
11476 "PSHUFLW $tmp,$src,0x4E\n\t"
11477 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11478 ins_encode %{
11479 __ movdl($dst$$Register, $src$$XMMRegister);
11480 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11481 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11482 %}
11483 ins_pipe( pipe_slow );
11484 %}
11485
11486 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11487 match(Set dst (MoveL2D src));
11488 effect(DEF dst, USE src);
11489
11490 ins_cost(200);
11491 format %{ "MOV $dst,$src.lo\n\t"
11492 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11493 opcode(0x89, 0x89);
11494 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11495 ins_pipe( ialu_mem_long_reg );
11496 %}
11497
11498
11499 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11500 predicate(UseSSE<=1);
11501 match(Set dst (MoveL2D src));
11502 effect(DEF dst, USE src);
11503 ins_cost(125);
11504
11505 format %{ "FLD_D $src\n\t"
11506 "FSTP $dst\t# MoveL2D_stack_reg" %}
11507 opcode(0xDD); /* DD /0, FLD m64real */
11508 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11509 Pop_Reg_DPR(dst) );
11510 ins_pipe( fpu_reg_mem );
11511 %}
11512
11513
11514 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11515 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11516 match(Set dst (MoveL2D src));
11517 effect(DEF dst, USE src);
11518
11519 ins_cost(95);
11520 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11521 ins_encode %{
11522 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11523 %}
11524 ins_pipe( pipe_slow );
11525 %}
11526
11527 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11528 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11529 match(Set dst (MoveL2D src));
11530 effect(DEF dst, USE src);
11531
11532 ins_cost(95);
11533 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11534 ins_encode %{
11535 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11536 %}
11537 ins_pipe( pipe_slow );
11538 %}
11539
11540 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11541 predicate(UseSSE>=2);
11542 match(Set dst (MoveL2D src));
11543 effect(TEMP dst, USE src, TEMP tmp);
11544 ins_cost(85);
11545 format %{ "MOVD $dst,$src.lo\n\t"
11546 "MOVD $tmp,$src.hi\n\t"
11547 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11548 ins_encode %{
11549 __ movdl($dst$$XMMRegister, $src$$Register);
11550 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11551 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11552 %}
11553 ins_pipe( pipe_slow );
11554 %}
11555
11556
11557 // =======================================================================
11558 // fast clearing of an array
11559 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11560 predicate(!UseFastStosb);
11561 match(Set dummy (ClearArray cnt base));
11562 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11563 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11564 "SHL ECX,1\t# Convert doublewords to words\n\t"
11565 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11566 ins_encode %{
11567 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11568 %}
11569 ins_pipe( pipe_slow );
11570 %}
11571
11572 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11573 predicate(UseFastStosb);
11574 match(Set dummy (ClearArray cnt base));
11575 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11576 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11577 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11578 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11579 ins_encode %{
11580 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11581 %}
11582 ins_pipe( pipe_slow );
11583 %}
11584
11585 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11586 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11587 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11588 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11589
11590 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11591 ins_encode %{
11592 __ string_compare($str1$$Register, $str2$$Register,
11593 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11594 $tmp1$$XMMRegister);
11595 %}
11596 ins_pipe( pipe_slow );
11597 %}
11598
11599 // fast string equals
11600 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11601 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11602 match(Set result (StrEquals (Binary str1 str2) cnt));
11603 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11604
11605 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11606 ins_encode %{
11607 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11608 $cnt$$Register, $result$$Register, $tmp3$$Register,
11609 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11610 %}
11611 ins_pipe( pipe_slow );
11612 %}
11613
11614 // fast search of substring with known size.
11615 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11616 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11617 predicate(UseSSE42Intrinsics);
11618 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11619 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11620
11621 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11622 ins_encode %{
11623 int icnt2 = (int)$int_cnt2$$constant;
11624 if (icnt2 >= 8) {
11625 // IndexOf for constant substrings with size >= 8 elements
11626 // which don't need to be loaded through stack.
11627 __ string_indexofC8($str1$$Register, $str2$$Register,
11628 $cnt1$$Register, $cnt2$$Register,
11629 icnt2, $result$$Register,
11630 $vec$$XMMRegister, $tmp$$Register);
11631 } else {
11632 // Small strings are loaded through stack if they cross page boundary.
11633 __ string_indexof($str1$$Register, $str2$$Register,
11634 $cnt1$$Register, $cnt2$$Register,
11635 icnt2, $result$$Register,
11636 $vec$$XMMRegister, $tmp$$Register);
11637 }
11638 %}
11639 ins_pipe( pipe_slow );
11640 %}
11641
11642 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11643 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11644 predicate(UseSSE42Intrinsics);
11645 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11646 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11647
11648 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11649 ins_encode %{
11650 __ string_indexof($str1$$Register, $str2$$Register,
11651 $cnt1$$Register, $cnt2$$Register,
11652 (-1), $result$$Register,
11653 $vec$$XMMRegister, $tmp$$Register);
11654 %}
11655 ins_pipe( pipe_slow );
11656 %}
11657
11658 // fast array equals
11659 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11660 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11661 %{
11662 match(Set result (AryEq ary1 ary2));
11663 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11664 //ins_cost(300);
11665
11666 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11667 ins_encode %{
11668 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11669 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11670 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11671 %}
11672 ins_pipe( pipe_slow );
11673 %}
11674
11675 // encode char[] to byte[] in ISO_8859_1
11676 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11677 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11678 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11679 match(Set result (EncodeISOArray src (Binary dst len)));
11680 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11681
11682 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11683 ins_encode %{
11684 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11685 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11686 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11687 %}
11688 ins_pipe( pipe_slow );
11689 %}
11690
11691
11692 //----------Control Flow Instructions------------------------------------------
11693 // Signed compare Instructions
11694 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11695 match(Set cr (CmpI op1 op2));
11696 effect( DEF cr, USE op1, USE op2 );
11697 format %{ "CMP $op1,$op2" %}
11698 opcode(0x3B); /* Opcode 3B /r */
11699 ins_encode( OpcP, RegReg( op1, op2) );
11700 ins_pipe( ialu_cr_reg_reg );
11701 %}
11702
11703 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11704 match(Set cr (CmpI op1 op2));
11705 effect( DEF cr, USE op1 );
11706 format %{ "CMP $op1,$op2" %}
11707 opcode(0x81,0x07); /* Opcode 81 /7 */
11708 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11709 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11710 ins_pipe( ialu_cr_reg_imm );
11711 %}
11712
11713 // Cisc-spilled version of cmpI_eReg
11714 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11715 match(Set cr (CmpI op1 (LoadI op2)));
11716
11717 format %{ "CMP $op1,$op2" %}
11718 ins_cost(500);
11719 opcode(0x3B); /* Opcode 3B /r */
11720 ins_encode( OpcP, RegMem( op1, op2) );
11721 ins_pipe( ialu_cr_reg_mem );
11722 %}
11723
11724 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11725 match(Set cr (CmpI src zero));
11726 effect( DEF cr, USE src );
11727
11728 format %{ "TEST $src,$src" %}
11729 opcode(0x85);
11730 ins_encode( OpcP, RegReg( src, src ) );
11731 ins_pipe( ialu_cr_reg_imm );
11732 %}
11733
11734 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11735 match(Set cr (CmpI (AndI src con) zero));
11736
11737 format %{ "TEST $src,$con" %}
11738 opcode(0xF7,0x00);
11739 ins_encode( OpcP, RegOpc(src), Con32(con) );
11740 ins_pipe( ialu_cr_reg_imm );
11741 %}
11742
11743 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11744 match(Set cr (CmpI (AndI src mem) zero));
11745
11746 format %{ "TEST $src,$mem" %}
11747 opcode(0x85);
11748 ins_encode( OpcP, RegMem( src, mem ) );
11749 ins_pipe( ialu_cr_reg_mem );
11750 %}
11751
11752 // Unsigned compare Instructions; really, same as signed except they
11753 // produce an eFlagsRegU instead of eFlagsReg.
11754 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11755 match(Set cr (CmpU op1 op2));
11756
11757 format %{ "CMPu $op1,$op2" %}
11758 opcode(0x3B); /* Opcode 3B /r */
11759 ins_encode( OpcP, RegReg( op1, op2) );
11760 ins_pipe( ialu_cr_reg_reg );
11761 %}
11762
11763 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11764 match(Set cr (CmpU op1 op2));
11765
11766 format %{ "CMPu $op1,$op2" %}
11767 opcode(0x81,0x07); /* Opcode 81 /7 */
11768 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11769 ins_pipe( ialu_cr_reg_imm );
11770 %}
11771
11772 // // Cisc-spilled version of cmpU_eReg
11773 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11774 match(Set cr (CmpU op1 (LoadI op2)));
11775
11776 format %{ "CMPu $op1,$op2" %}
11777 ins_cost(500);
11778 opcode(0x3B); /* Opcode 3B /r */
11779 ins_encode( OpcP, RegMem( op1, op2) );
11780 ins_pipe( ialu_cr_reg_mem );
11781 %}
11782
11783 // // Cisc-spilled version of cmpU_eReg
11784 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11785 // match(Set cr (CmpU (LoadI op1) op2));
11786 //
11787 // format %{ "CMPu $op1,$op2" %}
11788 // ins_cost(500);
11789 // opcode(0x39); /* Opcode 39 /r */
11790 // ins_encode( OpcP, RegMem( op1, op2) );
11791 //%}
11792
11793 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11794 match(Set cr (CmpU src zero));
11795
11796 format %{ "TESTu $src,$src" %}
11797 opcode(0x85);
11798 ins_encode( OpcP, RegReg( src, src ) );
11799 ins_pipe( ialu_cr_reg_imm );
11800 %}
11801
11802 // Unsigned pointer compare Instructions
11803 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11804 match(Set cr (CmpP op1 op2));
11805
11806 format %{ "CMPu $op1,$op2" %}
11807 opcode(0x3B); /* Opcode 3B /r */
11808 ins_encode( OpcP, RegReg( op1, op2) );
11809 ins_pipe( ialu_cr_reg_reg );
11810 %}
11811
11812 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11813 match(Set cr (CmpP op1 op2));
11814
11815 format %{ "CMPu $op1,$op2" %}
11816 opcode(0x81,0x07); /* Opcode 81 /7 */
11817 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11818 ins_pipe( ialu_cr_reg_imm );
11819 %}
11820
11821 // // Cisc-spilled version of cmpP_eReg
11822 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11823 match(Set cr (CmpP op1 (LoadP op2)));
11824
11825 format %{ "CMPu $op1,$op2" %}
11826 ins_cost(500);
11827 opcode(0x3B); /* Opcode 3B /r */
11828 ins_encode( OpcP, RegMem( op1, op2) );
11829 ins_pipe( ialu_cr_reg_mem );
11830 %}
11831
11832 // // Cisc-spilled version of cmpP_eReg
11833 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11834 // match(Set cr (CmpP (LoadP op1) op2));
11835 //
11836 // format %{ "CMPu $op1,$op2" %}
11837 // ins_cost(500);
11838 // opcode(0x39); /* Opcode 39 /r */
11839 // ins_encode( OpcP, RegMem( op1, op2) );
11840 //%}
11841
11842 // Compare raw pointer (used in out-of-heap check).
11843 // Only works because non-oop pointers must be raw pointers
11844 // and raw pointers have no anti-dependencies.
11845 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11846 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11847 match(Set cr (CmpP op1 (LoadP op2)));
11848
11849 format %{ "CMPu $op1,$op2" %}
11850 opcode(0x3B); /* Opcode 3B /r */
11851 ins_encode( OpcP, RegMem( op1, op2) );
11852 ins_pipe( ialu_cr_reg_mem );
11853 %}
11854
11855 //
11856 // This will generate a signed flags result. This should be ok
11857 // since any compare to a zero should be eq/neq.
11858 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11859 match(Set cr (CmpP src zero));
11860
11861 format %{ "TEST $src,$src" %}
11862 opcode(0x85);
11863 ins_encode( OpcP, RegReg( src, src ) );
11864 ins_pipe( ialu_cr_reg_imm );
11865 %}
11866
11867 // Cisc-spilled version of testP_reg
11868 // This will generate a signed flags result. This should be ok
11869 // since any compare to a zero should be eq/neq.
11870 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11871 match(Set cr (CmpP (LoadP op) zero));
11872
11873 format %{ "TEST $op,0xFFFFFFFF" %}
11874 ins_cost(500);
11875 opcode(0xF7); /* Opcode F7 /0 */
11876 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11877 ins_pipe( ialu_cr_reg_imm );
11878 %}
11879
11880 // Yanked all unsigned pointer compare operations.
11881 // Pointer compares are done with CmpP which is already unsigned.
11882
11883 //----------Max and Min--------------------------------------------------------
11884 // Min Instructions
11885 ////
11886 // *** Min and Max using the conditional move are slower than the
11887 // *** branch version on a Pentium III.
11888 // // Conditional move for min
11889 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11890 // effect( USE_DEF op2, USE op1, USE cr );
11891 // format %{ "CMOVlt $op2,$op1\t! min" %}
11892 // opcode(0x4C,0x0F);
11893 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11894 // ins_pipe( pipe_cmov_reg );
11895 //%}
11896 //
11897 //// Min Register with Register (P6 version)
11898 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11899 // predicate(VM_Version::supports_cmov() );
11900 // match(Set op2 (MinI op1 op2));
11901 // ins_cost(200);
11902 // expand %{
11903 // eFlagsReg cr;
11904 // compI_eReg(cr,op1,op2);
11905 // cmovI_reg_lt(op2,op1,cr);
11906 // %}
11907 //%}
11908
11909 // Min Register with Register (generic version)
11910 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11911 match(Set dst (MinI dst src));
11912 effect(KILL flags);
11913 ins_cost(300);
11914
11915 format %{ "MIN $dst,$src" %}
11916 opcode(0xCC);
11917 ins_encode( min_enc(dst,src) );
11918 ins_pipe( pipe_slow );
11919 %}
11920
11921 // Max Register with Register
11922 // *** Min and Max using the conditional move are slower than the
11923 // *** branch version on a Pentium III.
11924 // // Conditional move for max
11925 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11926 // effect( USE_DEF op2, USE op1, USE cr );
11927 // format %{ "CMOVgt $op2,$op1\t! max" %}
11928 // opcode(0x4F,0x0F);
11929 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11930 // ins_pipe( pipe_cmov_reg );
11931 //%}
11932 //
11933 // // Max Register with Register (P6 version)
11934 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11935 // predicate(VM_Version::supports_cmov() );
11936 // match(Set op2 (MaxI op1 op2));
11937 // ins_cost(200);
11938 // expand %{
11939 // eFlagsReg cr;
11940 // compI_eReg(cr,op1,op2);
11941 // cmovI_reg_gt(op2,op1,cr);
11942 // %}
11943 //%}
11944
11945 // Max Register with Register (generic version)
11946 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11947 match(Set dst (MaxI dst src));
11948 effect(KILL flags);
11949 ins_cost(300);
11950
11951 format %{ "MAX $dst,$src" %}
11952 opcode(0xCC);
11953 ins_encode( max_enc(dst,src) );
11954 ins_pipe( pipe_slow );
11955 %}
11956
11957 // ============================================================================
11958 // Counted Loop limit node which represents exact final iterator value.
11959 // Note: the resulting value should fit into integer range since
11960 // counted loops have limit check on overflow.
11961 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11962 match(Set limit (LoopLimit (Binary init limit) stride));
11963 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11964 ins_cost(300);
11965
11966 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11967 ins_encode %{
11968 int strd = (int)$stride$$constant;
11969 assert(strd != 1 && strd != -1, "sanity");
11970 int m1 = (strd > 0) ? 1 : -1;
11971 // Convert limit to long (EAX:EDX)
11972 __ cdql();
11973 // Convert init to long (init:tmp)
11974 __ movl($tmp$$Register, $init$$Register);
11975 __ sarl($tmp$$Register, 31);
11976 // $limit - $init
11977 __ subl($limit$$Register, $init$$Register);
11978 __ sbbl($limit_hi$$Register, $tmp$$Register);
11979 // + ($stride - 1)
11980 if (strd > 0) {
11981 __ addl($limit$$Register, (strd - 1));
11982 __ adcl($limit_hi$$Register, 0);
11983 __ movl($tmp$$Register, strd);
11984 } else {
11985 __ addl($limit$$Register, (strd + 1));
11986 __ adcl($limit_hi$$Register, -1);
11987 __ lneg($limit_hi$$Register, $limit$$Register);
11988 __ movl($tmp$$Register, -strd);
11989 }
11990 // signed devision: (EAX:EDX) / pos_stride
11991 __ idivl($tmp$$Register);
11992 if (strd < 0) {
11993 // restore sign
11994 __ negl($tmp$$Register);
11995 }
11996 // (EAX) * stride
11997 __ mull($tmp$$Register);
11998 // + init (ignore upper bits)
11999 __ addl($limit$$Register, $init$$Register);
12000 %}
12001 ins_pipe( pipe_slow );
12002 %}
12003
12004 // ============================================================================
12005 // Branch Instructions
12006 // Jump Table
12007 instruct jumpXtnd(rRegI switch_val) %{
12008 match(Jump switch_val);
12009 ins_cost(350);
12010 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12011 ins_encode %{
12012 // Jump to Address(table_base + switch_reg)
12013 Address index(noreg, $switch_val$$Register, Address::times_1);
12014 __ jump(ArrayAddress($constantaddress, index));
12015 %}
12016 ins_pipe(pipe_jmp);
12017 %}
12018
12019 // Jump Direct - Label defines a relative address from JMP+1
12020 instruct jmpDir(label labl) %{
12021 match(Goto);
12022 effect(USE labl);
12023
12024 ins_cost(300);
12025 format %{ "JMP $labl" %}
12026 size(5);
12027 ins_encode %{
12028 Label* L = $labl$$label;
12029 __ jmp(*L, false); // Always long jump
12030 %}
12031 ins_pipe( pipe_jmp );
12032 %}
12033
12034 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12035 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12036 match(If cop cr);
12037 effect(USE labl);
12038
12039 ins_cost(300);
12040 format %{ "J$cop $labl" %}
12041 size(6);
12042 ins_encode %{
12043 Label* L = $labl$$label;
12044 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12045 %}
12046 ins_pipe( pipe_jcc );
12047 %}
12048
12049 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12050 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12051 match(CountedLoopEnd cop cr);
12052 effect(USE labl);
12053
12054 ins_cost(300);
12055 format %{ "J$cop $labl\t# Loop end" %}
12056 size(6);
12057 ins_encode %{
12058 Label* L = $labl$$label;
12059 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12060 %}
12061 ins_pipe( pipe_jcc );
12062 %}
12063
12064 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12065 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12066 match(CountedLoopEnd cop cmp);
12067 effect(USE labl);
12068
12069 ins_cost(300);
12070 format %{ "J$cop,u $labl\t# Loop end" %}
12071 size(6);
12072 ins_encode %{
12073 Label* L = $labl$$label;
12074 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12075 %}
12076 ins_pipe( pipe_jcc );
12077 %}
12078
12079 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12080 match(CountedLoopEnd cop cmp);
12081 effect(USE labl);
12082
12083 ins_cost(200);
12084 format %{ "J$cop,u $labl\t# Loop end" %}
12085 size(6);
12086 ins_encode %{
12087 Label* L = $labl$$label;
12088 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12089 %}
12090 ins_pipe( pipe_jcc );
12091 %}
12092
12093 // Jump Direct Conditional - using unsigned comparison
12094 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12095 match(If cop cmp);
12096 effect(USE labl);
12097
12098 ins_cost(300);
12099 format %{ "J$cop,u $labl" %}
12100 size(6);
12101 ins_encode %{
12102 Label* L = $labl$$label;
12103 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12104 %}
12105 ins_pipe(pipe_jcc);
12106 %}
12107
12108 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12109 match(If cop cmp);
12110 effect(USE labl);
12111
12112 ins_cost(200);
12113 format %{ "J$cop,u $labl" %}
12114 size(6);
12115 ins_encode %{
12116 Label* L = $labl$$label;
12117 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12118 %}
12119 ins_pipe(pipe_jcc);
12120 %}
12121
12122 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12123 match(If cop cmp);
12124 effect(USE labl);
12125
12126 ins_cost(200);
12127 format %{ $$template
12128 if ($cop$$cmpcode == Assembler::notEqual) {
12129 $$emit$$"JP,u $labl\n\t"
12130 $$emit$$"J$cop,u $labl"
12131 } else {
12132 $$emit$$"JP,u done\n\t"
12133 $$emit$$"J$cop,u $labl\n\t"
12134 $$emit$$"done:"
12135 }
12136 %}
12137 ins_encode %{
12138 Label* l = $labl$$label;
12139 if ($cop$$cmpcode == Assembler::notEqual) {
12140 __ jcc(Assembler::parity, *l, false);
12141 __ jcc(Assembler::notEqual, *l, false);
12142 } else if ($cop$$cmpcode == Assembler::equal) {
12143 Label done;
12144 __ jccb(Assembler::parity, done);
12145 __ jcc(Assembler::equal, *l, false);
12146 __ bind(done);
12147 } else {
12148 ShouldNotReachHere();
12149 }
12150 %}
12151 ins_pipe(pipe_jcc);
12152 %}
12153
12154 // ============================================================================
12155 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12156 // array for an instance of the superklass. Set a hidden internal cache on a
12157 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12158 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12159 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12160 match(Set result (PartialSubtypeCheck sub super));
12161 effect( KILL rcx, KILL cr );
12162
12163 ins_cost(1100); // slightly larger than the next version
12164 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12165 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12166 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12167 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12168 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12169 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12170 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12171 "miss:\t" %}
12172
12173 opcode(0x1); // Force a XOR of EDI
12174 ins_encode( enc_PartialSubtypeCheck() );
12175 ins_pipe( pipe_slow );
12176 %}
12177
12178 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12179 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12180 effect( KILL rcx, KILL result );
12181
12182 ins_cost(1000);
12183 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12184 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12185 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12186 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12187 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12188 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12189 "miss:\t" %}
12190
12191 opcode(0x0); // No need to XOR EDI
12192 ins_encode( enc_PartialSubtypeCheck() );
12193 ins_pipe( pipe_slow );
12194 %}
12195
12196 // ============================================================================
12197 // Branch Instructions -- short offset versions
12198 //
12199 // These instructions are used to replace jumps of a long offset (the default
12200 // match) with jumps of a shorter offset. These instructions are all tagged
12201 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12202 // match rules in general matching. Instead, the ADLC generates a conversion
12203 // method in the MachNode which can be used to do in-place replacement of the
12204 // long variant with the shorter variant. The compiler will determine if a
12205 // branch can be taken by the is_short_branch_offset() predicate in the machine
12206 // specific code section of the file.
12207
12208 // Jump Direct - Label defines a relative address from JMP+1
12209 instruct jmpDir_short(label labl) %{
12210 match(Goto);
12211 effect(USE labl);
12212
12213 ins_cost(300);
12214 format %{ "JMP,s $labl" %}
12215 size(2);
12216 ins_encode %{
12217 Label* L = $labl$$label;
12218 __ jmpb(*L);
12219 %}
12220 ins_pipe( pipe_jmp );
12221 ins_short_branch(1);
12222 %}
12223
12224 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12225 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12226 match(If cop cr);
12227 effect(USE labl);
12228
12229 ins_cost(300);
12230 format %{ "J$cop,s $labl" %}
12231 size(2);
12232 ins_encode %{
12233 Label* L = $labl$$label;
12234 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12235 %}
12236 ins_pipe( pipe_jcc );
12237 ins_short_branch(1);
12238 %}
12239
12240 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12241 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12242 match(CountedLoopEnd cop cr);
12243 effect(USE labl);
12244
12245 ins_cost(300);
12246 format %{ "J$cop,s $labl\t# Loop end" %}
12247 size(2);
12248 ins_encode %{
12249 Label* L = $labl$$label;
12250 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12251 %}
12252 ins_pipe( pipe_jcc );
12253 ins_short_branch(1);
12254 %}
12255
12256 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12257 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12258 match(CountedLoopEnd cop cmp);
12259 effect(USE labl);
12260
12261 ins_cost(300);
12262 format %{ "J$cop,us $labl\t# Loop end" %}
12263 size(2);
12264 ins_encode %{
12265 Label* L = $labl$$label;
12266 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12267 %}
12268 ins_pipe( pipe_jcc );
12269 ins_short_branch(1);
12270 %}
12271
12272 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12273 match(CountedLoopEnd cop cmp);
12274 effect(USE labl);
12275
12276 ins_cost(300);
12277 format %{ "J$cop,us $labl\t# Loop end" %}
12278 size(2);
12279 ins_encode %{
12280 Label* L = $labl$$label;
12281 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12282 %}
12283 ins_pipe( pipe_jcc );
12284 ins_short_branch(1);
12285 %}
12286
12287 // Jump Direct Conditional - using unsigned comparison
12288 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12289 match(If cop cmp);
12290 effect(USE labl);
12291
12292 ins_cost(300);
12293 format %{ "J$cop,us $labl" %}
12294 size(2);
12295 ins_encode %{
12296 Label* L = $labl$$label;
12297 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12298 %}
12299 ins_pipe( pipe_jcc );
12300 ins_short_branch(1);
12301 %}
12302
12303 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12304 match(If cop cmp);
12305 effect(USE labl);
12306
12307 ins_cost(300);
12308 format %{ "J$cop,us $labl" %}
12309 size(2);
12310 ins_encode %{
12311 Label* L = $labl$$label;
12312 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12313 %}
12314 ins_pipe( pipe_jcc );
12315 ins_short_branch(1);
12316 %}
12317
12318 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12319 match(If cop cmp);
12320 effect(USE labl);
12321
12322 ins_cost(300);
12323 format %{ $$template
12324 if ($cop$$cmpcode == Assembler::notEqual) {
12325 $$emit$$"JP,u,s $labl\n\t"
12326 $$emit$$"J$cop,u,s $labl"
12327 } else {
12328 $$emit$$"JP,u,s done\n\t"
12329 $$emit$$"J$cop,u,s $labl\n\t"
12330 $$emit$$"done:"
12331 }
12332 %}
12333 size(4);
12334 ins_encode %{
12335 Label* l = $labl$$label;
12336 if ($cop$$cmpcode == Assembler::notEqual) {
12337 __ jccb(Assembler::parity, *l);
12338 __ jccb(Assembler::notEqual, *l);
12339 } else if ($cop$$cmpcode == Assembler::equal) {
12340 Label done;
12341 __ jccb(Assembler::parity, done);
12342 __ jccb(Assembler::equal, *l);
12343 __ bind(done);
12344 } else {
12345 ShouldNotReachHere();
12346 }
12347 %}
12348 ins_pipe(pipe_jcc);
12349 ins_short_branch(1);
12350 %}
12351
12352 // ============================================================================
12353 // Long Compare
12354 //
12355 // Currently we hold longs in 2 registers. Comparing such values efficiently
12356 // is tricky. The flavor of compare used depends on whether we are testing
12357 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12358 // The GE test is the negated LT test. The LE test can be had by commuting
12359 // the operands (yielding a GE test) and then negating; negate again for the
12360 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12361 // NE test is negated from that.
12362
12363 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12364 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12365 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12366 // are collapsed internally in the ADLC's dfa-gen code. The match for
12367 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12368 // foo match ends up with the wrong leaf. One fix is to not match both
12369 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12370 // both forms beat the trinary form of long-compare and both are very useful
12371 // on Intel which has so few registers.
12372
12373 // Manifest a CmpL result in an integer register. Very painful.
12374 // This is the test to avoid.
12375 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12376 match(Set dst (CmpL3 src1 src2));
12377 effect( KILL flags );
12378 ins_cost(1000);
12379 format %{ "XOR $dst,$dst\n\t"
12380 "CMP $src1.hi,$src2.hi\n\t"
12381 "JLT,s m_one\n\t"
12382 "JGT,s p_one\n\t"
12383 "CMP $src1.lo,$src2.lo\n\t"
12384 "JB,s m_one\n\t"
12385 "JEQ,s done\n"
12386 "p_one:\tINC $dst\n\t"
12387 "JMP,s done\n"
12388 "m_one:\tDEC $dst\n"
12389 "done:" %}
12390 ins_encode %{
12391 Label p_one, m_one, done;
12392 __ xorptr($dst$$Register, $dst$$Register);
12393 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12394 __ jccb(Assembler::less, m_one);
12395 __ jccb(Assembler::greater, p_one);
12396 __ cmpl($src1$$Register, $src2$$Register);
12397 __ jccb(Assembler::below, m_one);
12398 __ jccb(Assembler::equal, done);
12399 __ bind(p_one);
12400 __ incrementl($dst$$Register);
12401 __ jmpb(done);
12402 __ bind(m_one);
12403 __ decrementl($dst$$Register);
12404 __ bind(done);
12405 %}
12406 ins_pipe( pipe_slow );
12407 %}
12408
12409 //======
12410 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12411 // compares. Can be used for LE or GT compares by reversing arguments.
12412 // NOT GOOD FOR EQ/NE tests.
12413 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12414 match( Set flags (CmpL src zero ));
12415 ins_cost(100);
12416 format %{ "TEST $src.hi,$src.hi" %}
12417 opcode(0x85);
12418 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12419 ins_pipe( ialu_cr_reg_reg );
12420 %}
12421
12422 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12423 // compares. Can be used for LE or GT compares by reversing arguments.
12424 // NOT GOOD FOR EQ/NE tests.
12425 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12426 match( Set flags (CmpL src1 src2 ));
12427 effect( TEMP tmp );
12428 ins_cost(300);
12429 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12430 "MOV $tmp,$src1.hi\n\t"
12431 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12432 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12433 ins_pipe( ialu_cr_reg_reg );
12434 %}
12435
12436 // Long compares reg < zero/req OR reg >= zero/req.
12437 // Just a wrapper for a normal branch, plus the predicate test.
12438 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12439 match(If cmp flags);
12440 effect(USE labl);
12441 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12442 expand %{
12443 jmpCon(cmp,flags,labl); // JLT or JGE...
12444 %}
12445 %}
12446
12447 // Compare 2 longs and CMOVE longs.
12448 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12449 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12450 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12451 ins_cost(400);
12452 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12453 "CMOV$cmp $dst.hi,$src.hi" %}
12454 opcode(0x0F,0x40);
12455 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12456 ins_pipe( pipe_cmov_reg_long );
12457 %}
12458
12459 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12460 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12461 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12462 ins_cost(500);
12463 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12464 "CMOV$cmp $dst.hi,$src.hi" %}
12465 opcode(0x0F,0x40);
12466 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12467 ins_pipe( pipe_cmov_reg_long );
12468 %}
12469
12470 // Compare 2 longs and CMOVE ints.
12471 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12472 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12473 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12474 ins_cost(200);
12475 format %{ "CMOV$cmp $dst,$src" %}
12476 opcode(0x0F,0x40);
12477 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12478 ins_pipe( pipe_cmov_reg );
12479 %}
12480
12481 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12482 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12483 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12484 ins_cost(250);
12485 format %{ "CMOV$cmp $dst,$src" %}
12486 opcode(0x0F,0x40);
12487 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12488 ins_pipe( pipe_cmov_mem );
12489 %}
12490
12491 // Compare 2 longs and CMOVE ints.
12492 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12493 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12494 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12495 ins_cost(200);
12496 format %{ "CMOV$cmp $dst,$src" %}
12497 opcode(0x0F,0x40);
12498 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12499 ins_pipe( pipe_cmov_reg );
12500 %}
12501
12502 // Compare 2 longs and CMOVE doubles
12503 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12504 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12505 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12506 ins_cost(200);
12507 expand %{
12508 fcmovDPR_regS(cmp,flags,dst,src);
12509 %}
12510 %}
12511
12512 // Compare 2 longs and CMOVE doubles
12513 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12514 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12515 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12516 ins_cost(200);
12517 expand %{
12518 fcmovD_regS(cmp,flags,dst,src);
12519 %}
12520 %}
12521
12522 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12523 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12524 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12525 ins_cost(200);
12526 expand %{
12527 fcmovFPR_regS(cmp,flags,dst,src);
12528 %}
12529 %}
12530
12531 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12532 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12533 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12534 ins_cost(200);
12535 expand %{
12536 fcmovF_regS(cmp,flags,dst,src);
12537 %}
12538 %}
12539
12540 //======
12541 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12542 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12543 match( Set flags (CmpL src zero ));
12544 effect(TEMP tmp);
12545 ins_cost(200);
12546 format %{ "MOV $tmp,$src.lo\n\t"
12547 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12548 ins_encode( long_cmp_flags0( src, tmp ) );
12549 ins_pipe( ialu_reg_reg_long );
12550 %}
12551
12552 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12553 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12554 match( Set flags (CmpL src1 src2 ));
12555 ins_cost(200+300);
12556 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12557 "JNE,s skip\n\t"
12558 "CMP $src1.hi,$src2.hi\n\t"
12559 "skip:\t" %}
12560 ins_encode( long_cmp_flags1( src1, src2 ) );
12561 ins_pipe( ialu_cr_reg_reg );
12562 %}
12563
12564 // Long compare reg == zero/reg OR reg != zero/reg
12565 // Just a wrapper for a normal branch, plus the predicate test.
12566 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12567 match(If cmp flags);
12568 effect(USE labl);
12569 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12570 expand %{
12571 jmpCon(cmp,flags,labl); // JEQ or JNE...
12572 %}
12573 %}
12574
12575 // Compare 2 longs and CMOVE longs.
12576 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12577 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12578 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12579 ins_cost(400);
12580 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12581 "CMOV$cmp $dst.hi,$src.hi" %}
12582 opcode(0x0F,0x40);
12583 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12584 ins_pipe( pipe_cmov_reg_long );
12585 %}
12586
12587 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12588 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12589 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12590 ins_cost(500);
12591 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12592 "CMOV$cmp $dst.hi,$src.hi" %}
12593 opcode(0x0F,0x40);
12594 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12595 ins_pipe( pipe_cmov_reg_long );
12596 %}
12597
12598 // Compare 2 longs and CMOVE ints.
12599 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12600 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12601 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12602 ins_cost(200);
12603 format %{ "CMOV$cmp $dst,$src" %}
12604 opcode(0x0F,0x40);
12605 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12606 ins_pipe( pipe_cmov_reg );
12607 %}
12608
12609 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12610 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12611 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12612 ins_cost(250);
12613 format %{ "CMOV$cmp $dst,$src" %}
12614 opcode(0x0F,0x40);
12615 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12616 ins_pipe( pipe_cmov_mem );
12617 %}
12618
12619 // Compare 2 longs and CMOVE ints.
12620 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12621 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12622 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12623 ins_cost(200);
12624 format %{ "CMOV$cmp $dst,$src" %}
12625 opcode(0x0F,0x40);
12626 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12627 ins_pipe( pipe_cmov_reg );
12628 %}
12629
12630 // Compare 2 longs and CMOVE doubles
12631 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12632 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12633 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12634 ins_cost(200);
12635 expand %{
12636 fcmovDPR_regS(cmp,flags,dst,src);
12637 %}
12638 %}
12639
12640 // Compare 2 longs and CMOVE doubles
12641 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12642 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12643 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12644 ins_cost(200);
12645 expand %{
12646 fcmovD_regS(cmp,flags,dst,src);
12647 %}
12648 %}
12649
12650 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12651 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12652 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12653 ins_cost(200);
12654 expand %{
12655 fcmovFPR_regS(cmp,flags,dst,src);
12656 %}
12657 %}
12658
12659 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12660 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12661 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12662 ins_cost(200);
12663 expand %{
12664 fcmovF_regS(cmp,flags,dst,src);
12665 %}
12666 %}
12667
12668 //======
12669 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12670 // Same as cmpL_reg_flags_LEGT except must negate src
12671 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12672 match( Set flags (CmpL src zero ));
12673 effect( TEMP tmp );
12674 ins_cost(300);
12675 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12676 "CMP $tmp,$src.lo\n\t"
12677 "SBB $tmp,$src.hi\n\t" %}
12678 ins_encode( long_cmp_flags3(src, tmp) );
12679 ins_pipe( ialu_reg_reg_long );
12680 %}
12681
12682 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12683 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12684 // requires a commuted test to get the same result.
12685 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12686 match( Set flags (CmpL src1 src2 ));
12687 effect( TEMP tmp );
12688 ins_cost(300);
12689 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12690 "MOV $tmp,$src2.hi\n\t"
12691 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12692 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12693 ins_pipe( ialu_cr_reg_reg );
12694 %}
12695
12696 // Long compares reg < zero/req OR reg >= zero/req.
12697 // Just a wrapper for a normal branch, plus the predicate test
12698 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12699 match(If cmp flags);
12700 effect(USE labl);
12701 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12702 ins_cost(300);
12703 expand %{
12704 jmpCon(cmp,flags,labl); // JGT or JLE...
12705 %}
12706 %}
12707
12708 // Compare 2 longs and CMOVE longs.
12709 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12710 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12711 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12712 ins_cost(400);
12713 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12714 "CMOV$cmp $dst.hi,$src.hi" %}
12715 opcode(0x0F,0x40);
12716 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12717 ins_pipe( pipe_cmov_reg_long );
12718 %}
12719
12720 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12721 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12722 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12723 ins_cost(500);
12724 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12725 "CMOV$cmp $dst.hi,$src.hi+4" %}
12726 opcode(0x0F,0x40);
12727 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12728 ins_pipe( pipe_cmov_reg_long );
12729 %}
12730
12731 // Compare 2 longs and CMOVE ints.
12732 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12733 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12734 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12735 ins_cost(200);
12736 format %{ "CMOV$cmp $dst,$src" %}
12737 opcode(0x0F,0x40);
12738 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12739 ins_pipe( pipe_cmov_reg );
12740 %}
12741
12742 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12743 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12744 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12745 ins_cost(250);
12746 format %{ "CMOV$cmp $dst,$src" %}
12747 opcode(0x0F,0x40);
12748 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12749 ins_pipe( pipe_cmov_mem );
12750 %}
12751
12752 // Compare 2 longs and CMOVE ptrs.
12753 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12754 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12755 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12756 ins_cost(200);
12757 format %{ "CMOV$cmp $dst,$src" %}
12758 opcode(0x0F,0x40);
12759 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12760 ins_pipe( pipe_cmov_reg );
12761 %}
12762
12763 // Compare 2 longs and CMOVE doubles
12764 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12765 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12766 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12767 ins_cost(200);
12768 expand %{
12769 fcmovDPR_regS(cmp,flags,dst,src);
12770 %}
12771 %}
12772
12773 // Compare 2 longs and CMOVE doubles
12774 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12775 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12776 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12777 ins_cost(200);
12778 expand %{
12779 fcmovD_regS(cmp,flags,dst,src);
12780 %}
12781 %}
12782
12783 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12784 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12785 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12786 ins_cost(200);
12787 expand %{
12788 fcmovFPR_regS(cmp,flags,dst,src);
12789 %}
12790 %}
12791
12792
12793 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12794 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12795 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12796 ins_cost(200);
12797 expand %{
12798 fcmovF_regS(cmp,flags,dst,src);
12799 %}
12800 %}
12801
12802
12803 // ============================================================================
12804 // Procedure Call/Return Instructions
12805 // Call Java Static Instruction
12806 // Note: If this code changes, the corresponding ret_addr_offset() and
12807 // compute_padding() functions will have to be adjusted.
12808 instruct CallStaticJavaDirect(method meth) %{
12809 match(CallStaticJava);
12810 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12811 effect(USE meth);
12812
12813 ins_cost(300);
12814 format %{ "CALL,static " %}
12815 opcode(0xE8); /* E8 cd */
12816 ins_encode( pre_call_resets,
12817 Java_Static_Call( meth ),
12818 call_epilog,
12819 post_call_FPU );
12820 ins_pipe( pipe_slow );
12821 ins_alignment(4);
12822 %}
12823
12824 // Call Java Static Instruction (method handle version)
12825 // Note: If this code changes, the corresponding ret_addr_offset() and
12826 // compute_padding() functions will have to be adjusted.
12827 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12828 match(CallStaticJava);
12829 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12830 effect(USE meth);
12831 // EBP is saved by all callees (for interpreter stack correction).
12832 // We use it here for a similar purpose, in {preserve,restore}_SP.
12833
12834 ins_cost(300);
12835 format %{ "CALL,static/MethodHandle " %}
12836 opcode(0xE8); /* E8 cd */
12837 ins_encode( pre_call_resets,
12838 preserve_SP,
12839 Java_Static_Call( meth ),
12840 restore_SP,
12841 call_epilog,
12842 post_call_FPU );
12843 ins_pipe( pipe_slow );
12844 ins_alignment(4);
12845 %}
12846
12847 // Call Java Dynamic Instruction
12848 // Note: If this code changes, the corresponding ret_addr_offset() and
12849 // compute_padding() functions will have to be adjusted.
12850 instruct CallDynamicJavaDirect(method meth) %{
12851 match(CallDynamicJava);
12852 effect(USE meth);
12853
12854 ins_cost(300);
12855 format %{ "MOV EAX,(oop)-1\n\t"
12856 "CALL,dynamic" %}
12857 opcode(0xE8); /* E8 cd */
12858 ins_encode( pre_call_resets,
12859 Java_Dynamic_Call( meth ),
12860 call_epilog,
12861 post_call_FPU );
12862 ins_pipe( pipe_slow );
12863 ins_alignment(4);
12864 %}
12865
12866 // Call Runtime Instruction
12867 instruct CallRuntimeDirect(method meth) %{
12868 match(CallRuntime );
12869 effect(USE meth);
12870
12871 ins_cost(300);
12872 format %{ "CALL,runtime " %}
12873 opcode(0xE8); /* E8 cd */
12874 // Use FFREEs to clear entries in float stack
12875 ins_encode( pre_call_resets,
12876 FFree_Float_Stack_All,
12877 Java_To_Runtime( meth ),
12878 post_call_FPU );
12879 ins_pipe( pipe_slow );
12880 %}
12881
12882 // Call runtime without safepoint
12883 instruct CallLeafDirect(method meth) %{
12884 match(CallLeaf);
12885 effect(USE meth);
12886
12887 ins_cost(300);
12888 format %{ "CALL_LEAF,runtime " %}
12889 opcode(0xE8); /* E8 cd */
12890 ins_encode( pre_call_resets,
12891 FFree_Float_Stack_All,
12892 Java_To_Runtime( meth ),
12893 Verify_FPU_For_Leaf, post_call_FPU );
12894 ins_pipe( pipe_slow );
12895 %}
12896
12897 instruct CallLeafNoFPDirect(method meth) %{
12898 match(CallLeafNoFP);
12899 effect(USE meth);
12900
12901 ins_cost(300);
12902 format %{ "CALL_LEAF_NOFP,runtime " %}
12903 opcode(0xE8); /* E8 cd */
12904 ins_encode(Java_To_Runtime(meth));
12905 ins_pipe( pipe_slow );
12906 %}
12907
12908
12909 // Return Instruction
12910 // Remove the return address & jump to it.
12911 instruct Ret() %{
12912 match(Return);
12913 format %{ "RET" %}
12914 opcode(0xC3);
12915 ins_encode(OpcP);
12916 ins_pipe( pipe_jmp );
12917 %}
12918
12919 // Tail Call; Jump from runtime stub to Java code.
12920 // Also known as an 'interprocedural jump'.
12921 // Target of jump will eventually return to caller.
12922 // TailJump below removes the return address.
12923 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12924 match(TailCall jump_target method_oop );
12925 ins_cost(300);
12926 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12927 opcode(0xFF, 0x4); /* Opcode FF /4 */
12928 ins_encode( OpcP, RegOpc(jump_target) );
12929 ins_pipe( pipe_jmp );
12930 %}
12931
12932
12933 // Tail Jump; remove the return address; jump to target.
12934 // TailCall above leaves the return address around.
12935 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12936 match( TailJump jump_target ex_oop );
12937 ins_cost(300);
12938 format %{ "POP EDX\t# pop return address into dummy\n\t"
12939 "JMP $jump_target " %}
12940 opcode(0xFF, 0x4); /* Opcode FF /4 */
12941 ins_encode( enc_pop_rdx,
12942 OpcP, RegOpc(jump_target) );
12943 ins_pipe( pipe_jmp );
12944 %}
12945
12946 // Create exception oop: created by stack-crawling runtime code.
12947 // Created exception is now available to this handler, and is setup
12948 // just prior to jumping to this handler. No code emitted.
12949 instruct CreateException( eAXRegP ex_oop )
12950 %{
12951 match(Set ex_oop (CreateEx));
12952
12953 size(0);
12954 // use the following format syntax
12955 format %{ "# exception oop is in EAX; no code emitted" %}
12956 ins_encode();
12957 ins_pipe( empty );
12958 %}
12959
12960
12961 // Rethrow exception:
12962 // The exception oop will come in the first argument position.
12963 // Then JUMP (not call) to the rethrow stub code.
12964 instruct RethrowException()
12965 %{
12966 match(Rethrow);
12967
12968 // use the following format syntax
12969 format %{ "JMP rethrow_stub" %}
12970 ins_encode(enc_rethrow);
12971 ins_pipe( pipe_jmp );
12972 %}
12973
12974 // inlined locking and unlocking
12975
12976
12977 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12978 match( Set cr (FastLock object box) );
12979 effect( TEMP tmp, TEMP scr, USE_KILL box );
12980 ins_cost(300);
12981 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12982 ins_encode( Fast_Lock(object,box,tmp,scr) );
12983 ins_pipe( pipe_slow );
12984 %}
12985
12986 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12987 match( Set cr (FastUnlock object box) );
12988 effect( TEMP tmp, USE_KILL box );
12989 ins_cost(300);
12990 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12991 ins_encode( Fast_Unlock(object,box,tmp) );
12992 ins_pipe( pipe_slow );
12993 %}
12994
12995
12996
12997 // ============================================================================
12998 // Safepoint Instruction
12999 instruct safePoint_poll(eFlagsReg cr) %{
13000 match(SafePoint);
13001 effect(KILL cr);
13002
13003 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13004 // On SPARC that might be acceptable as we can generate the address with
13005 // just a sethi, saving an or. By polling at offset 0 we can end up
13006 // putting additional pressure on the index-0 in the D$. Because of
13007 // alignment (just like the situation at hand) the lower indices tend
13008 // to see more traffic. It'd be better to change the polling address
13009 // to offset 0 of the last $line in the polling page.
13010
13011 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13012 ins_cost(125);
13013 size(6) ;
13014 ins_encode( Safepoint_Poll() );
13015 ins_pipe( ialu_reg_mem );
13016 %}
13017
13018
13019 // ============================================================================
13020 // This name is KNOWN by the ADLC and cannot be changed.
13021 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13022 // for this guy.
13023 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13024 match(Set dst (ThreadLocal));
13025 effect(DEF dst, KILL cr);
13026
13027 format %{ "MOV $dst, Thread::current()" %}
13028 ins_encode %{
13029 Register dstReg = as_Register($dst$$reg);
13030 __ get_thread(dstReg);
13031 %}
13032 ins_pipe( ialu_reg_fat );
13033 %}
13034
13035
13036
13037 //----------PEEPHOLE RULES-----------------------------------------------------
13038 // These must follow all instruction definitions as they use the names
13039 // defined in the instructions definitions.
13040 //
13041 // peepmatch ( root_instr_name [preceding_instruction]* );
13042 //
13043 // peepconstraint %{
13044 // (instruction_number.operand_name relational_op instruction_number.operand_name
13045 // [, ...] );
13046 // // instruction numbers are zero-based using left to right order in peepmatch
13047 //
13048 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13049 // // provide an instruction_number.operand_name for each operand that appears
13050 // // in the replacement instruction's match rule
13051 //
13052 // ---------VM FLAGS---------------------------------------------------------
13053 //
13054 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13055 //
13056 // Each peephole rule is given an identifying number starting with zero and
13057 // increasing by one in the order seen by the parser. An individual peephole
13058 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13059 // on the command-line.
13060 //
13061 // ---------CURRENT LIMITATIONS----------------------------------------------
13062 //
13063 // Only match adjacent instructions in same basic block
13064 // Only equality constraints
13065 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13066 // Only one replacement instruction
13067 //
13068 // ---------EXAMPLE----------------------------------------------------------
13069 //
13070 // // pertinent parts of existing instructions in architecture description
13071 // instruct movI(rRegI dst, rRegI src) %{
13072 // match(Set dst (CopyI src));
13073 // %}
13074 //
13075 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13076 // match(Set dst (AddI dst src));
13077 // effect(KILL cr);
13078 // %}
13079 //
13080 // // Change (inc mov) to lea
13081 // peephole %{
13082 // // increment preceeded by register-register move
13083 // peepmatch ( incI_eReg movI );
13084 // // require that the destination register of the increment
13085 // // match the destination register of the move
13086 // peepconstraint ( 0.dst == 1.dst );
13087 // // construct a replacement instruction that sets
13088 // // the destination to ( move's source register + one )
13089 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13090 // %}
13091 //
13092 // Implementation no longer uses movX instructions since
13093 // machine-independent system no longer uses CopyX nodes.
13094 //
13095 // peephole %{
13096 // peepmatch ( incI_eReg movI );
13097 // peepconstraint ( 0.dst == 1.dst );
13098 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13099 // %}
13100 //
13101 // peephole %{
13102 // peepmatch ( decI_eReg movI );
13103 // peepconstraint ( 0.dst == 1.dst );
13104 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13105 // %}
13106 //
13107 // peephole %{
13108 // peepmatch ( addI_eReg_imm movI );
13109 // peepconstraint ( 0.dst == 1.dst );
13110 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13111 // %}
13112 //
13113 // peephole %{
13114 // peepmatch ( addP_eReg_imm movP );
13115 // peepconstraint ( 0.dst == 1.dst );
13116 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13117 // %}
13118
13119 // // Change load of spilled value to only a spill
13120 // instruct storeI(memory mem, rRegI src) %{
13121 // match(Set mem (StoreI mem src));
13122 // %}
13123 //
13124 // instruct loadI(rRegI dst, memory mem) %{
13125 // match(Set dst (LoadI mem));
13126 // %}
13127 //
13128 peephole %{
13129 peepmatch ( loadI storeI );
13130 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13131 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13132 %}
13133
13134 //----------SMARTSPILL RULES---------------------------------------------------
13135 // These must follow all instruction definitions as they use the names
13136 // defined in the instructions definitions.