src/cpu/sparc/vm/sparc.ad

rev 5661 : 8003854: PPC64 (part 115): Introduce lateExpand that expands nodes after register allocation.

*** 1032,1041 ****
--- 1032,1046 ----
      }
      return offset;
    }
  }
  
+ bool MachConstantBaseNode::requires_late_expand() const { return false; }
+ void MachConstantBaseNode::lateExpand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
+   ShouldNotReachHere();
+ }
+ 
  void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
    Compile* C = ra_->C;
    Compile::ConstantTable& constant_table = C->constant_table();
    MacroAssembler _masm(&cbuf);
  
*** 1882,1891 ****
--- 1887,1899 ----
  // CMOVF/CMOVD are expensive on T4 and on SPARC64.
  const int Matcher::float_cmove_cost() {
    return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
  }
  
+ // Does the CPU require late expand (see block.cpp for description of late expand)?
+ const bool Matcher::require_late_expand = false;
+ 
  // Should the Matcher clone shifts on addressing modes, expecting them to
  // be subsumed into complex addressing expressions or compute them into
  // registers?  True for Intel but false for most RISCs
  const bool Matcher::clone_shift_expressions = false;