src/cpu/x86/vm/x86_64.ad

rev 5661 : 8003854: PPC64 (part 115): Introduce lateExpand that expands nodes after register allocation.

@@ -686,10 +686,15 @@
 
 int Compile::ConstantTable::calculate_table_base_offset() const {
   return 0;  // absolute addressing, no offset
 }
 
+bool MachConstantBaseNode::requires_late_expand() const { return false; }
+void MachConstantBaseNode::lateExpand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
+  ShouldNotReachHere();
+}
+
 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
   // Empty encoding
 }
 
 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {

@@ -1540,10 +1545,13 @@
 const int Matcher::long_cmove_cost() { return 0; }
 
 // No CMOVF/CMOVD with SSE2
 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
 
+// Does the CPU require late expand (see block.cpp for description of late expand)?
+const bool Matcher::require_late_expand = false;
+
 // Should the Matcher clone shifts on addressing modes, expecting them
 // to be subsumed into complex addressing expressions or compute them
 // into registers?  True for Intel but false for most RISCs
 const bool Matcher::clone_shift_expressions = true;