1 /*
2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "code/debugInfoRec.hpp"
29 #include "code/icBuffer.hpp"
30 #include "code/vtableStubs.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "oops/compiledICHolder.hpp"
33 #include "prims/jvmtiRedefineClassesTrace.hpp"
34 #include "runtime/sharedRuntime.hpp"
35 #include "runtime/vframeArray.hpp"
36 #include "vmreg_x86.inline.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_Runtime1.hpp"
39 #endif
40 #ifdef COMPILER2
41 #include "opto/runtime.hpp"
42 #endif
43
44 #define __ masm->
45
46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
47
48 class SimpleRuntimeFrame {
49
50 public:
51
52 // Most of the runtime stubs have this simple frame layout.
53 // This class exists to make the layout shared in one place.
54 // Offsets are for compiler stack slots, which are jints.
55 enum layout {
56 // The frame sender code expects that rbp will be in the "natural" place and
57 // will override any oopMap setting for it. We must therefore force the layout
58 // so that it agrees with the frame sender code.
59 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
60 rbp_off2,
61 return_off, return_off2,
62 framesize
63 };
64 };
65
66 class RegisterSaver {
67 // Capture info about frame layout. Layout offsets are in jint
68 // units because compiler frame slots are jints.
69 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
70 enum layout {
71 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
72 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
73 DEF_XMM_OFFS(0),
74 DEF_XMM_OFFS(1),
75 DEF_XMM_OFFS(2),
76 DEF_XMM_OFFS(3),
77 DEF_XMM_OFFS(4),
78 DEF_XMM_OFFS(5),
79 DEF_XMM_OFFS(6),
80 DEF_XMM_OFFS(7),
81 DEF_XMM_OFFS(8),
82 DEF_XMM_OFFS(9),
83 DEF_XMM_OFFS(10),
84 DEF_XMM_OFFS(11),
85 DEF_XMM_OFFS(12),
86 DEF_XMM_OFFS(13),
87 DEF_XMM_OFFS(14),
88 DEF_XMM_OFFS(15),
89 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
90 fpu_stateH_end,
91 r15_off, r15H_off,
92 r14_off, r14H_off,
93 r13_off, r13H_off,
94 r12_off, r12H_off,
95 r11_off, r11H_off,
96 r10_off, r10H_off,
97 r9_off, r9H_off,
98 r8_off, r8H_off,
99 rdi_off, rdiH_off,
100 rsi_off, rsiH_off,
101 ignore_off, ignoreH_off, // extra copy of rbp
102 rsp_off, rspH_off,
103 rbx_off, rbxH_off,
104 rdx_off, rdxH_off,
105 rcx_off, rcxH_off,
106 rax_off, raxH_off,
107 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
108 align_off, alignH_off,
109 flags_off, flagsH_off,
110 // The frame sender code expects that rbp will be in the "natural" place and
111 // will override any oopMap setting for it. We must therefore force the layout
112 // so that it agrees with the frame sender code.
113 rbp_off, rbpH_off, // copy of rbp we will restore
114 return_off, returnH_off, // slot for return address
115 reg_save_size // size in compiler stack slots
116 };
117
118 public:
119 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false);
120 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false);
121
122 // Offsets into the register save area
123 // Used by deoptimization when it is managing result register
124 // values on its own
125
126 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
127 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
128 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
129 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
130 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
131
132 // During deoptimization only the result registers need to be restored,
133 // all the other values have already been extracted.
134 static void restore_result_registers(MacroAssembler* masm);
135 };
136
137 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) {
138 int vect_words = 0;
139 #ifdef COMPILER2
140 if (save_vectors) {
141 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
142 assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
143 // Save upper half of YMM registes
144 vect_words = 16 * 16 / wordSize;
145 additional_frame_words += vect_words;
146 }
147 #else
148 assert(!save_vectors, "vectors are generated only by C2");
149 #endif
150
151 // Always make the frame size 16-byte aligned
152 int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
153 reg_save_size*BytesPerInt, 16);
154 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
155 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
156 // The caller will allocate additional_frame_words
157 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
158 // CodeBlob frame size is in words.
159 int frame_size_in_words = frame_size_in_bytes / wordSize;
160 *total_frame_words = frame_size_in_words;
161
162 // Save registers, fpu state, and flags.
163 // We assume caller has already pushed the return address onto the
164 // stack, so rsp is 8-byte aligned here.
165 // We push rpb twice in this sequence because we want the real rbp
166 // to be under the return like a normal enter.
167
168 __ enter(); // rsp becomes 16-byte aligned here
169 __ push_CPU_state(); // Push a multiple of 16 bytes
170
171 if (vect_words > 0) {
172 assert(vect_words*wordSize == 256, "");
173 __ subptr(rsp, 256); // Save upper half of YMM registes
174 __ vextractf128h(Address(rsp, 0),xmm0);
175 __ vextractf128h(Address(rsp, 16),xmm1);
176 __ vextractf128h(Address(rsp, 32),xmm2);
177 __ vextractf128h(Address(rsp, 48),xmm3);
178 __ vextractf128h(Address(rsp, 64),xmm4);
179 __ vextractf128h(Address(rsp, 80),xmm5);
180 __ vextractf128h(Address(rsp, 96),xmm6);
181 __ vextractf128h(Address(rsp,112),xmm7);
182 __ vextractf128h(Address(rsp,128),xmm8);
183 __ vextractf128h(Address(rsp,144),xmm9);
184 __ vextractf128h(Address(rsp,160),xmm10);
185 __ vextractf128h(Address(rsp,176),xmm11);
186 __ vextractf128h(Address(rsp,192),xmm12);
187 __ vextractf128h(Address(rsp,208),xmm13);
188 __ vextractf128h(Address(rsp,224),xmm14);
189 __ vextractf128h(Address(rsp,240),xmm15);
190 }
191 if (frame::arg_reg_save_area_bytes != 0) {
192 // Allocate argument register save area
193 __ subptr(rsp, frame::arg_reg_save_area_bytes);
194 }
195
196 // Set an oopmap for the call site. This oopmap will map all
197 // oop-registers and debug-info registers as callee-saved. This
198 // will allow deoptimization at this safepoint to find all possible
199 // debug-info recordings, as well as let GC find all oops.
200
201 OopMapSet *oop_maps = new OopMapSet();
202 OopMap* map = new OopMap(frame_size_in_slots, 0);
203
204 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_slots)
205
206 map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg());
207 map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg());
208 map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg());
209 map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg());
210 // rbp location is known implicitly by the frame sender code, needs no oopmap
211 // and the location where rbp was saved by is ignored
212 map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg());
213 map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg());
214 map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg());
215 map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg());
216 map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg());
217 map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg());
218 map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg());
219 map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg());
220 map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg());
221 map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg());
222 map->set_callee_saved(STACK_OFFSET(xmm0_off ), xmm0->as_VMReg());
223 map->set_callee_saved(STACK_OFFSET(xmm1_off ), xmm1->as_VMReg());
224 map->set_callee_saved(STACK_OFFSET(xmm2_off ), xmm2->as_VMReg());
225 map->set_callee_saved(STACK_OFFSET(xmm3_off ), xmm3->as_VMReg());
226 map->set_callee_saved(STACK_OFFSET(xmm4_off ), xmm4->as_VMReg());
227 map->set_callee_saved(STACK_OFFSET(xmm5_off ), xmm5->as_VMReg());
228 map->set_callee_saved(STACK_OFFSET(xmm6_off ), xmm6->as_VMReg());
229 map->set_callee_saved(STACK_OFFSET(xmm7_off ), xmm7->as_VMReg());
230 map->set_callee_saved(STACK_OFFSET(xmm8_off ), xmm8->as_VMReg());
231 map->set_callee_saved(STACK_OFFSET(xmm9_off ), xmm9->as_VMReg());
232 map->set_callee_saved(STACK_OFFSET(xmm10_off), xmm10->as_VMReg());
233 map->set_callee_saved(STACK_OFFSET(xmm11_off), xmm11->as_VMReg());
234 map->set_callee_saved(STACK_OFFSET(xmm12_off), xmm12->as_VMReg());
235 map->set_callee_saved(STACK_OFFSET(xmm13_off), xmm13->as_VMReg());
236 map->set_callee_saved(STACK_OFFSET(xmm14_off), xmm14->as_VMReg());
237 map->set_callee_saved(STACK_OFFSET(xmm15_off), xmm15->as_VMReg());
238
239 // %%% These should all be a waste but we'll keep things as they were for now
240 if (true) {
241 map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next());
242 map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next());
243 map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next());
244 map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next());
245 // rbp location is known implicitly by the frame sender code, needs no oopmap
246 map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next());
247 map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next());
248 map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next());
249 map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next());
250 map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next());
251 map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next());
252 map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next());
253 map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next());
254 map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next());
255 map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next());
256 map->set_callee_saved(STACK_OFFSET(xmm0H_off ), xmm0->as_VMReg()->next());
257 map->set_callee_saved(STACK_OFFSET(xmm1H_off ), xmm1->as_VMReg()->next());
258 map->set_callee_saved(STACK_OFFSET(xmm2H_off ), xmm2->as_VMReg()->next());
259 map->set_callee_saved(STACK_OFFSET(xmm3H_off ), xmm3->as_VMReg()->next());
260 map->set_callee_saved(STACK_OFFSET(xmm4H_off ), xmm4->as_VMReg()->next());
261 map->set_callee_saved(STACK_OFFSET(xmm5H_off ), xmm5->as_VMReg()->next());
262 map->set_callee_saved(STACK_OFFSET(xmm6H_off ), xmm6->as_VMReg()->next());
263 map->set_callee_saved(STACK_OFFSET(xmm7H_off ), xmm7->as_VMReg()->next());
264 map->set_callee_saved(STACK_OFFSET(xmm8H_off ), xmm8->as_VMReg()->next());
265 map->set_callee_saved(STACK_OFFSET(xmm9H_off ), xmm9->as_VMReg()->next());
266 map->set_callee_saved(STACK_OFFSET(xmm10H_off), xmm10->as_VMReg()->next());
267 map->set_callee_saved(STACK_OFFSET(xmm11H_off), xmm11->as_VMReg()->next());
268 map->set_callee_saved(STACK_OFFSET(xmm12H_off), xmm12->as_VMReg()->next());
269 map->set_callee_saved(STACK_OFFSET(xmm13H_off), xmm13->as_VMReg()->next());
270 map->set_callee_saved(STACK_OFFSET(xmm14H_off), xmm14->as_VMReg()->next());
271 map->set_callee_saved(STACK_OFFSET(xmm15H_off), xmm15->as_VMReg()->next());
272 }
273
274 return map;
275 }
276
277 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
278 if (frame::arg_reg_save_area_bytes != 0) {
279 // Pop arg register save area
280 __ addptr(rsp, frame::arg_reg_save_area_bytes);
281 }
282 #ifdef COMPILER2
283 if (restore_vectors) {
284 // Restore upper half of YMM registes.
285 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
286 assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
287 __ vinsertf128h(xmm0, Address(rsp, 0));
288 __ vinsertf128h(xmm1, Address(rsp, 16));
289 __ vinsertf128h(xmm2, Address(rsp, 32));
290 __ vinsertf128h(xmm3, Address(rsp, 48));
291 __ vinsertf128h(xmm4, Address(rsp, 64));
292 __ vinsertf128h(xmm5, Address(rsp, 80));
293 __ vinsertf128h(xmm6, Address(rsp, 96));
294 __ vinsertf128h(xmm7, Address(rsp,112));
295 __ vinsertf128h(xmm8, Address(rsp,128));
296 __ vinsertf128h(xmm9, Address(rsp,144));
297 __ vinsertf128h(xmm10, Address(rsp,160));
298 __ vinsertf128h(xmm11, Address(rsp,176));
299 __ vinsertf128h(xmm12, Address(rsp,192));
300 __ vinsertf128h(xmm13, Address(rsp,208));
301 __ vinsertf128h(xmm14, Address(rsp,224));
302 __ vinsertf128h(xmm15, Address(rsp,240));
303 __ addptr(rsp, 256);
304 }
305 #else
306 assert(!restore_vectors, "vectors are generated only by C2");
307 #endif
308 // Recover CPU state
309 __ pop_CPU_state();
310 // Get the rbp described implicitly by the calling convention (no oopMap)
311 __ pop(rbp);
312 }
313
314 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
315
316 // Just restore result register. Only used by deoptimization. By
317 // now any callee save register that needs to be restored to a c2
318 // caller of the deoptee has been extracted into the vframeArray
319 // and will be stuffed into the c2i adapter we create for later
320 // restoration so only result registers need to be restored here.
321
322 // Restore fp result register
323 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
324 // Restore integer result register
325 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
326 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
327
328 // Pop all of the register save are off the stack except the return address
329 __ addptr(rsp, return_offset_in_bytes());
330 }
331
332 // Is vector's size (in bytes) bigger than a size saved by default?
333 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions.
334 bool SharedRuntime::is_wide_vector(int size) {
335 return size > 16;
336 }
337
338 // The java_calling_convention describes stack locations as ideal slots on
339 // a frame with no abi restrictions. Since we must observe abi restrictions
340 // (like the placement of the register window) the slots must be biased by
341 // the following value.
342 static int reg2offset_in(VMReg r) {
343 // Account for saved rbp and return address
344 // This should really be in_preserve_stack_slots
345 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
346 }
347
348 static int reg2offset_out(VMReg r) {
349 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
350 }
351
352 // ---------------------------------------------------------------------------
353 // Read the array of BasicTypes from a signature, and compute where the
354 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
355 // quantities. Values less than VMRegImpl::stack0 are registers, those above
356 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
357 // as framesizes are fixed.
358 // VMRegImpl::stack0 refers to the first slot 0(sp).
359 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
360 // up to RegisterImpl::number_of_registers) are the 64-bit
361 // integer registers.
362
363 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
364 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
365 // units regardless of build. Of course for i486 there is no 64 bit build
366
367 // The Java calling convention is a "shifted" version of the C ABI.
368 // By skipping the first C ABI register we can call non-static jni methods
369 // with small numbers of arguments without having to shuffle the arguments
370 // at all. Since we control the java ABI we ought to at least get some
371 // advantage out of it.
372
373 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
374 VMRegPair *regs,
375 int total_args_passed,
376 int is_outgoing) {
377
378 // Create the mapping between argument positions and
379 // registers.
380 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
381 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
382 };
383 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
384 j_farg0, j_farg1, j_farg2, j_farg3,
385 j_farg4, j_farg5, j_farg6, j_farg7
386 };
387
388
389 uint int_args = 0;
390 uint fp_args = 0;
391 uint stk_args = 0; // inc by 2 each time
392
393 for (int i = 0; i < total_args_passed; i++) {
394 switch (sig_bt[i]) {
395 case T_BOOLEAN:
396 case T_CHAR:
397 case T_BYTE:
398 case T_SHORT:
399 case T_INT:
400 if (int_args < Argument::n_int_register_parameters_j) {
401 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
402 } else {
403 regs[i].set1(VMRegImpl::stack2reg(stk_args));
404 stk_args += 2;
405 }
406 break;
407 case T_VOID:
408 // halves of T_LONG or T_DOUBLE
409 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
410 regs[i].set_bad();
411 break;
412 case T_LONG:
413 assert(sig_bt[i + 1] == T_VOID, "expecting half");
414 // fall through
415 case T_OBJECT:
416 case T_ARRAY:
417 case T_ADDRESS:
418 if (int_args < Argument::n_int_register_parameters_j) {
419 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
420 } else {
421 regs[i].set2(VMRegImpl::stack2reg(stk_args));
422 stk_args += 2;
423 }
424 break;
425 case T_FLOAT:
426 if (fp_args < Argument::n_float_register_parameters_j) {
427 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
428 } else {
429 regs[i].set1(VMRegImpl::stack2reg(stk_args));
430 stk_args += 2;
431 }
432 break;
433 case T_DOUBLE:
434 assert(sig_bt[i + 1] == T_VOID, "expecting half");
435 if (fp_args < Argument::n_float_register_parameters_j) {
436 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
437 } else {
438 regs[i].set2(VMRegImpl::stack2reg(stk_args));
439 stk_args += 2;
440 }
441 break;
442 default:
443 ShouldNotReachHere();
444 break;
445 }
446 }
447
448 return round_to(stk_args, 2);
449 }
450
451 // Patch the callers callsite with entry to compiled code if it exists.
452 static void patch_callers_callsite(MacroAssembler *masm) {
453 Label L;
454 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
455 __ jcc(Assembler::equal, L);
456
457 // Save the current stack pointer
458 __ mov(r13, rsp);
459 // Schedule the branch target address early.
460 // Call into the VM to patch the caller, then jump to compiled callee
461 // rax isn't live so capture return address while we easily can
462 __ movptr(rax, Address(rsp, 0));
463
464 // align stack so push_CPU_state doesn't fault
465 __ andptr(rsp, -(StackAlignmentInBytes));
466 __ push_CPU_state();
467
468 // VM needs caller's callsite
469 // VM needs target method
470 // This needs to be a long call since we will relocate this adapter to
471 // the codeBuffer and it may not reach
472
473 // Allocate argument register save area
474 if (frame::arg_reg_save_area_bytes != 0) {
475 __ subptr(rsp, frame::arg_reg_save_area_bytes);
476 }
477 __ mov(c_rarg0, rbx);
478 __ mov(c_rarg1, rax);
479 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
480
481 // De-allocate argument register save area
482 if (frame::arg_reg_save_area_bytes != 0) {
483 __ addptr(rsp, frame::arg_reg_save_area_bytes);
484 }
485
486 __ pop_CPU_state();
487 // restore sp
488 __ mov(rsp, r13);
489 __ bind(L);
490 }
491
492
493 static void gen_c2i_adapter(MacroAssembler *masm,
494 int total_args_passed,
495 int comp_args_on_stack,
496 const BasicType *sig_bt,
497 const VMRegPair *regs,
498 Label& skip_fixup) {
499 // Before we get into the guts of the C2I adapter, see if we should be here
500 // at all. We've come from compiled code and are attempting to jump to the
501 // interpreter, which means the caller made a static call to get here
502 // (vcalls always get a compiled target if there is one). Check for a
503 // compiled target. If there is one, we need to patch the caller's call.
504 patch_callers_callsite(masm);
505
506 __ bind(skip_fixup);
507
508 // Since all args are passed on the stack, total_args_passed *
509 // Interpreter::stackElementSize is the space we need. Plus 1 because
510 // we also account for the return address location since
511 // we store it first rather than hold it in rax across all the shuffling
512
513 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
514
515 // stack is aligned, keep it that way
516 extraspace = round_to(extraspace, 2*wordSize);
517
518 // Get return address
519 __ pop(rax);
520
521 // set senderSP value
522 __ mov(r13, rsp);
523
524 __ subptr(rsp, extraspace);
525
526 // Store the return address in the expected location
527 __ movptr(Address(rsp, 0), rax);
528
529 // Now write the args into the outgoing interpreter space
530 for (int i = 0; i < total_args_passed; i++) {
531 if (sig_bt[i] == T_VOID) {
532 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
533 continue;
534 }
535
536 // offset to start parameters
537 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
538 int next_off = st_off - Interpreter::stackElementSize;
539
540 // Say 4 args:
541 // i st_off
542 // 0 32 T_LONG
543 // 1 24 T_VOID
544 // 2 16 T_OBJECT
545 // 3 8 T_BOOL
546 // - 0 return address
547 //
548 // However to make thing extra confusing. Because we can fit a long/double in
549 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
550 // leaves one slot empty and only stores to a single slot. In this case the
551 // slot that is occupied is the T_VOID slot. See I said it was confusing.
552
553 VMReg r_1 = regs[i].first();
554 VMReg r_2 = regs[i].second();
555 if (!r_1->is_valid()) {
556 assert(!r_2->is_valid(), "");
557 continue;
558 }
559 if (r_1->is_stack()) {
560 // memory to memory use rax
561 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
562 if (!r_2->is_valid()) {
563 // sign extend??
564 __ movl(rax, Address(rsp, ld_off));
565 __ movptr(Address(rsp, st_off), rax);
566
567 } else {
568
569 __ movq(rax, Address(rsp, ld_off));
570
571 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
572 // T_DOUBLE and T_LONG use two slots in the interpreter
573 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
574 // ld_off == LSW, ld_off+wordSize == MSW
575 // st_off == MSW, next_off == LSW
576 __ movq(Address(rsp, next_off), rax);
577 #ifdef ASSERT
578 // Overwrite the unused slot with known junk
579 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
580 __ movptr(Address(rsp, st_off), rax);
581 #endif /* ASSERT */
582 } else {
583 __ movq(Address(rsp, st_off), rax);
584 }
585 }
586 } else if (r_1->is_Register()) {
587 Register r = r_1->as_Register();
588 if (!r_2->is_valid()) {
589 // must be only an int (or less ) so move only 32bits to slot
590 // why not sign extend??
591 __ movl(Address(rsp, st_off), r);
592 } else {
593 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
594 // T_DOUBLE and T_LONG use two slots in the interpreter
595 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
596 // long/double in gpr
597 #ifdef ASSERT
598 // Overwrite the unused slot with known junk
599 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
600 __ movptr(Address(rsp, st_off), rax);
601 #endif /* ASSERT */
602 __ movq(Address(rsp, next_off), r);
603 } else {
604 __ movptr(Address(rsp, st_off), r);
605 }
606 }
607 } else {
608 assert(r_1->is_XMMRegister(), "");
609 if (!r_2->is_valid()) {
610 // only a float use just part of the slot
611 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
612 } else {
613 #ifdef ASSERT
614 // Overwrite the unused slot with known junk
615 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
616 __ movptr(Address(rsp, st_off), rax);
617 #endif /* ASSERT */
618 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
619 }
620 }
621 }
622
623 // Schedule the branch target address early.
624 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
625 __ jmp(rcx);
626 }
627
628 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
629 address code_start, address code_end,
630 Label& L_ok) {
631 Label L_fail;
632 __ lea(temp_reg, ExternalAddress(code_start));
633 __ cmpptr(pc_reg, temp_reg);
634 __ jcc(Assembler::belowEqual, L_fail);
635 __ lea(temp_reg, ExternalAddress(code_end));
636 __ cmpptr(pc_reg, temp_reg);
637 __ jcc(Assembler::below, L_ok);
638 __ bind(L_fail);
639 }
640
641 static void gen_i2c_adapter(MacroAssembler *masm,
642 int total_args_passed,
643 int comp_args_on_stack,
644 const BasicType *sig_bt,
645 const VMRegPair *regs) {
646
647 // Note: r13 contains the senderSP on entry. We must preserve it since
648 // we may do a i2c -> c2i transition if we lose a race where compiled
649 // code goes non-entrant while we get args ready.
650 // In addition we use r13 to locate all the interpreter args as
651 // we must align the stack to 16 bytes on an i2c entry else we
652 // lose alignment we expect in all compiled code and register
653 // save code can segv when fxsave instructions find improperly
654 // aligned stack pointer.
655
656 // Adapters can be frameless because they do not require the caller
657 // to perform additional cleanup work, such as correcting the stack pointer.
658 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
659 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
660 // even if a callee has modified the stack pointer.
661 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
662 // routinely repairs its caller's stack pointer (from sender_sp, which is set
663 // up via the senderSP register).
664 // In other words, if *either* the caller or callee is interpreted, we can
665 // get the stack pointer repaired after a call.
666 // This is why c2i and i2c adapters cannot be indefinitely composed.
667 // In particular, if a c2i adapter were to somehow call an i2c adapter,
668 // both caller and callee would be compiled methods, and neither would
669 // clean up the stack pointer changes performed by the two adapters.
670 // If this happens, control eventually transfers back to the compiled
671 // caller, but with an uncorrected stack, causing delayed havoc.
672
673 // Pick up the return address
674 __ movptr(rax, Address(rsp, 0));
675
676 if (VerifyAdapterCalls &&
677 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
678 // So, let's test for cascading c2i/i2c adapters right now.
679 // assert(Interpreter::contains($return_addr) ||
680 // StubRoutines::contains($return_addr),
681 // "i2c adapter must return to an interpreter frame");
682 __ block_comment("verify_i2c { ");
683 Label L_ok;
684 if (Interpreter::code() != NULL)
685 range_check(masm, rax, r11,
686 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
687 L_ok);
688 if (StubRoutines::code1() != NULL)
689 range_check(masm, rax, r11,
690 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
691 L_ok);
692 if (StubRoutines::code2() != NULL)
693 range_check(masm, rax, r11,
694 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
695 L_ok);
696 const char* msg = "i2c adapter must return to an interpreter frame";
697 __ block_comment(msg);
698 __ stop(msg);
699 __ bind(L_ok);
700 __ block_comment("} verify_i2ce ");
701 }
702
703 // Must preserve original SP for loading incoming arguments because
704 // we need to align the outgoing SP for compiled code.
705 __ movptr(r11, rsp);
706
707 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
708 // in registers, we will occasionally have no stack args.
709 int comp_words_on_stack = 0;
710 if (comp_args_on_stack) {
711 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
712 // registers are below. By subtracting stack0, we either get a negative
713 // number (all values in registers) or the maximum stack slot accessed.
714
715 // Convert 4-byte c2 stack slots to words.
716 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
717 // Round up to miminum stack alignment, in wordSize
718 comp_words_on_stack = round_to(comp_words_on_stack, 2);
719 __ subptr(rsp, comp_words_on_stack * wordSize);
720 }
721
722
723 // Ensure compiled code always sees stack at proper alignment
724 __ andptr(rsp, -16);
725
726 // push the return address and misalign the stack that youngest frame always sees
727 // as far as the placement of the call instruction
728 __ push(rax);
729
730 // Put saved SP in another register
731 const Register saved_sp = rax;
732 __ movptr(saved_sp, r11);
733
734 // Will jump to the compiled code just as if compiled code was doing it.
735 // Pre-load the register-jump target early, to schedule it better.
736 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
737
738 // Now generate the shuffle code. Pick up all register args and move the
739 // rest through the floating point stack top.
740 for (int i = 0; i < total_args_passed; i++) {
741 if (sig_bt[i] == T_VOID) {
742 // Longs and doubles are passed in native word order, but misaligned
743 // in the 32-bit build.
744 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
745 continue;
746 }
747
748 // Pick up 0, 1 or 2 words from SP+offset.
749
750 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
751 "scrambled load targets?");
752 // Load in argument order going down.
753 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
754 // Point to interpreter value (vs. tag)
755 int next_off = ld_off - Interpreter::stackElementSize;
756 //
757 //
758 //
759 VMReg r_1 = regs[i].first();
760 VMReg r_2 = regs[i].second();
761 if (!r_1->is_valid()) {
762 assert(!r_2->is_valid(), "");
763 continue;
764 }
765 if (r_1->is_stack()) {
766 // Convert stack slot to an SP offset (+ wordSize to account for return address )
767 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
768
769 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
770 // and if we end up going thru a c2i because of a miss a reasonable value of r13
771 // will be generated.
772 if (!r_2->is_valid()) {
773 // sign extend???
774 __ movl(r13, Address(saved_sp, ld_off));
775 __ movptr(Address(rsp, st_off), r13);
776 } else {
777 //
778 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
779 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
780 // So we must adjust where to pick up the data to match the interpreter.
781 //
782 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
783 // are accessed as negative so LSW is at LOW address
784
785 // ld_off is MSW so get LSW
786 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
787 next_off : ld_off;
788 __ movq(r13, Address(saved_sp, offset));
789 // st_off is LSW (i.e. reg.first())
790 __ movq(Address(rsp, st_off), r13);
791 }
792 } else if (r_1->is_Register()) { // Register argument
793 Register r = r_1->as_Register();
794 assert(r != rax, "must be different");
795 if (r_2->is_valid()) {
796 //
797 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
798 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
799 // So we must adjust where to pick up the data to match the interpreter.
800
801 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
802 next_off : ld_off;
803
804 // this can be a misaligned move
805 __ movq(r, Address(saved_sp, offset));
806 } else {
807 // sign extend and use a full word?
808 __ movl(r, Address(saved_sp, ld_off));
809 }
810 } else {
811 if (!r_2->is_valid()) {
812 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
813 } else {
814 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
815 }
816 }
817 }
818
819 // 6243940 We might end up in handle_wrong_method if
820 // the callee is deoptimized as we race thru here. If that
821 // happens we don't want to take a safepoint because the
822 // caller frame will look interpreted and arguments are now
823 // "compiled" so it is much better to make this transition
824 // invisible to the stack walking code. Unfortunately if
825 // we try and find the callee by normal means a safepoint
826 // is possible. So we stash the desired callee in the thread
827 // and the vm will find there should this case occur.
828
829 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
830
831 // put Method* where a c2i would expect should we end up there
832 // only needed becaus eof c2 resolve stubs return Method* as a result in
833 // rax
834 __ mov(rax, rbx);
835 __ jmp(r11);
836 }
837
838 // ---------------------------------------------------------------
839 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
840 int total_args_passed,
841 int comp_args_on_stack,
842 const BasicType *sig_bt,
843 const VMRegPair *regs,
844 AdapterFingerPrint* fingerprint) {
845 address i2c_entry = __ pc();
846
847 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
848
849 // -------------------------------------------------------------------------
850 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
851 // to the interpreter. The args start out packed in the compiled layout. They
852 // need to be unpacked into the interpreter layout. This will almost always
853 // require some stack space. We grow the current (compiled) stack, then repack
854 // the args. We finally end in a jump to the generic interpreter entry point.
855 // On exit from the interpreter, the interpreter will restore our SP (lest the
856 // compiled code, which relys solely on SP and not RBP, get sick).
857
858 address c2i_unverified_entry = __ pc();
859 Label skip_fixup;
860 Label ok;
861
862 Register holder = rax;
863 Register receiver = j_rarg0;
864 Register temp = rbx;
865
866 {
867 __ load_klass(temp, receiver);
868 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
869 __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset()));
870 __ jcc(Assembler::equal, ok);
871 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
872
873 __ bind(ok);
874 // Method might have been compiled since the call site was patched to
875 // interpreted if that is the case treat it as a miss so we can get
876 // the call site corrected.
877 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
878 __ jcc(Assembler::equal, skip_fixup);
879 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
880 }
881
882 address c2i_entry = __ pc();
883
884 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
885
886 __ flush();
887 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
888 }
889
890 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
891 VMRegPair *regs,
892 int total_args_passed) {
893 // We return the amount of VMRegImpl stack slots we need to reserve for all
894 // the arguments NOT counting out_preserve_stack_slots.
895
896 // NOTE: These arrays will have to change when c1 is ported
897 #ifdef _WIN64
898 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
899 c_rarg0, c_rarg1, c_rarg2, c_rarg3
900 };
901 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
902 c_farg0, c_farg1, c_farg2, c_farg3
903 };
904 #else
905 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
906 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
907 };
908 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
909 c_farg0, c_farg1, c_farg2, c_farg3,
910 c_farg4, c_farg5, c_farg6, c_farg7
911 };
912 #endif // _WIN64
913
914
915 uint int_args = 0;
916 uint fp_args = 0;
917 uint stk_args = 0; // inc by 2 each time
918
919 for (int i = 0; i < total_args_passed; i++) {
920 switch (sig_bt[i]) {
921 case T_BOOLEAN:
922 case T_CHAR:
923 case T_BYTE:
924 case T_SHORT:
925 case T_INT:
926 if (int_args < Argument::n_int_register_parameters_c) {
927 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
928 #ifdef _WIN64
929 fp_args++;
930 // Allocate slots for callee to stuff register args the stack.
931 stk_args += 2;
932 #endif
933 } else {
934 regs[i].set1(VMRegImpl::stack2reg(stk_args));
935 stk_args += 2;
936 }
937 break;
938 case T_LONG:
939 assert(sig_bt[i + 1] == T_VOID, "expecting half");
940 // fall through
941 case T_OBJECT:
942 case T_ARRAY:
943 case T_ADDRESS:
944 case T_METADATA:
945 if (int_args < Argument::n_int_register_parameters_c) {
946 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
947 #ifdef _WIN64
948 fp_args++;
949 stk_args += 2;
950 #endif
951 } else {
952 regs[i].set2(VMRegImpl::stack2reg(stk_args));
953 stk_args += 2;
954 }
955 break;
956 case T_FLOAT:
957 if (fp_args < Argument::n_float_register_parameters_c) {
958 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
959 #ifdef _WIN64
960 int_args++;
961 // Allocate slots for callee to stuff register args the stack.
962 stk_args += 2;
963 #endif
964 } else {
965 regs[i].set1(VMRegImpl::stack2reg(stk_args));
966 stk_args += 2;
967 }
968 break;
969 case T_DOUBLE:
970 assert(sig_bt[i + 1] == T_VOID, "expecting half");
971 if (fp_args < Argument::n_float_register_parameters_c) {
972 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
973 #ifdef _WIN64
974 int_args++;
975 // Allocate slots for callee to stuff register args the stack.
976 stk_args += 2;
977 #endif
978 } else {
979 regs[i].set2(VMRegImpl::stack2reg(stk_args));
980 stk_args += 2;
981 }
982 break;
983 case T_VOID: // Halves of longs and doubles
984 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
985 regs[i].set_bad();
986 break;
987 default:
988 ShouldNotReachHere();
989 break;
990 }
991 }
992 #ifdef _WIN64
993 // windows abi requires that we always allocate enough stack space
994 // for 4 64bit registers to be stored down.
995 if (stk_args < 8) {
996 stk_args = 8;
997 }
998 #endif // _WIN64
999
1000 return stk_args;
1001 }
1002
1003 // Do we need to convert ints to longs for c calls?
1004 bool SharedRuntime::c_calling_convention_requires_ints_as_longs() {
1005 return false;
1006 }
1007
1008 // On 64 bit we will store integer like items to the stack as
1009 // 64 bits items (sparc abi) even though java would only store
1010 // 32bits for a parameter. On 32bit it will simply be 32 bits
1011 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1012 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1013 if (src.first()->is_stack()) {
1014 if (dst.first()->is_stack()) {
1015 // stack to stack
1016 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
1017 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1018 } else {
1019 // stack to reg
1020 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1021 }
1022 } else if (dst.first()->is_stack()) {
1023 // reg to stack
1024 // Do we really have to sign extend???
1025 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1026 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1027 } else {
1028 // Do we really have to sign extend???
1029 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1030 if (dst.first() != src.first()) {
1031 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1032 }
1033 }
1034 }
1035
1036 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1037 if (src.first()->is_stack()) {
1038 if (dst.first()->is_stack()) {
1039 // stack to stack
1040 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1041 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1042 } else {
1043 // stack to reg
1044 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1045 }
1046 } else if (dst.first()->is_stack()) {
1047 // reg to stack
1048 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1049 } else {
1050 if (dst.first() != src.first()) {
1051 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1052 }
1053 }
1054 }
1055
1056 // An oop arg. Must pass a handle not the oop itself
1057 static void object_move(MacroAssembler* masm,
1058 OopMap* map,
1059 int oop_handle_offset,
1060 int framesize_in_slots,
1061 VMRegPair src,
1062 VMRegPair dst,
1063 bool is_receiver,
1064 int* receiver_offset) {
1065
1066 // must pass a handle. First figure out the location we use as a handle
1067
1068 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1069
1070 // See if oop is NULL if it is we need no handle
1071
1072 if (src.first()->is_stack()) {
1073
1074 // Oop is already on the stack as an argument
1075 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1076 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1077 if (is_receiver) {
1078 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1079 }
1080
1081 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1082 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1083 // conditionally move a NULL
1084 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1085 } else {
1086
1087 // Oop is in an a register we must store it to the space we reserve
1088 // on the stack for oop_handles and pass a handle if oop is non-NULL
1089
1090 const Register rOop = src.first()->as_Register();
1091 int oop_slot;
1092 if (rOop == j_rarg0)
1093 oop_slot = 0;
1094 else if (rOop == j_rarg1)
1095 oop_slot = 1;
1096 else if (rOop == j_rarg2)
1097 oop_slot = 2;
1098 else if (rOop == j_rarg3)
1099 oop_slot = 3;
1100 else if (rOop == j_rarg4)
1101 oop_slot = 4;
1102 else {
1103 assert(rOop == j_rarg5, "wrong register");
1104 oop_slot = 5;
1105 }
1106
1107 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1108 int offset = oop_slot*VMRegImpl::stack_slot_size;
1109
1110 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1111 // Store oop in handle area, may be NULL
1112 __ movptr(Address(rsp, offset), rOop);
1113 if (is_receiver) {
1114 *receiver_offset = offset;
1115 }
1116
1117 __ cmpptr(rOop, (int32_t)NULL_WORD);
1118 __ lea(rHandle, Address(rsp, offset));
1119 // conditionally move a NULL from the handle area where it was just stored
1120 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1121 }
1122
1123 // If arg is on the stack then place it otherwise it is already in correct reg.
1124 if (dst.first()->is_stack()) {
1125 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1126 }
1127 }
1128
1129 // A float arg may have to do float reg int reg conversion
1130 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1131 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1132
1133 // The calling conventions assures us that each VMregpair is either
1134 // all really one physical register or adjacent stack slots.
1135 // This greatly simplifies the cases here compared to sparc.
1136
1137 if (src.first()->is_stack()) {
1138 if (dst.first()->is_stack()) {
1139 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1140 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1141 } else {
1142 // stack to reg
1143 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1144 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1145 }
1146 } else if (dst.first()->is_stack()) {
1147 // reg to stack
1148 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1149 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1150 } else {
1151 // reg to reg
1152 // In theory these overlap but the ordering is such that this is likely a nop
1153 if ( src.first() != dst.first()) {
1154 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1155 }
1156 }
1157 }
1158
1159 // A long move
1160 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1161
1162 // The calling conventions assures us that each VMregpair is either
1163 // all really one physical register or adjacent stack slots.
1164 // This greatly simplifies the cases here compared to sparc.
1165
1166 if (src.is_single_phys_reg() ) {
1167 if (dst.is_single_phys_reg()) {
1168 if (dst.first() != src.first()) {
1169 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1170 }
1171 } else {
1172 assert(dst.is_single_reg(), "not a stack pair");
1173 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1174 }
1175 } else if (dst.is_single_phys_reg()) {
1176 assert(src.is_single_reg(), "not a stack pair");
1177 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1178 } else {
1179 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1180 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1181 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1182 }
1183 }
1184
1185 // A double move
1186 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1187
1188 // The calling conventions assures us that each VMregpair is either
1189 // all really one physical register or adjacent stack slots.
1190 // This greatly simplifies the cases here compared to sparc.
1191
1192 if (src.is_single_phys_reg() ) {
1193 if (dst.is_single_phys_reg()) {
1194 // In theory these overlap but the ordering is such that this is likely a nop
1195 if ( src.first() != dst.first()) {
1196 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1197 }
1198 } else {
1199 assert(dst.is_single_reg(), "not a stack pair");
1200 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1201 }
1202 } else if (dst.is_single_phys_reg()) {
1203 assert(src.is_single_reg(), "not a stack pair");
1204 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1205 } else {
1206 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1207 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1208 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1209 }
1210 }
1211
1212
1213 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1214 // We always ignore the frame_slots arg and just use the space just below frame pointer
1215 // which by this time is free to use
1216 switch (ret_type) {
1217 case T_FLOAT:
1218 __ movflt(Address(rbp, -wordSize), xmm0);
1219 break;
1220 case T_DOUBLE:
1221 __ movdbl(Address(rbp, -wordSize), xmm0);
1222 break;
1223 case T_VOID: break;
1224 default: {
1225 __ movptr(Address(rbp, -wordSize), rax);
1226 }
1227 }
1228 }
1229
1230 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1231 // We always ignore the frame_slots arg and just use the space just below frame pointer
1232 // which by this time is free to use
1233 switch (ret_type) {
1234 case T_FLOAT:
1235 __ movflt(xmm0, Address(rbp, -wordSize));
1236 break;
1237 case T_DOUBLE:
1238 __ movdbl(xmm0, Address(rbp, -wordSize));
1239 break;
1240 case T_VOID: break;
1241 default: {
1242 __ movptr(rax, Address(rbp, -wordSize));
1243 }
1244 }
1245 }
1246
1247 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1248 for ( int i = first_arg ; i < arg_count ; i++ ) {
1249 if (args[i].first()->is_Register()) {
1250 __ push(args[i].first()->as_Register());
1251 } else if (args[i].first()->is_XMMRegister()) {
1252 __ subptr(rsp, 2*wordSize);
1253 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1254 }
1255 }
1256 }
1257
1258 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1259 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1260 if (args[i].first()->is_Register()) {
1261 __ pop(args[i].first()->as_Register());
1262 } else if (args[i].first()->is_XMMRegister()) {
1263 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1264 __ addptr(rsp, 2*wordSize);
1265 }
1266 }
1267 }
1268
1269
1270 static void save_or_restore_arguments(MacroAssembler* masm,
1271 const int stack_slots,
1272 const int total_in_args,
1273 const int arg_save_area,
1274 OopMap* map,
1275 VMRegPair* in_regs,
1276 BasicType* in_sig_bt) {
1277 // if map is non-NULL then the code should store the values,
1278 // otherwise it should load them.
1279 int slot = arg_save_area;
1280 // Save down double word first
1281 for ( int i = 0; i < total_in_args; i++) {
1282 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1283 int offset = slot * VMRegImpl::stack_slot_size;
1284 slot += VMRegImpl::slots_per_word;
1285 assert(slot <= stack_slots, "overflow");
1286 if (map != NULL) {
1287 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1288 } else {
1289 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1290 }
1291 }
1292 if (in_regs[i].first()->is_Register() &&
1293 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
1294 int offset = slot * VMRegImpl::stack_slot_size;
1295 if (map != NULL) {
1296 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
1297 if (in_sig_bt[i] == T_ARRAY) {
1298 map->set_oop(VMRegImpl::stack2reg(slot));;
1299 }
1300 } else {
1301 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
1302 }
1303 slot += VMRegImpl::slots_per_word;
1304 }
1305 }
1306 // Save or restore single word registers
1307 for ( int i = 0; i < total_in_args; i++) {
1308 if (in_regs[i].first()->is_Register()) {
1309 int offset = slot * VMRegImpl::stack_slot_size;
1310 slot++;
1311 assert(slot <= stack_slots, "overflow");
1312
1313 // Value is in an input register pass we must flush it to the stack
1314 const Register reg = in_regs[i].first()->as_Register();
1315 switch (in_sig_bt[i]) {
1316 case T_BOOLEAN:
1317 case T_CHAR:
1318 case T_BYTE:
1319 case T_SHORT:
1320 case T_INT:
1321 if (map != NULL) {
1322 __ movl(Address(rsp, offset), reg);
1323 } else {
1324 __ movl(reg, Address(rsp, offset));
1325 }
1326 break;
1327 case T_ARRAY:
1328 case T_LONG:
1329 // handled above
1330 break;
1331 case T_OBJECT:
1332 default: ShouldNotReachHere();
1333 }
1334 } else if (in_regs[i].first()->is_XMMRegister()) {
1335 if (in_sig_bt[i] == T_FLOAT) {
1336 int offset = slot * VMRegImpl::stack_slot_size;
1337 slot++;
1338 assert(slot <= stack_slots, "overflow");
1339 if (map != NULL) {
1340 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1341 } else {
1342 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1343 }
1344 }
1345 } else if (in_regs[i].first()->is_stack()) {
1346 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1347 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1348 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1349 }
1350 }
1351 }
1352 }
1353
1354
1355 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1356 // keeps a new JNI critical region from starting until a GC has been
1357 // forced. Save down any oops in registers and describe them in an
1358 // OopMap.
1359 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1360 int stack_slots,
1361 int total_c_args,
1362 int total_in_args,
1363 int arg_save_area,
1364 OopMapSet* oop_maps,
1365 VMRegPair* in_regs,
1366 BasicType* in_sig_bt) {
1367 __ block_comment("check GC_locker::needs_gc");
1368 Label cont;
1369 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
1370 __ jcc(Assembler::equal, cont);
1371
1372 // Save down any incoming oops and call into the runtime to halt for a GC
1373
1374 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1375 save_or_restore_arguments(masm, stack_slots, total_in_args,
1376 arg_save_area, map, in_regs, in_sig_bt);
1377
1378 address the_pc = __ pc();
1379 oop_maps->add_gc_map( __ offset(), map);
1380 __ set_last_Java_frame(rsp, noreg, the_pc);
1381
1382 __ block_comment("block_for_jni_critical");
1383 __ movptr(c_rarg0, r15_thread);
1384 __ mov(r12, rsp); // remember sp
1385 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1386 __ andptr(rsp, -16); // align stack as required by ABI
1387 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1388 __ mov(rsp, r12); // restore sp
1389 __ reinit_heapbase();
1390
1391 __ reset_last_Java_frame(false, true);
1392
1393 save_or_restore_arguments(masm, stack_slots, total_in_args,
1394 arg_save_area, NULL, in_regs, in_sig_bt);
1395
1396 __ bind(cont);
1397 #ifdef ASSERT
1398 if (StressCriticalJNINatives) {
1399 // Stress register saving
1400 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1401 save_or_restore_arguments(masm, stack_slots, total_in_args,
1402 arg_save_area, map, in_regs, in_sig_bt);
1403 // Destroy argument registers
1404 for (int i = 0; i < total_in_args - 1; i++) {
1405 if (in_regs[i].first()->is_Register()) {
1406 const Register reg = in_regs[i].first()->as_Register();
1407 __ xorptr(reg, reg);
1408 } else if (in_regs[i].first()->is_XMMRegister()) {
1409 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1410 } else if (in_regs[i].first()->is_FloatRegister()) {
1411 ShouldNotReachHere();
1412 } else if (in_regs[i].first()->is_stack()) {
1413 // Nothing to do
1414 } else {
1415 ShouldNotReachHere();
1416 }
1417 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1418 i++;
1419 }
1420 }
1421
1422 save_or_restore_arguments(masm, stack_slots, total_in_args,
1423 arg_save_area, NULL, in_regs, in_sig_bt);
1424 }
1425 #endif
1426 }
1427
1428 // Unpack an array argument into a pointer to the body and the length
1429 // if the array is non-null, otherwise pass 0 for both.
1430 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1431 Register tmp_reg = rax;
1432 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1433 "possible collision");
1434 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1435 "possible collision");
1436
1437 __ block_comment("unpack_array_argument {");
1438
1439 // Pass the length, ptr pair
1440 Label is_null, done;
1441 VMRegPair tmp;
1442 tmp.set_ptr(tmp_reg->as_VMReg());
1443 if (reg.first()->is_stack()) {
1444 // Load the arg up from the stack
1445 move_ptr(masm, reg, tmp);
1446 reg = tmp;
1447 }
1448 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1449 __ jccb(Assembler::equal, is_null);
1450 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1451 move_ptr(masm, tmp, body_arg);
1452 // load the length relative to the body.
1453 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1454 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1455 move32_64(masm, tmp, length_arg);
1456 __ jmpb(done);
1457 __ bind(is_null);
1458 // Pass zeros
1459 __ xorptr(tmp_reg, tmp_reg);
1460 move_ptr(masm, tmp, body_arg);
1461 move32_64(masm, tmp, length_arg);
1462 __ bind(done);
1463
1464 __ block_comment("} unpack_array_argument");
1465 }
1466
1467
1468 // Different signatures may require very different orders for the move
1469 // to avoid clobbering other arguments. There's no simple way to
1470 // order them safely. Compute a safe order for issuing stores and
1471 // break any cycles in those stores. This code is fairly general but
1472 // it's not necessary on the other platforms so we keep it in the
1473 // platform dependent code instead of moving it into a shared file.
1474 // (See bugs 7013347 & 7145024.)
1475 // Note that this code is specific to LP64.
1476 class ComputeMoveOrder: public StackObj {
1477 class MoveOperation: public ResourceObj {
1478 friend class ComputeMoveOrder;
1479 private:
1480 VMRegPair _src;
1481 VMRegPair _dst;
1482 int _src_index;
1483 int _dst_index;
1484 bool _processed;
1485 MoveOperation* _next;
1486 MoveOperation* _prev;
1487
1488 static int get_id(VMRegPair r) {
1489 return r.first()->value();
1490 }
1491
1492 public:
1493 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst):
1494 _src(src)
1495 , _src_index(src_index)
1496 , _dst(dst)
1497 , _dst_index(dst_index)
1498 , _next(NULL)
1499 , _prev(NULL)
1500 , _processed(false) {
1501 }
1502
1503 VMRegPair src() const { return _src; }
1504 int src_id() const { return get_id(src()); }
1505 int src_index() const { return _src_index; }
1506 VMRegPair dst() const { return _dst; }
1507 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; }
1508 int dst_index() const { return _dst_index; }
1509 int dst_id() const { return get_id(dst()); }
1510 MoveOperation* next() const { return _next; }
1511 MoveOperation* prev() const { return _prev; }
1512 void set_processed() { _processed = true; }
1513 bool is_processed() const { return _processed; }
1514
1515 // insert
1516 void break_cycle(VMRegPair temp_register) {
1517 // create a new store following the last store
1518 // to move from the temp_register to the original
1519 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst());
1520
1521 // break the cycle of links and insert new_store at the end
1522 // break the reverse link.
1523 MoveOperation* p = prev();
1524 assert(p->next() == this, "must be");
1525 _prev = NULL;
1526 p->_next = new_store;
1527 new_store->_prev = p;
1528
1529 // change the original store to save it's value in the temp.
1530 set_dst(-1, temp_register);
1531 }
1532
1533 void link(GrowableArray<MoveOperation*>& killer) {
1534 // link this store in front the store that it depends on
1535 MoveOperation* n = killer.at_grow(src_id(), NULL);
1536 if (n != NULL) {
1537 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet");
1538 _next = n;
1539 n->_prev = this;
1540 }
1541 }
1542 };
1543
1544 private:
1545 GrowableArray<MoveOperation*> edges;
1546
1547 public:
1548 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs,
1549 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) {
1550 // Move operations where the dest is the stack can all be
1551 // scheduled first since they can't interfere with the other moves.
1552 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
1553 if (in_sig_bt[i] == T_ARRAY) {
1554 c_arg--;
1555 if (out_regs[c_arg].first()->is_stack() &&
1556 out_regs[c_arg + 1].first()->is_stack()) {
1557 arg_order.push(i);
1558 arg_order.push(c_arg);
1559 } else {
1560 if (out_regs[c_arg].first()->is_stack() ||
1561 in_regs[i].first() == out_regs[c_arg].first()) {
1562 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]);
1563 } else {
1564 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1565 }
1566 }
1567 } else if (in_sig_bt[i] == T_VOID) {
1568 arg_order.push(i);
1569 arg_order.push(c_arg);
1570 } else {
1571 if (out_regs[c_arg].first()->is_stack() ||
1572 in_regs[i].first() == out_regs[c_arg].first()) {
1573 arg_order.push(i);
1574 arg_order.push(c_arg);
1575 } else {
1576 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1577 }
1578 }
1579 }
1580 // Break any cycles in the register moves and emit the in the
1581 // proper order.
1582 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg);
1583 for (int i = 0; i < stores->length(); i++) {
1584 arg_order.push(stores->at(i)->src_index());
1585 arg_order.push(stores->at(i)->dst_index());
1586 }
1587 }
1588
1589 // Collected all the move operations
1590 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) {
1591 if (src.first() == dst.first()) return;
1592 edges.append(new MoveOperation(src_index, src, dst_index, dst));
1593 }
1594
1595 // Walk the edges breaking cycles between moves. The result list
1596 // can be walked in order to produce the proper set of loads
1597 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) {
1598 // Record which moves kill which values
1599 GrowableArray<MoveOperation*> killer;
1600 for (int i = 0; i < edges.length(); i++) {
1601 MoveOperation* s = edges.at(i);
1602 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer");
1603 killer.at_put_grow(s->dst_id(), s, NULL);
1604 }
1605 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL,
1606 "make sure temp isn't in the registers that are killed");
1607
1608 // create links between loads and stores
1609 for (int i = 0; i < edges.length(); i++) {
1610 edges.at(i)->link(killer);
1611 }
1612
1613 // at this point, all the move operations are chained together
1614 // in a doubly linked list. Processing it backwards finds
1615 // the beginning of the chain, forwards finds the end. If there's
1616 // a cycle it can be broken at any point, so pick an edge and walk
1617 // backward until the list ends or we end where we started.
1618 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>();
1619 for (int e = 0; e < edges.length(); e++) {
1620 MoveOperation* s = edges.at(e);
1621 if (!s->is_processed()) {
1622 MoveOperation* start = s;
1623 // search for the beginning of the chain or cycle
1624 while (start->prev() != NULL && start->prev() != s) {
1625 start = start->prev();
1626 }
1627 if (start->prev() == s) {
1628 start->break_cycle(temp_register);
1629 }
1630 // walk the chain forward inserting to store list
1631 while (start != NULL) {
1632 stores->append(start);
1633 start->set_processed();
1634 start = start->next();
1635 }
1636 }
1637 }
1638 return stores;
1639 }
1640 };
1641
1642 static void verify_oop_args(MacroAssembler* masm,
1643 methodHandle method,
1644 const BasicType* sig_bt,
1645 const VMRegPair* regs) {
1646 Register temp_reg = rbx; // not part of any compiled calling seq
1647 if (VerifyOops) {
1648 for (int i = 0; i < method->size_of_parameters(); i++) {
1649 if (sig_bt[i] == T_OBJECT ||
1650 sig_bt[i] == T_ARRAY) {
1651 VMReg r = regs[i].first();
1652 assert(r->is_valid(), "bad oop arg");
1653 if (r->is_stack()) {
1654 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1655 __ verify_oop(temp_reg);
1656 } else {
1657 __ verify_oop(r->as_Register());
1658 }
1659 }
1660 }
1661 }
1662 }
1663
1664 static void gen_special_dispatch(MacroAssembler* masm,
1665 methodHandle method,
1666 const BasicType* sig_bt,
1667 const VMRegPair* regs) {
1668 verify_oop_args(masm, method, sig_bt, regs);
1669 vmIntrinsics::ID iid = method->intrinsic_id();
1670
1671 // Now write the args into the outgoing interpreter space
1672 bool has_receiver = false;
1673 Register receiver_reg = noreg;
1674 int member_arg_pos = -1;
1675 Register member_reg = noreg;
1676 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1677 if (ref_kind != 0) {
1678 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1679 member_reg = rbx; // known to be free at this point
1680 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1681 } else if (iid == vmIntrinsics::_invokeBasic) {
1682 has_receiver = true;
1683 } else {
1684 fatal(err_msg_res("unexpected intrinsic id %d", iid));
1685 }
1686
1687 if (member_reg != noreg) {
1688 // Load the member_arg into register, if necessary.
1689 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1690 VMReg r = regs[member_arg_pos].first();
1691 if (r->is_stack()) {
1692 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1693 } else {
1694 // no data motion is needed
1695 member_reg = r->as_Register();
1696 }
1697 }
1698
1699 if (has_receiver) {
1700 // Make sure the receiver is loaded into a register.
1701 assert(method->size_of_parameters() > 0, "oob");
1702 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1703 VMReg r = regs[0].first();
1704 assert(r->is_valid(), "bad receiver arg");
1705 if (r->is_stack()) {
1706 // Porting note: This assumes that compiled calling conventions always
1707 // pass the receiver oop in a register. If this is not true on some
1708 // platform, pick a temp and load the receiver from stack.
1709 fatal("receiver always in a register");
1710 receiver_reg = j_rarg0; // known to be free at this point
1711 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1712 } else {
1713 // no data motion is needed
1714 receiver_reg = r->as_Register();
1715 }
1716 }
1717
1718 // Figure out which address we are really jumping to:
1719 MethodHandles::generate_method_handle_dispatch(masm, iid,
1720 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1721 }
1722
1723 // ---------------------------------------------------------------------------
1724 // Generate a native wrapper for a given method. The method takes arguments
1725 // in the Java compiled code convention, marshals them to the native
1726 // convention (handlizes oops, etc), transitions to native, makes the call,
1727 // returns to java state (possibly blocking), unhandlizes any result and
1728 // returns.
1729 //
1730 // Critical native functions are a shorthand for the use of
1731 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1732 // functions. The wrapper is expected to unpack the arguments before
1733 // passing them to the callee and perform checks before and after the
1734 // native call to ensure that they GC_locker
1735 // lock_critical/unlock_critical semantics are followed. Some other
1736 // parts of JNI setup are skipped like the tear down of the JNI handle
1737 // block and the check for pending exceptions it's impossible for them
1738 // to be thrown.
1739 //
1740 // They are roughly structured like this:
1741 // if (GC_locker::needs_gc())
1742 // SharedRuntime::block_for_jni_critical();
1743 // tranistion to thread_in_native
1744 // unpack arrray arguments and call native entry point
1745 // check for safepoint in progress
1746 // check if any thread suspend flags are set
1747 // call into JVM and possible unlock the JNI critical
1748 // if a GC was suppressed while in the critical native.
1749 // transition back to thread_in_Java
1750 // return to caller
1751 //
1752 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1753 methodHandle method,
1754 int compile_id,
1755 BasicType* in_sig_bt,
1756 VMRegPair* in_regs,
1757 BasicType ret_type) {
1758 if (method->is_method_handle_intrinsic()) {
1759 vmIntrinsics::ID iid = method->intrinsic_id();
1760 intptr_t start = (intptr_t)__ pc();
1761 int vep_offset = ((intptr_t)__ pc()) - start;
1762 gen_special_dispatch(masm,
1763 method,
1764 in_sig_bt,
1765 in_regs);
1766 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1767 __ flush();
1768 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1769 return nmethod::new_native_nmethod(method,
1770 compile_id,
1771 masm->code(),
1772 vep_offset,
1773 frame_complete,
1774 stack_slots / VMRegImpl::slots_per_word,
1775 in_ByteSize(-1),
1776 in_ByteSize(-1),
1777 (OopMapSet*)NULL);
1778 }
1779 bool is_critical_native = true;
1780 address native_func = method->critical_native_function();
1781 if (native_func == NULL) {
1782 native_func = method->native_function();
1783 is_critical_native = false;
1784 }
1785 assert(native_func != NULL, "must have function");
1786
1787 // An OopMap for lock (and class if static)
1788 OopMapSet *oop_maps = new OopMapSet();
1789 intptr_t start = (intptr_t)__ pc();
1790
1791 // We have received a description of where all the java arg are located
1792 // on entry to the wrapper. We need to convert these args to where
1793 // the jni function will expect them. To figure out where they go
1794 // we convert the java signature to a C signature by inserting
1795 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1796
1797 const int total_in_args = method->size_of_parameters();
1798 int total_c_args = total_in_args;
1799 if (!is_critical_native) {
1800 total_c_args += 1;
1801 if (method->is_static()) {
1802 total_c_args++;
1803 }
1804 } else {
1805 for (int i = 0; i < total_in_args; i++) {
1806 if (in_sig_bt[i] == T_ARRAY) {
1807 total_c_args++;
1808 }
1809 }
1810 }
1811
1812 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1813 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1814 BasicType* in_elem_bt = NULL;
1815
1816 int argc = 0;
1817 if (!is_critical_native) {
1818 out_sig_bt[argc++] = T_ADDRESS;
1819 if (method->is_static()) {
1820 out_sig_bt[argc++] = T_OBJECT;
1821 }
1822
1823 for (int i = 0; i < total_in_args ; i++ ) {
1824 out_sig_bt[argc++] = in_sig_bt[i];
1825 }
1826 } else {
1827 Thread* THREAD = Thread::current();
1828 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1829 SignatureStream ss(method->signature());
1830 for (int i = 0; i < total_in_args ; i++ ) {
1831 if (in_sig_bt[i] == T_ARRAY) {
1832 // Arrays are passed as int, elem* pair
1833 out_sig_bt[argc++] = T_INT;
1834 out_sig_bt[argc++] = T_ADDRESS;
1835 Symbol* atype = ss.as_symbol(CHECK_NULL);
1836 const char* at = atype->as_C_string();
1837 if (strlen(at) == 2) {
1838 assert(at[0] == '[', "must be");
1839 switch (at[1]) {
1840 case 'B': in_elem_bt[i] = T_BYTE; break;
1841 case 'C': in_elem_bt[i] = T_CHAR; break;
1842 case 'D': in_elem_bt[i] = T_DOUBLE; break;
1843 case 'F': in_elem_bt[i] = T_FLOAT; break;
1844 case 'I': in_elem_bt[i] = T_INT; break;
1845 case 'J': in_elem_bt[i] = T_LONG; break;
1846 case 'S': in_elem_bt[i] = T_SHORT; break;
1847 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
1848 default: ShouldNotReachHere();
1849 }
1850 }
1851 } else {
1852 out_sig_bt[argc++] = in_sig_bt[i];
1853 in_elem_bt[i] = T_VOID;
1854 }
1855 if (in_sig_bt[i] != T_VOID) {
1856 assert(in_sig_bt[i] == ss.type(), "must match");
1857 ss.next();
1858 }
1859 }
1860 }
1861
1862 // Now figure out where the args must be stored and how much stack space
1863 // they require.
1864 int out_arg_slots;
1865 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1866
1867 // Compute framesize for the wrapper. We need to handlize all oops in
1868 // incoming registers
1869
1870 // Calculate the total number of stack slots we will need.
1871
1872 // First count the abi requirement plus all of the outgoing args
1873 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1874
1875 // Now the space for the inbound oop handle area
1876 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
1877 if (is_critical_native) {
1878 // Critical natives may have to call out so they need a save area
1879 // for register arguments.
1880 int double_slots = 0;
1881 int single_slots = 0;
1882 for ( int i = 0; i < total_in_args; i++) {
1883 if (in_regs[i].first()->is_Register()) {
1884 const Register reg = in_regs[i].first()->as_Register();
1885 switch (in_sig_bt[i]) {
1886 case T_BOOLEAN:
1887 case T_BYTE:
1888 case T_SHORT:
1889 case T_CHAR:
1890 case T_INT: single_slots++; break;
1891 case T_ARRAY: // specific to LP64 (7145024)
1892 case T_LONG: double_slots++; break;
1893 default: ShouldNotReachHere();
1894 }
1895 } else if (in_regs[i].first()->is_XMMRegister()) {
1896 switch (in_sig_bt[i]) {
1897 case T_FLOAT: single_slots++; break;
1898 case T_DOUBLE: double_slots++; break;
1899 default: ShouldNotReachHere();
1900 }
1901 } else if (in_regs[i].first()->is_FloatRegister()) {
1902 ShouldNotReachHere();
1903 }
1904 }
1905 total_save_slots = double_slots * 2 + single_slots;
1906 // align the save area
1907 if (double_slots != 0) {
1908 stack_slots = round_to(stack_slots, 2);
1909 }
1910 }
1911
1912 int oop_handle_offset = stack_slots;
1913 stack_slots += total_save_slots;
1914
1915 // Now any space we need for handlizing a klass if static method
1916
1917 int klass_slot_offset = 0;
1918 int klass_offset = -1;
1919 int lock_slot_offset = 0;
1920 bool is_static = false;
1921
1922 if (method->is_static()) {
1923 klass_slot_offset = stack_slots;
1924 stack_slots += VMRegImpl::slots_per_word;
1925 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1926 is_static = true;
1927 }
1928
1929 // Plus a lock if needed
1930
1931 if (method->is_synchronized()) {
1932 lock_slot_offset = stack_slots;
1933 stack_slots += VMRegImpl::slots_per_word;
1934 }
1935
1936 // Now a place (+2) to save return values or temp during shuffling
1937 // + 4 for return address (which we own) and saved rbp
1938 stack_slots += 6;
1939
1940 // Ok The space we have allocated will look like:
1941 //
1942 //
1943 // FP-> | |
1944 // |---------------------|
1945 // | 2 slots for moves |
1946 // |---------------------|
1947 // | lock box (if sync) |
1948 // |---------------------| <- lock_slot_offset
1949 // | klass (if static) |
1950 // |---------------------| <- klass_slot_offset
1951 // | oopHandle area |
1952 // |---------------------| <- oop_handle_offset (6 java arg registers)
1953 // | outbound memory |
1954 // | based arguments |
1955 // | |
1956 // |---------------------|
1957 // | |
1958 // SP-> | out_preserved_slots |
1959 //
1960 //
1961
1962
1963 // Now compute actual number of stack words we need rounding to make
1964 // stack properly aligned.
1965 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1966
1967 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1968
1969 // First thing make an ic check to see if we should even be here
1970
1971 // We are free to use all registers as temps without saving them and
1972 // restoring them except rbp. rbp is the only callee save register
1973 // as far as the interpreter and the compiler(s) are concerned.
1974
1975
1976 const Register ic_reg = rax;
1977 const Register receiver = j_rarg0;
1978
1979 Label hit;
1980 Label exception_pending;
1981
1982 assert_different_registers(ic_reg, receiver, rscratch1);
1983 __ verify_oop(receiver);
1984 __ load_klass(rscratch1, receiver);
1985 __ cmpq(ic_reg, rscratch1);
1986 __ jcc(Assembler::equal, hit);
1987
1988 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1989
1990 // Verified entry point must be aligned
1991 __ align(8);
1992
1993 __ bind(hit);
1994
1995 int vep_offset = ((intptr_t)__ pc()) - start;
1996
1997 // The instruction at the verified entry point must be 5 bytes or longer
1998 // because it can be patched on the fly by make_non_entrant. The stack bang
1999 // instruction fits that requirement.
2000
2001 // Generate stack overflow check
2002
2003 if (UseStackBanging) {
2004 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2005 } else {
2006 // need a 5 byte instruction to allow MT safe patching to non-entrant
2007 __ fat_nop();
2008 }
2009
2010 // Generate a new frame for the wrapper.
2011 __ enter();
2012 // -2 because return address is already present and so is saved rbp
2013 __ subptr(rsp, stack_size - 2*wordSize);
2014
2015 // Frame is now completed as far as size and linkage.
2016 int frame_complete = ((intptr_t)__ pc()) - start;
2017
2018 #ifdef ASSERT
2019 {
2020 Label L;
2021 __ mov(rax, rsp);
2022 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
2023 __ cmpptr(rax, rsp);
2024 __ jcc(Assembler::equal, L);
2025 __ stop("improperly aligned stack");
2026 __ bind(L);
2027 }
2028 #endif /* ASSERT */
2029
2030
2031 // We use r14 as the oop handle for the receiver/klass
2032 // It is callee save so it survives the call to native
2033
2034 const Register oop_handle_reg = r14;
2035
2036 if (is_critical_native) {
2037 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
2038 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
2039 }
2040
2041 //
2042 // We immediately shuffle the arguments so that any vm call we have to
2043 // make from here on out (sync slow path, jvmti, etc.) we will have
2044 // captured the oops from our caller and have a valid oopMap for
2045 // them.
2046
2047 // -----------------
2048 // The Grand Shuffle
2049
2050 // The Java calling convention is either equal (linux) or denser (win64) than the
2051 // c calling convention. However the because of the jni_env argument the c calling
2052 // convention always has at least one more (and two for static) arguments than Java.
2053 // Therefore if we move the args from java -> c backwards then we will never have
2054 // a register->register conflict and we don't have to build a dependency graph
2055 // and figure out how to break any cycles.
2056 //
2057
2058 // Record esp-based slot for receiver on stack for non-static methods
2059 int receiver_offset = -1;
2060
2061 // This is a trick. We double the stack slots so we can claim
2062 // the oops in the caller's frame. Since we are sure to have
2063 // more args than the caller doubling is enough to make
2064 // sure we can capture all the incoming oop args from the
2065 // caller.
2066 //
2067 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2068
2069 // Mark location of rbp (someday)
2070 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
2071
2072 // Use eax, ebx as temporaries during any memory-memory moves we have to do
2073 // All inbound args are referenced based on rbp and all outbound args via rsp.
2074
2075
2076 #ifdef ASSERT
2077 bool reg_destroyed[RegisterImpl::number_of_registers];
2078 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
2079 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2080 reg_destroyed[r] = false;
2081 }
2082 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
2083 freg_destroyed[f] = false;
2084 }
2085
2086 #endif /* ASSERT */
2087
2088 // This may iterate in two different directions depending on the
2089 // kind of native it is. The reason is that for regular JNI natives
2090 // the incoming and outgoing registers are offset upwards and for
2091 // critical natives they are offset down.
2092 GrowableArray<int> arg_order(2 * total_in_args);
2093 VMRegPair tmp_vmreg;
2094 tmp_vmreg.set1(rbx->as_VMReg());
2095
2096 if (!is_critical_native) {
2097 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
2098 arg_order.push(i);
2099 arg_order.push(c_arg);
2100 }
2101 } else {
2102 // Compute a valid move order, using tmp_vmreg to break any cycles
2103 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg);
2104 }
2105
2106 int temploc = -1;
2107 for (int ai = 0; ai < arg_order.length(); ai += 2) {
2108 int i = arg_order.at(ai);
2109 int c_arg = arg_order.at(ai + 1);
2110 __ block_comment(err_msg("move %d -> %d", i, c_arg));
2111 if (c_arg == -1) {
2112 assert(is_critical_native, "should only be required for critical natives");
2113 // This arg needs to be moved to a temporary
2114 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register());
2115 in_regs[i] = tmp_vmreg;
2116 temploc = i;
2117 continue;
2118 } else if (i == -1) {
2119 assert(is_critical_native, "should only be required for critical natives");
2120 // Read from the temporary location
2121 assert(temploc != -1, "must be valid");
2122 i = temploc;
2123 temploc = -1;
2124 }
2125 #ifdef ASSERT
2126 if (in_regs[i].first()->is_Register()) {
2127 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
2128 } else if (in_regs[i].first()->is_XMMRegister()) {
2129 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
2130 }
2131 if (out_regs[c_arg].first()->is_Register()) {
2132 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2133 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2134 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2135 }
2136 #endif /* ASSERT */
2137 switch (in_sig_bt[i]) {
2138 case T_ARRAY:
2139 if (is_critical_native) {
2140 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
2141 c_arg++;
2142 #ifdef ASSERT
2143 if (out_regs[c_arg].first()->is_Register()) {
2144 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2145 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2146 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2147 }
2148 #endif
2149 break;
2150 }
2151 case T_OBJECT:
2152 assert(!is_critical_native, "no oop arguments");
2153 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2154 ((i == 0) && (!is_static)),
2155 &receiver_offset);
2156 break;
2157 case T_VOID:
2158 break;
2159
2160 case T_FLOAT:
2161 float_move(masm, in_regs[i], out_regs[c_arg]);
2162 break;
2163
2164 case T_DOUBLE:
2165 assert( i + 1 < total_in_args &&
2166 in_sig_bt[i + 1] == T_VOID &&
2167 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2168 double_move(masm, in_regs[i], out_regs[c_arg]);
2169 break;
2170
2171 case T_LONG :
2172 long_move(masm, in_regs[i], out_regs[c_arg]);
2173 break;
2174
2175 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2176
2177 default:
2178 move32_64(masm, in_regs[i], out_regs[c_arg]);
2179 }
2180 }
2181
2182 int c_arg;
2183
2184 // Pre-load a static method's oop into r14. Used both by locking code and
2185 // the normal JNI call code.
2186 if (!is_critical_native) {
2187 // point c_arg at the first arg that is already loaded in case we
2188 // need to spill before we call out
2189 c_arg = total_c_args - total_in_args;
2190
2191 if (method->is_static()) {
2192
2193 // load oop into a register
2194 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror()));
2195
2196 // Now handlize the static class mirror it's known not-null.
2197 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
2198 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2199
2200 // Now get the handle
2201 __ lea(oop_handle_reg, Address(rsp, klass_offset));
2202 // store the klass handle as second argument
2203 __ movptr(c_rarg1, oop_handle_reg);
2204 // and protect the arg if we must spill
2205 c_arg--;
2206 }
2207 } else {
2208 // For JNI critical methods we need to save all registers in save_args.
2209 c_arg = 0;
2210 }
2211
2212 // Change state to native (we save the return address in the thread, since it might not
2213 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
2214 // points into the right code segment. It does not have to be the correct return pc.
2215 // We use the same pc/oopMap repeatedly when we call out
2216
2217 intptr_t the_pc = (intptr_t) __ pc();
2218 oop_maps->add_gc_map(the_pc - start, map);
2219
2220 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
2221
2222
2223 // We have all of the arguments setup at this point. We must not touch any register
2224 // argument registers at this point (what if we save/restore them there are no oop?
2225
2226 {
2227 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2228 // protect the args we've loaded
2229 save_args(masm, total_c_args, c_arg, out_regs);
2230 __ mov_metadata(c_rarg1, method());
2231 __ call_VM_leaf(
2232 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2233 r15_thread, c_rarg1);
2234 restore_args(masm, total_c_args, c_arg, out_regs);
2235 }
2236
2237 // RedefineClasses() tracing support for obsolete method entry
2238 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2239 // protect the args we've loaded
2240 save_args(masm, total_c_args, c_arg, out_regs);
2241 __ mov_metadata(c_rarg1, method());
2242 __ call_VM_leaf(
2243 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2244 r15_thread, c_rarg1);
2245 restore_args(masm, total_c_args, c_arg, out_regs);
2246 }
2247
2248 // Lock a synchronized method
2249
2250 // Register definitions used by locking and unlocking
2251
2252 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
2253 const Register obj_reg = rbx; // Will contain the oop
2254 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
2255 const Register old_hdr = r13; // value of old header at unlock time
2256
2257 Label slow_path_lock;
2258 Label lock_done;
2259
2260 if (method->is_synchronized()) {
2261 assert(!is_critical_native, "unhandled");
2262
2263
2264 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2265
2266 // Get the handle (the 2nd argument)
2267 __ mov(oop_handle_reg, c_rarg1);
2268
2269 // Get address of the box
2270
2271 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2272
2273 // Load the oop from the handle
2274 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2275
2276 if (UseBiasedLocking) {
2277 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
2278 }
2279
2280 // Load immediate 1 into swap_reg %rax
2281 __ movl(swap_reg, 1);
2282
2283 // Load (object->mark() | 1) into swap_reg %rax
2284 __ orptr(swap_reg, Address(obj_reg, 0));
2285
2286 // Save (object->mark() | 1) into BasicLock's displaced header
2287 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2288
2289 if (os::is_MP()) {
2290 __ lock();
2291 }
2292
2293 // src -> dest iff dest == rax else rax <- dest
2294 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
2295 __ jcc(Assembler::equal, lock_done);
2296
2297 // Hmm should this move to the slow path code area???
2298
2299 // Test if the oopMark is an obvious stack pointer, i.e.,
2300 // 1) (mark & 3) == 0, and
2301 // 2) rsp <= mark < mark + os::pagesize()
2302 // These 3 tests can be done by evaluating the following
2303 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2304 // assuming both stack pointer and pagesize have their
2305 // least significant 2 bits clear.
2306 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2307
2308 __ subptr(swap_reg, rsp);
2309 __ andptr(swap_reg, 3 - os::vm_page_size());
2310
2311 // Save the test result, for recursive case, the result is zero
2312 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2313 __ jcc(Assembler::notEqual, slow_path_lock);
2314
2315 // Slow path will re-enter here
2316
2317 __ bind(lock_done);
2318 }
2319
2320
2321 // Finally just about ready to make the JNI call
2322
2323
2324 // get JNIEnv* which is first argument to native
2325 if (!is_critical_native) {
2326 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
2327 }
2328
2329 // Now set thread in native
2330 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2331
2332 __ call(RuntimeAddress(native_func));
2333
2334 // Verify or restore cpu control state after JNI call
2335 __ restore_cpu_control_state_after_jni();
2336
2337 // Unpack native results.
2338 switch (ret_type) {
2339 case T_BOOLEAN: __ c2bool(rax); break;
2340 case T_CHAR : __ movzwl(rax, rax); break;
2341 case T_BYTE : __ sign_extend_byte (rax); break;
2342 case T_SHORT : __ sign_extend_short(rax); break;
2343 case T_INT : /* nothing to do */ break;
2344 case T_DOUBLE :
2345 case T_FLOAT :
2346 // Result is in xmm0 we'll save as needed
2347 break;
2348 case T_ARRAY: // Really a handle
2349 case T_OBJECT: // Really a handle
2350 break; // can't de-handlize until after safepoint check
2351 case T_VOID: break;
2352 case T_LONG: break;
2353 default : ShouldNotReachHere();
2354 }
2355
2356 // Switch thread to "native transition" state before reading the synchronization state.
2357 // This additional state is necessary because reading and testing the synchronization
2358 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2359 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2360 // VM thread changes sync state to synchronizing and suspends threads for GC.
2361 // Thread A is resumed to finish this native method, but doesn't block here since it
2362 // didn't see any synchronization is progress, and escapes.
2363 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2364
2365 if(os::is_MP()) {
2366 if (UseMembar) {
2367 // Force this write out before the read below
2368 __ membar(Assembler::Membar_mask_bits(
2369 Assembler::LoadLoad | Assembler::LoadStore |
2370 Assembler::StoreLoad | Assembler::StoreStore));
2371 } else {
2372 // Write serialization page so VM thread can do a pseudo remote membar.
2373 // We use the current thread pointer to calculate a thread specific
2374 // offset to write to within the page. This minimizes bus traffic
2375 // due to cache line collision.
2376 __ serialize_memory(r15_thread, rcx);
2377 }
2378 }
2379
2380 Label after_transition;
2381
2382 // check for safepoint operation in progress and/or pending suspend requests
2383 {
2384 Label Continue;
2385
2386 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
2387 SafepointSynchronize::_not_synchronized);
2388
2389 Label L;
2390 __ jcc(Assembler::notEqual, L);
2391 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
2392 __ jcc(Assembler::equal, Continue);
2393 __ bind(L);
2394
2395 // Don't use call_VM as it will see a possible pending exception and forward it
2396 // and never return here preventing us from clearing _last_native_pc down below.
2397 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
2398 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
2399 // by hand.
2400 //
2401 save_native_result(masm, ret_type, stack_slots);
2402 __ mov(c_rarg0, r15_thread);
2403 __ mov(r12, rsp); // remember sp
2404 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2405 __ andptr(rsp, -16); // align stack as required by ABI
2406 if (!is_critical_native) {
2407 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
2408 } else {
2409 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
2410 }
2411 __ mov(rsp, r12); // restore sp
2412 __ reinit_heapbase();
2413 // Restore any method result value
2414 restore_native_result(masm, ret_type, stack_slots);
2415
2416 if (is_critical_native) {
2417 // The call above performed the transition to thread_in_Java so
2418 // skip the transition logic below.
2419 __ jmpb(after_transition);
2420 }
2421
2422 __ bind(Continue);
2423 }
2424
2425 // change thread state
2426 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
2427 __ bind(after_transition);
2428
2429 Label reguard;
2430 Label reguard_done;
2431 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
2432 __ jcc(Assembler::equal, reguard);
2433 __ bind(reguard_done);
2434
2435 // native result if any is live
2436
2437 // Unlock
2438 Label unlock_done;
2439 Label slow_path_unlock;
2440 if (method->is_synchronized()) {
2441
2442 // Get locked oop from the handle we passed to jni
2443 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2444
2445 Label done;
2446
2447 if (UseBiasedLocking) {
2448 __ biased_locking_exit(obj_reg, old_hdr, done);
2449 }
2450
2451 // Simple recursive lock?
2452
2453 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
2454 __ jcc(Assembler::equal, done);
2455
2456 // Must save rax if if it is live now because cmpxchg must use it
2457 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2458 save_native_result(masm, ret_type, stack_slots);
2459 }
2460
2461
2462 // get address of the stack lock
2463 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2464 // get old displaced header
2465 __ movptr(old_hdr, Address(rax, 0));
2466
2467 // Atomic swap old header if oop still contains the stack lock
2468 if (os::is_MP()) {
2469 __ lock();
2470 }
2471 __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
2472 __ jcc(Assembler::notEqual, slow_path_unlock);
2473
2474 // slow path re-enters here
2475 __ bind(unlock_done);
2476 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2477 restore_native_result(masm, ret_type, stack_slots);
2478 }
2479
2480 __ bind(done);
2481
2482 }
2483 {
2484 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2485 save_native_result(masm, ret_type, stack_slots);
2486 __ mov_metadata(c_rarg1, method());
2487 __ call_VM_leaf(
2488 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2489 r15_thread, c_rarg1);
2490 restore_native_result(masm, ret_type, stack_slots);
2491 }
2492
2493 __ reset_last_Java_frame(false, true);
2494
2495 // Unpack oop result
2496 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2497 Label L;
2498 __ testptr(rax, rax);
2499 __ jcc(Assembler::zero, L);
2500 __ movptr(rax, Address(rax, 0));
2501 __ bind(L);
2502 __ verify_oop(rax);
2503 }
2504
2505 if (!is_critical_native) {
2506 // reset handle block
2507 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
2508 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
2509 }
2510
2511 // pop our frame
2512
2513 __ leave();
2514
2515 if (!is_critical_native) {
2516 // Any exception pending?
2517 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2518 __ jcc(Assembler::notEqual, exception_pending);
2519 }
2520
2521 // Return
2522
2523 __ ret(0);
2524
2525 // Unexpected paths are out of line and go here
2526
2527 if (!is_critical_native) {
2528 // forward the exception
2529 __ bind(exception_pending);
2530
2531 // and forward the exception
2532 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2533 }
2534
2535 // Slow path locking & unlocking
2536 if (method->is_synchronized()) {
2537
2538 // BEGIN Slow path lock
2539 __ bind(slow_path_lock);
2540
2541 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2542 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2543
2544 // protect the args we've loaded
2545 save_args(masm, total_c_args, c_arg, out_regs);
2546
2547 __ mov(c_rarg0, obj_reg);
2548 __ mov(c_rarg1, lock_reg);
2549 __ mov(c_rarg2, r15_thread);
2550
2551 // Not a leaf but we have last_Java_frame setup as we want
2552 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
2553 restore_args(masm, total_c_args, c_arg, out_regs);
2554
2555 #ifdef ASSERT
2556 { Label L;
2557 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2558 __ jcc(Assembler::equal, L);
2559 __ stop("no pending exception allowed on exit from monitorenter");
2560 __ bind(L);
2561 }
2562 #endif
2563 __ jmp(lock_done);
2564
2565 // END Slow path lock
2566
2567 // BEGIN Slow path unlock
2568 __ bind(slow_path_unlock);
2569
2570 // If we haven't already saved the native result we must save it now as xmm registers
2571 // are still exposed.
2572
2573 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2574 save_native_result(masm, ret_type, stack_slots);
2575 }
2576
2577 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2578
2579 __ mov(c_rarg0, obj_reg);
2580 __ mov(r12, rsp); // remember sp
2581 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2582 __ andptr(rsp, -16); // align stack as required by ABI
2583
2584 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2585 // NOTE that obj_reg == rbx currently
2586 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
2587 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2588
2589 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2590 __ mov(rsp, r12); // restore sp
2591 __ reinit_heapbase();
2592 #ifdef ASSERT
2593 {
2594 Label L;
2595 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2596 __ jcc(Assembler::equal, L);
2597 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2598 __ bind(L);
2599 }
2600 #endif /* ASSERT */
2601
2602 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
2603
2604 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2605 restore_native_result(masm, ret_type, stack_slots);
2606 }
2607 __ jmp(unlock_done);
2608
2609 // END Slow path unlock
2610
2611 } // synchronized
2612
2613 // SLOW PATH Reguard the stack if needed
2614
2615 __ bind(reguard);
2616 save_native_result(masm, ret_type, stack_slots);
2617 __ mov(r12, rsp); // remember sp
2618 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2619 __ andptr(rsp, -16); // align stack as required by ABI
2620 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2621 __ mov(rsp, r12); // restore sp
2622 __ reinit_heapbase();
2623 restore_native_result(masm, ret_type, stack_slots);
2624 // and continue
2625 __ jmp(reguard_done);
2626
2627
2628
2629 __ flush();
2630
2631 nmethod *nm = nmethod::new_native_nmethod(method,
2632 compile_id,
2633 masm->code(),
2634 vep_offset,
2635 frame_complete,
2636 stack_slots / VMRegImpl::slots_per_word,
2637 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2638 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2639 oop_maps);
2640
2641 if (is_critical_native) {
2642 nm->set_lazy_critical_native(true);
2643 }
2644
2645 return nm;
2646
2647 }
2648
2649 #ifdef HAVE_DTRACE_H
2650 // ---------------------------------------------------------------------------
2651 // Generate a dtrace nmethod for a given signature. The method takes arguments
2652 // in the Java compiled code convention, marshals them to the native
2653 // abi and then leaves nops at the position you would expect to call a native
2654 // function. When the probe is enabled the nops are replaced with a trap
2655 // instruction that dtrace inserts and the trace will cause a notification
2656 // to dtrace.
2657 //
2658 // The probes are only able to take primitive types and java/lang/String as
2659 // arguments. No other java types are allowed. Strings are converted to utf8
2660 // strings so that from dtrace point of view java strings are converted to C
2661 // strings. There is an arbitrary fixed limit on the total space that a method
2662 // can use for converting the strings. (256 chars per string in the signature).
2663 // So any java string larger then this is truncated.
2664
2665 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2666 static bool offsets_initialized = false;
2667
2668
2669 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
2670 methodHandle method) {
2671
2672
2673 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2674 // be single threaded in this method.
2675 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2676
2677 if (!offsets_initialized) {
2678 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
2679 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
2680 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
2681 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
2682 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
2683 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
2684
2685 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
2686 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
2687 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
2688 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
2689 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
2690 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
2691 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
2692 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
2693
2694 offsets_initialized = true;
2695 }
2696 // Fill in the signature array, for the calling-convention call.
2697 int total_args_passed = method->size_of_parameters();
2698
2699 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2700 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2701
2702 // The signature we are going to use for the trap that dtrace will see
2703 // java/lang/String is converted. We drop "this" and any other object
2704 // is converted to NULL. (A one-slot java/lang/Long object reference
2705 // is converted to a two-slot long, which is why we double the allocation).
2706 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2707 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2708
2709 int i=0;
2710 int total_strings = 0;
2711 int first_arg_to_pass = 0;
2712 int total_c_args = 0;
2713
2714 // Skip the receiver as dtrace doesn't want to see it
2715 if( !method->is_static() ) {
2716 in_sig_bt[i++] = T_OBJECT;
2717 first_arg_to_pass = 1;
2718 }
2719
2720 // We need to convert the java args to where a native (non-jni) function
2721 // would expect them. To figure out where they go we convert the java
2722 // signature to a C signature.
2723
2724 SignatureStream ss(method->signature());
2725 for ( ; !ss.at_return_type(); ss.next()) {
2726 BasicType bt = ss.type();
2727 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2728 out_sig_bt[total_c_args++] = bt;
2729 if( bt == T_OBJECT) {
2730 Symbol* s = ss.as_symbol_or_null(); // symbol is created
2731 if (s == vmSymbols::java_lang_String()) {
2732 total_strings++;
2733 out_sig_bt[total_c_args-1] = T_ADDRESS;
2734 } else if (s == vmSymbols::java_lang_Boolean() ||
2735 s == vmSymbols::java_lang_Character() ||
2736 s == vmSymbols::java_lang_Byte() ||
2737 s == vmSymbols::java_lang_Short() ||
2738 s == vmSymbols::java_lang_Integer() ||
2739 s == vmSymbols::java_lang_Float()) {
2740 out_sig_bt[total_c_args-1] = T_INT;
2741 } else if (s == vmSymbols::java_lang_Long() ||
2742 s == vmSymbols::java_lang_Double()) {
2743 out_sig_bt[total_c_args-1] = T_LONG;
2744 out_sig_bt[total_c_args++] = T_VOID;
2745 }
2746 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2747 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2748 // We convert double to long
2749 out_sig_bt[total_c_args-1] = T_LONG;
2750 out_sig_bt[total_c_args++] = T_VOID;
2751 } else if ( bt == T_FLOAT) {
2752 // We convert float to int
2753 out_sig_bt[total_c_args-1] = T_INT;
2754 }
2755 }
2756
2757 assert(i==total_args_passed, "validly parsed signature");
2758
2759 // Now get the compiled-Java layout as input arguments
2760 int comp_args_on_stack;
2761 comp_args_on_stack = SharedRuntime::java_calling_convention(
2762 in_sig_bt, in_regs, total_args_passed, false);
2763
2764 // Now figure out where the args must be stored and how much stack space
2765 // they require (neglecting out_preserve_stack_slots but space for storing
2766 // the 1st six register arguments). It's weird see int_stk_helper.
2767
2768 int out_arg_slots;
2769 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2770
2771 // Calculate the total number of stack slots we will need.
2772
2773 // First count the abi requirement plus all of the outgoing args
2774 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2775
2776 // Now space for the string(s) we must convert
2777 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2778 for (i = 0; i < total_strings ; i++) {
2779 string_locs[i] = stack_slots;
2780 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2781 }
2782
2783 // Plus the temps we might need to juggle register args
2784 // regs take two slots each
2785 stack_slots += (Argument::n_int_register_parameters_c +
2786 Argument::n_float_register_parameters_c) * 2;
2787
2788
2789 // + 4 for return address (which we own) and saved rbp,
2790
2791 stack_slots += 4;
2792
2793 // Ok The space we have allocated will look like:
2794 //
2795 //
2796 // FP-> | |
2797 // |---------------------|
2798 // | string[n] |
2799 // |---------------------| <- string_locs[n]
2800 // | string[n-1] |
2801 // |---------------------| <- string_locs[n-1]
2802 // | ... |
2803 // | ... |
2804 // |---------------------| <- string_locs[1]
2805 // | string[0] |
2806 // |---------------------| <- string_locs[0]
2807 // | outbound memory |
2808 // | based arguments |
2809 // | |
2810 // |---------------------|
2811 // | |
2812 // SP-> | out_preserved_slots |
2813 //
2814 //
2815
2816 // Now compute actual number of stack words we need rounding to make
2817 // stack properly aligned.
2818 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2819
2820 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2821
2822 intptr_t start = (intptr_t)__ pc();
2823
2824 // First thing make an ic check to see if we should even be here
2825
2826 // We are free to use all registers as temps without saving them and
2827 // restoring them except rbp. rbp, is the only callee save register
2828 // as far as the interpreter and the compiler(s) are concerned.
2829
2830 const Register ic_reg = rax;
2831 const Register receiver = rcx;
2832 Label hit;
2833 Label exception_pending;
2834
2835
2836 __ verify_oop(receiver);
2837 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2838 __ jcc(Assembler::equal, hit);
2839
2840 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2841
2842 // verified entry must be aligned for code patching.
2843 // and the first 5 bytes must be in the same cache line
2844 // if we align at 8 then we will be sure 5 bytes are in the same line
2845 __ align(8);
2846
2847 __ bind(hit);
2848
2849 int vep_offset = ((intptr_t)__ pc()) - start;
2850
2851
2852 // The instruction at the verified entry point must be 5 bytes or longer
2853 // because it can be patched on the fly by make_non_entrant. The stack bang
2854 // instruction fits that requirement.
2855
2856 // Generate stack overflow check
2857
2858 if (UseStackBanging) {
2859 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2860 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2861 } else {
2862 __ movl(rax, stack_size);
2863 __ bang_stack_size(rax, rbx);
2864 }
2865 } else {
2866 // need a 5 byte instruction to allow MT safe patching to non-entrant
2867 __ fat_nop();
2868 }
2869
2870 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
2871 "valid size for make_non_entrant");
2872
2873 // Generate a new frame for the wrapper.
2874 __ enter();
2875
2876 // -4 because return address is already present and so is saved rbp,
2877 if (stack_size - 2*wordSize != 0) {
2878 __ subq(rsp, stack_size - 2*wordSize);
2879 }
2880
2881 // Frame is now completed as far a size and linkage.
2882
2883 int frame_complete = ((intptr_t)__ pc()) - start;
2884
2885 int c_arg, j_arg;
2886
2887 // State of input register args
2888
2889 bool live[ConcreteRegisterImpl::number_of_registers];
2890
2891 live[j_rarg0->as_VMReg()->value()] = false;
2892 live[j_rarg1->as_VMReg()->value()] = false;
2893 live[j_rarg2->as_VMReg()->value()] = false;
2894 live[j_rarg3->as_VMReg()->value()] = false;
2895 live[j_rarg4->as_VMReg()->value()] = false;
2896 live[j_rarg5->as_VMReg()->value()] = false;
2897
2898 live[j_farg0->as_VMReg()->value()] = false;
2899 live[j_farg1->as_VMReg()->value()] = false;
2900 live[j_farg2->as_VMReg()->value()] = false;
2901 live[j_farg3->as_VMReg()->value()] = false;
2902 live[j_farg4->as_VMReg()->value()] = false;
2903 live[j_farg5->as_VMReg()->value()] = false;
2904 live[j_farg6->as_VMReg()->value()] = false;
2905 live[j_farg7->as_VMReg()->value()] = false;
2906
2907
2908 bool rax_is_zero = false;
2909
2910 // All args (except strings) destined for the stack are moved first
2911 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2912 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2913 VMRegPair src = in_regs[j_arg];
2914 VMRegPair dst = out_regs[c_arg];
2915
2916 // Get the real reg value or a dummy (rsp)
2917
2918 int src_reg = src.first()->is_reg() ?
2919 src.first()->value() :
2920 rsp->as_VMReg()->value();
2921
2922 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2923 (in_sig_bt[j_arg] == T_OBJECT &&
2924 out_sig_bt[c_arg] != T_INT &&
2925 out_sig_bt[c_arg] != T_ADDRESS &&
2926 out_sig_bt[c_arg] != T_LONG);
2927
2928 live[src_reg] = !useless;
2929
2930 if (dst.first()->is_stack()) {
2931
2932 // Even though a string arg in a register is still live after this loop
2933 // after the string conversion loop (next) it will be dead so we take
2934 // advantage of that now for simpler code to manage live.
2935
2936 live[src_reg] = false;
2937 switch (in_sig_bt[j_arg]) {
2938
2939 case T_ARRAY:
2940 case T_OBJECT:
2941 {
2942 Address stack_dst(rsp, reg2offset_out(dst.first()));
2943
2944 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2945 // need to unbox a one-word value
2946 Register in_reg = rax;
2947 if ( src.first()->is_reg() ) {
2948 in_reg = src.first()->as_Register();
2949 } else {
2950 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
2951 rax_is_zero = false;
2952 }
2953 Label skipUnbox;
2954 __ movptr(Address(rsp, reg2offset_out(dst.first())),
2955 (int32_t)NULL_WORD);
2956 __ testq(in_reg, in_reg);
2957 __ jcc(Assembler::zero, skipUnbox);
2958
2959 BasicType bt = out_sig_bt[c_arg];
2960 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2961 Address src1(in_reg, box_offset);
2962 if ( bt == T_LONG ) {
2963 __ movq(in_reg, src1);
2964 __ movq(stack_dst, in_reg);
2965 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2966 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2967 } else {
2968 __ movl(in_reg, src1);
2969 __ movl(stack_dst, in_reg);
2970 }
2971
2972 __ bind(skipUnbox);
2973 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2974 // Convert the arg to NULL
2975 if (!rax_is_zero) {
2976 __ xorq(rax, rax);
2977 rax_is_zero = true;
2978 }
2979 __ movq(stack_dst, rax);
2980 }
2981 }
2982 break;
2983
2984 case T_VOID:
2985 break;
2986
2987 case T_FLOAT:
2988 // This does the right thing since we know it is destined for the
2989 // stack
2990 float_move(masm, src, dst);
2991 break;
2992
2993 case T_DOUBLE:
2994 // This does the right thing since we know it is destined for the
2995 // stack
2996 double_move(masm, src, dst);
2997 break;
2998
2999 case T_LONG :
3000 long_move(masm, src, dst);
3001 break;
3002
3003 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
3004
3005 default:
3006 move32_64(masm, src, dst);
3007 }
3008 }
3009
3010 }
3011
3012 // If we have any strings we must store any register based arg to the stack
3013 // This includes any still live xmm registers too.
3014
3015 int sid = 0;
3016
3017 if (total_strings > 0 ) {
3018 for (j_arg = first_arg_to_pass, c_arg = 0 ;
3019 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3020 VMRegPair src = in_regs[j_arg];
3021 VMRegPair dst = out_regs[c_arg];
3022
3023 if (src.first()->is_reg()) {
3024 Address src_tmp(rbp, fp_offset[src.first()->value()]);
3025
3026 // string oops were left untouched by the previous loop even if the
3027 // eventual (converted) arg is destined for the stack so park them
3028 // away now (except for first)
3029
3030 if (out_sig_bt[c_arg] == T_ADDRESS) {
3031 Address utf8_addr = Address(
3032 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
3033 if (sid != 1) {
3034 // The first string arg won't be killed until after the utf8
3035 // conversion
3036 __ movq(utf8_addr, src.first()->as_Register());
3037 }
3038 } else if (dst.first()->is_reg()) {
3039 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
3040
3041 // Convert the xmm register to an int and store it in the reserved
3042 // location for the eventual c register arg
3043 XMMRegister f = src.first()->as_XMMRegister();
3044 if (in_sig_bt[j_arg] == T_FLOAT) {
3045 __ movflt(src_tmp, f);
3046 } else {
3047 __ movdbl(src_tmp, f);
3048 }
3049 } else {
3050 // If the arg is an oop type we don't support don't bother to store
3051 // it remember string was handled above.
3052 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
3053 (in_sig_bt[j_arg] == T_OBJECT &&
3054 out_sig_bt[c_arg] != T_INT &&
3055 out_sig_bt[c_arg] != T_LONG);
3056
3057 if (!useless) {
3058 __ movq(src_tmp, src.first()->as_Register());
3059 }
3060 }
3061 }
3062 }
3063 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3064 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3065 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3066 }
3067 }
3068
3069 // Now that the volatile registers are safe, convert all the strings
3070 sid = 0;
3071
3072 for (j_arg = first_arg_to_pass, c_arg = 0 ;
3073 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3074 if (out_sig_bt[c_arg] == T_ADDRESS) {
3075 // It's a string
3076 Address utf8_addr = Address(
3077 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
3078 // The first string we find might still be in the original java arg
3079 // register
3080
3081 VMReg src = in_regs[j_arg].first();
3082
3083 // We will need to eventually save the final argument to the trap
3084 // in the von-volatile location dedicated to src. This is the offset
3085 // from fp we will use.
3086 int src_off = src->is_reg() ?
3087 fp_offset[src->value()] : reg2offset_in(src);
3088
3089 // This is where the argument will eventually reside
3090 VMRegPair dst = out_regs[c_arg];
3091
3092 if (src->is_reg()) {
3093 if (sid == 1) {
3094 __ movq(c_rarg0, src->as_Register());
3095 } else {
3096 __ movq(c_rarg0, utf8_addr);
3097 }
3098 } else {
3099 // arg is still in the original location
3100 __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
3101 }
3102 Label done, convert;
3103
3104 // see if the oop is NULL
3105 __ testq(c_rarg0, c_rarg0);
3106 __ jcc(Assembler::notEqual, convert);
3107
3108 if (dst.first()->is_reg()) {
3109 // Save the ptr to utf string in the origina src loc or the tmp
3110 // dedicated to it
3111 __ movq(Address(rbp, src_off), c_rarg0);
3112 } else {
3113 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
3114 }
3115 __ jmp(done);
3116
3117 __ bind(convert);
3118
3119 __ lea(c_rarg1, utf8_addr);
3120 if (dst.first()->is_reg()) {
3121 __ movq(Address(rbp, src_off), c_rarg1);
3122 } else {
3123 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
3124 }
3125 // And do the conversion
3126 __ call(RuntimeAddress(
3127 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
3128
3129 __ bind(done);
3130 }
3131 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3132 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3133 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3134 }
3135 }
3136 // The get_utf call killed all the c_arg registers
3137 live[c_rarg0->as_VMReg()->value()] = false;
3138 live[c_rarg1->as_VMReg()->value()] = false;
3139 live[c_rarg2->as_VMReg()->value()] = false;
3140 live[c_rarg3->as_VMReg()->value()] = false;
3141 live[c_rarg4->as_VMReg()->value()] = false;
3142 live[c_rarg5->as_VMReg()->value()] = false;
3143
3144 live[c_farg0->as_VMReg()->value()] = false;
3145 live[c_farg1->as_VMReg()->value()] = false;
3146 live[c_farg2->as_VMReg()->value()] = false;
3147 live[c_farg3->as_VMReg()->value()] = false;
3148 live[c_farg4->as_VMReg()->value()] = false;
3149 live[c_farg5->as_VMReg()->value()] = false;
3150 live[c_farg6->as_VMReg()->value()] = false;
3151 live[c_farg7->as_VMReg()->value()] = false;
3152 }
3153
3154 // Now we can finally move the register args to their desired locations
3155
3156 rax_is_zero = false;
3157
3158 for (j_arg = first_arg_to_pass, c_arg = 0 ;
3159 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3160
3161 VMRegPair src = in_regs[j_arg];
3162 VMRegPair dst = out_regs[c_arg];
3163
3164 // Only need to look for args destined for the interger registers (since we
3165 // convert float/double args to look like int/long outbound)
3166 if (dst.first()->is_reg()) {
3167 Register r = dst.first()->as_Register();
3168
3169 // Check if the java arg is unsupported and thereofre useless
3170 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
3171 (in_sig_bt[j_arg] == T_OBJECT &&
3172 out_sig_bt[c_arg] != T_INT &&
3173 out_sig_bt[c_arg] != T_ADDRESS &&
3174 out_sig_bt[c_arg] != T_LONG);
3175
3176
3177 // If we're going to kill an existing arg save it first
3178 if (live[dst.first()->value()]) {
3179 // you can't kill yourself
3180 if (src.first() != dst.first()) {
3181 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
3182 }
3183 }
3184 if (src.first()->is_reg()) {
3185 if (live[src.first()->value()] ) {
3186 if (in_sig_bt[j_arg] == T_FLOAT) {
3187 __ movdl(r, src.first()->as_XMMRegister());
3188 } else if (in_sig_bt[j_arg] == T_DOUBLE) {
3189 __ movdq(r, src.first()->as_XMMRegister());
3190 } else if (r != src.first()->as_Register()) {
3191 if (!useless) {
3192 __ movq(r, src.first()->as_Register());
3193 }
3194 }
3195 } else {
3196 // If the arg is an oop type we don't support don't bother to store
3197 // it
3198 if (!useless) {
3199 if (in_sig_bt[j_arg] == T_DOUBLE ||
3200 in_sig_bt[j_arg] == T_LONG ||
3201 in_sig_bt[j_arg] == T_OBJECT ) {
3202 __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
3203 } else {
3204 __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
3205 }
3206 }
3207 }
3208 live[src.first()->value()] = false;
3209 } else if (!useless) {
3210 // full sized move even for int should be ok
3211 __ movq(r, Address(rbp, reg2offset_in(src.first())));
3212 }
3213
3214 // At this point r has the original java arg in the final location
3215 // (assuming it wasn't useless). If the java arg was an oop
3216 // we have a bit more to do
3217
3218 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
3219 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
3220 // need to unbox a one-word value
3221 Label skip;
3222 __ testq(r, r);
3223 __ jcc(Assembler::equal, skip);
3224 BasicType bt = out_sig_bt[c_arg];
3225 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
3226 Address src1(r, box_offset);
3227 if ( bt == T_LONG ) {
3228 __ movq(r, src1);
3229 } else {
3230 __ movl(r, src1);
3231 }
3232 __ bind(skip);
3233
3234 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
3235 // Convert the arg to NULL
3236 __ xorq(r, r);
3237 }
3238 }
3239
3240 // dst can longer be holding an input value
3241 live[dst.first()->value()] = false;
3242 }
3243 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3244 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3245 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3246 }
3247 }
3248
3249
3250 // Ok now we are done. Need to place the nop that dtrace wants in order to
3251 // patch in the trap
3252 int patch_offset = ((intptr_t)__ pc()) - start;
3253
3254 __ nop();
3255
3256
3257 // Return
3258
3259 __ leave();
3260 __ ret(0);
3261
3262 __ flush();
3263
3264 nmethod *nm = nmethod::new_dtrace_nmethod(
3265 method, masm->code(), vep_offset, patch_offset, frame_complete,
3266 stack_slots / VMRegImpl::slots_per_word);
3267 return nm;
3268
3269 }
3270
3271 #endif // HAVE_DTRACE_H
3272
3273 // this function returns the adjust size (in number of words) to a c2i adapter
3274 // activation for use during deoptimization
3275 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
3276 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
3277 }
3278
3279
3280 uint SharedRuntime::out_preserve_stack_slots() {
3281 return 0;
3282 }
3283
3284 //------------------------------generate_deopt_blob----------------------------
3285 void SharedRuntime::generate_deopt_blob() {
3286 // Allocate space for the code
3287 ResourceMark rm;
3288 // Setup code generation tools
3289 CodeBuffer buffer("deopt_blob", 2048, 1024);
3290 MacroAssembler* masm = new MacroAssembler(&buffer);
3291 int frame_size_in_words;
3292 OopMap* map = NULL;
3293 OopMapSet *oop_maps = new OopMapSet();
3294
3295 // -------------
3296 // This code enters when returning to a de-optimized nmethod. A return
3297 // address has been pushed on the the stack, and return values are in
3298 // registers.
3299 // If we are doing a normal deopt then we were called from the patched
3300 // nmethod from the point we returned to the nmethod. So the return
3301 // address on the stack is wrong by NativeCall::instruction_size
3302 // We will adjust the value so it looks like we have the original return
3303 // address on the stack (like when we eagerly deoptimized).
3304 // In the case of an exception pending when deoptimizing, we enter
3305 // with a return address on the stack that points after the call we patched
3306 // into the exception handler. We have the following register state from,
3307 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
3308 // rax: exception oop
3309 // rbx: exception handler
3310 // rdx: throwing pc
3311 // So in this case we simply jam rdx into the useless return address and
3312 // the stack looks just like we want.
3313 //
3314 // At this point we need to de-opt. We save the argument return
3315 // registers. We call the first C routine, fetch_unroll_info(). This
3316 // routine captures the return values and returns a structure which
3317 // describes the current frame size and the sizes of all replacement frames.
3318 // The current frame is compiled code and may contain many inlined
3319 // functions, each with their own JVM state. We pop the current frame, then
3320 // push all the new frames. Then we call the C routine unpack_frames() to
3321 // populate these frames. Finally unpack_frames() returns us the new target
3322 // address. Notice that callee-save registers are BLOWN here; they have
3323 // already been captured in the vframeArray at the time the return PC was
3324 // patched.
3325 address start = __ pc();
3326 Label cont;
3327
3328 // Prolog for non exception case!
3329
3330 // Save everything in sight.
3331 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3332
3333 // Normal deoptimization. Save exec mode for unpack_frames.
3334 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
3335 __ jmp(cont);
3336
3337 int reexecute_offset = __ pc() - start;
3338
3339 // Reexecute case
3340 // return address is the pc describes what bci to do re-execute at
3341
3342 // No need to update map as each call to save_live_registers will produce identical oopmap
3343 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3344
3345 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
3346 __ jmp(cont);
3347
3348 int exception_offset = __ pc() - start;
3349
3350 // Prolog for exception case
3351
3352 // all registers are dead at this entry point, except for rax, and
3353 // rdx which contain the exception oop and exception pc
3354 // respectively. Set them in TLS and fall thru to the
3355 // unpack_with_exception_in_tls entry point.
3356
3357 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3358 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
3359
3360 int exception_in_tls_offset = __ pc() - start;
3361
3362 // new implementation because exception oop is now passed in JavaThread
3363
3364 // Prolog for exception case
3365 // All registers must be preserved because they might be used by LinearScan
3366 // Exceptiop oop and throwing PC are passed in JavaThread
3367 // tos: stack at point of call to method that threw the exception (i.e. only
3368 // args are on the stack, no return address)
3369
3370 // make room on stack for the return address
3371 // It will be patched later with the throwing pc. The correct value is not
3372 // available now because loading it from memory would destroy registers.
3373 __ push(0);
3374
3375 // Save everything in sight.
3376 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3377
3378 // Now it is safe to overwrite any register
3379
3380 // Deopt during an exception. Save exec mode for unpack_frames.
3381 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
3382
3383 // load throwing pc from JavaThread and patch it as the return address
3384 // of the current frame. Then clear the field in JavaThread
3385
3386 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3387 __ movptr(Address(rbp, wordSize), rdx);
3388 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3389
3390 #ifdef ASSERT
3391 // verify that there is really an exception oop in JavaThread
3392 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3393 __ verify_oop(rax);
3394
3395 // verify that there is no pending exception
3396 Label no_pending_exception;
3397 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3398 __ testptr(rax, rax);
3399 __ jcc(Assembler::zero, no_pending_exception);
3400 __ stop("must not have pending exception here");
3401 __ bind(no_pending_exception);
3402 #endif
3403
3404 __ bind(cont);
3405
3406 // Call C code. Need thread and this frame, but NOT official VM entry
3407 // crud. We cannot block on this call, no GC can happen.
3408 //
3409 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
3410
3411 // fetch_unroll_info needs to call last_java_frame().
3412
3413 __ set_last_Java_frame(noreg, noreg, NULL);
3414 #ifdef ASSERT
3415 { Label L;
3416 __ cmpptr(Address(r15_thread,
3417 JavaThread::last_Java_fp_offset()),
3418 (int32_t)0);
3419 __ jcc(Assembler::equal, L);
3420 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
3421 __ bind(L);
3422 }
3423 #endif // ASSERT
3424 __ mov(c_rarg0, r15_thread);
3425 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3426
3427 // Need to have an oopmap that tells fetch_unroll_info where to
3428 // find any register it might need.
3429 oop_maps->add_gc_map(__ pc() - start, map);
3430
3431 __ reset_last_Java_frame(false, false);
3432
3433 // Load UnrollBlock* into rdi
3434 __ mov(rdi, rax);
3435
3436 Label noException;
3437 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
3438 __ jcc(Assembler::notEqual, noException);
3439 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3440 // QQQ this is useless it was NULL above
3441 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3442 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
3443 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3444
3445 __ verify_oop(rax);
3446
3447 // Overwrite the result registers with the exception results.
3448 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3449 // I think this is useless
3450 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
3451
3452 __ bind(noException);
3453
3454 // Only register save data is on the stack.
3455 // Now restore the result registers. Everything else is either dead
3456 // or captured in the vframeArray.
3457 RegisterSaver::restore_result_registers(masm);
3458
3459 // All of the register save area has been popped of the stack. Only the
3460 // return address remains.
3461
3462 // Pop all the frames we must move/replace.
3463 //
3464 // Frame picture (youngest to oldest)
3465 // 1: self-frame (no frame link)
3466 // 2: deopting frame (no frame link)
3467 // 3: caller of deopting frame (could be compiled/interpreted).
3468 //
3469 // Note: by leaving the return address of self-frame on the stack
3470 // and using the size of frame 2 to adjust the stack
3471 // when we are done the return to frame 3 will still be on the stack.
3472
3473 // Pop deoptimized frame
3474 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3475 __ addptr(rsp, rcx);
3476
3477 // rsp should be pointing at the return address to the caller (3)
3478
3479 // Stack bang to make sure there's enough room for these interpreter frames.
3480 if (UseStackBanging) {
3481 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3482 __ bang_stack_size(rbx, rcx);
3483 }
3484
3485 // Load address of array of frame pcs into rcx
3486 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3487
3488 // Trash the old pc
3489 __ addptr(rsp, wordSize);
3490
3491 // Load address of array of frame sizes into rsi
3492 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3493
3494 // Load counter into rdx
3495 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3496
3497 // Pick up the initial fp we should save
3498 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3499
3500 // Now adjust the caller's stack to make up for the extra locals
3501 // but record the original sp so that we can save it in the skeletal interpreter
3502 // frame and the stack walking of interpreter_sender will get the unextended sp
3503 // value and not the "real" sp value.
3504
3505 const Register sender_sp = r8;
3506
3507 __ mov(sender_sp, rsp);
3508 __ movl(rbx, Address(rdi,
3509 Deoptimization::UnrollBlock::
3510 caller_adjustment_offset_in_bytes()));
3511 __ subptr(rsp, rbx);
3512
3513 // Push interpreter frames in a loop
3514 Label loop;
3515 __ bind(loop);
3516 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3517 #ifdef CC_INTERP
3518 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
3519 #ifdef ASSERT
3520 __ push(0xDEADDEAD); // Make a recognizable pattern
3521 __ push(0xDEADDEAD);
3522 #else /* ASSERT */
3523 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
3524 #endif /* ASSERT */
3525 #else
3526 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
3527 #endif // CC_INTERP
3528 __ pushptr(Address(rcx, 0)); // Save return address
3529 __ enter(); // Save old & set new ebp
3530 __ subptr(rsp, rbx); // Prolog
3531 #ifdef CC_INTERP
3532 __ movptr(Address(rbp,
3533 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3534 sender_sp); // Make it walkable
3535 #else /* CC_INTERP */
3536 // This value is corrected by layout_activation_impl
3537 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3538 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
3539 #endif /* CC_INTERP */
3540 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3541 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3542 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3543 __ decrementl(rdx); // Decrement counter
3544 __ jcc(Assembler::notZero, loop);
3545 __ pushptr(Address(rcx, 0)); // Save final return address
3546
3547 // Re-push self-frame
3548 __ enter(); // Save old & set new ebp
3549
3550 // Allocate a full sized register save area.
3551 // Return address and rbp are in place, so we allocate two less words.
3552 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
3553
3554 // Restore frame locals after moving the frame
3555 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
3556 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3557
3558 // Call C code. Need thread but NOT official VM entry
3559 // crud. We cannot block on this call, no GC can happen. Call should
3560 // restore return values to their stack-slots with the new SP.
3561 //
3562 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
3563
3564 // Use rbp because the frames look interpreted now
3565 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3566 // Don't need the precise return PC here, just precise enough to point into this code blob.
3567 address the_pc = __ pc();
3568 __ set_last_Java_frame(noreg, rbp, the_pc);
3569
3570 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
3571 __ mov(c_rarg0, r15_thread);
3572 __ movl(c_rarg1, r14); // second arg: exec_mode
3573 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3574 // Revert SP alignment after call since we're going to do some SP relative addressing below
3575 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
3576
3577 // Set an oopmap for the call site
3578 // Use the same PC we used for the last java frame
3579 oop_maps->add_gc_map(the_pc - start,
3580 new OopMap( frame_size_in_words, 0 ));
3581
3582 // Clear fp AND pc
3583 __ reset_last_Java_frame(true, true);
3584
3585 // Collect return values
3586 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
3587 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
3588 // I think this is useless (throwing pc?)
3589 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
3590
3591 // Pop self-frame.
3592 __ leave(); // Epilog
3593
3594 // Jump to interpreter
3595 __ ret(0);
3596
3597 // Make sure all code is generated
3598 masm->flush();
3599
3600 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3601 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3602 }
3603
3604 #ifdef COMPILER2
3605 //------------------------------generate_uncommon_trap_blob--------------------
3606 void SharedRuntime::generate_uncommon_trap_blob() {
3607 // Allocate space for the code
3608 ResourceMark rm;
3609 // Setup code generation tools
3610 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
3611 MacroAssembler* masm = new MacroAssembler(&buffer);
3612
3613 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3614
3615 address start = __ pc();
3616
3617 // Push self-frame. We get here with a return address on the
3618 // stack, so rsp is 8-byte aligned until we allocate our frame.
3619 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
3620
3621 // No callee saved registers. rbp is assumed implicitly saved
3622 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3623
3624 // compiler left unloaded_class_index in j_rarg0 move to where the
3625 // runtime expects it.
3626 __ movl(c_rarg1, j_rarg0);
3627
3628 __ set_last_Java_frame(noreg, noreg, NULL);
3629
3630 // Call C code. Need thread but NOT official VM entry
3631 // crud. We cannot block on this call, no GC can happen. Call should
3632 // capture callee-saved registers as well as return values.
3633 // Thread is in rdi already.
3634 //
3635 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
3636
3637 __ mov(c_rarg0, r15_thread);
3638 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3639
3640 // Set an oopmap for the call site
3641 OopMapSet* oop_maps = new OopMapSet();
3642 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
3643
3644 // location of rbp is known implicitly by the frame sender code
3645
3646 oop_maps->add_gc_map(__ pc() - start, map);
3647
3648 __ reset_last_Java_frame(false, false);
3649
3650 // Load UnrollBlock* into rdi
3651 __ mov(rdi, rax);
3652
3653 // Pop all the frames we must move/replace.
3654 //
3655 // Frame picture (youngest to oldest)
3656 // 1: self-frame (no frame link)
3657 // 2: deopting frame (no frame link)
3658 // 3: caller of deopting frame (could be compiled/interpreted).
3659
3660 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
3661 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
3662
3663 // Pop deoptimized frame (int)
3664 __ movl(rcx, Address(rdi,
3665 Deoptimization::UnrollBlock::
3666 size_of_deoptimized_frame_offset_in_bytes()));
3667 __ addptr(rsp, rcx);
3668
3669 // rsp should be pointing at the return address to the caller (3)
3670
3671 // Stack bang to make sure there's enough room for these interpreter frames.
3672 if (UseStackBanging) {
3673 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3674 __ bang_stack_size(rbx, rcx);
3675 }
3676
3677 // Load address of array of frame pcs into rcx (address*)
3678 __ movptr(rcx,
3679 Address(rdi,
3680 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3681
3682 // Trash the return pc
3683 __ addptr(rsp, wordSize);
3684
3685 // Load address of array of frame sizes into rsi (intptr_t*)
3686 __ movptr(rsi, Address(rdi,
3687 Deoptimization::UnrollBlock::
3688 frame_sizes_offset_in_bytes()));
3689
3690 // Counter
3691 __ movl(rdx, Address(rdi,
3692 Deoptimization::UnrollBlock::
3693 number_of_frames_offset_in_bytes())); // (int)
3694
3695 // Pick up the initial fp we should save
3696 __ movptr(rbp,
3697 Address(rdi,
3698 Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3699
3700 // Now adjust the caller's stack to make up for the extra locals but
3701 // record the original sp so that we can save it in the skeletal
3702 // interpreter frame and the stack walking of interpreter_sender
3703 // will get the unextended sp value and not the "real" sp value.
3704
3705 const Register sender_sp = r8;
3706
3707 __ mov(sender_sp, rsp);
3708 __ movl(rbx, Address(rdi,
3709 Deoptimization::UnrollBlock::
3710 caller_adjustment_offset_in_bytes())); // (int)
3711 __ subptr(rsp, rbx);
3712
3713 // Push interpreter frames in a loop
3714 Label loop;
3715 __ bind(loop);
3716 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3717 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
3718 __ pushptr(Address(rcx, 0)); // Save return address
3719 __ enter(); // Save old & set new rbp
3720 __ subptr(rsp, rbx); // Prolog
3721 #ifdef CC_INTERP
3722 __ movptr(Address(rbp,
3723 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3724 sender_sp); // Make it walkable
3725 #else // CC_INTERP
3726 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
3727 sender_sp); // Make it walkable
3728 // This value is corrected by layout_activation_impl
3729 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3730 #endif // CC_INTERP
3731 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3732 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3733 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3734 __ decrementl(rdx); // Decrement counter
3735 __ jcc(Assembler::notZero, loop);
3736 __ pushptr(Address(rcx, 0)); // Save final return address
3737
3738 // Re-push self-frame
3739 __ enter(); // Save old & set new rbp
3740 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
3741 // Prolog
3742
3743 // Use rbp because the frames look interpreted now
3744 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3745 // Don't need the precise return PC here, just precise enough to point into this code blob.
3746 address the_pc = __ pc();
3747 __ set_last_Java_frame(noreg, rbp, the_pc);
3748
3749 // Call C code. Need thread but NOT official VM entry
3750 // crud. We cannot block on this call, no GC can happen. Call should
3751 // restore return values to their stack-slots with the new SP.
3752 // Thread is in rdi already.
3753 //
3754 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3755
3756 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
3757 __ mov(c_rarg0, r15_thread);
3758 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3759 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3760
3761 // Set an oopmap for the call site
3762 // Use the same PC we used for the last java frame
3763 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3764
3765 // Clear fp AND pc
3766 __ reset_last_Java_frame(true, true);
3767
3768 // Pop self-frame.
3769 __ leave(); // Epilog
3770
3771 // Jump to interpreter
3772 __ ret(0);
3773
3774 // Make sure all code is generated
3775 masm->flush();
3776
3777 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3778 SimpleRuntimeFrame::framesize >> 1);
3779 }
3780 #endif // COMPILER2
3781
3782
3783 //------------------------------generate_handler_blob------
3784 //
3785 // Generate a special Compile2Runtime blob that saves all registers,
3786 // and setup oopmap.
3787 //
3788 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3789 assert(StubRoutines::forward_exception_entry() != NULL,
3790 "must be generated before");
3791
3792 ResourceMark rm;
3793 OopMapSet *oop_maps = new OopMapSet();
3794 OopMap* map;
3795
3796 // Allocate space for the code. Setup code generation tools.
3797 CodeBuffer buffer("handler_blob", 2048, 1024);
3798 MacroAssembler* masm = new MacroAssembler(&buffer);
3799
3800 address start = __ pc();
3801 address call_pc = NULL;
3802 int frame_size_in_words;
3803 bool cause_return = (poll_type == POLL_AT_RETURN);
3804 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP);
3805
3806 // Make room for return address (or push it again)
3807 if (!cause_return) {
3808 __ push(rbx);
3809 }
3810
3811 // Save registers, fpu state, and flags
3812 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors);
3813
3814 // The following is basically a call_VM. However, we need the precise
3815 // address of the call in order to generate an oopmap. Hence, we do all the
3816 // work outselves.
3817
3818 __ set_last_Java_frame(noreg, noreg, NULL);
3819
3820 // The return address must always be correct so that frame constructor never
3821 // sees an invalid pc.
3822
3823 if (!cause_return) {
3824 // overwrite the dummy value we pushed on entry
3825 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3826 __ movptr(Address(rbp, wordSize), c_rarg0);
3827 }
3828
3829 // Do the call
3830 __ mov(c_rarg0, r15_thread);
3831 __ call(RuntimeAddress(call_ptr));
3832
3833 // Set an oopmap for the call site. This oopmap will map all
3834 // oop-registers and debug-info registers as callee-saved. This
3835 // will allow deoptimization at this safepoint to find all possible
3836 // debug-info recordings, as well as let GC find all oops.
3837
3838 oop_maps->add_gc_map( __ pc() - start, map);
3839
3840 Label noException;
3841
3842 __ reset_last_Java_frame(false, false);
3843
3844 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3845 __ jcc(Assembler::equal, noException);
3846
3847 // Exception pending
3848
3849 RegisterSaver::restore_live_registers(masm, save_vectors);
3850
3851 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3852
3853 // No exception case
3854 __ bind(noException);
3855
3856 // Normal exit, restore registers and exit.
3857 RegisterSaver::restore_live_registers(masm, save_vectors);
3858
3859 __ ret(0);
3860
3861 // Make sure all code is generated
3862 masm->flush();
3863
3864 // Fill-out other meta info
3865 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3866 }
3867
3868 //
3869 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3870 //
3871 // Generate a stub that calls into vm to find out the proper destination
3872 // of a java call. All the argument registers are live at this point
3873 // but since this is generic code we don't know what they are and the caller
3874 // must do any gc of the args.
3875 //
3876 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3877 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3878
3879 // allocate space for the code
3880 ResourceMark rm;
3881
3882 CodeBuffer buffer(name, 1000, 512);
3883 MacroAssembler* masm = new MacroAssembler(&buffer);
3884
3885 int frame_size_in_words;
3886
3887 OopMapSet *oop_maps = new OopMapSet();
3888 OopMap* map = NULL;
3889
3890 int start = __ offset();
3891
3892 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3893
3894 int frame_complete = __ offset();
3895
3896 __ set_last_Java_frame(noreg, noreg, NULL);
3897
3898 __ mov(c_rarg0, r15_thread);
3899
3900 __ call(RuntimeAddress(destination));
3901
3902
3903 // Set an oopmap for the call site.
3904 // We need this not only for callee-saved registers, but also for volatile
3905 // registers that the compiler might be keeping live across a safepoint.
3906
3907 oop_maps->add_gc_map( __ offset() - start, map);
3908
3909 // rax contains the address we are going to jump to assuming no exception got installed
3910
3911 // clear last_Java_sp
3912 __ reset_last_Java_frame(false, false);
3913 // check for pending exceptions
3914 Label pending;
3915 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3916 __ jcc(Assembler::notEqual, pending);
3917
3918 // get the returned Method*
3919 __ get_vm_result_2(rbx, r15_thread);
3920 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3921
3922 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3923
3924 RegisterSaver::restore_live_registers(masm);
3925
3926 // We are back the the original state on entry and ready to go.
3927
3928 __ jmp(rax);
3929
3930 // Pending exception after the safepoint
3931
3932 __ bind(pending);
3933
3934 RegisterSaver::restore_live_registers(masm);
3935
3936 // exception pending => remove activation and forward to exception handler
3937
3938 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3939
3940 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3941 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3942
3943 // -------------
3944 // make sure all code is generated
3945 masm->flush();
3946
3947 // return the blob
3948 // frame_size_words or bytes??
3949 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3950 }
3951
3952
3953 #ifdef COMPILER2
3954 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3955 //
3956 //------------------------------generate_exception_blob---------------------------
3957 // creates exception blob at the end
3958 // Using exception blob, this code is jumped from a compiled method.
3959 // (see emit_exception_handler in x86_64.ad file)
3960 //
3961 // Given an exception pc at a call we call into the runtime for the
3962 // handler in this method. This handler might merely restore state
3963 // (i.e. callee save registers) unwind the frame and jump to the
3964 // exception handler for the nmethod if there is no Java level handler
3965 // for the nmethod.
3966 //
3967 // This code is entered with a jmp.
3968 //
3969 // Arguments:
3970 // rax: exception oop
3971 // rdx: exception pc
3972 //
3973 // Results:
3974 // rax: exception oop
3975 // rdx: exception pc in caller or ???
3976 // destination: exception handler of caller
3977 //
3978 // Note: the exception pc MUST be at a call (precise debug information)
3979 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3980 //
3981
3982 void OptoRuntime::generate_exception_blob() {
3983 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3984 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3985 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3986
3987 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3988
3989 // Allocate space for the code
3990 ResourceMark rm;
3991 // Setup code generation tools
3992 CodeBuffer buffer("exception_blob", 2048, 1024);
3993 MacroAssembler* masm = new MacroAssembler(&buffer);
3994
3995
3996 address start = __ pc();
3997
3998 // Exception pc is 'return address' for stack walker
3999 __ push(rdx);
4000 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
4001
4002 // Save callee-saved registers. See x86_64.ad.
4003
4004 // rbp is an implicitly saved callee saved register (i.e. the calling
4005 // convention will save restore it in prolog/epilog) Other than that
4006 // there are no callee save registers now that adapter frames are gone.
4007
4008 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
4009
4010 // Store exception in Thread object. We cannot pass any arguments to the
4011 // handle_exception call, since we do not want to make any assumption
4012 // about the size of the frame where the exception happened in.
4013 // c_rarg0 is either rdi (Linux) or rcx (Windows).
4014 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
4015 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
4016
4017 // This call does all the hard work. It checks if an exception handler
4018 // exists in the method.
4019 // If so, it returns the handler address.
4020 // If not, it prepares for stack-unwinding, restoring the callee-save
4021 // registers of the frame being removed.
4022 //
4023 // address OptoRuntime::handle_exception_C(JavaThread* thread)
4024
4025 // At a method handle call, the stack may not be properly aligned
4026 // when returning with an exception.
4027 address the_pc = __ pc();
4028 __ set_last_Java_frame(noreg, noreg, the_pc);
4029 __ mov(c_rarg0, r15_thread);
4030 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack
4031 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
4032
4033 // Set an oopmap for the call site. This oopmap will only be used if we
4034 // are unwinding the stack. Hence, all locations will be dead.
4035 // Callee-saved registers will be the same as the frame above (i.e.,
4036 // handle_exception_stub), since they were restored when we got the
4037 // exception.
4038
4039 OopMapSet* oop_maps = new OopMapSet();
4040
4041 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
4042
4043 __ reset_last_Java_frame(false, true);
4044
4045 // Restore callee-saved registers
4046
4047 // rbp is an implicitly saved callee saved register (i.e. the calling
4048 // convention will save restore it in prolog/epilog) Other than that
4049 // there are no callee save registers no that adapter frames are gone.
4050
4051 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
4052
4053 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
4054 __ pop(rdx); // No need for exception pc anymore
4055
4056 // rax: exception handler
4057
4058 // Restore SP from BP if the exception PC is a MethodHandle call site.
4059 __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0);
4060 __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
4061
4062 // We have a handler in rax (could be deopt blob).
4063 __ mov(r8, rax);
4064
4065 // Get the exception oop
4066 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
4067 // Get the exception pc in case we are deoptimized
4068 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
4069 #ifdef ASSERT
4070 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
4071 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
4072 #endif
4073 // Clear the exception oop so GC no longer processes it as a root.
4074 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
4075
4076 // rax: exception oop
4077 // r8: exception handler
4078 // rdx: exception pc
4079 // Jump to handler
4080
4081 __ jmp(r8);
4082
4083 // Make sure all code is generated
4084 masm->flush();
4085
4086 // Set exception blob
4087 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
4088 }
4089 #endif // COMPILER2