1 /* 2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "code/debugInfoRec.hpp" 28 #include "code/icBuffer.hpp" 29 #include "code/vtableStubs.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "oops/compiledICHolder.hpp" 32 #include "prims/jvmtiRedefineClassesTrace.hpp" 33 #include "runtime/sharedRuntime.hpp" 34 #include "runtime/vframeArray.hpp" 35 #include "vmreg_sparc.inline.hpp" 36 #ifdef COMPILER1 37 #include "c1/c1_Runtime1.hpp" 38 #endif 39 #ifdef COMPILER2 40 #include "opto/runtime.hpp" 41 #endif 42 #ifdef SHARK 43 #include "compiler/compileBroker.hpp" 44 #include "shark/sharkCompiler.hpp" 45 #endif 46 47 #define __ masm-> 48 49 50 class RegisterSaver { 51 52 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O. 53 // The Oregs are problematic. In the 32bit build the compiler can 54 // have O registers live with 64 bit quantities. A window save will 55 // cut the heads off of the registers. We have to do a very extensive 56 // stack dance to save and restore these properly. 57 58 // Note that the Oregs problem only exists if we block at either a polling 59 // page exception a compiled code safepoint that was not originally a call 60 // or deoptimize following one of these kinds of safepoints. 61 62 // Lots of registers to save. For all builds, a window save will preserve 63 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit 64 // builds a window-save will preserve the %o registers. In the LION build 65 // we need to save the 64-bit %o registers which requires we save them 66 // before the window-save (as then they become %i registers and get their 67 // heads chopped off on interrupt). We have to save some %g registers here 68 // as well. 69 enum { 70 // This frame's save area. Includes extra space for the native call: 71 // vararg's layout space and the like. Briefly holds the caller's 72 // register save area. 73 call_args_area = frame::register_save_words_sp_offset + 74 frame::memory_parameter_word_sp_offset*wordSize, 75 // Make sure save locations are always 8 byte aligned. 76 // can't use round_to because it doesn't produce compile time constant 77 start_of_extra_save_area = ((call_args_area + 7) & ~7), 78 g1_offset = start_of_extra_save_area, // g-regs needing saving 79 g3_offset = g1_offset+8, 80 g4_offset = g3_offset+8, 81 g5_offset = g4_offset+8, 82 o0_offset = g5_offset+8, 83 o1_offset = o0_offset+8, 84 o2_offset = o1_offset+8, 85 o3_offset = o2_offset+8, 86 o4_offset = o3_offset+8, 87 o5_offset = o4_offset+8, 88 start_of_flags_save_area = o5_offset+8, 89 ccr_offset = start_of_flags_save_area, 90 fsr_offset = ccr_offset + 8, 91 d00_offset = fsr_offset+8, // Start of float save area 92 register_save_size = d00_offset+8*32 93 }; 94 95 96 public: 97 98 static int Oexception_offset() { return o0_offset; }; 99 static int G3_offset() { return g3_offset; }; 100 static int G5_offset() { return g5_offset; }; 101 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); 102 static void restore_live_registers(MacroAssembler* masm); 103 104 // During deoptimization only the result register need to be restored 105 // all the other values have already been extracted. 106 107 static void restore_result_registers(MacroAssembler* masm); 108 }; 109 110 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { 111 // Record volatile registers as callee-save values in an OopMap so their save locations will be 112 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for 113 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers 114 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame 115 // (as the stub's I's) when the runtime routine called by the stub creates its frame. 116 int i; 117 // Always make the frame size 16 byte aligned. 118 int frame_size = round_to(additional_frame_words + register_save_size, 16); 119 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words 120 int frame_size_in_slots = frame_size / sizeof(jint); 121 // CodeBlob frame size is in words. 122 *total_frame_words = frame_size / wordSize; 123 // OopMap* map = new OopMap(*total_frame_words, 0); 124 OopMap* map = new OopMap(frame_size_in_slots, 0); 125 126 #if !defined(_LP64) 127 128 // Save 64-bit O registers; they will get their heads chopped off on a 'save'. 129 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); 130 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); 131 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); 132 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); 133 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); 134 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); 135 #endif /* _LP64 */ 136 137 __ save(SP, -frame_size, SP); 138 139 #ifndef _LP64 140 // Reload the 64 bit Oregs. Although they are now Iregs we load them 141 // to Oregs here to avoid interrupts cutting off their heads 142 143 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); 149 150 __ stx(O0, SP, o0_offset+STACK_BIAS); 151 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg()); 152 153 __ stx(O1, SP, o1_offset+STACK_BIAS); 154 155 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg()); 156 157 __ stx(O2, SP, o2_offset+STACK_BIAS); 158 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg()); 159 160 __ stx(O3, SP, o3_offset+STACK_BIAS); 161 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg()); 162 163 __ stx(O4, SP, o4_offset+STACK_BIAS); 164 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg()); 165 166 __ stx(O5, SP, o5_offset+STACK_BIAS); 167 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg()); 168 #endif /* _LP64 */ 169 170 171 #ifdef _LP64 172 int debug_offset = 0; 173 #else 174 int debug_offset = 4; 175 #endif 176 // Save the G's 177 __ stx(G1, SP, g1_offset+STACK_BIAS); 178 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg()); 179 180 __ stx(G3, SP, g3_offset+STACK_BIAS); 181 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg()); 182 183 __ stx(G4, SP, g4_offset+STACK_BIAS); 184 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg()); 185 186 __ stx(G5, SP, g5_offset+STACK_BIAS); 187 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg()); 188 189 // This is really a waste but we'll keep things as they were for now 190 if (true) { 191 #ifndef _LP64 192 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next()); 193 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next()); 194 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next()); 195 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next()); 196 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next()); 197 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next()); 198 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next()); 199 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next()); 200 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next()); 201 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next()); 202 #endif /* _LP64 */ 203 } 204 205 206 // Save the flags 207 __ rdccr( G5 ); 208 __ stx(G5, SP, ccr_offset+STACK_BIAS); 209 __ stxfsr(SP, fsr_offset+STACK_BIAS); 210 211 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles) 212 int offset = d00_offset; 213 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { 214 FloatRegister f = as_FloatRegister(i); 215 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS); 216 // Record as callee saved both halves of double registers (2 float registers). 217 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg()); 218 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next()); 219 offset += sizeof(double); 220 } 221 222 // And we're done. 223 224 return map; 225 } 226 227 228 // Pop the current frame and restore all the registers that we 229 // saved. 230 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { 231 232 // Restore all the FP registers 233 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { 234 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i)); 235 } 236 237 __ ldx(SP, ccr_offset+STACK_BIAS, G1); 238 __ wrccr (G1) ; 239 240 // Restore the G's 241 // Note that G2 (AKA GThread) must be saved and restored separately. 242 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr. 243 244 __ ldx(SP, g1_offset+STACK_BIAS, G1); 245 __ ldx(SP, g3_offset+STACK_BIAS, G3); 246 __ ldx(SP, g4_offset+STACK_BIAS, G4); 247 __ ldx(SP, g5_offset+STACK_BIAS, G5); 248 249 250 #if !defined(_LP64) 251 // Restore the 64-bit O's. 252 __ ldx(SP, o0_offset+STACK_BIAS, O0); 253 __ ldx(SP, o1_offset+STACK_BIAS, O1); 254 __ ldx(SP, o2_offset+STACK_BIAS, O2); 255 __ ldx(SP, o3_offset+STACK_BIAS, O3); 256 __ ldx(SP, o4_offset+STACK_BIAS, O4); 257 __ ldx(SP, o5_offset+STACK_BIAS, O5); 258 259 // And temporarily place them in TLS 260 261 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); 262 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); 263 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); 264 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); 265 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); 266 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); 267 #endif /* _LP64 */ 268 269 // Restore flags 270 271 __ ldxfsr(SP, fsr_offset+STACK_BIAS); 272 273 __ restore(); 274 275 #if !defined(_LP64) 276 // Now reload the 64bit Oregs after we've restore the window. 277 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); 283 #endif /* _LP64 */ 284 285 } 286 287 // Pop the current frame and restore the registers that might be holding 288 // a result. 289 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { 290 291 #if !defined(_LP64) 292 // 32bit build returns longs in G1 293 __ ldx(SP, g1_offset+STACK_BIAS, G1); 294 295 // Retrieve the 64-bit O's. 296 __ ldx(SP, o0_offset+STACK_BIAS, O0); 297 __ ldx(SP, o1_offset+STACK_BIAS, O1); 298 // and save to TLS 299 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); 300 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); 301 #endif /* _LP64 */ 302 303 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0)); 304 305 __ restore(); 306 307 #if !defined(_LP64) 308 // Now reload the 64bit Oregs after we've restore the window. 309 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); 311 #endif /* _LP64 */ 312 313 } 314 315 // Is vector's size (in bytes) bigger than a size saved by default? 316 // 8 bytes FP registers are saved by default on SPARC. 317 bool SharedRuntime::is_wide_vector(int size) { 318 // Note, MaxVectorSize == 8 on SPARC. 319 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size)); 320 return size > 8; 321 } 322 323 // The java_calling_convention describes stack locations as ideal slots on 324 // a frame with no abi restrictions. Since we must observe abi restrictions 325 // (like the placement of the register window) the slots must be biased by 326 // the following value. 327 static int reg2offset(VMReg r) { 328 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 329 } 330 331 static VMRegPair reg64_to_VMRegPair(Register r) { 332 VMRegPair ret; 333 if (wordSize == 8) { 334 ret.set2(r->as_VMReg()); 335 } else { 336 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg()); 337 } 338 return ret; 339 } 340 341 // --------------------------------------------------------------------------- 342 // Read the array of BasicTypes from a signature, and compute where the 343 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size) 344 // quantities. Values less than VMRegImpl::stack0 are registers, those above 345 // refer to 4-byte stack slots. All stack slots are based off of the window 346 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window, 347 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register 348 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit 349 // integer registers. Values 64-95 are the (32-bit only) float registers. 350 // Each 32-bit quantity is given its own number, so the integer registers 351 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is 352 // an O0-low and an O0-high. Essentially, all int register numbers are doubled. 353 354 // Register results are passed in O0-O5, for outgoing call arguments. To 355 // convert to incoming arguments, convert all O's to I's. The regs array 356 // refer to the low and hi 32-bit words of 64-bit registers or stack slots. 357 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a 358 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was 359 // passed (used as a placeholder for the other half of longs and doubles in 360 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is 361 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention). 362 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first() 363 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the 364 // same VMRegPair. 365 366 // Note: the INPUTS in sig_bt are in units of Java argument words, which are 367 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit 368 // units regardless of build. 369 370 371 // --------------------------------------------------------------------------- 372 // The compiled Java calling convention. The Java convention always passes 373 // 64-bit values in adjacent aligned locations (either registers or stack), 374 // floats in float registers and doubles in aligned float pairs. There is 375 // no backing varargs store for values in registers. 376 // In the 32-bit build, longs are passed on the stack (cannot be 377 // passed in I's, because longs in I's get their heads chopped off at 378 // interrupt). 379 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, 380 VMRegPair *regs, 381 int total_args_passed, 382 int is_outgoing) { 383 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); 384 385 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; 386 const int flt_reg_max = 8; 387 388 int int_reg = 0; 389 int flt_reg = 0; 390 int slot = 0; 391 392 for (int i = 0; i < total_args_passed; i++) { 393 switch (sig_bt[i]) { 394 case T_INT: 395 case T_SHORT: 396 case T_CHAR: 397 case T_BYTE: 398 case T_BOOLEAN: 399 #ifndef _LP64 400 case T_OBJECT: 401 case T_ARRAY: 402 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address 403 #endif // _LP64 404 if (int_reg < int_reg_max) { 405 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); 406 regs[i].set1(r->as_VMReg()); 407 } else { 408 regs[i].set1(VMRegImpl::stack2reg(slot++)); 409 } 410 break; 411 412 #ifdef _LP64 413 case T_LONG: 414 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); 415 // fall-through 416 case T_OBJECT: 417 case T_ARRAY: 418 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address 419 if (int_reg < int_reg_max) { 420 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); 421 regs[i].set2(r->as_VMReg()); 422 } else { 423 slot = round_to(slot, 2); // align 424 regs[i].set2(VMRegImpl::stack2reg(slot)); 425 slot += 2; 426 } 427 break; 428 #else 429 case T_LONG: 430 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); 431 // On 32-bit SPARC put longs always on the stack to keep the pressure off 432 // integer argument registers. They should be used for oops. 433 slot = round_to(slot, 2); // align 434 regs[i].set2(VMRegImpl::stack2reg(slot)); 435 slot += 2; 436 #endif 437 break; 438 439 case T_FLOAT: 440 if (flt_reg < flt_reg_max) { 441 FloatRegister r = as_FloatRegister(flt_reg++); 442 regs[i].set1(r->as_VMReg()); 443 } else { 444 regs[i].set1(VMRegImpl::stack2reg(slot++)); 445 } 446 break; 447 448 case T_DOUBLE: 449 assert(sig_bt[i+1] == T_VOID, "expecting half"); 450 if (round_to(flt_reg, 2) + 1 < flt_reg_max) { 451 flt_reg = round_to(flt_reg, 2); // align 452 FloatRegister r = as_FloatRegister(flt_reg); 453 regs[i].set2(r->as_VMReg()); 454 flt_reg += 2; 455 } else { 456 slot = round_to(slot, 2); // align 457 regs[i].set2(VMRegImpl::stack2reg(slot)); 458 slot += 2; 459 } 460 break; 461 462 case T_VOID: 463 regs[i].set_bad(); // Halves of longs & doubles 464 break; 465 466 default: 467 fatal(err_msg_res("unknown basic type %d", sig_bt[i])); 468 break; 469 } 470 } 471 472 // retun the amount of stack space these arguments will need. 473 return slot; 474 } 475 476 // Helper class mostly to avoid passing masm everywhere, and handle 477 // store displacement overflow logic. 478 class AdapterGenerator { 479 MacroAssembler *masm; 480 Register Rdisp; 481 void set_Rdisp(Register r) { Rdisp = r; } 482 483 void patch_callers_callsite(); 484 485 // base+st_off points to top of argument 486 int arg_offset(const int st_off) { return st_off; } 487 int next_arg_offset(const int st_off) { 488 return st_off - Interpreter::stackElementSize; 489 } 490 491 // Argument slot values may be loaded first into a register because 492 // they might not fit into displacement. 493 RegisterOrConstant arg_slot(const int st_off); 494 RegisterOrConstant next_arg_slot(const int st_off); 495 496 // Stores long into offset pointed to by base 497 void store_c2i_long(Register r, Register base, 498 const int st_off, bool is_stack); 499 void store_c2i_object(Register r, Register base, 500 const int st_off); 501 void store_c2i_int(Register r, Register base, 502 const int st_off); 503 void store_c2i_double(VMReg r_2, 504 VMReg r_1, Register base, const int st_off); 505 void store_c2i_float(FloatRegister f, Register base, 506 const int st_off); 507 508 public: 509 void gen_c2i_adapter(int total_args_passed, 510 // VMReg max_arg, 511 int comp_args_on_stack, // VMRegStackSlots 512 const BasicType *sig_bt, 513 const VMRegPair *regs, 514 Label& skip_fixup); 515 void gen_i2c_adapter(int total_args_passed, 516 // VMReg max_arg, 517 int comp_args_on_stack, // VMRegStackSlots 518 const BasicType *sig_bt, 519 const VMRegPair *regs); 520 521 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} 522 }; 523 524 525 // Patch the callers callsite with entry to compiled code if it exists. 526 void AdapterGenerator::patch_callers_callsite() { 527 Label L; 528 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); 529 __ br_null(G3_scratch, false, Assembler::pt, L); 530 __ delayed()->nop(); 531 // Call into the VM to patch the caller, then jump to compiled callee 532 __ save_frame(4); // Args in compiled layout; do not blow them 533 534 // Must save all the live Gregs the list is: 535 // G1: 1st Long arg (32bit build) 536 // G2: global allocated to TLS 537 // G3: used in inline cache check (scratch) 538 // G4: 2nd Long arg (32bit build); 539 // G5: used in inline cache check (Method*) 540 541 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops. 542 543 #ifdef _LP64 544 // mov(s,d) 545 __ mov(G1, L1); 546 __ mov(G4, L4); 547 __ mov(G5_method, L5); 548 __ mov(G5_method, O0); // VM needs target method 549 __ mov(I7, O1); // VM needs caller's callsite 550 // Must be a leaf call... 551 // can be very far once the blob has been relocated 552 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)); 553 __ relocate(relocInfo::runtime_call_type); 554 __ jumpl_to(dest, O7, O7); 555 __ delayed()->mov(G2_thread, L7_thread_cache); 556 __ mov(L7_thread_cache, G2_thread); 557 __ mov(L1, G1); 558 __ mov(L4, G4); 559 __ mov(L5, G5_method); 560 #else 561 __ stx(G1, FP, -8 + STACK_BIAS); 562 __ stx(G4, FP, -16 + STACK_BIAS); 563 __ mov(G5_method, L5); 564 __ mov(G5_method, O0); // VM needs target method 565 __ mov(I7, O1); // VM needs caller's callsite 566 // Must be a leaf call... 567 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type); 568 __ delayed()->mov(G2_thread, L7_thread_cache); 569 __ mov(L7_thread_cache, G2_thread); 570 __ ldx(FP, -8 + STACK_BIAS, G1); 571 __ ldx(FP, -16 + STACK_BIAS, G4); 572 __ mov(L5, G5_method); 573 #endif /* _LP64 */ 574 575 __ restore(); // Restore args 576 __ bind(L); 577 } 578 579 580 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) { 581 RegisterOrConstant roc(arg_offset(st_off)); 582 return __ ensure_simm13_or_reg(roc, Rdisp); 583 } 584 585 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) { 586 RegisterOrConstant roc(next_arg_offset(st_off)); 587 return __ ensure_simm13_or_reg(roc, Rdisp); 588 } 589 590 591 // Stores long into offset pointed to by base 592 void AdapterGenerator::store_c2i_long(Register r, Register base, 593 const int st_off, bool is_stack) { 594 #ifdef _LP64 595 // In V9, longs are given 2 64-bit slots in the interpreter, but the 596 // data is passed in only 1 slot. 597 __ stx(r, base, next_arg_slot(st_off)); 598 #else 599 #ifdef COMPILER2 600 // Misaligned store of 64-bit data 601 __ stw(r, base, arg_slot(st_off)); // lo bits 602 __ srlx(r, 32, r); 603 __ stw(r, base, next_arg_slot(st_off)); // hi bits 604 #else 605 if (is_stack) { 606 // Misaligned store of 64-bit data 607 __ stw(r, base, arg_slot(st_off)); // lo bits 608 __ srlx(r, 32, r); 609 __ stw(r, base, next_arg_slot(st_off)); // hi bits 610 } else { 611 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits 612 __ stw(r , base, next_arg_slot(st_off)); // hi bits 613 } 614 #endif // COMPILER2 615 #endif // _LP64 616 } 617 618 void AdapterGenerator::store_c2i_object(Register r, Register base, 619 const int st_off) { 620 __ st_ptr (r, base, arg_slot(st_off)); 621 } 622 623 void AdapterGenerator::store_c2i_int(Register r, Register base, 624 const int st_off) { 625 __ st (r, base, arg_slot(st_off)); 626 } 627 628 // Stores into offset pointed to by base 629 void AdapterGenerator::store_c2i_double(VMReg r_2, 630 VMReg r_1, Register base, const int st_off) { 631 #ifdef _LP64 632 // In V9, doubles are given 2 64-bit slots in the interpreter, but the 633 // data is passed in only 1 slot. 634 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); 635 #else 636 // Need to marshal 64-bit value from misaligned Lesp loads 637 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); 638 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) ); 639 #endif 640 } 641 642 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, 643 const int st_off) { 644 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off)); 645 } 646 647 void AdapterGenerator::gen_c2i_adapter( 648 int total_args_passed, 649 // VMReg max_arg, 650 int comp_args_on_stack, // VMRegStackSlots 651 const BasicType *sig_bt, 652 const VMRegPair *regs, 653 Label& L_skip_fixup) { 654 655 // Before we get into the guts of the C2I adapter, see if we should be here 656 // at all. We've come from compiled code and are attempting to jump to the 657 // interpreter, which means the caller made a static call to get here 658 // (vcalls always get a compiled target if there is one). Check for a 659 // compiled target. If there is one, we need to patch the caller's call. 660 // However we will run interpreted if we come thru here. The next pass 661 // thru the call site will run compiled. If we ran compiled here then 662 // we can (theorectically) do endless i2c->c2i->i2c transitions during 663 // deopt/uncommon trap cycles. If we always go interpreted here then 664 // we can have at most one and don't need to play any tricks to keep 665 // from endlessly growing the stack. 666 // 667 // Actually if we detected that we had an i2c->c2i transition here we 668 // ought to be able to reset the world back to the state of the interpreted 669 // call and not bother building another interpreter arg area. We don't 670 // do that at this point. 671 672 patch_callers_callsite(); 673 674 __ bind(L_skip_fixup); 675 676 // Since all args are passed on the stack, total_args_passed*wordSize is the 677 // space we need. Add in varargs area needed by the interpreter. Round up 678 // to stack alignment. 679 const int arg_size = total_args_passed * Interpreter::stackElementSize; 680 const int varargs_area = 681 (frame::varargs_offset - frame::register_save_words)*wordSize; 682 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); 683 684 const int bias = STACK_BIAS; 685 const int interp_arg_offset = frame::varargs_offset*wordSize + 686 (total_args_passed-1)*Interpreter::stackElementSize; 687 688 const Register base = SP; 689 690 // Make some extra space on the stack. 691 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP); 692 set_Rdisp(G3_scratch); 693 694 // Write the args into the outgoing interpreter space. 695 for (int i = 0; i < total_args_passed; i++) { 696 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; 697 VMReg r_1 = regs[i].first(); 698 VMReg r_2 = regs[i].second(); 699 if (!r_1->is_valid()) { 700 assert(!r_2->is_valid(), ""); 701 continue; 702 } 703 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 704 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias; 705 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp); 706 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle 707 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); 708 else __ ldx(base, ld_off, G1_scratch); 709 } 710 711 if (r_1->is_Register()) { 712 Register r = r_1->as_Register()->after_restore(); 713 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { 714 store_c2i_object(r, base, st_off); 715 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { 716 store_c2i_long(r, base, st_off, r_2->is_stack()); 717 } else { 718 store_c2i_int(r, base, st_off); 719 } 720 } else { 721 assert(r_1->is_FloatRegister(), ""); 722 if (sig_bt[i] == T_FLOAT) { 723 store_c2i_float(r_1->as_FloatRegister(), base, st_off); 724 } else { 725 assert(sig_bt[i] == T_DOUBLE, "wrong type"); 726 store_c2i_double(r_2, r_1, base, st_off); 727 } 728 } 729 } 730 731 // Load the interpreter entry point. 732 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); 733 734 // Pass O5_savedSP as an argument to the interpreter. 735 // The interpreter will restore SP to this value before returning. 736 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP); 737 738 __ mov((frame::varargs_offset)*wordSize - 739 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); 740 // Jump to the interpreter just as if interpreter was doing it. 741 __ jmpl(G3_scratch, 0, G0); 742 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp 743 // (really L0) is in use by the compiled frame as a generic temp. However, 744 // the interpreter does not know where its args are without some kind of 745 // arg pointer being passed in. Pass it in Gargs. 746 __ delayed()->add(SP, G1, Gargs); 747 } 748 749 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg, 750 address code_start, address code_end, 751 Label& L_ok) { 752 Label L_fail; 753 __ set(ExternalAddress(code_start), temp_reg); 754 __ set(pointer_delta(code_end, code_start, 1), temp2_reg); 755 __ cmp(pc_reg, temp_reg); 756 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail); 757 __ delayed()->add(temp_reg, temp2_reg, temp_reg); 758 __ cmp(pc_reg, temp_reg); 759 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok); 760 __ bind(L_fail); 761 } 762 763 void AdapterGenerator::gen_i2c_adapter( 764 int total_args_passed, 765 // VMReg max_arg, 766 int comp_args_on_stack, // VMRegStackSlots 767 const BasicType *sig_bt, 768 const VMRegPair *regs) { 769 770 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame 771 // layout. Lesp was saved by the calling I-frame and will be restored on 772 // return. Meanwhile, outgoing arg space is all owned by the callee 773 // C-frame, so we can mangle it at will. After adjusting the frame size, 774 // hoist register arguments and repack other args according to the compiled 775 // code convention. Finally, end in a jump to the compiled code. The entry 776 // point address is the start of the buffer. 777 778 // We will only enter here from an interpreted frame and never from after 779 // passing thru a c2i. Azul allowed this but we do not. If we lose the 780 // race and use a c2i we will remain interpreted for the race loser(s). 781 // This removes all sorts of headaches on the x86 side and also eliminates 782 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. 783 784 // More detail: 785 // Adapters can be frameless because they do not require the caller 786 // to perform additional cleanup work, such as correcting the stack pointer. 787 // An i2c adapter is frameless because the *caller* frame, which is interpreted, 788 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), 789 // even if a callee has modified the stack pointer. 790 // A c2i adapter is frameless because the *callee* frame, which is interpreted, 791 // routinely repairs its caller's stack pointer (from sender_sp, which is set 792 // up via the senderSP register). 793 // In other words, if *either* the caller or callee is interpreted, we can 794 // get the stack pointer repaired after a call. 795 // This is why c2i and i2c adapters cannot be indefinitely composed. 796 // In particular, if a c2i adapter were to somehow call an i2c adapter, 797 // both caller and callee would be compiled methods, and neither would 798 // clean up the stack pointer changes performed by the two adapters. 799 // If this happens, control eventually transfers back to the compiled 800 // caller, but with an uncorrected stack, causing delayed havoc. 801 802 if (VerifyAdapterCalls && 803 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { 804 // So, let's test for cascading c2i/i2c adapters right now. 805 // assert(Interpreter::contains($return_addr) || 806 // StubRoutines::contains($return_addr), 807 // "i2c adapter must return to an interpreter frame"); 808 __ block_comment("verify_i2c { "); 809 Label L_ok; 810 if (Interpreter::code() != NULL) 811 range_check(masm, O7, O0, O1, 812 Interpreter::code()->code_start(), Interpreter::code()->code_end(), 813 L_ok); 814 if (StubRoutines::code1() != NULL) 815 range_check(masm, O7, O0, O1, 816 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), 817 L_ok); 818 if (StubRoutines::code2() != NULL) 819 range_check(masm, O7, O0, O1, 820 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), 821 L_ok); 822 const char* msg = "i2c adapter must return to an interpreter frame"; 823 __ block_comment(msg); 824 __ stop(msg); 825 __ bind(L_ok); 826 __ block_comment("} verify_i2ce "); 827 } 828 829 // As you can see from the list of inputs & outputs there are not a lot 830 // of temp registers to work with: mostly G1, G3 & G4. 831 832 // Inputs: 833 // G2_thread - TLS 834 // G5_method - Method oop 835 // G4 (Gargs) - Pointer to interpreter's args 836 // O0..O4 - free for scratch 837 // O5_savedSP - Caller's saved SP, to be restored if needed 838 // O6 - Current SP! 839 // O7 - Valid return address 840 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) 841 842 // Outputs: 843 // G2_thread - TLS 844 // O0-O5 - Outgoing args in compiled layout 845 // O6 - Adjusted or restored SP 846 // O7 - Valid return address 847 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) 848 // F0-F7 - more outgoing args 849 850 851 // Gargs is the incoming argument base, and also an outgoing argument. 852 __ sub(Gargs, BytesPerWord, Gargs); 853 854 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME 855 // WITH O7 HOLDING A VALID RETURN PC 856 // 857 // | | 858 // : java stack : 859 // | | 860 // +--------------+ <--- start of outgoing args 861 // | receiver | | 862 // : rest of args : |---size is java-arg-words 863 // | | | 864 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I 865 // | | | 866 // : unused : |---Space for max Java stack, plus stack alignment 867 // | | | 868 // +--------------+ <--- SP + 16*wordsize 869 // | | 870 // : window : 871 // | | 872 // +--------------+ <--- SP 873 874 // WE REPACK THE STACK. We use the common calling convention layout as 875 // discovered by calling SharedRuntime::calling_convention. We assume it 876 // causes an arbitrary shuffle of memory, which may require some register 877 // temps to do the shuffle. We hope for (and optimize for) the case where 878 // temps are not needed. We may have to resize the stack slightly, in case 879 // we need alignment padding (32-bit interpreter can pass longs & doubles 880 // misaligned, but the compilers expect them aligned). 881 // 882 // | | 883 // : java stack : 884 // | | 885 // +--------------+ <--- start of outgoing args 886 // | pad, align | | 887 // +--------------+ | 888 // | ints, longs, | | 889 // | floats, | |---Outgoing stack args. 890 // : doubles : | First few args in registers. 891 // | | | 892 // +--------------+ <--- SP' + 16*wordsize 893 // | | 894 // : window : 895 // | | 896 // +--------------+ <--- SP' 897 898 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME 899 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP 900 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. 901 902 // Cut-out for having no stack args. Since up to 6 args are passed 903 // in registers, we will commonly have no stack args. 904 if (comp_args_on_stack > 0) { 905 // Convert VMReg stack slots to words. 906 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; 907 // Round up to miminum stack alignment, in wordSize 908 comp_words_on_stack = round_to(comp_words_on_stack, 2); 909 // Now compute the distance from Lesp to SP. This calculation does not 910 // include the space for total_args_passed because Lesp has not yet popped 911 // the arguments. 912 __ sub(SP, (comp_words_on_stack)*wordSize, SP); 913 } 914 915 // Now generate the shuffle code. Pick up all register args and move the 916 // rest through G1_scratch. 917 for (int i = 0; i < total_args_passed; i++) { 918 if (sig_bt[i] == T_VOID) { 919 // Longs and doubles are passed in native word order, but misaligned 920 // in the 32-bit build. 921 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 922 continue; 923 } 924 925 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the 926 // 32-bit build and aligned in the 64-bit build. Look for the obvious 927 // ldx/lddf optimizations. 928 929 // Load in argument order going down. 930 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; 931 set_Rdisp(G1_scratch); 932 933 VMReg r_1 = regs[i].first(); 934 VMReg r_2 = regs[i].second(); 935 if (!r_1->is_valid()) { 936 assert(!r_2->is_valid(), ""); 937 continue; 938 } 939 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9 940 r_1 = F8->as_VMReg(); // as part of the load/store shuffle 941 if (r_2->is_valid()) r_2 = r_1->next(); 942 } 943 if (r_1->is_Register()) { // Register argument 944 Register r = r_1->as_Register()->after_restore(); 945 if (!r_2->is_valid()) { 946 __ ld(Gargs, arg_slot(ld_off), r); 947 } else { 948 #ifdef _LP64 949 // In V9, longs are given 2 64-bit slots in the interpreter, but the 950 // data is passed in only 1 slot. 951 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? 952 next_arg_slot(ld_off) : arg_slot(ld_off); 953 __ ldx(Gargs, slot, r); 954 #else 955 fatal("longs should be on stack"); 956 #endif 957 } 958 } else { 959 assert(r_1->is_FloatRegister(), ""); 960 if (!r_2->is_valid()) { 961 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); 962 } else { 963 #ifdef _LP64 964 // In V9, doubles are given 2 64-bit slots in the interpreter, but the 965 // data is passed in only 1 slot. This code also handles longs that 966 // are passed on the stack, but need a stack-to-stack move through a 967 // spare float register. 968 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? 969 next_arg_slot(ld_off) : arg_slot(ld_off); 970 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); 971 #else 972 // Need to marshal 64-bit value from misaligned Lesp loads 973 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); 974 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); 975 #endif 976 } 977 } 978 // Was the argument really intended to be on the stack, but was loaded 979 // into F8/F9? 980 if (regs[i].first()->is_stack()) { 981 assert(r_1->as_FloatRegister() == F8, "fix this code"); 982 // Convert stack slot to an SP offset 983 int st_off = reg2offset(regs[i].first()) + STACK_BIAS; 984 // Store down the shuffled stack word. Target address _is_ aligned. 985 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); 986 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); 987 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); 988 } 989 } 990 991 // Jump to the compiled code just as if compiled code was doing it. 992 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); 993 994 // 6243940 We might end up in handle_wrong_method if 995 // the callee is deoptimized as we race thru here. If that 996 // happens we don't want to take a safepoint because the 997 // caller frame will look interpreted and arguments are now 998 // "compiled" so it is much better to make this transition 999 // invisible to the stack walking code. Unfortunately if 1000 // we try and find the callee by normal means a safepoint 1001 // is possible. So we stash the desired callee in the thread 1002 // and the vm will find there should this case occur. 1003 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); 1004 __ st_ptr(G5_method, callee_target_addr); 1005 1006 if (StressNonEntrant) { 1007 // Open a big window for deopt failure 1008 __ save_frame(0); 1009 __ mov(G0, L0); 1010 Label loop; 1011 __ bind(loop); 1012 __ sub(L0, 1, L0); 1013 __ br_null_short(L0, Assembler::pt, loop); 1014 __ restore(); 1015 } 1016 1017 __ jmpl(G3, 0, G0); 1018 __ delayed()->nop(); 1019 } 1020 1021 // --------------------------------------------------------------- 1022 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, 1023 int total_args_passed, 1024 // VMReg max_arg, 1025 int comp_args_on_stack, // VMRegStackSlots 1026 const BasicType *sig_bt, 1027 const VMRegPair *regs, 1028 AdapterFingerPrint* fingerprint) { 1029 address i2c_entry = __ pc(); 1030 1031 AdapterGenerator agen(masm); 1032 1033 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs); 1034 1035 1036 // ------------------------------------------------------------------------- 1037 // Generate a C2I adapter. On entry we know G5 holds the Method*. The 1038 // args start out packed in the compiled layout. They need to be unpacked 1039 // into the interpreter layout. This will almost always require some stack 1040 // space. We grow the current (compiled) stack, then repack the args. We 1041 // finally end in a jump to the generic interpreter entry point. On exit 1042 // from the interpreter, the interpreter will restore our SP (lest the 1043 // compiled code, which relys solely on SP and not FP, get sick). 1044 1045 address c2i_unverified_entry = __ pc(); 1046 Label L_skip_fixup; 1047 { 1048 Register R_temp = G1; // another scratch register 1049 1050 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); 1051 1052 __ verify_oop(O0); 1053 __ load_klass(O0, G3_scratch); 1054 1055 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); 1056 __ cmp(G3_scratch, R_temp); 1057 1058 Label ok, ok2; 1059 __ brx(Assembler::equal, false, Assembler::pt, ok); 1060 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); 1061 __ jump_to(ic_miss, G3_scratch); 1062 __ delayed()->nop(); 1063 1064 __ bind(ok); 1065 // Method might have been compiled since the call site was patched to 1066 // interpreted if that is the case treat it as a miss so we can get 1067 // the call site corrected. 1068 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); 1069 __ bind(ok2); 1070 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup); 1071 __ delayed()->nop(); 1072 __ jump_to(ic_miss, G3_scratch); 1073 __ delayed()->nop(); 1074 1075 } 1076 1077 address c2i_entry = __ pc(); 1078 1079 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup); 1080 1081 __ flush(); 1082 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); 1083 1084 } 1085 1086 // Helper function for native calling conventions 1087 static VMReg int_stk_helper( int i ) { 1088 // Bias any stack based VMReg we get by ignoring the window area 1089 // but not the register parameter save area. 1090 // 1091 // This is strange for the following reasons. We'd normally expect 1092 // the calling convention to return an VMReg for a stack slot 1093 // completely ignoring any abi reserved area. C2 thinks of that 1094 // abi area as only out_preserve_stack_slots. This does not include 1095 // the area allocated by the C abi to store down integer arguments 1096 // because the java calling convention does not use it. So 1097 // since c2 assumes that there are only out_preserve_stack_slots 1098 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack 1099 // location the c calling convention must add in this bias amount 1100 // to make up for the fact that the out_preserve_stack_slots is 1101 // insufficient for C calls. What a mess. I sure hope those 6 1102 // stack words were worth it on every java call! 1103 1104 // Another way of cleaning this up would be for out_preserve_stack_slots 1105 // to take a parameter to say whether it was C or java calling conventions. 1106 // Then things might look a little better (but not much). 1107 1108 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM; 1109 if( mem_parm_offset < 0 ) { 1110 return as_oRegister(i)->as_VMReg(); 1111 } else { 1112 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word; 1113 // Now return a biased offset that will be correct when out_preserve_slots is added back in 1114 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots()); 1115 } 1116 } 1117 1118 1119 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, 1120 VMRegPair *regs, 1121 int total_args_passed) { 1122 1123 // Return the number of VMReg stack_slots needed for the args. 1124 // This value does not include an abi space (like register window 1125 // save area). 1126 1127 // The native convention is V8 if !LP64 1128 // The LP64 convention is the V9 convention which is slightly more sane. 1129 1130 // We return the amount of VMReg stack slots we need to reserve for all 1131 // the arguments NOT counting out_preserve_stack_slots. Since we always 1132 // have space for storing at least 6 registers to memory we start with that. 1133 // See int_stk_helper for a further discussion. 1134 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots(); 1135 1136 #ifdef _LP64 1137 // V9 convention: All things "as-if" on double-wide stack slots. 1138 // Hoist any int/ptr/long's in the first 6 to int regs. 1139 // Hoist any flt/dbl's in the first 16 dbl regs. 1140 int j = 0; // Count of actual args, not HALVES 1141 for( int i=0; i<total_args_passed; i++, j++ ) { 1142 switch( sig_bt[i] ) { 1143 case T_BOOLEAN: 1144 case T_BYTE: 1145 case T_CHAR: 1146 case T_INT: 1147 case T_SHORT: 1148 regs[i].set1( int_stk_helper( j ) ); break; 1149 case T_LONG: 1150 assert( sig_bt[i+1] == T_VOID, "expecting half" ); 1151 case T_ADDRESS: // raw pointers, like current thread, for VM calls 1152 case T_ARRAY: 1153 case T_OBJECT: 1154 case T_METADATA: 1155 regs[i].set2( int_stk_helper( j ) ); 1156 break; 1157 case T_FLOAT: 1158 if ( j < 16 ) { 1159 // V9ism: floats go in ODD registers 1160 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg()); 1161 } else { 1162 // V9ism: floats go in ODD stack slot 1163 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1))); 1164 } 1165 break; 1166 case T_DOUBLE: 1167 assert( sig_bt[i+1] == T_VOID, "expecting half" ); 1168 if ( j < 16 ) { 1169 // V9ism: doubles go in EVEN/ODD regs 1170 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg()); 1171 } else { 1172 // V9ism: doubles go in EVEN/ODD stack slots 1173 regs[i].set2(VMRegImpl::stack2reg(j<<1)); 1174 } 1175 break; 1176 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES 1177 default: 1178 ShouldNotReachHere(); 1179 } 1180 if (regs[i].first()->is_stack()) { 1181 int off = regs[i].first()->reg2stack(); 1182 if (off > max_stack_slots) max_stack_slots = off; 1183 } 1184 if (regs[i].second()->is_stack()) { 1185 int off = regs[i].second()->reg2stack(); 1186 if (off > max_stack_slots) max_stack_slots = off; 1187 } 1188 } 1189 1190 #else // _LP64 1191 // V8 convention: first 6 things in O-regs, rest on stack. 1192 // Alignment is willy-nilly. 1193 for( int i=0; i<total_args_passed; i++ ) { 1194 switch( sig_bt[i] ) { 1195 case T_ADDRESS: // raw pointers, like current thread, for VM calls 1196 case T_ARRAY: 1197 case T_BOOLEAN: 1198 case T_BYTE: 1199 case T_CHAR: 1200 case T_FLOAT: 1201 case T_INT: 1202 case T_OBJECT: 1203 case T_METADATA: 1204 case T_SHORT: 1205 regs[i].set1( int_stk_helper( i ) ); 1206 break; 1207 case T_DOUBLE: 1208 case T_LONG: 1209 assert( sig_bt[i+1] == T_VOID, "expecting half" ); 1210 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) ); 1211 break; 1212 case T_VOID: regs[i].set_bad(); break; 1213 default: 1214 ShouldNotReachHere(); 1215 } 1216 if (regs[i].first()->is_stack()) { 1217 int off = regs[i].first()->reg2stack(); 1218 if (off > max_stack_slots) max_stack_slots = off; 1219 } 1220 if (regs[i].second()->is_stack()) { 1221 int off = regs[i].second()->reg2stack(); 1222 if (off > max_stack_slots) max_stack_slots = off; 1223 } 1224 } 1225 #endif // _LP64 1226 1227 return round_to(max_stack_slots + 1, 2); 1228 1229 } 1230 1231 // Do we need to convert ints to longs for c calls? 1232 bool SharedRuntime::c_calling_convention_requires_ints_as_longs() { 1233 return false; 1234 } 1235 1236 // --------------------------------------------------------------------------- 1237 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1238 switch (ret_type) { 1239 case T_FLOAT: 1240 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS); 1241 break; 1242 case T_DOUBLE: 1243 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS); 1244 break; 1245 } 1246 } 1247 1248 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1249 switch (ret_type) { 1250 case T_FLOAT: 1251 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0); 1252 break; 1253 case T_DOUBLE: 1254 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0); 1255 break; 1256 } 1257 } 1258 1259 // Check and forward and pending exception. Thread is stored in 1260 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there 1261 // is no exception handler. We merely pop this frame off and throw the 1262 // exception in the caller's frame. 1263 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) { 1264 Label L; 1265 __ br_null(Rex_oop, false, Assembler::pt, L); 1266 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception 1267 // Since this is a native call, we *know* the proper exception handler 1268 // without calling into the VM: it's the empty function. Just pop this 1269 // frame and then jump to forward_exception_entry; O7 will contain the 1270 // native caller's return PC. 1271 AddressLiteral exception_entry(StubRoutines::forward_exception_entry()); 1272 __ jump_to(exception_entry, G3_scratch); 1273 __ delayed()->restore(); // Pop this frame off. 1274 __ bind(L); 1275 } 1276 1277 // A simple move of integer like type 1278 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1279 if (src.first()->is_stack()) { 1280 if (dst.first()->is_stack()) { 1281 // stack to stack 1282 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1283 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1284 } else { 1285 // stack to reg 1286 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1287 } 1288 } else if (dst.first()->is_stack()) { 1289 // reg to stack 1290 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1291 } else { 1292 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1293 } 1294 } 1295 1296 // On 64 bit we will store integer like items to the stack as 1297 // 64 bits items (sparc abi) even though java would only store 1298 // 32bits for a parameter. On 32bit it will simply be 32 bits 1299 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 1300 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1301 if (src.first()->is_stack()) { 1302 if (dst.first()->is_stack()) { 1303 // stack to stack 1304 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1305 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1306 } else { 1307 // stack to reg 1308 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1309 } 1310 } else if (dst.first()->is_stack()) { 1311 // reg to stack 1312 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1313 } else { 1314 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1315 } 1316 } 1317 1318 1319 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1320 if (src.first()->is_stack()) { 1321 if (dst.first()->is_stack()) { 1322 // stack to stack 1323 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1324 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1325 } else { 1326 // stack to reg 1327 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1328 } 1329 } else if (dst.first()->is_stack()) { 1330 // reg to stack 1331 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1332 } else { 1333 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1334 } 1335 } 1336 1337 1338 // An oop arg. Must pass a handle not the oop itself 1339 static void object_move(MacroAssembler* masm, 1340 OopMap* map, 1341 int oop_handle_offset, 1342 int framesize_in_slots, 1343 VMRegPair src, 1344 VMRegPair dst, 1345 bool is_receiver, 1346 int* receiver_offset) { 1347 1348 // must pass a handle. First figure out the location we use as a handle 1349 1350 if (src.first()->is_stack()) { 1351 // Oop is already on the stack 1352 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register(); 1353 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle); 1354 __ ld_ptr(rHandle, 0, L4); 1355 #ifdef _LP64 1356 __ movr( Assembler::rc_z, L4, G0, rHandle ); 1357 #else 1358 __ tst( L4 ); 1359 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); 1360 #endif 1361 if (dst.first()->is_stack()) { 1362 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); 1363 } 1364 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1365 if (is_receiver) { 1366 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 1367 } 1368 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 1369 } else { 1370 // Oop is in an input register pass we must flush it to the stack 1371 const Register rOop = src.first()->as_Register(); 1372 const Register rHandle = L5; 1373 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset; 1374 int offset = oop_slot*VMRegImpl::stack_slot_size; 1375 Label skip; 1376 __ st_ptr(rOop, SP, offset + STACK_BIAS); 1377 if (is_receiver) { 1378 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size; 1379 } 1380 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 1381 __ add(SP, offset + STACK_BIAS, rHandle); 1382 #ifdef _LP64 1383 __ movr( Assembler::rc_z, rOop, G0, rHandle ); 1384 #else 1385 __ tst( rOop ); 1386 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); 1387 #endif 1388 1389 if (dst.first()->is_stack()) { 1390 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); 1391 } else { 1392 __ mov(rHandle, dst.first()->as_Register()); 1393 } 1394 } 1395 } 1396 1397 // A float arg may have to do float reg int reg conversion 1398 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1399 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 1400 1401 if (src.first()->is_stack()) { 1402 if (dst.first()->is_stack()) { 1403 // stack to stack the easiest of the bunch 1404 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1405 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1406 } else { 1407 // stack to reg 1408 if (dst.first()->is_Register()) { 1409 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1410 } else { 1411 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); 1412 } 1413 } 1414 } else if (dst.first()->is_stack()) { 1415 // reg to stack 1416 if (src.first()->is_Register()) { 1417 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1418 } else { 1419 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); 1420 } 1421 } else { 1422 // reg to reg 1423 if (src.first()->is_Register()) { 1424 if (dst.first()->is_Register()) { 1425 // gpr -> gpr 1426 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1427 } else { 1428 // gpr -> fpr 1429 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS); 1430 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister()); 1431 } 1432 } else if (dst.first()->is_Register()) { 1433 // fpr -> gpr 1434 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS); 1435 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register()); 1436 } else { 1437 // fpr -> fpr 1438 // In theory these overlap but the ordering is such that this is likely a nop 1439 if ( src.first() != dst.first()) { 1440 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); 1441 } 1442 } 1443 } 1444 } 1445 1446 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1447 VMRegPair src_lo(src.first()); 1448 VMRegPair src_hi(src.second()); 1449 VMRegPair dst_lo(dst.first()); 1450 VMRegPair dst_hi(dst.second()); 1451 simple_move32(masm, src_lo, dst_lo); 1452 simple_move32(masm, src_hi, dst_hi); 1453 } 1454 1455 // A long move 1456 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1457 1458 // Do the simple ones here else do two int moves 1459 if (src.is_single_phys_reg() ) { 1460 if (dst.is_single_phys_reg()) { 1461 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1462 } else { 1463 // split src into two separate registers 1464 // Remember hi means hi address or lsw on sparc 1465 // Move msw to lsw 1466 if (dst.second()->is_reg()) { 1467 // MSW -> MSW 1468 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register()); 1469 // Now LSW -> LSW 1470 // this will only move lo -> lo and ignore hi 1471 VMRegPair split(dst.second()); 1472 simple_move32(masm, src, split); 1473 } else { 1474 VMRegPair split(src.first(), L4->as_VMReg()); 1475 // MSW -> MSW (lo ie. first word) 1476 __ srax(src.first()->as_Register(), 32, L4); 1477 split_long_move(masm, split, dst); 1478 } 1479 } 1480 } else if (dst.is_single_phys_reg()) { 1481 if (src.is_adjacent_aligned_on_stack(2)) { 1482 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1483 } else { 1484 // dst is a single reg. 1485 // Remember lo is low address not msb for stack slots 1486 // and lo is the "real" register for registers 1487 // src is 1488 1489 VMRegPair split; 1490 1491 if (src.first()->is_reg()) { 1492 // src.lo (msw) is a reg, src.hi is stk/reg 1493 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg] 1494 split.set_pair(dst.first(), src.first()); 1495 } else { 1496 // msw is stack move to L5 1497 // lsw is stack move to dst.lo (real reg) 1498 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5 1499 split.set_pair(dst.first(), L5->as_VMReg()); 1500 } 1501 1502 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg) 1503 // msw -> src.lo/L5, lsw -> dst.lo 1504 split_long_move(masm, src, split); 1505 1506 // So dst now has the low order correct position the 1507 // msw half 1508 __ sllx(split.first()->as_Register(), 32, L5); 1509 1510 const Register d = dst.first()->as_Register(); 1511 __ or3(L5, d, d); 1512 } 1513 } else { 1514 // For LP64 we can probably do better. 1515 split_long_move(masm, src, dst); 1516 } 1517 } 1518 1519 // A double move 1520 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1521 1522 // The painful thing here is that like long_move a VMRegPair might be 1523 // 1: a single physical register 1524 // 2: two physical registers (v8) 1525 // 3: a physical reg [lo] and a stack slot [hi] (v8) 1526 // 4: two stack slots 1527 1528 // Since src is always a java calling convention we know that the src pair 1529 // is always either all registers or all stack (and aligned?) 1530 1531 // in a register [lo] and a stack slot [hi] 1532 if (src.first()->is_stack()) { 1533 if (dst.first()->is_stack()) { 1534 // stack to stack the easiest of the bunch 1535 // ought to be a way to do this where if alignment is ok we use ldd/std when possible 1536 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1537 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); 1538 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1539 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1540 } else { 1541 // stack to reg 1542 if (dst.second()->is_stack()) { 1543 // stack -> reg, stack -> stack 1544 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); 1545 if (dst.first()->is_Register()) { 1546 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1547 } else { 1548 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); 1549 } 1550 // This was missing. (very rare case) 1551 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1552 } else { 1553 // stack -> reg 1554 // Eventually optimize for alignment QQQ 1555 if (dst.first()->is_Register()) { 1556 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1557 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register()); 1558 } else { 1559 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); 1560 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister()); 1561 } 1562 } 1563 } 1564 } else if (dst.first()->is_stack()) { 1565 // reg to stack 1566 if (src.first()->is_Register()) { 1567 // Eventually optimize for alignment QQQ 1568 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1569 if (src.second()->is_stack()) { 1570 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); 1571 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1572 } else { 1573 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS); 1574 } 1575 } else { 1576 // fpr to stack 1577 if (src.second()->is_stack()) { 1578 ShouldNotReachHere(); 1579 } else { 1580 // Is the stack aligned? 1581 if (reg2offset(dst.first()) & 0x7) { 1582 // No do as pairs 1583 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); 1584 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS); 1585 } else { 1586 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); 1587 } 1588 } 1589 } 1590 } else { 1591 // reg to reg 1592 if (src.first()->is_Register()) { 1593 if (dst.first()->is_Register()) { 1594 // gpr -> gpr 1595 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1596 __ mov(src.second()->as_Register(), dst.second()->as_Register()); 1597 } else { 1598 // gpr -> fpr 1599 // ought to be able to do a single store 1600 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS); 1601 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS); 1602 // ought to be able to do a single load 1603 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister()); 1604 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister()); 1605 } 1606 } else if (dst.first()->is_Register()) { 1607 // fpr -> gpr 1608 // ought to be able to do a single store 1609 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS); 1610 // ought to be able to do a single load 1611 // REMEMBER first() is low address not LSB 1612 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register()); 1613 if (dst.second()->is_Register()) { 1614 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register()); 1615 } else { 1616 __ ld(FP, -4 + STACK_BIAS, L4); 1617 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1618 } 1619 } else { 1620 // fpr -> fpr 1621 // In theory these overlap but the ordering is such that this is likely a nop 1622 if ( src.first() != dst.first()) { 1623 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); 1624 } 1625 } 1626 } 1627 } 1628 1629 // Creates an inner frame if one hasn't already been created, and 1630 // saves a copy of the thread in L7_thread_cache 1631 static void create_inner_frame(MacroAssembler* masm, bool* already_created) { 1632 if (!*already_created) { 1633 __ save_frame(0); 1634 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below 1635 // Don't use save_thread because it smashes G2 and we merely want to save a 1636 // copy 1637 __ mov(G2_thread, L7_thread_cache); 1638 *already_created = true; 1639 } 1640 } 1641 1642 1643 static void save_or_restore_arguments(MacroAssembler* masm, 1644 const int stack_slots, 1645 const int total_in_args, 1646 const int arg_save_area, 1647 OopMap* map, 1648 VMRegPair* in_regs, 1649 BasicType* in_sig_bt) { 1650 // if map is non-NULL then the code should store the values, 1651 // otherwise it should load them. 1652 if (map != NULL) { 1653 // Fill in the map 1654 for (int i = 0; i < total_in_args; i++) { 1655 if (in_sig_bt[i] == T_ARRAY) { 1656 if (in_regs[i].first()->is_stack()) { 1657 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1658 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); 1659 } else if (in_regs[i].first()->is_Register()) { 1660 map->set_oop(in_regs[i].first()); 1661 } else { 1662 ShouldNotReachHere(); 1663 } 1664 } 1665 } 1666 } 1667 1668 // Save or restore double word values 1669 int handle_index = 0; 1670 for (int i = 0; i < total_in_args; i++) { 1671 int slot = handle_index + arg_save_area; 1672 int offset = slot * VMRegImpl::stack_slot_size; 1673 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) { 1674 const Register reg = in_regs[i].first()->as_Register(); 1675 if (reg->is_global()) { 1676 handle_index += 2; 1677 assert(handle_index <= stack_slots, "overflow"); 1678 if (map != NULL) { 1679 __ stx(reg, SP, offset + STACK_BIAS); 1680 } else { 1681 __ ldx(SP, offset + STACK_BIAS, reg); 1682 } 1683 } 1684 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) { 1685 handle_index += 2; 1686 assert(handle_index <= stack_slots, "overflow"); 1687 if (map != NULL) { 1688 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); 1689 } else { 1690 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); 1691 } 1692 } 1693 } 1694 // Save floats 1695 for (int i = 0; i < total_in_args; i++) { 1696 int slot = handle_index + arg_save_area; 1697 int offset = slot * VMRegImpl::stack_slot_size; 1698 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) { 1699 handle_index++; 1700 assert(handle_index <= stack_slots, "overflow"); 1701 if (map != NULL) { 1702 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); 1703 } else { 1704 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); 1705 } 1706 } 1707 } 1708 1709 } 1710 1711 1712 // Check GC_locker::needs_gc and enter the runtime if it's true. This 1713 // keeps a new JNI critical region from starting until a GC has been 1714 // forced. Save down any oops in registers and describe them in an 1715 // OopMap. 1716 static void check_needs_gc_for_critical_native(MacroAssembler* masm, 1717 const int stack_slots, 1718 const int total_in_args, 1719 const int arg_save_area, 1720 OopMapSet* oop_maps, 1721 VMRegPair* in_regs, 1722 BasicType* in_sig_bt) { 1723 __ block_comment("check GC_locker::needs_gc"); 1724 Label cont; 1725 AddressLiteral sync_state(GC_locker::needs_gc_address()); 1726 __ load_bool_contents(sync_state, G3_scratch); 1727 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont); 1728 __ delayed()->nop(); 1729 1730 // Save down any values that are live in registers and call into the 1731 // runtime to halt for a GC 1732 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1733 save_or_restore_arguments(masm, stack_slots, total_in_args, 1734 arg_save_area, map, in_regs, in_sig_bt); 1735 1736 __ mov(G2_thread, L7_thread_cache); 1737 1738 __ set_last_Java_frame(SP, noreg); 1739 1740 __ block_comment("block_for_jni_critical"); 1741 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type); 1742 __ delayed()->mov(L7_thread_cache, O0); 1743 oop_maps->add_gc_map( __ offset(), map); 1744 1745 __ restore_thread(L7_thread_cache); // restore G2_thread 1746 __ reset_last_Java_frame(); 1747 1748 // Reload all the register arguments 1749 save_or_restore_arguments(masm, stack_slots, total_in_args, 1750 arg_save_area, NULL, in_regs, in_sig_bt); 1751 1752 __ bind(cont); 1753 #ifdef ASSERT 1754 if (StressCriticalJNINatives) { 1755 // Stress register saving 1756 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1757 save_or_restore_arguments(masm, stack_slots, total_in_args, 1758 arg_save_area, map, in_regs, in_sig_bt); 1759 // Destroy argument registers 1760 for (int i = 0; i < total_in_args; i++) { 1761 if (in_regs[i].first()->is_Register()) { 1762 const Register reg = in_regs[i].first()->as_Register(); 1763 if (reg->is_global()) { 1764 __ mov(G0, reg); 1765 } 1766 } else if (in_regs[i].first()->is_FloatRegister()) { 1767 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister()); 1768 } 1769 } 1770 1771 save_or_restore_arguments(masm, stack_slots, total_in_args, 1772 arg_save_area, NULL, in_regs, in_sig_bt); 1773 } 1774 #endif 1775 } 1776 1777 // Unpack an array argument into a pointer to the body and the length 1778 // if the array is non-null, otherwise pass 0 for both. 1779 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { 1780 // Pass the length, ptr pair 1781 Label is_null, done; 1782 if (reg.first()->is_stack()) { 1783 VMRegPair tmp = reg64_to_VMRegPair(L2); 1784 // Load the arg up from the stack 1785 move_ptr(masm, reg, tmp); 1786 reg = tmp; 1787 } 1788 __ cmp(reg.first()->as_Register(), G0); 1789 __ brx(Assembler::equal, false, Assembler::pt, is_null); 1790 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4); 1791 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg); 1792 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4); 1793 move32_64(masm, reg64_to_VMRegPair(L4), length_arg); 1794 __ ba_short(done); 1795 __ bind(is_null); 1796 // Pass zeros 1797 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg); 1798 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); 1799 __ bind(done); 1800 } 1801 1802 static void verify_oop_args(MacroAssembler* masm, 1803 methodHandle method, 1804 const BasicType* sig_bt, 1805 const VMRegPair* regs) { 1806 Register temp_reg = G5_method; // not part of any compiled calling seq 1807 if (VerifyOops) { 1808 for (int i = 0; i < method->size_of_parameters(); i++) { 1809 if (sig_bt[i] == T_OBJECT || 1810 sig_bt[i] == T_ARRAY) { 1811 VMReg r = regs[i].first(); 1812 assert(r->is_valid(), "bad oop arg"); 1813 if (r->is_stack()) { 1814 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; 1815 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg); 1816 __ ld_ptr(SP, ld_off, temp_reg); 1817 __ verify_oop(temp_reg); 1818 } else { 1819 __ verify_oop(r->as_Register()); 1820 } 1821 } 1822 } 1823 } 1824 } 1825 1826 static void gen_special_dispatch(MacroAssembler* masm, 1827 methodHandle method, 1828 const BasicType* sig_bt, 1829 const VMRegPair* regs) { 1830 verify_oop_args(masm, method, sig_bt, regs); 1831 vmIntrinsics::ID iid = method->intrinsic_id(); 1832 1833 // Now write the args into the outgoing interpreter space 1834 bool has_receiver = false; 1835 Register receiver_reg = noreg; 1836 int member_arg_pos = -1; 1837 Register member_reg = noreg; 1838 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); 1839 if (ref_kind != 0) { 1840 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument 1841 member_reg = G5_method; // known to be free at this point 1842 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); 1843 } else if (iid == vmIntrinsics::_invokeBasic) { 1844 has_receiver = true; 1845 } else { 1846 fatal(err_msg_res("unexpected intrinsic id %d", iid)); 1847 } 1848 1849 if (member_reg != noreg) { 1850 // Load the member_arg into register, if necessary. 1851 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); 1852 VMReg r = regs[member_arg_pos].first(); 1853 if (r->is_stack()) { 1854 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; 1855 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); 1856 __ ld_ptr(SP, ld_off, member_reg); 1857 } else { 1858 // no data motion is needed 1859 member_reg = r->as_Register(); 1860 } 1861 } 1862 1863 if (has_receiver) { 1864 // Make sure the receiver is loaded into a register. 1865 assert(method->size_of_parameters() > 0, "oob"); 1866 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); 1867 VMReg r = regs[0].first(); 1868 assert(r->is_valid(), "bad receiver arg"); 1869 if (r->is_stack()) { 1870 // Porting note: This assumes that compiled calling conventions always 1871 // pass the receiver oop in a register. If this is not true on some 1872 // platform, pick a temp and load the receiver from stack. 1873 fatal("receiver always in a register"); 1874 receiver_reg = G3_scratch; // known to be free at this point 1875 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; 1876 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); 1877 __ ld_ptr(SP, ld_off, receiver_reg); 1878 } else { 1879 // no data motion is needed 1880 receiver_reg = r->as_Register(); 1881 } 1882 } 1883 1884 // Figure out which address we are really jumping to: 1885 MethodHandles::generate_method_handle_dispatch(masm, iid, 1886 receiver_reg, member_reg, /*for_compiler_entry:*/ true); 1887 } 1888 1889 // --------------------------------------------------------------------------- 1890 // Generate a native wrapper for a given method. The method takes arguments 1891 // in the Java compiled code convention, marshals them to the native 1892 // convention (handlizes oops, etc), transitions to native, makes the call, 1893 // returns to java state (possibly blocking), unhandlizes any result and 1894 // returns. 1895 // 1896 // Critical native functions are a shorthand for the use of 1897 // GetPrimtiveArrayCritical and disallow the use of any other JNI 1898 // functions. The wrapper is expected to unpack the arguments before 1899 // passing them to the callee and perform checks before and after the 1900 // native call to ensure that they GC_locker 1901 // lock_critical/unlock_critical semantics are followed. Some other 1902 // parts of JNI setup are skipped like the tear down of the JNI handle 1903 // block and the check for pending exceptions it's impossible for them 1904 // to be thrown. 1905 // 1906 // They are roughly structured like this: 1907 // if (GC_locker::needs_gc()) 1908 // SharedRuntime::block_for_jni_critical(); 1909 // tranistion to thread_in_native 1910 // unpack arrray arguments and call native entry point 1911 // check for safepoint in progress 1912 // check if any thread suspend flags are set 1913 // call into JVM and possible unlock the JNI critical 1914 // if a GC was suppressed while in the critical native. 1915 // transition back to thread_in_Java 1916 // return to caller 1917 // 1918 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, 1919 methodHandle method, 1920 int compile_id, 1921 BasicType* in_sig_bt, 1922 VMRegPair* in_regs, 1923 BasicType ret_type) { 1924 if (method->is_method_handle_intrinsic()) { 1925 vmIntrinsics::ID iid = method->intrinsic_id(); 1926 intptr_t start = (intptr_t)__ pc(); 1927 int vep_offset = ((intptr_t)__ pc()) - start; 1928 gen_special_dispatch(masm, 1929 method, 1930 in_sig_bt, 1931 in_regs); 1932 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period 1933 __ flush(); 1934 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually 1935 return nmethod::new_native_nmethod(method, 1936 compile_id, 1937 masm->code(), 1938 vep_offset, 1939 frame_complete, 1940 stack_slots / VMRegImpl::slots_per_word, 1941 in_ByteSize(-1), 1942 in_ByteSize(-1), 1943 (OopMapSet*)NULL); 1944 } 1945 bool is_critical_native = true; 1946 address native_func = method->critical_native_function(); 1947 if (native_func == NULL) { 1948 native_func = method->native_function(); 1949 is_critical_native = false; 1950 } 1951 assert(native_func != NULL, "must have function"); 1952 1953 // Native nmethod wrappers never take possesion of the oop arguments. 1954 // So the caller will gc the arguments. The only thing we need an 1955 // oopMap for is if the call is static 1956 // 1957 // An OopMap for lock (and class if static), and one for the VM call itself 1958 OopMapSet *oop_maps = new OopMapSet(); 1959 intptr_t start = (intptr_t)__ pc(); 1960 1961 // First thing make an ic check to see if we should even be here 1962 { 1963 Label L; 1964 const Register temp_reg = G3_scratch; 1965 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); 1966 __ verify_oop(O0); 1967 __ load_klass(O0, temp_reg); 1968 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); 1969 1970 __ jump_to(ic_miss, temp_reg); 1971 __ delayed()->nop(); 1972 __ align(CodeEntryAlignment); 1973 __ bind(L); 1974 } 1975 1976 int vep_offset = ((intptr_t)__ pc()) - start; 1977 1978 #ifdef COMPILER1 1979 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) { 1980 // Object.hashCode can pull the hashCode from the header word 1981 // instead of doing a full VM transition once it's been computed. 1982 // Since hashCode is usually polymorphic at call sites we can't do 1983 // this optimization at the call site without a lot of work. 1984 Label slowCase; 1985 Register receiver = O0; 1986 Register result = O0; 1987 Register header = G3_scratch; 1988 Register hash = G3_scratch; // overwrite header value with hash value 1989 Register mask = G1; // to get hash field from header 1990 1991 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked. 1992 // We depend on hash_mask being at most 32 bits and avoid the use of 1993 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit 1994 // vm: see markOop.hpp. 1995 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header); 1996 __ sethi(markOopDesc::hash_mask, mask); 1997 __ btst(markOopDesc::unlocked_value, header); 1998 __ br(Assembler::zero, false, Assembler::pn, slowCase); 1999 if (UseBiasedLocking) { 2000 // Check if biased and fall through to runtime if so 2001 __ delayed()->nop(); 2002 __ btst(markOopDesc::biased_lock_bit_in_place, header); 2003 __ br(Assembler::notZero, false, Assembler::pn, slowCase); 2004 } 2005 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask); 2006 2007 // Check for a valid (non-zero) hash code and get its value. 2008 #ifdef _LP64 2009 __ srlx(header, markOopDesc::hash_shift, hash); 2010 #else 2011 __ srl(header, markOopDesc::hash_shift, hash); 2012 #endif 2013 __ andcc(hash, mask, hash); 2014 __ br(Assembler::equal, false, Assembler::pn, slowCase); 2015 __ delayed()->nop(); 2016 2017 // leaf return. 2018 __ retl(); 2019 __ delayed()->mov(hash, result); 2020 __ bind(slowCase); 2021 } 2022 #endif // COMPILER1 2023 2024 2025 // We have received a description of where all the java arg are located 2026 // on entry to the wrapper. We need to convert these args to where 2027 // the jni function will expect them. To figure out where they go 2028 // we convert the java signature to a C signature by inserting 2029 // the hidden arguments as arg[0] and possibly arg[1] (static method) 2030 2031 const int total_in_args = method->size_of_parameters(); 2032 int total_c_args = total_in_args; 2033 int total_save_slots = 6 * VMRegImpl::slots_per_word; 2034 if (!is_critical_native) { 2035 total_c_args += 1; 2036 if (method->is_static()) { 2037 total_c_args++; 2038 } 2039 } else { 2040 for (int i = 0; i < total_in_args; i++) { 2041 if (in_sig_bt[i] == T_ARRAY) { 2042 // These have to be saved and restored across the safepoint 2043 total_c_args++; 2044 } 2045 } 2046 } 2047 2048 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); 2049 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); 2050 BasicType* in_elem_bt = NULL; 2051 2052 int argc = 0; 2053 if (!is_critical_native) { 2054 out_sig_bt[argc++] = T_ADDRESS; 2055 if (method->is_static()) { 2056 out_sig_bt[argc++] = T_OBJECT; 2057 } 2058 2059 for (int i = 0; i < total_in_args ; i++ ) { 2060 out_sig_bt[argc++] = in_sig_bt[i]; 2061 } 2062 } else { 2063 Thread* THREAD = Thread::current(); 2064 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); 2065 SignatureStream ss(method->signature()); 2066 for (int i = 0; i < total_in_args ; i++ ) { 2067 if (in_sig_bt[i] == T_ARRAY) { 2068 // Arrays are passed as int, elem* pair 2069 out_sig_bt[argc++] = T_INT; 2070 out_sig_bt[argc++] = T_ADDRESS; 2071 Symbol* atype = ss.as_symbol(CHECK_NULL); 2072 const char* at = atype->as_C_string(); 2073 if (strlen(at) == 2) { 2074 assert(at[0] == '[', "must be"); 2075 switch (at[1]) { 2076 case 'B': in_elem_bt[i] = T_BYTE; break; 2077 case 'C': in_elem_bt[i] = T_CHAR; break; 2078 case 'D': in_elem_bt[i] = T_DOUBLE; break; 2079 case 'F': in_elem_bt[i] = T_FLOAT; break; 2080 case 'I': in_elem_bt[i] = T_INT; break; 2081 case 'J': in_elem_bt[i] = T_LONG; break; 2082 case 'S': in_elem_bt[i] = T_SHORT; break; 2083 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; 2084 default: ShouldNotReachHere(); 2085 } 2086 } 2087 } else { 2088 out_sig_bt[argc++] = in_sig_bt[i]; 2089 in_elem_bt[i] = T_VOID; 2090 } 2091 if (in_sig_bt[i] != T_VOID) { 2092 assert(in_sig_bt[i] == ss.type(), "must match"); 2093 ss.next(); 2094 } 2095 } 2096 } 2097 2098 // Now figure out where the args must be stored and how much stack space 2099 // they require (neglecting out_preserve_stack_slots but space for storing 2100 // the 1st six register arguments). It's weird see int_stk_helper. 2101 // 2102 int out_arg_slots; 2103 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); 2104 2105 if (is_critical_native) { 2106 // Critical natives may have to call out so they need a save area 2107 // for register arguments. 2108 int double_slots = 0; 2109 int single_slots = 0; 2110 for ( int i = 0; i < total_in_args; i++) { 2111 if (in_regs[i].first()->is_Register()) { 2112 const Register reg = in_regs[i].first()->as_Register(); 2113 switch (in_sig_bt[i]) { 2114 case T_ARRAY: 2115 case T_BOOLEAN: 2116 case T_BYTE: 2117 case T_SHORT: 2118 case T_CHAR: 2119 case T_INT: assert(reg->is_in(), "don't need to save these"); break; 2120 case T_LONG: if (reg->is_global()) double_slots++; break; 2121 default: ShouldNotReachHere(); 2122 } 2123 } else if (in_regs[i].first()->is_FloatRegister()) { 2124 switch (in_sig_bt[i]) { 2125 case T_FLOAT: single_slots++; break; 2126 case T_DOUBLE: double_slots++; break; 2127 default: ShouldNotReachHere(); 2128 } 2129 } 2130 } 2131 total_save_slots = double_slots * 2 + single_slots; 2132 } 2133 2134 // Compute framesize for the wrapper. We need to handlize all oops in 2135 // registers. We must create space for them here that is disjoint from 2136 // the windowed save area because we have no control over when we might 2137 // flush the window again and overwrite values that gc has since modified. 2138 // (The live window race) 2139 // 2140 // We always just allocate 6 word for storing down these object. This allow 2141 // us to simply record the base and use the Ireg number to decide which 2142 // slot to use. (Note that the reg number is the inbound number not the 2143 // outbound number). 2144 // We must shuffle args to match the native convention, and include var-args space. 2145 2146 // Calculate the total number of stack slots we will need. 2147 2148 // First count the abi requirement plus all of the outgoing args 2149 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 2150 2151 // Now the space for the inbound oop handle area 2152 2153 int oop_handle_offset = round_to(stack_slots, 2); 2154 stack_slots += total_save_slots; 2155 2156 // Now any space we need for handlizing a klass if static method 2157 2158 int klass_slot_offset = 0; 2159 int klass_offset = -1; 2160 int lock_slot_offset = 0; 2161 bool is_static = false; 2162 2163 if (method->is_static()) { 2164 klass_slot_offset = stack_slots; 2165 stack_slots += VMRegImpl::slots_per_word; 2166 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; 2167 is_static = true; 2168 } 2169 2170 // Plus a lock if needed 2171 2172 if (method->is_synchronized()) { 2173 lock_slot_offset = stack_slots; 2174 stack_slots += VMRegImpl::slots_per_word; 2175 } 2176 2177 // Now a place to save return value or as a temporary for any gpr -> fpr moves 2178 stack_slots += 2; 2179 2180 // Ok The space we have allocated will look like: 2181 // 2182 // 2183 // FP-> | | 2184 // |---------------------| 2185 // | 2 slots for moves | 2186 // |---------------------| 2187 // | lock box (if sync) | 2188 // |---------------------| <- lock_slot_offset 2189 // | klass (if static) | 2190 // |---------------------| <- klass_slot_offset 2191 // | oopHandle area | 2192 // |---------------------| <- oop_handle_offset 2193 // | outbound memory | 2194 // | based arguments | 2195 // | | 2196 // |---------------------| 2197 // | vararg area | 2198 // |---------------------| 2199 // | | 2200 // SP-> | out_preserved_slots | 2201 // 2202 // 2203 2204 2205 // Now compute actual number of stack words we need rounding to make 2206 // stack properly aligned. 2207 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word); 2208 2209 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 2210 2211 // Generate stack overflow check before creating frame 2212 __ generate_stack_overflow_check(stack_size); 2213 2214 // Generate a new frame for the wrapper. 2215 __ save(SP, -stack_size, SP); 2216 2217 int frame_complete = ((intptr_t)__ pc()) - start; 2218 2219 __ verify_thread(); 2220 2221 if (is_critical_native) { 2222 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args, 2223 oop_handle_offset, oop_maps, in_regs, in_sig_bt); 2224 } 2225 2226 // 2227 // We immediately shuffle the arguments so that any vm call we have to 2228 // make from here on out (sync slow path, jvmti, etc.) we will have 2229 // captured the oops from our caller and have a valid oopMap for 2230 // them. 2231 2232 // ----------------- 2233 // The Grand Shuffle 2234 // 2235 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* 2236 // (derived from JavaThread* which is in L7_thread_cache) and, if static, 2237 // the class mirror instead of a receiver. This pretty much guarantees that 2238 // register layout will not match. We ignore these extra arguments during 2239 // the shuffle. The shuffle is described by the two calling convention 2240 // vectors we have in our possession. We simply walk the java vector to 2241 // get the source locations and the c vector to get the destinations. 2242 // Because we have a new window and the argument registers are completely 2243 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about 2244 // here. 2245 2246 // This is a trick. We double the stack slots so we can claim 2247 // the oops in the caller's frame. Since we are sure to have 2248 // more args than the caller doubling is enough to make 2249 // sure we can capture all the incoming oop args from the 2250 // caller. 2251 // 2252 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 2253 // Record sp-based slot for receiver on stack for non-static methods 2254 int receiver_offset = -1; 2255 2256 // We move the arguments backward because the floating point registers 2257 // destination will always be to a register with a greater or equal register 2258 // number or the stack. 2259 2260 #ifdef ASSERT 2261 bool reg_destroyed[RegisterImpl::number_of_registers]; 2262 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; 2263 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 2264 reg_destroyed[r] = false; 2265 } 2266 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { 2267 freg_destroyed[f] = false; 2268 } 2269 2270 #endif /* ASSERT */ 2271 2272 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) { 2273 2274 #ifdef ASSERT 2275 if (in_regs[i].first()->is_Register()) { 2276 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!"); 2277 } else if (in_regs[i].first()->is_FloatRegister()) { 2278 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!"); 2279 } 2280 if (out_regs[c_arg].first()->is_Register()) { 2281 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 2282 } else if (out_regs[c_arg].first()->is_FloatRegister()) { 2283 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true; 2284 } 2285 #endif /* ASSERT */ 2286 2287 switch (in_sig_bt[i]) { 2288 case T_ARRAY: 2289 if (is_critical_native) { 2290 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]); 2291 c_arg--; 2292 break; 2293 } 2294 case T_OBJECT: 2295 assert(!is_critical_native, "no oop arguments"); 2296 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], 2297 ((i == 0) && (!is_static)), 2298 &receiver_offset); 2299 break; 2300 case T_VOID: 2301 break; 2302 2303 case T_FLOAT: 2304 float_move(masm, in_regs[i], out_regs[c_arg]); 2305 break; 2306 2307 case T_DOUBLE: 2308 assert( i + 1 < total_in_args && 2309 in_sig_bt[i + 1] == T_VOID && 2310 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 2311 double_move(masm, in_regs[i], out_regs[c_arg]); 2312 break; 2313 2314 case T_LONG : 2315 long_move(masm, in_regs[i], out_regs[c_arg]); 2316 break; 2317 2318 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 2319 2320 default: 2321 move32_64(masm, in_regs[i], out_regs[c_arg]); 2322 } 2323 } 2324 2325 // Pre-load a static method's oop into O1. Used both by locking code and 2326 // the normal JNI call code. 2327 if (method->is_static() && !is_critical_native) { 2328 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1); 2329 2330 // Now handlize the static class mirror in O1. It's known not-null. 2331 __ st_ptr(O1, SP, klass_offset + STACK_BIAS); 2332 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); 2333 __ add(SP, klass_offset + STACK_BIAS, O1); 2334 } 2335 2336 2337 const Register L6_handle = L6; 2338 2339 if (method->is_synchronized()) { 2340 assert(!is_critical_native, "unhandled"); 2341 __ mov(O1, L6_handle); 2342 } 2343 2344 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs 2345 // except O6/O7. So if we must call out we must push a new frame. We immediately 2346 // push a new frame and flush the windows. 2347 #ifdef _LP64 2348 intptr_t thepc = (intptr_t) __ pc(); 2349 { 2350 address here = __ pc(); 2351 // Call the next instruction 2352 __ call(here + 8, relocInfo::none); 2353 __ delayed()->nop(); 2354 } 2355 #else 2356 intptr_t thepc = __ load_pc_address(O7, 0); 2357 #endif /* _LP64 */ 2358 2359 // We use the same pc/oopMap repeatedly when we call out 2360 oop_maps->add_gc_map(thepc - start, map); 2361 2362 // O7 now has the pc loaded that we will use when we finally call to native. 2363 2364 // Save thread in L7; it crosses a bunch of VM calls below 2365 // Don't use save_thread because it smashes G2 and we merely 2366 // want to save a copy 2367 __ mov(G2_thread, L7_thread_cache); 2368 2369 2370 // If we create an inner frame once is plenty 2371 // when we create it we must also save G2_thread 2372 bool inner_frame_created = false; 2373 2374 // dtrace method entry support 2375 { 2376 SkipIfEqual skip_if( 2377 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); 2378 // create inner frame 2379 __ save_frame(0); 2380 __ mov(G2_thread, L7_thread_cache); 2381 __ set_metadata_constant(method(), O1); 2382 __ call_VM_leaf(L7_thread_cache, 2383 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), 2384 G2_thread, O1); 2385 __ restore(); 2386 } 2387 2388 // RedefineClasses() tracing support for obsolete method entry 2389 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { 2390 // create inner frame 2391 __ save_frame(0); 2392 __ mov(G2_thread, L7_thread_cache); 2393 __ set_metadata_constant(method(), O1); 2394 __ call_VM_leaf(L7_thread_cache, 2395 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), 2396 G2_thread, O1); 2397 __ restore(); 2398 } 2399 2400 // We are in the jni frame unless saved_frame is true in which case 2401 // we are in one frame deeper (the "inner" frame). If we are in the 2402 // "inner" frames the args are in the Iregs and if the jni frame then 2403 // they are in the Oregs. 2404 // If we ever need to go to the VM (for locking, jvmti) then 2405 // we will always be in the "inner" frame. 2406 2407 // Lock a synchronized method 2408 int lock_offset = -1; // Set if locked 2409 if (method->is_synchronized()) { 2410 Register Roop = O1; 2411 const Register L3_box = L3; 2412 2413 create_inner_frame(masm, &inner_frame_created); 2414 2415 __ ld_ptr(I1, 0, O1); 2416 Label done; 2417 2418 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size); 2419 __ add(FP, lock_offset+STACK_BIAS, L3_box); 2420 #ifdef ASSERT 2421 if (UseBiasedLocking) { 2422 // making the box point to itself will make it clear it went unused 2423 // but also be obviously invalid 2424 __ st_ptr(L3_box, L3_box, 0); 2425 } 2426 #endif // ASSERT 2427 // 2428 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch 2429 // 2430 __ compiler_lock_object(Roop, L1, L3_box, L2); 2431 __ br(Assembler::equal, false, Assembler::pt, done); 2432 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box); 2433 2434 2435 // None of the above fast optimizations worked so we have to get into the 2436 // slow case of monitor enter. Inline a special case of call_VM that 2437 // disallows any pending_exception. 2438 __ mov(Roop, O0); // Need oop in O0 2439 __ mov(L3_box, O1); 2440 2441 // Record last_Java_sp, in case the VM code releases the JVM lock. 2442 2443 __ set_last_Java_frame(FP, I7); 2444 2445 // do the call 2446 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); 2447 __ delayed()->mov(L7_thread_cache, O2); 2448 2449 __ restore_thread(L7_thread_cache); // restore G2_thread 2450 __ reset_last_Java_frame(); 2451 2452 #ifdef ASSERT 2453 { Label L; 2454 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); 2455 __ br_null_short(O0, Assembler::pt, L); 2456 __ stop("no pending exception allowed on exit from IR::monitorenter"); 2457 __ bind(L); 2458 } 2459 #endif 2460 __ bind(done); 2461 } 2462 2463 2464 // Finally just about ready to make the JNI call 2465 2466 __ flushw(); 2467 if (inner_frame_created) { 2468 __ restore(); 2469 } else { 2470 // Store only what we need from this frame 2471 // QQQ I think that non-v9 (like we care) we don't need these saves 2472 // either as the flush traps and the current window goes too. 2473 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS); 2474 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); 2475 } 2476 2477 // get JNIEnv* which is first argument to native 2478 if (!is_critical_native) { 2479 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0); 2480 } 2481 2482 // Use that pc we placed in O7 a while back as the current frame anchor 2483 __ set_last_Java_frame(SP, O7); 2484 2485 // We flushed the windows ages ago now mark them as flushed before transitioning. 2486 __ set(JavaFrameAnchor::flushed, G3_scratch); 2487 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); 2488 2489 // Transition from _thread_in_Java to _thread_in_native. 2490 __ set(_thread_in_native, G3_scratch); 2491 2492 #ifdef _LP64 2493 AddressLiteral dest(native_func); 2494 __ relocate(relocInfo::runtime_call_type); 2495 __ jumpl_to(dest, O7, O7); 2496 #else 2497 __ call(native_func, relocInfo::runtime_call_type); 2498 #endif 2499 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); 2500 2501 __ restore_thread(L7_thread_cache); // restore G2_thread 2502 2503 // Unpack native results. For int-types, we do any needed sign-extension 2504 // and move things into I0. The return value there will survive any VM 2505 // calls for blocking or unlocking. An FP or OOP result (handle) is done 2506 // specially in the slow-path code. 2507 switch (ret_type) { 2508 case T_VOID: break; // Nothing to do! 2509 case T_FLOAT: break; // Got it where we want it (unless slow-path) 2510 case T_DOUBLE: break; // Got it where we want it (unless slow-path) 2511 // In 64 bits build result is in O0, in O0, O1 in 32bit build 2512 case T_LONG: 2513 #ifndef _LP64 2514 __ mov(O1, I1); 2515 #endif 2516 // Fall thru 2517 case T_OBJECT: // Really a handle 2518 case T_ARRAY: 2519 case T_INT: 2520 __ mov(O0, I0); 2521 break; 2522 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false 2523 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break; 2524 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value! 2525 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break; 2526 break; // Cannot de-handlize until after reclaiming jvm_lock 2527 default: 2528 ShouldNotReachHere(); 2529 } 2530 2531 Label after_transition; 2532 // must we block? 2533 2534 // Block, if necessary, before resuming in _thread_in_Java state. 2535 // In order for GC to work, don't clear the last_Java_sp until after blocking. 2536 { Label no_block; 2537 AddressLiteral sync_state(SafepointSynchronize::address_of_state()); 2538 2539 // Switch thread to "native transition" state before reading the synchronization state. 2540 // This additional state is necessary because reading and testing the synchronization 2541 // state is not atomic w.r.t. GC, as this scenario demonstrates: 2542 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. 2543 // VM thread changes sync state to synchronizing and suspends threads for GC. 2544 // Thread A is resumed to finish this native method, but doesn't block here since it 2545 // didn't see any synchronization is progress, and escapes. 2546 __ set(_thread_in_native_trans, G3_scratch); 2547 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); 2548 if(os::is_MP()) { 2549 if (UseMembar) { 2550 // Force this write out before the read below 2551 __ membar(Assembler::StoreLoad); 2552 } else { 2553 // Write serialization page so VM thread can do a pseudo remote membar. 2554 // We use the current thread pointer to calculate a thread specific 2555 // offset to write to within the page. This minimizes bus traffic 2556 // due to cache line collision. 2557 __ serialize_memory(G2_thread, G1_scratch, G3_scratch); 2558 } 2559 } 2560 __ load_contents(sync_state, G3_scratch); 2561 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized); 2562 2563 Label L; 2564 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset()); 2565 __ br(Assembler::notEqual, false, Assembler::pn, L); 2566 __ delayed()->ld(suspend_state, G3_scratch); 2567 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block); 2568 __ bind(L); 2569 2570 // Block. Save any potential method result value before the operation and 2571 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this 2572 // lets us share the oopMap we used when we went native rather the create 2573 // a distinct one for this pc 2574 // 2575 save_native_result(masm, ret_type, stack_slots); 2576 if (!is_critical_native) { 2577 __ call_VM_leaf(L7_thread_cache, 2578 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), 2579 G2_thread); 2580 } else { 2581 __ call_VM_leaf(L7_thread_cache, 2582 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), 2583 G2_thread); 2584 } 2585 2586 // Restore any method result value 2587 restore_native_result(masm, ret_type, stack_slots); 2588 2589 if (is_critical_native) { 2590 // The call above performed the transition to thread_in_Java so 2591 // skip the transition logic below. 2592 __ ba(after_transition); 2593 __ delayed()->nop(); 2594 } 2595 2596 __ bind(no_block); 2597 } 2598 2599 // thread state is thread_in_native_trans. Any safepoint blocking has already 2600 // happened so we can now change state to _thread_in_Java. 2601 __ set(_thread_in_Java, G3_scratch); 2602 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); 2603 __ bind(after_transition); 2604 2605 Label no_reguard; 2606 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch); 2607 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard); 2608 2609 save_native_result(masm, ret_type, stack_slots); 2610 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); 2611 __ delayed()->nop(); 2612 2613 __ restore_thread(L7_thread_cache); // restore G2_thread 2614 restore_native_result(masm, ret_type, stack_slots); 2615 2616 __ bind(no_reguard); 2617 2618 // Handle possible exception (will unlock if necessary) 2619 2620 // native result if any is live in freg or I0 (and I1 if long and 32bit vm) 2621 2622 // Unlock 2623 if (method->is_synchronized()) { 2624 Label done; 2625 Register I2_ex_oop = I2; 2626 const Register L3_box = L3; 2627 // Get locked oop from the handle we passed to jni 2628 __ ld_ptr(L6_handle, 0, L4); 2629 __ add(SP, lock_offset+STACK_BIAS, L3_box); 2630 // Must save pending exception around the slow-path VM call. Since it's a 2631 // leaf call, the pending exception (if any) can be kept in a register. 2632 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop); 2633 // Now unlock 2634 // (Roop, Rmark, Rbox, Rscratch) 2635 __ compiler_unlock_object(L4, L1, L3_box, L2); 2636 __ br(Assembler::equal, false, Assembler::pt, done); 2637 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box); 2638 2639 // save and restore any potential method result value around the unlocking 2640 // operation. Will save in I0 (or stack for FP returns). 2641 save_native_result(masm, ret_type, stack_slots); 2642 2643 // Must clear pending-exception before re-entering the VM. Since this is 2644 // a leaf call, pending-exception-oop can be safely kept in a register. 2645 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset())); 2646 2647 // slow case of monitor enter. Inline a special case of call_VM that 2648 // disallows any pending_exception. 2649 __ mov(L3_box, O1); 2650 2651 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type); 2652 __ delayed()->mov(L4, O0); // Need oop in O0 2653 2654 __ restore_thread(L7_thread_cache); // restore G2_thread 2655 2656 #ifdef ASSERT 2657 { Label L; 2658 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); 2659 __ br_null_short(O0, Assembler::pt, L); 2660 __ stop("no pending exception allowed on exit from IR::monitorexit"); 2661 __ bind(L); 2662 } 2663 #endif 2664 restore_native_result(masm, ret_type, stack_slots); 2665 // check_forward_pending_exception jump to forward_exception if any pending 2666 // exception is set. The forward_exception routine expects to see the 2667 // exception in pending_exception and not in a register. Kind of clumsy, 2668 // since all folks who branch to forward_exception must have tested 2669 // pending_exception first and hence have it in a register already. 2670 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset())); 2671 __ bind(done); 2672 } 2673 2674 // Tell dtrace about this method exit 2675 { 2676 SkipIfEqual skip_if( 2677 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); 2678 save_native_result(masm, ret_type, stack_slots); 2679 __ set_metadata_constant(method(), O1); 2680 __ call_VM_leaf(L7_thread_cache, 2681 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), 2682 G2_thread, O1); 2683 restore_native_result(masm, ret_type, stack_slots); 2684 } 2685 2686 // Clear "last Java frame" SP and PC. 2687 __ verify_thread(); // G2_thread must be correct 2688 __ reset_last_Java_frame(); 2689 2690 // Unpack oop result 2691 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { 2692 Label L; 2693 __ addcc(G0, I0, G0); 2694 __ brx(Assembler::notZero, true, Assembler::pt, L); 2695 __ delayed()->ld_ptr(I0, 0, I0); 2696 __ mov(G0, I0); 2697 __ bind(L); 2698 __ verify_oop(I0); 2699 } 2700 2701 if (!is_critical_native) { 2702 // reset handle block 2703 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5); 2704 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes()); 2705 2706 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch); 2707 check_forward_pending_exception(masm, G3_scratch); 2708 } 2709 2710 2711 // Return 2712 2713 #ifndef _LP64 2714 if (ret_type == T_LONG) { 2715 2716 // Must leave proper result in O0,O1 and G1 (c2/tiered only) 2717 __ sllx(I0, 32, G1); // Shift bits into high G1 2718 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) 2719 __ or3 (I1, G1, G1); // OR 64 bits into G1 2720 } 2721 #endif 2722 2723 __ ret(); 2724 __ delayed()->restore(); 2725 2726 __ flush(); 2727 2728 nmethod *nm = nmethod::new_native_nmethod(method, 2729 compile_id, 2730 masm->code(), 2731 vep_offset, 2732 frame_complete, 2733 stack_slots / VMRegImpl::slots_per_word, 2734 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), 2735 in_ByteSize(lock_offset), 2736 oop_maps); 2737 2738 if (is_critical_native) { 2739 nm->set_lazy_critical_native(true); 2740 } 2741 return nm; 2742 2743 } 2744 2745 #ifdef HAVE_DTRACE_H 2746 // --------------------------------------------------------------------------- 2747 // Generate a dtrace nmethod for a given signature. The method takes arguments 2748 // in the Java compiled code convention, marshals them to the native 2749 // abi and then leaves nops at the position you would expect to call a native 2750 // function. When the probe is enabled the nops are replaced with a trap 2751 // instruction that dtrace inserts and the trace will cause a notification 2752 // to dtrace. 2753 // 2754 // The probes are only able to take primitive types and java/lang/String as 2755 // arguments. No other java types are allowed. Strings are converted to utf8 2756 // strings so that from dtrace point of view java strings are converted to C 2757 // strings. There is an arbitrary fixed limit on the total space that a method 2758 // can use for converting the strings. (256 chars per string in the signature). 2759 // So any java string larger then this is truncated. 2760 2761 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; 2762 static bool offsets_initialized = false; 2763 2764 nmethod *SharedRuntime::generate_dtrace_nmethod( 2765 MacroAssembler *masm, methodHandle method) { 2766 2767 2768 // generate_dtrace_nmethod is guarded by a mutex so we are sure to 2769 // be single threaded in this method. 2770 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); 2771 2772 // Fill in the signature array, for the calling-convention call. 2773 int total_args_passed = method->size_of_parameters(); 2774 2775 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); 2776 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); 2777 2778 // The signature we are going to use for the trap that dtrace will see 2779 // java/lang/String is converted. We drop "this" and any other object 2780 // is converted to NULL. (A one-slot java/lang/Long object reference 2781 // is converted to a two-slot long, which is why we double the allocation). 2782 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); 2783 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); 2784 2785 int i=0; 2786 int total_strings = 0; 2787 int first_arg_to_pass = 0; 2788 int total_c_args = 0; 2789 2790 // Skip the receiver as dtrace doesn't want to see it 2791 if( !method->is_static() ) { 2792 in_sig_bt[i++] = T_OBJECT; 2793 first_arg_to_pass = 1; 2794 } 2795 2796 SignatureStream ss(method->signature()); 2797 for ( ; !ss.at_return_type(); ss.next()) { 2798 BasicType bt = ss.type(); 2799 in_sig_bt[i++] = bt; // Collect remaining bits of signature 2800 out_sig_bt[total_c_args++] = bt; 2801 if( bt == T_OBJECT) { 2802 Symbol* s = ss.as_symbol_or_null(); 2803 if (s == vmSymbols::java_lang_String()) { 2804 total_strings++; 2805 out_sig_bt[total_c_args-1] = T_ADDRESS; 2806 } else if (s == vmSymbols::java_lang_Boolean() || 2807 s == vmSymbols::java_lang_Byte()) { 2808 out_sig_bt[total_c_args-1] = T_BYTE; 2809 } else if (s == vmSymbols::java_lang_Character() || 2810 s == vmSymbols::java_lang_Short()) { 2811 out_sig_bt[total_c_args-1] = T_SHORT; 2812 } else if (s == vmSymbols::java_lang_Integer() || 2813 s == vmSymbols::java_lang_Float()) { 2814 out_sig_bt[total_c_args-1] = T_INT; 2815 } else if (s == vmSymbols::java_lang_Long() || 2816 s == vmSymbols::java_lang_Double()) { 2817 out_sig_bt[total_c_args-1] = T_LONG; 2818 out_sig_bt[total_c_args++] = T_VOID; 2819 } 2820 } else if ( bt == T_LONG || bt == T_DOUBLE ) { 2821 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots 2822 // We convert double to long 2823 out_sig_bt[total_c_args-1] = T_LONG; 2824 out_sig_bt[total_c_args++] = T_VOID; 2825 } else if ( bt == T_FLOAT) { 2826 // We convert float to int 2827 out_sig_bt[total_c_args-1] = T_INT; 2828 } 2829 } 2830 2831 assert(i==total_args_passed, "validly parsed signature"); 2832 2833 // Now get the compiled-Java layout as input arguments 2834 int comp_args_on_stack; 2835 comp_args_on_stack = SharedRuntime::java_calling_convention( 2836 in_sig_bt, in_regs, total_args_passed, false); 2837 2838 // We have received a description of where all the java arg are located 2839 // on entry to the wrapper. We need to convert these args to where 2840 // the a native (non-jni) function would expect them. To figure out 2841 // where they go we convert the java signature to a C signature and remove 2842 // T_VOID for any long/double we might have received. 2843 2844 2845 // Now figure out where the args must be stored and how much stack space 2846 // they require (neglecting out_preserve_stack_slots but space for storing 2847 // the 1st six register arguments). It's weird see int_stk_helper. 2848 // 2849 int out_arg_slots; 2850 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); 2851 2852 // Calculate the total number of stack slots we will need. 2853 2854 // First count the abi requirement plus all of the outgoing args 2855 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 2856 2857 // Plus a temp for possible converion of float/double/long register args 2858 2859 int conversion_temp = stack_slots; 2860 stack_slots += 2; 2861 2862 2863 // Now space for the string(s) we must convert 2864 2865 int string_locs = stack_slots; 2866 stack_slots += total_strings * 2867 (max_dtrace_string_size / VMRegImpl::stack_slot_size); 2868 2869 // Ok The space we have allocated will look like: 2870 // 2871 // 2872 // FP-> | | 2873 // |---------------------| 2874 // | string[n] | 2875 // |---------------------| <- string_locs[n] 2876 // | string[n-1] | 2877 // |---------------------| <- string_locs[n-1] 2878 // | ... | 2879 // | ... | 2880 // |---------------------| <- string_locs[1] 2881 // | string[0] | 2882 // |---------------------| <- string_locs[0] 2883 // | temp | 2884 // |---------------------| <- conversion_temp 2885 // | outbound memory | 2886 // | based arguments | 2887 // | | 2888 // |---------------------| 2889 // | | 2890 // SP-> | out_preserved_slots | 2891 // 2892 // 2893 2894 // Now compute actual number of stack words we need rounding to make 2895 // stack properly aligned. 2896 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); 2897 2898 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 2899 2900 intptr_t start = (intptr_t)__ pc(); 2901 2902 // First thing make an ic check to see if we should even be here 2903 2904 { 2905 Label L; 2906 const Register temp_reg = G3_scratch; 2907 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); 2908 __ verify_oop(O0); 2909 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg); 2910 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); 2911 2912 __ jump_to(ic_miss, temp_reg); 2913 __ delayed()->nop(); 2914 __ align(CodeEntryAlignment); 2915 __ bind(L); 2916 } 2917 2918 int vep_offset = ((intptr_t)__ pc()) - start; 2919 2920 2921 // The instruction at the verified entry point must be 5 bytes or longer 2922 // because it can be patched on the fly by make_non_entrant. The stack bang 2923 // instruction fits that requirement. 2924 2925 // Generate stack overflow check before creating frame 2926 __ generate_stack_overflow_check(stack_size); 2927 2928 assert(((intptr_t)__ pc() - start - vep_offset) >= 5, 2929 "valid size for make_non_entrant"); 2930 2931 // Generate a new frame for the wrapper. 2932 __ save(SP, -stack_size, SP); 2933 2934 // Frame is now completed as far a size and linkage. 2935 2936 int frame_complete = ((intptr_t)__ pc()) - start; 2937 2938 #ifdef ASSERT 2939 bool reg_destroyed[RegisterImpl::number_of_registers]; 2940 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; 2941 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 2942 reg_destroyed[r] = false; 2943 } 2944 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { 2945 freg_destroyed[f] = false; 2946 } 2947 2948 #endif /* ASSERT */ 2949 2950 VMRegPair zero; 2951 const Register g0 = G0; // without this we get a compiler warning (why??) 2952 zero.set2(g0->as_VMReg()); 2953 2954 int c_arg, j_arg; 2955 2956 Register conversion_off = noreg; 2957 2958 for (j_arg = first_arg_to_pass, c_arg = 0 ; 2959 j_arg < total_args_passed ; j_arg++, c_arg++ ) { 2960 2961 VMRegPair src = in_regs[j_arg]; 2962 VMRegPair dst = out_regs[c_arg]; 2963 2964 #ifdef ASSERT 2965 if (src.first()->is_Register()) { 2966 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!"); 2967 } else if (src.first()->is_FloatRegister()) { 2968 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding( 2969 FloatRegisterImpl::S)], "ack!"); 2970 } 2971 if (dst.first()->is_Register()) { 2972 reg_destroyed[dst.first()->as_Register()->encoding()] = true; 2973 } else if (dst.first()->is_FloatRegister()) { 2974 freg_destroyed[dst.first()->as_FloatRegister()->encoding( 2975 FloatRegisterImpl::S)] = true; 2976 } 2977 #endif /* ASSERT */ 2978 2979 switch (in_sig_bt[j_arg]) { 2980 case T_ARRAY: 2981 case T_OBJECT: 2982 { 2983 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT || 2984 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { 2985 // need to unbox a one-slot value 2986 Register in_reg = L0; 2987 Register tmp = L2; 2988 if ( src.first()->is_reg() ) { 2989 in_reg = src.first()->as_Register(); 2990 } else { 2991 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS), 2992 "must be"); 2993 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg); 2994 } 2995 // If the final destination is an acceptable register 2996 if ( dst.first()->is_reg() ) { 2997 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) { 2998 tmp = dst.first()->as_Register(); 2999 } 3000 } 3001 3002 Label skipUnbox; 3003 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) { 3004 __ mov(G0, tmp->successor()); 3005 } 3006 __ br_null(in_reg, true, Assembler::pn, skipUnbox); 3007 __ delayed()->mov(G0, tmp); 3008 3009 BasicType bt = out_sig_bt[c_arg]; 3010 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); 3011 switch (bt) { 3012 case T_BYTE: 3013 __ ldub(in_reg, box_offset, tmp); break; 3014 case T_SHORT: 3015 __ lduh(in_reg, box_offset, tmp); break; 3016 case T_INT: 3017 __ ld(in_reg, box_offset, tmp); break; 3018 case T_LONG: 3019 __ ld_long(in_reg, box_offset, tmp); break; 3020 default: ShouldNotReachHere(); 3021 } 3022 3023 __ bind(skipUnbox); 3024 // If tmp wasn't final destination copy to final destination 3025 if (tmp == L2) { 3026 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2); 3027 if (out_sig_bt[c_arg] == T_LONG) { 3028 long_move(masm, tmp_as_VM, dst); 3029 } else { 3030 move32_64(masm, tmp_as_VM, out_regs[c_arg]); 3031 } 3032 } 3033 if (out_sig_bt[c_arg] == T_LONG) { 3034 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); 3035 ++c_arg; // move over the T_VOID to keep the loop indices in sync 3036 } 3037 } else if (out_sig_bt[c_arg] == T_ADDRESS) { 3038 Register s = 3039 src.first()->is_reg() ? src.first()->as_Register() : L2; 3040 Register d = 3041 dst.first()->is_reg() ? dst.first()->as_Register() : L2; 3042 3043 // We store the oop now so that the conversion pass can reach 3044 // while in the inner frame. This will be the only store if 3045 // the oop is NULL. 3046 if (s != L2) { 3047 // src is register 3048 if (d != L2) { 3049 // dst is register 3050 __ mov(s, d); 3051 } else { 3052 assert(Assembler::is_simm13(reg2offset(dst.first()) + 3053 STACK_BIAS), "must be"); 3054 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS); 3055 } 3056 } else { 3057 // src not a register 3058 assert(Assembler::is_simm13(reg2offset(src.first()) + 3059 STACK_BIAS), "must be"); 3060 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d); 3061 if (d == L2) { 3062 assert(Assembler::is_simm13(reg2offset(dst.first()) + 3063 STACK_BIAS), "must be"); 3064 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS); 3065 } 3066 } 3067 } else if (out_sig_bt[c_arg] != T_VOID) { 3068 // Convert the arg to NULL 3069 if (dst.first()->is_reg()) { 3070 __ mov(G0, dst.first()->as_Register()); 3071 } else { 3072 assert(Assembler::is_simm13(reg2offset(dst.first()) + 3073 STACK_BIAS), "must be"); 3074 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS); 3075 } 3076 } 3077 } 3078 break; 3079 case T_VOID: 3080 break; 3081 3082 case T_FLOAT: 3083 if (src.first()->is_stack()) { 3084 // Stack to stack/reg is simple 3085 move32_64(masm, src, dst); 3086 } else { 3087 if (dst.first()->is_reg()) { 3088 // freg -> reg 3089 int off = 3090 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; 3091 Register d = dst.first()->as_Register(); 3092 if (Assembler::is_simm13(off)) { 3093 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3094 SP, off); 3095 __ ld(SP, off, d); 3096 } else { 3097 if (conversion_off == noreg) { 3098 __ set(off, L6); 3099 conversion_off = L6; 3100 } 3101 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3102 SP, conversion_off); 3103 __ ld(SP, conversion_off , d); 3104 } 3105 } else { 3106 // freg -> mem 3107 int off = STACK_BIAS + reg2offset(dst.first()); 3108 if (Assembler::is_simm13(off)) { 3109 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3110 SP, off); 3111 } else { 3112 if (conversion_off == noreg) { 3113 __ set(off, L6); 3114 conversion_off = L6; 3115 } 3116 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3117 SP, conversion_off); 3118 } 3119 } 3120 } 3121 break; 3122 3123 case T_DOUBLE: 3124 assert( j_arg + 1 < total_args_passed && 3125 in_sig_bt[j_arg + 1] == T_VOID && 3126 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 3127 if (src.first()->is_stack()) { 3128 // Stack to stack/reg is simple 3129 long_move(masm, src, dst); 3130 } else { 3131 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2; 3132 3133 // Destination could be an odd reg on 32bit in which case 3134 // we can't load direct to the destination. 3135 3136 if (!d->is_even() && wordSize == 4) { 3137 d = L2; 3138 } 3139 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; 3140 if (Assembler::is_simm13(off)) { 3141 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), 3142 SP, off); 3143 __ ld_long(SP, off, d); 3144 } else { 3145 if (conversion_off == noreg) { 3146 __ set(off, L6); 3147 conversion_off = L6; 3148 } 3149 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), 3150 SP, conversion_off); 3151 __ ld_long(SP, conversion_off, d); 3152 } 3153 if (d == L2) { 3154 long_move(masm, reg64_to_VMRegPair(L2), dst); 3155 } 3156 } 3157 break; 3158 3159 case T_LONG : 3160 // 32bit can't do a split move of something like g1 -> O0, O1 3161 // so use a memory temp 3162 if (src.is_single_phys_reg() && wordSize == 4) { 3163 Register tmp = L2; 3164 if (dst.first()->is_reg() && 3165 (wordSize == 8 || dst.first()->as_Register()->is_even())) { 3166 tmp = dst.first()->as_Register(); 3167 } 3168 3169 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; 3170 if (Assembler::is_simm13(off)) { 3171 __ stx(src.first()->as_Register(), SP, off); 3172 __ ld_long(SP, off, tmp); 3173 } else { 3174 if (conversion_off == noreg) { 3175 __ set(off, L6); 3176 conversion_off = L6; 3177 } 3178 __ stx(src.first()->as_Register(), SP, conversion_off); 3179 __ ld_long(SP, conversion_off, tmp); 3180 } 3181 3182 if (tmp == L2) { 3183 long_move(masm, reg64_to_VMRegPair(L2), dst); 3184 } 3185 } else { 3186 long_move(masm, src, dst); 3187 } 3188 break; 3189 3190 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 3191 3192 default: 3193 move32_64(masm, src, dst); 3194 } 3195 } 3196 3197 3198 // If we have any strings we must store any register based arg to the stack 3199 // This includes any still live xmm registers too. 3200 3201 if (total_strings > 0 ) { 3202 3203 // protect all the arg registers 3204 __ save_frame(0); 3205 __ mov(G2_thread, L7_thread_cache); 3206 const Register L2_string_off = L2; 3207 3208 // Get first string offset 3209 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off); 3210 3211 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) { 3212 if (out_sig_bt[c_arg] == T_ADDRESS) { 3213 3214 VMRegPair dst = out_regs[c_arg]; 3215 const Register d = dst.first()->is_reg() ? 3216 dst.first()->as_Register()->after_save() : noreg; 3217 3218 // It's a string the oop and it was already copied to the out arg 3219 // position 3220 if (d != noreg) { 3221 __ mov(d, O0); 3222 } else { 3223 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), 3224 "must be"); 3225 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0); 3226 } 3227 Label skip; 3228 3229 __ br_null(O0, false, Assembler::pn, skip); 3230 __ delayed()->add(FP, L2_string_off, O1); 3231 3232 if (d != noreg) { 3233 __ mov(O1, d); 3234 } else { 3235 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), 3236 "must be"); 3237 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS); 3238 } 3239 3240 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf), 3241 relocInfo::runtime_call_type); 3242 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off); 3243 3244 __ bind(skip); 3245 3246 } 3247 3248 } 3249 __ mov(L7_thread_cache, G2_thread); 3250 __ restore(); 3251 3252 } 3253 3254 3255 // Ok now we are done. Need to place the nop that dtrace wants in order to 3256 // patch in the trap 3257 3258 int patch_offset = ((intptr_t)__ pc()) - start; 3259 3260 __ nop(); 3261 3262 3263 // Return 3264 3265 __ ret(); 3266 __ delayed()->restore(); 3267 3268 __ flush(); 3269 3270 nmethod *nm = nmethod::new_dtrace_nmethod( 3271 method, masm->code(), vep_offset, patch_offset, frame_complete, 3272 stack_slots / VMRegImpl::slots_per_word); 3273 return nm; 3274 3275 } 3276 3277 #endif // HAVE_DTRACE_H 3278 3279 // this function returns the adjust size (in number of words) to a c2i adapter 3280 // activation for use during deoptimization 3281 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { 3282 assert(callee_locals >= callee_parameters, 3283 "test and remove; got more parms than locals"); 3284 if (callee_locals < callee_parameters) 3285 return 0; // No adjustment for negative locals 3286 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; 3287 return round_to(diff, WordsPerLong); 3288 } 3289 3290 // "Top of Stack" slots that may be unused by the calling convention but must 3291 // otherwise be preserved. 3292 // On Intel these are not necessary and the value can be zero. 3293 // On Sparc this describes the words reserved for storing a register window 3294 // when an interrupt occurs. 3295 uint SharedRuntime::out_preserve_stack_slots() { 3296 return frame::register_save_words * VMRegImpl::slots_per_word; 3297 } 3298 3299 static void gen_new_frame(MacroAssembler* masm, bool deopt) { 3300 // 3301 // Common out the new frame generation for deopt and uncommon trap 3302 // 3303 Register G3pcs = G3_scratch; // Array of new pcs (input) 3304 Register Oreturn0 = O0; 3305 Register Oreturn1 = O1; 3306 Register O2UnrollBlock = O2; 3307 Register O3array = O3; // Array of frame sizes (input) 3308 Register O4array_size = O4; // number of frames (input) 3309 Register O7frame_size = O7; // number of frames (input) 3310 3311 __ ld_ptr(O3array, 0, O7frame_size); 3312 __ sub(G0, O7frame_size, O7frame_size); 3313 __ save(SP, O7frame_size, SP); 3314 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc 3315 3316 #ifdef ASSERT 3317 // make sure that the frames are aligned properly 3318 #ifndef _LP64 3319 __ btst(wordSize*2-1, SP); 3320 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc); 3321 #endif 3322 #endif 3323 3324 // Deopt needs to pass some extra live values from frame to frame 3325 3326 if (deopt) { 3327 __ mov(Oreturn0->after_save(), Oreturn0); 3328 __ mov(Oreturn1->after_save(), Oreturn1); 3329 } 3330 3331 __ mov(O4array_size->after_save(), O4array_size); 3332 __ sub(O4array_size, 1, O4array_size); 3333 __ mov(O3array->after_save(), O3array); 3334 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock); 3335 __ add(G3pcs, wordSize, G3pcs); // point to next pc value 3336 3337 #ifdef ASSERT 3338 // trash registers to show a clear pattern in backtraces 3339 __ set(0xDEAD0000, I0); 3340 __ add(I0, 2, I1); 3341 __ add(I0, 4, I2); 3342 __ add(I0, 6, I3); 3343 __ add(I0, 8, I4); 3344 // Don't touch I5 could have valuable savedSP 3345 __ set(0xDEADBEEF, L0); 3346 __ mov(L0, L1); 3347 __ mov(L0, L2); 3348 __ mov(L0, L3); 3349 __ mov(L0, L4); 3350 __ mov(L0, L5); 3351 3352 // trash the return value as there is nothing to return yet 3353 __ set(0xDEAD0001, O7); 3354 #endif 3355 3356 __ mov(SP, O5_savedSP); 3357 } 3358 3359 3360 static void make_new_frames(MacroAssembler* masm, bool deopt) { 3361 // 3362 // loop through the UnrollBlock info and create new frames 3363 // 3364 Register G3pcs = G3_scratch; 3365 Register Oreturn0 = O0; 3366 Register Oreturn1 = O1; 3367 Register O2UnrollBlock = O2; 3368 Register O3array = O3; 3369 Register O4array_size = O4; 3370 Label loop; 3371 3372 // Before we make new frames, check to see if stack is available. 3373 // Do this after the caller's return address is on top of stack 3374 if (UseStackBanging) { 3375 // Get total frame size for interpreted frames 3376 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4); 3377 __ bang_stack_size(O4, O3, G3_scratch); 3378 } 3379 3380 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size); 3381 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs); 3382 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array); 3383 3384 // Adjust old interpreter frame to make space for new frame's extra java locals 3385 // 3386 // We capture the original sp for the transition frame only because it is needed in 3387 // order to properly calculate interpreter_sp_adjustment. Even though in real life 3388 // every interpreter frame captures a savedSP it is only needed at the transition 3389 // (fortunately). If we had to have it correct everywhere then we would need to 3390 // be told the sp_adjustment for each frame we create. If the frame size array 3391 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size] 3392 // for each frame we create and keep up the illusion every where. 3393 // 3394 3395 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7); 3396 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment 3397 __ sub(SP, O7, SP); 3398 3399 #ifdef ASSERT 3400 // make sure that there is at least one entry in the array 3401 __ tst(O4array_size); 3402 __ breakpoint_trap(Assembler::zero, Assembler::icc); 3403 #endif 3404 3405 // Now push the new interpreter frames 3406 __ bind(loop); 3407 3408 // allocate a new frame, filling the registers 3409 3410 gen_new_frame(masm, deopt); // allocate an interpreter frame 3411 3412 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop); 3413 __ delayed()->add(O3array, wordSize, O3array); 3414 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc 3415 3416 } 3417 3418 //------------------------------generate_deopt_blob---------------------------- 3419 // Ought to generate an ideal graph & compile, but here's some SPARC ASM 3420 // instead. 3421 void SharedRuntime::generate_deopt_blob() { 3422 // allocate space for the code 3423 ResourceMark rm; 3424 // setup code generation tools 3425 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code 3426 if (UseStackBanging) { 3427 pad += StackShadowPages*16 + 32; 3428 } 3429 #ifdef _LP64 3430 CodeBuffer buffer("deopt_blob", 2100+pad, 512); 3431 #else 3432 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread) 3433 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread) 3434 CodeBuffer buffer("deopt_blob", 1600+pad, 512); 3435 #endif /* _LP64 */ 3436 MacroAssembler* masm = new MacroAssembler(&buffer); 3437 FloatRegister Freturn0 = F0; 3438 Register Greturn1 = G1; 3439 Register Oreturn0 = O0; 3440 Register Oreturn1 = O1; 3441 Register O2UnrollBlock = O2; 3442 Register L0deopt_mode = L0; 3443 Register G4deopt_mode = G4_scratch; 3444 int frame_size_words; 3445 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS); 3446 #if !defined(_LP64) && defined(COMPILER2) 3447 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS); 3448 #endif 3449 Label cont; 3450 3451 OopMapSet *oop_maps = new OopMapSet(); 3452 3453 // 3454 // This is the entry point for code which is returning to a de-optimized 3455 // frame. 3456 // The steps taken by this frame are as follows: 3457 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1) 3458 // and all potentially live registers (at a pollpoint many registers can be live). 3459 // 3460 // - call the C routine: Deoptimization::fetch_unroll_info (this function 3461 // returns information about the number and size of interpreter frames 3462 // which are equivalent to the frame which is being deoptimized) 3463 // - deallocate the unpack frame, restoring only results values. Other 3464 // volatile registers will now be captured in the vframeArray as needed. 3465 // - deallocate the deoptimization frame 3466 // - in a loop using the information returned in the previous step 3467 // push new interpreter frames (take care to propagate the return 3468 // values through each new frame pushed) 3469 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0) 3470 // - call the C routine: Deoptimization::unpack_frames (this function 3471 // lays out values on the interpreter frame which was just created) 3472 // - deallocate the dummy unpack_frame 3473 // - ensure that all the return values are correctly set and then do 3474 // a return to the interpreter entry point 3475 // 3476 // Refer to the following methods for more information: 3477 // - Deoptimization::fetch_unroll_info 3478 // - Deoptimization::unpack_frames 3479 3480 OopMap* map = NULL; 3481 3482 int start = __ offset(); 3483 3484 // restore G2, the trampoline destroyed it 3485 __ get_thread(); 3486 3487 // On entry we have been called by the deoptimized nmethod with a call that 3488 // replaced the original call (or safepoint polling location) so the deoptimizing 3489 // pc is now in O7. Return values are still in the expected places 3490 3491 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3492 __ ba(cont); 3493 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode); 3494 3495 int exception_offset = __ offset() - start; 3496 3497 // restore G2, the trampoline destroyed it 3498 __ get_thread(); 3499 3500 // On entry we have been jumped to by the exception handler (or exception_blob 3501 // for server). O0 contains the exception oop and O7 contains the original 3502 // exception pc. So if we push a frame here it will look to the 3503 // stack walking code (fetch_unroll_info) just like a normal call so 3504 // state will be extracted normally. 3505 3506 // save exception oop in JavaThread and fall through into the 3507 // exception_in_tls case since they are handled in same way except 3508 // for where the pending exception is kept. 3509 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset()); 3510 3511 // 3512 // Vanilla deoptimization with an exception pending in exception_oop 3513 // 3514 int exception_in_tls_offset = __ offset() - start; 3515 3516 // No need to update oop_map as each call to save_live_registers will produce identical oopmap 3517 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3518 3519 // Restore G2_thread 3520 __ get_thread(); 3521 3522 #ifdef ASSERT 3523 { 3524 // verify that there is really an exception oop in exception_oop 3525 Label has_exception; 3526 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); 3527 __ br_notnull_short(Oexception, Assembler::pt, has_exception); 3528 __ stop("no exception in thread"); 3529 __ bind(has_exception); 3530 3531 // verify that there is no pending exception 3532 Label no_pending_exception; 3533 Address exception_addr(G2_thread, Thread::pending_exception_offset()); 3534 __ ld_ptr(exception_addr, Oexception); 3535 __ br_null_short(Oexception, Assembler::pt, no_pending_exception); 3536 __ stop("must not have pending exception here"); 3537 __ bind(no_pending_exception); 3538 } 3539 #endif 3540 3541 __ ba(cont); 3542 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);; 3543 3544 // 3545 // Reexecute entry, similar to c2 uncommon trap 3546 // 3547 int reexecute_offset = __ offset() - start; 3548 3549 // No need to update oop_map as each call to save_live_registers will produce identical oopmap 3550 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3551 3552 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode); 3553 3554 __ bind(cont); 3555 3556 __ set_last_Java_frame(SP, noreg); 3557 3558 // do the call by hand so we can get the oopmap 3559 3560 __ mov(G2_thread, L7_thread_cache); 3561 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type); 3562 __ delayed()->mov(G2_thread, O0); 3563 3564 // Set an oopmap for the call site this describes all our saved volatile registers 3565 3566 oop_maps->add_gc_map( __ offset()-start, map); 3567 3568 __ mov(L7_thread_cache, G2_thread); 3569 3570 __ reset_last_Java_frame(); 3571 3572 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers 3573 // so this move will survive 3574 3575 __ mov(L0deopt_mode, G4deopt_mode); 3576 3577 __ mov(O0, O2UnrollBlock->after_save()); 3578 3579 RegisterSaver::restore_result_registers(masm); 3580 3581 Label noException; 3582 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException); 3583 3584 // Move the pending exception from exception_oop to Oexception so 3585 // the pending exception will be picked up the interpreter. 3586 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception); 3587 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); 3588 __ bind(noException); 3589 3590 // deallocate the deoptimization frame taking care to preserve the return values 3591 __ mov(Oreturn0, Oreturn0->after_save()); 3592 __ mov(Oreturn1, Oreturn1->after_save()); 3593 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); 3594 __ restore(); 3595 3596 // Allocate new interpreter frame(s) and possible c2i adapter frame 3597 3598 make_new_frames(masm, true); 3599 3600 // push a dummy "unpack_frame" taking care of float return values and 3601 // call Deoptimization::unpack_frames to have the unpacker layout 3602 // information in the interpreter frames just created and then return 3603 // to the interpreter entry point 3604 __ save(SP, -frame_size_words*wordSize, SP); 3605 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr); 3606 #if !defined(_LP64) 3607 #if defined(COMPILER2) 3608 // 32-bit 1-register longs return longs in G1 3609 __ stx(Greturn1, saved_Greturn1_addr); 3610 #endif 3611 __ set_last_Java_frame(SP, noreg); 3612 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode); 3613 #else 3614 // LP64 uses g4 in set_last_Java_frame 3615 __ mov(G4deopt_mode, O1); 3616 __ set_last_Java_frame(SP, G0); 3617 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1); 3618 #endif 3619 __ reset_last_Java_frame(); 3620 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0); 3621 3622 #if !defined(_LP64) && defined(COMPILER2) 3623 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into 3624 // I0/I1 if the return value is long. 3625 Label not_long; 3626 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long); 3627 __ ldd(saved_Greturn1_addr,I0); 3628 __ bind(not_long); 3629 #endif 3630 __ ret(); 3631 __ delayed()->restore(); 3632 3633 masm->flush(); 3634 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words); 3635 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); 3636 } 3637 3638 #ifdef COMPILER2 3639 3640 //------------------------------generate_uncommon_trap_blob-------------------- 3641 // Ought to generate an ideal graph & compile, but here's some SPARC ASM 3642 // instead. 3643 void SharedRuntime::generate_uncommon_trap_blob() { 3644 // allocate space for the code 3645 ResourceMark rm; 3646 // setup code generation tools 3647 int pad = VerifyThread ? 512 : 0; 3648 if (UseStackBanging) { 3649 pad += StackShadowPages*16 + 32; 3650 } 3651 #ifdef _LP64 3652 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512); 3653 #else 3654 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread) 3655 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread) 3656 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512); 3657 #endif 3658 MacroAssembler* masm = new MacroAssembler(&buffer); 3659 Register O2UnrollBlock = O2; 3660 Register O2klass_index = O2; 3661 3662 // 3663 // This is the entry point for all traps the compiler takes when it thinks 3664 // it cannot handle further execution of compilation code. The frame is 3665 // deoptimized in these cases and converted into interpreter frames for 3666 // execution 3667 // The steps taken by this frame are as follows: 3668 // - push a fake "unpack_frame" 3669 // - call the C routine Deoptimization::uncommon_trap (this function 3670 // packs the current compiled frame into vframe arrays and returns 3671 // information about the number and size of interpreter frames which 3672 // are equivalent to the frame which is being deoptimized) 3673 // - deallocate the "unpack_frame" 3674 // - deallocate the deoptimization frame 3675 // - in a loop using the information returned in the previous step 3676 // push interpreter frames; 3677 // - create a dummy "unpack_frame" 3678 // - call the C routine: Deoptimization::unpack_frames (this function 3679 // lays out values on the interpreter frame which was just created) 3680 // - deallocate the dummy unpack_frame 3681 // - return to the interpreter entry point 3682 // 3683 // Refer to the following methods for more information: 3684 // - Deoptimization::uncommon_trap 3685 // - Deoptimization::unpack_frame 3686 3687 // the unloaded class index is in O0 (first parameter to this blob) 3688 3689 // push a dummy "unpack_frame" 3690 // and call Deoptimization::uncommon_trap to pack the compiled frame into 3691 // vframe array and return the UnrollBlock information 3692 __ save_frame(0); 3693 __ set_last_Java_frame(SP, noreg); 3694 __ mov(I0, O2klass_index); 3695 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index); 3696 __ reset_last_Java_frame(); 3697 __ mov(O0, O2UnrollBlock->after_save()); 3698 __ restore(); 3699 3700 // deallocate the deoptimized frame taking care to preserve the return values 3701 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); 3702 __ restore(); 3703 3704 // Allocate new interpreter frame(s) and possible c2i adapter frame 3705 3706 make_new_frames(masm, false); 3707 3708 // push a dummy "unpack_frame" taking care of float return values and 3709 // call Deoptimization::unpack_frames to have the unpacker layout 3710 // information in the interpreter frames just created and then return 3711 // to the interpreter entry point 3712 __ save_frame(0); 3713 __ set_last_Java_frame(SP, noreg); 3714 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case 3715 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3); 3716 __ reset_last_Java_frame(); 3717 __ ret(); 3718 __ delayed()->restore(); 3719 3720 masm->flush(); 3721 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize); 3722 } 3723 3724 #endif // COMPILER2 3725 3726 //------------------------------generate_handler_blob------------------- 3727 // 3728 // Generate a special Compile2Runtime blob that saves all registers, and sets 3729 // up an OopMap. 3730 // 3731 // This blob is jumped to (via a breakpoint and the signal handler) from a 3732 // safepoint in compiled code. On entry to this blob, O7 contains the 3733 // address in the original nmethod at which we should resume normal execution. 3734 // Thus, this blob looks like a subroutine which must preserve lots of 3735 // registers and return normally. Note that O7 is never register-allocated, 3736 // so it is guaranteed to be free here. 3737 // 3738 3739 // The hardest part of what this blob must do is to save the 64-bit %o 3740 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and 3741 // an interrupt will chop off their heads. Making space in the caller's frame 3742 // first will let us save the 64-bit %o's before save'ing, but we cannot hand 3743 // the adjusted FP off to the GC stack-crawler: this will modify the caller's 3744 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save 3745 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP). 3746 // Tricky, tricky, tricky... 3747 3748 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { 3749 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 3750 3751 // allocate space for the code 3752 ResourceMark rm; 3753 // setup code generation tools 3754 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) 3755 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) 3756 // even larger with TraceJumps 3757 int pad = TraceJumps ? 512 : 0; 3758 CodeBuffer buffer("handler_blob", 1600 + pad, 512); 3759 MacroAssembler* masm = new MacroAssembler(&buffer); 3760 int frame_size_words; 3761 OopMapSet *oop_maps = new OopMapSet(); 3762 OopMap* map = NULL; 3763 3764 int start = __ offset(); 3765 3766 bool cause_return = (poll_type == POLL_AT_RETURN); 3767 // If this causes a return before the processing, then do a "restore" 3768 if (cause_return) { 3769 __ restore(); 3770 } else { 3771 // Make it look like we were called via the poll 3772 // so that frame constructor always sees a valid return address 3773 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7); 3774 __ sub(O7, frame::pc_return_offset, O7); 3775 } 3776 3777 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3778 3779 // setup last_Java_sp (blows G4) 3780 __ set_last_Java_frame(SP, noreg); 3781 3782 // call into the runtime to handle illegal instructions exception 3783 // Do not use call_VM_leaf, because we need to make a GC map at this call site. 3784 __ mov(G2_thread, O0); 3785 __ save_thread(L7_thread_cache); 3786 __ call(call_ptr); 3787 __ delayed()->nop(); 3788 3789 // Set an oopmap for the call site. 3790 // We need this not only for callee-saved registers, but also for volatile 3791 // registers that the compiler might be keeping live across a safepoint. 3792 3793 oop_maps->add_gc_map( __ offset() - start, map); 3794 3795 __ restore_thread(L7_thread_cache); 3796 // clear last_Java_sp 3797 __ reset_last_Java_frame(); 3798 3799 // Check for exceptions 3800 Label pending; 3801 3802 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); 3803 __ br_notnull_short(O1, Assembler::pn, pending); 3804 3805 RegisterSaver::restore_live_registers(masm); 3806 3807 // We are back the the original state on entry and ready to go. 3808 3809 __ retl(); 3810 __ delayed()->nop(); 3811 3812 // Pending exception after the safepoint 3813 3814 __ bind(pending); 3815 3816 RegisterSaver::restore_live_registers(masm); 3817 3818 // We are back the the original state on entry. 3819 3820 // Tail-call forward_exception_entry, with the issuing PC in O7, 3821 // so it looks like the original nmethod called forward_exception_entry. 3822 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); 3823 __ JMP(O0, 0); 3824 __ delayed()->nop(); 3825 3826 // ------------- 3827 // make sure all code is generated 3828 masm->flush(); 3829 3830 // return exception blob 3831 return SafepointBlob::create(&buffer, oop_maps, frame_size_words); 3832 } 3833 3834 // 3835 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss 3836 // 3837 // Generate a stub that calls into vm to find out the proper destination 3838 // of a java call. All the argument registers are live at this point 3839 // but since this is generic code we don't know what they are and the caller 3840 // must do any gc of the args. 3841 // 3842 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { 3843 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 3844 3845 // allocate space for the code 3846 ResourceMark rm; 3847 // setup code generation tools 3848 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) 3849 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) 3850 // even larger with TraceJumps 3851 int pad = TraceJumps ? 512 : 0; 3852 CodeBuffer buffer(name, 1600 + pad, 512); 3853 MacroAssembler* masm = new MacroAssembler(&buffer); 3854 int frame_size_words; 3855 OopMapSet *oop_maps = new OopMapSet(); 3856 OopMap* map = NULL; 3857 3858 int start = __ offset(); 3859 3860 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3861 3862 int frame_complete = __ offset(); 3863 3864 // setup last_Java_sp (blows G4) 3865 __ set_last_Java_frame(SP, noreg); 3866 3867 // call into the runtime to handle illegal instructions exception 3868 // Do not use call_VM_leaf, because we need to make a GC map at this call site. 3869 __ mov(G2_thread, O0); 3870 __ save_thread(L7_thread_cache); 3871 __ call(destination, relocInfo::runtime_call_type); 3872 __ delayed()->nop(); 3873 3874 // O0 contains the address we are going to jump to assuming no exception got installed 3875 3876 // Set an oopmap for the call site. 3877 // We need this not only for callee-saved registers, but also for volatile 3878 // registers that the compiler might be keeping live across a safepoint. 3879 3880 oop_maps->add_gc_map( __ offset() - start, map); 3881 3882 __ restore_thread(L7_thread_cache); 3883 // clear last_Java_sp 3884 __ reset_last_Java_frame(); 3885 3886 // Check for exceptions 3887 Label pending; 3888 3889 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); 3890 __ br_notnull_short(O1, Assembler::pn, pending); 3891 3892 // get the returned Method* 3893 3894 __ get_vm_result_2(G5_method); 3895 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS); 3896 3897 // O0 is where we want to jump, overwrite G3 which is saved and scratch 3898 3899 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS); 3900 3901 RegisterSaver::restore_live_registers(masm); 3902 3903 // We are back the the original state on entry and ready to go. 3904 3905 __ JMP(G3, 0); 3906 __ delayed()->nop(); 3907 3908 // Pending exception after the safepoint 3909 3910 __ bind(pending); 3911 3912 RegisterSaver::restore_live_registers(masm); 3913 3914 // We are back the the original state on entry. 3915 3916 // Tail-call forward_exception_entry, with the issuing PC in O7, 3917 // so it looks like the original nmethod called forward_exception_entry. 3918 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); 3919 __ JMP(O0, 0); 3920 __ delayed()->nop(); 3921 3922 // ------------- 3923 // make sure all code is generated 3924 masm->flush(); 3925 3926 // return the blob 3927 // frame_size_words or bytes?? 3928 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); 3929 }