1 //
   2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // X86 Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 
  32 register %{
  33 //----------Architecture Description Register Definitions----------------------
  34 // General Registers
  35 // "reg_def"  name ( register save type, C convention save type,
  36 //                   ideal register type, encoding );
  37 // Register Save Types:
  38 //
  39 // NS  = No-Save:       The register allocator assumes that these registers
  40 //                      can be used without saving upon entry to the method, &
  41 //                      that they do not need to be saved at call sites.
  42 //
  43 // SOC = Save-On-Call:  The register allocator assumes that these registers
  44 //                      can be used without saving upon entry to the method,
  45 //                      but that they must be saved at call sites.
  46 //
  47 // SOE = Save-On-Entry: The register allocator assumes that these registers
  48 //                      must be saved before using them upon entry to the
  49 //                      method, but they do not need to be saved at call
  50 //                      sites.
  51 //
  52 // AS  = Always-Save:   The register allocator assumes that these registers
  53 //                      must be saved before using them upon entry to the
  54 //                      method, & that they must be saved at call sites.
  55 //
  56 // Ideal Register Type is used to determine how to save & restore a
  57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  59 //
  60 // The encoding number is the actual bit-pattern placed into the opcodes.
  61 
  62 // General Registers
  63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
  64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
  65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
  66 
  67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
  68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
  69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
  70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
  71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
  72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
  73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
  74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
  75 reg_def ESP( NS,  NS, Op_RegI, 4, rsp->as_VMReg());
  76 
  77 // Float registers.  We treat TOS/FPR0 special.  It is invisible to the
  78 // allocator, and only shows up in the encodings.
  79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
  80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
  81 // Ok so here's the trick FPR1 is really st(0) except in the midst
  82 // of emission of assembly for a machnode. During the emission the fpu stack
  83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
  84 // the stack will not have this element so FPR1 == st(0) from the
  85 // oopMap viewpoint. This same weirdness with numbering causes
  86 // instruction encoding to have to play games with the register
  87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
  88 // where it does flt->flt moves to see an example
  89 //
  90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
  91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
  92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
  93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
  94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
  95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
  96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
  97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
  98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
  99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
 104 
 105 // Specify priority of register selection within phases of register
 106 // allocation.  Highest priority is first.  A useful heuristic is to
 107 // give registers a low priority when they are required by machine
 108 // instructions, like EAX and EDX.  Registers which are used as
 109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
 110 // For the Intel integer registers, the equivalent Long pairs are
 111 // EDX:EAX, EBX:ECX, and EDI:EBP.
 112 alloc_class chunk0( ECX,   EBX,   EBP,   EDI,   EAX,   EDX,   ESI, ESP,
 113                     FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
 114                     FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
 115                     FPR6L, FPR6H, FPR7L, FPR7H );
 116 
 117 
 118 //----------Architecture Description Register Classes--------------------------
 119 // Several register classes are automatically defined based upon information in
 120 // this architecture description.
 121 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
 122 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )
 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 125 //
 126 // Class for all registers
 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
 128 // Class for general registers
 129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
 130 // Class for general registers which may be used for implicit null checks on win95
 131 // Also safe for use by tailjump. We don't want to allocate in rbp,
 132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
 133 // Class of "X" registers
 134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
 135 // Class of registers that can appear in an address with no offset.
 136 // EBP and ESP require an extra instruction byte for zero offset.
 137 // Used in fast-unlock
 138 reg_class p_reg(EDX, EDI, ESI, EBX);
 139 // Class for general registers not including ECX
 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
 141 // Class for general registers not including EAX
 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
 143 // Class for general registers not including EAX or EBX.
 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
 145 // Class of EAX (for multiply and divide operations)
 146 reg_class eax_reg(EAX);
 147 // Class of EBX (for atomic add)
 148 reg_class ebx_reg(EBX);
 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
 150 reg_class ecx_reg(ECX);
 151 // Class of EDX (for multiply and divide operations)
 152 reg_class edx_reg(EDX);
 153 // Class of EDI (for synchronization)
 154 reg_class edi_reg(EDI);
 155 // Class of ESI (for synchronization)
 156 reg_class esi_reg(ESI);
 157 // Singleton class for interpreter's stack pointer
 158 reg_class ebp_reg(EBP);
 159 // Singleton class for stack pointer
 160 reg_class sp_reg(ESP);
 161 // Singleton class for instruction pointer
 162 // reg_class ip_reg(EIP);
 163 // Class of integer register pairs
 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
 165 // Class of integer register pairs that aligns with calling convention
 166 reg_class eadx_reg( EAX,EDX );
 167 reg_class ebcx_reg( ECX,EBX );
 168 // Not AX or DX, used in divides
 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
 170 
 171 // Floating point registers.  Notice FPR0 is not a choice.
 172 // FPR0 is not ever allocated; we use clever encodings to fake
 173 // a 2-address instructions out of Intels FP stack.
 174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
 175 
 176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
 177                       FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
 178                       FPR7L,FPR7H );
 179 
 180 reg_class fp_flt_reg0( FPR1L );
 181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
 182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
 183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
 184                           FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
 185 
 186 %}
 187 
 188 
 189 //----------SOURCE BLOCK-------------------------------------------------------
 190 // This is a block of C++ code which provides values, functions, and
 191 // definitions necessary in the rest of the architecture description
 192 source_hpp %{
 193 // Must be visible to the DFA in dfa_x86_32.cpp
 194 extern bool is_operand_hi32_zero(Node* n);
 195 %}
 196 
 197 source %{
 198 #define   RELOC_IMM32    Assembler::imm_operand
 199 #define   RELOC_DISP32   Assembler::disp32_operand
 200 
 201 #define __ _masm.
 202 
 203 // How to find the high register of a Long pair, given the low register
 204 #define   HIGH_FROM_LOW(x) ((x)+2)
 205 
 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
 207 // instructions, to allow sign-masking or sign-bit flipping.  They allow
 208 // fast versions of NegF/NegD and AbsF/AbsD.
 209 
 210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
 212   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
 213   // of 128-bits operands for SSE instructions.
 214   jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
 215   // Store the value to a 128-bits operand.
 216   operand[0] = lo;
 217   operand[1] = hi;
 218   return operand;
 219 }
 220 
 221 // Buffer for 128-bits masks used by SSE instructions.
 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
 223 
 224 // Static initialization during VM startup.
 225 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
 227 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
 229 
 230 // Offset hacking within calls.
 231 static int pre_call_resets_size() {
 232   int size = 0;
 233   Compile* C = Compile::current();
 234   if (C->in_24_bit_fp_mode()) {
 235     size += 6; // fldcw
 236   }
 237   if (C->max_vector_size() > 16) {
 238     size += 3; // vzeroupper
 239   }
 240   return size;
 241 }
 242 
 243 static int preserve_SP_size() {
 244   return 2;  // op, rm(reg/reg)
 245 }
 246 
 247 // !!!!! Special hack to get all type of calls to specify the byte offset
 248 //       from the start of the call to the point where the return address
 249 //       will point.
 250 int MachCallStaticJavaNode::ret_addr_offset() {
 251   int offset = 5 + pre_call_resets_size();  // 5 bytes from start of call to where return address points
 252   if (_method_handle_invoke)
 253     offset += preserve_SP_size();
 254   return offset;
 255 }
 256 
 257 int MachCallDynamicJavaNode::ret_addr_offset() {
 258   return 10 + pre_call_resets_size();  // 10 bytes from start of call to where return address points
 259 }
 260 
 261 static int sizeof_FFree_Float_Stack_All = -1;
 262 
 263 int MachCallRuntimeNode::ret_addr_offset() {
 264   assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
 265   return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
 266 }
 267 
 268 // Indicate if the safepoint node needs the polling page as an input.
 269 // Since x86 does have absolute addressing, it doesn't.
 270 bool SafePointNode::needs_polling_address_input() {
 271   return false;
 272 }
 273 
 274 //
 275 // Compute padding required for nodes which need alignment
 276 //
 277 
 278 // The address of the call instruction needs to be 4-byte aligned to
 279 // ensure that it does not span a cache line so that it can be patched.
 280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
 281   current_offset += pre_call_resets_size();  // skip fldcw, if any
 282   current_offset += 1;      // skip call opcode byte
 283   return round_to(current_offset, alignment_required()) - current_offset;
 284 }
 285 
 286 // The address of the call instruction needs to be 4-byte aligned to
 287 // ensure that it does not span a cache line so that it can be patched.
 288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
 289   current_offset += pre_call_resets_size();  // skip fldcw, if any
 290   current_offset += preserve_SP_size();   // skip mov rbp, rsp
 291   current_offset += 1;      // skip call opcode byte
 292   return round_to(current_offset, alignment_required()) - current_offset;
 293 }
 294 
 295 // The address of the call instruction needs to be 4-byte aligned to
 296 // ensure that it does not span a cache line so that it can be patched.
 297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
 298   current_offset += pre_call_resets_size();  // skip fldcw, if any
 299   current_offset += 5;      // skip MOV instruction
 300   current_offset += 1;      // skip call opcode byte
 301   return round_to(current_offset, alignment_required()) - current_offset;
 302 }
 303 
 304 // EMIT_RM()
 305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 306   unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
 307   cbuf.insts()->emit_int8(c);
 308 }
 309 
 310 // EMIT_CC()
 311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
 312   unsigned char c = (unsigned char)( f1 | f2 );
 313   cbuf.insts()->emit_int8(c);
 314 }
 315 
 316 // EMIT_OPCODE()
 317 void emit_opcode(CodeBuffer &cbuf, int code) {
 318   cbuf.insts()->emit_int8((unsigned char) code);
 319 }
 320 
 321 // EMIT_OPCODE() w/ relocation information
 322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
 323   cbuf.relocate(cbuf.insts_mark() + offset, reloc);
 324   emit_opcode(cbuf, code);
 325 }
 326 
 327 // EMIT_D8()
 328 void emit_d8(CodeBuffer &cbuf, int d8) {
 329   cbuf.insts()->emit_int8((unsigned char) d8);
 330 }
 331 
 332 // EMIT_D16()
 333 void emit_d16(CodeBuffer &cbuf, int d16) {
 334   cbuf.insts()->emit_int16(d16);
 335 }
 336 
 337 // EMIT_D32()
 338 void emit_d32(CodeBuffer &cbuf, int d32) {
 339   cbuf.insts()->emit_int32(d32);
 340 }
 341 
 342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
 343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
 344         int format) {
 345   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 346   cbuf.insts()->emit_int32(d32);
 347 }
 348 
 349 // emit 32 bit value and construct relocation entry from RelocationHolder
 350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
 351         int format) {
 352 #ifdef ASSERT
 353   if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
 354     assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
 355   }
 356 #endif
 357   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 358   cbuf.insts()->emit_int32(d32);
 359 }
 360 
 361 // Access stack slot for load or store
 362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
 363   emit_opcode( cbuf, opcode );               // (e.g., FILD   [ESP+src])
 364   if( -128 <= disp && disp <= 127 ) {
 365     emit_rm( cbuf, 0x01, rm_field, ESP_enc );  // R/M byte
 366     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte
 367     emit_d8 (cbuf, disp);     // Displacement  // R/M byte
 368   } else {
 369     emit_rm( cbuf, 0x02, rm_field, ESP_enc );  // R/M byte
 370     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte
 371     emit_d32(cbuf, disp);     // Displacement  // R/M byte
 372   }
 373 }
 374 
 375    // rRegI ereg, memory mem) %{    // emit_reg_mem
 376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
 377   // There is no index & no scale, use form without SIB byte
 378   if ((index == 0x4) &&
 379       (scale == 0) && (base != ESP_enc)) {
 380     // If no displacement, mode is 0x0; unless base is [EBP]
 381     if ( (displace == 0) && (base != EBP_enc) ) {
 382       emit_rm(cbuf, 0x0, reg_encoding, base);
 383     }
 384     else {                    // If 8-bit displacement, mode 0x1
 385       if ((displace >= -128) && (displace <= 127)
 386           && (disp_reloc == relocInfo::none) ) {
 387         emit_rm(cbuf, 0x1, reg_encoding, base);
 388         emit_d8(cbuf, displace);
 389       }
 390       else {                  // If 32-bit displacement
 391         if (base == -1) { // Special flag for absolute address
 392           emit_rm(cbuf, 0x0, reg_encoding, 0x5);
 393           // (manual lies; no SIB needed here)
 394           if ( disp_reloc != relocInfo::none ) {
 395             emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 396           } else {
 397             emit_d32      (cbuf, displace);
 398           }
 399         }
 400         else {                // Normal base + offset
 401           emit_rm(cbuf, 0x2, reg_encoding, base);
 402           if ( disp_reloc != relocInfo::none ) {
 403             emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 404           } else {
 405             emit_d32      (cbuf, displace);
 406           }
 407         }
 408       }
 409     }
 410   }
 411   else {                      // Else, encode with the SIB byte
 412     // If no displacement, mode is 0x0; unless base is [EBP]
 413     if (displace == 0 && (base != EBP_enc)) {  // If no displacement
 414       emit_rm(cbuf, 0x0, reg_encoding, 0x4);
 415       emit_rm(cbuf, scale, index, base);
 416     }
 417     else {                    // If 8-bit displacement, mode 0x1
 418       if ((displace >= -128) && (displace <= 127)
 419           && (disp_reloc == relocInfo::none) ) {
 420         emit_rm(cbuf, 0x1, reg_encoding, 0x4);
 421         emit_rm(cbuf, scale, index, base);
 422         emit_d8(cbuf, displace);
 423       }
 424       else {                  // If 32-bit displacement
 425         if (base == 0x04 ) {
 426           emit_rm(cbuf, 0x2, reg_encoding, 0x4);
 427           emit_rm(cbuf, scale, index, 0x04);
 428         } else {
 429           emit_rm(cbuf, 0x2, reg_encoding, 0x4);
 430           emit_rm(cbuf, scale, index, base);
 431         }
 432         if ( disp_reloc != relocInfo::none ) {
 433           emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 434         } else {
 435           emit_d32      (cbuf, displace);
 436         }
 437       }
 438     }
 439   }
 440 }
 441 
 442 
 443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
 444   if( dst_encoding == src_encoding ) {
 445     // reg-reg copy, use an empty encoding
 446   } else {
 447     emit_opcode( cbuf, 0x8B );
 448     emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
 449   }
 450 }
 451 
 452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
 453   Label exit;
 454   __ jccb(Assembler::noParity, exit);
 455   __ pushf();
 456   //
 457   // comiss/ucomiss instructions set ZF,PF,CF flags and
 458   // zero OF,AF,SF for NaN values.
 459   // Fixup flags by zeroing ZF,PF so that compare of NaN
 460   // values returns 'less than' result (CF is set).
 461   // Leave the rest of flags unchanged.
 462   //
 463   //    7 6 5 4 3 2 1 0
 464   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
 465   //    0 0 1 0 1 0 1 1   (0x2B)
 466   //
 467   __ andl(Address(rsp, 0), 0xffffff2b);
 468   __ popf();
 469   __ bind(exit);
 470 }
 471 
 472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
 473   Label done;
 474   __ movl(dst, -1);
 475   __ jcc(Assembler::parity, done);
 476   __ jcc(Assembler::below, done);
 477   __ setb(Assembler::notEqual, dst);
 478   __ movzbl(dst, dst);
 479   __ bind(done);
 480 }
 481 
 482 
 483 //=============================================================================
 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 485 
 486 int Compile::ConstantTable::calculate_table_base_offset() const {
 487   return 0;  // absolute addressing, no offset
 488 }
 489 
 490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 491   // Empty encoding
 492 }
 493 
 494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 495   return 0;
 496 }
 497 
 498 #ifndef PRODUCT
 499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 500   st->print("# MachConstantBaseNode (empty encoding)");
 501 }
 502 #endif
 503 
 504 
 505 //=============================================================================
 506 #ifndef PRODUCT
 507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 508   Compile* C = ra_->C;
 509 
 510   int framesize = C->frame_slots() << LogBytesPerInt;
 511   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 512   // Remove wordSize for return addr which is already pushed.
 513   framesize -= wordSize;
 514 
 515   if (C->need_stack_bang(framesize)) {
 516     framesize -= wordSize;
 517     st->print("# stack bang");
 518     st->print("\n\t");
 519     st->print("PUSH   EBP\t# Save EBP");
 520     if (framesize) {
 521       st->print("\n\t");
 522       st->print("SUB    ESP, #%d\t# Create frame",framesize);
 523     }
 524   } else {
 525     st->print("SUB    ESP, #%d\t# Create frame",framesize);
 526     st->print("\n\t");
 527     framesize -= wordSize;
 528     st->print("MOV    [ESP + #%d], EBP\t# Save EBP",framesize);
 529   }
 530 
 531   if (VerifyStackAtCalls) {
 532     st->print("\n\t");
 533     framesize -= wordSize;
 534     st->print("MOV    [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
 535   }
 536 
 537   if( C->in_24_bit_fp_mode() ) {
 538     st->print("\n\t");
 539     st->print("FLDCW  \t# load 24 bit fpu control word");
 540   }
 541   if (UseSSE >= 2 && VerifyFPU) {
 542     st->print("\n\t");
 543     st->print("# verify FPU stack (must be clean on entry)");
 544   }
 545 
 546 #ifdef ASSERT
 547   if (VerifyStackAtCalls) {
 548     st->print("\n\t");
 549     st->print("# stack alignment check");
 550   }
 551 #endif
 552   st->cr();
 553 }
 554 #endif
 555 
 556 
 557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 558   Compile* C = ra_->C;
 559   MacroAssembler _masm(&cbuf);
 560 
 561   int framesize = C->frame_slots() << LogBytesPerInt;
 562 
 563   __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
 564 
 565   C->set_frame_complete(cbuf.insts_size());
 566 
 567   if (C->has_mach_constant_base_node()) {
 568     // NOTE: We set the table base offset here because users might be
 569     // emitted before MachConstantBaseNode.
 570     Compile::ConstantTable& constant_table = C->constant_table();
 571     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 572   }
 573 }
 574 
 575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
 576   return MachNode::size(ra_); // too many variables; just compute it the hard way
 577 }
 578 
 579 int MachPrologNode::reloc() const {
 580   return 0; // a large enough number
 581 }
 582 
 583 //=============================================================================
 584 #ifndef PRODUCT
 585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
 586   Compile *C = ra_->C;
 587   int framesize = C->frame_slots() << LogBytesPerInt;
 588   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 589   // Remove two words for return addr and rbp,
 590   framesize -= 2*wordSize;
 591 
 592   if (C->max_vector_size() > 16) {
 593     st->print("VZEROUPPER");
 594     st->cr(); st->print("\t");
 595   }
 596   if (C->in_24_bit_fp_mode()) {
 597     st->print("FLDCW  standard control word");
 598     st->cr(); st->print("\t");
 599   }
 600   if (framesize) {
 601     st->print("ADD    ESP,%d\t# Destroy frame",framesize);
 602     st->cr(); st->print("\t");
 603   }
 604   st->print_cr("POPL   EBP"); st->print("\t");
 605   if (do_polling() && C->is_method_compilation()) {
 606     st->print("TEST   PollPage,EAX\t! Poll Safepoint");
 607     st->cr(); st->print("\t");
 608   }
 609 }
 610 #endif
 611 
 612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 613   Compile *C = ra_->C;
 614 
 615   if (C->max_vector_size() > 16) {
 616     // Clear upper bits of YMM registers when current compiled code uses
 617     // wide vectors to avoid AVX <-> SSE transition penalty during call.
 618     MacroAssembler masm(&cbuf);
 619     masm.vzeroupper();
 620   }
 621   // If method set FPU control word, restore to standard control word
 622   if (C->in_24_bit_fp_mode()) {
 623     MacroAssembler masm(&cbuf);
 624     masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 625   }
 626 
 627   int framesize = C->frame_slots() << LogBytesPerInt;
 628   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 629   // Remove two words for return addr and rbp,
 630   framesize -= 2*wordSize;
 631 
 632   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
 633 
 634   if (framesize >= 128) {
 635     emit_opcode(cbuf, 0x81); // add  SP, #framesize
 636     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
 637     emit_d32(cbuf, framesize);
 638   } else if (framesize) {
 639     emit_opcode(cbuf, 0x83); // add  SP, #framesize
 640     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
 641     emit_d8(cbuf, framesize);
 642   }
 643 
 644   emit_opcode(cbuf, 0x58 | EBP_enc);
 645 
 646   if (do_polling() && C->is_method_compilation()) {
 647     cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
 648     emit_opcode(cbuf,0x85);
 649     emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
 650     emit_d32(cbuf, (intptr_t)os::get_polling_page());
 651   }
 652 }
 653 
 654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 655   Compile *C = ra_->C;
 656   // If method set FPU control word, restore to standard control word
 657   int size = C->in_24_bit_fp_mode() ? 6 : 0;
 658   if (C->max_vector_size() > 16) size += 3; // vzeroupper
 659   if (do_polling() && C->is_method_compilation()) size += 6;
 660 
 661   int framesize = C->frame_slots() << LogBytesPerInt;
 662   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 663   // Remove two words for return addr and rbp,
 664   framesize -= 2*wordSize;
 665 
 666   size++; // popl rbp,
 667 
 668   if (framesize >= 128) {
 669     size += 6;
 670   } else {
 671     size += framesize ? 3 : 0;
 672   }
 673   return size;
 674 }
 675 
 676 int MachEpilogNode::reloc() const {
 677   return 0; // a large enough number
 678 }
 679 
 680 const Pipeline * MachEpilogNode::pipeline() const {
 681   return MachNode::pipeline_class();
 682 }
 683 
 684 int MachEpilogNode::safepoint_offset() const { return 0; }
 685 
 686 //=============================================================================
 687 
 688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
 689 static enum RC rc_class( OptoReg::Name reg ) {
 690 
 691   if( !OptoReg::is_valid(reg)  ) return rc_bad;
 692   if (OptoReg::is_stack(reg)) return rc_stack;
 693 
 694   VMReg r = OptoReg::as_VMReg(reg);
 695   if (r->is_Register()) return rc_int;
 696   if (r->is_FloatRegister()) {
 697     assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
 698     return rc_float;
 699   }
 700   assert(r->is_XMMRegister(), "must be");
 701   return rc_xmm;
 702 }
 703 
 704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
 705                         int opcode, const char *op_str, int size, outputStream* st ) {
 706   if( cbuf ) {
 707     emit_opcode  (*cbuf, opcode );
 708     encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
 709 #ifndef PRODUCT
 710   } else if( !do_size ) {
 711     if( size != 0 ) st->print("\n\t");
 712     if( opcode == 0x8B || opcode == 0x89 ) { // MOV
 713       if( is_load ) st->print("%s   %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
 714       else          st->print("%s   [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
 715     } else { // FLD, FST, PUSH, POP
 716       st->print("%s [ESP + #%d]",op_str,offset);
 717     }
 718 #endif
 719   }
 720   int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
 721   return size+3+offset_size;
 722 }
 723 
 724 // Helper for XMM registers.  Extra opcode bits, limited syntax.
 725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
 726                          int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
 727   if (cbuf) {
 728     MacroAssembler _masm(cbuf);
 729     if (reg_lo+1 == reg_hi) { // double move?
 730       if (is_load) {
 731         __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
 732       } else {
 733         __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
 734       }
 735     } else {
 736       if (is_load) {
 737         __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
 738       } else {
 739         __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
 740       }
 741     }
 742 #ifndef PRODUCT
 743   } else if (!do_size) {
 744     if (size != 0) st->print("\n\t");
 745     if (reg_lo+1 == reg_hi) { // double move?
 746       if (is_load) st->print("%s %s,[ESP + #%d]",
 747                               UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
 748                               Matcher::regName[reg_lo], offset);
 749       else         st->print("MOVSD  [ESP + #%d],%s",
 750                               offset, Matcher::regName[reg_lo]);
 751     } else {
 752       if (is_load) st->print("MOVSS  %s,[ESP + #%d]",
 753                               Matcher::regName[reg_lo], offset);
 754       else         st->print("MOVSS  [ESP + #%d],%s",
 755                               offset, Matcher::regName[reg_lo]);
 756     }
 757 #endif
 758   }
 759   int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
 760   // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
 761   return size+5+offset_size;
 762 }
 763 
 764 
 765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 766                             int src_hi, int dst_hi, int size, outputStream* st ) {
 767   if (cbuf) {
 768     MacroAssembler _masm(cbuf);
 769     if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
 770       __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 771                 as_XMMRegister(Matcher::_regEncode[src_lo]));
 772     } else {
 773       __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 774                 as_XMMRegister(Matcher::_regEncode[src_lo]));
 775     }
 776 #ifndef PRODUCT
 777   } else if (!do_size) {
 778     if (size != 0) st->print("\n\t");
 779     if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
 780       if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
 781         st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 782       } else {
 783         st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 784       }
 785     } else {
 786       if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
 787         st->print("MOVSD  %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 788       } else {
 789         st->print("MOVSS  %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 790       }
 791     }
 792 #endif
 793   }
 794   // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
 795   // Only MOVAPS SSE prefix uses 1 byte.
 796   int sz = 4;
 797   if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
 798       UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
 799   return size + sz;
 800 }
 801 
 802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 803                             int src_hi, int dst_hi, int size, outputStream* st ) {
 804   // 32-bit
 805   if (cbuf) {
 806     MacroAssembler _masm(cbuf);
 807     __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 808              as_Register(Matcher::_regEncode[src_lo]));
 809 #ifndef PRODUCT
 810   } else if (!do_size) {
 811     st->print("movdl   %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 812 #endif
 813   }
 814   return 4;
 815 }
 816 
 817 
 818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 819                                  int src_hi, int dst_hi, int size, outputStream* st ) {
 820   // 32-bit
 821   if (cbuf) {
 822     MacroAssembler _masm(cbuf);
 823     __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
 824              as_XMMRegister(Matcher::_regEncode[src_lo]));
 825 #ifndef PRODUCT
 826   } else if (!do_size) {
 827     st->print("movdl   %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 828 #endif
 829   }
 830   return 4;
 831 }
 832 
 833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
 834   if( cbuf ) {
 835     emit_opcode(*cbuf, 0x8B );
 836     emit_rm    (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
 837 #ifndef PRODUCT
 838   } else if( !do_size ) {
 839     if( size != 0 ) st->print("\n\t");
 840     st->print("MOV    %s,%s",Matcher::regName[dst],Matcher::regName[src]);
 841 #endif
 842   }
 843   return size+2;
 844 }
 845 
 846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
 847                                  int offset, int size, outputStream* st ) {
 848   if( src_lo != FPR1L_num ) {      // Move value to top of FP stack, if not already there
 849     if( cbuf ) {
 850       emit_opcode( *cbuf, 0xD9 );  // FLD (i.e., push it)
 851       emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
 852 #ifndef PRODUCT
 853     } else if( !do_size ) {
 854       if( size != 0 ) st->print("\n\t");
 855       st->print("FLD    %s",Matcher::regName[src_lo]);
 856 #endif
 857     }
 858     size += 2;
 859   }
 860 
 861   int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
 862   const char *op_str;
 863   int op;
 864   if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
 865     op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
 866     op = 0xDD;
 867   } else {                   // 32-bit store
 868     op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
 869     op = 0xD9;
 870     assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
 871   }
 872 
 873   return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
 874 }
 875 
 876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
 877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 878                           int src_hi, int dst_hi, uint ireg, outputStream* st);
 879 
 880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
 881                             int stack_offset, int reg, uint ireg, outputStream* st);
 882 
 883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
 884                                      int dst_offset, uint ireg, outputStream* st) {
 885   int calc_size = 0;
 886   int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
 887   int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
 888   switch (ireg) {
 889   case Op_VecS:
 890     calc_size = 3+src_offset_size + 3+dst_offset_size;
 891     break;
 892   case Op_VecD:
 893     calc_size = 3+src_offset_size + 3+dst_offset_size;
 894     src_offset += 4;
 895     dst_offset += 4;
 896     src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
 897     dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
 898     calc_size += 3+src_offset_size + 3+dst_offset_size;
 899     break;
 900   case Op_VecX:
 901     calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
 902     break;
 903   case Op_VecY:
 904     calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
 905     break;
 906   default:
 907     ShouldNotReachHere();
 908   }
 909   if (cbuf) {
 910     MacroAssembler _masm(cbuf);
 911     int offset = __ offset();
 912     switch (ireg) {
 913     case Op_VecS:
 914       __ pushl(Address(rsp, src_offset));
 915       __ popl (Address(rsp, dst_offset));
 916       break;
 917     case Op_VecD:
 918       __ pushl(Address(rsp, src_offset));
 919       __ popl (Address(rsp, dst_offset));
 920       __ pushl(Address(rsp, src_offset+4));
 921       __ popl (Address(rsp, dst_offset+4));
 922       break;
 923     case Op_VecX:
 924       __ movdqu(Address(rsp, -16), xmm0);
 925       __ movdqu(xmm0, Address(rsp, src_offset));
 926       __ movdqu(Address(rsp, dst_offset), xmm0);
 927       __ movdqu(xmm0, Address(rsp, -16));
 928       break;
 929     case Op_VecY:
 930       __ vmovdqu(Address(rsp, -32), xmm0);
 931       __ vmovdqu(xmm0, Address(rsp, src_offset));
 932       __ vmovdqu(Address(rsp, dst_offset), xmm0);
 933       __ vmovdqu(xmm0, Address(rsp, -32));
 934       break;
 935     default:
 936       ShouldNotReachHere();
 937     }
 938     int size = __ offset() - offset;
 939     assert(size == calc_size, "incorrect size calculattion");
 940     return size;
 941 #ifndef PRODUCT
 942   } else if (!do_size) {
 943     switch (ireg) {
 944     case Op_VecS:
 945       st->print("pushl   [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
 946                 "popl    [rsp + #%d]",
 947                 src_offset, dst_offset);
 948       break;
 949     case Op_VecD:
 950       st->print("pushl   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 951                 "popq    [rsp + #%d]\n\t"
 952                 "pushl   [rsp + #%d]\n\t"
 953                 "popq    [rsp + #%d]",
 954                 src_offset, dst_offset, src_offset+4, dst_offset+4);
 955       break;
 956      case Op_VecX:
 957       st->print("movdqu  [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
 958                 "movdqu  xmm0, [rsp + #%d]\n\t"
 959                 "movdqu  [rsp + #%d], xmm0\n\t"
 960                 "movdqu  xmm0, [rsp - #16]",
 961                 src_offset, dst_offset);
 962       break;
 963     case Op_VecY:
 964       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
 965                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 966                 "vmovdqu [rsp + #%d], xmm0\n\t"
 967                 "vmovdqu xmm0, [rsp - #32]",
 968                 src_offset, dst_offset);
 969       break;
 970     default:
 971       ShouldNotReachHere();
 972     }
 973 #endif
 974   }
 975   return calc_size;
 976 }
 977 
 978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
 979   // Get registers to move
 980   OptoReg::Name src_second = ra_->get_reg_second(in(1));
 981   OptoReg::Name src_first = ra_->get_reg_first(in(1));
 982   OptoReg::Name dst_second = ra_->get_reg_second(this );
 983   OptoReg::Name dst_first = ra_->get_reg_first(this );
 984 
 985   enum RC src_second_rc = rc_class(src_second);
 986   enum RC src_first_rc = rc_class(src_first);
 987   enum RC dst_second_rc = rc_class(dst_second);
 988   enum RC dst_first_rc = rc_class(dst_first);
 989 
 990   assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
 991 
 992   // Generate spill code!
 993   int size = 0;
 994 
 995   if( src_first == dst_first && src_second == dst_second )
 996     return size;            // Self copy, no move
 997 
 998   if (bottom_type()->isa_vect() != NULL) {
 999     uint ireg = ideal_reg();
1000     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001     assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004       // mem -> mem
1005       int src_offset = ra_->reg2offset(src_first);
1006       int dst_offset = ra_->reg2offset(dst_first);
1007       return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008     } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009       return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010     } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011       int stack_offset = ra_->reg2offset(dst_first);
1012       return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013     } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014       int stack_offset = ra_->reg2offset(src_first);
1015       return vec_spill_helper(cbuf, do_size, true,  stack_offset, dst_first, ireg, st);
1016     } else {
1017       ShouldNotReachHere();
1018     }
1019   }
1020 
1021   // --------------------------------------
1022   // Check for mem-mem move.  push/pop to move.
1023   if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024     if( src_second == dst_first ) { // overlapping stack copy ranges
1025       assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026       size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH  ",size, st);
1027       size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP   ",size, st);
1028       src_second_rc = dst_second_rc = rc_bad;  // flag as already moved the second bits
1029     }
1030     // move low bits
1031     size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH  ",size, st);
1032     size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP   ",size, st);
1033     if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034       size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH  ",size, st);
1035       size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP   ",size, st);
1036     }
1037     return size;
1038   }
1039 
1040   // --------------------------------------
1041   // Check for integer reg-reg copy
1042   if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043     size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1044 
1045   // Check for integer store
1046   if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047     size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1048 
1049   // Check for integer load
1050   if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051     size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1052 
1053   // Check for integer reg-xmm reg copy
1054   if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056             "no 64 bit integer-float reg moves" );
1057     return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058   }
1059   // --------------------------------------
1060   // Check for float reg-reg copy
1061   if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063             (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064     if( cbuf ) {
1065 
1066       // Note the mucking with the register encode to compensate for the 0/1
1067       // indexing issue mentioned in a comment in the reg_def sections
1068       // for FPR registers many lines above here.
1069 
1070       if( src_first != FPR1L_num ) {
1071         emit_opcode  (*cbuf, 0xD9 );           // FLD    ST(i)
1072         emit_d8      (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073         emit_opcode  (*cbuf, 0xDD );           // FSTP   ST(i)
1074         emit_d8      (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075      } else {
1076         emit_opcode  (*cbuf, 0xDD );           // FST    ST(i)
1077         emit_d8      (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078      }
1079 #ifndef PRODUCT
1080     } else if( !do_size ) {
1081       if( size != 0 ) st->print("\n\t");
1082       if( src_first != FPR1L_num ) st->print("FLD    %s\n\tFSTP   %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083       else                      st->print(             "FST    %s",                            Matcher::regName[dst_first]);
1084 #endif
1085     }
1086     return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087   }
1088 
1089   // Check for float store
1090   if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091     return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092   }
1093 
1094   // Check for float load
1095   if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096     int offset = ra_->reg2offset(src_first);
1097     const char *op_str;
1098     int op;
1099     if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100       op_str = "FLD_D";
1101       op = 0xDD;
1102     } else {                   // 32-bit load
1103       op_str = "FLD_S";
1104       op = 0xD9;
1105       assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106     }
1107     if( cbuf ) {
1108       emit_opcode  (*cbuf, op );
1109       encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110       emit_opcode  (*cbuf, 0xDD );           // FSTP   ST(i)
1111       emit_d8      (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113     } else if( !do_size ) {
1114       if( size != 0 ) st->print("\n\t");
1115       st->print("%s  ST,[ESP + #%d]\n\tFSTP   %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117     }
1118     int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119     return size + 3+offset_size+2;
1120   }
1121 
1122   // Check for xmm reg-reg copy
1123   if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125             (src_first+1 == src_second && dst_first+1 == dst_second),
1126             "no non-adjacent float-moves" );
1127     return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128   }
1129 
1130   // Check for xmm reg-integer reg copy
1131   if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133             "no 64 bit float-integer reg moves" );
1134     return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135   }
1136 
1137   // Check for xmm store
1138   if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139     return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140   }
1141 
1142   // Check for float xmm load
1143   if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144     return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145   }
1146 
1147   // Copy from float reg to xmm reg
1148   if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149     // copy to the top of stack from floating point reg
1150     // and use LEA to preserve flags
1151     if( cbuf ) {
1152       emit_opcode(*cbuf,0x8D);  // LEA  ESP,[ESP-8]
1153       emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154       emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155       emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157     } else if( !do_size ) {
1158       if( size != 0 ) st->print("\n\t");
1159       st->print("LEA    ESP,[ESP-8]");
1160 #endif
1161     }
1162     size += 4;
1163 
1164     size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1165 
1166     // Copy from the temp memory to the xmm reg.
1167     size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1168 
1169     if( cbuf ) {
1170       emit_opcode(*cbuf,0x8D);  // LEA  ESP,[ESP+8]
1171       emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172       emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173       emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175     } else if( !do_size ) {
1176       if( size != 0 ) st->print("\n\t");
1177       st->print("LEA    ESP,[ESP+8]");
1178 #endif
1179     }
1180     size += 4;
1181     return size;
1182   }
1183 
1184   assert( size > 0, "missed a case" );
1185 
1186   // --------------------------------------------------------------------
1187   // Check for second bits still needing moving.
1188   if( src_second == dst_second )
1189     return size;               // Self copy; no move
1190   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1191 
1192   // Check for second word int-int move
1193   if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194     return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1195 
1196   // Check for second word integer store
1197   if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198     return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1199 
1200   // Check for second word integer load
1201   if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202     return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1203 
1204 
1205   Unimplemented();
1206 }
1207 
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210   implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1213 
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215   implementation( &cbuf, ra_, false, NULL );
1216 }
1217 
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219   return implementation( NULL, ra_, true, NULL );
1220 }
1221 
1222 
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227   int reg = ra_->get_reg_first(this);
1228   st->print("LEA    %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1231 
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234   int reg = ra_->get_encode(this);
1235   if( offset >= 128 ) {
1236     emit_opcode(cbuf, 0x8D);      // LEA  reg,[SP+offset]
1237     emit_rm(cbuf, 0x2, reg, 0x04);
1238     emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239     emit_d32(cbuf, offset);
1240   }
1241   else {
1242     emit_opcode(cbuf, 0x8D);      // LEA  reg,[SP+offset]
1243     emit_rm(cbuf, 0x1, reg, 0x04);
1244     emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245     emit_d8(cbuf, offset);
1246   }
1247 }
1248 
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251   if( offset >= 128 ) {
1252     return 7;
1253   }
1254   else {
1255     return 4;
1256   }
1257 }
1258 
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262   st->print_cr(  "CMP    EAX,[ECX+4]\t# Inline cache check");
1263   st->print_cr("\tJNE    SharedRuntime::handle_ic_miss_stub");
1264   st->print_cr("\tNOP");
1265   st->print_cr("\tNOP");
1266   if( !OptoBreakpoint )
1267     st->print_cr("\tNOP");
1268 }
1269 #endif
1270 
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272   MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274   uint insts_size = cbuf.insts_size();
1275 #endif
1276   masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277   masm.jump_cc(Assembler::notEqual,
1278                RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279   /* WARNING these NOPs are critical so that verified entry point is properly
1280      aligned for patching by NativeJump::patch_verified_entry() */
1281   int nops_cnt = 2;
1282   if( !OptoBreakpoint ) // Leave space for int3
1283      nops_cnt += 1;
1284   masm.nop(nops_cnt);
1285 
1286   assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1288 
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290   return OptoBreakpoint ? 11 : 12;
1291 }
1292 
1293 
1294 //=============================================================================
1295 uint size_exception_handler() {
1296   // NativeCall instruction size is the same as NativeJump.
1297   // exception handler starts out as jump and can be patched to
1298   // a call be deoptimization.  (4932387)
1299   // Note that this value is also credited (in output.cpp) to
1300   // the size of the code section.
1301   return NativeJump::instruction_size;
1302 }
1303 
1304 // Emit exception handler code.  Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1307 
1308   // Note that the code buffer's insts_mark is always relative to insts.
1309   // That's why we must use the macroassembler to generate a handler.
1310   MacroAssembler _masm(&cbuf);
1311   address base =
1312   __ start_a_stub(size_exception_handler());
1313   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1314   int offset = __ offset();
1315   __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317   __ end_a_stub();
1318   return offset;
1319 }
1320 
1321 uint size_deopt_handler() {
1322   // NativeCall instruction size is the same as NativeJump.
1323   // exception handler starts out as jump and can be patched to
1324   // a call be deoptimization.  (4932387)
1325   // Note that this value is also credited (in output.cpp) to
1326   // the size of the code section.
1327   return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1329 
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1332 
1333   // Note that the code buffer's insts_mark is always relative to insts.
1334   // That's why we must use the macroassembler to generate a handler.
1335   MacroAssembler _masm(&cbuf);
1336   address base =
1337   __ start_a_stub(size_exception_handler());
1338   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1339   int offset = __ offset();
1340   InternalAddress here(__ pc());
1341   __ pushptr(here.addr());
1342 
1343   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345   __ end_a_stub();
1346   return offset;
1347 }
1348 
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350   return regnum - 32; // The FP registers are in the second chunk
1351 }
1352 
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355   return true;
1356 }
1357 
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 //       this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363   // The passed offset is relative to address of the branch.
1364   // On 86 a branch displacement is calculated relative to address
1365   // of a next instruction.
1366   offset -= br_size;
1367 
1368   // the short version of jmpConUCF2 contains multiple branches,
1369   // making the reach slightly less
1370   if (rule == jmpConUCF2_rule)
1371     return (-126 <= offset && offset <= 125);
1372   return (-128 <= offset && offset <= 127);
1373 }
1374 
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377   return false;
1378 }
1379 
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1382 
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1385 
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1388 
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391 
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers?  True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1396 
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1400 
1401 bool Matcher::narrow_oop_use_complex_address() {
1402   ShouldNotCallThis();
1403   return true;
1404 }
1405 
1406 bool Matcher::narrow_klass_use_complex_address() {
1407   ShouldNotCallThis();
1408   return true;
1409 }
1410 
1411 
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers.  Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1417 
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed.  Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece.  Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1423 
1424 
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426   // Get the memory operand from the node
1427   uint numopnds = node->num_opnds();        // Virtual call for number of operands
1428   uint skipped  = node->oper_input_base();  // Sum of leaves skipped so far
1429   assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430   uint opcnt     = 1;                 // First operand
1431   uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432   while( idx >= skipped+num_edges ) {
1433     skipped += num_edges;
1434     opcnt++;                          // Bump operand count
1435     assert( opcnt < numopnds, "Accessing non-existent operand" );
1436     num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437   }
1438 
1439   MachOper *memory = node->_opnds[opcnt];
1440   MachOper *new_memory = NULL;
1441   switch (memory->opcode()) {
1442   case DIRECT:
1443   case INDOFFSET32X:
1444     // No transformation necessary.
1445     return;
1446   case INDIRECT:
1447     new_memory = new (C) indirect_win95_safeOper( );
1448     break;
1449   case INDOFFSET8:
1450     new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451     break;
1452   case INDOFFSET32:
1453     new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454     break;
1455   case INDINDEXOFFSET:
1456     new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457     break;
1458   case INDINDEXSCALE:
1459     new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460     break;
1461   case INDINDEXSCALEOFFSET:
1462     new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463     break;
1464   case LOAD_LONG_INDIRECT:
1465   case LOAD_LONG_INDOFFSET32:
1466     // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467     return;
1468   default:
1469     assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470     return;
1471   }
1472   node->_opnds[opcnt] = new_memory;
1473 }
1474 
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1478 
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1482 
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1485 
1486 // Return whether or not this register is ever used as an argument.  This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491   if(  reg == ECX_num   || reg == EDX_num   ) return true;
1492   if( (reg == XMM0_num  || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493   if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494   return false;
1495 }
1496 
1497 bool Matcher::is_spillable_arg( int reg ) {
1498   return can_be_java_arg(reg);
1499 }
1500 
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502   // Use hardware integer DIV instruction when
1503   // it is faster than a code which use multiply.
1504   // Only when constant divisor fits into 32 bit
1505   // (min_jint is excluded to get only correct
1506   // positive 32 bit values from negative).
1507   return VM_Version::has_fast_idiv() &&
1508          (divisor == (int)divisor && divisor != min_jint);
1509 }
1510 
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513   return EAX_REG_mask();
1514 }
1515 
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518   return EDX_REG_mask();
1519 }
1520 
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523   ShouldNotReachHere();
1524   return RegMask();
1525 }
1526 
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529   ShouldNotReachHere();
1530   return RegMask();
1531 }
1532 
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534   return EBP_REG_mask();
1535 }
1536 
1537 // Returns true if the high 32 bits of the value is known to be zero.
1538 bool is_operand_hi32_zero(Node* n) {
1539   int opc = n->Opcode();
1540   if (opc == Op_AndL) {
1541     Node* o2 = n->in(2);
1542     if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1543       return true;
1544     }
1545   }
1546   if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1547     return true;
1548   }
1549   return false;
1550 }
1551 
1552 %}
1553 
1554 //----------ENCODING BLOCK-----------------------------------------------------
1555 // This block specifies the encoding classes used by the compiler to output
1556 // byte streams.  Encoding classes generate functions which are called by
1557 // Machine Instruction Nodes in order to generate the bit encoding of the
1558 // instruction.  Operands specify their base encoding interface with the
1559 // interface keyword.  There are currently supported four interfaces,
1560 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
1561 // operand to generate a function which returns its register number when
1562 // queried.   CONST_INTER causes an operand to generate a function which
1563 // returns the value of the constant when queried.  MEMORY_INTER causes an
1564 // operand to generate four functions which return the Base Register, the
1565 // Index Register, the Scale Value, and the Offset Value of the operand when
1566 // queried.  COND_INTER causes an operand to generate six functions which
1567 // return the encoding code (ie - encoding bits for the instruction)
1568 // associated with each basic boolean condition for a conditional instruction.
1569 // Instructions specify two basic values for encoding.  They use the
1570 // ins_encode keyword to specify their encoding class (which must be one of
1571 // the class names specified in the encoding block), and they use the
1572 // opcode keyword to specify, in order, their primary, secondary, and
1573 // tertiary opcode.  Only the opcode sections which a particular instruction
1574 // needs for encoding need to be specified.
1575 encode %{
1576   // Build emit functions for each basic byte or larger field in the intel
1577   // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1578   // code in the enc_class source block.  Emit functions will live in the
1579   // main source block for now.  In future, we can generalize this by
1580   // adding a syntax that specifies the sizes of fields in an order,
1581   // so that the adlc can build the emit functions automagically
1582 
1583   // Emit primary opcode
1584   enc_class OpcP %{
1585     emit_opcode(cbuf, $primary);
1586   %}
1587 
1588   // Emit secondary opcode
1589   enc_class OpcS %{
1590     emit_opcode(cbuf, $secondary);
1591   %}
1592 
1593   // Emit opcode directly
1594   enc_class Opcode(immI d8) %{
1595     emit_opcode(cbuf, $d8$$constant);
1596   %}
1597 
1598   enc_class SizePrefix %{
1599     emit_opcode(cbuf,0x66);
1600   %}
1601 
1602   enc_class RegReg (rRegI dst, rRegI src) %{    // RegReg(Many)
1603     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1604   %}
1605 
1606   enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{    // OpcRegReg(Many)
1607     emit_opcode(cbuf,$opcode$$constant);
1608     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1609   %}
1610 
1611   enc_class mov_r32_imm0( rRegI dst ) %{
1612     emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd   -- MOV r32  ,imm32
1613     emit_d32   ( cbuf, 0x0  );             //                         imm32==0x0
1614   %}
1615 
1616   enc_class cdq_enc %{
1617     // Full implementation of Java idiv and irem; checks for
1618     // special case as described in JVM spec., p.243 & p.271.
1619     //
1620     //         normal case                           special case
1621     //
1622     // input : rax,: dividend                         min_int
1623     //         reg: divisor                          -1
1624     //
1625     // output: rax,: quotient  (= rax, idiv reg)       min_int
1626     //         rdx: remainder (= rax, irem reg)       0
1627     //
1628     //  Code sequnce:
1629     //
1630     //  81 F8 00 00 00 80    cmp         rax,80000000h
1631     //  0F 85 0B 00 00 00    jne         normal_case
1632     //  33 D2                xor         rdx,edx
1633     //  83 F9 FF             cmp         rcx,0FFh
1634     //  0F 84 03 00 00 00    je          done
1635     //                  normal_case:
1636     //  99                   cdq
1637     //  F7 F9                idiv        rax,ecx
1638     //                  done:
1639     //
1640     emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1641     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1642     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80);                     // cmp rax,80000000h
1643     emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1644     emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1645     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);                     // jne normal_case
1646     emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2);                     // xor rdx,edx
1647     emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1648     emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1649     emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1650     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);                     // je done
1651     // normal_case:
1652     emit_opcode(cbuf,0x99);                                         // cdq
1653     // idiv (note: must be emitted by the user of this rule)
1654     // normal:
1655   %}
1656 
1657   // Dense encoding for older common ops
1658   enc_class Opc_plus(immI opcode, rRegI reg) %{
1659     emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1660   %}
1661 
1662 
1663   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1664   enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1665     // Check for 8-bit immediate, and set sign extend bit in opcode
1666     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1667       emit_opcode(cbuf, $primary | 0x02);
1668     }
1669     else {                          // If 32-bit immediate
1670       emit_opcode(cbuf, $primary);
1671     }
1672   %}
1673 
1674   enc_class OpcSErm (rRegI dst, immI imm) %{    // OpcSEr/m
1675     // Emit primary opcode and set sign-extend bit
1676     // Check for 8-bit immediate, and set sign extend bit in opcode
1677     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1678       emit_opcode(cbuf, $primary | 0x02);    }
1679     else {                          // If 32-bit immediate
1680       emit_opcode(cbuf, $primary);
1681     }
1682     // Emit r/m byte with secondary opcode, after primary opcode.
1683     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1684   %}
1685 
1686   enc_class Con8or32 (immI imm) %{    // Con8or32(storeImmI), 8 or 32 bits
1687     // Check for 8-bit immediate, and set sign extend bit in opcode
1688     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1689       $$$emit8$imm$$constant;
1690     }
1691     else {                          // If 32-bit immediate
1692       // Output immediate
1693       $$$emit32$imm$$constant;
1694     }
1695   %}
1696 
1697   enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1698     // Emit primary opcode and set sign-extend bit
1699     // Check for 8-bit immediate, and set sign extend bit in opcode
1700     int con = (int)$imm$$constant; // Throw away top bits
1701     emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1702     // Emit r/m byte with secondary opcode, after primary opcode.
1703     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1704     if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1705     else                               emit_d32(cbuf,con);
1706   %}
1707 
1708   enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1709     // Emit primary opcode and set sign-extend bit
1710     // Check for 8-bit immediate, and set sign extend bit in opcode
1711     int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1712     emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1713     // Emit r/m byte with tertiary opcode, after primary opcode.
1714     emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1715     if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1716     else                               emit_d32(cbuf,con);
1717   %}
1718 
1719   enc_class OpcSReg (rRegI dst) %{    // BSWAP
1720     emit_cc(cbuf, $secondary, $dst$$reg );
1721   %}
1722 
1723   enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1724     int destlo = $dst$$reg;
1725     int desthi = HIGH_FROM_LOW(destlo);
1726     // bswap lo
1727     emit_opcode(cbuf, 0x0F);
1728     emit_cc(cbuf, 0xC8, destlo);
1729     // bswap hi
1730     emit_opcode(cbuf, 0x0F);
1731     emit_cc(cbuf, 0xC8, desthi);
1732     // xchg lo and hi
1733     emit_opcode(cbuf, 0x87);
1734     emit_rm(cbuf, 0x3, destlo, desthi);
1735   %}
1736 
1737   enc_class RegOpc (rRegI div) %{    // IDIV, IMOD, JMP indirect, ...
1738     emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1739   %}
1740 
1741   enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1742     $$$emit8$primary;
1743     emit_cc(cbuf, $secondary, $cop$$cmpcode);
1744   %}
1745 
1746   enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1747     int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1748     emit_d8(cbuf, op >> 8 );
1749     emit_d8(cbuf, op & 255);
1750   %}
1751 
1752   // emulate a CMOV with a conditional branch around a MOV
1753   enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1754     // Invert sense of branch from sense of CMOV
1755     emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1756     emit_d8( cbuf, $brOffs$$constant );
1757   %}
1758 
1759   enc_class enc_PartialSubtypeCheck( ) %{
1760     Register Redi = as_Register(EDI_enc); // result register
1761     Register Reax = as_Register(EAX_enc); // super class
1762     Register Recx = as_Register(ECX_enc); // killed
1763     Register Resi = as_Register(ESI_enc); // sub class
1764     Label miss;
1765 
1766     MacroAssembler _masm(&cbuf);
1767     __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1768                                      NULL, &miss,
1769                                      /*set_cond_codes:*/ true);
1770     if ($primary) {
1771       __ xorptr(Redi, Redi);
1772     }
1773     __ bind(miss);
1774   %}
1775 
1776   enc_class FFree_Float_Stack_All %{    // Free_Float_Stack_All
1777     MacroAssembler masm(&cbuf);
1778     int start = masm.offset();
1779     if (UseSSE >= 2) {
1780       if (VerifyFPU) {
1781         masm.verify_FPU(0, "must be empty in SSE2+ mode");
1782       }
1783     } else {
1784       // External c_calling_convention expects the FPU stack to be 'clean'.
1785       // Compiled code leaves it dirty.  Do cleanup now.
1786       masm.empty_FPU_stack();
1787     }
1788     if (sizeof_FFree_Float_Stack_All == -1) {
1789       sizeof_FFree_Float_Stack_All = masm.offset() - start;
1790     } else {
1791       assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1792     }
1793   %}
1794 
1795   enc_class Verify_FPU_For_Leaf %{
1796     if( VerifyFPU ) {
1797       MacroAssembler masm(&cbuf);
1798       masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1799     }
1800   %}
1801 
1802   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1803     // This is the instruction starting address for relocation info.
1804     cbuf.set_insts_mark();
1805     $$$emit8$primary;
1806     // CALL directly to the runtime
1807     emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1808                 runtime_call_Relocation::spec(), RELOC_IMM32 );
1809 
1810     if (UseSSE >= 2) {
1811       MacroAssembler _masm(&cbuf);
1812       BasicType rt = tf()->return_type();
1813 
1814       if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1815         // A C runtime call where the return value is unused.  In SSE2+
1816         // mode the result needs to be removed from the FPU stack.  It's
1817         // likely that this function call could be removed by the
1818         // optimizer if the C function is a pure function.
1819         __ ffree(0);
1820       } else if (rt == T_FLOAT) {
1821         __ lea(rsp, Address(rsp, -4));
1822         __ fstp_s(Address(rsp, 0));
1823         __ movflt(xmm0, Address(rsp, 0));
1824         __ lea(rsp, Address(rsp,  4));
1825       } else if (rt == T_DOUBLE) {
1826         __ lea(rsp, Address(rsp, -8));
1827         __ fstp_d(Address(rsp, 0));
1828         __ movdbl(xmm0, Address(rsp, 0));
1829         __ lea(rsp, Address(rsp,  8));
1830       }
1831     }
1832   %}
1833 
1834 
1835   enc_class pre_call_resets %{
1836     // If method sets FPU control word restore it here
1837     debug_only(int off0 = cbuf.insts_size());
1838     if (ra_->C->in_24_bit_fp_mode()) {
1839       MacroAssembler _masm(&cbuf);
1840       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1841     }
1842     if (ra_->C->max_vector_size() > 16) {
1843       // Clear upper bits of YMM registers when current compiled code uses
1844       // wide vectors to avoid AVX <-> SSE transition penalty during call.
1845       MacroAssembler _masm(&cbuf);
1846       __ vzeroupper();
1847     }
1848     debug_only(int off1 = cbuf.insts_size());
1849     assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1850   %}
1851 
1852   enc_class post_call_FPU %{
1853     // If method sets FPU control word do it here also
1854     if (Compile::current()->in_24_bit_fp_mode()) {
1855       MacroAssembler masm(&cbuf);
1856       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1857     }
1858   %}
1859 
1860   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
1861     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
1862     // who we intended to call.
1863     cbuf.set_insts_mark();
1864     $$$emit8$primary;
1865     if (!_method) {
1866       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1867                      runtime_call_Relocation::spec(), RELOC_IMM32 );
1868     } else if (_optimized_virtual) {
1869       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1870                      opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1871     } else {
1872       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1873                      static_call_Relocation::spec(), RELOC_IMM32 );
1874     }
1875     if (_method) {  // Emit stub for static call.
1876       CompiledStaticCall::emit_to_interp_stub(cbuf);
1877     }
1878   %}
1879 
1880   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
1881     MacroAssembler _masm(&cbuf);
1882     __ ic_call((address)$meth$$method);
1883   %}
1884 
1885   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
1886     int disp = in_bytes(Method::from_compiled_offset());
1887     assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1888 
1889     // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1890     cbuf.set_insts_mark();
1891     $$$emit8$primary;
1892     emit_rm(cbuf, 0x01, $secondary, EAX_enc );  // R/M byte
1893     emit_d8(cbuf, disp);             // Displacement
1894 
1895   %}
1896 
1897 //   Following encoding is no longer used, but may be restored if calling
1898 //   convention changes significantly.
1899 //   Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1900 //
1901 //   enc_class Java_Interpreter_Call (label labl) %{    // JAVA INTERPRETER CALL
1902 //     // int ic_reg     = Matcher::inline_cache_reg();
1903 //     // int ic_encode  = Matcher::_regEncode[ic_reg];
1904 //     // int imo_reg    = Matcher::interpreter_method_oop_reg();
1905 //     // int imo_encode = Matcher::_regEncode[imo_reg];
1906 //
1907 //     // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1908 //     // // so we load it immediately before the call
1909 //     // emit_opcode(cbuf, 0x8B);                     // MOV    imo_reg,ic_reg  # method_oop
1910 //     // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1911 //
1912 //     // xor rbp,ebp
1913 //     emit_opcode(cbuf, 0x33);
1914 //     emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1915 //
1916 //     // CALL to interpreter.
1917 //     cbuf.set_insts_mark();
1918 //     $$$emit8$primary;
1919 //     emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1920 //                 runtime_call_Relocation::spec(), RELOC_IMM32 );
1921 //   %}
1922 
1923   enc_class RegOpcImm (rRegI dst, immI8 shift) %{    // SHL, SAR, SHR
1924     $$$emit8$primary;
1925     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1926     $$$emit8$shift$$constant;
1927   %}
1928 
1929   enc_class LdImmI (rRegI dst, immI src) %{    // Load Immediate
1930     // Load immediate does not have a zero or sign extended version
1931     // for 8-bit immediates
1932     emit_opcode(cbuf, 0xB8 + $dst$$reg);
1933     $$$emit32$src$$constant;
1934   %}
1935 
1936   enc_class LdImmP (rRegI dst, immI src) %{    // Load Immediate
1937     // Load immediate does not have a zero or sign extended version
1938     // for 8-bit immediates
1939     emit_opcode(cbuf, $primary + $dst$$reg);
1940     $$$emit32$src$$constant;
1941   %}
1942 
1943   enc_class LdImmL_Lo( eRegL dst, immL src) %{    // Load Immediate
1944     // Load immediate does not have a zero or sign extended version
1945     // for 8-bit immediates
1946     int dst_enc = $dst$$reg;
1947     int src_con = $src$$constant & 0x0FFFFFFFFL;
1948     if (src_con == 0) {
1949       // xor dst, dst
1950       emit_opcode(cbuf, 0x33);
1951       emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1952     } else {
1953       emit_opcode(cbuf, $primary + dst_enc);
1954       emit_d32(cbuf, src_con);
1955     }
1956   %}
1957 
1958   enc_class LdImmL_Hi( eRegL dst, immL src) %{    // Load Immediate
1959     // Load immediate does not have a zero or sign extended version
1960     // for 8-bit immediates
1961     int dst_enc = $dst$$reg + 2;
1962     int src_con = ((julong)($src$$constant)) >> 32;
1963     if (src_con == 0) {
1964       // xor dst, dst
1965       emit_opcode(cbuf, 0x33);
1966       emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1967     } else {
1968       emit_opcode(cbuf, $primary + dst_enc);
1969       emit_d32(cbuf, src_con);
1970     }
1971   %}
1972 
1973 
1974   // Encode a reg-reg copy.  If it is useless, then empty encoding.
1975   enc_class enc_Copy( rRegI dst, rRegI src ) %{
1976     encode_Copy( cbuf, $dst$$reg, $src$$reg );
1977   %}
1978 
1979   enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1980     encode_Copy( cbuf, $dst$$reg, $src$$reg );
1981   %}
1982 
1983   enc_class RegReg (rRegI dst, rRegI src) %{    // RegReg(Many)
1984     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985   %}
1986 
1987   enc_class RegReg_Lo(eRegL dst, eRegL src) %{    // RegReg(Many)
1988     $$$emit8$primary;
1989     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1990   %}
1991 
1992   enc_class RegReg_Hi(eRegL dst, eRegL src) %{    // RegReg(Many)
1993     $$$emit8$secondary;
1994     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1995   %}
1996 
1997   enc_class RegReg_Lo2(eRegL dst, eRegL src) %{    // RegReg(Many)
1998     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1999   %}
2000 
2001   enc_class RegReg_Hi2(eRegL dst, eRegL src) %{    // RegReg(Many)
2002     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003   %}
2004 
2005   enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2006     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2007   %}
2008 
2009   enc_class Con32 (immI src) %{    // Con32(storeImmI)
2010     // Output immediate
2011     $$$emit32$src$$constant;
2012   %}
2013 
2014   enc_class Con32FPR_as_bits(immFPR src) %{        // storeF_imm
2015     // Output Float immediate bits
2016     jfloat jf = $src$$constant;
2017     int    jf_as_bits = jint_cast( jf );
2018     emit_d32(cbuf, jf_as_bits);
2019   %}
2020 
2021   enc_class Con32F_as_bits(immF src) %{      // storeX_imm
2022     // Output Float immediate bits
2023     jfloat jf = $src$$constant;
2024     int    jf_as_bits = jint_cast( jf );
2025     emit_d32(cbuf, jf_as_bits);
2026   %}
2027 
2028   enc_class Con16 (immI src) %{    // Con16(storeImmI)
2029     // Output immediate
2030     $$$emit16$src$$constant;
2031   %}
2032 
2033   enc_class Con_d32(immI src) %{
2034     emit_d32(cbuf,$src$$constant);
2035   %}
2036 
2037   enc_class conmemref (eRegP t1) %{    // Con32(storeImmI)
2038     // Output immediate memory reference
2039     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2040     emit_d32(cbuf, 0x00);
2041   %}
2042 
2043   enc_class lock_prefix( ) %{
2044     if( os::is_MP() )
2045       emit_opcode(cbuf,0xF0);         // [Lock]
2046   %}
2047 
2048   // Cmp-xchg long value.
2049   // Note: we need to swap rbx, and rcx before and after the
2050   //       cmpxchg8 instruction because the instruction uses
2051   //       rcx as the high order word of the new value to store but
2052   //       our register encoding uses rbx,.
2053   enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2054 
2055     // XCHG  rbx,ecx
2056     emit_opcode(cbuf,0x87);
2057     emit_opcode(cbuf,0xD9);
2058     // [Lock]
2059     if( os::is_MP() )
2060       emit_opcode(cbuf,0xF0);
2061     // CMPXCHG8 [Eptr]
2062     emit_opcode(cbuf,0x0F);
2063     emit_opcode(cbuf,0xC7);
2064     emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2065     // XCHG  rbx,ecx
2066     emit_opcode(cbuf,0x87);
2067     emit_opcode(cbuf,0xD9);
2068   %}
2069 
2070   enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2071     // [Lock]
2072     if( os::is_MP() )
2073       emit_opcode(cbuf,0xF0);
2074 
2075     // CMPXCHG [Eptr]
2076     emit_opcode(cbuf,0x0F);
2077     emit_opcode(cbuf,0xB1);
2078     emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2079   %}
2080 
2081   enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2082     int res_encoding = $res$$reg;
2083 
2084     // MOV  res,0
2085     emit_opcode( cbuf, 0xB8 + res_encoding);
2086     emit_d32( cbuf, 0 );
2087     // JNE,s  fail
2088     emit_opcode(cbuf,0x75);
2089     emit_d8(cbuf, 5 );
2090     // MOV  res,1
2091     emit_opcode( cbuf, 0xB8 + res_encoding);
2092     emit_d32( cbuf, 1 );
2093     // fail:
2094   %}
2095 
2096   enc_class set_instruction_start( ) %{
2097     cbuf.set_insts_mark();            // Mark start of opcode for reloc info in mem operand
2098   %}
2099 
2100   enc_class RegMem (rRegI ereg, memory mem) %{    // emit_reg_mem
2101     int reg_encoding = $ereg$$reg;
2102     int base  = $mem$$base;
2103     int index = $mem$$index;
2104     int scale = $mem$$scale;
2105     int displace = $mem$$disp;
2106     relocInfo::relocType disp_reloc = $mem->disp_reloc();
2107     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2108   %}
2109 
2110   enc_class RegMem_Hi(eRegL ereg, memory mem) %{    // emit_reg_mem
2111     int reg_encoding = HIGH_FROM_LOW($ereg$$reg);  // Hi register of pair, computed from lo
2112     int base  = $mem$$base;
2113     int index = $mem$$index;
2114     int scale = $mem$$scale;
2115     int displace = $mem$$disp + 4;      // Offset is 4 further in memory
2116     assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2117     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2118   %}
2119 
2120   enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2121     int r1, r2;
2122     if( $tertiary == 0xA4 ) { r1 = $dst$$reg;  r2 = HIGH_FROM_LOW($dst$$reg); }
2123     else                    { r2 = $dst$$reg;  r1 = HIGH_FROM_LOW($dst$$reg); }
2124     emit_opcode(cbuf,0x0F);
2125     emit_opcode(cbuf,$tertiary);
2126     emit_rm(cbuf, 0x3, r1, r2);
2127     emit_d8(cbuf,$cnt$$constant);
2128     emit_d8(cbuf,$primary);
2129     emit_rm(cbuf, 0x3, $secondary, r1);
2130     emit_d8(cbuf,$cnt$$constant);
2131   %}
2132 
2133   enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2134     emit_opcode( cbuf, 0x8B ); // Move
2135     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2136     if( $cnt$$constant > 32 ) { // Shift, if not by zero
2137       emit_d8(cbuf,$primary);
2138       emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2139       emit_d8(cbuf,$cnt$$constant-32);
2140     }
2141     emit_d8(cbuf,$primary);
2142     emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2143     emit_d8(cbuf,31);
2144   %}
2145 
2146   enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2147     int r1, r2;
2148     if( $secondary == 0x5 ) { r1 = $dst$$reg;  r2 = HIGH_FROM_LOW($dst$$reg); }
2149     else                    { r2 = $dst$$reg;  r1 = HIGH_FROM_LOW($dst$$reg); }
2150 
2151     emit_opcode( cbuf, 0x8B ); // Move r1,r2
2152     emit_rm(cbuf, 0x3, r1, r2);
2153     if( $cnt$$constant > 32 ) { // Shift, if not by zero
2154       emit_opcode(cbuf,$primary);
2155       emit_rm(cbuf, 0x3, $secondary, r1);
2156       emit_d8(cbuf,$cnt$$constant-32);
2157     }
2158     emit_opcode(cbuf,0x33);  // XOR r2,r2
2159     emit_rm(cbuf, 0x3, r2, r2);
2160   %}
2161 
2162   // Clone of RegMem but accepts an extra parameter to access each
2163   // half of a double in memory; it never needs relocation info.
2164   enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2165     emit_opcode(cbuf,$opcode$$constant);
2166     int reg_encoding = $rm_reg$$reg;
2167     int base     = $mem$$base;
2168     int index    = $mem$$index;
2169     int scale    = $mem$$scale;
2170     int displace = $mem$$disp + $disp_for_half$$constant;
2171     relocInfo::relocType disp_reloc = relocInfo::none;
2172     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2173   %}
2174 
2175   // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2176   //
2177   // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2178   // and it never needs relocation information.
2179   // Frequently used to move data between FPU's Stack Top and memory.
2180   enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2181     int rm_byte_opcode = $rm_opcode$$constant;
2182     int base     = $mem$$base;
2183     int index    = $mem$$index;
2184     int scale    = $mem$$scale;
2185     int displace = $mem$$disp;
2186     assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2187     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2188   %}
2189 
2190   enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2191     int rm_byte_opcode = $rm_opcode$$constant;
2192     int base     = $mem$$base;
2193     int index    = $mem$$index;
2194     int scale    = $mem$$scale;
2195     int displace = $mem$$disp;
2196     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2197     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2198   %}
2199 
2200   enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{    // emit_reg_lea
2201     int reg_encoding = $dst$$reg;
2202     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
2203     int index        = 0x04;            // 0x04 indicates no index
2204     int scale        = 0x00;            // 0x00 indicates no scale
2205     int displace     = $src1$$constant; // 0x00 indicates no displacement
2206     relocInfo::relocType disp_reloc = relocInfo::none;
2207     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2208   %}
2209 
2210   enc_class min_enc (rRegI dst, rRegI src) %{    // MIN
2211     // Compare dst,src
2212     emit_opcode(cbuf,0x3B);
2213     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2214     // jmp dst < src around move
2215     emit_opcode(cbuf,0x7C);
2216     emit_d8(cbuf,2);
2217     // move dst,src
2218     emit_opcode(cbuf,0x8B);
2219     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2220   %}
2221 
2222   enc_class max_enc (rRegI dst, rRegI src) %{    // MAX
2223     // Compare dst,src
2224     emit_opcode(cbuf,0x3B);
2225     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2226     // jmp dst > src around move
2227     emit_opcode(cbuf,0x7F);
2228     emit_d8(cbuf,2);
2229     // move dst,src
2230     emit_opcode(cbuf,0x8B);
2231     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2232   %}
2233 
2234   enc_class enc_FPR_store(memory mem, regDPR src) %{
2235     // If src is FPR1, we can just FST to store it.
2236     // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2237     int reg_encoding = 0x2; // Just store
2238     int base  = $mem$$base;
2239     int index = $mem$$index;
2240     int scale = $mem$$scale;
2241     int displace = $mem$$disp;
2242     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2243     if( $src$$reg != FPR1L_enc ) {
2244       reg_encoding = 0x3;  // Store & pop
2245       emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2246       emit_d8( cbuf, 0xC0-1+$src$$reg );
2247     }
2248     cbuf.set_insts_mark();       // Mark start of opcode for reloc info in mem operand
2249     emit_opcode(cbuf,$primary);
2250     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2251   %}
2252 
2253   enc_class neg_reg(rRegI dst) %{
2254     // NEG $dst
2255     emit_opcode(cbuf,0xF7);
2256     emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2257   %}
2258 
2259   enc_class setLT_reg(eCXRegI dst) %{
2260     // SETLT $dst
2261     emit_opcode(cbuf,0x0F);
2262     emit_opcode(cbuf,0x9C);
2263     emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2264   %}
2265 
2266   enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{    // cadd_cmpLT
2267     int tmpReg = $tmp$$reg;
2268 
2269     // SUB $p,$q
2270     emit_opcode(cbuf,0x2B);
2271     emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2272     // SBB $tmp,$tmp
2273     emit_opcode(cbuf,0x1B);
2274     emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2275     // AND $tmp,$y
2276     emit_opcode(cbuf,0x23);
2277     emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2278     // ADD $p,$tmp
2279     emit_opcode(cbuf,0x03);
2280     emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2281   %}
2282 
2283   enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2284     // TEST shift,32
2285     emit_opcode(cbuf,0xF7);
2286     emit_rm(cbuf, 0x3, 0, ECX_enc);
2287     emit_d32(cbuf,0x20);
2288     // JEQ,s small
2289     emit_opcode(cbuf, 0x74);
2290     emit_d8(cbuf, 0x04);
2291     // MOV    $dst.hi,$dst.lo
2292     emit_opcode( cbuf, 0x8B );
2293     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2294     // CLR    $dst.lo
2295     emit_opcode(cbuf, 0x33);
2296     emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2297 // small:
2298     // SHLD   $dst.hi,$dst.lo,$shift
2299     emit_opcode(cbuf,0x0F);
2300     emit_opcode(cbuf,0xA5);
2301     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2302     // SHL    $dst.lo,$shift"
2303     emit_opcode(cbuf,0xD3);
2304     emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2305   %}
2306 
2307   enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2308     // TEST shift,32
2309     emit_opcode(cbuf,0xF7);
2310     emit_rm(cbuf, 0x3, 0, ECX_enc);
2311     emit_d32(cbuf,0x20);
2312     // JEQ,s small
2313     emit_opcode(cbuf, 0x74);
2314     emit_d8(cbuf, 0x04);
2315     // MOV    $dst.lo,$dst.hi
2316     emit_opcode( cbuf, 0x8B );
2317     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2318     // CLR    $dst.hi
2319     emit_opcode(cbuf, 0x33);
2320     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2321 // small:
2322     // SHRD   $dst.lo,$dst.hi,$shift
2323     emit_opcode(cbuf,0x0F);
2324     emit_opcode(cbuf,0xAD);
2325     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2326     // SHR    $dst.hi,$shift"
2327     emit_opcode(cbuf,0xD3);
2328     emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2329   %}
2330 
2331   enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2332     // TEST shift,32
2333     emit_opcode(cbuf,0xF7);
2334     emit_rm(cbuf, 0x3, 0, ECX_enc);
2335     emit_d32(cbuf,0x20);
2336     // JEQ,s small
2337     emit_opcode(cbuf, 0x74);
2338     emit_d8(cbuf, 0x05);
2339     // MOV    $dst.lo,$dst.hi
2340     emit_opcode( cbuf, 0x8B );
2341     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2342     // SAR    $dst.hi,31
2343     emit_opcode(cbuf, 0xC1);
2344     emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2345     emit_d8(cbuf, 0x1F );
2346 // small:
2347     // SHRD   $dst.lo,$dst.hi,$shift
2348     emit_opcode(cbuf,0x0F);
2349     emit_opcode(cbuf,0xAD);
2350     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2351     // SAR    $dst.hi,$shift"
2352     emit_opcode(cbuf,0xD3);
2353     emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2354   %}
2355 
2356 
2357   // ----------------- Encodings for floating point unit -----------------
2358   // May leave result in FPU-TOS or FPU reg depending on opcodes
2359   enc_class OpcReg_FPR(regFPR src) %{    // FMUL, FDIV
2360     $$$emit8$primary;
2361     emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2362   %}
2363 
2364   // Pop argument in FPR0 with FSTP ST(0)
2365   enc_class PopFPU() %{
2366     emit_opcode( cbuf, 0xDD );
2367     emit_d8( cbuf, 0xD8 );
2368   %}
2369 
2370   // !!!!! equivalent to Pop_Reg_F
2371   enc_class Pop_Reg_DPR( regDPR dst ) %{
2372     emit_opcode( cbuf, 0xDD );           // FSTP   ST(i)
2373     emit_d8( cbuf, 0xD8+$dst$$reg );
2374   %}
2375 
2376   enc_class Push_Reg_DPR( regDPR dst ) %{
2377     emit_opcode( cbuf, 0xD9 );
2378     emit_d8( cbuf, 0xC0-1+$dst$$reg );   // FLD ST(i-1)
2379   %}
2380 
2381   enc_class strictfp_bias1( regDPR dst ) %{
2382     emit_opcode( cbuf, 0xDB );           // FLD m80real
2383     emit_opcode( cbuf, 0x2D );
2384     emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2385     emit_opcode( cbuf, 0xDE );           // FMULP ST(dst), ST0
2386     emit_opcode( cbuf, 0xC8+$dst$$reg );
2387   %}
2388 
2389   enc_class strictfp_bias2( regDPR dst ) %{
2390     emit_opcode( cbuf, 0xDB );           // FLD m80real
2391     emit_opcode( cbuf, 0x2D );
2392     emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2393     emit_opcode( cbuf, 0xDE );           // FMULP ST(dst), ST0
2394     emit_opcode( cbuf, 0xC8+$dst$$reg );
2395   %}
2396 
2397   // Special case for moving an integer register to a stack slot.
2398   enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2399     store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2400   %}
2401 
2402   // Special case for moving a register to a stack slot.
2403   enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2404     // Opcode already emitted
2405     emit_rm( cbuf, 0x02, $src$$reg, ESP_enc );   // R/M byte
2406     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);          // SIB byte
2407     emit_d32(cbuf, $dst$$disp);   // Displacement
2408   %}
2409 
2410   // Push the integer in stackSlot 'src' onto FP-stack
2411   enc_class Push_Mem_I( memory src ) %{    // FILD   [ESP+src]
2412     store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2413   %}
2414 
2415   // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2416   enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2417     store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2418   %}
2419 
2420   // Same as Pop_Mem_F except for opcode
2421   // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2422   enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2423     store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2424   %}
2425 
2426   enc_class Pop_Reg_FPR( regFPR dst ) %{
2427     emit_opcode( cbuf, 0xDD );           // FSTP   ST(i)
2428     emit_d8( cbuf, 0xD8+$dst$$reg );
2429   %}
2430 
2431   enc_class Push_Reg_FPR( regFPR dst ) %{
2432     emit_opcode( cbuf, 0xD9 );           // FLD    ST(i-1)
2433     emit_d8( cbuf, 0xC0-1+$dst$$reg );
2434   %}
2435 
2436   // Push FPU's float to a stack-slot, and pop FPU-stack
2437   enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2438     int pop = 0x02;
2439     if ($src$$reg != FPR1L_enc) {
2440       emit_opcode( cbuf, 0xD9 );         // FLD    ST(i-1)
2441       emit_d8( cbuf, 0xC0-1+$src$$reg );
2442       pop = 0x03;
2443     }
2444     store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S  [ESP+dst]
2445   %}
2446 
2447   // Push FPU's double to a stack-slot, and pop FPU-stack
2448   enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2449     int pop = 0x02;
2450     if ($src$$reg != FPR1L_enc) {
2451       emit_opcode( cbuf, 0xD9 );         // FLD    ST(i-1)
2452       emit_d8( cbuf, 0xC0-1+$src$$reg );
2453       pop = 0x03;
2454     }
2455     store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D  [ESP+dst]
2456   %}
2457 
2458   // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2459   enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2460     int pop = 0xD0 - 1; // -1 since we skip FLD
2461     if ($src$$reg != FPR1L_enc) {
2462       emit_opcode( cbuf, 0xD9 );         // FLD    ST(src-1)
2463       emit_d8( cbuf, 0xC0-1+$src$$reg );
2464       pop = 0xD8;
2465     }
2466     emit_opcode( cbuf, 0xDD );
2467     emit_d8( cbuf, pop+$dst$$reg );      // FST<P> ST(i)
2468   %}
2469 
2470 
2471   enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2472     // load dst in FPR0
2473     emit_opcode( cbuf, 0xD9 );
2474     emit_d8( cbuf, 0xC0-1+$dst$$reg );
2475     if ($src$$reg != FPR1L_enc) {
2476       // fincstp
2477       emit_opcode (cbuf, 0xD9);
2478       emit_opcode (cbuf, 0xF7);
2479       // swap src with FPR1:
2480       // FXCH FPR1 with src
2481       emit_opcode(cbuf, 0xD9);
2482       emit_d8(cbuf, 0xC8-1+$src$$reg );
2483       // fdecstp
2484       emit_opcode (cbuf, 0xD9);
2485       emit_opcode (cbuf, 0xF6);
2486     }
2487   %}
2488 
2489   enc_class Push_ModD_encoding(regD src0, regD src1) %{
2490     MacroAssembler _masm(&cbuf);
2491     __ subptr(rsp, 8);
2492     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2493     __ fld_d(Address(rsp, 0));
2494     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2495     __ fld_d(Address(rsp, 0));
2496   %}
2497 
2498   enc_class Push_ModF_encoding(regF src0, regF src1) %{
2499     MacroAssembler _masm(&cbuf);
2500     __ subptr(rsp, 4);
2501     __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2502     __ fld_s(Address(rsp, 0));
2503     __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2504     __ fld_s(Address(rsp, 0));
2505   %}
2506 
2507   enc_class Push_ResultD(regD dst) %{
2508     MacroAssembler _masm(&cbuf);
2509     __ fstp_d(Address(rsp, 0));
2510     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2511     __ addptr(rsp, 8);
2512   %}
2513 
2514   enc_class Push_ResultF(regF dst, immI d8) %{
2515     MacroAssembler _masm(&cbuf);
2516     __ fstp_s(Address(rsp, 0));
2517     __ movflt($dst$$XMMRegister, Address(rsp, 0));
2518     __ addptr(rsp, $d8$$constant);
2519   %}
2520 
2521   enc_class Push_SrcD(regD src) %{
2522     MacroAssembler _masm(&cbuf);
2523     __ subptr(rsp, 8);
2524     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2525     __ fld_d(Address(rsp, 0));
2526   %}
2527 
2528   enc_class push_stack_temp_qword() %{
2529     MacroAssembler _masm(&cbuf);
2530     __ subptr(rsp, 8);
2531   %}
2532 
2533   enc_class pop_stack_temp_qword() %{
2534     MacroAssembler _masm(&cbuf);
2535     __ addptr(rsp, 8);
2536   %}
2537 
2538   enc_class push_xmm_to_fpr1(regD src) %{
2539     MacroAssembler _masm(&cbuf);
2540     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2541     __ fld_d(Address(rsp, 0));
2542   %}
2543 
2544   enc_class Push_Result_Mod_DPR( regDPR src) %{
2545     if ($src$$reg != FPR1L_enc) {
2546       // fincstp
2547       emit_opcode (cbuf, 0xD9);
2548       emit_opcode (cbuf, 0xF7);
2549       // FXCH FPR1 with src
2550       emit_opcode(cbuf, 0xD9);
2551       emit_d8(cbuf, 0xC8-1+$src$$reg );
2552       // fdecstp
2553       emit_opcode (cbuf, 0xD9);
2554       emit_opcode (cbuf, 0xF6);
2555     }
2556     // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2557     // // FSTP   FPR$dst$$reg
2558     // emit_opcode( cbuf, 0xDD );
2559     // emit_d8( cbuf, 0xD8+$dst$$reg );
2560   %}
2561 
2562   enc_class fnstsw_sahf_skip_parity() %{
2563     // fnstsw ax
2564     emit_opcode( cbuf, 0xDF );
2565     emit_opcode( cbuf, 0xE0 );
2566     // sahf
2567     emit_opcode( cbuf, 0x9E );
2568     // jnp  ::skip
2569     emit_opcode( cbuf, 0x7B );
2570     emit_opcode( cbuf, 0x05 );
2571   %}
2572 
2573   enc_class emitModDPR() %{
2574     // fprem must be iterative
2575     // :: loop
2576     // fprem
2577     emit_opcode( cbuf, 0xD9 );
2578     emit_opcode( cbuf, 0xF8 );
2579     // wait
2580     emit_opcode( cbuf, 0x9b );
2581     // fnstsw ax
2582     emit_opcode( cbuf, 0xDF );
2583     emit_opcode( cbuf, 0xE0 );
2584     // sahf
2585     emit_opcode( cbuf, 0x9E );
2586     // jp  ::loop
2587     emit_opcode( cbuf, 0x0F );
2588     emit_opcode( cbuf, 0x8A );
2589     emit_opcode( cbuf, 0xF4 );
2590     emit_opcode( cbuf, 0xFF );
2591     emit_opcode( cbuf, 0xFF );
2592     emit_opcode( cbuf, 0xFF );
2593   %}
2594 
2595   enc_class fpu_flags() %{
2596     // fnstsw_ax
2597     emit_opcode( cbuf, 0xDF);
2598     emit_opcode( cbuf, 0xE0);
2599     // test ax,0x0400
2600     emit_opcode( cbuf, 0x66 );   // operand-size prefix for 16-bit immediate
2601     emit_opcode( cbuf, 0xA9 );
2602     emit_d16   ( cbuf, 0x0400 );
2603     // // // This sequence works, but stalls for 12-16 cycles on PPro
2604     // // test rax,0x0400
2605     // emit_opcode( cbuf, 0xA9 );
2606     // emit_d32   ( cbuf, 0x00000400 );
2607     //
2608     // jz exit (no unordered comparison)
2609     emit_opcode( cbuf, 0x74 );
2610     emit_d8    ( cbuf, 0x02 );
2611     // mov ah,1 - treat as LT case (set carry flag)
2612     emit_opcode( cbuf, 0xB4 );
2613     emit_d8    ( cbuf, 0x01 );
2614     // sahf
2615     emit_opcode( cbuf, 0x9E);
2616   %}
2617 
2618   enc_class cmpF_P6_fixup() %{
2619     // Fixup the integer flags in case comparison involved a NaN
2620     //
2621     // JNP exit (no unordered comparison, P-flag is set by NaN)
2622     emit_opcode( cbuf, 0x7B );
2623     emit_d8    ( cbuf, 0x03 );
2624     // MOV AH,1 - treat as LT case (set carry flag)
2625     emit_opcode( cbuf, 0xB4 );
2626     emit_d8    ( cbuf, 0x01 );
2627     // SAHF
2628     emit_opcode( cbuf, 0x9E);
2629     // NOP     // target for branch to avoid branch to branch
2630     emit_opcode( cbuf, 0x90);
2631   %}
2632 
2633 //     fnstsw_ax();
2634 //     sahf();
2635 //     movl(dst, nan_result);
2636 //     jcc(Assembler::parity, exit);
2637 //     movl(dst, less_result);
2638 //     jcc(Assembler::below, exit);
2639 //     movl(dst, equal_result);
2640 //     jcc(Assembler::equal, exit);
2641 //     movl(dst, greater_result);
2642 
2643 // less_result     =  1;
2644 // greater_result  = -1;
2645 // equal_result    = 0;
2646 // nan_result      = -1;
2647 
2648   enc_class CmpF_Result(rRegI dst) %{
2649     // fnstsw_ax();
2650     emit_opcode( cbuf, 0xDF);
2651     emit_opcode( cbuf, 0xE0);
2652     // sahf
2653     emit_opcode( cbuf, 0x9E);
2654     // movl(dst, nan_result);
2655     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2656     emit_d32( cbuf, -1 );
2657     // jcc(Assembler::parity, exit);
2658     emit_opcode( cbuf, 0x7A );
2659     emit_d8    ( cbuf, 0x13 );
2660     // movl(dst, less_result);
2661     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2662     emit_d32( cbuf, -1 );
2663     // jcc(Assembler::below, exit);
2664     emit_opcode( cbuf, 0x72 );
2665     emit_d8    ( cbuf, 0x0C );
2666     // movl(dst, equal_result);
2667     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2668     emit_d32( cbuf, 0 );
2669     // jcc(Assembler::equal, exit);
2670     emit_opcode( cbuf, 0x74 );
2671     emit_d8    ( cbuf, 0x05 );
2672     // movl(dst, greater_result);
2673     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2674     emit_d32( cbuf, 1 );
2675   %}
2676 
2677 
2678   // Compare the longs and set flags
2679   // BROKEN!  Do Not use as-is
2680   enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2681     // CMP    $src1.hi,$src2.hi
2682     emit_opcode( cbuf, 0x3B );
2683     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2684     // JNE,s  done
2685     emit_opcode(cbuf,0x75);
2686     emit_d8(cbuf, 2 );
2687     // CMP    $src1.lo,$src2.lo
2688     emit_opcode( cbuf, 0x3B );
2689     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2690 // done:
2691   %}
2692 
2693   enc_class convert_int_long( regL dst, rRegI src ) %{
2694     // mov $dst.lo,$src
2695     int dst_encoding = $dst$$reg;
2696     int src_encoding = $src$$reg;
2697     encode_Copy( cbuf, dst_encoding  , src_encoding );
2698     // mov $dst.hi,$src
2699     encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2700     // sar $dst.hi,31
2701     emit_opcode( cbuf, 0xC1 );
2702     emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2703     emit_d8(cbuf, 0x1F );
2704   %}
2705 
2706   enc_class convert_long_double( eRegL src ) %{
2707     // push $src.hi
2708     emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2709     // push $src.lo
2710     emit_opcode(cbuf, 0x50+$src$$reg  );
2711     // fild 64-bits at [SP]
2712     emit_opcode(cbuf,0xdf);
2713     emit_d8(cbuf, 0x6C);
2714     emit_d8(cbuf, 0x24);
2715     emit_d8(cbuf, 0x00);
2716     // pop stack
2717     emit_opcode(cbuf, 0x83); // add  SP, #8
2718     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2719     emit_d8(cbuf, 0x8);
2720   %}
2721 
2722   enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2723     // IMUL   EDX:EAX,$src1
2724     emit_opcode( cbuf, 0xF7 );
2725     emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2726     // SAR    EDX,$cnt-32
2727     int shift_count = ((int)$cnt$$constant) - 32;
2728     if (shift_count > 0) {
2729       emit_opcode(cbuf, 0xC1);
2730       emit_rm(cbuf, 0x3, 7, $dst$$reg );
2731       emit_d8(cbuf, shift_count);
2732     }
2733   %}
2734 
2735   // this version doesn't have add sp, 8
2736   enc_class convert_long_double2( eRegL src ) %{
2737     // push $src.hi
2738     emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2739     // push $src.lo
2740     emit_opcode(cbuf, 0x50+$src$$reg  );
2741     // fild 64-bits at [SP]
2742     emit_opcode(cbuf,0xdf);
2743     emit_d8(cbuf, 0x6C);
2744     emit_d8(cbuf, 0x24);
2745     emit_d8(cbuf, 0x00);
2746   %}
2747 
2748   enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2749     // Basic idea: long = (long)int * (long)int
2750     // IMUL EDX:EAX, src
2751     emit_opcode( cbuf, 0xF7 );
2752     emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2753   %}
2754 
2755   enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2756     // Basic Idea:  long = (int & 0xffffffffL) * (int & 0xffffffffL)
2757     // MUL EDX:EAX, src
2758     emit_opcode( cbuf, 0xF7 );
2759     emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2760   %}
2761 
2762   enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2763     // Basic idea: lo(result) = lo(x_lo * y_lo)
2764     //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2765     // MOV    $tmp,$src.lo
2766     encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2767     // IMUL   $tmp,EDX
2768     emit_opcode( cbuf, 0x0F );
2769     emit_opcode( cbuf, 0xAF );
2770     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2771     // MOV    EDX,$src.hi
2772     encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2773     // IMUL   EDX,EAX
2774     emit_opcode( cbuf, 0x0F );
2775     emit_opcode( cbuf, 0xAF );
2776     emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2777     // ADD    $tmp,EDX
2778     emit_opcode( cbuf, 0x03 );
2779     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2780     // MUL   EDX:EAX,$src.lo
2781     emit_opcode( cbuf, 0xF7 );
2782     emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2783     // ADD    EDX,ESI
2784     emit_opcode( cbuf, 0x03 );
2785     emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2786   %}
2787 
2788   enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2789     // Basic idea: lo(result) = lo(src * y_lo)
2790     //             hi(result) = hi(src * y_lo) + lo(src * y_hi)
2791     // IMUL   $tmp,EDX,$src
2792     emit_opcode( cbuf, 0x6B );
2793     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2794     emit_d8( cbuf, (int)$src$$constant );
2795     // MOV    EDX,$src
2796     emit_opcode(cbuf, 0xB8 + EDX_enc);
2797     emit_d32( cbuf, (int)$src$$constant );
2798     // MUL   EDX:EAX,EDX
2799     emit_opcode( cbuf, 0xF7 );
2800     emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2801     // ADD    EDX,ESI
2802     emit_opcode( cbuf, 0x03 );
2803     emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2804   %}
2805 
2806   enc_class long_div( eRegL src1, eRegL src2 ) %{
2807     // PUSH src1.hi
2808     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2809     // PUSH src1.lo
2810     emit_opcode(cbuf,               0x50+$src1$$reg  );
2811     // PUSH src2.hi
2812     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2813     // PUSH src2.lo
2814     emit_opcode(cbuf,               0x50+$src2$$reg  );
2815     // CALL directly to the runtime
2816     cbuf.set_insts_mark();
2817     emit_opcode(cbuf,0xE8);       // Call into runtime
2818     emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2819     // Restore stack
2820     emit_opcode(cbuf, 0x83); // add  SP, #framesize
2821     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2822     emit_d8(cbuf, 4*4);
2823   %}
2824 
2825   enc_class long_mod( eRegL src1, eRegL src2 ) %{
2826     // PUSH src1.hi
2827     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2828     // PUSH src1.lo
2829     emit_opcode(cbuf,               0x50+$src1$$reg  );
2830     // PUSH src2.hi
2831     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2832     // PUSH src2.lo
2833     emit_opcode(cbuf,               0x50+$src2$$reg  );
2834     // CALL directly to the runtime
2835     cbuf.set_insts_mark();
2836     emit_opcode(cbuf,0xE8);       // Call into runtime
2837     emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2838     // Restore stack
2839     emit_opcode(cbuf, 0x83); // add  SP, #framesize
2840     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2841     emit_d8(cbuf, 4*4);
2842   %}
2843 
2844   enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2845     // MOV   $tmp,$src.lo
2846     emit_opcode(cbuf, 0x8B);
2847     emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2848     // OR    $tmp,$src.hi
2849     emit_opcode(cbuf, 0x0B);
2850     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2851   %}
2852 
2853   enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2854     // CMP    $src1.lo,$src2.lo
2855     emit_opcode( cbuf, 0x3B );
2856     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2857     // JNE,s  skip
2858     emit_cc(cbuf, 0x70, 0x5);
2859     emit_d8(cbuf,2);
2860     // CMP    $src1.hi,$src2.hi
2861     emit_opcode( cbuf, 0x3B );
2862     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2863   %}
2864 
2865   enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2866     // CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2867     emit_opcode( cbuf, 0x3B );
2868     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2869     // MOV    $tmp,$src1.hi
2870     emit_opcode( cbuf, 0x8B );
2871     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2872     // SBB   $tmp,$src2.hi\t! Compute flags for long compare
2873     emit_opcode( cbuf, 0x1B );
2874     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2875   %}
2876 
2877   enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2878     // XOR    $tmp,$tmp
2879     emit_opcode(cbuf,0x33);  // XOR
2880     emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2881     // CMP    $tmp,$src.lo
2882     emit_opcode( cbuf, 0x3B );
2883     emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2884     // SBB    $tmp,$src.hi
2885     emit_opcode( cbuf, 0x1B );
2886     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2887   %}
2888 
2889  // Sniff, sniff... smells like Gnu Superoptimizer
2890   enc_class neg_long( eRegL dst ) %{
2891     emit_opcode(cbuf,0xF7);    // NEG hi
2892     emit_rm    (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2893     emit_opcode(cbuf,0xF7);    // NEG lo
2894     emit_rm    (cbuf,0x3, 0x3,               $dst$$reg );
2895     emit_opcode(cbuf,0x83);    // SBB hi,0
2896     emit_rm    (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2897     emit_d8    (cbuf,0 );
2898   %}
2899 
2900 
2901   // Because the transitions from emitted code to the runtime
2902   // monitorenter/exit helper stubs are so slow it's critical that
2903   // we inline both the stack-locking fast-path and the inflated fast path.
2904   //
2905   // See also: cmpFastLock and cmpFastUnlock.
2906   //
2907   // What follows is a specialized inline transliteration of the code
2908   // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
2909   // another option would be to emit TrySlowEnter and TrySlowExit methods
2910   // at startup-time.  These methods would accept arguments as
2911   // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2912   // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
2913   // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2914   // In practice, however, the # of lock sites is bounded and is usually small.
2915   // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2916   // if the processor uses simple bimodal branch predictors keyed by EIP
2917   // Since the helper routines would be called from multiple synchronization
2918   // sites.
2919   //
2920   // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2921   // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2922   // to those specialized methods.  That'd give us a mostly platform-independent
2923   // implementation that the JITs could optimize and inline at their pleasure.
2924   // Done correctly, the only time we'd need to cross to native could would be
2925   // to park() or unpark() threads.  We'd also need a few more unsafe operators
2926   // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2927   // (b) explicit barriers or fence operations.
2928   //
2929   // TODO:
2930   //
2931   // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2932   //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2933   //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
2934   //    the lock operators would typically be faster than reifying Self.
2935   //
2936   // *  Ideally I'd define the primitives as:
2937   //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2938   //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2939   //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
2940   //    Instead, we're stuck with a rather awkward and brittle register assignments below.
2941   //    Furthermore the register assignments are overconstrained, possibly resulting in
2942   //    sub-optimal code near the synchronization site.
2943   //
2944   // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
2945   //    Alternately, use a better sp-proximity test.
2946   //
2947   // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2948   //    Either one is sufficient to uniquely identify a thread.
2949   //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2950   //
2951   // *  Intrinsify notify() and notifyAll() for the common cases where the
2952   //    object is locked by the calling thread but the waitlist is empty.
2953   //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2954   //
2955   // *  use jccb and jmpb instead of jcc and jmp to improve code density.
2956   //    But beware of excessive branch density on AMD Opterons.
2957   //
2958   // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2959   //    or failure of the fast-path.  If the fast-path fails then we pass
2960   //    control to the slow-path, typically in C.  In Fast_Lock and
2961   //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2962   //    will emit a conditional branch immediately after the node.
2963   //    So we have branches to branches and lots of ICC.ZF games.
2964   //    Instead, it might be better to have C2 pass a "FailureLabel"
2965   //    into Fast_Lock and Fast_Unlock.  In the case of success, control
2966   //    will drop through the node.  ICC.ZF is undefined at exit.
2967   //    In the case of failure, the node will branch directly to the
2968   //    FailureLabel
2969 
2970 
2971   // obj: object to lock
2972   // box: on-stack box address (displaced header location) - KILLED
2973   // rax,: tmp -- KILLED
2974   // scr: tmp -- KILLED
2975   enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2976 
2977     Register objReg = as_Register($obj$$reg);
2978     Register boxReg = as_Register($box$$reg);
2979     Register tmpReg = as_Register($tmp$$reg);
2980     Register scrReg = as_Register($scr$$reg);
2981 
2982     // Ensure the register assignents are disjoint
2983     guarantee (objReg != boxReg, "") ;
2984     guarantee (objReg != tmpReg, "") ;
2985     guarantee (objReg != scrReg, "") ;
2986     guarantee (boxReg != tmpReg, "") ;
2987     guarantee (boxReg != scrReg, "") ;
2988     guarantee (tmpReg == as_Register(EAX_enc), "") ;
2989 
2990     MacroAssembler masm(&cbuf);
2991 
2992     if (_counters != NULL) {
2993       masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
2994     }
2995     if (EmitSync & 1) {
2996         // set box->dhw = unused_mark (3)
2997         // Force all sync thru slow-path: slow_enter() and slow_exit() 
2998         masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;             
2999         masm.cmpptr (rsp, (int32_t)0) ;                        
3000     } else 
3001     if (EmitSync & 2) { 
3002         Label DONE_LABEL ;           
3003         if (UseBiasedLocking) {
3004            // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3005            masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3006         }
3007 
3008         masm.movptr(tmpReg, Address(objReg, 0)) ;          // fetch markword 
3009         masm.orptr (tmpReg, 0x1);
3010         masm.movptr(Address(boxReg, 0), tmpReg);           // Anticipate successful CAS 
3011         if (os::is_MP()) { masm.lock();  }
3012         masm.cmpxchgptr(boxReg, Address(objReg, 0));          // Updates tmpReg
3013         masm.jcc(Assembler::equal, DONE_LABEL);
3014         // Recursive locking
3015         masm.subptr(tmpReg, rsp);
3016         masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3017         masm.movptr(Address(boxReg, 0), tmpReg);
3018         masm.bind(DONE_LABEL) ; 
3019     } else {  
3020       // Possible cases that we'll encounter in fast_lock 
3021       // ------------------------------------------------
3022       // * Inflated
3023       //    -- unlocked
3024       //    -- Locked
3025       //       = by self
3026       //       = by other
3027       // * biased
3028       //    -- by Self
3029       //    -- by other
3030       // * neutral
3031       // * stack-locked
3032       //    -- by self
3033       //       = sp-proximity test hits
3034       //       = sp-proximity test generates false-negative
3035       //    -- by other
3036       //
3037 
3038       Label IsInflated, DONE_LABEL, PopDone ;
3039 
3040       // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3041       // order to reduce the number of conditional branches in the most common cases.
3042       // Beware -- there's a subtle invariant that fetch of the markword
3043       // at [FETCH], below, will never observe a biased encoding (*101b).
3044       // If this invariant is not held we risk exclusion (safety) failure.
3045       if (UseBiasedLocking && !UseOptoBiasInlining) {
3046         masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3047       }
3048 
3049       masm.movptr(tmpReg, Address(objReg, 0)) ;         // [FETCH]
3050       masm.testptr(tmpReg, 0x02) ;                      // Inflated v (Stack-locked or neutral)
3051       masm.jccb  (Assembler::notZero, IsInflated) ;
3052 
3053       // Attempt stack-locking ...
3054       masm.orptr (tmpReg, 0x1);
3055       masm.movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
3056       if (os::is_MP()) { masm.lock();  }
3057       masm.cmpxchgptr(boxReg, Address(objReg, 0));           // Updates tmpReg
3058       if (_counters != NULL) {
3059         masm.cond_inc32(Assembler::equal,
3060                         ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3061       }
3062       masm.jccb (Assembler::equal, DONE_LABEL);
3063 
3064       // Recursive locking
3065       masm.subptr(tmpReg, rsp);
3066       masm.andptr(tmpReg, 0xFFFFF003 );
3067       masm.movptr(Address(boxReg, 0), tmpReg);
3068       if (_counters != NULL) {
3069         masm.cond_inc32(Assembler::equal,
3070                         ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3071       }
3072       masm.jmp  (DONE_LABEL) ;
3073 
3074       masm.bind (IsInflated) ;
3075 
3076       // The object is inflated.
3077       //
3078       // TODO-FIXME: eliminate the ugly use of manifest constants:
3079       //   Use markOopDesc::monitor_value instead of "2".
3080       //   use markOop::unused_mark() instead of "3".
3081       // The tmpReg value is an objectMonitor reference ORed with
3082       // markOopDesc::monitor_value (2).   We can either convert tmpReg to an
3083       // objectmonitor pointer by masking off the "2" bit or we can just
3084       // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3085       // field offsets with "-2" to compensate for and annul the low-order tag bit.
3086       //
3087       // I use the latter as it avoids AGI stalls.
3088       // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3089       // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3090       //
3091       #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3092 
3093       // boxReg refers to the on-stack BasicLock in the current frame.
3094       // We'd like to write:
3095       //   set box->_displaced_header = markOop::unused_mark().  Any non-0 value suffices.
3096       // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
3097       // additional latency as we have another ST in the store buffer that must drain.
3098 
3099       if (EmitSync & 8192) { 
3100          masm.movptr(Address(boxReg, 0), 3) ;            // results in ST-before-CAS penalty
3101          masm.get_thread (scrReg) ; 
3102          masm.movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2] 
3103          masm.movptr(tmpReg, NULL_WORD);                 // consider: xor vs mov
3104          if (os::is_MP()) { masm.lock(); } 
3105          masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
3106       } else 
3107       if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
3108          masm.movptr(scrReg, boxReg) ; 
3109          masm.movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2] 
3110 
3111          // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3112          if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3113             // prefetchw [eax + Offset(_owner)-2]
3114             masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3115          }
3116 
3117          if ((EmitSync & 64) == 0) {
3118            // Optimistic form: consider XORL tmpReg,tmpReg
3119            masm.movptr(tmpReg, NULL_WORD) ; 
3120          } else { 
3121            // Can suffer RTS->RTO upgrades on shared or cold $ lines
3122            // Test-And-CAS instead of CAS
3123            masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
3124            masm.testptr(tmpReg, tmpReg) ;                   // Locked ? 
3125            masm.jccb  (Assembler::notZero, DONE_LABEL) ;                   
3126          }
3127 
3128          // Appears unlocked - try to swing _owner from null to non-null.
3129          // Ideally, I'd manifest "Self" with get_thread and then attempt
3130          // to CAS the register containing Self into m->Owner.
3131          // But we don't have enough registers, so instead we can either try to CAS
3132          // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
3133          // we later store "Self" into m->Owner.  Transiently storing a stack address
3134          // (rsp or the address of the box) into  m->owner is harmless.
3135          // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
3136          if (os::is_MP()) { masm.lock();  }
3137          masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
3138          masm.movptr(Address(scrReg, 0), 3) ;          // box->_displaced_header = 3
3139          masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
3140          masm.get_thread (scrReg) ;                    // beware: clobbers ICCs
3141          masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 
3142          masm.xorptr(boxReg, boxReg) ;                 // set icc.ZFlag = 1 to indicate success
3143                        
3144          // If the CAS fails we can either retry or pass control to the slow-path.  
3145          // We use the latter tactic.  
3146          // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3147          // If the CAS was successful ...
3148          //   Self has acquired the lock
3149          //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3150          // Intentional fall-through into DONE_LABEL ...
3151       } else {
3152          masm.movptr(Address(boxReg, 0), 3) ;       // results in ST-before-CAS penalty
3153          masm.movptr(boxReg, tmpReg) ; 
3154 
3155          // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3156          if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3157             // prefetchw [eax + Offset(_owner)-2]
3158             masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3159          }
3160 
3161          if ((EmitSync & 64) == 0) {
3162            // Optimistic form
3163            masm.xorptr  (tmpReg, tmpReg) ; 
3164          } else { 
3165            // Can suffer RTS->RTO upgrades on shared or cold $ lines
3166            masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
3167            masm.testptr(tmpReg, tmpReg) ;                   // Locked ? 
3168            masm.jccb  (Assembler::notZero, DONE_LABEL) ;                   
3169          }
3170 
3171          // Appears unlocked - try to swing _owner from null to non-null.
3172          // Use either "Self" (in scr) or rsp as thread identity in _owner.
3173          // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
3174          masm.get_thread (scrReg) ;
3175          if (os::is_MP()) { masm.lock(); }
3176          masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3177 
3178          // If the CAS fails we can either retry or pass control to the slow-path.
3179          // We use the latter tactic.
3180          // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3181          // If the CAS was successful ...
3182          //   Self has acquired the lock
3183          //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3184          // Intentional fall-through into DONE_LABEL ...
3185       }
3186 
3187       // DONE_LABEL is a hot target - we'd really like to place it at the
3188       // start of cache line by padding with NOPs.
3189       // See the AMD and Intel software optimization manuals for the
3190       // most efficient "long" NOP encodings.
3191       // Unfortunately none of our alignment mechanisms suffice.
3192       masm.bind(DONE_LABEL);
3193 
3194       // Avoid branch-to-branch on AMD processors
3195       // This appears to be superstition.
3196       if (EmitSync & 32) masm.nop() ;
3197 
3198 
3199       // At DONE_LABEL the icc ZFlag is set as follows ...
3200       // Fast_Unlock uses the same protocol.
3201       // ZFlag == 1 -> Success
3202       // ZFlag == 0 -> Failure - force control through the slow-path
3203     }
3204   %}
3205 
3206   // obj: object to unlock
3207   // box: box address (displaced header location), killed.  Must be EAX.
3208   // rbx,: killed tmp; cannot be obj nor box.
3209   //
3210   // Some commentary on balanced locking:
3211   //
3212   // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3213   // Methods that don't have provably balanced locking are forced to run in the
3214   // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3215   // The interpreter provides two properties:
3216   // I1:  At return-time the interpreter automatically and quietly unlocks any
3217   //      objects acquired the current activation (frame).  Recall that the
3218   //      interpreter maintains an on-stack list of locks currently held by
3219   //      a frame.
3220   // I2:  If a method attempts to unlock an object that is not held by the
3221   //      the frame the interpreter throws IMSX.
3222   //
3223   // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3224   // B() doesn't have provably balanced locking so it runs in the interpreter.
3225   // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
3226   // is still locked by A().
3227   //
3228   // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
3229   // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3230   // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
3231   // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3232 
3233   enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3234 
3235     Register objReg = as_Register($obj$$reg);
3236     Register boxReg = as_Register($box$$reg);
3237     Register tmpReg = as_Register($tmp$$reg);
3238 
3239     guarantee (objReg != boxReg, "") ;
3240     guarantee (objReg != tmpReg, "") ;
3241     guarantee (boxReg != tmpReg, "") ;
3242     guarantee (boxReg == as_Register(EAX_enc), "") ;
3243     MacroAssembler masm(&cbuf);
3244 
3245     if (EmitSync & 4) {
3246       // Disable - inhibit all inlining.  Force control through the slow-path
3247       masm.cmpptr (rsp, 0) ; 
3248     } else 
3249     if (EmitSync & 8) {
3250       Label DONE_LABEL ;
3251       if (UseBiasedLocking) {
3252          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3253       }
3254       // classic stack-locking code ...
3255       masm.movptr(tmpReg, Address(boxReg, 0)) ;
3256       masm.testptr(tmpReg, tmpReg) ;
3257       masm.jcc   (Assembler::zero, DONE_LABEL) ;
3258       if (os::is_MP()) { masm.lock(); }
3259       masm.cmpxchgptr(tmpReg, Address(objReg, 0));          // Uses EAX which is box
3260       masm.bind(DONE_LABEL);
3261     } else {
3262       Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3263 
3264       // Critically, the biased locking test must have precedence over
3265       // and appear before the (box->dhw == 0) recursive stack-lock test.
3266       if (UseBiasedLocking && !UseOptoBiasInlining) {
3267          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3268       }
3269       
3270       masm.cmpptr(Address(boxReg, 0), 0) ;            // Examine the displaced header
3271       masm.movptr(tmpReg, Address(objReg, 0)) ;       // Examine the object's markword
3272       masm.jccb  (Assembler::zero, DONE_LABEL) ;      // 0 indicates recursive stack-lock
3273 
3274       masm.testptr(tmpReg, 0x02) ;                     // Inflated? 
3275       masm.jccb  (Assembler::zero, Stacked) ;
3276 
3277       masm.bind  (Inflated) ;
3278       // It's inflated.
3279       // Despite our balanced locking property we still check that m->_owner == Self
3280       // as java routines or native JNI code called by this thread might
3281       // have released the lock.
3282       // Refer to the comments in synchronizer.cpp for how we might encode extra
3283       // state in _succ so we can avoid fetching EntryList|cxq.
3284       //
3285       // I'd like to add more cases in fast_lock() and fast_unlock() --
3286       // such as recursive enter and exit -- but we have to be wary of
3287       // I$ bloat, T$ effects and BP$ effects.
3288       //
3289       // If there's no contention try a 1-0 exit.  That is, exit without
3290       // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
3291       // we detect and recover from the race that the 1-0 exit admits.
3292       //
3293       // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3294       // before it STs null into _owner, releasing the lock.  Updates
3295       // to data protected by the critical section must be visible before
3296       // we drop the lock (and thus before any other thread could acquire
3297       // the lock and observe the fields protected by the lock).
3298       // IA32's memory-model is SPO, so STs are ordered with respect to
3299       // each other and there's no need for an explicit barrier (fence).
3300       // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3301 
3302       masm.get_thread (boxReg) ;
3303       if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3304         // prefetchw [ebx + Offset(_owner)-2]
3305         masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3306       }
3307 
3308       // Note that we could employ various encoding schemes to reduce
3309       // the number of loads below (currently 4) to just 2 or 3.
3310       // Refer to the comments in synchronizer.cpp.
3311       // In practice the chain of fetches doesn't seem to impact performance, however.
3312       if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3313          // Attempt to reduce branch density - AMD's branch predictor.
3314          masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;  
3315          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3316          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
3317          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
3318          masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
3319          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 
3320          masm.jmpb  (DONE_LABEL) ; 
3321       } else { 
3322          masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;  
3323          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3324          masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
3325          masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
3326          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
3327          masm.jccb  (Assembler::notZero, CheckSucc) ; 
3328          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 
3329          masm.jmpb  (DONE_LABEL) ; 
3330       }
3331 
3332       // The Following code fragment (EmitSync & 65536) improves the performance of
3333       // contended applications and contended synchronization microbenchmarks.
3334       // Unfortunately the emission of the code - even though not executed - causes regressions
3335       // in scimark and jetstream, evidently because of $ effects.  Replacing the code
3336       // with an equal number of never-executed NOPs results in the same regression.
3337       // We leave it off by default.
3338 
3339       if ((EmitSync & 65536) != 0) {
3340          Label LSuccess, LGoSlowPath ;
3341 
3342          masm.bind  (CheckSucc) ;
3343 
3344          // Optional pre-test ... it's safe to elide this
3345          if ((EmitSync & 16) == 0) { 
3346             masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 
3347             masm.jccb  (Assembler::zero, LGoSlowPath) ; 
3348          }
3349 
3350          // We have a classic Dekker-style idiom:
3351          //    ST m->_owner = 0 ; MEMBAR; LD m->_succ
3352          // There are a number of ways to implement the barrier:
3353          // (1) lock:andl &m->_owner, 0
3354          //     is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3355          //     LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3356          //     Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3357          // (2) If supported, an explicit MFENCE is appealing.
3358          //     In older IA32 processors MFENCE is slower than lock:add or xchg
3359          //     particularly if the write-buffer is full as might be the case if
3360          //     if stores closely precede the fence or fence-equivalent instruction.
3361          //     In more modern implementations MFENCE appears faster, however.
3362          // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3363          //     The $lines underlying the top-of-stack should be in M-state.
3364          //     The locked add instruction is serializing, of course.
3365          // (4) Use xchg, which is serializing
3366          //     mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3367          // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3368          //     The integer condition codes will tell us if succ was 0.
3369          //     Since _succ and _owner should reside in the same $line and
3370          //     we just stored into _owner, it's likely that the $line
3371          //     remains in M-state for the lock:orl.
3372          //
3373          // We currently use (3), although it's likely that switching to (2)
3374          // is correct for the future.
3375             
3376          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 
3377          if (os::is_MP()) { 
3378             if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 
3379               masm.mfence();
3380             } else { 
3381               masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; 
3382             }
3383          }
3384          // Ratify _succ remains non-null
3385          masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 
3386          masm.jccb  (Assembler::notZero, LSuccess) ; 
3387 
3388          masm.xorptr(boxReg, boxReg) ;                  // box is really EAX
3389          if (os::is_MP()) { masm.lock(); }
3390          masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3391          masm.jccb  (Assembler::notEqual, LSuccess) ;
3392          // Since we're low on registers we installed rsp as a placeholding in _owner.
3393          // Now install Self over rsp.  This is safe as we're transitioning from
3394          // non-null to non=null
3395          masm.get_thread (boxReg) ;
3396          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3397          // Intentional fall-through into LGoSlowPath ...
3398 
3399          masm.bind  (LGoSlowPath) ; 
3400          masm.orptr(boxReg, 1) ;                      // set ICC.ZF=0 to indicate failure
3401          masm.jmpb  (DONE_LABEL) ; 
3402 
3403          masm.bind  (LSuccess) ; 
3404          masm.xorptr(boxReg, boxReg) ;                 // set ICC.ZF=1 to indicate success
3405          masm.jmpb  (DONE_LABEL) ; 
3406       }
3407 
3408       masm.bind (Stacked) ;
3409       // It's not inflated and it's not recursively stack-locked and it's not biased.
3410       // It must be stack-locked.
3411       // Try to reset the header to displaced header.
3412       // The "box" value on the stack is stable, so we can reload
3413       // and be assured we observe the same value as above.
3414       masm.movptr(tmpReg, Address(boxReg, 0)) ;
3415       if (os::is_MP()) {   masm.lock();    }
3416       masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3417       // Intention fall-thru into DONE_LABEL
3418 
3419 
3420       // DONE_LABEL is a hot target - we'd really like to place it at the
3421       // start of cache line by padding with NOPs.
3422       // See the AMD and Intel software optimization manuals for the
3423       // most efficient "long" NOP encodings.
3424       // Unfortunately none of our alignment mechanisms suffice.
3425       if ((EmitSync & 65536) == 0) {
3426          masm.bind (CheckSucc) ;
3427       }
3428       masm.bind(DONE_LABEL);
3429 
3430       // Avoid branch to branch on AMD processors
3431       if (EmitSync & 32768) { masm.nop() ; }
3432     }
3433   %}
3434 
3435 
3436   enc_class enc_pop_rdx() %{
3437     emit_opcode(cbuf,0x5A);
3438   %}
3439 
3440   enc_class enc_rethrow() %{
3441     cbuf.set_insts_mark();
3442     emit_opcode(cbuf, 0xE9);        // jmp    entry
3443     emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3444                    runtime_call_Relocation::spec(), RELOC_IMM32 );
3445   %}
3446 
3447 
3448   // Convert a double to an int.  Java semantics require we do complex
3449   // manglelations in the corner cases.  So we set the rounding mode to
3450   // 'zero', store the darned double down as an int, and reset the
3451   // rounding mode to 'nearest'.  The hardware throws an exception which
3452   // patches up the correct value directly to the stack.
3453   enc_class DPR2I_encoding( regDPR src ) %{
3454     // Flip to round-to-zero mode.  We attempted to allow invalid-op
3455     // exceptions here, so that a NAN or other corner-case value will
3456     // thrown an exception (but normal values get converted at full speed).
3457     // However, I2C adapters and other float-stack manglers leave pending
3458     // invalid-op exceptions hanging.  We would have to clear them before
3459     // enabling them and that is more expensive than just testing for the
3460     // invalid value Intel stores down in the corner cases.
3461     emit_opcode(cbuf,0xD9);            // FLDCW  trunc
3462     emit_opcode(cbuf,0x2D);
3463     emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3464     // Allocate a word
3465     emit_opcode(cbuf,0x83);            // SUB ESP,4
3466     emit_opcode(cbuf,0xEC);
3467     emit_d8(cbuf,0x04);
3468     // Encoding assumes a double has been pushed into FPR0.
3469     // Store down the double as an int, popping the FPU stack
3470     emit_opcode(cbuf,0xDB);            // FISTP [ESP]
3471     emit_opcode(cbuf,0x1C);
3472     emit_d8(cbuf,0x24);
3473     // Restore the rounding mode; mask the exception
3474     emit_opcode(cbuf,0xD9);            // FLDCW   std/24-bit mode
3475     emit_opcode(cbuf,0x2D);
3476     emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3477         ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3478         : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3479 
3480     // Load the converted int; adjust CPU stack
3481     emit_opcode(cbuf,0x58);       // POP EAX
3482     emit_opcode(cbuf,0x3D);       // CMP EAX,imm
3483     emit_d32   (cbuf,0x80000000); //         0x80000000
3484     emit_opcode(cbuf,0x75);       // JNE around_slow_call
3485     emit_d8    (cbuf,0x07);       // Size of slow_call
3486     // Push src onto stack slow-path
3487     emit_opcode(cbuf,0xD9 );      // FLD     ST(i)
3488     emit_d8    (cbuf,0xC0-1+$src$$reg );
3489     // CALL directly to the runtime
3490     cbuf.set_insts_mark();
3491     emit_opcode(cbuf,0xE8);       // Call into runtime
3492     emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3493     // Carry on here...
3494   %}
3495 
3496   enc_class DPR2L_encoding( regDPR src ) %{
3497     emit_opcode(cbuf,0xD9);            // FLDCW  trunc
3498     emit_opcode(cbuf,0x2D);
3499     emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3500     // Allocate a word
3501     emit_opcode(cbuf,0x83);            // SUB ESP,8
3502     emit_opcode(cbuf,0xEC);
3503     emit_d8(cbuf,0x08);
3504     // Encoding assumes a double has been pushed into FPR0.
3505     // Store down the double as a long, popping the FPU stack
3506     emit_opcode(cbuf,0xDF);            // FISTP [ESP]
3507     emit_opcode(cbuf,0x3C);
3508     emit_d8(cbuf,0x24);
3509     // Restore the rounding mode; mask the exception
3510     emit_opcode(cbuf,0xD9);            // FLDCW   std/24-bit mode
3511     emit_opcode(cbuf,0x2D);
3512     emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3513         ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3514         : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3515 
3516     // Load the converted int; adjust CPU stack
3517     emit_opcode(cbuf,0x58);       // POP EAX
3518     emit_opcode(cbuf,0x5A);       // POP EDX
3519     emit_opcode(cbuf,0x81);       // CMP EDX,imm
3520     emit_d8    (cbuf,0xFA);       // rdx
3521     emit_d32   (cbuf,0x80000000); //         0x80000000
3522     emit_opcode(cbuf,0x75);       // JNE around_slow_call
3523     emit_d8    (cbuf,0x07+4);     // Size of slow_call
3524     emit_opcode(cbuf,0x85);       // TEST EAX,EAX
3525     emit_opcode(cbuf,0xC0);       // 2/rax,/rax,
3526     emit_opcode(cbuf,0x75);       // JNE around_slow_call
3527     emit_d8    (cbuf,0x07);       // Size of slow_call
3528     // Push src onto stack slow-path
3529     emit_opcode(cbuf,0xD9 );      // FLD     ST(i)
3530     emit_d8    (cbuf,0xC0-1+$src$$reg );
3531     // CALL directly to the runtime
3532     cbuf.set_insts_mark();
3533     emit_opcode(cbuf,0xE8);       // Call into runtime
3534     emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3535     // Carry on here...
3536   %}
3537 
3538   enc_class FMul_ST_reg( eRegFPR src1 ) %{
3539     // Operand was loaded from memory into fp ST (stack top)
3540     // FMUL   ST,$src  /* D8 C8+i */
3541     emit_opcode(cbuf, 0xD8);
3542     emit_opcode(cbuf, 0xC8 + $src1$$reg);
3543   %}
3544 
3545   enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3546     // FADDP  ST,src2  /* D8 C0+i */
3547     emit_opcode(cbuf, 0xD8);
3548     emit_opcode(cbuf, 0xC0 + $src2$$reg);
3549     //could use FADDP  src2,fpST  /* DE C0+i */
3550   %}
3551 
3552   enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3553     // FADDP  src2,ST  /* DE C0+i */
3554     emit_opcode(cbuf, 0xDE);
3555     emit_opcode(cbuf, 0xC0 + $src2$$reg);
3556   %}
3557 
3558   enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3559     // Operand has been loaded into fp ST (stack top)
3560       // FSUB   ST,$src1
3561       emit_opcode(cbuf, 0xD8);
3562       emit_opcode(cbuf, 0xE0 + $src1$$reg);
3563 
3564       // FDIV
3565       emit_opcode(cbuf, 0xD8);
3566       emit_opcode(cbuf, 0xF0 + $src2$$reg);
3567   %}
3568 
3569   enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3570     // Operand was loaded from memory into fp ST (stack top)
3571     // FADD   ST,$src  /* D8 C0+i */
3572     emit_opcode(cbuf, 0xD8);
3573     emit_opcode(cbuf, 0xC0 + $src1$$reg);
3574 
3575     // FMUL  ST,src2  /* D8 C*+i */
3576     emit_opcode(cbuf, 0xD8);
3577     emit_opcode(cbuf, 0xC8 + $src2$$reg);
3578   %}
3579 
3580 
3581   enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3582     // Operand was loaded from memory into fp ST (stack top)
3583     // FADD   ST,$src  /* D8 C0+i */
3584     emit_opcode(cbuf, 0xD8);
3585     emit_opcode(cbuf, 0xC0 + $src1$$reg);
3586 
3587     // FMULP  src2,ST  /* DE C8+i */
3588     emit_opcode(cbuf, 0xDE);
3589     emit_opcode(cbuf, 0xC8 + $src2$$reg);
3590   %}
3591 
3592   // Atomically load the volatile long
3593   enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3594     emit_opcode(cbuf,0xDF);
3595     int rm_byte_opcode = 0x05;
3596     int base     = $mem$$base;
3597     int index    = $mem$$index;
3598     int scale    = $mem$$scale;
3599     int displace = $mem$$disp;
3600     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3601     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3602     store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3603   %}
3604 
3605   // Volatile Store Long.  Must be atomic, so move it into
3606   // the FP TOS and then do a 64-bit FIST.  Has to probe the
3607   // target address before the store (for null-ptr checks)
3608   // so the memory operand is used twice in the encoding.
3609   enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3610     store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3611     cbuf.set_insts_mark();            // Mark start of FIST in case $mem has an oop
3612     emit_opcode(cbuf,0xDF);
3613     int rm_byte_opcode = 0x07;
3614     int base     = $mem$$base;
3615     int index    = $mem$$index;
3616     int scale    = $mem$$scale;
3617     int displace = $mem$$disp;
3618     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3619     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3620   %}
3621 
3622   // Safepoint Poll.  This polls the safepoint page, and causes an
3623   // exception if it is not readable. Unfortunately, it kills the condition code
3624   // in the process
3625   // We current use TESTL [spp],EDI
3626   // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3627 
3628   enc_class Safepoint_Poll() %{
3629     cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3630     emit_opcode(cbuf,0x85);
3631     emit_rm (cbuf, 0x0, 0x7, 0x5);
3632     emit_d32(cbuf, (intptr_t)os::get_polling_page());
3633   %}
3634 %}
3635 
3636 
3637 //----------FRAME--------------------------------------------------------------
3638 // Definition of frame structure and management information.
3639 //
3640 //  S T A C K   L A Y O U T    Allocators stack-slot number
3641 //                             |   (to get allocators register number
3642 //  G  Owned by    |        |  v    add OptoReg::stack0())
3643 //  r   CALLER     |        |
3644 //  o     |        +--------+      pad to even-align allocators stack-slot
3645 //  w     V        |  pad0  |        numbers; owned by CALLER
3646 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3647 //  h     ^        |   in   |  5
3648 //        |        |  args  |  4   Holes in incoming args owned by SELF
3649 //  |     |        |        |  3
3650 //  |     |        +--------+
3651 //  V     |        | old out|      Empty on Intel, window on Sparc
3652 //        |    old |preserve|      Must be even aligned.
3653 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
3654 //        |        |   in   |  3   area for Intel ret address
3655 //     Owned by    |preserve|      Empty on Sparc.
3656 //       SELF      +--------+
3657 //        |        |  pad2  |  2   pad to align old SP
3658 //        |        +--------+  1
3659 //        |        | locks  |  0
3660 //        |        +--------+----> OptoReg::stack0(), even aligned
3661 //        |        |  pad1  | 11   pad to align new SP
3662 //        |        +--------+
3663 //        |        |        | 10
3664 //        |        | spills |  9   spills
3665 //        V        |        |  8   (pad0 slot for callee)
3666 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3667 //        ^        |  out   |  7
3668 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3669 //     Owned by    +--------+
3670 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3671 //        |    new |preserve|      Must be even-aligned.
3672 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3673 //        |        |        |
3674 //
3675 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3676 //         known from SELF's arguments and the Java calling convention.
3677 //         Region 6-7 is determined per call site.
3678 // Note 2: If the calling convention leaves holes in the incoming argument
3679 //         area, those holes are owned by SELF.  Holes in the outgoing area
3680 //         are owned by the CALLEE.  Holes should not be nessecary in the
3681 //         incoming area, as the Java calling convention is completely under
3682 //         the control of the AD file.  Doubles can be sorted and packed to
3683 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
3684 //         varargs C calling conventions.
3685 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3686 //         even aligned with pad0 as needed.
3687 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3688 //         region 6-11 is even aligned; it may be padded out more so that
3689 //         the region from SP to FP meets the minimum stack alignment.
3690 
3691 frame %{
3692   // What direction does stack grow in (assumed to be same for C & Java)
3693   stack_direction(TOWARDS_LOW);
3694 
3695   // These three registers define part of the calling convention
3696   // between compiled code and the interpreter.
3697   inline_cache_reg(EAX);                // Inline Cache Register
3698   interpreter_method_oop_reg(EBX);      // Method Oop Register when calling interpreter
3699 
3700   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3701   cisc_spilling_operand_name(indOffset32);
3702 
3703   // Number of stack slots consumed by locking an object
3704   sync_stack_slots(1);
3705 
3706   // Compiled code's Frame Pointer
3707   frame_pointer(ESP);
3708   // Interpreter stores its frame pointer in a register which is
3709   // stored to the stack by I2CAdaptors.
3710   // I2CAdaptors convert from interpreted java to compiled java.
3711   interpreter_frame_pointer(EBP);
3712 
3713   // Stack alignment requirement
3714   // Alignment size in bytes (128-bit -> 16 bytes)
3715   stack_alignment(StackAlignmentInBytes);
3716 
3717   // Number of stack slots between incoming argument block and the start of
3718   // a new frame.  The PROLOG must add this many slots to the stack.  The
3719   // EPILOG must remove this many slots.  Intel needs one slot for
3720   // return address and one for rbp, (must save rbp)
3721   in_preserve_stack_slots(2+VerifyStackAtCalls);
3722 
3723   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3724   // for calls to C.  Supports the var-args backing area for register parms.
3725   varargs_C_out_slots_killed(0);
3726 
3727   // The after-PROLOG location of the return address.  Location of
3728   // return address specifies a type (REG or STACK) and a number
3729   // representing the register number (i.e. - use a register name) or
3730   // stack slot.
3731   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3732   // Otherwise, it is above the locks and verification slot and alignment word
3733   return_addr(STACK - 1 +
3734               round_to((Compile::current()->in_preserve_stack_slots() +
3735                         Compile::current()->fixed_slots()),
3736                        stack_alignment_in_slots()));
3737 
3738   // Body of function which returns an integer array locating
3739   // arguments either in registers or in stack slots.  Passed an array
3740   // of ideal registers called "sig" and a "length" count.  Stack-slot
3741   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3742   // arguments for a CALLEE.  Incoming stack arguments are
3743   // automatically biased by the preserve_stack_slots field above.
3744   calling_convention %{
3745     // No difference between ingoing/outgoing just pass false
3746     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3747   %}
3748 
3749 
3750   // Body of function which returns an integer array locating
3751   // arguments either in registers or in stack slots.  Passed an array
3752   // of ideal registers called "sig" and a "length" count.  Stack-slot
3753   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3754   // arguments for a CALLEE.  Incoming stack arguments are
3755   // automatically biased by the preserve_stack_slots field above.
3756   c_calling_convention %{
3757     // This is obviously always outgoing
3758     (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3759   %}
3760 
3761   // Location of C & interpreter return values
3762   c_return_value %{
3763     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3764     static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num,      EAX_num,      FPR1L_num,    FPR1L_num, EAX_num };
3765     static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3766 
3767     // in SSE2+ mode we want to keep the FPU stack clean so pretend
3768     // that C functions return float and double results in XMM0.
3769     if( ideal_reg == Op_RegD && UseSSE>=2 )
3770       return OptoRegPair(XMM0b_num,XMM0_num);
3771     if( ideal_reg == Op_RegF && UseSSE>=2 )
3772       return OptoRegPair(OptoReg::Bad,XMM0_num);
3773 
3774     return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3775   %}
3776 
3777   // Location of return values
3778   return_value %{
3779     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3780     static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num,      EAX_num,      FPR1L_num,    FPR1L_num, EAX_num };
3781     static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3782     if( ideal_reg == Op_RegD && UseSSE>=2 )
3783       return OptoRegPair(XMM0b_num,XMM0_num);
3784     if( ideal_reg == Op_RegF && UseSSE>=1 )
3785       return OptoRegPair(OptoReg::Bad,XMM0_num);
3786     return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3787   %}
3788 
3789 %}
3790 
3791 //----------ATTRIBUTES---------------------------------------------------------
3792 //----------Operand Attributes-------------------------------------------------
3793 op_attrib op_cost(0);        // Required cost attribute
3794 
3795 //----------Instruction Attributes---------------------------------------------
3796 ins_attrib ins_cost(100);       // Required cost attribute
3797 ins_attrib ins_size(8);         // Required size attribute (in bits)
3798 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3799                                 // non-matching short branch variant of some
3800                                                             // long branch?
3801 ins_attrib ins_alignment(1);    // Required alignment attribute (must be a power of 2)
3802                                 // specifies the alignment that some part of the instruction (not
3803                                 // necessarily the start) requires.  If > 1, a compute_padding()
3804                                 // function must be provided for the instruction
3805 
3806 //----------OPERANDS-----------------------------------------------------------
3807 // Operand definitions must precede instruction definitions for correct parsing
3808 // in the ADLC because operands constitute user defined types which are used in
3809 // instruction definitions.
3810 
3811 //----------Simple Operands----------------------------------------------------
3812 // Immediate Operands
3813 // Integer Immediate
3814 operand immI() %{
3815   match(ConI);
3816 
3817   op_cost(10);
3818   format %{ %}
3819   interface(CONST_INTER);
3820 %}
3821 
3822 // Constant for test vs zero
3823 operand immI0() %{
3824   predicate(n->get_int() == 0);
3825   match(ConI);
3826 
3827   op_cost(0);
3828   format %{ %}
3829   interface(CONST_INTER);
3830 %}
3831 
3832 // Constant for increment
3833 operand immI1() %{
3834   predicate(n->get_int() == 1);
3835   match(ConI);
3836 
3837   op_cost(0);
3838   format %{ %}
3839   interface(CONST_INTER);
3840 %}
3841 
3842 // Constant for decrement
3843 operand immI_M1() %{
3844   predicate(n->get_int() == -1);
3845   match(ConI);
3846 
3847   op_cost(0);
3848   format %{ %}
3849   interface(CONST_INTER);
3850 %}
3851 
3852 // Valid scale values for addressing modes
3853 operand immI2() %{
3854   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3855   match(ConI);
3856 
3857   format %{ %}
3858   interface(CONST_INTER);
3859 %}
3860 
3861 operand immI8() %{
3862   predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3863   match(ConI);
3864 
3865   op_cost(5);
3866   format %{ %}
3867   interface(CONST_INTER);
3868 %}
3869 
3870 operand immI16() %{
3871   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3872   match(ConI);
3873 
3874   op_cost(10);
3875   format %{ %}
3876   interface(CONST_INTER);
3877 %}
3878 
3879 // Constant for long shifts
3880 operand immI_32() %{
3881   predicate( n->get_int() == 32 );
3882   match(ConI);
3883 
3884   op_cost(0);
3885   format %{ %}
3886   interface(CONST_INTER);
3887 %}
3888 
3889 operand immI_1_31() %{
3890   predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3891   match(ConI);
3892 
3893   op_cost(0);
3894   format %{ %}
3895   interface(CONST_INTER);
3896 %}
3897 
3898 operand immI_32_63() %{
3899   predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3900   match(ConI);
3901   op_cost(0);
3902 
3903   format %{ %}
3904   interface(CONST_INTER);
3905 %}
3906 
3907 operand immI_1() %{
3908   predicate( n->get_int() == 1 );
3909   match(ConI);
3910 
3911   op_cost(0);
3912   format %{ %}
3913   interface(CONST_INTER);
3914 %}
3915 
3916 operand immI_2() %{
3917   predicate( n->get_int() == 2 );
3918   match(ConI);
3919 
3920   op_cost(0);
3921   format %{ %}
3922   interface(CONST_INTER);
3923 %}
3924 
3925 operand immI_3() %{
3926   predicate( n->get_int() == 3 );
3927   match(ConI);
3928 
3929   op_cost(0);
3930   format %{ %}
3931   interface(CONST_INTER);
3932 %}
3933 
3934 // Pointer Immediate
3935 operand immP() %{
3936   match(ConP);
3937 
3938   op_cost(10);
3939   format %{ %}
3940   interface(CONST_INTER);
3941 %}
3942 
3943 // NULL Pointer Immediate
3944 operand immP0() %{
3945   predicate( n->get_ptr() == 0 );
3946   match(ConP);
3947   op_cost(0);
3948 
3949   format %{ %}
3950   interface(CONST_INTER);
3951 %}
3952 
3953 // Long Immediate
3954 operand immL() %{
3955   match(ConL);
3956 
3957   op_cost(20);
3958   format %{ %}
3959   interface(CONST_INTER);
3960 %}
3961 
3962 // Long Immediate zero
3963 operand immL0() %{
3964   predicate( n->get_long() == 0L );
3965   match(ConL);
3966   op_cost(0);
3967 
3968   format %{ %}
3969   interface(CONST_INTER);
3970 %}
3971 
3972 // Long Immediate zero
3973 operand immL_M1() %{
3974   predicate( n->get_long() == -1L );
3975   match(ConL);
3976   op_cost(0);
3977 
3978   format %{ %}
3979   interface(CONST_INTER);
3980 %}
3981 
3982 // Long immediate from 0 to 127.
3983 // Used for a shorter form of long mul by 10.
3984 operand immL_127() %{
3985   predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3986   match(ConL);
3987   op_cost(0);
3988 
3989   format %{ %}
3990   interface(CONST_INTER);
3991 %}
3992 
3993 // Long Immediate: low 32-bit mask
3994 operand immL_32bits() %{
3995   predicate(n->get_long() == 0xFFFFFFFFL);
3996   match(ConL);
3997   op_cost(0);
3998 
3999   format %{ %}
4000   interface(CONST_INTER);
4001 %}
4002 
4003 // Long Immediate: low 32-bit mask
4004 operand immL32() %{
4005   predicate(n->get_long() == (int)(n->get_long()));
4006   match(ConL);
4007   op_cost(20);
4008 
4009   format %{ %}
4010   interface(CONST_INTER);
4011 %}
4012 
4013 //Double Immediate zero
4014 operand immDPR0() %{
4015   // Do additional (and counter-intuitive) test against NaN to work around VC++
4016   // bug that generates code such that NaNs compare equal to 0.0
4017   predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4018   match(ConD);
4019 
4020   op_cost(5);
4021   format %{ %}
4022   interface(CONST_INTER);
4023 %}
4024 
4025 // Double Immediate one
4026 operand immDPR1() %{
4027   predicate( UseSSE<=1 && n->getd() == 1.0 );
4028   match(ConD);
4029 
4030   op_cost(5);
4031   format %{ %}
4032   interface(CONST_INTER);
4033 %}
4034 
4035 // Double Immediate
4036 operand immDPR() %{
4037   predicate(UseSSE<=1);
4038   match(ConD);
4039 
4040   op_cost(5);
4041   format %{ %}
4042   interface(CONST_INTER);
4043 %}
4044 
4045 operand immD() %{
4046   predicate(UseSSE>=2);
4047   match(ConD);
4048 
4049   op_cost(5);
4050   format %{ %}
4051   interface(CONST_INTER);
4052 %}
4053 
4054 // Double Immediate zero
4055 operand immD0() %{
4056   // Do additional (and counter-intuitive) test against NaN to work around VC++
4057   // bug that generates code such that NaNs compare equal to 0.0 AND do not
4058   // compare equal to -0.0.
4059   predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4060   match(ConD);
4061 
4062   format %{ %}
4063   interface(CONST_INTER);
4064 %}
4065 
4066 // Float Immediate zero
4067 operand immFPR0() %{
4068   predicate(UseSSE == 0 && n->getf() == 0.0F);
4069   match(ConF);
4070 
4071   op_cost(5);
4072   format %{ %}
4073   interface(CONST_INTER);
4074 %}
4075 
4076 // Float Immediate one
4077 operand immFPR1() %{
4078   predicate(UseSSE == 0 && n->getf() == 1.0F);
4079   match(ConF);
4080 
4081   op_cost(5);
4082   format %{ %}
4083   interface(CONST_INTER);
4084 %}
4085 
4086 // Float Immediate
4087 operand immFPR() %{
4088   predicate( UseSSE == 0 );
4089   match(ConF);
4090 
4091   op_cost(5);
4092   format %{ %}
4093   interface(CONST_INTER);
4094 %}
4095 
4096 // Float Immediate
4097 operand immF() %{
4098   predicate(UseSSE >= 1);
4099   match(ConF);
4100 
4101   op_cost(5);
4102   format %{ %}
4103   interface(CONST_INTER);
4104 %}
4105 
4106 // Float Immediate zero.  Zero and not -0.0
4107 operand immF0() %{
4108   predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4109   match(ConF);
4110 
4111   op_cost(5);
4112   format %{ %}
4113   interface(CONST_INTER);
4114 %}
4115 
4116 // Immediates for special shifts (sign extend)
4117 
4118 // Constants for increment
4119 operand immI_16() %{
4120   predicate( n->get_int() == 16 );
4121   match(ConI);
4122 
4123   format %{ %}
4124   interface(CONST_INTER);
4125 %}
4126 
4127 operand immI_24() %{
4128   predicate( n->get_int() == 24 );
4129   match(ConI);
4130 
4131   format %{ %}
4132   interface(CONST_INTER);
4133 %}
4134 
4135 // Constant for byte-wide masking
4136 operand immI_255() %{
4137   predicate( n->get_int() == 255 );
4138   match(ConI);
4139 
4140   format %{ %}
4141   interface(CONST_INTER);
4142 %}
4143 
4144 // Constant for short-wide masking
4145 operand immI_65535() %{
4146   predicate(n->get_int() == 65535);
4147   match(ConI);
4148 
4149   format %{ %}
4150   interface(CONST_INTER);
4151 %}
4152 
4153 // Register Operands
4154 // Integer Register
4155 operand rRegI() %{
4156   constraint(ALLOC_IN_RC(int_reg));
4157   match(RegI);
4158   match(xRegI);
4159   match(eAXRegI);
4160   match(eBXRegI);
4161   match(eCXRegI);
4162   match(eDXRegI);
4163   match(eDIRegI);
4164   match(eSIRegI);
4165 
4166   format %{ %}
4167   interface(REG_INTER);
4168 %}
4169 
4170 // Subset of Integer Register
4171 operand xRegI(rRegI reg) %{
4172   constraint(ALLOC_IN_RC(int_x_reg));
4173   match(reg);
4174   match(eAXRegI);
4175   match(eBXRegI);
4176   match(eCXRegI);
4177   match(eDXRegI);
4178 
4179   format %{ %}
4180   interface(REG_INTER);
4181 %}
4182 
4183 // Special Registers
4184 operand eAXRegI(xRegI reg) %{
4185   constraint(ALLOC_IN_RC(eax_reg));
4186   match(reg);
4187   match(rRegI);
4188 
4189   format %{ "EAX" %}
4190   interface(REG_INTER);
4191 %}
4192 
4193 // Special Registers
4194 operand eBXRegI(xRegI reg) %{
4195   constraint(ALLOC_IN_RC(ebx_reg));
4196   match(reg);
4197   match(rRegI);
4198 
4199   format %{ "EBX" %}
4200   interface(REG_INTER);
4201 %}
4202 
4203 operand eCXRegI(xRegI reg) %{
4204   constraint(ALLOC_IN_RC(ecx_reg));
4205   match(reg);
4206   match(rRegI);
4207 
4208   format %{ "ECX" %}
4209   interface(REG_INTER);
4210 %}
4211 
4212 operand eDXRegI(xRegI reg) %{
4213   constraint(ALLOC_IN_RC(edx_reg));
4214   match(reg);
4215   match(rRegI);
4216 
4217   format %{ "EDX" %}
4218   interface(REG_INTER);
4219 %}
4220 
4221 operand eDIRegI(xRegI reg) %{
4222   constraint(ALLOC_IN_RC(edi_reg));
4223   match(reg);
4224   match(rRegI);
4225 
4226   format %{ "EDI" %}
4227   interface(REG_INTER);
4228 %}
4229 
4230 operand naxRegI() %{
4231   constraint(ALLOC_IN_RC(nax_reg));
4232   match(RegI);
4233   match(eCXRegI);
4234   match(eDXRegI);
4235   match(eSIRegI);
4236   match(eDIRegI);
4237 
4238   format %{ %}
4239   interface(REG_INTER);
4240 %}
4241 
4242 operand nadxRegI() %{
4243   constraint(ALLOC_IN_RC(nadx_reg));
4244   match(RegI);
4245   match(eBXRegI);
4246   match(eCXRegI);
4247   match(eSIRegI);
4248   match(eDIRegI);
4249 
4250   format %{ %}
4251   interface(REG_INTER);
4252 %}
4253 
4254 operand ncxRegI() %{
4255   constraint(ALLOC_IN_RC(ncx_reg));
4256   match(RegI);
4257   match(eAXRegI);
4258   match(eDXRegI);
4259   match(eSIRegI);
4260   match(eDIRegI);
4261 
4262   format %{ %}
4263   interface(REG_INTER);
4264 %}
4265 
4266 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4267 // //
4268 operand eSIRegI(xRegI reg) %{
4269    constraint(ALLOC_IN_RC(esi_reg));
4270    match(reg);
4271    match(rRegI);
4272 
4273    format %{ "ESI" %}
4274    interface(REG_INTER);
4275 %}
4276 
4277 // Pointer Register
4278 operand anyRegP() %{
4279   constraint(ALLOC_IN_RC(any_reg));
4280   match(RegP);
4281   match(eAXRegP);
4282   match(eBXRegP);
4283   match(eCXRegP);
4284   match(eDIRegP);
4285   match(eRegP);
4286 
4287   format %{ %}
4288   interface(REG_INTER);
4289 %}
4290 
4291 operand eRegP() %{
4292   constraint(ALLOC_IN_RC(int_reg));
4293   match(RegP);
4294   match(eAXRegP);
4295   match(eBXRegP);
4296   match(eCXRegP);
4297   match(eDIRegP);
4298 
4299   format %{ %}
4300   interface(REG_INTER);
4301 %}
4302 
4303 // On windows95, EBP is not safe to use for implicit null tests.
4304 operand eRegP_no_EBP() %{
4305   constraint(ALLOC_IN_RC(int_reg_no_rbp));
4306   match(RegP);
4307   match(eAXRegP);
4308   match(eBXRegP);
4309   match(eCXRegP);
4310   match(eDIRegP);
4311 
4312   op_cost(100);
4313   format %{ %}
4314   interface(REG_INTER);
4315 %}
4316 
4317 operand naxRegP() %{
4318   constraint(ALLOC_IN_RC(nax_reg));
4319   match(RegP);
4320   match(eBXRegP);
4321   match(eDXRegP);
4322   match(eCXRegP);
4323   match(eSIRegP);
4324   match(eDIRegP);
4325 
4326   format %{ %}
4327   interface(REG_INTER);
4328 %}
4329 
4330 operand nabxRegP() %{
4331   constraint(ALLOC_IN_RC(nabx_reg));
4332   match(RegP);
4333   match(eCXRegP);
4334   match(eDXRegP);
4335   match(eSIRegP);
4336   match(eDIRegP);
4337 
4338   format %{ %}
4339   interface(REG_INTER);
4340 %}
4341 
4342 operand pRegP() %{
4343   constraint(ALLOC_IN_RC(p_reg));
4344   match(RegP);
4345   match(eBXRegP);
4346   match(eDXRegP);
4347   match(eSIRegP);
4348   match(eDIRegP);
4349 
4350   format %{ %}
4351   interface(REG_INTER);
4352 %}
4353 
4354 // Special Registers
4355 // Return a pointer value
4356 operand eAXRegP(eRegP reg) %{
4357   constraint(ALLOC_IN_RC(eax_reg));
4358   match(reg);
4359   format %{ "EAX" %}
4360   interface(REG_INTER);
4361 %}
4362 
4363 // Used in AtomicAdd
4364 operand eBXRegP(eRegP reg) %{
4365   constraint(ALLOC_IN_RC(ebx_reg));
4366   match(reg);
4367   format %{ "EBX" %}
4368   interface(REG_INTER);
4369 %}
4370 
4371 // Tail-call (interprocedural jump) to interpreter
4372 operand eCXRegP(eRegP reg) %{
4373   constraint(ALLOC_IN_RC(ecx_reg));
4374   match(reg);
4375   format %{ "ECX" %}
4376   interface(REG_INTER);
4377 %}
4378 
4379 operand eSIRegP(eRegP reg) %{
4380   constraint(ALLOC_IN_RC(esi_reg));
4381   match(reg);
4382   format %{ "ESI" %}
4383   interface(REG_INTER);
4384 %}
4385 
4386 // Used in rep stosw
4387 operand eDIRegP(eRegP reg) %{
4388   constraint(ALLOC_IN_RC(edi_reg));
4389   match(reg);
4390   format %{ "EDI" %}
4391   interface(REG_INTER);
4392 %}
4393 
4394 operand eBPRegP() %{
4395   constraint(ALLOC_IN_RC(ebp_reg));
4396   match(RegP);
4397   format %{ "EBP" %}
4398   interface(REG_INTER);
4399 %}
4400 
4401 operand eRegL() %{
4402   constraint(ALLOC_IN_RC(long_reg));
4403   match(RegL);
4404   match(eADXRegL);
4405 
4406   format %{ %}
4407   interface(REG_INTER);
4408 %}
4409 
4410 operand eADXRegL( eRegL reg ) %{
4411   constraint(ALLOC_IN_RC(eadx_reg));
4412   match(reg);
4413 
4414   format %{ "EDX:EAX" %}
4415   interface(REG_INTER);
4416 %}
4417 
4418 operand eBCXRegL( eRegL reg ) %{
4419   constraint(ALLOC_IN_RC(ebcx_reg));
4420   match(reg);
4421 
4422   format %{ "EBX:ECX" %}
4423   interface(REG_INTER);
4424 %}
4425 
4426 // Special case for integer high multiply
4427 operand eADXRegL_low_only() %{
4428   constraint(ALLOC_IN_RC(eadx_reg));
4429   match(RegL);
4430 
4431   format %{ "EAX" %}
4432   interface(REG_INTER);
4433 %}
4434 
4435 // Flags register, used as output of compare instructions
4436 operand eFlagsReg() %{
4437   constraint(ALLOC_IN_RC(int_flags));
4438   match(RegFlags);
4439 
4440   format %{ "EFLAGS" %}
4441   interface(REG_INTER);
4442 %}
4443 
4444 // Flags register, used as output of FLOATING POINT compare instructions
4445 operand eFlagsRegU() %{
4446   constraint(ALLOC_IN_RC(int_flags));
4447   match(RegFlags);
4448 
4449   format %{ "EFLAGS_U" %}
4450   interface(REG_INTER);
4451 %}
4452 
4453 operand eFlagsRegUCF() %{
4454   constraint(ALLOC_IN_RC(int_flags));
4455   match(RegFlags);
4456   predicate(false);
4457 
4458   format %{ "EFLAGS_U_CF" %}
4459   interface(REG_INTER);
4460 %}
4461 
4462 // Condition Code Register used by long compare
4463 operand flagsReg_long_LTGE() %{
4464   constraint(ALLOC_IN_RC(int_flags));
4465   match(RegFlags);
4466   format %{ "FLAGS_LTGE" %}
4467   interface(REG_INTER);
4468 %}
4469 operand flagsReg_long_EQNE() %{
4470   constraint(ALLOC_IN_RC(int_flags));
4471   match(RegFlags);
4472   format %{ "FLAGS_EQNE" %}
4473   interface(REG_INTER);
4474 %}
4475 operand flagsReg_long_LEGT() %{
4476   constraint(ALLOC_IN_RC(int_flags));
4477   match(RegFlags);
4478   format %{ "FLAGS_LEGT" %}
4479   interface(REG_INTER);
4480 %}
4481 
4482 // Float register operands
4483 operand regDPR() %{
4484   predicate( UseSSE < 2 );
4485   constraint(ALLOC_IN_RC(fp_dbl_reg));
4486   match(RegD);
4487   match(regDPR1);
4488   match(regDPR2);
4489   format %{ %}
4490   interface(REG_INTER);
4491 %}
4492 
4493 operand regDPR1(regDPR reg) %{
4494   predicate( UseSSE < 2 );
4495   constraint(ALLOC_IN_RC(fp_dbl_reg0));
4496   match(reg);
4497   format %{ "FPR1" %}
4498   interface(REG_INTER);
4499 %}
4500 
4501 operand regDPR2(regDPR reg) %{
4502   predicate( UseSSE < 2 );
4503   constraint(ALLOC_IN_RC(fp_dbl_reg1));
4504   match(reg);
4505   format %{ "FPR2" %}
4506   interface(REG_INTER);
4507 %}
4508 
4509 operand regnotDPR1(regDPR reg) %{
4510   predicate( UseSSE < 2 );
4511   constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4512   match(reg);
4513   format %{ %}
4514   interface(REG_INTER);
4515 %}
4516 
4517 // Float register operands
4518 operand regFPR() %{
4519   predicate( UseSSE < 2 );
4520   constraint(ALLOC_IN_RC(fp_flt_reg));
4521   match(RegF);
4522   match(regFPR1);
4523   format %{ %}
4524   interface(REG_INTER);
4525 %}
4526 
4527 // Float register operands
4528 operand regFPR1(regFPR reg) %{
4529   predicate( UseSSE < 2 );
4530   constraint(ALLOC_IN_RC(fp_flt_reg0));
4531   match(reg);
4532   format %{ "FPR1" %}
4533   interface(REG_INTER);
4534 %}
4535 
4536 // XMM Float register operands
4537 operand regF() %{
4538   predicate( UseSSE>=1 );
4539   constraint(ALLOC_IN_RC(float_reg));
4540   match(RegF);
4541   format %{ %}
4542   interface(REG_INTER);
4543 %}
4544 
4545 // XMM Double register operands
4546 operand regD() %{
4547   predicate( UseSSE>=2 );
4548   constraint(ALLOC_IN_RC(double_reg));
4549   match(RegD);
4550   format %{ %}
4551   interface(REG_INTER);
4552 %}
4553 
4554 
4555 //----------Memory Operands----------------------------------------------------
4556 // Direct Memory Operand
4557 operand direct(immP addr) %{
4558   match(addr);
4559 
4560   format %{ "[$addr]" %}
4561   interface(MEMORY_INTER) %{
4562     base(0xFFFFFFFF);
4563     index(0x4);
4564     scale(0x0);
4565     disp($addr);
4566   %}
4567 %}
4568 
4569 // Indirect Memory Operand
4570 operand indirect(eRegP reg) %{
4571   constraint(ALLOC_IN_RC(int_reg));
4572   match(reg);
4573 
4574   format %{ "[$reg]" %}
4575   interface(MEMORY_INTER) %{
4576     base($reg);
4577     index(0x4);
4578     scale(0x0);
4579     disp(0x0);
4580   %}
4581 %}
4582 
4583 // Indirect Memory Plus Short Offset Operand
4584 operand indOffset8(eRegP reg, immI8 off) %{
4585   match(AddP reg off);
4586 
4587   format %{ "[$reg + $off]" %}
4588   interface(MEMORY_INTER) %{
4589     base($reg);
4590     index(0x4);
4591     scale(0x0);
4592     disp($off);
4593   %}
4594 %}
4595 
4596 // Indirect Memory Plus Long Offset Operand
4597 operand indOffset32(eRegP reg, immI off) %{
4598   match(AddP reg off);
4599 
4600   format %{ "[$reg + $off]" %}
4601   interface(MEMORY_INTER) %{
4602     base($reg);
4603     index(0x4);
4604     scale(0x0);
4605     disp($off);
4606   %}
4607 %}
4608 
4609 // Indirect Memory Plus Long Offset Operand
4610 operand indOffset32X(rRegI reg, immP off) %{
4611   match(AddP off reg);
4612 
4613   format %{ "[$reg + $off]" %}
4614   interface(MEMORY_INTER) %{
4615     base($reg);
4616     index(0x4);
4617     scale(0x0);
4618     disp($off);
4619   %}
4620 %}
4621 
4622 // Indirect Memory Plus Index Register Plus Offset Operand
4623 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4624   match(AddP (AddP reg ireg) off);
4625 
4626   op_cost(10);
4627   format %{"[$reg + $off + $ireg]" %}
4628   interface(MEMORY_INTER) %{
4629     base($reg);
4630     index($ireg);
4631     scale(0x0);
4632     disp($off);
4633   %}
4634 %}
4635 
4636 // Indirect Memory Plus Index Register Plus Offset Operand
4637 operand indIndex(eRegP reg, rRegI ireg) %{
4638   match(AddP reg ireg);
4639 
4640   op_cost(10);
4641   format %{"[$reg + $ireg]" %}
4642   interface(MEMORY_INTER) %{
4643     base($reg);
4644     index($ireg);
4645     scale(0x0);
4646     disp(0x0);
4647   %}
4648 %}
4649 
4650 // // -------------------------------------------------------------------------
4651 // // 486 architecture doesn't support "scale * index + offset" with out a base
4652 // // -------------------------------------------------------------------------
4653 // // Scaled Memory Operands
4654 // // Indirect Memory Times Scale Plus Offset Operand
4655 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4656 //   match(AddP off (LShiftI ireg scale));
4657 //
4658 //   op_cost(10);
4659 //   format %{"[$off + $ireg << $scale]" %}
4660 //   interface(MEMORY_INTER) %{
4661 //     base(0x4);
4662 //     index($ireg);
4663 //     scale($scale);
4664 //     disp($off);
4665 //   %}
4666 // %}
4667 
4668 // Indirect Memory Times Scale Plus Index Register
4669 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4670   match(AddP reg (LShiftI ireg scale));
4671 
4672   op_cost(10);
4673   format %{"[$reg + $ireg << $scale]" %}
4674   interface(MEMORY_INTER) %{
4675     base($reg);
4676     index($ireg);
4677     scale($scale);
4678     disp(0x0);
4679   %}
4680 %}
4681 
4682 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4683 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4684   match(AddP (AddP reg (LShiftI ireg scale)) off);
4685 
4686   op_cost(10);
4687   format %{"[$reg + $off + $ireg << $scale]" %}
4688   interface(MEMORY_INTER) %{
4689     base($reg);
4690     index($ireg);
4691     scale($scale);
4692     disp($off);
4693   %}
4694 %}
4695 
4696 //----------Load Long Memory Operands------------------------------------------
4697 // The load-long idiom will use it's address expression again after loading
4698 // the first word of the long.  If the load-long destination overlaps with
4699 // registers used in the addressing expression, the 2nd half will be loaded
4700 // from a clobbered address.  Fix this by requiring that load-long use
4701 // address registers that do not overlap with the load-long target.
4702 
4703 // load-long support
4704 operand load_long_RegP() %{
4705   constraint(ALLOC_IN_RC(esi_reg));
4706   match(RegP);
4707   match(eSIRegP);
4708   op_cost(100);
4709   format %{  %}
4710   interface(REG_INTER);
4711 %}
4712 
4713 // Indirect Memory Operand Long
4714 operand load_long_indirect(load_long_RegP reg) %{
4715   constraint(ALLOC_IN_RC(esi_reg));
4716   match(reg);
4717 
4718   format %{ "[$reg]" %}
4719   interface(MEMORY_INTER) %{
4720     base($reg);
4721     index(0x4);
4722     scale(0x0);
4723     disp(0x0);
4724   %}
4725 %}
4726 
4727 // Indirect Memory Plus Long Offset Operand
4728 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4729   match(AddP reg off);
4730 
4731   format %{ "[$reg + $off]" %}
4732   interface(MEMORY_INTER) %{
4733     base($reg);
4734     index(0x4);
4735     scale(0x0);
4736     disp($off);
4737   %}
4738 %}
4739 
4740 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4741 
4742 
4743 //----------Special Memory Operands--------------------------------------------
4744 // Stack Slot Operand - This operand is used for loading and storing temporary
4745 //                      values on the stack where a match requires a value to
4746 //                      flow through memory.
4747 operand stackSlotP(sRegP reg) %{
4748   constraint(ALLOC_IN_RC(stack_slots));
4749   // No match rule because this operand is only generated in matching
4750   format %{ "[$reg]" %}
4751   interface(MEMORY_INTER) %{
4752     base(0x4);   // ESP
4753     index(0x4);  // No Index
4754     scale(0x0);  // No Scale
4755     disp($reg);  // Stack Offset
4756   %}
4757 %}
4758 
4759 operand stackSlotI(sRegI reg) %{
4760   constraint(ALLOC_IN_RC(stack_slots));
4761   // No match rule because this operand is only generated in matching
4762   format %{ "[$reg]" %}
4763   interface(MEMORY_INTER) %{
4764     base(0x4);   // ESP
4765     index(0x4);  // No Index
4766     scale(0x0);  // No Scale
4767     disp($reg);  // Stack Offset
4768   %}
4769 %}
4770 
4771 operand stackSlotF(sRegF reg) %{
4772   constraint(ALLOC_IN_RC(stack_slots));
4773   // No match rule because this operand is only generated in matching
4774   format %{ "[$reg]" %}
4775   interface(MEMORY_INTER) %{
4776     base(0x4);   // ESP
4777     index(0x4);  // No Index
4778     scale(0x0);  // No Scale
4779     disp($reg);  // Stack Offset
4780   %}
4781 %}
4782 
4783 operand stackSlotD(sRegD reg) %{
4784   constraint(ALLOC_IN_RC(stack_slots));
4785   // No match rule because this operand is only generated in matching
4786   format %{ "[$reg]" %}
4787   interface(MEMORY_INTER) %{
4788     base(0x4);   // ESP
4789     index(0x4);  // No Index
4790     scale(0x0);  // No Scale
4791     disp($reg);  // Stack Offset
4792   %}
4793 %}
4794 
4795 operand stackSlotL(sRegL reg) %{
4796   constraint(ALLOC_IN_RC(stack_slots));
4797   // No match rule because this operand is only generated in matching
4798   format %{ "[$reg]" %}
4799   interface(MEMORY_INTER) %{
4800     base(0x4);   // ESP
4801     index(0x4);  // No Index
4802     scale(0x0);  // No Scale
4803     disp($reg);  // Stack Offset
4804   %}
4805 %}
4806 
4807 //----------Memory Operands - Win95 Implicit Null Variants----------------
4808 // Indirect Memory Operand
4809 operand indirect_win95_safe(eRegP_no_EBP reg)
4810 %{
4811   constraint(ALLOC_IN_RC(int_reg));
4812   match(reg);
4813 
4814   op_cost(100);
4815   format %{ "[$reg]" %}
4816   interface(MEMORY_INTER) %{
4817     base($reg);
4818     index(0x4);
4819     scale(0x0);
4820     disp(0x0);
4821   %}
4822 %}
4823 
4824 // Indirect Memory Plus Short Offset Operand
4825 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4826 %{
4827   match(AddP reg off);
4828 
4829   op_cost(100);
4830   format %{ "[$reg + $off]" %}
4831   interface(MEMORY_INTER) %{
4832     base($reg);
4833     index(0x4);
4834     scale(0x0);
4835     disp($off);
4836   %}
4837 %}
4838 
4839 // Indirect Memory Plus Long Offset Operand
4840 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4841 %{
4842   match(AddP reg off);
4843 
4844   op_cost(100);
4845   format %{ "[$reg + $off]" %}
4846   interface(MEMORY_INTER) %{
4847     base($reg);
4848     index(0x4);
4849     scale(0x0);
4850     disp($off);
4851   %}
4852 %}
4853 
4854 // Indirect Memory Plus Index Register Plus Offset Operand
4855 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4856 %{
4857   match(AddP (AddP reg ireg) off);
4858 
4859   op_cost(100);
4860   format %{"[$reg + $off + $ireg]" %}
4861   interface(MEMORY_INTER) %{
4862     base($reg);
4863     index($ireg);
4864     scale(0x0);
4865     disp($off);
4866   %}
4867 %}
4868 
4869 // Indirect Memory Times Scale Plus Index Register
4870 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4871 %{
4872   match(AddP reg (LShiftI ireg scale));
4873 
4874   op_cost(100);
4875   format %{"[$reg + $ireg << $scale]" %}
4876   interface(MEMORY_INTER) %{
4877     base($reg);
4878     index($ireg);
4879     scale($scale);
4880     disp(0x0);
4881   %}
4882 %}
4883 
4884 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4885 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4886 %{
4887   match(AddP (AddP reg (LShiftI ireg scale)) off);
4888 
4889   op_cost(100);
4890   format %{"[$reg + $off + $ireg << $scale]" %}
4891   interface(MEMORY_INTER) %{
4892     base($reg);
4893     index($ireg);
4894     scale($scale);
4895     disp($off);
4896   %}
4897 %}
4898 
4899 //----------Conditional Branch Operands----------------------------------------
4900 // Comparison Op  - This is the operation of the comparison, and is limited to
4901 //                  the following set of codes:
4902 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4903 //
4904 // Other attributes of the comparison, such as unsignedness, are specified
4905 // by the comparison instruction that sets a condition code flags register.
4906 // That result is represented by a flags operand whose subtype is appropriate
4907 // to the unsignedness (etc.) of the comparison.
4908 //
4909 // Later, the instruction which matches both the Comparison Op (a Bool) and
4910 // the flags (produced by the Cmp) specifies the coding of the comparison op
4911 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4912 
4913 // Comparision Code
4914 operand cmpOp() %{
4915   match(Bool);
4916 
4917   format %{ "" %}
4918   interface(COND_INTER) %{
4919     equal(0x4, "e");
4920     not_equal(0x5, "ne");
4921     less(0xC, "l");
4922     greater_equal(0xD, "ge");
4923     less_equal(0xE, "le");
4924     greater(0xF, "g");
4925   %}
4926 %}
4927 
4928 // Comparison Code, unsigned compare.  Used by FP also, with
4929 // C2 (unordered) turned into GT or LT already.  The other bits
4930 // C0 and C3 are turned into Carry & Zero flags.
4931 operand cmpOpU() %{
4932   match(Bool);
4933 
4934   format %{ "" %}
4935   interface(COND_INTER) %{
4936     equal(0x4, "e");
4937     not_equal(0x5, "ne");
4938     less(0x2, "b");
4939     greater_equal(0x3, "nb");
4940     less_equal(0x6, "be");
4941     greater(0x7, "nbe");
4942   %}
4943 %}
4944 
4945 // Floating comparisons that don't require any fixup for the unordered case
4946 operand cmpOpUCF() %{
4947   match(Bool);
4948   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4949             n->as_Bool()->_test._test == BoolTest::ge ||
4950             n->as_Bool()->_test._test == BoolTest::le ||
4951             n->as_Bool()->_test._test == BoolTest::gt);
4952   format %{ "" %}
4953   interface(COND_INTER) %{
4954     equal(0x4, "e");
4955     not_equal(0x5, "ne");
4956     less(0x2, "b");
4957     greater_equal(0x3, "nb");
4958     less_equal(0x6, "be");
4959     greater(0x7, "nbe");
4960   %}
4961 %}
4962 
4963 
4964 // Floating comparisons that can be fixed up with extra conditional jumps
4965 operand cmpOpUCF2() %{
4966   match(Bool);
4967   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4968             n->as_Bool()->_test._test == BoolTest::eq);
4969   format %{ "" %}
4970   interface(COND_INTER) %{
4971     equal(0x4, "e");
4972     not_equal(0x5, "ne");
4973     less(0x2, "b");
4974     greater_equal(0x3, "nb");
4975     less_equal(0x6, "be");
4976     greater(0x7, "nbe");
4977   %}
4978 %}
4979 
4980 // Comparison Code for FP conditional move
4981 operand cmpOp_fcmov() %{
4982   match(Bool);
4983 
4984   format %{ "" %}
4985   interface(COND_INTER) %{
4986     equal        (0x0C8);
4987     not_equal    (0x1C8);
4988     less         (0x0C0);
4989     greater_equal(0x1C0);
4990     less_equal   (0x0D0);
4991     greater      (0x1D0);
4992   %}
4993 %}
4994 
4995 // Comparision Code used in long compares
4996 operand cmpOp_commute() %{
4997   match(Bool);
4998 
4999   format %{ "" %}
5000   interface(COND_INTER) %{
5001     equal(0x4, "e");
5002     not_equal(0x5, "ne");
5003     less(0xF, "g");
5004     greater_equal(0xE, "le");
5005     less_equal(0xD, "ge");
5006     greater(0xC, "l");
5007   %}
5008 %}
5009 
5010 //----------OPERAND CLASSES----------------------------------------------------
5011 // Operand Classes are groups of operands that are used as to simplify
5012 // instruction definitions by not requiring the AD writer to specify separate
5013 // instructions for every form of operand when the instruction accepts
5014 // multiple operand types with the same basic encoding and format.  The classic
5015 // case of this is memory operands.
5016 
5017 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5018                indIndex, indIndexScale, indIndexScaleOffset);
5019 
5020 // Long memory operations are encoded in 2 instructions and a +4 offset.
5021 // This means some kind of offset is always required and you cannot use
5022 // an oop as the offset (done when working on static globals).
5023 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5024                     indIndex, indIndexScale, indIndexScaleOffset);
5025 
5026 
5027 //----------PIPELINE-----------------------------------------------------------
5028 // Rules which define the behavior of the target architectures pipeline.
5029 pipeline %{
5030 
5031 //----------ATTRIBUTES---------------------------------------------------------
5032 attributes %{
5033   variable_size_instructions;        // Fixed size instructions
5034   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
5035   instruction_unit_size = 1;         // An instruction is 1 bytes long
5036   instruction_fetch_unit_size = 16;  // The processor fetches one line
5037   instruction_fetch_units = 1;       // of 16 bytes
5038 
5039   // List of nop instructions
5040   nops( MachNop );
5041 %}
5042 
5043 //----------RESOURCES----------------------------------------------------------
5044 // Resources are the functional units available to the machine
5045 
5046 // Generic P2/P3 pipeline
5047 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5048 // 3 instructions decoded per cycle.
5049 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5050 // 2 ALU op, only ALU0 handles mul/div instructions.
5051 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5052            MS0, MS1, MEM = MS0 | MS1,
5053            BR, FPU,
5054            ALU0, ALU1, ALU = ALU0 | ALU1 );
5055 
5056 //----------PIPELINE DESCRIPTION-----------------------------------------------
5057 // Pipeline Description specifies the stages in the machine's pipeline
5058 
5059 // Generic P2/P3 pipeline
5060 pipe_desc(S0, S1, S2, S3, S4, S5);
5061 
5062 //----------PIPELINE CLASSES---------------------------------------------------
5063 // Pipeline Classes describe the stages in which input and output are
5064 // referenced by the hardware pipeline.
5065 
5066 // Naming convention: ialu or fpu
5067 // Then: _reg
5068 // Then: _reg if there is a 2nd register
5069 // Then: _long if it's a pair of instructions implementing a long
5070 // Then: _fat if it requires the big decoder
5071 //   Or: _mem if it requires the big decoder and a memory unit.
5072 
5073 // Integer ALU reg operation
5074 pipe_class ialu_reg(rRegI dst) %{
5075     single_instruction;
5076     dst    : S4(write);
5077     dst    : S3(read);
5078     DECODE : S0;        // any decoder
5079     ALU    : S3;        // any alu
5080 %}
5081 
5082 // Long ALU reg operation
5083 pipe_class ialu_reg_long(eRegL dst) %{
5084     instruction_count(2);
5085     dst    : S4(write);
5086     dst    : S3(read);
5087     DECODE : S0(2);     // any 2 decoders
5088     ALU    : S3(2);     // both alus
5089 %}
5090 
5091 // Integer ALU reg operation using big decoder
5092 pipe_class ialu_reg_fat(rRegI dst) %{
5093     single_instruction;
5094     dst    : S4(write);
5095     dst    : S3(read);
5096     D0     : S0;        // big decoder only
5097     ALU    : S3;        // any alu
5098 %}
5099 
5100 // Long ALU reg operation using big decoder
5101 pipe_class ialu_reg_long_fat(eRegL dst) %{
5102     instruction_count(2);
5103     dst    : S4(write);
5104     dst    : S3(read);
5105     D0     : S0(2);     // big decoder only; twice
5106     ALU    : S3(2);     // any 2 alus
5107 %}
5108 
5109 // Integer ALU reg-reg operation
5110 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5111     single_instruction;
5112     dst    : S4(write);
5113     src    : S3(read);
5114     DECODE : S0;        // any decoder
5115     ALU    : S3;        // any alu
5116 %}
5117 
5118 // Long ALU reg-reg operation
5119 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5120     instruction_count(2);
5121     dst    : S4(write);
5122     src    : S3(read);
5123     DECODE : S0(2);     // any 2 decoders
5124     ALU    : S3(2);     // both alus
5125 %}
5126 
5127 // Integer ALU reg-reg operation
5128 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5129     single_instruction;
5130     dst    : S4(write);
5131     src    : S3(read);
5132     D0     : S0;        // big decoder only
5133     ALU    : S3;        // any alu
5134 %}
5135 
5136 // Long ALU reg-reg operation
5137 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5138     instruction_count(2);
5139     dst    : S4(write);
5140     src    : S3(read);
5141     D0     : S0(2);     // big decoder only; twice
5142     ALU    : S3(2);     // both alus
5143 %}
5144 
5145 // Integer ALU reg-mem operation
5146 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5147     single_instruction;
5148     dst    : S5(write);
5149     mem    : S3(read);
5150     D0     : S0;        // big decoder only
5151     ALU    : S4;        // any alu
5152     MEM    : S3;        // any mem
5153 %}
5154 
5155 // Long ALU reg-mem operation
5156 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5157     instruction_count(2);
5158     dst    : S5(write);
5159     mem    : S3(read);
5160     D0     : S0(2);     // big decoder only; twice
5161     ALU    : S4(2);     // any 2 alus
5162     MEM    : S3(2);     // both mems
5163 %}
5164 
5165 // Integer mem operation (prefetch)
5166 pipe_class ialu_mem(memory mem)
5167 %{
5168     single_instruction;
5169     mem    : S3(read);
5170     D0     : S0;        // big decoder only
5171     MEM    : S3;        // any mem
5172 %}
5173 
5174 // Integer Store to Memory
5175 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5176     single_instruction;
5177     mem    : S3(read);
5178     src    : S5(read);
5179     D0     : S0;        // big decoder only
5180     ALU    : S4;        // any alu
5181     MEM    : S3;
5182 %}
5183 
5184 // Long Store to Memory
5185 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5186     instruction_count(2);
5187     mem    : S3(read);
5188     src    : S5(read);
5189     D0     : S0(2);     // big decoder only; twice
5190     ALU    : S4(2);     // any 2 alus
5191     MEM    : S3(2);     // Both mems
5192 %}
5193 
5194 // Integer Store to Memory
5195 pipe_class ialu_mem_imm(memory mem) %{
5196     single_instruction;
5197     mem    : S3(read);
5198     D0     : S0;        // big decoder only
5199     ALU    : S4;        // any alu
5200     MEM    : S3;
5201 %}
5202 
5203 // Integer ALU0 reg-reg operation
5204 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5205     single_instruction;
5206     dst    : S4(write);
5207     src    : S3(read);
5208     D0     : S0;        // Big decoder only
5209     ALU0   : S3;        // only alu0
5210 %}
5211 
5212 // Integer ALU0 reg-mem operation
5213 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5214     single_instruction;
5215     dst    : S5(write);
5216     mem    : S3(read);
5217     D0     : S0;        // big decoder only
5218     ALU0   : S4;        // ALU0 only
5219     MEM    : S3;        // any mem
5220 %}
5221 
5222 // Integer ALU reg-reg operation
5223 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5224     single_instruction;
5225     cr     : S4(write);
5226     src1   : S3(read);
5227     src2   : S3(read);
5228     DECODE : S0;        // any decoder
5229     ALU    : S3;        // any alu
5230 %}
5231 
5232 // Integer ALU reg-imm operation
5233 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5234     single_instruction;
5235     cr     : S4(write);
5236     src1   : S3(read);
5237     DECODE : S0;        // any decoder
5238     ALU    : S3;        // any alu
5239 %}
5240 
5241 // Integer ALU reg-mem operation
5242 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5243     single_instruction;
5244     cr     : S4(write);
5245     src1   : S3(read);
5246     src2   : S3(read);
5247     D0     : S0;        // big decoder only
5248     ALU    : S4;        // any alu
5249     MEM    : S3;
5250 %}
5251 
5252 // Conditional move reg-reg
5253 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5254     instruction_count(4);
5255     y      : S4(read);
5256     q      : S3(read);
5257     p      : S3(read);
5258     DECODE : S0(4);     // any decoder
5259 %}
5260 
5261 // Conditional move reg-reg
5262 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5263     single_instruction;
5264     dst    : S4(write);
5265     src    : S3(read);
5266     cr     : S3(read);
5267     DECODE : S0;        // any decoder
5268 %}
5269 
5270 // Conditional move reg-mem
5271 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5272     single_instruction;
5273     dst    : S4(write);
5274     src    : S3(read);
5275     cr     : S3(read);
5276     DECODE : S0;        // any decoder
5277     MEM    : S3;
5278 %}
5279 
5280 // Conditional move reg-reg long
5281 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5282     single_instruction;
5283     dst    : S4(write);
5284     src    : S3(read);
5285     cr     : S3(read);
5286     DECODE : S0(2);     // any 2 decoders
5287 %}
5288 
5289 // Conditional move double reg-reg
5290 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5291     single_instruction;
5292     dst    : S4(write);
5293     src    : S3(read);
5294     cr     : S3(read);
5295     DECODE : S0;        // any decoder
5296 %}
5297 
5298 // Float reg-reg operation
5299 pipe_class fpu_reg(regDPR dst) %{
5300     instruction_count(2);
5301     dst    : S3(read);
5302     DECODE : S0(2);     // any 2 decoders
5303     FPU    : S3;
5304 %}
5305 
5306 // Float reg-reg operation
5307 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5308     instruction_count(2);
5309     dst    : S4(write);
5310     src    : S3(read);
5311     DECODE : S0(2);     // any 2 decoders
5312     FPU    : S3;
5313 %}
5314 
5315 // Float reg-reg operation
5316 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5317     instruction_count(3);
5318     dst    : S4(write);
5319     src1   : S3(read);
5320     src2   : S3(read);
5321     DECODE : S0(3);     // any 3 decoders
5322     FPU    : S3(2);
5323 %}
5324 
5325 // Float reg-reg operation
5326 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5327     instruction_count(4);
5328     dst    : S4(write);
5329     src1   : S3(read);
5330     src2   : S3(read);
5331     src3   : S3(read);
5332     DECODE : S0(4);     // any 3 decoders
5333     FPU    : S3(2);
5334 %}
5335 
5336 // Float reg-reg operation
5337 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5338     instruction_count(4);
5339     dst    : S4(write);
5340     src1   : S3(read);
5341     src2   : S3(read);
5342     src3   : S3(read);
5343     DECODE : S1(3);     // any 3 decoders
5344     D0     : S0;        // Big decoder only
5345     FPU    : S3(2);
5346     MEM    : S3;
5347 %}
5348 
5349 // Float reg-mem operation
5350 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5351     instruction_count(2);
5352     dst    : S5(write);
5353     mem    : S3(read);
5354     D0     : S0;        // big decoder only
5355     DECODE : S1;        // any decoder for FPU POP
5356     FPU    : S4;
5357     MEM    : S3;        // any mem
5358 %}
5359 
5360 // Float reg-mem operation
5361 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5362     instruction_count(3);
5363     dst    : S5(write);
5364     src1   : S3(read);
5365     mem    : S3(read);
5366     D0     : S0;        // big decoder only
5367     DECODE : S1(2);     // any decoder for FPU POP
5368     FPU    : S4;
5369     MEM    : S3;        // any mem
5370 %}
5371 
5372 // Float mem-reg operation
5373 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5374     instruction_count(2);
5375     src    : S5(read);
5376     mem    : S3(read);
5377     DECODE : S0;        // any decoder for FPU PUSH
5378     D0     : S1;        // big decoder only
5379     FPU    : S4;
5380     MEM    : S3;        // any mem
5381 %}
5382 
5383 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5384     instruction_count(3);
5385     src1   : S3(read);
5386     src2   : S3(read);
5387     mem    : S3(read);
5388     DECODE : S0(2);     // any decoder for FPU PUSH
5389     D0     : S1;        // big decoder only
5390     FPU    : S4;
5391     MEM    : S3;        // any mem
5392 %}
5393 
5394 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5395     instruction_count(3);
5396     src1   : S3(read);
5397     src2   : S3(read);
5398     mem    : S4(read);
5399     DECODE : S0;        // any decoder for FPU PUSH
5400     D0     : S0(2);     // big decoder only
5401     FPU    : S4;
5402     MEM    : S3(2);     // any mem
5403 %}
5404 
5405 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5406     instruction_count(2);
5407     src1   : S3(read);
5408     dst    : S4(read);
5409     D0     : S0(2);     // big decoder only
5410     MEM    : S3(2);     // any mem
5411 %}
5412 
5413 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5414     instruction_count(3);
5415     src1   : S3(read);
5416     src2   : S3(read);
5417     dst    : S4(read);
5418     D0     : S0(3);     // big decoder only
5419     FPU    : S4;
5420     MEM    : S3(3);     // any mem
5421 %}
5422 
5423 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5424     instruction_count(3);
5425     src1   : S4(read);
5426     mem    : S4(read);
5427     DECODE : S0;        // any decoder for FPU PUSH
5428     D0     : S0(2);     // big decoder only
5429     FPU    : S4;
5430     MEM    : S3(2);     // any mem
5431 %}
5432 
5433 // Float load constant
5434 pipe_class fpu_reg_con(regDPR dst) %{
5435     instruction_count(2);
5436     dst    : S5(write);
5437     D0     : S0;        // big decoder only for the load
5438     DECODE : S1;        // any decoder for FPU POP
5439     FPU    : S4;
5440     MEM    : S3;        // any mem
5441 %}
5442 
5443 // Float load constant
5444 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5445     instruction_count(3);
5446     dst    : S5(write);
5447     src    : S3(read);
5448     D0     : S0;        // big decoder only for the load
5449     DECODE : S1(2);     // any decoder for FPU POP
5450     FPU    : S4;
5451     MEM    : S3;        // any mem
5452 %}
5453 
5454 // UnConditional branch
5455 pipe_class pipe_jmp( label labl ) %{
5456     single_instruction;
5457     BR   : S3;
5458 %}
5459 
5460 // Conditional branch
5461 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5462     single_instruction;
5463     cr    : S1(read);
5464     BR    : S3;
5465 %}
5466 
5467 // Allocation idiom
5468 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5469     instruction_count(1); force_serialization;
5470     fixed_latency(6);
5471     heap_ptr : S3(read);
5472     DECODE   : S0(3);
5473     D0       : S2;
5474     MEM      : S3;
5475     ALU      : S3(2);
5476     dst      : S5(write);
5477     BR       : S5;
5478 %}
5479 
5480 // Generic big/slow expanded idiom
5481 pipe_class pipe_slow(  ) %{
5482     instruction_count(10); multiple_bundles; force_serialization;
5483     fixed_latency(100);
5484     D0  : S0(2);
5485     MEM : S3(2);
5486 %}
5487 
5488 // The real do-nothing guy
5489 pipe_class empty( ) %{
5490     instruction_count(0);
5491 %}
5492 
5493 // Define the class for the Nop node
5494 define %{
5495    MachNop = empty;
5496 %}
5497 
5498 %}
5499 
5500 //----------INSTRUCTIONS-------------------------------------------------------
5501 //
5502 // match      -- States which machine-independent subtree may be replaced
5503 //               by this instruction.
5504 // ins_cost   -- The estimated cost of this instruction is used by instruction
5505 //               selection to identify a minimum cost tree of machine
5506 //               instructions that matches a tree of machine-independent
5507 //               instructions.
5508 // format     -- A string providing the disassembly for this instruction.
5509 //               The value of an instruction's operand may be inserted
5510 //               by referring to it with a '$' prefix.
5511 // opcode     -- Three instruction opcodes may be provided.  These are referred
5512 //               to within an encode class as $primary, $secondary, and $tertiary
5513 //               respectively.  The primary opcode is commonly used to
5514 //               indicate the type of machine instruction, while secondary
5515 //               and tertiary are often used for prefix options or addressing
5516 //               modes.
5517 // ins_encode -- A list of encode classes with parameters. The encode class
5518 //               name must have been defined in an 'enc_class' specification
5519 //               in the encode section of the architecture description.
5520 
5521 //----------BSWAP-Instruction--------------------------------------------------
5522 instruct bytes_reverse_int(rRegI dst) %{
5523   match(Set dst (ReverseBytesI dst));
5524 
5525   format %{ "BSWAP  $dst" %}
5526   opcode(0x0F, 0xC8);
5527   ins_encode( OpcP, OpcSReg(dst) );
5528   ins_pipe( ialu_reg );
5529 %}
5530 
5531 instruct bytes_reverse_long(eRegL dst) %{
5532   match(Set dst (ReverseBytesL dst));
5533 
5534   format %{ "BSWAP  $dst.lo\n\t"
5535             "BSWAP  $dst.hi\n\t"
5536             "XCHG   $dst.lo $dst.hi" %}
5537 
5538   ins_cost(125);
5539   ins_encode( bswap_long_bytes(dst) );
5540   ins_pipe( ialu_reg_reg);
5541 %}
5542 
5543 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5544   match(Set dst (ReverseBytesUS dst));
5545   effect(KILL cr);
5546 
5547   format %{ "BSWAP  $dst\n\t" 
5548             "SHR    $dst,16\n\t" %}
5549   ins_encode %{
5550     __ bswapl($dst$$Register);
5551     __ shrl($dst$$Register, 16); 
5552   %}
5553   ins_pipe( ialu_reg );
5554 %}
5555 
5556 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5557   match(Set dst (ReverseBytesS dst));
5558   effect(KILL cr);
5559 
5560   format %{ "BSWAP  $dst\n\t" 
5561             "SAR    $dst,16\n\t" %}
5562   ins_encode %{
5563     __ bswapl($dst$$Register);
5564     __ sarl($dst$$Register, 16); 
5565   %}
5566   ins_pipe( ialu_reg );
5567 %}
5568 
5569 
5570 //---------- Zeros Count Instructions ------------------------------------------
5571 
5572 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5573   predicate(UseCountLeadingZerosInstruction);
5574   match(Set dst (CountLeadingZerosI src));
5575   effect(KILL cr);
5576 
5577   format %{ "LZCNT  $dst, $src\t# count leading zeros (int)" %}
5578   ins_encode %{
5579     __ lzcntl($dst$$Register, $src$$Register);
5580   %}
5581   ins_pipe(ialu_reg);
5582 %}
5583 
5584 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5585   predicate(!UseCountLeadingZerosInstruction);
5586   match(Set dst (CountLeadingZerosI src));
5587   effect(KILL cr);
5588 
5589   format %{ "BSR    $dst, $src\t# count leading zeros (int)\n\t"
5590             "JNZ    skip\n\t"
5591             "MOV    $dst, -1\n"
5592       "skip:\n\t"
5593             "NEG    $dst\n\t"
5594             "ADD    $dst, 31" %}
5595   ins_encode %{
5596     Register Rdst = $dst$$Register;
5597     Register Rsrc = $src$$Register;
5598     Label skip;
5599     __ bsrl(Rdst, Rsrc);
5600     __ jccb(Assembler::notZero, skip);
5601     __ movl(Rdst, -1);
5602     __ bind(skip);
5603     __ negl(Rdst);
5604     __ addl(Rdst, BitsPerInt - 1);
5605   %}
5606   ins_pipe(ialu_reg);
5607 %}
5608 
5609 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5610   predicate(UseCountLeadingZerosInstruction);
5611   match(Set dst (CountLeadingZerosL src));
5612   effect(TEMP dst, KILL cr);
5613 
5614   format %{ "LZCNT  $dst, $src.hi\t# count leading zeros (long)\n\t"
5615             "JNC    done\n\t"
5616             "LZCNT  $dst, $src.lo\n\t"
5617             "ADD    $dst, 32\n"
5618       "done:" %}
5619   ins_encode %{
5620     Register Rdst = $dst$$Register;
5621     Register Rsrc = $src$$Register;
5622     Label done;
5623     __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5624     __ jccb(Assembler::carryClear, done);
5625     __ lzcntl(Rdst, Rsrc);
5626     __ addl(Rdst, BitsPerInt);
5627     __ bind(done);
5628   %}
5629   ins_pipe(ialu_reg);
5630 %}
5631 
5632 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5633   predicate(!UseCountLeadingZerosInstruction);
5634   match(Set dst (CountLeadingZerosL src));
5635   effect(TEMP dst, KILL cr);
5636 
5637   format %{ "BSR    $dst, $src.hi\t# count leading zeros (long)\n\t"
5638             "JZ     msw_is_zero\n\t"
5639             "ADD    $dst, 32\n\t"
5640             "JMP    not_zero\n"
5641       "msw_is_zero:\n\t"
5642             "BSR    $dst, $src.lo\n\t"
5643             "JNZ    not_zero\n\t"
5644             "MOV    $dst, -1\n"
5645       "not_zero:\n\t"
5646             "NEG    $dst\n\t"
5647             "ADD    $dst, 63\n" %}
5648  ins_encode %{
5649     Register Rdst = $dst$$Register;
5650     Register Rsrc = $src$$Register;
5651     Label msw_is_zero;
5652     Label not_zero;
5653     __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5654     __ jccb(Assembler::zero, msw_is_zero);
5655     __ addl(Rdst, BitsPerInt);
5656     __ jmpb(not_zero);
5657     __ bind(msw_is_zero);
5658     __ bsrl(Rdst, Rsrc);
5659     __ jccb(Assembler::notZero, not_zero);
5660     __ movl(Rdst, -1);
5661     __ bind(not_zero);
5662     __ negl(Rdst);
5663     __ addl(Rdst, BitsPerLong - 1);
5664   %}
5665   ins_pipe(ialu_reg);
5666 %}
5667 
5668 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5669   match(Set dst (CountTrailingZerosI src));
5670   effect(KILL cr);
5671 
5672   format %{ "BSF    $dst, $src\t# count trailing zeros (int)\n\t"
5673             "JNZ    done\n\t"
5674             "MOV    $dst, 32\n"
5675       "done:" %}
5676   ins_encode %{
5677     Register Rdst = $dst$$Register;
5678     Label done;
5679     __ bsfl(Rdst, $src$$Register);
5680     __ jccb(Assembler::notZero, done);
5681     __ movl(Rdst, BitsPerInt);
5682     __ bind(done);
5683   %}
5684   ins_pipe(ialu_reg);
5685 %}
5686 
5687 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5688   match(Set dst (CountTrailingZerosL src));
5689   effect(TEMP dst, KILL cr);
5690 
5691   format %{ "BSF    $dst, $src.lo\t# count trailing zeros (long)\n\t"
5692             "JNZ    done\n\t"
5693             "BSF    $dst, $src.hi\n\t"
5694             "JNZ    msw_not_zero\n\t"
5695             "MOV    $dst, 32\n"
5696       "msw_not_zero:\n\t"
5697             "ADD    $dst, 32\n"
5698       "done:" %}
5699   ins_encode %{
5700     Register Rdst = $dst$$Register;
5701     Register Rsrc = $src$$Register;
5702     Label msw_not_zero;
5703     Label done;
5704     __ bsfl(Rdst, Rsrc);
5705     __ jccb(Assembler::notZero, done);
5706     __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5707     __ jccb(Assembler::notZero, msw_not_zero);
5708     __ movl(Rdst, BitsPerInt);
5709     __ bind(msw_not_zero);
5710     __ addl(Rdst, BitsPerInt);
5711     __ bind(done);
5712   %}
5713   ins_pipe(ialu_reg);
5714 %}
5715 
5716 
5717 //---------- Population Count Instructions -------------------------------------
5718 
5719 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5720   predicate(UsePopCountInstruction);
5721   match(Set dst (PopCountI src));
5722   effect(KILL cr);
5723 
5724   format %{ "POPCNT $dst, $src" %}
5725   ins_encode %{
5726     __ popcntl($dst$$Register, $src$$Register);
5727   %}
5728   ins_pipe(ialu_reg);
5729 %}
5730 
5731 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5732   predicate(UsePopCountInstruction);
5733   match(Set dst (PopCountI (LoadI mem)));
5734   effect(KILL cr);
5735 
5736   format %{ "POPCNT $dst, $mem" %}
5737   ins_encode %{
5738     __ popcntl($dst$$Register, $mem$$Address);
5739   %}
5740   ins_pipe(ialu_reg);
5741 %}
5742 
5743 // Note: Long.bitCount(long) returns an int.
5744 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5745   predicate(UsePopCountInstruction);
5746   match(Set dst (PopCountL src));
5747   effect(KILL cr, TEMP tmp, TEMP dst);
5748 
5749   format %{ "POPCNT $dst, $src.lo\n\t"
5750             "POPCNT $tmp, $src.hi\n\t"
5751             "ADD    $dst, $tmp" %}
5752   ins_encode %{
5753     __ popcntl($dst$$Register, $src$$Register);
5754     __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5755     __ addl($dst$$Register, $tmp$$Register);
5756   %}
5757   ins_pipe(ialu_reg);
5758 %}
5759 
5760 // Note: Long.bitCount(long) returns an int.
5761 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5762   predicate(UsePopCountInstruction);
5763   match(Set dst (PopCountL (LoadL mem)));
5764   effect(KILL cr, TEMP tmp, TEMP dst);
5765 
5766   format %{ "POPCNT $dst, $mem\n\t"
5767             "POPCNT $tmp, $mem+4\n\t"
5768             "ADD    $dst, $tmp" %}
5769   ins_encode %{
5770     //__ popcntl($dst$$Register, $mem$$Address$$first);
5771     //__ popcntl($tmp$$Register, $mem$$Address$$second);
5772     __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5773     __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5774     __ addl($dst$$Register, $tmp$$Register);
5775   %}
5776   ins_pipe(ialu_reg);
5777 %}
5778 
5779 
5780 //----------Load/Store/Move Instructions---------------------------------------
5781 //----------Load Instructions--------------------------------------------------
5782 // Load Byte (8bit signed)
5783 instruct loadB(xRegI dst, memory mem) %{
5784   match(Set dst (LoadB mem));
5785 
5786   ins_cost(125);
5787   format %{ "MOVSX8 $dst,$mem\t# byte" %}
5788 
5789   ins_encode %{
5790     __ movsbl($dst$$Register, $mem$$Address);
5791   %}
5792 
5793   ins_pipe(ialu_reg_mem);
5794 %}
5795 
5796 // Load Byte (8bit signed) into Long Register
5797 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5798   match(Set dst (ConvI2L (LoadB mem)));
5799   effect(KILL cr);
5800 
5801   ins_cost(375);
5802   format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5803             "MOV    $dst.hi,$dst.lo\n\t"
5804             "SAR    $dst.hi,7" %}
5805 
5806   ins_encode %{
5807     __ movsbl($dst$$Register, $mem$$Address);
5808     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5809     __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5810   %}
5811 
5812   ins_pipe(ialu_reg_mem);
5813 %}
5814 
5815 // Load Unsigned Byte (8bit UNsigned)
5816 instruct loadUB(xRegI dst, memory mem) %{
5817   match(Set dst (LoadUB mem));
5818 
5819   ins_cost(125);
5820   format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5821 
5822   ins_encode %{
5823     __ movzbl($dst$$Register, $mem$$Address);
5824   %}
5825 
5826   ins_pipe(ialu_reg_mem);
5827 %}
5828 
5829 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5830 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5831   match(Set dst (ConvI2L (LoadUB mem)));
5832   effect(KILL cr);
5833 
5834   ins_cost(250);
5835   format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5836             "XOR    $dst.hi,$dst.hi" %}
5837 
5838   ins_encode %{
5839     Register Rdst = $dst$$Register;
5840     __ movzbl(Rdst, $mem$$Address);
5841     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5842   %}
5843 
5844   ins_pipe(ialu_reg_mem);
5845 %}
5846 
5847 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5848 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5849   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5850   effect(KILL cr);
5851 
5852   format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5853             "XOR    $dst.hi,$dst.hi\n\t"
5854             "AND    $dst.lo,$mask" %}
5855   ins_encode %{
5856     Register Rdst = $dst$$Register;
5857     __ movzbl(Rdst, $mem$$Address);
5858     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5859     __ andl(Rdst, $mask$$constant);
5860   %}
5861   ins_pipe(ialu_reg_mem);
5862 %}
5863 
5864 // Load Short (16bit signed)
5865 instruct loadS(rRegI dst, memory mem) %{
5866   match(Set dst (LoadS mem));
5867 
5868   ins_cost(125);
5869   format %{ "MOVSX  $dst,$mem\t# short" %}
5870 
5871   ins_encode %{
5872     __ movswl($dst$$Register, $mem$$Address);
5873   %}
5874 
5875   ins_pipe(ialu_reg_mem);
5876 %}
5877 
5878 // Load Short (16 bit signed) to Byte (8 bit signed)
5879 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5880   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5881 
5882   ins_cost(125);
5883   format %{ "MOVSX  $dst, $mem\t# short -> byte" %}
5884   ins_encode %{
5885     __ movsbl($dst$$Register, $mem$$Address);
5886   %}
5887   ins_pipe(ialu_reg_mem);
5888 %}
5889 
5890 // Load Short (16bit signed) into Long Register
5891 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5892   match(Set dst (ConvI2L (LoadS mem)));
5893   effect(KILL cr);
5894 
5895   ins_cost(375);
5896   format %{ "MOVSX  $dst.lo,$mem\t# short -> long\n\t"
5897             "MOV    $dst.hi,$dst.lo\n\t"
5898             "SAR    $dst.hi,15" %}
5899 
5900   ins_encode %{
5901     __ movswl($dst$$Register, $mem$$Address);
5902     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5903     __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5904   %}
5905 
5906   ins_pipe(ialu_reg_mem);
5907 %}
5908 
5909 // Load Unsigned Short/Char (16bit unsigned)
5910 instruct loadUS(rRegI dst, memory mem) %{
5911   match(Set dst (LoadUS mem));
5912 
5913   ins_cost(125);
5914   format %{ "MOVZX  $dst,$mem\t# ushort/char -> int" %}
5915 
5916   ins_encode %{
5917     __ movzwl($dst$$Register, $mem$$Address);
5918   %}
5919 
5920   ins_pipe(ialu_reg_mem);
5921 %}
5922 
5923 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5924 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5925   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5926 
5927   ins_cost(125);
5928   format %{ "MOVSX  $dst, $mem\t# ushort -> byte" %}
5929   ins_encode %{
5930     __ movsbl($dst$$Register, $mem$$Address);
5931   %}
5932   ins_pipe(ialu_reg_mem);
5933 %}
5934 
5935 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5936 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5937   match(Set dst (ConvI2L (LoadUS mem)));
5938   effect(KILL cr);
5939 
5940   ins_cost(250);
5941   format %{ "MOVZX  $dst.lo,$mem\t# ushort/char -> long\n\t"
5942             "XOR    $dst.hi,$dst.hi" %}
5943 
5944   ins_encode %{
5945     __ movzwl($dst$$Register, $mem$$Address);
5946     __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5947   %}
5948 
5949   ins_pipe(ialu_reg_mem);
5950 %}
5951 
5952 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5953 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5954   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5955   effect(KILL cr);
5956 
5957   format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5958             "XOR    $dst.hi,$dst.hi" %}
5959   ins_encode %{
5960     Register Rdst = $dst$$Register;
5961     __ movzbl(Rdst, $mem$$Address);
5962     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5963   %}
5964   ins_pipe(ialu_reg_mem);
5965 %}
5966 
5967 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5968 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5969   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5970   effect(KILL cr);
5971 
5972   format %{ "MOVZX  $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5973             "XOR    $dst.hi,$dst.hi\n\t"
5974             "AND    $dst.lo,$mask" %}
5975   ins_encode %{
5976     Register Rdst = $dst$$Register;
5977     __ movzwl(Rdst, $mem$$Address);
5978     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5979     __ andl(Rdst, $mask$$constant);
5980   %}
5981   ins_pipe(ialu_reg_mem);
5982 %}
5983 
5984 // Load Integer
5985 instruct loadI(rRegI dst, memory mem) %{
5986   match(Set dst (LoadI mem));
5987 
5988   ins_cost(125);
5989   format %{ "MOV    $dst,$mem\t# int" %}
5990 
5991   ins_encode %{
5992     __ movl($dst$$Register, $mem$$Address);
5993   %}
5994 
5995   ins_pipe(ialu_reg_mem);
5996 %}
5997 
5998 // Load Integer (32 bit signed) to Byte (8 bit signed)
5999 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6000   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6001 
6002   ins_cost(125);
6003   format %{ "MOVSX  $dst, $mem\t# int -> byte" %}
6004   ins_encode %{
6005     __ movsbl($dst$$Register, $mem$$Address);
6006   %}
6007   ins_pipe(ialu_reg_mem);
6008 %}
6009 
6010 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6011 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6012   match(Set dst (AndI (LoadI mem) mask));
6013 
6014   ins_cost(125);
6015   format %{ "MOVZX  $dst, $mem\t# int -> ubyte" %}
6016   ins_encode %{
6017     __ movzbl($dst$$Register, $mem$$Address);
6018   %}
6019   ins_pipe(ialu_reg_mem);
6020 %}
6021 
6022 // Load Integer (32 bit signed) to Short (16 bit signed)
6023 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6024   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6025 
6026   ins_cost(125);
6027   format %{ "MOVSX  $dst, $mem\t# int -> short" %}
6028   ins_encode %{
6029     __ movswl($dst$$Register, $mem$$Address);
6030   %}
6031   ins_pipe(ialu_reg_mem);
6032 %}
6033 
6034 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6035 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6036   match(Set dst (AndI (LoadI mem) mask));
6037 
6038   ins_cost(125);
6039   format %{ "MOVZX  $dst, $mem\t# int -> ushort/char" %}
6040   ins_encode %{
6041     __ movzwl($dst$$Register, $mem$$Address);
6042   %}
6043   ins_pipe(ialu_reg_mem);
6044 %}
6045 
6046 // Load Integer into Long Register
6047 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6048   match(Set dst (ConvI2L (LoadI mem)));
6049   effect(KILL cr);
6050 
6051   ins_cost(375);
6052   format %{ "MOV    $dst.lo,$mem\t# int -> long\n\t"
6053             "MOV    $dst.hi,$dst.lo\n\t"
6054             "SAR    $dst.hi,31" %}
6055 
6056   ins_encode %{
6057     __ movl($dst$$Register, $mem$$Address);
6058     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6059     __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6060   %}
6061 
6062   ins_pipe(ialu_reg_mem);
6063 %}
6064 
6065 // Load Integer with mask 0xFF into Long Register
6066 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6067   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6068   effect(KILL cr);
6069 
6070   format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6071             "XOR    $dst.hi,$dst.hi" %}
6072   ins_encode %{
6073     Register Rdst = $dst$$Register;
6074     __ movzbl(Rdst, $mem$$Address);
6075     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6076   %}
6077   ins_pipe(ialu_reg_mem);
6078 %}
6079 
6080 // Load Integer with mask 0xFFFF into Long Register
6081 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6082   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6083   effect(KILL cr);
6084 
6085   format %{ "MOVZX  $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6086             "XOR    $dst.hi,$dst.hi" %}
6087   ins_encode %{
6088     Register Rdst = $dst$$Register;
6089     __ movzwl(Rdst, $mem$$Address);
6090     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6091   %}
6092   ins_pipe(ialu_reg_mem);
6093 %}
6094 
6095 // Load Integer with 32-bit mask into Long Register
6096 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6097   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6098   effect(KILL cr);
6099 
6100   format %{ "MOV    $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6101             "XOR    $dst.hi,$dst.hi\n\t"
6102             "AND    $dst.lo,$mask" %}
6103   ins_encode %{
6104     Register Rdst = $dst$$Register;
6105     __ movl(Rdst, $mem$$Address);
6106     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6107     __ andl(Rdst, $mask$$constant);
6108   %}
6109   ins_pipe(ialu_reg_mem);
6110 %}
6111 
6112 // Load Unsigned Integer into Long Register
6113 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6114   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6115   effect(KILL cr);
6116 
6117   ins_cost(250);
6118   format %{ "MOV    $dst.lo,$mem\t# uint -> long\n\t"
6119             "XOR    $dst.hi,$dst.hi" %}
6120 
6121   ins_encode %{
6122     __ movl($dst$$Register, $mem$$Address);
6123     __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6124   %}
6125 
6126   ins_pipe(ialu_reg_mem);
6127 %}
6128 
6129 // Load Long.  Cannot clobber address while loading, so restrict address
6130 // register to ESI
6131 instruct loadL(eRegL dst, load_long_memory mem) %{
6132   predicate(!((LoadLNode*)n)->require_atomic_access());
6133   match(Set dst (LoadL mem));
6134 
6135   ins_cost(250);
6136   format %{ "MOV    $dst.lo,$mem\t# long\n\t"
6137             "MOV    $dst.hi,$mem+4" %}
6138 
6139   ins_encode %{
6140     Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6141     Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6142     __ movl($dst$$Register, Amemlo);
6143     __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6144   %}
6145 
6146   ins_pipe(ialu_reg_long_mem);
6147 %}
6148 
6149 // Volatile Load Long.  Must be atomic, so do 64-bit FILD
6150 // then store it down to the stack and reload on the int
6151 // side.
6152 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6153   predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6154   match(Set dst (LoadL mem));
6155 
6156   ins_cost(200);
6157   format %{ "FILD   $mem\t# Atomic volatile long load\n\t"
6158             "FISTp  $dst" %}
6159   ins_encode(enc_loadL_volatile(mem,dst));
6160   ins_pipe( fpu_reg_mem );
6161 %}
6162 
6163 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6164   predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6165   match(Set dst (LoadL mem));
6166   effect(TEMP tmp);
6167   ins_cost(180);
6168   format %{ "MOVSD  $tmp,$mem\t# Atomic volatile long load\n\t"
6169             "MOVSD  $dst,$tmp" %}
6170   ins_encode %{
6171     __ movdbl($tmp$$XMMRegister, $mem$$Address);
6172     __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6173   %}
6174   ins_pipe( pipe_slow );
6175 %}
6176 
6177 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6178   predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6179   match(Set dst (LoadL mem));
6180   effect(TEMP tmp);
6181   ins_cost(160);
6182   format %{ "MOVSD  $tmp,$mem\t# Atomic volatile long load\n\t"
6183             "MOVD   $dst.lo,$tmp\n\t"
6184             "PSRLQ  $tmp,32\n\t"
6185             "MOVD   $dst.hi,$tmp" %}
6186   ins_encode %{
6187     __ movdbl($tmp$$XMMRegister, $mem$$Address);
6188     __ movdl($dst$$Register, $tmp$$XMMRegister);
6189     __ psrlq($tmp$$XMMRegister, 32);
6190     __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6191   %}
6192   ins_pipe( pipe_slow );
6193 %}
6194 
6195 // Load Range
6196 instruct loadRange(rRegI dst, memory mem) %{
6197   match(Set dst (LoadRange mem));
6198 
6199   ins_cost(125);
6200   format %{ "MOV    $dst,$mem" %}
6201   opcode(0x8B);
6202   ins_encode( OpcP, RegMem(dst,mem));
6203   ins_pipe( ialu_reg_mem );
6204 %}
6205 
6206 
6207 // Load Pointer
6208 instruct loadP(eRegP dst, memory mem) %{
6209   match(Set dst (LoadP mem));
6210 
6211   ins_cost(125);
6212   format %{ "MOV    $dst,$mem" %}
6213   opcode(0x8B);
6214   ins_encode( OpcP, RegMem(dst,mem));
6215   ins_pipe( ialu_reg_mem );
6216 %}
6217 
6218 // Load Klass Pointer
6219 instruct loadKlass(eRegP dst, memory mem) %{
6220   match(Set dst (LoadKlass mem));
6221 
6222   ins_cost(125);
6223   format %{ "MOV    $dst,$mem" %}
6224   opcode(0x8B);
6225   ins_encode( OpcP, RegMem(dst,mem));
6226   ins_pipe( ialu_reg_mem );
6227 %}
6228 
6229 // Load Double
6230 instruct loadDPR(regDPR dst, memory mem) %{
6231   predicate(UseSSE<=1);
6232   match(Set dst (LoadD mem));
6233 
6234   ins_cost(150);
6235   format %{ "FLD_D  ST,$mem\n\t"
6236             "FSTP   $dst" %}
6237   opcode(0xDD);               /* DD /0 */
6238   ins_encode( OpcP, RMopc_Mem(0x00,mem),
6239               Pop_Reg_DPR(dst) );
6240   ins_pipe( fpu_reg_mem );
6241 %}
6242 
6243 // Load Double to XMM
6244 instruct loadD(regD dst, memory mem) %{
6245   predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6246   match(Set dst (LoadD mem));
6247   ins_cost(145);
6248   format %{ "MOVSD  $dst,$mem" %}
6249   ins_encode %{
6250     __ movdbl ($dst$$XMMRegister, $mem$$Address);
6251   %}
6252   ins_pipe( pipe_slow );
6253 %}
6254 
6255 instruct loadD_partial(regD dst, memory mem) %{
6256   predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6257   match(Set dst (LoadD mem));
6258   ins_cost(145);
6259   format %{ "MOVLPD $dst,$mem" %}
6260   ins_encode %{
6261     __ movdbl ($dst$$XMMRegister, $mem$$Address);
6262   %}
6263   ins_pipe( pipe_slow );
6264 %}
6265 
6266 // Load to XMM register (single-precision floating point)
6267 // MOVSS instruction
6268 instruct loadF(regF dst, memory mem) %{
6269   predicate(UseSSE>=1);
6270   match(Set dst (LoadF mem));
6271   ins_cost(145);
6272   format %{ "MOVSS  $dst,$mem" %}
6273   ins_encode %{
6274     __ movflt ($dst$$XMMRegister, $mem$$Address);
6275   %}
6276   ins_pipe( pipe_slow );
6277 %}
6278 
6279 // Load Float
6280 instruct loadFPR(regFPR dst, memory mem) %{
6281   predicate(UseSSE==0);
6282   match(Set dst (LoadF mem));
6283 
6284   ins_cost(150);
6285   format %{ "FLD_S  ST,$mem\n\t"
6286             "FSTP   $dst" %}
6287   opcode(0xD9);               /* D9 /0 */
6288   ins_encode( OpcP, RMopc_Mem(0x00,mem),
6289               Pop_Reg_FPR(dst) );
6290   ins_pipe( fpu_reg_mem );
6291 %}
6292 
6293 // Load Effective Address
6294 instruct leaP8(eRegP dst, indOffset8 mem) %{
6295   match(Set dst mem);
6296 
6297   ins_cost(110);
6298   format %{ "LEA    $dst,$mem" %}
6299   opcode(0x8D);
6300   ins_encode( OpcP, RegMem(dst,mem));
6301   ins_pipe( ialu_reg_reg_fat );
6302 %}
6303 
6304 instruct leaP32(eRegP dst, indOffset32 mem) %{
6305   match(Set dst mem);
6306 
6307   ins_cost(110);
6308   format %{ "LEA    $dst,$mem" %}
6309   opcode(0x8D);
6310   ins_encode( OpcP, RegMem(dst,mem));
6311   ins_pipe( ialu_reg_reg_fat );
6312 %}
6313 
6314 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6315   match(Set dst mem);
6316 
6317   ins_cost(110);
6318   format %{ "LEA    $dst,$mem" %}
6319   opcode(0x8D);
6320   ins_encode( OpcP, RegMem(dst,mem));
6321   ins_pipe( ialu_reg_reg_fat );
6322 %}
6323 
6324 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6325   match(Set dst mem);
6326 
6327   ins_cost(110);
6328   format %{ "LEA    $dst,$mem" %}
6329   opcode(0x8D);
6330   ins_encode( OpcP, RegMem(dst,mem));
6331   ins_pipe( ialu_reg_reg_fat );
6332 %}
6333 
6334 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6335   match(Set dst mem);
6336 
6337   ins_cost(110);
6338   format %{ "LEA    $dst,$mem" %}
6339   opcode(0x8D);
6340   ins_encode( OpcP, RegMem(dst,mem));
6341   ins_pipe( ialu_reg_reg_fat );
6342 %}
6343 
6344 // Load Constant
6345 instruct loadConI(rRegI dst, immI src) %{
6346   match(Set dst src);
6347 
6348   format %{ "MOV    $dst,$src" %}
6349   ins_encode( LdImmI(dst, src) );
6350   ins_pipe( ialu_reg_fat );
6351 %}
6352 
6353 // Load Constant zero
6354 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6355   match(Set dst src);
6356   effect(KILL cr);
6357 
6358   ins_cost(50);
6359   format %{ "XOR    $dst,$dst" %}
6360   opcode(0x33);  /* + rd */
6361   ins_encode( OpcP, RegReg( dst, dst ) );
6362   ins_pipe( ialu_reg );
6363 %}
6364 
6365 instruct loadConP(eRegP dst, immP src) %{
6366   match(Set dst src);
6367 
6368   format %{ "MOV    $dst,$src" %}
6369   opcode(0xB8);  /* + rd */
6370   ins_encode( LdImmP(dst, src) );
6371   ins_pipe( ialu_reg_fat );
6372 %}
6373 
6374 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6375   match(Set dst src);
6376   effect(KILL cr);
6377   ins_cost(200);
6378   format %{ "MOV    $dst.lo,$src.lo\n\t"
6379             "MOV    $dst.hi,$src.hi" %}
6380   opcode(0xB8);
6381   ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6382   ins_pipe( ialu_reg_long_fat );
6383 %}
6384 
6385 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6386   match(Set dst src);
6387   effect(KILL cr);
6388   ins_cost(150);
6389   format %{ "XOR    $dst.lo,$dst.lo\n\t"
6390             "XOR    $dst.hi,$dst.hi" %}
6391   opcode(0x33,0x33);
6392   ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6393   ins_pipe( ialu_reg_long );
6394 %}
6395 
6396 // The instruction usage is guarded by predicate in operand immFPR().
6397 instruct loadConFPR(regFPR dst, immFPR con) %{
6398   match(Set dst con);
6399   ins_cost(125);
6400   format %{ "FLD_S  ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6401             "FSTP   $dst" %}
6402   ins_encode %{
6403     __ fld_s($constantaddress($con));
6404     __ fstp_d($dst$$reg);
6405   %}
6406   ins_pipe(fpu_reg_con);
6407 %}
6408 
6409 // The instruction usage is guarded by predicate in operand immFPR0().
6410 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6411   match(Set dst con);
6412   ins_cost(125);
6413   format %{ "FLDZ   ST\n\t"
6414             "FSTP   $dst" %}
6415   ins_encode %{
6416     __ fldz();
6417     __ fstp_d($dst$$reg);
6418   %}
6419   ins_pipe(fpu_reg_con);
6420 %}
6421 
6422 // The instruction usage is guarded by predicate in operand immFPR1().
6423 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6424   match(Set dst con);
6425   ins_cost(125);
6426   format %{ "FLD1   ST\n\t"
6427             "FSTP   $dst" %}
6428   ins_encode %{
6429     __ fld1();
6430     __ fstp_d($dst$$reg);
6431   %}
6432   ins_pipe(fpu_reg_con);
6433 %}
6434 
6435 // The instruction usage is guarded by predicate in operand immF().
6436 instruct loadConF(regF dst, immF con) %{
6437   match(Set dst con);
6438   ins_cost(125);
6439   format %{ "MOVSS  $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6440   ins_encode %{
6441     __ movflt($dst$$XMMRegister, $constantaddress($con));
6442   %}
6443   ins_pipe(pipe_slow);
6444 %}
6445 
6446 // The instruction usage is guarded by predicate in operand immF0().
6447 instruct loadConF0(regF dst, immF0 src) %{
6448   match(Set dst src);
6449   ins_cost(100);
6450   format %{ "XORPS  $dst,$dst\t# float 0.0" %}
6451   ins_encode %{
6452     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6453   %}
6454   ins_pipe(pipe_slow);
6455 %}
6456 
6457 // The instruction usage is guarded by predicate in operand immDPR().
6458 instruct loadConDPR(regDPR dst, immDPR con) %{
6459   match(Set dst con);
6460   ins_cost(125);
6461 
6462   format %{ "FLD_D  ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6463             "FSTP   $dst" %}
6464   ins_encode %{
6465     __ fld_d($constantaddress($con));
6466     __ fstp_d($dst$$reg);
6467   %}
6468   ins_pipe(fpu_reg_con);
6469 %}
6470 
6471 // The instruction usage is guarded by predicate in operand immDPR0().
6472 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6473   match(Set dst con);
6474   ins_cost(125);
6475 
6476   format %{ "FLDZ   ST\n\t"
6477             "FSTP   $dst" %}
6478   ins_encode %{
6479     __ fldz();
6480     __ fstp_d($dst$$reg);
6481   %}
6482   ins_pipe(fpu_reg_con);
6483 %}
6484 
6485 // The instruction usage is guarded by predicate in operand immDPR1().
6486 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6487   match(Set dst con);
6488   ins_cost(125);
6489 
6490   format %{ "FLD1   ST\n\t"
6491             "FSTP   $dst" %}
6492   ins_encode %{
6493     __ fld1();
6494     __ fstp_d($dst$$reg);
6495   %}
6496   ins_pipe(fpu_reg_con);
6497 %}
6498 
6499 // The instruction usage is guarded by predicate in operand immD().
6500 instruct loadConD(regD dst, immD con) %{
6501   match(Set dst con);
6502   ins_cost(125);
6503   format %{ "MOVSD  $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6504   ins_encode %{
6505     __ movdbl($dst$$XMMRegister, $constantaddress($con));
6506   %}
6507   ins_pipe(pipe_slow);
6508 %}
6509 
6510 // The instruction usage is guarded by predicate in operand immD0().
6511 instruct loadConD0(regD dst, immD0 src) %{
6512   match(Set dst src);
6513   ins_cost(100);
6514   format %{ "XORPD  $dst,$dst\t# double 0.0" %}
6515   ins_encode %{
6516     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6517   %}
6518   ins_pipe( pipe_slow );
6519 %}
6520 
6521 // Load Stack Slot
6522 instruct loadSSI(rRegI dst, stackSlotI src) %{
6523   match(Set dst src);
6524   ins_cost(125);
6525 
6526   format %{ "MOV    $dst,$src" %}
6527   opcode(0x8B);
6528   ins_encode( OpcP, RegMem(dst,src));
6529   ins_pipe( ialu_reg_mem );
6530 %}
6531 
6532 instruct loadSSL(eRegL dst, stackSlotL src) %{
6533   match(Set dst src);
6534 
6535   ins_cost(200);
6536   format %{ "MOV    $dst,$src.lo\n\t"
6537             "MOV    $dst+4,$src.hi" %}
6538   opcode(0x8B, 0x8B);
6539   ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6540   ins_pipe( ialu_mem_long_reg );
6541 %}
6542 
6543 // Load Stack Slot
6544 instruct loadSSP(eRegP dst, stackSlotP src) %{
6545   match(Set dst src);
6546   ins_cost(125);
6547 
6548   format %{ "MOV    $dst,$src" %}
6549   opcode(0x8B);
6550   ins_encode( OpcP, RegMem(dst,src));
6551   ins_pipe( ialu_reg_mem );
6552 %}
6553 
6554 // Load Stack Slot
6555 instruct loadSSF(regFPR dst, stackSlotF src) %{
6556   match(Set dst src);
6557   ins_cost(125);
6558 
6559   format %{ "FLD_S  $src\n\t"
6560             "FSTP   $dst" %}
6561   opcode(0xD9);               /* D9 /0, FLD m32real */
6562   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6563               Pop_Reg_FPR(dst) );
6564   ins_pipe( fpu_reg_mem );
6565 %}
6566 
6567 // Load Stack Slot
6568 instruct loadSSD(regDPR dst, stackSlotD src) %{
6569   match(Set dst src);
6570   ins_cost(125);
6571 
6572   format %{ "FLD_D  $src\n\t"
6573             "FSTP   $dst" %}
6574   opcode(0xDD);               /* DD /0, FLD m64real */
6575   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6576               Pop_Reg_DPR(dst) );
6577   ins_pipe( fpu_reg_mem );
6578 %}
6579 
6580 // Prefetch instructions.
6581 // Must be safe to execute with invalid address (cannot fault).
6582 
6583 instruct prefetchr0( memory mem ) %{
6584   predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6585   match(PrefetchRead mem);
6586   ins_cost(0);
6587   size(0);
6588   format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6589   ins_encode();
6590   ins_pipe(empty);
6591 %}
6592 
6593 instruct prefetchr( memory mem ) %{
6594   predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6595   match(PrefetchRead mem);
6596   ins_cost(100);
6597 
6598   format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6599   ins_encode %{
6600     __ prefetchr($mem$$Address);
6601   %}
6602   ins_pipe(ialu_mem);
6603 %}
6604 
6605 instruct prefetchrNTA( memory mem ) %{
6606   predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6607   match(PrefetchRead mem);
6608   ins_cost(100);
6609 
6610   format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6611   ins_encode %{
6612     __ prefetchnta($mem$$Address);
6613   %}
6614   ins_pipe(ialu_mem);
6615 %}
6616 
6617 instruct prefetchrT0( memory mem ) %{
6618   predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6619   match(PrefetchRead mem);
6620   ins_cost(100);
6621 
6622   format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6623   ins_encode %{
6624     __ prefetcht0($mem$$Address);
6625   %}
6626   ins_pipe(ialu_mem);
6627 %}
6628 
6629 instruct prefetchrT2( memory mem ) %{
6630   predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6631   match(PrefetchRead mem);
6632   ins_cost(100);
6633 
6634   format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6635   ins_encode %{
6636     __ prefetcht2($mem$$Address);
6637   %}
6638   ins_pipe(ialu_mem);
6639 %}
6640 
6641 instruct prefetchw0( memory mem ) %{
6642   predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6643   match(PrefetchWrite mem);
6644   ins_cost(0);
6645   size(0);
6646   format %{ "Prefetch (non-SSE is empty encoding)" %}
6647   ins_encode();
6648   ins_pipe(empty);
6649 %}
6650 
6651 instruct prefetchw( memory mem ) %{
6652   predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6653   match( PrefetchWrite mem );
6654   ins_cost(100);
6655 
6656   format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6657   ins_encode %{
6658     __ prefetchw($mem$$Address);
6659   %}
6660   ins_pipe(ialu_mem);
6661 %}
6662 
6663 instruct prefetchwNTA( memory mem ) %{
6664   predicate(UseSSE>=1);
6665   match(PrefetchWrite mem);
6666   ins_cost(100);
6667 
6668   format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6669   ins_encode %{
6670     __ prefetchnta($mem$$Address);
6671   %}
6672   ins_pipe(ialu_mem);
6673 %}
6674 
6675 // Prefetch instructions for allocation.
6676 
6677 instruct prefetchAlloc0( memory mem ) %{
6678   predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6679   match(PrefetchAllocation mem);
6680   ins_cost(0);
6681   size(0);
6682   format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6683   ins_encode();
6684   ins_pipe(empty);
6685 %}
6686 
6687 instruct prefetchAlloc( memory mem ) %{
6688   predicate(AllocatePrefetchInstr==3);
6689   match( PrefetchAllocation mem );
6690   ins_cost(100);
6691 
6692   format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6693   ins_encode %{
6694     __ prefetchw($mem$$Address);
6695   %}
6696   ins_pipe(ialu_mem);
6697 %}
6698 
6699 instruct prefetchAllocNTA( memory mem ) %{
6700   predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6701   match(PrefetchAllocation mem);
6702   ins_cost(100);
6703 
6704   format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6705   ins_encode %{
6706     __ prefetchnta($mem$$Address);
6707   %}
6708   ins_pipe(ialu_mem);
6709 %}
6710 
6711 instruct prefetchAllocT0( memory mem ) %{
6712   predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6713   match(PrefetchAllocation mem);
6714   ins_cost(100);
6715 
6716   format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6717   ins_encode %{
6718     __ prefetcht0($mem$$Address);
6719   %}
6720   ins_pipe(ialu_mem);
6721 %}
6722 
6723 instruct prefetchAllocT2( memory mem ) %{
6724   predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6725   match(PrefetchAllocation mem);
6726   ins_cost(100);
6727 
6728   format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6729   ins_encode %{
6730     __ prefetcht2($mem$$Address);
6731   %}
6732   ins_pipe(ialu_mem);
6733 %}
6734 
6735 //----------Store Instructions-------------------------------------------------
6736 
6737 // Store Byte
6738 instruct storeB(memory mem, xRegI src) %{
6739   match(Set mem (StoreB mem src));
6740 
6741   ins_cost(125);
6742   format %{ "MOV8   $mem,$src" %}
6743   opcode(0x88);
6744   ins_encode( OpcP, RegMem( src, mem ) );
6745   ins_pipe( ialu_mem_reg );
6746 %}
6747 
6748 // Store Char/Short
6749 instruct storeC(memory mem, rRegI src) %{
6750   match(Set mem (StoreC mem src));
6751 
6752   ins_cost(125);
6753   format %{ "MOV16  $mem,$src" %}
6754   opcode(0x89, 0x66);
6755   ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6756   ins_pipe( ialu_mem_reg );
6757 %}
6758 
6759 // Store Integer
6760 instruct storeI(memory mem, rRegI src) %{
6761   match(Set mem (StoreI mem src));
6762 
6763   ins_cost(125);
6764   format %{ "MOV    $mem,$src" %}
6765   opcode(0x89);
6766   ins_encode( OpcP, RegMem( src, mem ) );
6767   ins_pipe( ialu_mem_reg );
6768 %}
6769 
6770 // Store Long
6771 instruct storeL(long_memory mem, eRegL src) %{
6772   predicate(!((StoreLNode*)n)->require_atomic_access());
6773   match(Set mem (StoreL mem src));
6774 
6775   ins_cost(200);
6776   format %{ "MOV    $mem,$src.lo\n\t"
6777             "MOV    $mem+4,$src.hi" %}
6778   opcode(0x89, 0x89);
6779   ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6780   ins_pipe( ialu_mem_long_reg );
6781 %}
6782 
6783 // Store Long to Integer
6784 instruct storeL2I(memory mem, eRegL src) %{
6785   match(Set mem (StoreI mem (ConvL2I src)));
6786 
6787   format %{ "MOV    $mem,$src.lo\t# long -> int" %}
6788   ins_encode %{
6789     __ movl($mem$$Address, $src$$Register);
6790   %}
6791   ins_pipe(ialu_mem_reg);
6792 %}
6793 
6794 // Volatile Store Long.  Must be atomic, so move it into
6795 // the FP TOS and then do a 64-bit FIST.  Has to probe the
6796 // target address before the store (for null-ptr checks)
6797 // so the memory operand is used twice in the encoding.
6798 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6799   predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6800   match(Set mem (StoreL mem src));
6801   effect( KILL cr );
6802   ins_cost(400);
6803   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6804             "FILD   $src\n\t"
6805             "FISTp  $mem\t # 64-bit atomic volatile long store" %}
6806   opcode(0x3B);
6807   ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6808   ins_pipe( fpu_reg_mem );
6809 %}
6810 
6811 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6812   predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6813   match(Set mem (StoreL mem src));
6814   effect( TEMP tmp, KILL cr );
6815   ins_cost(380);
6816   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6817             "MOVSD  $tmp,$src\n\t"
6818             "MOVSD  $mem,$tmp\t # 64-bit atomic volatile long store" %}
6819   ins_encode %{
6820     __ cmpl(rax, $mem$$Address);
6821     __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6822     __ movdbl($mem$$Address, $tmp$$XMMRegister);
6823   %}
6824   ins_pipe( pipe_slow );
6825 %}
6826 
6827 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6828   predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6829   match(Set mem (StoreL mem src));
6830   effect( TEMP tmp2 , TEMP tmp, KILL cr );
6831   ins_cost(360);
6832   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6833             "MOVD   $tmp,$src.lo\n\t"
6834             "MOVD   $tmp2,$src.hi\n\t"
6835             "PUNPCKLDQ $tmp,$tmp2\n\t"
6836             "MOVSD  $mem,$tmp\t # 64-bit atomic volatile long store" %}
6837   ins_encode %{
6838     __ cmpl(rax, $mem$$Address);
6839     __ movdl($tmp$$XMMRegister, $src$$Register);
6840     __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6841     __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6842     __ movdbl($mem$$Address, $tmp$$XMMRegister);
6843   %}
6844   ins_pipe( pipe_slow );
6845 %}
6846 
6847 // Store Pointer; for storing unknown oops and raw pointers
6848 instruct storeP(memory mem, anyRegP src) %{
6849   match(Set mem (StoreP mem src));
6850 
6851   ins_cost(125);
6852   format %{ "MOV    $mem,$src" %}
6853   opcode(0x89);
6854   ins_encode( OpcP, RegMem( src, mem ) );
6855   ins_pipe( ialu_mem_reg );
6856 %}
6857 
6858 // Store Integer Immediate
6859 instruct storeImmI(memory mem, immI src) %{
6860   match(Set mem (StoreI mem src));
6861 
6862   ins_cost(150);
6863   format %{ "MOV    $mem,$src" %}
6864   opcode(0xC7);               /* C7 /0 */
6865   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32( src ));
6866   ins_pipe( ialu_mem_imm );
6867 %}
6868 
6869 // Store Short/Char Immediate
6870 instruct storeImmI16(memory mem, immI16 src) %{
6871   predicate(UseStoreImmI16);
6872   match(Set mem (StoreC mem src));
6873 
6874   ins_cost(150);
6875   format %{ "MOV16  $mem,$src" %}
6876   opcode(0xC7);     /* C7 /0 Same as 32 store immediate with prefix */
6877   ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem),  Con16( src ));
6878   ins_pipe( ialu_mem_imm );
6879 %}
6880 
6881 // Store Pointer Immediate; null pointers or constant oops that do not
6882 // need card-mark barriers.
6883 instruct storeImmP(memory mem, immP src) %{
6884   match(Set mem (StoreP mem src));
6885 
6886   ins_cost(150);
6887   format %{ "MOV    $mem,$src" %}
6888   opcode(0xC7);               /* C7 /0 */
6889   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32( src ));
6890   ins_pipe( ialu_mem_imm );
6891 %}
6892 
6893 // Store Byte Immediate
6894 instruct storeImmB(memory mem, immI8 src) %{
6895   match(Set mem (StoreB mem src));
6896 
6897   ins_cost(150);
6898   format %{ "MOV8   $mem,$src" %}
6899   opcode(0xC6);               /* C6 /0 */
6900   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con8or32( src ));
6901   ins_pipe( ialu_mem_imm );
6902 %}
6903 
6904 // Store CMS card-mark Immediate
6905 instruct storeImmCM(memory mem, immI8 src) %{
6906   match(Set mem (StoreCM mem src));
6907 
6908   ins_cost(150);
6909   format %{ "MOV8   $mem,$src\t! CMS card-mark imm0" %}
6910   opcode(0xC6);               /* C6 /0 */
6911   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con8or32( src ));
6912   ins_pipe( ialu_mem_imm );
6913 %}
6914 
6915 // Store Double
6916 instruct storeDPR( memory mem, regDPR1 src) %{
6917   predicate(UseSSE<=1);
6918   match(Set mem (StoreD mem src));
6919 
6920   ins_cost(100);
6921   format %{ "FST_D  $mem,$src" %}
6922   opcode(0xDD);       /* DD /2 */
6923   ins_encode( enc_FPR_store(mem,src) );
6924   ins_pipe( fpu_mem_reg );
6925 %}
6926 
6927 // Store double does rounding on x86
6928 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6929   predicate(UseSSE<=1);
6930   match(Set mem (StoreD mem (RoundDouble src)));
6931 
6932   ins_cost(100);
6933   format %{ "FST_D  $mem,$src\t# round" %}
6934   opcode(0xDD);       /* DD /2 */
6935   ins_encode( enc_FPR_store(mem,src) );
6936   ins_pipe( fpu_mem_reg );
6937 %}
6938 
6939 // Store XMM register to memory (double-precision floating points)
6940 // MOVSD instruction
6941 instruct storeD(memory mem, regD src) %{
6942   predicate(UseSSE>=2);
6943   match(Set mem (StoreD mem src));
6944   ins_cost(95);
6945   format %{ "MOVSD  $mem,$src" %}
6946   ins_encode %{
6947     __ movdbl($mem$$Address, $src$$XMMRegister);
6948   %}
6949   ins_pipe( pipe_slow );
6950 %}
6951 
6952 // Store XMM register to memory (single-precision floating point)
6953 // MOVSS instruction
6954 instruct storeF(memory mem, regF src) %{
6955   predicate(UseSSE>=1);
6956   match(Set mem (StoreF mem src));
6957   ins_cost(95);
6958   format %{ "MOVSS  $mem,$src" %}
6959   ins_encode %{
6960     __ movflt($mem$$Address, $src$$XMMRegister);
6961   %}
6962   ins_pipe( pipe_slow );
6963 %}
6964 
6965 // Store Float
6966 instruct storeFPR( memory mem, regFPR1 src) %{
6967   predicate(UseSSE==0);
6968   match(Set mem (StoreF mem src));
6969 
6970   ins_cost(100);
6971   format %{ "FST_S  $mem,$src" %}
6972   opcode(0xD9);       /* D9 /2 */
6973   ins_encode( enc_FPR_store(mem,src) );
6974   ins_pipe( fpu_mem_reg );
6975 %}
6976 
6977 // Store Float does rounding on x86
6978 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6979   predicate(UseSSE==0);
6980   match(Set mem (StoreF mem (RoundFloat src)));
6981 
6982   ins_cost(100);
6983   format %{ "FST_S  $mem,$src\t# round" %}
6984   opcode(0xD9);       /* D9 /2 */
6985   ins_encode( enc_FPR_store(mem,src) );
6986   ins_pipe( fpu_mem_reg );
6987 %}
6988 
6989 // Store Float does rounding on x86
6990 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6991   predicate(UseSSE<=1);
6992   match(Set mem (StoreF mem (ConvD2F src)));
6993 
6994   ins_cost(100);
6995   format %{ "FST_S  $mem,$src\t# D-round" %}
6996   opcode(0xD9);       /* D9 /2 */
6997   ins_encode( enc_FPR_store(mem,src) );
6998   ins_pipe( fpu_mem_reg );
6999 %}
7000 
7001 // Store immediate Float value (it is faster than store from FPU register)
7002 // The instruction usage is guarded by predicate in operand immFPR().
7003 instruct storeFPR_imm( memory mem, immFPR src) %{
7004   match(Set mem (StoreF mem src));
7005 
7006   ins_cost(50);
7007   format %{ "MOV    $mem,$src\t# store float" %}
7008   opcode(0xC7);               /* C7 /0 */
7009   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32FPR_as_bits( src ));
7010   ins_pipe( ialu_mem_imm );
7011 %}
7012 
7013 // Store immediate Float value (it is faster than store from XMM register)
7014 // The instruction usage is guarded by predicate in operand immF().
7015 instruct storeF_imm( memory mem, immF src) %{
7016   match(Set mem (StoreF mem src));
7017 
7018   ins_cost(50);
7019   format %{ "MOV    $mem,$src\t# store float" %}
7020   opcode(0xC7);               /* C7 /0 */
7021   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32F_as_bits( src ));
7022   ins_pipe( ialu_mem_imm );
7023 %}
7024 
7025 // Store Integer to stack slot
7026 instruct storeSSI(stackSlotI dst, rRegI src) %{
7027   match(Set dst src);
7028 
7029   ins_cost(100);
7030   format %{ "MOV    $dst,$src" %}
7031   opcode(0x89);
7032   ins_encode( OpcPRegSS( dst, src ) );
7033   ins_pipe( ialu_mem_reg );
7034 %}
7035 
7036 // Store Integer to stack slot
7037 instruct storeSSP(stackSlotP dst, eRegP src) %{
7038   match(Set dst src);
7039 
7040   ins_cost(100);
7041   format %{ "MOV    $dst,$src" %}
7042   opcode(0x89);
7043   ins_encode( OpcPRegSS( dst, src ) );
7044   ins_pipe( ialu_mem_reg );
7045 %}
7046 
7047 // Store Long to stack slot
7048 instruct storeSSL(stackSlotL dst, eRegL src) %{
7049   match(Set dst src);
7050 
7051   ins_cost(200);
7052   format %{ "MOV    $dst,$src.lo\n\t"
7053             "MOV    $dst+4,$src.hi" %}
7054   opcode(0x89, 0x89);
7055   ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7056   ins_pipe( ialu_mem_long_reg );
7057 %}
7058 
7059 //----------MemBar Instructions-----------------------------------------------
7060 // Memory barrier flavors
7061 
7062 instruct membar_acquire() %{
7063   match(MemBarAcquire);
7064   ins_cost(400);
7065 
7066   size(0);
7067   format %{ "MEMBAR-acquire ! (empty encoding)" %}
7068   ins_encode();
7069   ins_pipe(empty);
7070 %}
7071 
7072 instruct membar_acquire_lock() %{
7073   match(MemBarAcquireLock);
7074   ins_cost(0);
7075 
7076   size(0);
7077   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7078   ins_encode( );
7079   ins_pipe(empty);
7080 %}
7081 
7082 instruct membar_release() %{
7083   match(MemBarRelease);
7084   ins_cost(400);
7085 
7086   size(0);
7087   format %{ "MEMBAR-release ! (empty encoding)" %}
7088   ins_encode( );
7089   ins_pipe(empty);
7090 %}
7091 
7092 instruct membar_release_lock() %{
7093   match(MemBarReleaseLock);
7094   ins_cost(0);
7095 
7096   size(0);
7097   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7098   ins_encode( );
7099   ins_pipe(empty);
7100 %}
7101 
7102 instruct membar_volatile(eFlagsReg cr) %{
7103   match(MemBarVolatile);
7104   effect(KILL cr);
7105   ins_cost(400);
7106 
7107   format %{ 
7108     $$template
7109     if (os::is_MP()) {
7110       $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7111     } else {
7112       $$emit$$"MEMBAR-volatile ! (empty encoding)"
7113     }
7114   %}
7115   ins_encode %{
7116     __ membar(Assembler::StoreLoad);
7117   %}
7118   ins_pipe(pipe_slow);
7119 %}
7120 
7121 instruct unnecessary_membar_volatile() %{
7122   match(MemBarVolatile);
7123   predicate(Matcher::post_store_load_barrier(n));
7124   ins_cost(0);
7125 
7126   size(0);
7127   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7128   ins_encode( );
7129   ins_pipe(empty);
7130 %}
7131 
7132 instruct membar_storestore() %{
7133   match(MemBarStoreStore);
7134   ins_cost(0);
7135 
7136   size(0);
7137   format %{ "MEMBAR-storestore (empty encoding)" %}
7138   ins_encode( );
7139   ins_pipe(empty);
7140 %}
7141 
7142 //----------Move Instructions--------------------------------------------------
7143 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7144   match(Set dst (CastX2P src));
7145   format %{ "# X2P  $dst, $src" %}
7146   ins_encode( /*empty encoding*/ );
7147   ins_cost(0);
7148   ins_pipe(empty);
7149 %}
7150 
7151 instruct castP2X(rRegI dst, eRegP src ) %{
7152   match(Set dst (CastP2X src));
7153   ins_cost(50);
7154   format %{ "MOV    $dst, $src\t# CastP2X" %}
7155   ins_encode( enc_Copy( dst, src) );
7156   ins_pipe( ialu_reg_reg );
7157 %}
7158 
7159 //----------Conditional Move---------------------------------------------------
7160 // Conditional move
7161 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7162   predicate(!VM_Version::supports_cmov() );
7163   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7164   ins_cost(200);
7165   format %{ "J$cop,us skip\t# signed cmove\n\t"
7166             "MOV    $dst,$src\n"
7167       "skip:" %}
7168   ins_encode %{
7169     Label Lskip;
7170     // Invert sense of branch from sense of CMOV
7171     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7172     __ movl($dst$$Register, $src$$Register);
7173     __ bind(Lskip);
7174   %}
7175   ins_pipe( pipe_cmov_reg );
7176 %}
7177 
7178 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7179   predicate(!VM_Version::supports_cmov() );
7180   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7181   ins_cost(200);
7182   format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7183             "MOV    $dst,$src\n"
7184       "skip:" %}
7185   ins_encode %{
7186     Label Lskip;
7187     // Invert sense of branch from sense of CMOV
7188     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7189     __ movl($dst$$Register, $src$$Register);
7190     __ bind(Lskip);
7191   %}
7192   ins_pipe( pipe_cmov_reg );
7193 %}
7194 
7195 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7196   predicate(VM_Version::supports_cmov() );
7197   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7198   ins_cost(200);
7199   format %{ "CMOV$cop $dst,$src" %}
7200   opcode(0x0F,0x40);
7201   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7202   ins_pipe( pipe_cmov_reg );
7203 %}
7204 
7205 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7206   predicate(VM_Version::supports_cmov() );
7207   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7208   ins_cost(200);
7209   format %{ "CMOV$cop $dst,$src" %}
7210   opcode(0x0F,0x40);
7211   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7212   ins_pipe( pipe_cmov_reg );
7213 %}
7214 
7215 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7216   predicate(VM_Version::supports_cmov() );
7217   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7218   ins_cost(200);
7219   expand %{
7220     cmovI_regU(cop, cr, dst, src);
7221   %}
7222 %}
7223 
7224 // Conditional move
7225 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7226   predicate(VM_Version::supports_cmov() );
7227   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7228   ins_cost(250);
7229   format %{ "CMOV$cop $dst,$src" %}
7230   opcode(0x0F,0x40);
7231   ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7232   ins_pipe( pipe_cmov_mem );
7233 %}
7234 
7235 // Conditional move
7236 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7237   predicate(VM_Version::supports_cmov() );
7238   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7239   ins_cost(250);
7240   format %{ "CMOV$cop $dst,$src" %}
7241   opcode(0x0F,0x40);
7242   ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7243   ins_pipe( pipe_cmov_mem );
7244 %}
7245 
7246 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7247   predicate(VM_Version::supports_cmov() );
7248   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7249   ins_cost(250);
7250   expand %{
7251     cmovI_memU(cop, cr, dst, src);
7252   %}
7253 %}
7254 
7255 // Conditional move
7256 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7257   predicate(VM_Version::supports_cmov() );
7258   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7259   ins_cost(200);
7260   format %{ "CMOV$cop $dst,$src\t# ptr" %}
7261   opcode(0x0F,0x40);
7262   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7263   ins_pipe( pipe_cmov_reg );
7264 %}
7265 
7266 // Conditional move (non-P6 version)
7267 // Note:  a CMoveP is generated for  stubs and native wrappers
7268 //        regardless of whether we are on a P6, so we
7269 //        emulate a cmov here
7270 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7271   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7272   ins_cost(300);
7273   format %{ "Jn$cop   skip\n\t"
7274           "MOV    $dst,$src\t# pointer\n"
7275       "skip:" %}
7276   opcode(0x8b);
7277   ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7278   ins_pipe( pipe_cmov_reg );
7279 %}
7280 
7281 // Conditional move
7282 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7283   predicate(VM_Version::supports_cmov() );
7284   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7285   ins_cost(200);
7286   format %{ "CMOV$cop $dst,$src\t# ptr" %}
7287   opcode(0x0F,0x40);
7288   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7289   ins_pipe( pipe_cmov_reg );
7290 %}
7291 
7292 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7293   predicate(VM_Version::supports_cmov() );
7294   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7295   ins_cost(200);
7296   expand %{
7297     cmovP_regU(cop, cr, dst, src);
7298   %}
7299 %}
7300 
7301 // DISABLED: Requires the ADLC to emit a bottom_type call that
7302 // correctly meets the two pointer arguments; one is an incoming
7303 // register but the other is a memory operand.  ALSO appears to
7304 // be buggy with implicit null checks.
7305 //
7306 //// Conditional move
7307 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7308 //  predicate(VM_Version::supports_cmov() );
7309 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7310 //  ins_cost(250);
7311 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7312 //  opcode(0x0F,0x40);
7313 //  ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7314 //  ins_pipe( pipe_cmov_mem );
7315 //%}
7316 //
7317 //// Conditional move
7318 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7319 //  predicate(VM_Version::supports_cmov() );
7320 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7321 //  ins_cost(250);
7322 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7323 //  opcode(0x0F,0x40);
7324 //  ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7325 //  ins_pipe( pipe_cmov_mem );
7326 //%}
7327 
7328 // Conditional move
7329 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7330   predicate(UseSSE<=1);
7331   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7332   ins_cost(200);
7333   format %{ "FCMOV$cop $dst,$src\t# double" %}
7334   opcode(0xDA);
7335   ins_encode( enc_cmov_dpr(cop,src) );
7336   ins_pipe( pipe_cmovDPR_reg );
7337 %}
7338 
7339 // Conditional move
7340 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7341   predicate(UseSSE==0);
7342   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7343   ins_cost(200);
7344   format %{ "FCMOV$cop $dst,$src\t# float" %}
7345   opcode(0xDA);
7346   ins_encode( enc_cmov_dpr(cop,src) );
7347   ins_pipe( pipe_cmovDPR_reg );
7348 %}
7349 
7350 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7351 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7352   predicate(UseSSE<=1);
7353   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7354   ins_cost(200);
7355   format %{ "Jn$cop   skip\n\t"
7356             "MOV    $dst,$src\t# double\n"
7357       "skip:" %}
7358   opcode (0xdd, 0x3);     /* DD D8+i or DD /3 */
7359   ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7360   ins_pipe( pipe_cmovDPR_reg );
7361 %}
7362 
7363 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7364 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7365   predicate(UseSSE==0);
7366   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7367   ins_cost(200);
7368   format %{ "Jn$cop    skip\n\t"
7369             "MOV    $dst,$src\t# float\n"
7370       "skip:" %}
7371   opcode (0xdd, 0x3);     /* DD D8+i or DD /3 */
7372   ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7373   ins_pipe( pipe_cmovDPR_reg );
7374 %}
7375 
7376 // No CMOVE with SSE/SSE2
7377 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7378   predicate (UseSSE>=1);
7379   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7380   ins_cost(200);
7381   format %{ "Jn$cop   skip\n\t"
7382             "MOVSS  $dst,$src\t# float\n"
7383       "skip:" %}
7384   ins_encode %{
7385     Label skip;
7386     // Invert sense of branch from sense of CMOV
7387     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7388     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7389     __ bind(skip);
7390   %}
7391   ins_pipe( pipe_slow );
7392 %}
7393 
7394 // No CMOVE with SSE/SSE2
7395 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7396   predicate (UseSSE>=2);
7397   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7398   ins_cost(200);
7399   format %{ "Jn$cop   skip\n\t"
7400             "MOVSD  $dst,$src\t# float\n"
7401       "skip:" %}
7402   ins_encode %{
7403     Label skip;
7404     // Invert sense of branch from sense of CMOV
7405     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7406     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7407     __ bind(skip);
7408   %}
7409   ins_pipe( pipe_slow );
7410 %}
7411 
7412 // unsigned version
7413 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7414   predicate (UseSSE>=1);
7415   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7416   ins_cost(200);
7417   format %{ "Jn$cop   skip\n\t"
7418             "MOVSS  $dst,$src\t# float\n"
7419       "skip:" %}
7420   ins_encode %{
7421     Label skip;
7422     // Invert sense of branch from sense of CMOV
7423     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7424     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7425     __ bind(skip);
7426   %}
7427   ins_pipe( pipe_slow );
7428 %}
7429 
7430 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7431   predicate (UseSSE>=1);
7432   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7433   ins_cost(200);
7434   expand %{
7435     fcmovF_regU(cop, cr, dst, src);
7436   %}
7437 %}
7438 
7439 // unsigned version
7440 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7441   predicate (UseSSE>=2);
7442   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7443   ins_cost(200);
7444   format %{ "Jn$cop   skip\n\t"
7445             "MOVSD  $dst,$src\t# float\n"
7446       "skip:" %}
7447   ins_encode %{
7448     Label skip;
7449     // Invert sense of branch from sense of CMOV
7450     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7451     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7452     __ bind(skip);
7453   %}
7454   ins_pipe( pipe_slow );
7455 %}
7456 
7457 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7458   predicate (UseSSE>=2);
7459   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7460   ins_cost(200);
7461   expand %{
7462     fcmovD_regU(cop, cr, dst, src);
7463   %}
7464 %}
7465 
7466 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7467   predicate(VM_Version::supports_cmov() );
7468   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7469   ins_cost(200);
7470   format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7471             "CMOV$cop $dst.hi,$src.hi" %}
7472   opcode(0x0F,0x40);
7473   ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7474   ins_pipe( pipe_cmov_reg_long );
7475 %}
7476 
7477 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7478   predicate(VM_Version::supports_cmov() );
7479   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7480   ins_cost(200);
7481   format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7482             "CMOV$cop $dst.hi,$src.hi" %}
7483   opcode(0x0F,0x40);
7484   ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7485   ins_pipe( pipe_cmov_reg_long );
7486 %}
7487 
7488 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7489   predicate(VM_Version::supports_cmov() );
7490   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7491   ins_cost(200);
7492   expand %{
7493     cmovL_regU(cop, cr, dst, src);
7494   %}
7495 %}
7496 
7497 //----------Arithmetic Instructions--------------------------------------------
7498 //----------Addition Instructions----------------------------------------------
7499 // Integer Addition Instructions
7500 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7501   match(Set dst (AddI dst src));
7502   effect(KILL cr);
7503 
7504   size(2);
7505   format %{ "ADD    $dst,$src" %}
7506   opcode(0x03);
7507   ins_encode( OpcP, RegReg( dst, src) );
7508   ins_pipe( ialu_reg_reg );
7509 %}
7510 
7511 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7512   match(Set dst (AddI dst src));
7513   effect(KILL cr);
7514 
7515   format %{ "ADD    $dst,$src" %}
7516   opcode(0x81, 0x00); /* /0 id */
7517   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7518   ins_pipe( ialu_reg );
7519 %}
7520 
7521 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7522   predicate(UseIncDec);
7523   match(Set dst (AddI dst src));
7524   effect(KILL cr);
7525 
7526   size(1);
7527   format %{ "INC    $dst" %}
7528   opcode(0x40); /*  */
7529   ins_encode( Opc_plus( primary, dst ) );
7530   ins_pipe( ialu_reg );
7531 %}
7532 
7533 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7534   match(Set dst (AddI src0 src1));
7535   ins_cost(110);
7536 
7537   format %{ "LEA    $dst,[$src0 + $src1]" %}
7538   opcode(0x8D); /* 0x8D /r */
7539   ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7540   ins_pipe( ialu_reg_reg );
7541 %}
7542 
7543 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7544   match(Set dst (AddP src0 src1));
7545   ins_cost(110);
7546 
7547   format %{ "LEA    $dst,[$src0 + $src1]\t# ptr" %}
7548   opcode(0x8D); /* 0x8D /r */
7549   ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7550   ins_pipe( ialu_reg_reg );
7551 %}
7552 
7553 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7554   predicate(UseIncDec);
7555   match(Set dst (AddI dst src));
7556   effect(KILL cr);
7557 
7558   size(1);
7559   format %{ "DEC    $dst" %}
7560   opcode(0x48); /*  */
7561   ins_encode( Opc_plus( primary, dst ) );
7562   ins_pipe( ialu_reg );
7563 %}
7564 
7565 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7566   match(Set dst (AddP dst src));
7567   effect(KILL cr);
7568 
7569   size(2);
7570   format %{ "ADD    $dst,$src" %}
7571   opcode(0x03);
7572   ins_encode( OpcP, RegReg( dst, src) );
7573   ins_pipe( ialu_reg_reg );
7574 %}
7575 
7576 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7577   match(Set dst (AddP dst src));
7578   effect(KILL cr);
7579 
7580   format %{ "ADD    $dst,$src" %}
7581   opcode(0x81,0x00); /* Opcode 81 /0 id */
7582   // ins_encode( RegImm( dst, src) );
7583   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7584   ins_pipe( ialu_reg );
7585 %}
7586 
7587 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7588   match(Set dst (AddI dst (LoadI src)));
7589   effect(KILL cr);
7590 
7591   ins_cost(125);
7592   format %{ "ADD    $dst,$src" %}
7593   opcode(0x03);
7594   ins_encode( OpcP, RegMem( dst, src) );
7595   ins_pipe( ialu_reg_mem );
7596 %}
7597 
7598 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7599   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7600   effect(KILL cr);
7601 
7602   ins_cost(150);
7603   format %{ "ADD    $dst,$src" %}
7604   opcode(0x01);  /* Opcode 01 /r */
7605   ins_encode( OpcP, RegMem( src, dst ) );
7606   ins_pipe( ialu_mem_reg );
7607 %}
7608 
7609 // Add Memory with Immediate
7610 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7611   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7612   effect(KILL cr);
7613 
7614   ins_cost(125);
7615   format %{ "ADD    $dst,$src" %}
7616   opcode(0x81);               /* Opcode 81 /0 id */
7617   ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7618   ins_pipe( ialu_mem_imm );
7619 %}
7620 
7621 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7622   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7623   effect(KILL cr);
7624 
7625   ins_cost(125);
7626   format %{ "INC    $dst" %}
7627   opcode(0xFF);               /* Opcode FF /0 */
7628   ins_encode( OpcP, RMopc_Mem(0x00,dst));
7629   ins_pipe( ialu_mem_imm );
7630 %}
7631 
7632 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7633   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7634   effect(KILL cr);
7635 
7636   ins_cost(125);
7637   format %{ "DEC    $dst" %}
7638   opcode(0xFF);               /* Opcode FF /1 */
7639   ins_encode( OpcP, RMopc_Mem(0x01,dst));
7640   ins_pipe( ialu_mem_imm );
7641 %}
7642 
7643 
7644 instruct checkCastPP( eRegP dst ) %{
7645   match(Set dst (CheckCastPP dst));
7646 
7647   size(0);
7648   format %{ "#checkcastPP of $dst" %}
7649   ins_encode( /*empty encoding*/ );
7650   ins_pipe( empty );
7651 %}
7652 
7653 instruct castPP( eRegP dst ) %{
7654   match(Set dst (CastPP dst));
7655   format %{ "#castPP of $dst" %}
7656   ins_encode( /*empty encoding*/ );
7657   ins_pipe( empty );
7658 %}
7659 
7660 instruct castII( rRegI dst ) %{
7661   match(Set dst (CastII dst));
7662   format %{ "#castII of $dst" %}
7663   ins_encode( /*empty encoding*/ );
7664   ins_cost(0);
7665   ins_pipe( empty );
7666 %}
7667 
7668 
7669 // Load-locked - same as a regular pointer load when used with compare-swap
7670 instruct loadPLocked(eRegP dst, memory mem) %{
7671   match(Set dst (LoadPLocked mem));
7672 
7673   ins_cost(125);
7674   format %{ "MOV    $dst,$mem\t# Load ptr. locked" %}
7675   opcode(0x8B);
7676   ins_encode( OpcP, RegMem(dst,mem));
7677   ins_pipe( ialu_reg_mem );
7678 %}
7679 
7680 // Conditional-store of the updated heap-top.
7681 // Used during allocation of the shared heap.
7682 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
7683 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7684   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7685   // EAX is killed if there is contention, but then it's also unused.
7686   // In the common case of no contention, EAX holds the new oop address.
7687   format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7688   ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7689   ins_pipe( pipe_cmpxchg );
7690 %}
7691 
7692 // Conditional-store of an int value.
7693 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG on Intel.
7694 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7695   match(Set cr (StoreIConditional mem (Binary oldval newval)));
7696   effect(KILL oldval);
7697   format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7698   ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7699   ins_pipe( pipe_cmpxchg );
7700 %}
7701 
7702 // Conditional-store of a long value.
7703 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG8 on Intel.
7704 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7705   match(Set cr (StoreLConditional mem (Binary oldval newval)));
7706   effect(KILL oldval);
7707   format %{ "XCHG   EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7708             "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7709             "XCHG   EBX,ECX"
7710   %}
7711   ins_encode %{
7712     // Note: we need to swap rbx, and rcx before and after the
7713     //       cmpxchg8 instruction because the instruction uses
7714     //       rcx as the high order word of the new value to store but
7715     //       our register encoding uses rbx.
7716     __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7717     if( os::is_MP() )
7718       __ lock();
7719     __ cmpxchg8($mem$$Address);
7720     __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7721   %}
7722   ins_pipe( pipe_cmpxchg );
7723 %}
7724 
7725 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7726 
7727 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7728   predicate(VM_Version::supports_cx8());
7729   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7730   effect(KILL cr, KILL oldval);
7731   format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7732             "MOV    $res,0\n\t"
7733             "JNE,s  fail\n\t"
7734             "MOV    $res,1\n"
7735           "fail:" %}
7736   ins_encode( enc_cmpxchg8(mem_ptr),
7737               enc_flags_ne_to_boolean(res) );
7738   ins_pipe( pipe_cmpxchg );
7739 %}
7740 
7741 instruct compareAndSwapP( rRegI res,  pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7742   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7743   effect(KILL cr, KILL oldval);
7744   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7745             "MOV    $res,0\n\t"
7746             "JNE,s  fail\n\t"
7747             "MOV    $res,1\n"
7748           "fail:" %}
7749   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7750   ins_pipe( pipe_cmpxchg );
7751 %}
7752 
7753 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7754   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7755   effect(KILL cr, KILL oldval);
7756   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7757             "MOV    $res,0\n\t"
7758             "JNE,s  fail\n\t"
7759             "MOV    $res,1\n"
7760           "fail:" %}
7761   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7762   ins_pipe( pipe_cmpxchg );
7763 %}
7764 
7765 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7766   predicate(n->as_LoadStore()->result_not_used());
7767   match(Set dummy (GetAndAddI mem add));
7768   effect(KILL cr);
7769   format %{ "ADDL  [$mem],$add" %}
7770   ins_encode %{
7771     if (os::is_MP()) { __ lock(); }
7772     __ addl($mem$$Address, $add$$constant);
7773   %}
7774   ins_pipe( pipe_cmpxchg );
7775 %}
7776 
7777 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7778   match(Set newval (GetAndAddI mem newval));
7779   effect(KILL cr);
7780   format %{ "XADDL  [$mem],$newval" %}
7781   ins_encode %{
7782     if (os::is_MP()) { __ lock(); }
7783     __ xaddl($mem$$Address, $newval$$Register);
7784   %}
7785   ins_pipe( pipe_cmpxchg );
7786 %}
7787 
7788 instruct xchgI( memory mem, rRegI newval) %{
7789   match(Set newval (GetAndSetI mem newval));
7790   format %{ "XCHGL  $newval,[$mem]" %}
7791   ins_encode %{
7792     __ xchgl($newval$$Register, $mem$$Address);
7793   %}
7794   ins_pipe( pipe_cmpxchg );
7795 %}
7796 
7797 instruct xchgP( memory mem, pRegP newval) %{
7798   match(Set newval (GetAndSetP mem newval));
7799   format %{ "XCHGL  $newval,[$mem]" %}
7800   ins_encode %{
7801     __ xchgl($newval$$Register, $mem$$Address);
7802   %}
7803   ins_pipe( pipe_cmpxchg );
7804 %}
7805 
7806 //----------Subtraction Instructions-------------------------------------------
7807 // Integer Subtraction Instructions
7808 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7809   match(Set dst (SubI dst src));
7810   effect(KILL cr);
7811 
7812   size(2);
7813   format %{ "SUB    $dst,$src" %}
7814   opcode(0x2B);
7815   ins_encode( OpcP, RegReg( dst, src) );
7816   ins_pipe( ialu_reg_reg );
7817 %}
7818 
7819 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7820   match(Set dst (SubI dst src));
7821   effect(KILL cr);
7822 
7823   format %{ "SUB    $dst,$src" %}
7824   opcode(0x81,0x05);  /* Opcode 81 /5 */
7825   // ins_encode( RegImm( dst, src) );
7826   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7827   ins_pipe( ialu_reg );
7828 %}
7829 
7830 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7831   match(Set dst (SubI dst (LoadI src)));
7832   effect(KILL cr);
7833 
7834   ins_cost(125);
7835   format %{ "SUB    $dst,$src" %}
7836   opcode(0x2B);
7837   ins_encode( OpcP, RegMem( dst, src) );
7838   ins_pipe( ialu_reg_mem );
7839 %}
7840 
7841 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7842   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7843   effect(KILL cr);
7844 
7845   ins_cost(150);
7846   format %{ "SUB    $dst,$src" %}
7847   opcode(0x29);  /* Opcode 29 /r */
7848   ins_encode( OpcP, RegMem( src, dst ) );
7849   ins_pipe( ialu_mem_reg );
7850 %}
7851 
7852 // Subtract from a pointer
7853 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7854   match(Set dst (AddP dst (SubI zero src)));
7855   effect(KILL cr);
7856 
7857   size(2);
7858   format %{ "SUB    $dst,$src" %}
7859   opcode(0x2B);
7860   ins_encode( OpcP, RegReg( dst, src) );
7861   ins_pipe( ialu_reg_reg );
7862 %}
7863 
7864 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7865   match(Set dst (SubI zero dst));
7866   effect(KILL cr);
7867 
7868   size(2);
7869   format %{ "NEG    $dst" %}
7870   opcode(0xF7,0x03);  // Opcode F7 /3
7871   ins_encode( OpcP, RegOpc( dst ) );
7872   ins_pipe( ialu_reg );
7873 %}
7874 
7875 
7876 //----------Multiplication/Division Instructions-------------------------------
7877 // Integer Multiplication Instructions
7878 // Multiply Register
7879 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7880   match(Set dst (MulI dst src));
7881   effect(KILL cr);
7882 
7883   size(3);
7884   ins_cost(300);
7885   format %{ "IMUL   $dst,$src" %}
7886   opcode(0xAF, 0x0F);
7887   ins_encode( OpcS, OpcP, RegReg( dst, src) );
7888   ins_pipe( ialu_reg_reg_alu0 );
7889 %}
7890 
7891 // Multiply 32-bit Immediate
7892 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7893   match(Set dst (MulI src imm));
7894   effect(KILL cr);
7895 
7896   ins_cost(300);
7897   format %{ "IMUL   $dst,$src,$imm" %}
7898   opcode(0x69);  /* 69 /r id */
7899   ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7900   ins_pipe( ialu_reg_reg_alu0 );
7901 %}
7902 
7903 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7904   match(Set dst src);
7905   effect(KILL cr);
7906 
7907   // Note that this is artificially increased to make it more expensive than loadConL
7908   ins_cost(250);
7909   format %{ "MOV    EAX,$src\t// low word only" %}
7910   opcode(0xB8);
7911   ins_encode( LdImmL_Lo(dst, src) );
7912   ins_pipe( ialu_reg_fat );
7913 %}
7914 
7915 // Multiply by 32-bit Immediate, taking the shifted high order results
7916 //  (special case for shift by 32)
7917 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7918   match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7919   predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7920              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7921              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7922   effect(USE src1, KILL cr);
7923 
7924   // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7925   ins_cost(0*100 + 1*400 - 150);
7926   format %{ "IMUL   EDX:EAX,$src1" %}
7927   ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7928   ins_pipe( pipe_slow );
7929 %}
7930 
7931 // Multiply by 32-bit Immediate, taking the shifted high order results
7932 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7933   match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7934   predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7935              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7936              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7937   effect(USE src1, KILL cr);
7938 
7939   // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7940   ins_cost(1*100 + 1*400 - 150);
7941   format %{ "IMUL   EDX:EAX,$src1\n\t"
7942             "SAR    EDX,$cnt-32" %}
7943   ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7944   ins_pipe( pipe_slow );
7945 %}
7946 
7947 // Multiply Memory 32-bit Immediate
7948 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7949   match(Set dst (MulI (LoadI src) imm));
7950   effect(KILL cr);
7951 
7952   ins_cost(300);
7953   format %{ "IMUL   $dst,$src,$imm" %}
7954   opcode(0x69);  /* 69 /r id */
7955   ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7956   ins_pipe( ialu_reg_mem_alu0 );
7957 %}
7958 
7959 // Multiply Memory
7960 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7961   match(Set dst (MulI dst (LoadI src)));
7962   effect(KILL cr);
7963 
7964   ins_cost(350);
7965   format %{ "IMUL   $dst,$src" %}
7966   opcode(0xAF, 0x0F);
7967   ins_encode( OpcS, OpcP, RegMem( dst, src) );
7968   ins_pipe( ialu_reg_mem_alu0 );
7969 %}
7970 
7971 // Multiply Register Int to Long
7972 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7973   // Basic Idea: long = (long)int * (long)int
7974   match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7975   effect(DEF dst, USE src, USE src1, KILL flags);
7976 
7977   ins_cost(300);
7978   format %{ "IMUL   $dst,$src1" %}
7979 
7980   ins_encode( long_int_multiply( dst, src1 ) );
7981   ins_pipe( ialu_reg_reg_alu0 );
7982 %}
7983 
7984 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7985   // Basic Idea:  long = (int & 0xffffffffL) * (int & 0xffffffffL)
7986   match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7987   effect(KILL flags);
7988 
7989   ins_cost(300);
7990   format %{ "MUL    $dst,$src1" %}
7991 
7992   ins_encode( long_uint_multiply(dst, src1) );
7993   ins_pipe( ialu_reg_reg_alu0 );
7994 %}
7995 
7996 // Multiply Register Long
7997 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7998   match(Set dst (MulL dst src));
7999   effect(KILL cr, TEMP tmp);
8000   ins_cost(4*100+3*400);
8001 // Basic idea: lo(result) = lo(x_lo * y_lo)
8002 //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8003   format %{ "MOV    $tmp,$src.lo\n\t"
8004             "IMUL   $tmp,EDX\n\t"
8005             "MOV    EDX,$src.hi\n\t"
8006             "IMUL   EDX,EAX\n\t"
8007             "ADD    $tmp,EDX\n\t"
8008             "MUL    EDX:EAX,$src.lo\n\t"
8009             "ADD    EDX,$tmp" %}
8010   ins_encode( long_multiply( dst, src, tmp ) );
8011   ins_pipe( pipe_slow );
8012 %}
8013 
8014 // Multiply Register Long where the left operand's high 32 bits are zero
8015 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8016   predicate(is_operand_hi32_zero(n->in(1)));
8017   match(Set dst (MulL dst src));
8018   effect(KILL cr, TEMP tmp);
8019   ins_cost(2*100+2*400);
8020 // Basic idea: lo(result) = lo(x_lo * y_lo)
8021 //             hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8022   format %{ "MOV    $tmp,$src.hi\n\t"
8023             "IMUL   $tmp,EAX\n\t"
8024             "MUL    EDX:EAX,$src.lo\n\t"
8025             "ADD    EDX,$tmp" %}
8026   ins_encode %{
8027     __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8028     __ imull($tmp$$Register, rax);
8029     __ mull($src$$Register);
8030     __ addl(rdx, $tmp$$Register);
8031   %}
8032   ins_pipe( pipe_slow );
8033 %}
8034 
8035 // Multiply Register Long where the right operand's high 32 bits are zero
8036 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8037   predicate(is_operand_hi32_zero(n->in(2)));
8038   match(Set dst (MulL dst src));
8039   effect(KILL cr, TEMP tmp);
8040   ins_cost(2*100+2*400);
8041 // Basic idea: lo(result) = lo(x_lo * y_lo)
8042 //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8043   format %{ "MOV    $tmp,$src.lo\n\t"
8044             "IMUL   $tmp,EDX\n\t"
8045             "MUL    EDX:EAX,$src.lo\n\t"
8046             "ADD    EDX,$tmp" %}
8047   ins_encode %{
8048     __ movl($tmp$$Register, $src$$Register);
8049     __ imull($tmp$$Register, rdx);
8050     __ mull($src$$Register);
8051     __ addl(rdx, $tmp$$Register);
8052   %}
8053   ins_pipe( pipe_slow );
8054 %}
8055 
8056 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8057 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8058   predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8059   match(Set dst (MulL dst src));
8060   effect(KILL cr);
8061   ins_cost(1*400);
8062 // Basic idea: lo(result) = lo(x_lo * y_lo)
8063 //             hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8064   format %{ "MUL    EDX:EAX,$src.lo\n\t" %}
8065   ins_encode %{
8066     __ mull($src$$Register);
8067   %}
8068   ins_pipe( pipe_slow );
8069 %}
8070 
8071 // Multiply Register Long by small constant
8072 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8073   match(Set dst (MulL dst src));
8074   effect(KILL cr, TEMP tmp);
8075   ins_cost(2*100+2*400);
8076   size(12);
8077 // Basic idea: lo(result) = lo(src * EAX)
8078 //             hi(result) = hi(src * EAX) + lo(src * EDX)
8079   format %{ "IMUL   $tmp,EDX,$src\n\t"
8080             "MOV    EDX,$src\n\t"
8081             "MUL    EDX\t# EDX*EAX -> EDX:EAX\n\t"
8082             "ADD    EDX,$tmp" %}
8083   ins_encode( long_multiply_con( dst, src, tmp ) );
8084   ins_pipe( pipe_slow );
8085 %}
8086 
8087 // Integer DIV with Register
8088 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8089   match(Set rax (DivI rax div));
8090   effect(KILL rdx, KILL cr);
8091   size(26);
8092   ins_cost(30*100+10*100);
8093   format %{ "CMP    EAX,0x80000000\n\t"
8094             "JNE,s  normal\n\t"
8095             "XOR    EDX,EDX\n\t"
8096             "CMP    ECX,-1\n\t"
8097             "JE,s   done\n"
8098     "normal: CDQ\n\t"
8099             "IDIV   $div\n\t"
8100     "done:"        %}
8101   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8102   ins_encode( cdq_enc, OpcP, RegOpc(div) );
8103   ins_pipe( ialu_reg_reg_alu0 );
8104 %}
8105 
8106 // Divide Register Long
8107 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8108   match(Set dst (DivL src1 src2));
8109   effect( KILL cr, KILL cx, KILL bx );
8110   ins_cost(10000);
8111   format %{ "PUSH   $src1.hi\n\t"
8112             "PUSH   $src1.lo\n\t"
8113             "PUSH   $src2.hi\n\t"
8114             "PUSH   $src2.lo\n\t"
8115             "CALL   SharedRuntime::ldiv\n\t"
8116             "ADD    ESP,16" %}
8117   ins_encode( long_div(src1,src2) );
8118   ins_pipe( pipe_slow );
8119 %}
8120 
8121 // Integer DIVMOD with Register, both quotient and mod results
8122 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8123   match(DivModI rax div);
8124   effect(KILL cr);
8125   size(26);
8126   ins_cost(30*100+10*100);
8127   format %{ "CMP    EAX,0x80000000\n\t"
8128             "JNE,s  normal\n\t"
8129             "XOR    EDX,EDX\n\t"
8130             "CMP    ECX,-1\n\t"
8131             "JE,s   done\n"
8132     "normal: CDQ\n\t"
8133             "IDIV   $div\n\t"
8134     "done:"        %}
8135   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8136   ins_encode( cdq_enc, OpcP, RegOpc(div) );
8137   ins_pipe( pipe_slow );
8138 %}
8139 
8140 // Integer MOD with Register
8141 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8142   match(Set rdx (ModI rax div));
8143   effect(KILL rax, KILL cr);
8144 
8145   size(26);
8146   ins_cost(300);
8147   format %{ "CDQ\n\t"
8148             "IDIV   $div" %}
8149   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8150   ins_encode( cdq_enc, OpcP, RegOpc(div) );
8151   ins_pipe( ialu_reg_reg_alu0 );
8152 %}
8153 
8154 // Remainder Register Long
8155 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8156   match(Set dst (ModL src1 src2));
8157   effect( KILL cr, KILL cx, KILL bx );
8158   ins_cost(10000);
8159   format %{ "PUSH   $src1.hi\n\t"
8160             "PUSH   $src1.lo\n\t"
8161             "PUSH   $src2.hi\n\t"
8162             "PUSH   $src2.lo\n\t"
8163             "CALL   SharedRuntime::lrem\n\t"
8164             "ADD    ESP,16" %}
8165   ins_encode( long_mod(src1,src2) );
8166   ins_pipe( pipe_slow );
8167 %}
8168 
8169 // Divide Register Long (no special case since divisor != -1)
8170 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8171   match(Set dst (DivL dst imm));
8172   effect( TEMP tmp, TEMP tmp2, KILL cr );
8173   ins_cost(1000);
8174   format %{ "MOV    $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8175             "XOR    $tmp2,$tmp2\n\t"
8176             "CMP    $tmp,EDX\n\t"
8177             "JA,s   fast\n\t"
8178             "MOV    $tmp2,EAX\n\t"
8179             "MOV    EAX,EDX\n\t"
8180             "MOV    EDX,0\n\t"
8181             "JLE,s  pos\n\t"
8182             "LNEG   EAX : $tmp2\n\t"
8183             "DIV    $tmp # unsigned division\n\t"
8184             "XCHG   EAX,$tmp2\n\t"
8185             "DIV    $tmp\n\t"
8186             "LNEG   $tmp2 : EAX\n\t"
8187             "JMP,s  done\n"
8188     "pos:\n\t"
8189             "DIV    $tmp\n\t"
8190             "XCHG   EAX,$tmp2\n"
8191     "fast:\n\t"
8192             "DIV    $tmp\n"
8193     "done:\n\t"
8194             "MOV    EDX,$tmp2\n\t"
8195             "NEG    EDX:EAX # if $imm < 0" %}
8196   ins_encode %{
8197     int con = (int)$imm$$constant;
8198     assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8199     int pcon = (con > 0) ? con : -con;
8200     Label Lfast, Lpos, Ldone;
8201 
8202     __ movl($tmp$$Register, pcon);
8203     __ xorl($tmp2$$Register,$tmp2$$Register);
8204     __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8205     __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8206 
8207     __ movl($tmp2$$Register, $dst$$Register); // save
8208     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8209     __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8210     __ jccb(Assembler::lessEqual, Lpos); // result is positive
8211 
8212     // Negative dividend.
8213     // convert value to positive to use unsigned division
8214     __ lneg($dst$$Register, $tmp2$$Register);
8215     __ divl($tmp$$Register);
8216     __ xchgl($dst$$Register, $tmp2$$Register);
8217     __ divl($tmp$$Register);
8218     // revert result back to negative
8219     __ lneg($tmp2$$Register, $dst$$Register);
8220     __ jmpb(Ldone);
8221 
8222     __ bind(Lpos);
8223     __ divl($tmp$$Register); // Use unsigned division
8224     __ xchgl($dst$$Register, $tmp2$$Register);
8225     // Fallthrow for final divide, tmp2 has 32 bit hi result
8226 
8227     __ bind(Lfast);
8228     // fast path: src is positive
8229     __ divl($tmp$$Register); // Use unsigned division
8230 
8231     __ bind(Ldone);
8232     __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8233     if (con < 0) {
8234       __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8235     }
8236   %}
8237   ins_pipe( pipe_slow );
8238 %}
8239 
8240 // Remainder Register Long (remainder fit into 32 bits)
8241 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8242   match(Set dst (ModL dst imm));
8243   effect( TEMP tmp, TEMP tmp2, KILL cr );
8244   ins_cost(1000);
8245   format %{ "MOV    $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8246             "CMP    $tmp,EDX\n\t"
8247             "JA,s   fast\n\t"
8248             "MOV    $tmp2,EAX\n\t"
8249             "MOV    EAX,EDX\n\t"
8250             "MOV    EDX,0\n\t"
8251             "JLE,s  pos\n\t"
8252             "LNEG   EAX : $tmp2\n\t"
8253             "DIV    $tmp # unsigned division\n\t"
8254             "MOV    EAX,$tmp2\n\t"
8255             "DIV    $tmp\n\t"
8256             "NEG    EDX\n\t"
8257             "JMP,s  done\n"
8258     "pos:\n\t"
8259             "DIV    $tmp\n\t"
8260             "MOV    EAX,$tmp2\n"
8261     "fast:\n\t"
8262             "DIV    $tmp\n"
8263     "done:\n\t"
8264             "MOV    EAX,EDX\n\t"
8265             "SAR    EDX,31\n\t" %}
8266   ins_encode %{
8267     int con = (int)$imm$$constant;
8268     assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8269     int pcon = (con > 0) ? con : -con;
8270     Label  Lfast, Lpos, Ldone;
8271 
8272     __ movl($tmp$$Register, pcon);
8273     __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8274     __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8275 
8276     __ movl($tmp2$$Register, $dst$$Register); // save
8277     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8278     __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8279     __ jccb(Assembler::lessEqual, Lpos); // result is positive
8280 
8281     // Negative dividend.
8282     // convert value to positive to use unsigned division
8283     __ lneg($dst$$Register, $tmp2$$Register);
8284     __ divl($tmp$$Register);
8285     __ movl($dst$$Register, $tmp2$$Register);
8286     __ divl($tmp$$Register);
8287     // revert remainder back to negative
8288     __ negl(HIGH_FROM_LOW($dst$$Register));
8289     __ jmpb(Ldone);
8290 
8291     __ bind(Lpos);
8292     __ divl($tmp$$Register);
8293     __ movl($dst$$Register, $tmp2$$Register);
8294 
8295     __ bind(Lfast);
8296     // fast path: src is positive
8297     __ divl($tmp$$Register);
8298 
8299     __ bind(Ldone);
8300     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8301     __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8302 
8303   %}
8304   ins_pipe( pipe_slow );
8305 %}
8306 
8307 // Integer Shift Instructions
8308 // Shift Left by one
8309 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8310   match(Set dst (LShiftI dst shift));
8311   effect(KILL cr);
8312 
8313   size(2);
8314   format %{ "SHL    $dst,$shift" %}
8315   opcode(0xD1, 0x4);  /* D1 /4 */
8316   ins_encode( OpcP, RegOpc( dst ) );
8317   ins_pipe( ialu_reg );
8318 %}
8319 
8320 // Shift Left by 8-bit immediate
8321 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8322   match(Set dst (LShiftI dst shift));
8323   effect(KILL cr);
8324 
8325   size(3);
8326   format %{ "SHL    $dst,$shift" %}
8327   opcode(0xC1, 0x4);  /* C1 /4 ib */
8328   ins_encode( RegOpcImm( dst, shift) );
8329   ins_pipe( ialu_reg );
8330 %}
8331 
8332 // Shift Left by variable
8333 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8334   match(Set dst (LShiftI dst shift));
8335   effect(KILL cr);
8336 
8337   size(2);
8338   format %{ "SHL    $dst,$shift" %}
8339   opcode(0xD3, 0x4);  /* D3 /4 */
8340   ins_encode( OpcP, RegOpc( dst ) );
8341   ins_pipe( ialu_reg_reg );
8342 %}
8343 
8344 // Arithmetic shift right by one
8345 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8346   match(Set dst (RShiftI dst shift));
8347   effect(KILL cr);
8348 
8349   size(2);
8350   format %{ "SAR    $dst,$shift" %}
8351   opcode(0xD1, 0x7);  /* D1 /7 */
8352   ins_encode( OpcP, RegOpc( dst ) );
8353   ins_pipe( ialu_reg );
8354 %}
8355 
8356 // Arithmetic shift right by one
8357 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8358   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8359   effect(KILL cr);
8360   format %{ "SAR    $dst,$shift" %}
8361   opcode(0xD1, 0x7);  /* D1 /7 */
8362   ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8363   ins_pipe( ialu_mem_imm );
8364 %}
8365 
8366 // Arithmetic Shift Right by 8-bit immediate
8367 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8368   match(Set dst (RShiftI dst shift));
8369   effect(KILL cr);
8370 
8371   size(3);
8372   format %{ "SAR    $dst,$shift" %}
8373   opcode(0xC1, 0x7);  /* C1 /7 ib */
8374   ins_encode( RegOpcImm( dst, shift ) );
8375   ins_pipe( ialu_mem_imm );
8376 %}
8377 
8378 // Arithmetic Shift Right by 8-bit immediate
8379 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8380   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8381   effect(KILL cr);
8382 
8383   format %{ "SAR    $dst,$shift" %}
8384   opcode(0xC1, 0x7);  /* C1 /7 ib */
8385   ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8386   ins_pipe( ialu_mem_imm );
8387 %}
8388 
8389 // Arithmetic Shift Right by variable
8390 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8391   match(Set dst (RShiftI dst shift));
8392   effect(KILL cr);
8393 
8394   size(2);
8395   format %{ "SAR    $dst,$shift" %}
8396   opcode(0xD3, 0x7);  /* D3 /7 */
8397   ins_encode( OpcP, RegOpc( dst ) );
8398   ins_pipe( ialu_reg_reg );
8399 %}
8400 
8401 // Logical shift right by one
8402 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8403   match(Set dst (URShiftI dst shift));
8404   effect(KILL cr);
8405 
8406   size(2);
8407   format %{ "SHR    $dst,$shift" %}
8408   opcode(0xD1, 0x5);  /* D1 /5 */
8409   ins_encode( OpcP, RegOpc( dst ) );
8410   ins_pipe( ialu_reg );
8411 %}
8412 
8413 // Logical Shift Right by 8-bit immediate
8414 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8415   match(Set dst (URShiftI dst shift));
8416   effect(KILL cr);
8417 
8418   size(3);
8419   format %{ "SHR    $dst,$shift" %}
8420   opcode(0xC1, 0x5);  /* C1 /5 ib */
8421   ins_encode( RegOpcImm( dst, shift) );
8422   ins_pipe( ialu_reg );
8423 %}
8424 
8425 
8426 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8427 // This idiom is used by the compiler for the i2b bytecode.
8428 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8429   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8430 
8431   size(3);
8432   format %{ "MOVSX  $dst,$src :8" %}
8433   ins_encode %{
8434     __ movsbl($dst$$Register, $src$$Register);
8435   %}
8436   ins_pipe(ialu_reg_reg);
8437 %}
8438 
8439 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8440 // This idiom is used by the compiler the i2s bytecode.
8441 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8442   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8443 
8444   size(3);
8445   format %{ "MOVSX  $dst,$src :16" %}
8446   ins_encode %{
8447     __ movswl($dst$$Register, $src$$Register);
8448   %}
8449   ins_pipe(ialu_reg_reg);
8450 %}
8451 
8452 
8453 // Logical Shift Right by variable
8454 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8455   match(Set dst (URShiftI dst shift));
8456   effect(KILL cr);
8457 
8458   size(2);
8459   format %{ "SHR    $dst,$shift" %}
8460   opcode(0xD3, 0x5);  /* D3 /5 */
8461   ins_encode( OpcP, RegOpc( dst ) );
8462   ins_pipe( ialu_reg_reg );
8463 %}
8464 
8465 
8466 //----------Logical Instructions-----------------------------------------------
8467 //----------Integer Logical Instructions---------------------------------------
8468 // And Instructions
8469 // And Register with Register
8470 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8471   match(Set dst (AndI dst src));
8472   effect(KILL cr);
8473 
8474   size(2);
8475   format %{ "AND    $dst,$src" %}
8476   opcode(0x23);
8477   ins_encode( OpcP, RegReg( dst, src) );
8478   ins_pipe( ialu_reg_reg );
8479 %}
8480 
8481 // And Register with Immediate
8482 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8483   match(Set dst (AndI dst src));
8484   effect(KILL cr);
8485 
8486   format %{ "AND    $dst,$src" %}
8487   opcode(0x81,0x04);  /* Opcode 81 /4 */
8488   // ins_encode( RegImm( dst, src) );
8489   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8490   ins_pipe( ialu_reg );
8491 %}
8492 
8493 // And Register with Memory
8494 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8495   match(Set dst (AndI dst (LoadI src)));
8496   effect(KILL cr);
8497 
8498   ins_cost(125);
8499   format %{ "AND    $dst,$src" %}
8500   opcode(0x23);
8501   ins_encode( OpcP, RegMem( dst, src) );
8502   ins_pipe( ialu_reg_mem );
8503 %}
8504 
8505 // And Memory with Register
8506 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8507   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8508   effect(KILL cr);
8509 
8510   ins_cost(150);
8511   format %{ "AND    $dst,$src" %}
8512   opcode(0x21);  /* Opcode 21 /r */
8513   ins_encode( OpcP, RegMem( src, dst ) );
8514   ins_pipe( ialu_mem_reg );
8515 %}
8516 
8517 // And Memory with Immediate
8518 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8519   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8520   effect(KILL cr);
8521 
8522   ins_cost(125);
8523   format %{ "AND    $dst,$src" %}
8524   opcode(0x81, 0x4);  /* Opcode 81 /4 id */
8525   // ins_encode( MemImm( dst, src) );
8526   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8527   ins_pipe( ialu_mem_imm );
8528 %}
8529 
8530 // Or Instructions
8531 // Or Register with Register
8532 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8533   match(Set dst (OrI dst src));
8534   effect(KILL cr);
8535 
8536   size(2);
8537   format %{ "OR     $dst,$src" %}
8538   opcode(0x0B);
8539   ins_encode( OpcP, RegReg( dst, src) );
8540   ins_pipe( ialu_reg_reg );
8541 %}
8542 
8543 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8544   match(Set dst (OrI dst (CastP2X src)));
8545   effect(KILL cr);
8546 
8547   size(2);
8548   format %{ "OR     $dst,$src" %}
8549   opcode(0x0B);
8550   ins_encode( OpcP, RegReg( dst, src) );
8551   ins_pipe( ialu_reg_reg );
8552 %}
8553 
8554 
8555 // Or Register with Immediate
8556 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8557   match(Set dst (OrI dst src));
8558   effect(KILL cr);
8559 
8560   format %{ "OR     $dst,$src" %}
8561   opcode(0x81,0x01);  /* Opcode 81 /1 id */
8562   // ins_encode( RegImm( dst, src) );
8563   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8564   ins_pipe( ialu_reg );
8565 %}
8566 
8567 // Or Register with Memory
8568 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8569   match(Set dst (OrI dst (LoadI src)));
8570   effect(KILL cr);
8571 
8572   ins_cost(125);
8573   format %{ "OR     $dst,$src" %}
8574   opcode(0x0B);
8575   ins_encode( OpcP, RegMem( dst, src) );
8576   ins_pipe( ialu_reg_mem );
8577 %}
8578 
8579 // Or Memory with Register
8580 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8581   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8582   effect(KILL cr);
8583 
8584   ins_cost(150);
8585   format %{ "OR     $dst,$src" %}
8586   opcode(0x09);  /* Opcode 09 /r */
8587   ins_encode( OpcP, RegMem( src, dst ) );
8588   ins_pipe( ialu_mem_reg );
8589 %}
8590 
8591 // Or Memory with Immediate
8592 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8593   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8594   effect(KILL cr);
8595 
8596   ins_cost(125);
8597   format %{ "OR     $dst,$src" %}
8598   opcode(0x81,0x1);  /* Opcode 81 /1 id */
8599   // ins_encode( MemImm( dst, src) );
8600   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8601   ins_pipe( ialu_mem_imm );
8602 %}
8603 
8604 // ROL/ROR
8605 // ROL expand
8606 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8607   effect(USE_DEF dst, USE shift, KILL cr);
8608 
8609   format %{ "ROL    $dst, $shift" %}
8610   opcode(0xD1, 0x0); /* Opcode D1 /0 */
8611   ins_encode( OpcP, RegOpc( dst ));
8612   ins_pipe( ialu_reg );
8613 %}
8614 
8615 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8616   effect(USE_DEF dst, USE shift, KILL cr);
8617 
8618   format %{ "ROL    $dst, $shift" %}
8619   opcode(0xC1, 0x0); /*Opcode /C1  /0  */
8620   ins_encode( RegOpcImm(dst, shift) );
8621   ins_pipe(ialu_reg);
8622 %}
8623 
8624 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8625   effect(USE_DEF dst, USE shift, KILL cr);
8626 
8627   format %{ "ROL    $dst, $shift" %}
8628   opcode(0xD3, 0x0);    /* Opcode D3 /0 */
8629   ins_encode(OpcP, RegOpc(dst));
8630   ins_pipe( ialu_reg_reg );
8631 %}
8632 // end of ROL expand
8633 
8634 // ROL 32bit by one once
8635 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8636   match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8637 
8638   expand %{
8639     rolI_eReg_imm1(dst, lshift, cr);
8640   %}
8641 %}
8642 
8643 // ROL 32bit var by imm8 once
8644 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8645   predicate(  0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8646   match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8647 
8648   expand %{
8649     rolI_eReg_imm8(dst, lshift, cr);
8650   %}
8651 %}
8652 
8653 // ROL 32bit var by var once
8654 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8655   match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8656 
8657   expand %{
8658     rolI_eReg_CL(dst, shift, cr);
8659   %}
8660 %}
8661 
8662 // ROL 32bit var by var once
8663 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8664   match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8665 
8666   expand %{
8667     rolI_eReg_CL(dst, shift, cr);
8668   %}
8669 %}
8670 
8671 // ROR expand
8672 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8673   effect(USE_DEF dst, USE shift, KILL cr);
8674 
8675   format %{ "ROR    $dst, $shift" %}
8676   opcode(0xD1,0x1);  /* Opcode D1 /1 */
8677   ins_encode( OpcP, RegOpc( dst ) );
8678   ins_pipe( ialu_reg );
8679 %}
8680 
8681 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8682   effect (USE_DEF dst, USE shift, KILL cr);
8683 
8684   format %{ "ROR    $dst, $shift" %}
8685   opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8686   ins_encode( RegOpcImm(dst, shift) );
8687   ins_pipe( ialu_reg );
8688 %}
8689 
8690 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8691   effect(USE_DEF dst, USE shift, KILL cr);
8692 
8693   format %{ "ROR    $dst, $shift" %}
8694   opcode(0xD3, 0x1);    /* Opcode D3 /1 */
8695   ins_encode(OpcP, RegOpc(dst));
8696   ins_pipe( ialu_reg_reg );
8697 %}
8698 // end of ROR expand
8699 
8700 // ROR right once
8701 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8702   match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8703 
8704   expand %{
8705     rorI_eReg_imm1(dst, rshift, cr);
8706   %}
8707 %}
8708 
8709 // ROR 32bit by immI8 once
8710 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8711   predicate(  0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8712   match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8713 
8714   expand %{
8715     rorI_eReg_imm8(dst, rshift, cr);
8716   %}
8717 %}
8718 
8719 // ROR 32bit var by var once
8720 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8721   match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8722 
8723   expand %{
8724     rorI_eReg_CL(dst, shift, cr);
8725   %}
8726 %}
8727 
8728 // ROR 32bit var by var once
8729 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8730   match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8731 
8732   expand %{
8733     rorI_eReg_CL(dst, shift, cr);
8734   %}
8735 %}
8736 
8737 // Xor Instructions
8738 // Xor Register with Register
8739 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8740   match(Set dst (XorI dst src));
8741   effect(KILL cr);
8742 
8743   size(2);
8744   format %{ "XOR    $dst,$src" %}
8745   opcode(0x33);
8746   ins_encode( OpcP, RegReg( dst, src) );
8747   ins_pipe( ialu_reg_reg );
8748 %}
8749 
8750 // Xor Register with Immediate -1
8751 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8752   match(Set dst (XorI dst imm));  
8753 
8754   size(2);
8755   format %{ "NOT    $dst" %}  
8756   ins_encode %{
8757      __ notl($dst$$Register);
8758   %}
8759   ins_pipe( ialu_reg );
8760 %}
8761 
8762 // Xor Register with Immediate
8763 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8764   match(Set dst (XorI dst src));
8765   effect(KILL cr);
8766 
8767   format %{ "XOR    $dst,$src" %}
8768   opcode(0x81,0x06);  /* Opcode 81 /6 id */
8769   // ins_encode( RegImm( dst, src) );
8770   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8771   ins_pipe( ialu_reg );
8772 %}
8773 
8774 // Xor Register with Memory
8775 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8776   match(Set dst (XorI dst (LoadI src)));
8777   effect(KILL cr);
8778 
8779   ins_cost(125);
8780   format %{ "XOR    $dst,$src" %}
8781   opcode(0x33);
8782   ins_encode( OpcP, RegMem(dst, src) );
8783   ins_pipe( ialu_reg_mem );
8784 %}
8785 
8786 // Xor Memory with Register
8787 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8788   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8789   effect(KILL cr);
8790 
8791   ins_cost(150);
8792   format %{ "XOR    $dst,$src" %}
8793   opcode(0x31);  /* Opcode 31 /r */
8794   ins_encode( OpcP, RegMem( src, dst ) );
8795   ins_pipe( ialu_mem_reg );
8796 %}
8797 
8798 // Xor Memory with Immediate
8799 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8800   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8801   effect(KILL cr);
8802 
8803   ins_cost(125);
8804   format %{ "XOR    $dst,$src" %}
8805   opcode(0x81,0x6);  /* Opcode 81 /6 id */
8806   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8807   ins_pipe( ialu_mem_imm );
8808 %}
8809 
8810 //----------Convert Int to Boolean---------------------------------------------
8811 
8812 instruct movI_nocopy(rRegI dst, rRegI src) %{
8813   effect( DEF dst, USE src );
8814   format %{ "MOV    $dst,$src" %}
8815   ins_encode( enc_Copy( dst, src) );
8816   ins_pipe( ialu_reg_reg );
8817 %}
8818 
8819 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8820   effect( USE_DEF dst, USE src, KILL cr );
8821 
8822   size(4);
8823   format %{ "NEG    $dst\n\t"
8824             "ADC    $dst,$src" %}
8825   ins_encode( neg_reg(dst),
8826               OpcRegReg(0x13,dst,src) );
8827   ins_pipe( ialu_reg_reg_long );
8828 %}
8829 
8830 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8831   match(Set dst (Conv2B src));
8832 
8833   expand %{
8834     movI_nocopy(dst,src);
8835     ci2b(dst,src,cr);
8836   %}
8837 %}
8838 
8839 instruct movP_nocopy(rRegI dst, eRegP src) %{
8840   effect( DEF dst, USE src );
8841   format %{ "MOV    $dst,$src" %}
8842   ins_encode( enc_Copy( dst, src) );
8843   ins_pipe( ialu_reg_reg );
8844 %}
8845 
8846 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8847   effect( USE_DEF dst, USE src, KILL cr );
8848   format %{ "NEG    $dst\n\t"
8849             "ADC    $dst,$src" %}
8850   ins_encode( neg_reg(dst),
8851               OpcRegReg(0x13,dst,src) );
8852   ins_pipe( ialu_reg_reg_long );
8853 %}
8854 
8855 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8856   match(Set dst (Conv2B src));
8857 
8858   expand %{
8859     movP_nocopy(dst,src);
8860     cp2b(dst,src,cr);
8861   %}
8862 %}
8863 
8864 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8865   match(Set dst (CmpLTMask p q));
8866   effect(KILL cr);
8867   ins_cost(400);
8868 
8869   // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8870   format %{ "XOR    $dst,$dst\n\t"
8871             "CMP    $p,$q\n\t"
8872             "SETlt  $dst\n\t"
8873             "NEG    $dst" %}
8874   ins_encode %{
8875     Register Rp = $p$$Register;
8876     Register Rq = $q$$Register;
8877     Register Rd = $dst$$Register;
8878     Label done;
8879     __ xorl(Rd, Rd);
8880     __ cmpl(Rp, Rq);
8881     __ setb(Assembler::less, Rd);
8882     __ negl(Rd);
8883   %}
8884 
8885   ins_pipe(pipe_slow);
8886 %}
8887 
8888 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8889   match(Set dst (CmpLTMask dst zero));
8890   effect(DEF dst, KILL cr);
8891   ins_cost(100);
8892 
8893   format %{ "SAR    $dst,31\t# cmpLTMask0" %}
8894   ins_encode %{
8895   __ sarl($dst$$Register, 31);
8896   %}
8897   ins_pipe(ialu_reg);
8898 %}
8899 
8900 /* better to save a register than avoid a branch */
8901 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8902   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8903   effect(KILL cr);
8904   ins_cost(400);
8905   format %{ "SUB    $p,$q\t# cadd_cmpLTMask\n\t"
8906             "JGE    done\n\t"
8907             "ADD    $p,$y\n"
8908             "done:  " %}
8909   ins_encode %{
8910     Register Rp = $p$$Register;
8911     Register Rq = $q$$Register;
8912     Register Ry = $y$$Register;
8913     Label done;
8914     __ subl(Rp, Rq);
8915     __ jccb(Assembler::greaterEqual, done);
8916     __ addl(Rp, Ry);
8917     __ bind(done);
8918   %}
8919 
8920   ins_pipe(pipe_cmplt);
8921 %}
8922 
8923 /* better to save a register than avoid a branch */
8924 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8925   match(Set y (AndI (CmpLTMask p q) y));
8926   effect(KILL cr);
8927 
8928   ins_cost(300);
8929 
8930   format %{ "CMPL     $p, $q\t# and_cmpLTMask\n\t"
8931             "JLT      done\n\t"
8932             "XORL     $y, $y\n"
8933             "done:  " %}
8934   ins_encode %{
8935     Register Rp = $p$$Register;
8936     Register Rq = $q$$Register;
8937     Register Ry = $y$$Register;
8938     Label done;
8939     __ cmpl(Rp, Rq);
8940     __ jccb(Assembler::less, done);
8941     __ xorl(Ry, Ry);
8942     __ bind(done);
8943   %}
8944 
8945   ins_pipe(pipe_cmplt);
8946 %}
8947 
8948 /* If I enable this, I encourage spilling in the inner loop of compress.
8949 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8950   match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8951 */
8952 
8953 //----------Long Instructions------------------------------------------------
8954 // Add Long Register with Register
8955 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8956   match(Set dst (AddL dst src));
8957   effect(KILL cr);
8958   ins_cost(200);
8959   format %{ "ADD    $dst.lo,$src.lo\n\t"
8960             "ADC    $dst.hi,$src.hi" %}
8961   opcode(0x03, 0x13);
8962   ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8963   ins_pipe( ialu_reg_reg_long );
8964 %}
8965 
8966 // Add Long Register with Immediate
8967 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8968   match(Set dst (AddL dst src));
8969   effect(KILL cr);
8970   format %{ "ADD    $dst.lo,$src.lo\n\t"
8971             "ADC    $dst.hi,$src.hi" %}
8972   opcode(0x81,0x00,0x02);  /* Opcode 81 /0, 81 /2 */
8973   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8974   ins_pipe( ialu_reg_long );
8975 %}
8976 
8977 // Add Long Register with Memory
8978 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8979   match(Set dst (AddL dst (LoadL mem)));
8980   effect(KILL cr);
8981   ins_cost(125);
8982   format %{ "ADD    $dst.lo,$mem\n\t"
8983             "ADC    $dst.hi,$mem+4" %}
8984   opcode(0x03, 0x13);
8985   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8986   ins_pipe( ialu_reg_long_mem );
8987 %}
8988 
8989 // Subtract Long Register with Register.
8990 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8991   match(Set dst (SubL dst src));
8992   effect(KILL cr);
8993   ins_cost(200);
8994   format %{ "SUB    $dst.lo,$src.lo\n\t"
8995             "SBB    $dst.hi,$src.hi" %}
8996   opcode(0x2B, 0x1B);
8997   ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8998   ins_pipe( ialu_reg_reg_long );
8999 %}
9000 
9001 // Subtract Long Register with Immediate
9002 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9003   match(Set dst (SubL dst src));
9004   effect(KILL cr);
9005   format %{ "SUB    $dst.lo,$src.lo\n\t"
9006             "SBB    $dst.hi,$src.hi" %}
9007   opcode(0x81,0x05,0x03);  /* Opcode 81 /5, 81 /3 */
9008   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9009   ins_pipe( ialu_reg_long );
9010 %}
9011 
9012 // Subtract Long Register with Memory
9013 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9014   match(Set dst (SubL dst (LoadL mem)));
9015   effect(KILL cr);
9016   ins_cost(125);
9017   format %{ "SUB    $dst.lo,$mem\n\t"
9018             "SBB    $dst.hi,$mem+4" %}
9019   opcode(0x2B, 0x1B);
9020   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9021   ins_pipe( ialu_reg_long_mem );
9022 %}
9023 
9024 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9025   match(Set dst (SubL zero dst));
9026   effect(KILL cr);
9027   ins_cost(300);
9028   format %{ "NEG    $dst.hi\n\tNEG    $dst.lo\n\tSBB    $dst.hi,0" %}
9029   ins_encode( neg_long(dst) );
9030   ins_pipe( ialu_reg_reg_long );
9031 %}
9032 
9033 // And Long Register with Register
9034 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9035   match(Set dst (AndL dst src));
9036   effect(KILL cr);
9037   format %{ "AND    $dst.lo,$src.lo\n\t"
9038             "AND    $dst.hi,$src.hi" %}
9039   opcode(0x23,0x23);
9040   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9041   ins_pipe( ialu_reg_reg_long );
9042 %}
9043 
9044 // And Long Register with Immediate
9045 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9046   match(Set dst (AndL dst src));
9047   effect(KILL cr);
9048   format %{ "AND    $dst.lo,$src.lo\n\t"
9049             "AND    $dst.hi,$src.hi" %}
9050   opcode(0x81,0x04,0x04);  /* Opcode 81 /4, 81 /4 */
9051   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9052   ins_pipe( ialu_reg_long );
9053 %}
9054 
9055 // And Long Register with Memory
9056 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9057   match(Set dst (AndL dst (LoadL mem)));
9058   effect(KILL cr);
9059   ins_cost(125);
9060   format %{ "AND    $dst.lo,$mem\n\t"
9061             "AND    $dst.hi,$mem+4" %}
9062   opcode(0x23, 0x23);
9063   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9064   ins_pipe( ialu_reg_long_mem );
9065 %}
9066 
9067 // Or Long Register with Register
9068 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9069   match(Set dst (OrL dst src));
9070   effect(KILL cr);
9071   format %{ "OR     $dst.lo,$src.lo\n\t"
9072             "OR     $dst.hi,$src.hi" %}
9073   opcode(0x0B,0x0B);
9074   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9075   ins_pipe( ialu_reg_reg_long );
9076 %}
9077 
9078 // Or Long Register with Immediate
9079 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9080   match(Set dst (OrL dst src));
9081   effect(KILL cr);
9082   format %{ "OR     $dst.lo,$src.lo\n\t"
9083             "OR     $dst.hi,$src.hi" %}
9084   opcode(0x81,0x01,0x01);  /* Opcode 81 /1, 81 /1 */
9085   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9086   ins_pipe( ialu_reg_long );
9087 %}
9088 
9089 // Or Long Register with Memory
9090 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9091   match(Set dst (OrL dst (LoadL mem)));
9092   effect(KILL cr);
9093   ins_cost(125);
9094   format %{ "OR     $dst.lo,$mem\n\t"
9095             "OR     $dst.hi,$mem+4" %}
9096   opcode(0x0B,0x0B);
9097   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9098   ins_pipe( ialu_reg_long_mem );
9099 %}
9100 
9101 // Xor Long Register with Register
9102 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9103   match(Set dst (XorL dst src));
9104   effect(KILL cr);
9105   format %{ "XOR    $dst.lo,$src.lo\n\t"
9106             "XOR    $dst.hi,$src.hi" %}
9107   opcode(0x33,0x33);
9108   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9109   ins_pipe( ialu_reg_reg_long );
9110 %}
9111 
9112 // Xor Long Register with Immediate -1
9113 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9114   match(Set dst (XorL dst imm));  
9115   format %{ "NOT    $dst.lo\n\t"
9116             "NOT    $dst.hi" %}
9117   ins_encode %{
9118      __ notl($dst$$Register);
9119      __ notl(HIGH_FROM_LOW($dst$$Register));
9120   %}
9121   ins_pipe( ialu_reg_long );
9122 %}
9123 
9124 // Xor Long Register with Immediate
9125 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9126   match(Set dst (XorL dst src));
9127   effect(KILL cr);
9128   format %{ "XOR    $dst.lo,$src.lo\n\t"
9129             "XOR    $dst.hi,$src.hi" %}
9130   opcode(0x81,0x06,0x06);  /* Opcode 81 /6, 81 /6 */
9131   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9132   ins_pipe( ialu_reg_long );
9133 %}
9134 
9135 // Xor Long Register with Memory
9136 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9137   match(Set dst (XorL dst (LoadL mem)));
9138   effect(KILL cr);
9139   ins_cost(125);
9140   format %{ "XOR    $dst.lo,$mem\n\t"
9141             "XOR    $dst.hi,$mem+4" %}
9142   opcode(0x33,0x33);
9143   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9144   ins_pipe( ialu_reg_long_mem );
9145 %}
9146 
9147 // Shift Left Long by 1
9148 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9149   predicate(UseNewLongLShift);
9150   match(Set dst (LShiftL dst cnt));
9151   effect(KILL cr);
9152   ins_cost(100);
9153   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9154             "ADC    $dst.hi,$dst.hi" %}
9155   ins_encode %{
9156     __ addl($dst$$Register,$dst$$Register);
9157     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9158   %}
9159   ins_pipe( ialu_reg_long );
9160 %}
9161 
9162 // Shift Left Long by 2
9163 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9164   predicate(UseNewLongLShift);
9165   match(Set dst (LShiftL dst cnt));
9166   effect(KILL cr);
9167   ins_cost(100);
9168   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9169             "ADC    $dst.hi,$dst.hi\n\t" 
9170             "ADD    $dst.lo,$dst.lo\n\t"
9171             "ADC    $dst.hi,$dst.hi" %}
9172   ins_encode %{
9173     __ addl($dst$$Register,$dst$$Register);
9174     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9175     __ addl($dst$$Register,$dst$$Register);
9176     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9177   %}
9178   ins_pipe( ialu_reg_long );
9179 %}
9180 
9181 // Shift Left Long by 3
9182 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9183   predicate(UseNewLongLShift);
9184   match(Set dst (LShiftL dst cnt));
9185   effect(KILL cr);
9186   ins_cost(100);
9187   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9188             "ADC    $dst.hi,$dst.hi\n\t" 
9189             "ADD    $dst.lo,$dst.lo\n\t"
9190             "ADC    $dst.hi,$dst.hi\n\t" 
9191             "ADD    $dst.lo,$dst.lo\n\t"
9192             "ADC    $dst.hi,$dst.hi" %}
9193   ins_encode %{
9194     __ addl($dst$$Register,$dst$$Register);
9195     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9196     __ addl($dst$$Register,$dst$$Register);
9197     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9198     __ addl($dst$$Register,$dst$$Register);
9199     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9200   %}
9201   ins_pipe( ialu_reg_long );
9202 %}
9203 
9204 // Shift Left Long by 1-31
9205 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9206   match(Set dst (LShiftL dst cnt));
9207   effect(KILL cr);
9208   ins_cost(200);
9209   format %{ "SHLD   $dst.hi,$dst.lo,$cnt\n\t"
9210             "SHL    $dst.lo,$cnt" %}
9211   opcode(0xC1, 0x4, 0xA4);  /* 0F/A4, then C1 /4 ib */
9212   ins_encode( move_long_small_shift(dst,cnt) );
9213   ins_pipe( ialu_reg_long );
9214 %}
9215 
9216 // Shift Left Long by 32-63
9217 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9218   match(Set dst (LShiftL dst cnt));
9219   effect(KILL cr);
9220   ins_cost(300);
9221   format %{ "MOV    $dst.hi,$dst.lo\n"
9222           "\tSHL    $dst.hi,$cnt-32\n"
9223           "\tXOR    $dst.lo,$dst.lo" %}
9224   opcode(0xC1, 0x4);  /* C1 /4 ib */
9225   ins_encode( move_long_big_shift_clr(dst,cnt) );
9226   ins_pipe( ialu_reg_long );
9227 %}
9228 
9229 // Shift Left Long by variable
9230 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9231   match(Set dst (LShiftL dst shift));
9232   effect(KILL cr);
9233   ins_cost(500+200);
9234   size(17);
9235   format %{ "TEST   $shift,32\n\t"
9236             "JEQ,s  small\n\t"
9237             "MOV    $dst.hi,$dst.lo\n\t"
9238             "XOR    $dst.lo,$dst.lo\n"
9239     "small:\tSHLD   $dst.hi,$dst.lo,$shift\n\t"
9240             "SHL    $dst.lo,$shift" %}
9241   ins_encode( shift_left_long( dst, shift ) );
9242   ins_pipe( pipe_slow );
9243 %}
9244 
9245 // Shift Right Long by 1-31
9246 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9247   match(Set dst (URShiftL dst cnt));
9248   effect(KILL cr);
9249   ins_cost(200);
9250   format %{ "SHRD   $dst.lo,$dst.hi,$cnt\n\t"
9251             "SHR    $dst.hi,$cnt" %}
9252   opcode(0xC1, 0x5, 0xAC);  /* 0F/AC, then C1 /5 ib */
9253   ins_encode( move_long_small_shift(dst,cnt) );
9254   ins_pipe( ialu_reg_long );
9255 %}
9256 
9257 // Shift Right Long by 32-63
9258 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9259   match(Set dst (URShiftL dst cnt));
9260   effect(KILL cr);
9261   ins_cost(300);
9262   format %{ "MOV    $dst.lo,$dst.hi\n"
9263           "\tSHR    $dst.lo,$cnt-32\n"
9264           "\tXOR    $dst.hi,$dst.hi" %}
9265   opcode(0xC1, 0x5);  /* C1 /5 ib */
9266   ins_encode( move_long_big_shift_clr(dst,cnt) );
9267   ins_pipe( ialu_reg_long );
9268 %}
9269 
9270 // Shift Right Long by variable
9271 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9272   match(Set dst (URShiftL dst shift));
9273   effect(KILL cr);
9274   ins_cost(600);
9275   size(17);
9276   format %{ "TEST   $shift,32\n\t"
9277             "JEQ,s  small\n\t"
9278             "MOV    $dst.lo,$dst.hi\n\t"
9279             "XOR    $dst.hi,$dst.hi\n"
9280     "small:\tSHRD   $dst.lo,$dst.hi,$shift\n\t"
9281             "SHR    $dst.hi,$shift" %}
9282   ins_encode( shift_right_long( dst, shift ) );
9283   ins_pipe( pipe_slow );
9284 %}
9285 
9286 // Shift Right Long by 1-31
9287 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9288   match(Set dst (RShiftL dst cnt));
9289   effect(KILL cr);
9290   ins_cost(200);
9291   format %{ "SHRD   $dst.lo,$dst.hi,$cnt\n\t"
9292             "SAR    $dst.hi,$cnt" %}
9293   opcode(0xC1, 0x7, 0xAC);  /* 0F/AC, then C1 /7 ib */
9294   ins_encode( move_long_small_shift(dst,cnt) );
9295   ins_pipe( ialu_reg_long );
9296 %}
9297 
9298 // Shift Right Long by 32-63
9299 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9300   match(Set dst (RShiftL dst cnt));
9301   effect(KILL cr);
9302   ins_cost(300);
9303   format %{ "MOV    $dst.lo,$dst.hi\n"
9304           "\tSAR    $dst.lo,$cnt-32\n"
9305           "\tSAR    $dst.hi,31" %}
9306   opcode(0xC1, 0x7);  /* C1 /7 ib */
9307   ins_encode( move_long_big_shift_sign(dst,cnt) );
9308   ins_pipe( ialu_reg_long );
9309 %}
9310 
9311 // Shift Right arithmetic Long by variable
9312 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9313   match(Set dst (RShiftL dst shift));
9314   effect(KILL cr);
9315   ins_cost(600);
9316   size(18);
9317   format %{ "TEST   $shift,32\n\t"
9318             "JEQ,s  small\n\t"
9319             "MOV    $dst.lo,$dst.hi\n\t"
9320             "SAR    $dst.hi,31\n"
9321     "small:\tSHRD   $dst.lo,$dst.hi,$shift\n\t"
9322             "SAR    $dst.hi,$shift" %}
9323   ins_encode( shift_right_arith_long( dst, shift ) );
9324   ins_pipe( pipe_slow );
9325 %}
9326 
9327 
9328 //----------Double Instructions------------------------------------------------
9329 // Double Math
9330 
9331 // Compare & branch
9332 
9333 // P6 version of float compare, sets condition codes in EFLAGS
9334 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9335   predicate(VM_Version::supports_cmov() && UseSSE <=1);
9336   match(Set cr (CmpD src1 src2));
9337   effect(KILL rax);
9338   ins_cost(150);
9339   format %{ "FLD    $src1\n\t"
9340             "FUCOMIP ST,$src2  // P6 instruction\n\t"
9341             "JNP    exit\n\t"
9342             "MOV    ah,1       // saw a NaN, set CF\n\t"
9343             "SAHF\n"
9344      "exit:\tNOP               // avoid branch to branch" %}
9345   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9346   ins_encode( Push_Reg_DPR(src1),
9347               OpcP, RegOpc(src2),
9348               cmpF_P6_fixup );
9349   ins_pipe( pipe_slow );
9350 %}
9351 
9352 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9353   predicate(VM_Version::supports_cmov() && UseSSE <=1);
9354   match(Set cr (CmpD src1 src2));
9355   ins_cost(150);
9356   format %{ "FLD    $src1\n\t"
9357             "FUCOMIP ST,$src2  // P6 instruction" %}
9358   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9359   ins_encode( Push_Reg_DPR(src1),
9360               OpcP, RegOpc(src2));
9361   ins_pipe( pipe_slow );
9362 %}
9363 
9364 // Compare & branch
9365 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9366   predicate(UseSSE<=1);
9367   match(Set cr (CmpD src1 src2));
9368   effect(KILL rax);
9369   ins_cost(200);
9370   format %{ "FLD    $src1\n\t"
9371             "FCOMp  $src2\n\t"
9372             "FNSTSW AX\n\t"
9373             "TEST   AX,0x400\n\t"
9374             "JZ,s   flags\n\t"
9375             "MOV    AH,1\t# unordered treat as LT\n"
9376     "flags:\tSAHF" %}
9377   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9378   ins_encode( Push_Reg_DPR(src1),
9379               OpcP, RegOpc(src2),
9380               fpu_flags);
9381   ins_pipe( pipe_slow );
9382 %}
9383 
9384 // Compare vs zero into -1,0,1
9385 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9386   predicate(UseSSE<=1);
9387   match(Set dst (CmpD3 src1 zero));
9388   effect(KILL cr, KILL rax);
9389   ins_cost(280);
9390   format %{ "FTSTD  $dst,$src1" %}
9391   opcode(0xE4, 0xD9);
9392   ins_encode( Push_Reg_DPR(src1),
9393               OpcS, OpcP, PopFPU,
9394               CmpF_Result(dst));
9395   ins_pipe( pipe_slow );
9396 %}
9397 
9398 // Compare into -1,0,1
9399 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9400   predicate(UseSSE<=1);
9401   match(Set dst (CmpD3 src1 src2));
9402   effect(KILL cr, KILL rax);
9403   ins_cost(300);
9404   format %{ "FCMPD  $dst,$src1,$src2" %}
9405   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9406   ins_encode( Push_Reg_DPR(src1),
9407               OpcP, RegOpc(src2),
9408               CmpF_Result(dst));
9409   ins_pipe( pipe_slow );
9410 %}
9411 
9412 // float compare and set condition codes in EFLAGS by XMM regs
9413 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9414   predicate(UseSSE>=2);
9415   match(Set cr (CmpD src1 src2));
9416   ins_cost(145);
9417   format %{ "UCOMISD $src1,$src2\n\t"
9418             "JNP,s   exit\n\t"
9419             "PUSHF\t# saw NaN, set CF\n\t"
9420             "AND     [rsp], #0xffffff2b\n\t"
9421             "POPF\n"
9422     "exit:" %}
9423   ins_encode %{
9424     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9425     emit_cmpfp_fixup(_masm);
9426   %}
9427   ins_pipe( pipe_slow );
9428 %}
9429 
9430 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9431   predicate(UseSSE>=2);
9432   match(Set cr (CmpD src1 src2));
9433   ins_cost(100);
9434   format %{ "UCOMISD $src1,$src2" %}
9435   ins_encode %{
9436     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9437   %}
9438   ins_pipe( pipe_slow );
9439 %}
9440 
9441 // float compare and set condition codes in EFLAGS by XMM regs
9442 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9443   predicate(UseSSE>=2);
9444   match(Set cr (CmpD src1 (LoadD src2)));
9445   ins_cost(145);
9446   format %{ "UCOMISD $src1,$src2\n\t"
9447             "JNP,s   exit\n\t"
9448             "PUSHF\t# saw NaN, set CF\n\t"
9449             "AND     [rsp], #0xffffff2b\n\t"
9450             "POPF\n"
9451     "exit:" %}
9452   ins_encode %{
9453     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9454     emit_cmpfp_fixup(_masm);
9455   %}
9456   ins_pipe( pipe_slow );
9457 %}
9458 
9459 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9460   predicate(UseSSE>=2);
9461   match(Set cr (CmpD src1 (LoadD src2)));
9462   ins_cost(100);
9463   format %{ "UCOMISD $src1,$src2" %}
9464   ins_encode %{
9465     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9466   %}
9467   ins_pipe( pipe_slow );
9468 %}
9469 
9470 // Compare into -1,0,1 in XMM
9471 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9472   predicate(UseSSE>=2);
9473   match(Set dst (CmpD3 src1 src2));
9474   effect(KILL cr);
9475   ins_cost(255);
9476   format %{ "UCOMISD $src1, $src2\n\t"
9477             "MOV     $dst, #-1\n\t"
9478             "JP,s    done\n\t"
9479             "JB,s    done\n\t"
9480             "SETNE   $dst\n\t"
9481             "MOVZB   $dst, $dst\n"
9482     "done:" %}
9483   ins_encode %{
9484     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9485     emit_cmpfp3(_masm, $dst$$Register);
9486   %}
9487   ins_pipe( pipe_slow );
9488 %}
9489 
9490 // Compare into -1,0,1 in XMM and memory
9491 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9492   predicate(UseSSE>=2);
9493   match(Set dst (CmpD3 src1 (LoadD src2)));
9494   effect(KILL cr);
9495   ins_cost(275);
9496   format %{ "UCOMISD $src1, $src2\n\t"
9497             "MOV     $dst, #-1\n\t"
9498             "JP,s    done\n\t"
9499             "JB,s    done\n\t"
9500             "SETNE   $dst\n\t"
9501             "MOVZB   $dst, $dst\n"
9502     "done:" %}
9503   ins_encode %{
9504     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9505     emit_cmpfp3(_masm, $dst$$Register);
9506   %}
9507   ins_pipe( pipe_slow );
9508 %}
9509 
9510 
9511 instruct subDPR_reg(regDPR dst, regDPR src) %{
9512   predicate (UseSSE <=1);
9513   match(Set dst (SubD dst src));
9514 
9515   format %{ "FLD    $src\n\t"
9516             "DSUBp  $dst,ST" %}
9517   opcode(0xDE, 0x5); /* DE E8+i  or DE /5 */
9518   ins_cost(150);
9519   ins_encode( Push_Reg_DPR(src),
9520               OpcP, RegOpc(dst) );
9521   ins_pipe( fpu_reg_reg );
9522 %}
9523 
9524 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9525   predicate (UseSSE <=1);
9526   match(Set dst (RoundDouble (SubD src1 src2)));
9527   ins_cost(250);
9528 
9529   format %{ "FLD    $src2\n\t"
9530             "DSUB   ST,$src1\n\t"
9531             "FSTP_D $dst\t# D-round" %}
9532   opcode(0xD8, 0x5);
9533   ins_encode( Push_Reg_DPR(src2),
9534               OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9535   ins_pipe( fpu_mem_reg_reg );
9536 %}
9537 
9538 
9539 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9540   predicate (UseSSE <=1);
9541   match(Set dst (SubD dst (LoadD src)));
9542   ins_cost(150);
9543 
9544   format %{ "FLD    $src\n\t"
9545             "DSUBp  $dst,ST" %}
9546   opcode(0xDE, 0x5, 0xDD); /* DE C0+i */  /* LoadD  DD /0 */
9547   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9548               OpcP, RegOpc(dst) );
9549   ins_pipe( fpu_reg_mem );
9550 %}
9551 
9552 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9553   predicate (UseSSE<=1);
9554   match(Set dst (AbsD src));
9555   ins_cost(100);
9556   format %{ "FABS" %}
9557   opcode(0xE1, 0xD9);
9558   ins_encode( OpcS, OpcP );
9559   ins_pipe( fpu_reg_reg );
9560 %}
9561 
9562 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9563   predicate(UseSSE<=1);
9564   match(Set dst (NegD src));
9565   ins_cost(100);
9566   format %{ "FCHS" %}
9567   opcode(0xE0, 0xD9);
9568   ins_encode( OpcS, OpcP );
9569   ins_pipe( fpu_reg_reg );
9570 %}
9571 
9572 instruct addDPR_reg(regDPR dst, regDPR src) %{
9573   predicate(UseSSE<=1);
9574   match(Set dst (AddD dst src));
9575   format %{ "FLD    $src\n\t"
9576             "DADD   $dst,ST" %}
9577   size(4);
9578   ins_cost(150);
9579   opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9580   ins_encode( Push_Reg_DPR(src),
9581               OpcP, RegOpc(dst) );
9582   ins_pipe( fpu_reg_reg );
9583 %}
9584 
9585 
9586 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9587   predicate(UseSSE<=1);
9588   match(Set dst (RoundDouble (AddD src1 src2)));
9589   ins_cost(250);
9590 
9591   format %{ "FLD    $src2\n\t"
9592             "DADD   ST,$src1\n\t"
9593             "FSTP_D $dst\t# D-round" %}
9594   opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9595   ins_encode( Push_Reg_DPR(src2),
9596               OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9597   ins_pipe( fpu_mem_reg_reg );
9598 %}
9599 
9600 
9601 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9602   predicate(UseSSE<=1);
9603   match(Set dst (AddD dst (LoadD src)));
9604   ins_cost(150);
9605 
9606   format %{ "FLD    $src\n\t"
9607             "DADDp  $dst,ST" %}
9608   opcode(0xDE, 0x0, 0xDD); /* DE C0+i */  /* LoadD  DD /0 */
9609   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9610               OpcP, RegOpc(dst) );
9611   ins_pipe( fpu_reg_mem );
9612 %}
9613 
9614 // add-to-memory
9615 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9616   predicate(UseSSE<=1);
9617   match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9618   ins_cost(150);
9619 
9620   format %{ "FLD_D  $dst\n\t"
9621             "DADD   ST,$src\n\t"
9622             "FST_D  $dst" %}
9623   opcode(0xDD, 0x0);
9624   ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9625               Opcode(0xD8), RegOpc(src),
9626               set_instruction_start,
9627               Opcode(0xDD), RMopc_Mem(0x03,dst) );
9628   ins_pipe( fpu_reg_mem );
9629 %}
9630 
9631 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9632   predicate(UseSSE<=1);
9633   match(Set dst (AddD dst con));
9634   ins_cost(125);
9635   format %{ "FLD1\n\t"
9636             "DADDp  $dst,ST" %}
9637   ins_encode %{
9638     __ fld1();
9639     __ faddp($dst$$reg);
9640   %}
9641   ins_pipe(fpu_reg);
9642 %}
9643 
9644 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9645   predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9646   match(Set dst (AddD dst con));
9647   ins_cost(200);
9648   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9649             "DADDp  $dst,ST" %}
9650   ins_encode %{
9651     __ fld_d($constantaddress($con));
9652     __ faddp($dst$$reg);
9653   %}
9654   ins_pipe(fpu_reg_mem);
9655 %}
9656 
9657 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9658   predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9659   match(Set dst (RoundDouble (AddD src con)));
9660   ins_cost(200);
9661   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9662             "DADD   ST,$src\n\t"
9663             "FSTP_D $dst\t# D-round" %}
9664   ins_encode %{
9665     __ fld_d($constantaddress($con));
9666     __ fadd($src$$reg);
9667     __ fstp_d(Address(rsp, $dst$$disp));
9668   %}
9669   ins_pipe(fpu_mem_reg_con);
9670 %}
9671 
9672 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9673   predicate(UseSSE<=1);
9674   match(Set dst (MulD dst src));
9675   format %{ "FLD    $src\n\t"
9676             "DMULp  $dst,ST" %}
9677   opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9678   ins_cost(150);
9679   ins_encode( Push_Reg_DPR(src),
9680               OpcP, RegOpc(dst) );
9681   ins_pipe( fpu_reg_reg );
9682 %}
9683 
9684 // Strict FP instruction biases argument before multiply then
9685 // biases result to avoid double rounding of subnormals.
9686 //
9687 // scale arg1 by multiplying arg1 by 2^(-15360)
9688 // load arg2
9689 // multiply scaled arg1 by arg2
9690 // rescale product by 2^(15360)
9691 //
9692 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9693   predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9694   match(Set dst (MulD dst src));
9695   ins_cost(1);   // Select this instruction for all strict FP double multiplies
9696 
9697   format %{ "FLD    StubRoutines::_fpu_subnormal_bias1\n\t"
9698             "DMULp  $dst,ST\n\t"
9699             "FLD    $src\n\t"
9700             "DMULp  $dst,ST\n\t"
9701             "FLD    StubRoutines::_fpu_subnormal_bias2\n\t"
9702             "DMULp  $dst,ST\n\t" %}
9703   opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9704   ins_encode( strictfp_bias1(dst),
9705               Push_Reg_DPR(src),
9706               OpcP, RegOpc(dst),
9707               strictfp_bias2(dst) );
9708   ins_pipe( fpu_reg_reg );
9709 %}
9710 
9711 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9712   predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9713   match(Set dst (MulD dst con));
9714   ins_cost(200);
9715   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9716             "DMULp  $dst,ST" %}
9717   ins_encode %{
9718     __ fld_d($constantaddress($con));
9719     __ fmulp($dst$$reg);
9720   %}
9721   ins_pipe(fpu_reg_mem);
9722 %}
9723 
9724 
9725 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9726   predicate( UseSSE<=1 );
9727   match(Set dst (MulD dst (LoadD src)));
9728   ins_cost(200);
9729   format %{ "FLD_D  $src\n\t"
9730             "DMULp  $dst,ST" %}
9731   opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/  /* LoadD  DD /0 */
9732   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9733               OpcP, RegOpc(dst) );
9734   ins_pipe( fpu_reg_mem );
9735 %}
9736 
9737 //
9738 // Cisc-alternate to reg-reg multiply
9739 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9740   predicate( UseSSE<=1 );
9741   match(Set dst (MulD src (LoadD mem)));
9742   ins_cost(250);
9743   format %{ "FLD_D  $mem\n\t"
9744             "DMUL   ST,$src\n\t"
9745             "FSTP_D $dst" %}
9746   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */  /* LoadD D9 /0 */
9747   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9748               OpcReg_FPR(src),
9749               Pop_Reg_DPR(dst) );
9750   ins_pipe( fpu_reg_reg_mem );
9751 %}
9752 
9753 
9754 // MACRO3 -- addDPR a mulDPR
9755 // This instruction is a '2-address' instruction in that the result goes
9756 // back to src2.  This eliminates a move from the macro; possibly the
9757 // register allocator will have to add it back (and maybe not).
9758 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9759   predicate( UseSSE<=1 );
9760   match(Set src2 (AddD (MulD src0 src1) src2));
9761   format %{ "FLD    $src0\t# ===MACRO3d===\n\t"
9762             "DMUL   ST,$src1\n\t"
9763             "DADDp  $src2,ST" %}
9764   ins_cost(250);
9765   opcode(0xDD); /* LoadD DD /0 */
9766   ins_encode( Push_Reg_FPR(src0),
9767               FMul_ST_reg(src1),
9768               FAddP_reg_ST(src2) );
9769   ins_pipe( fpu_reg_reg_reg );
9770 %}
9771 
9772 
9773 // MACRO3 -- subDPR a mulDPR
9774 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9775   predicate( UseSSE<=1 );
9776   match(Set src2 (SubD (MulD src0 src1) src2));
9777   format %{ "FLD    $src0\t# ===MACRO3d===\n\t"
9778             "DMUL   ST,$src1\n\t"
9779             "DSUBRp $src2,ST" %}
9780   ins_cost(250);
9781   ins_encode( Push_Reg_FPR(src0),
9782               FMul_ST_reg(src1),
9783               Opcode(0xDE), Opc_plus(0xE0,src2));
9784   ins_pipe( fpu_reg_reg_reg );
9785 %}
9786 
9787 
9788 instruct divDPR_reg(regDPR dst, regDPR src) %{
9789   predicate( UseSSE<=1 );
9790   match(Set dst (DivD dst src));
9791 
9792   format %{ "FLD    $src\n\t"
9793             "FDIVp  $dst,ST" %}
9794   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9795   ins_cost(150);
9796   ins_encode( Push_Reg_DPR(src),
9797               OpcP, RegOpc(dst) );
9798   ins_pipe( fpu_reg_reg );
9799 %}
9800 
9801 // Strict FP instruction biases argument before division then
9802 // biases result, to avoid double rounding of subnormals.
9803 //
9804 // scale dividend by multiplying dividend by 2^(-15360)
9805 // load divisor
9806 // divide scaled dividend by divisor
9807 // rescale quotient by 2^(15360)
9808 //
9809 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9810   predicate (UseSSE<=1);
9811   match(Set dst (DivD dst src));
9812   predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9813   ins_cost(01);
9814 
9815   format %{ "FLD    StubRoutines::_fpu_subnormal_bias1\n\t"
9816             "DMULp  $dst,ST\n\t"
9817             "FLD    $src\n\t"
9818             "FDIVp  $dst,ST\n\t"
9819             "FLD    StubRoutines::_fpu_subnormal_bias2\n\t"
9820             "DMULp  $dst,ST\n\t" %}
9821   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9822   ins_encode( strictfp_bias1(dst),
9823               Push_Reg_DPR(src),
9824               OpcP, RegOpc(dst),
9825               strictfp_bias2(dst) );
9826   ins_pipe( fpu_reg_reg );
9827 %}
9828 
9829 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9830   predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9831   match(Set dst (RoundDouble (DivD src1 src2)));
9832 
9833   format %{ "FLD    $src1\n\t"
9834             "FDIV   ST,$src2\n\t"
9835             "FSTP_D $dst\t# D-round" %}
9836   opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9837   ins_encode( Push_Reg_DPR(src1),
9838               OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9839   ins_pipe( fpu_mem_reg_reg );
9840 %}
9841 
9842 
9843 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9844   predicate(UseSSE<=1);
9845   match(Set dst (ModD dst src));
9846   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9847 
9848   format %{ "DMOD   $dst,$src" %}
9849   ins_cost(250);
9850   ins_encode(Push_Reg_Mod_DPR(dst, src),
9851               emitModDPR(),
9852               Push_Result_Mod_DPR(src),
9853               Pop_Reg_DPR(dst));
9854   ins_pipe( pipe_slow );
9855 %}
9856 
9857 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9858   predicate(UseSSE>=2);
9859   match(Set dst (ModD src0 src1));
9860   effect(KILL rax, KILL cr);
9861 
9862   format %{ "SUB    ESP,8\t # DMOD\n"
9863           "\tMOVSD  [ESP+0],$src1\n"
9864           "\tFLD_D  [ESP+0]\n"
9865           "\tMOVSD  [ESP+0],$src0\n"
9866           "\tFLD_D  [ESP+0]\n"
9867      "loop:\tFPREM\n"
9868           "\tFWAIT\n"
9869           "\tFNSTSW AX\n"
9870           "\tSAHF\n"
9871           "\tJP     loop\n"
9872           "\tFSTP_D [ESP+0]\n"
9873           "\tMOVSD  $dst,[ESP+0]\n"
9874           "\tADD    ESP,8\n"
9875           "\tFSTP   ST0\t # Restore FPU Stack"
9876     %}
9877   ins_cost(250);
9878   ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9879   ins_pipe( pipe_slow );
9880 %}
9881 
9882 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9883   predicate (UseSSE<=1);
9884   match(Set dst (SinD src));
9885   ins_cost(1800);
9886   format %{ "DSIN   $dst" %}
9887   opcode(0xD9, 0xFE);
9888   ins_encode( OpcP, OpcS );
9889   ins_pipe( pipe_slow );
9890 %}
9891 
9892 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9893   predicate (UseSSE>=2);
9894   match(Set dst (SinD dst));
9895   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9896   ins_cost(1800);
9897   format %{ "DSIN   $dst" %}
9898   opcode(0xD9, 0xFE);
9899   ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9900   ins_pipe( pipe_slow );
9901 %}
9902 
9903 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9904   predicate (UseSSE<=1);
9905   match(Set dst (CosD src));
9906   ins_cost(1800);
9907   format %{ "DCOS   $dst" %}
9908   opcode(0xD9, 0xFF);
9909   ins_encode( OpcP, OpcS );
9910   ins_pipe( pipe_slow );
9911 %}
9912 
9913 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9914   predicate (UseSSE>=2);
9915   match(Set dst (CosD dst));
9916   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9917   ins_cost(1800);
9918   format %{ "DCOS   $dst" %}
9919   opcode(0xD9, 0xFF);
9920   ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9921   ins_pipe( pipe_slow );
9922 %}
9923 
9924 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9925   predicate (UseSSE<=1);
9926   match(Set dst(TanD src));
9927   format %{ "DTAN   $dst" %}
9928   ins_encode( Opcode(0xD9), Opcode(0xF2),    // fptan
9929               Opcode(0xDD), Opcode(0xD8));   // fstp st
9930   ins_pipe( pipe_slow );
9931 %}
9932 
9933 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9934   predicate (UseSSE>=2);
9935   match(Set dst(TanD dst));
9936   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9937   format %{ "DTAN   $dst" %}
9938   ins_encode( Push_SrcD(dst),
9939               Opcode(0xD9), Opcode(0xF2),    // fptan
9940               Opcode(0xDD), Opcode(0xD8),   // fstp st
9941               Push_ResultD(dst) );
9942   ins_pipe( pipe_slow );
9943 %}
9944 
9945 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9946   predicate (UseSSE<=1);
9947   match(Set dst(AtanD dst src));
9948   format %{ "DATA   $dst,$src" %}
9949   opcode(0xD9, 0xF3);
9950   ins_encode( Push_Reg_DPR(src),
9951               OpcP, OpcS, RegOpc(dst) );
9952   ins_pipe( pipe_slow );
9953 %}
9954 
9955 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9956   predicate (UseSSE>=2);
9957   match(Set dst(AtanD dst src));
9958   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9959   format %{ "DATA   $dst,$src" %}
9960   opcode(0xD9, 0xF3);
9961   ins_encode( Push_SrcD(src),
9962               OpcP, OpcS, Push_ResultD(dst) );
9963   ins_pipe( pipe_slow );
9964 %}
9965 
9966 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9967   predicate (UseSSE<=1);
9968   match(Set dst (SqrtD src));
9969   format %{ "DSQRT  $dst,$src" %}
9970   opcode(0xFA, 0xD9);
9971   ins_encode( Push_Reg_DPR(src),
9972               OpcS, OpcP, Pop_Reg_DPR(dst) );
9973   ins_pipe( pipe_slow );
9974 %}
9975 
9976 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9977   predicate (UseSSE<=1);
9978   match(Set Y (PowD X Y));  // Raise X to the Yth power
9979   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9980   format %{ "fast_pow $X $Y -> $Y  // KILL $rax, $rcx, $rdx" %}
9981   ins_encode %{
9982     __ subptr(rsp, 8);
9983     __ fld_s($X$$reg - 1);
9984     __ fast_pow();
9985     __ addptr(rsp, 8);
9986   %}
9987   ins_pipe( pipe_slow );
9988 %}
9989 
9990 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9991   predicate (UseSSE>=2);
9992   match(Set dst (PowD src0 src1));  // Raise src0 to the src1'th power
9993   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9994   format %{ "fast_pow $src0 $src1 -> $dst  // KILL $rax, $rcx, $rdx" %}
9995   ins_encode %{
9996     __ subptr(rsp, 8);
9997     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9998     __ fld_d(Address(rsp, 0));
9999     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10000     __ fld_d(Address(rsp, 0));
10001     __ fast_pow();
10002     __ fstp_d(Address(rsp, 0));
10003     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10004     __ addptr(rsp, 8);
10005   %}
10006   ins_pipe( pipe_slow );
10007 %}
10008 
10009 
10010 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10011   predicate (UseSSE<=1);
10012   match(Set dpr1 (ExpD dpr1));
10013   effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10014   format %{ "fast_exp $dpr1 -> $dpr1  // KILL $rax, $rcx, $rdx" %}
10015   ins_encode %{
10016     __ fast_exp();
10017   %}
10018   ins_pipe( pipe_slow );
10019 %}
10020 
10021 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10022   predicate (UseSSE>=2);
10023   match(Set dst (ExpD src));
10024   effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10025   format %{ "fast_exp $dst -> $src  // KILL $rax, $rcx, $rdx" %}
10026   ins_encode %{
10027     __ subptr(rsp, 8);
10028     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10029     __ fld_d(Address(rsp, 0));
10030     __ fast_exp();
10031     __ fstp_d(Address(rsp, 0));
10032     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10033     __ addptr(rsp, 8);
10034   %}
10035   ins_pipe( pipe_slow );
10036 %}
10037 
10038 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10039   predicate (UseSSE<=1);
10040   // The source Double operand on FPU stack
10041   match(Set dst (Log10D src));
10042   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
10043   // fxch         ; swap ST(0) with ST(1)
10044   // fyl2x        ; compute log_10(2) * log_2(x)
10045   format %{ "FLDLG2 \t\t\t#Log10\n\t"
10046             "FXCH   \n\t"
10047             "FYL2X  \t\t\t# Q=Log10*Log_2(x)"
10048          %}
10049   ins_encode( Opcode(0xD9), Opcode(0xEC),   // fldlg2
10050               Opcode(0xD9), Opcode(0xC9),   // fxch
10051               Opcode(0xD9), Opcode(0xF1));  // fyl2x
10052 
10053   ins_pipe( pipe_slow );
10054 %}
10055 
10056 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10057   predicate (UseSSE>=2);
10058   effect(KILL cr);
10059   match(Set dst (Log10D src));
10060   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
10061   // fyl2x        ; compute log_10(2) * log_2(x)
10062   format %{ "FLDLG2 \t\t\t#Log10\n\t"
10063             "FYL2X  \t\t\t# Q=Log10*Log_2(x)"
10064          %}
10065   ins_encode( Opcode(0xD9), Opcode(0xEC),   // fldlg2
10066               Push_SrcD(src),
10067               Opcode(0xD9), Opcode(0xF1),   // fyl2x
10068               Push_ResultD(dst));
10069 
10070   ins_pipe( pipe_slow );
10071 %}
10072 
10073 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10074   predicate (UseSSE<=1);
10075   // The source Double operand on FPU stack
10076   match(Set dst (LogD src));
10077   // fldln2       ; push log_e(2) on the FPU stack; full 80-bit number
10078   // fxch         ; swap ST(0) with ST(1)
10079   // fyl2x        ; compute log_e(2) * log_2(x)
10080   format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10081             "FXCH   \n\t"
10082             "FYL2X  \t\t\t# Q=Log_e*Log_2(x)"
10083          %}
10084   ins_encode( Opcode(0xD9), Opcode(0xED),   // fldln2
10085               Opcode(0xD9), Opcode(0xC9),   // fxch
10086               Opcode(0xD9), Opcode(0xF1));  // fyl2x
10087 
10088   ins_pipe( pipe_slow );
10089 %}
10090 
10091 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10092   predicate (UseSSE>=2);
10093   effect(KILL cr);
10094   // The source and result Double operands in XMM registers
10095   match(Set dst (LogD src));
10096   // fldln2       ; push log_e(2) on the FPU stack; full 80-bit number
10097   // fyl2x        ; compute log_e(2) * log_2(x)
10098   format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10099             "FYL2X  \t\t\t# Q=Log_e*Log_2(x)"
10100          %}
10101   ins_encode( Opcode(0xD9), Opcode(0xED),   // fldln2
10102               Push_SrcD(src),
10103               Opcode(0xD9), Opcode(0xF1),   // fyl2x
10104               Push_ResultD(dst));
10105   ins_pipe( pipe_slow );
10106 %}
10107 
10108 //-------------Float Instructions-------------------------------
10109 // Float Math
10110 
10111 // Code for float compare:
10112 //     fcompp();
10113 //     fwait(); fnstsw_ax();
10114 //     sahf();
10115 //     movl(dst, unordered_result);
10116 //     jcc(Assembler::parity, exit);
10117 //     movl(dst, less_result);
10118 //     jcc(Assembler::below, exit);
10119 //     movl(dst, equal_result);
10120 //     jcc(Assembler::equal, exit);
10121 //     movl(dst, greater_result);
10122 //   exit:
10123 
10124 // P6 version of float compare, sets condition codes in EFLAGS
10125 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10126   predicate(VM_Version::supports_cmov() && UseSSE == 0);
10127   match(Set cr (CmpF src1 src2));
10128   effect(KILL rax);
10129   ins_cost(150);
10130   format %{ "FLD    $src1\n\t"
10131             "FUCOMIP ST,$src2  // P6 instruction\n\t"
10132             "JNP    exit\n\t"
10133             "MOV    ah,1       // saw a NaN, set CF (treat as LT)\n\t"
10134             "SAHF\n"
10135      "exit:\tNOP               // avoid branch to branch" %}
10136   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10137   ins_encode( Push_Reg_DPR(src1),
10138               OpcP, RegOpc(src2),
10139               cmpF_P6_fixup );
10140   ins_pipe( pipe_slow );
10141 %}
10142 
10143 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10144   predicate(VM_Version::supports_cmov() && UseSSE == 0);
10145   match(Set cr (CmpF src1 src2));
10146   ins_cost(100);
10147   format %{ "FLD    $src1\n\t"
10148             "FUCOMIP ST,$src2  // P6 instruction" %}
10149   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10150   ins_encode( Push_Reg_DPR(src1),
10151               OpcP, RegOpc(src2));
10152   ins_pipe( pipe_slow );
10153 %}
10154 
10155 
10156 // Compare & branch
10157 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10158   predicate(UseSSE == 0);
10159   match(Set cr (CmpF src1 src2));
10160   effect(KILL rax);
10161   ins_cost(200);
10162   format %{ "FLD    $src1\n\t"
10163             "FCOMp  $src2\n\t"
10164             "FNSTSW AX\n\t"
10165             "TEST   AX,0x400\n\t"
10166             "JZ,s   flags\n\t"
10167             "MOV    AH,1\t# unordered treat as LT\n"
10168     "flags:\tSAHF" %}
10169   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10170   ins_encode( Push_Reg_DPR(src1),
10171               OpcP, RegOpc(src2),
10172               fpu_flags);
10173   ins_pipe( pipe_slow );
10174 %}
10175 
10176 // Compare vs zero into -1,0,1
10177 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10178   predicate(UseSSE == 0);
10179   match(Set dst (CmpF3 src1 zero));
10180   effect(KILL cr, KILL rax);
10181   ins_cost(280);
10182   format %{ "FTSTF  $dst,$src1" %}
10183   opcode(0xE4, 0xD9);
10184   ins_encode( Push_Reg_DPR(src1),
10185               OpcS, OpcP, PopFPU,
10186               CmpF_Result(dst));
10187   ins_pipe( pipe_slow );
10188 %}
10189 
10190 // Compare into -1,0,1
10191 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10192   predicate(UseSSE == 0);
10193   match(Set dst (CmpF3 src1 src2));
10194   effect(KILL cr, KILL rax);
10195   ins_cost(300);
10196   format %{ "FCMPF  $dst,$src1,$src2" %}
10197   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10198   ins_encode( Push_Reg_DPR(src1),
10199               OpcP, RegOpc(src2),
10200               CmpF_Result(dst));
10201   ins_pipe( pipe_slow );
10202 %}
10203 
10204 // float compare and set condition codes in EFLAGS by XMM regs
10205 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10206   predicate(UseSSE>=1);
10207   match(Set cr (CmpF src1 src2));
10208   ins_cost(145);
10209   format %{ "UCOMISS $src1,$src2\n\t"
10210             "JNP,s   exit\n\t"
10211             "PUSHF\t# saw NaN, set CF\n\t"
10212             "AND     [rsp], #0xffffff2b\n\t"
10213             "POPF\n"
10214     "exit:" %}
10215   ins_encode %{
10216     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10217     emit_cmpfp_fixup(_masm);
10218   %}
10219   ins_pipe( pipe_slow );
10220 %}
10221 
10222 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10223   predicate(UseSSE>=1);
10224   match(Set cr (CmpF src1 src2));
10225   ins_cost(100);
10226   format %{ "UCOMISS $src1,$src2" %}
10227   ins_encode %{
10228     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10229   %}
10230   ins_pipe( pipe_slow );
10231 %}
10232 
10233 // float compare and set condition codes in EFLAGS by XMM regs
10234 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10235   predicate(UseSSE>=1);
10236   match(Set cr (CmpF src1 (LoadF src2)));
10237   ins_cost(165);
10238   format %{ "UCOMISS $src1,$src2\n\t"
10239             "JNP,s   exit\n\t"
10240             "PUSHF\t# saw NaN, set CF\n\t"
10241             "AND     [rsp], #0xffffff2b\n\t"
10242             "POPF\n"
10243     "exit:" %}
10244   ins_encode %{
10245     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10246     emit_cmpfp_fixup(_masm);
10247   %}
10248   ins_pipe( pipe_slow );
10249 %}
10250 
10251 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10252   predicate(UseSSE>=1);
10253   match(Set cr (CmpF src1 (LoadF src2)));
10254   ins_cost(100);
10255   format %{ "UCOMISS $src1,$src2" %}
10256   ins_encode %{
10257     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10258   %}
10259   ins_pipe( pipe_slow );
10260 %}
10261 
10262 // Compare into -1,0,1 in XMM
10263 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10264   predicate(UseSSE>=1);
10265   match(Set dst (CmpF3 src1 src2));
10266   effect(KILL cr);
10267   ins_cost(255);
10268   format %{ "UCOMISS $src1, $src2\n\t"
10269             "MOV     $dst, #-1\n\t"
10270             "JP,s    done\n\t"
10271             "JB,s    done\n\t"
10272             "SETNE   $dst\n\t"
10273             "MOVZB   $dst, $dst\n"
10274     "done:" %}
10275   ins_encode %{
10276     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10277     emit_cmpfp3(_masm, $dst$$Register);
10278   %}
10279   ins_pipe( pipe_slow );
10280 %}
10281 
10282 // Compare into -1,0,1 in XMM and memory
10283 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10284   predicate(UseSSE>=1);
10285   match(Set dst (CmpF3 src1 (LoadF src2)));
10286   effect(KILL cr);
10287   ins_cost(275);
10288   format %{ "UCOMISS $src1, $src2\n\t"
10289             "MOV     $dst, #-1\n\t"
10290             "JP,s    done\n\t"
10291             "JB,s    done\n\t"
10292             "SETNE   $dst\n\t"
10293             "MOVZB   $dst, $dst\n"
10294     "done:" %}
10295   ins_encode %{
10296     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10297     emit_cmpfp3(_masm, $dst$$Register);
10298   %}
10299   ins_pipe( pipe_slow );
10300 %}
10301 
10302 // Spill to obtain 24-bit precision
10303 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10304   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10305   match(Set dst (SubF src1 src2));
10306 
10307   format %{ "FSUB   $dst,$src1 - $src2" %}
10308   opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10309   ins_encode( Push_Reg_FPR(src1),
10310               OpcReg_FPR(src2),
10311               Pop_Mem_FPR(dst) );
10312   ins_pipe( fpu_mem_reg_reg );
10313 %}
10314 //
10315 // This instruction does not round to 24-bits
10316 instruct subFPR_reg(regFPR dst, regFPR src) %{
10317   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10318   match(Set dst (SubF dst src));
10319 
10320   format %{ "FSUB   $dst,$src" %}
10321   opcode(0xDE, 0x5); /* DE E8+i  or DE /5 */
10322   ins_encode( Push_Reg_FPR(src),
10323               OpcP, RegOpc(dst) );
10324   ins_pipe( fpu_reg_reg );
10325 %}
10326 
10327 // Spill to obtain 24-bit precision
10328 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10329   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10330   match(Set dst (AddF src1 src2));
10331 
10332   format %{ "FADD   $dst,$src1,$src2" %}
10333   opcode(0xD8, 0x0); /* D8 C0+i */
10334   ins_encode( Push_Reg_FPR(src2),
10335               OpcReg_FPR(src1),
10336               Pop_Mem_FPR(dst) );
10337   ins_pipe( fpu_mem_reg_reg );
10338 %}
10339 //
10340 // This instruction does not round to 24-bits
10341 instruct addFPR_reg(regFPR dst, regFPR src) %{
10342   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10343   match(Set dst (AddF dst src));
10344 
10345   format %{ "FLD    $src\n\t"
10346             "FADDp  $dst,ST" %}
10347   opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10348   ins_encode( Push_Reg_FPR(src),
10349               OpcP, RegOpc(dst) );
10350   ins_pipe( fpu_reg_reg );
10351 %}
10352 
10353 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10354   predicate(UseSSE==0);
10355   match(Set dst (AbsF src));
10356   ins_cost(100);
10357   format %{ "FABS" %}
10358   opcode(0xE1, 0xD9);
10359   ins_encode( OpcS, OpcP );
10360   ins_pipe( fpu_reg_reg );
10361 %}
10362 
10363 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10364   predicate(UseSSE==0);
10365   match(Set dst (NegF src));
10366   ins_cost(100);
10367   format %{ "FCHS" %}
10368   opcode(0xE0, 0xD9);
10369   ins_encode( OpcS, OpcP );
10370   ins_pipe( fpu_reg_reg );
10371 %}
10372 
10373 // Cisc-alternate to addFPR_reg
10374 // Spill to obtain 24-bit precision
10375 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10376   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10377   match(Set dst (AddF src1 (LoadF src2)));
10378 
10379   format %{ "FLD    $src2\n\t"
10380             "FADD   ST,$src1\n\t"
10381             "FSTP_S $dst" %}
10382   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10383   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10384               OpcReg_FPR(src1),
10385               Pop_Mem_FPR(dst) );
10386   ins_pipe( fpu_mem_reg_mem );
10387 %}
10388 //
10389 // Cisc-alternate to addFPR_reg
10390 // This instruction does not round to 24-bits
10391 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10392   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10393   match(Set dst (AddF dst (LoadF src)));
10394 
10395   format %{ "FADD   $dst,$src" %}
10396   opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/  /* LoadF  D9 /0 */
10397   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10398               OpcP, RegOpc(dst) );
10399   ins_pipe( fpu_reg_mem );
10400 %}
10401 
10402 // // Following two instructions for _222_mpegaudio
10403 // Spill to obtain 24-bit precision
10404 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10405   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10406   match(Set dst (AddF src1 src2));
10407 
10408   format %{ "FADD   $dst,$src1,$src2" %}
10409   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10410   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10411               OpcReg_FPR(src2),
10412               Pop_Mem_FPR(dst) );
10413   ins_pipe( fpu_mem_reg_mem );
10414 %}
10415 
10416 // Cisc-spill variant
10417 // Spill to obtain 24-bit precision
10418 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10419   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10420   match(Set dst (AddF src1 (LoadF src2)));
10421 
10422   format %{ "FADD   $dst,$src1,$src2 cisc" %}
10423   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10424   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10425               set_instruction_start,
10426               OpcP, RMopc_Mem(secondary,src1),
10427               Pop_Mem_FPR(dst) );
10428   ins_pipe( fpu_mem_mem_mem );
10429 %}
10430 
10431 // Spill to obtain 24-bit precision
10432 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10433   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10434   match(Set dst (AddF src1 src2));
10435 
10436   format %{ "FADD   $dst,$src1,$src2" %}
10437   opcode(0xD8, 0x0, 0xD9); /* D8 /0 */  /* LoadF  D9 /0 */
10438   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10439               set_instruction_start,
10440               OpcP, RMopc_Mem(secondary,src1),
10441               Pop_Mem_FPR(dst) );
10442   ins_pipe( fpu_mem_mem_mem );
10443 %}
10444 
10445 
10446 // Spill to obtain 24-bit precision
10447 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10448   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10449   match(Set dst (AddF src con));
10450   format %{ "FLD    $src\n\t"
10451             "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10452             "FSTP_S $dst"  %}
10453   ins_encode %{
10454     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10455     __ fadd_s($constantaddress($con));
10456     __ fstp_s(Address(rsp, $dst$$disp));
10457   %}
10458   ins_pipe(fpu_mem_reg_con);
10459 %}
10460 //
10461 // This instruction does not round to 24-bits
10462 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10463   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10464   match(Set dst (AddF src con));
10465   format %{ "FLD    $src\n\t"
10466             "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10467             "FSTP   $dst"  %}
10468   ins_encode %{
10469     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10470     __ fadd_s($constantaddress($con));
10471     __ fstp_d($dst$$reg);
10472   %}
10473   ins_pipe(fpu_reg_reg_con);
10474 %}
10475 
10476 // Spill to obtain 24-bit precision
10477 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10478   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10479   match(Set dst (MulF src1 src2));
10480 
10481   format %{ "FLD    $src1\n\t"
10482             "FMUL   $src2\n\t"
10483             "FSTP_S $dst"  %}
10484   opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10485   ins_encode( Push_Reg_FPR(src1),
10486               OpcReg_FPR(src2),
10487               Pop_Mem_FPR(dst) );
10488   ins_pipe( fpu_mem_reg_reg );
10489 %}
10490 //
10491 // This instruction does not round to 24-bits
10492 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10493   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10494   match(Set dst (MulF src1 src2));
10495 
10496   format %{ "FLD    $src1\n\t"
10497             "FMUL   $src2\n\t"
10498             "FSTP_S $dst"  %}
10499   opcode(0xD8, 0x1); /* D8 C8+i */
10500   ins_encode( Push_Reg_FPR(src2),
10501               OpcReg_FPR(src1),
10502               Pop_Reg_FPR(dst) );
10503   ins_pipe( fpu_reg_reg_reg );
10504 %}
10505 
10506 
10507 // Spill to obtain 24-bit precision
10508 // Cisc-alternate to reg-reg multiply
10509 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10510   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10511   match(Set dst (MulF src1 (LoadF src2)));
10512 
10513   format %{ "FLD_S  $src2\n\t"
10514             "FMUL   $src1\n\t"
10515             "FSTP_S $dst"  %}
10516   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/  /* LoadF D9 /0 */
10517   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10518               OpcReg_FPR(src1),
10519               Pop_Mem_FPR(dst) );
10520   ins_pipe( fpu_mem_reg_mem );
10521 %}
10522 //
10523 // This instruction does not round to 24-bits
10524 // Cisc-alternate to reg-reg multiply
10525 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10526   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10527   match(Set dst (MulF src1 (LoadF src2)));
10528 
10529   format %{ "FMUL   $dst,$src1,$src2" %}
10530   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */  /* LoadF D9 /0 */
10531   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10532               OpcReg_FPR(src1),
10533               Pop_Reg_FPR(dst) );
10534   ins_pipe( fpu_reg_reg_mem );
10535 %}
10536 
10537 // Spill to obtain 24-bit precision
10538 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10539   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10540   match(Set dst (MulF src1 src2));
10541 
10542   format %{ "FMUL   $dst,$src1,$src2" %}
10543   opcode(0xD8, 0x1, 0xD9); /* D8 /1 */  /* LoadF D9 /0 */
10544   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10545               set_instruction_start,
10546               OpcP, RMopc_Mem(secondary,src1),
10547               Pop_Mem_FPR(dst) );
10548   ins_pipe( fpu_mem_mem_mem );
10549 %}
10550 
10551 // Spill to obtain 24-bit precision
10552 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10553   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10554   match(Set dst (MulF src con));
10555 
10556   format %{ "FLD    $src\n\t"
10557             "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10558             "FSTP_S $dst"  %}
10559   ins_encode %{
10560     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10561     __ fmul_s($constantaddress($con));
10562     __ fstp_s(Address(rsp, $dst$$disp));
10563   %}
10564   ins_pipe(fpu_mem_reg_con);
10565 %}
10566 //
10567 // This instruction does not round to 24-bits
10568 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10569   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10570   match(Set dst (MulF src con));
10571 
10572   format %{ "FLD    $src\n\t"
10573             "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10574             "FSTP   $dst"  %}
10575   ins_encode %{
10576     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10577     __ fmul_s($constantaddress($con));
10578     __ fstp_d($dst$$reg);
10579   %}
10580   ins_pipe(fpu_reg_reg_con);
10581 %}
10582 
10583 
10584 //
10585 // MACRO1 -- subsume unshared load into mulFPR
10586 // This instruction does not round to 24-bits
10587 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10588   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10589   match(Set dst (MulF (LoadF mem1) src));
10590 
10591   format %{ "FLD    $mem1    ===MACRO1===\n\t"
10592             "FMUL   ST,$src\n\t"
10593             "FSTP   $dst" %}
10594   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */  /* LoadF D9 /0 */
10595   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10596               OpcReg_FPR(src),
10597               Pop_Reg_FPR(dst) );
10598   ins_pipe( fpu_reg_reg_mem );
10599 %}
10600 //
10601 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10602 // This instruction does not round to 24-bits
10603 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10604   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10605   match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10606   ins_cost(95);
10607 
10608   format %{ "FLD    $mem1     ===MACRO2===\n\t"
10609             "FMUL   ST,$src1  subsume mulFPR left load\n\t"
10610             "FADD   ST,$src2\n\t"
10611             "FSTP   $dst" %}
10612   opcode(0xD9); /* LoadF D9 /0 */
10613   ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10614               FMul_ST_reg(src1),
10615               FAdd_ST_reg(src2),
10616               Pop_Reg_FPR(dst) );
10617   ins_pipe( fpu_reg_mem_reg_reg );
10618 %}
10619 
10620 // MACRO3 -- addFPR a mulFPR
10621 // This instruction does not round to 24-bits.  It is a '2-address'
10622 // instruction in that the result goes back to src2.  This eliminates
10623 // a move from the macro; possibly the register allocator will have
10624 // to add it back (and maybe not).
10625 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10626   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10627   match(Set src2 (AddF (MulF src0 src1) src2));
10628 
10629   format %{ "FLD    $src0     ===MACRO3===\n\t"
10630             "FMUL   ST,$src1\n\t"
10631             "FADDP  $src2,ST" %}
10632   opcode(0xD9); /* LoadF D9 /0 */
10633   ins_encode( Push_Reg_FPR(src0),
10634               FMul_ST_reg(src1),
10635               FAddP_reg_ST(src2) );
10636   ins_pipe( fpu_reg_reg_reg );
10637 %}
10638 
10639 // MACRO4 -- divFPR subFPR
10640 // This instruction does not round to 24-bits
10641 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10642   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10643   match(Set dst (DivF (SubF src2 src1) src3));
10644 
10645   format %{ "FLD    $src2   ===MACRO4===\n\t"
10646             "FSUB   ST,$src1\n\t"
10647             "FDIV   ST,$src3\n\t"
10648             "FSTP  $dst" %}
10649   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10650   ins_encode( Push_Reg_FPR(src2),
10651               subFPR_divFPR_encode(src1,src3),
10652               Pop_Reg_FPR(dst) );
10653   ins_pipe( fpu_reg_reg_reg_reg );
10654 %}
10655 
10656 // Spill to obtain 24-bit precision
10657 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10658   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10659   match(Set dst (DivF src1 src2));
10660 
10661   format %{ "FDIV   $dst,$src1,$src2" %}
10662   opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10663   ins_encode( Push_Reg_FPR(src1),
10664               OpcReg_FPR(src2),
10665               Pop_Mem_FPR(dst) );
10666   ins_pipe( fpu_mem_reg_reg );
10667 %}
10668 //
10669 // This instruction does not round to 24-bits
10670 instruct divFPR_reg(regFPR dst, regFPR src) %{
10671   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10672   match(Set dst (DivF dst src));
10673 
10674   format %{ "FDIV   $dst,$src" %}
10675   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10676   ins_encode( Push_Reg_FPR(src),
10677               OpcP, RegOpc(dst) );
10678   ins_pipe( fpu_reg_reg );
10679 %}
10680 
10681 
10682 // Spill to obtain 24-bit precision
10683 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10684   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10685   match(Set dst (ModF src1 src2));
10686   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10687 
10688   format %{ "FMOD   $dst,$src1,$src2" %}
10689   ins_encode( Push_Reg_Mod_DPR(src1, src2),
10690               emitModDPR(),
10691               Push_Result_Mod_DPR(src2),
10692               Pop_Mem_FPR(dst));
10693   ins_pipe( pipe_slow );
10694 %}
10695 //
10696 // This instruction does not round to 24-bits
10697 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10698   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10699   match(Set dst (ModF dst src));
10700   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10701 
10702   format %{ "FMOD   $dst,$src" %}
10703   ins_encode(Push_Reg_Mod_DPR(dst, src),
10704               emitModDPR(),
10705               Push_Result_Mod_DPR(src),
10706               Pop_Reg_FPR(dst));
10707   ins_pipe( pipe_slow );
10708 %}
10709 
10710 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10711   predicate(UseSSE>=1);
10712   match(Set dst (ModF src0 src1));
10713   effect(KILL rax, KILL cr);
10714   format %{ "SUB    ESP,4\t # FMOD\n"
10715           "\tMOVSS  [ESP+0],$src1\n"
10716           "\tFLD_S  [ESP+0]\n"
10717           "\tMOVSS  [ESP+0],$src0\n"
10718           "\tFLD_S  [ESP+0]\n"
10719      "loop:\tFPREM\n"
10720           "\tFWAIT\n"
10721           "\tFNSTSW AX\n"
10722           "\tSAHF\n"
10723           "\tJP     loop\n"
10724           "\tFSTP_S [ESP+0]\n"
10725           "\tMOVSS  $dst,[ESP+0]\n"
10726           "\tADD    ESP,4\n"
10727           "\tFSTP   ST0\t # Restore FPU Stack"
10728     %}
10729   ins_cost(250);
10730   ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10731   ins_pipe( pipe_slow );
10732 %}
10733 
10734 
10735 //----------Arithmetic Conversion Instructions---------------------------------
10736 // The conversions operations are all Alpha sorted.  Please keep it that way!
10737 
10738 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10739   predicate(UseSSE==0);
10740   match(Set dst (RoundFloat src));
10741   ins_cost(125);
10742   format %{ "FST_S  $dst,$src\t# F-round" %}
10743   ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10744   ins_pipe( fpu_mem_reg );
10745 %}
10746 
10747 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10748   predicate(UseSSE<=1);
10749   match(Set dst (RoundDouble src));
10750   ins_cost(125);
10751   format %{ "FST_D  $dst,$src\t# D-round" %}
10752   ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10753   ins_pipe( fpu_mem_reg );
10754 %}
10755 
10756 // Force rounding to 24-bit precision and 6-bit exponent
10757 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10758   predicate(UseSSE==0);
10759   match(Set dst (ConvD2F src));
10760   format %{ "FST_S  $dst,$src\t# F-round" %}
10761   expand %{
10762     roundFloat_mem_reg(dst,src);
10763   %}
10764 %}
10765 
10766 // Force rounding to 24-bit precision and 6-bit exponent
10767 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10768   predicate(UseSSE==1);
10769   match(Set dst (ConvD2F src));
10770   effect( KILL cr );
10771   format %{ "SUB    ESP,4\n\t"
10772             "FST_S  [ESP],$src\t# F-round\n\t"
10773             "MOVSS  $dst,[ESP]\n\t"
10774             "ADD ESP,4" %}
10775   ins_encode %{
10776     __ subptr(rsp, 4);
10777     if ($src$$reg != FPR1L_enc) {
10778       __ fld_s($src$$reg-1);
10779       __ fstp_s(Address(rsp, 0));
10780     } else {
10781       __ fst_s(Address(rsp, 0));
10782     }
10783     __ movflt($dst$$XMMRegister, Address(rsp, 0));
10784     __ addptr(rsp, 4);
10785   %}
10786   ins_pipe( pipe_slow );
10787 %}
10788 
10789 // Force rounding double precision to single precision
10790 instruct convD2F_reg(regF dst, regD src) %{
10791   predicate(UseSSE>=2);
10792   match(Set dst (ConvD2F src));
10793   format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10794   ins_encode %{
10795     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10796   %}
10797   ins_pipe( pipe_slow );
10798 %}
10799 
10800 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10801   predicate(UseSSE==0);
10802   match(Set dst (ConvF2D src));
10803   format %{ "FST_S  $dst,$src\t# D-round" %}
10804   ins_encode( Pop_Reg_Reg_DPR(dst, src));
10805   ins_pipe( fpu_reg_reg );
10806 %}
10807 
10808 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10809   predicate(UseSSE==1);
10810   match(Set dst (ConvF2D src));
10811   format %{ "FST_D  $dst,$src\t# D-round" %}
10812   expand %{
10813     roundDouble_mem_reg(dst,src);
10814   %}
10815 %}
10816 
10817 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10818   predicate(UseSSE==1);
10819   match(Set dst (ConvF2D src));
10820   effect( KILL cr );
10821   format %{ "SUB    ESP,4\n\t"
10822             "MOVSS  [ESP] $src\n\t"
10823             "FLD_S  [ESP]\n\t"
10824             "ADD    ESP,4\n\t"
10825             "FSTP   $dst\t# D-round" %}
10826   ins_encode %{
10827     __ subptr(rsp, 4);
10828     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10829     __ fld_s(Address(rsp, 0));
10830     __ addptr(rsp, 4);
10831     __ fstp_d($dst$$reg);
10832   %}
10833   ins_pipe( pipe_slow );
10834 %}
10835 
10836 instruct convF2D_reg(regD dst, regF src) %{
10837   predicate(UseSSE>=2);
10838   match(Set dst (ConvF2D src));
10839   format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10840   ins_encode %{
10841     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10842   %}
10843   ins_pipe( pipe_slow );
10844 %}
10845 
10846 // Convert a double to an int.  If the double is a NAN, stuff a zero in instead.
10847 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10848   predicate(UseSSE<=1);
10849   match(Set dst (ConvD2I src));
10850   effect( KILL tmp, KILL cr );
10851   format %{ "FLD    $src\t# Convert double to int \n\t"
10852             "FLDCW  trunc mode\n\t"
10853             "SUB    ESP,4\n\t"
10854             "FISTp  [ESP + #0]\n\t"
10855             "FLDCW  std/24-bit mode\n\t"
10856             "POP    EAX\n\t"
10857             "CMP    EAX,0x80000000\n\t"
10858             "JNE,s  fast\n\t"
10859             "FLD_D  $src\n\t"
10860             "CALL   d2i_wrapper\n"
10861       "fast:" %}
10862   ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10863   ins_pipe( pipe_slow );
10864 %}
10865 
10866 // Convert a double to an int.  If the double is a NAN, stuff a zero in instead.
10867 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10868   predicate(UseSSE>=2);
10869   match(Set dst (ConvD2I src));
10870   effect( KILL tmp, KILL cr );
10871   format %{ "CVTTSD2SI $dst, $src\n\t"
10872             "CMP    $dst,0x80000000\n\t"
10873             "JNE,s  fast\n\t"
10874             "SUB    ESP, 8\n\t"
10875             "MOVSD  [ESP], $src\n\t"
10876             "FLD_D  [ESP]\n\t"
10877             "ADD    ESP, 8\n\t"
10878             "CALL   d2i_wrapper\n"
10879       "fast:" %}
10880   ins_encode %{
10881     Label fast;
10882     __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10883     __ cmpl($dst$$Register, 0x80000000);
10884     __ jccb(Assembler::notEqual, fast);
10885     __ subptr(rsp, 8);
10886     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10887     __ fld_d(Address(rsp, 0));
10888     __ addptr(rsp, 8);
10889     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10890     __ bind(fast);
10891   %}
10892   ins_pipe( pipe_slow );
10893 %}
10894 
10895 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10896   predicate(UseSSE<=1);
10897   match(Set dst (ConvD2L src));
10898   effect( KILL cr );
10899   format %{ "FLD    $src\t# Convert double to long\n\t"
10900             "FLDCW  trunc mode\n\t"
10901             "SUB    ESP,8\n\t"
10902             "FISTp  [ESP + #0]\n\t"
10903             "FLDCW  std/24-bit mode\n\t"
10904             "POP    EAX\n\t"
10905             "POP    EDX\n\t"
10906             "CMP    EDX,0x80000000\n\t"
10907             "JNE,s  fast\n\t"
10908             "TEST   EAX,EAX\n\t"
10909             "JNE,s  fast\n\t"
10910             "FLD    $src\n\t"
10911             "CALL   d2l_wrapper\n"
10912       "fast:" %}
10913   ins_encode( Push_Reg_DPR(src),  DPR2L_encoding(src) );
10914   ins_pipe( pipe_slow );
10915 %}
10916 
10917 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10918 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10919   predicate (UseSSE>=2);
10920   match(Set dst (ConvD2L src));
10921   effect( KILL cr );
10922   format %{ "SUB    ESP,8\t# Convert double to long\n\t"
10923             "MOVSD  [ESP],$src\n\t"
10924             "FLD_D  [ESP]\n\t"
10925             "FLDCW  trunc mode\n\t"
10926             "FISTp  [ESP + #0]\n\t"
10927             "FLDCW  std/24-bit mode\n\t"
10928             "POP    EAX\n\t"
10929             "POP    EDX\n\t"
10930             "CMP    EDX,0x80000000\n\t"
10931             "JNE,s  fast\n\t"
10932             "TEST   EAX,EAX\n\t"
10933             "JNE,s  fast\n\t"
10934             "SUB    ESP,8\n\t"
10935             "MOVSD  [ESP],$src\n\t"
10936             "FLD_D  [ESP]\n\t"
10937             "ADD    ESP,8\n\t"
10938             "CALL   d2l_wrapper\n"
10939       "fast:" %}
10940   ins_encode %{
10941     Label fast;
10942     __ subptr(rsp, 8);
10943     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10944     __ fld_d(Address(rsp, 0));
10945     __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10946     __ fistp_d(Address(rsp, 0));
10947     // Restore the rounding mode, mask the exception
10948     if (Compile::current()->in_24_bit_fp_mode()) {
10949       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10950     } else {
10951       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10952     }
10953     // Load the converted long, adjust CPU stack
10954     __ pop(rax);
10955     __ pop(rdx);
10956     __ cmpl(rdx, 0x80000000);
10957     __ jccb(Assembler::notEqual, fast);
10958     __ testl(rax, rax);
10959     __ jccb(Assembler::notEqual, fast);
10960     __ subptr(rsp, 8);
10961     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10962     __ fld_d(Address(rsp, 0));
10963     __ addptr(rsp, 8);
10964     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10965     __ bind(fast);
10966   %}
10967   ins_pipe( pipe_slow );
10968 %}
10969 
10970 // Convert a double to an int.  Java semantics require we do complex
10971 // manglations in the corner cases.  So we set the rounding mode to
10972 // 'zero', store the darned double down as an int, and reset the
10973 // rounding mode to 'nearest'.  The hardware stores a flag value down
10974 // if we would overflow or converted a NAN; we check for this and
10975 // and go the slow path if needed.
10976 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10977   predicate(UseSSE==0);
10978   match(Set dst (ConvF2I src));
10979   effect( KILL tmp, KILL cr );
10980   format %{ "FLD    $src\t# Convert float to int \n\t"
10981             "FLDCW  trunc mode\n\t"
10982             "SUB    ESP,4\n\t"
10983             "FISTp  [ESP + #0]\n\t"
10984             "FLDCW  std/24-bit mode\n\t"
10985             "POP    EAX\n\t"
10986             "CMP    EAX,0x80000000\n\t"
10987             "JNE,s  fast\n\t"
10988             "FLD    $src\n\t"
10989             "CALL   d2i_wrapper\n"
10990       "fast:" %}
10991   // DPR2I_encoding works for FPR2I
10992   ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10993   ins_pipe( pipe_slow );
10994 %}
10995 
10996 // Convert a float in xmm to an int reg.
10997 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10998   predicate(UseSSE>=1);
10999   match(Set dst (ConvF2I src));
11000   effect( KILL tmp, KILL cr );
11001   format %{ "CVTTSS2SI $dst, $src\n\t"
11002             "CMP    $dst,0x80000000\n\t"
11003             "JNE,s  fast\n\t"
11004             "SUB    ESP, 4\n\t"
11005             "MOVSS  [ESP], $src\n\t"
11006             "FLD    [ESP]\n\t"
11007             "ADD    ESP, 4\n\t"
11008             "CALL   d2i_wrapper\n"
11009       "fast:" %}
11010   ins_encode %{
11011     Label fast;
11012     __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11013     __ cmpl($dst$$Register, 0x80000000);
11014     __ jccb(Assembler::notEqual, fast);
11015     __ subptr(rsp, 4);
11016     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11017     __ fld_s(Address(rsp, 0));
11018     __ addptr(rsp, 4);
11019     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11020     __ bind(fast);
11021   %}
11022   ins_pipe( pipe_slow );
11023 %}
11024 
11025 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11026   predicate(UseSSE==0);
11027   match(Set dst (ConvF2L src));
11028   effect( KILL cr );
11029   format %{ "FLD    $src\t# Convert float to long\n\t"
11030             "FLDCW  trunc mode\n\t"
11031             "SUB    ESP,8\n\t"
11032             "FISTp  [ESP + #0]\n\t"
11033             "FLDCW  std/24-bit mode\n\t"
11034             "POP    EAX\n\t"
11035             "POP    EDX\n\t"
11036             "CMP    EDX,0x80000000\n\t"
11037             "JNE,s  fast\n\t"
11038             "TEST   EAX,EAX\n\t"
11039             "JNE,s  fast\n\t"
11040             "FLD    $src\n\t"
11041             "CALL   d2l_wrapper\n"
11042       "fast:" %}
11043   // DPR2L_encoding works for FPR2L
11044   ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11045   ins_pipe( pipe_slow );
11046 %}
11047 
11048 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11049 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11050   predicate (UseSSE>=1);
11051   match(Set dst (ConvF2L src));
11052   effect( KILL cr );
11053   format %{ "SUB    ESP,8\t# Convert float to long\n\t"
11054             "MOVSS  [ESP],$src\n\t"
11055             "FLD_S  [ESP]\n\t"
11056             "FLDCW  trunc mode\n\t"
11057             "FISTp  [ESP + #0]\n\t"
11058             "FLDCW  std/24-bit mode\n\t"
11059             "POP    EAX\n\t"
11060             "POP    EDX\n\t"
11061             "CMP    EDX,0x80000000\n\t"
11062             "JNE,s  fast\n\t"
11063             "TEST   EAX,EAX\n\t"
11064             "JNE,s  fast\n\t"
11065             "SUB    ESP,4\t# Convert float to long\n\t"
11066             "MOVSS  [ESP],$src\n\t"
11067             "FLD_S  [ESP]\n\t"
11068             "ADD    ESP,4\n\t"
11069             "CALL   d2l_wrapper\n"
11070       "fast:" %}
11071   ins_encode %{
11072     Label fast;
11073     __ subptr(rsp, 8);
11074     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11075     __ fld_s(Address(rsp, 0));
11076     __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11077     __ fistp_d(Address(rsp, 0));
11078     // Restore the rounding mode, mask the exception
11079     if (Compile::current()->in_24_bit_fp_mode()) {
11080       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11081     } else {
11082       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11083     }
11084     // Load the converted long, adjust CPU stack
11085     __ pop(rax);
11086     __ pop(rdx);
11087     __ cmpl(rdx, 0x80000000);
11088     __ jccb(Assembler::notEqual, fast);
11089     __ testl(rax, rax);
11090     __ jccb(Assembler::notEqual, fast);
11091     __ subptr(rsp, 4);
11092     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11093     __ fld_s(Address(rsp, 0));
11094     __ addptr(rsp, 4);
11095     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11096     __ bind(fast);
11097   %}
11098   ins_pipe( pipe_slow );
11099 %}
11100 
11101 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11102   predicate( UseSSE<=1 );
11103   match(Set dst (ConvI2D src));
11104   format %{ "FILD   $src\n\t"
11105             "FSTP   $dst" %}
11106   opcode(0xDB, 0x0);  /* DB /0 */
11107   ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11108   ins_pipe( fpu_reg_mem );
11109 %}
11110 
11111 instruct convI2D_reg(regD dst, rRegI src) %{
11112   predicate( UseSSE>=2 && !UseXmmI2D );
11113   match(Set dst (ConvI2D src));
11114   format %{ "CVTSI2SD $dst,$src" %}
11115   ins_encode %{
11116     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11117   %}
11118   ins_pipe( pipe_slow );
11119 %}
11120 
11121 instruct convI2D_mem(regD dst, memory mem) %{
11122   predicate( UseSSE>=2 );
11123   match(Set dst (ConvI2D (LoadI mem)));
11124   format %{ "CVTSI2SD $dst,$mem" %}
11125   ins_encode %{
11126     __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11127   %}
11128   ins_pipe( pipe_slow );
11129 %}
11130 
11131 instruct convXI2D_reg(regD dst, rRegI src)
11132 %{
11133   predicate( UseSSE>=2 && UseXmmI2D );
11134   match(Set dst (ConvI2D src));
11135 
11136   format %{ "MOVD  $dst,$src\n\t"
11137             "CVTDQ2PD $dst,$dst\t# i2d" %}
11138   ins_encode %{
11139     __ movdl($dst$$XMMRegister, $src$$Register);
11140     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11141   %}
11142   ins_pipe(pipe_slow); // XXX
11143 %}
11144 
11145 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11146   predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11147   match(Set dst (ConvI2D (LoadI mem)));
11148   format %{ "FILD   $mem\n\t"
11149             "FSTP   $dst" %}
11150   opcode(0xDB);      /* DB /0 */
11151   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11152               Pop_Reg_DPR(dst));
11153   ins_pipe( fpu_reg_mem );
11154 %}
11155 
11156 // Convert a byte to a float; no rounding step needed.
11157 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11158   predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11159   match(Set dst (ConvI2F src));
11160   format %{ "FILD   $src\n\t"
11161             "FSTP   $dst" %}
11162 
11163   opcode(0xDB, 0x0);  /* DB /0 */
11164   ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11165   ins_pipe( fpu_reg_mem );
11166 %}
11167 
11168 // In 24-bit mode, force exponent rounding by storing back out
11169 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11170   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11171   match(Set dst (ConvI2F src));
11172   ins_cost(200);
11173   format %{ "FILD   $src\n\t"
11174             "FSTP_S $dst" %}
11175   opcode(0xDB, 0x0);  /* DB /0 */
11176   ins_encode( Push_Mem_I(src),
11177               Pop_Mem_FPR(dst));
11178   ins_pipe( fpu_mem_mem );
11179 %}
11180 
11181 // In 24-bit mode, force exponent rounding by storing back out
11182 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11183   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11184   match(Set dst (ConvI2F (LoadI mem)));
11185   ins_cost(200);
11186   format %{ "FILD   $mem\n\t"
11187             "FSTP_S $dst" %}
11188   opcode(0xDB);  /* DB /0 */
11189   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11190               Pop_Mem_FPR(dst));
11191   ins_pipe( fpu_mem_mem );
11192 %}
11193 
11194 // This instruction does not round to 24-bits
11195 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11196   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11197   match(Set dst (ConvI2F src));
11198   format %{ "FILD   $src\n\t"
11199             "FSTP   $dst" %}
11200   opcode(0xDB, 0x0);  /* DB /0 */
11201   ins_encode( Push_Mem_I(src),
11202               Pop_Reg_FPR(dst));
11203   ins_pipe( fpu_reg_mem );
11204 %}
11205 
11206 // This instruction does not round to 24-bits
11207 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11208   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11209   match(Set dst (ConvI2F (LoadI mem)));
11210   format %{ "FILD   $mem\n\t"
11211             "FSTP   $dst" %}
11212   opcode(0xDB);      /* DB /0 */
11213   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11214               Pop_Reg_FPR(dst));
11215   ins_pipe( fpu_reg_mem );
11216 %}
11217 
11218 // Convert an int to a float in xmm; no rounding step needed.
11219 instruct convI2F_reg(regF dst, rRegI src) %{
11220   predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11221   match(Set dst (ConvI2F src));
11222   format %{ "CVTSI2SS $dst, $src" %}
11223   ins_encode %{
11224     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11225   %}
11226   ins_pipe( pipe_slow );
11227 %}
11228 
11229  instruct convXI2F_reg(regF dst, rRegI src)
11230 %{
11231   predicate( UseSSE>=2 && UseXmmI2F );
11232   match(Set dst (ConvI2F src));
11233 
11234   format %{ "MOVD  $dst,$src\n\t"
11235             "CVTDQ2PS $dst,$dst\t# i2f" %}
11236   ins_encode %{
11237     __ movdl($dst$$XMMRegister, $src$$Register);
11238     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11239   %}
11240   ins_pipe(pipe_slow); // XXX
11241 %}
11242 
11243 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11244   match(Set dst (ConvI2L src));
11245   effect(KILL cr);
11246   ins_cost(375);
11247   format %{ "MOV    $dst.lo,$src\n\t"
11248             "MOV    $dst.hi,$src\n\t"
11249             "SAR    $dst.hi,31" %}
11250   ins_encode(convert_int_long(dst,src));
11251   ins_pipe( ialu_reg_reg_long );
11252 %}
11253 
11254 // Zero-extend convert int to long
11255 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11256   match(Set dst (AndL (ConvI2L src) mask) );
11257   effect( KILL flags );
11258   ins_cost(250);
11259   format %{ "MOV    $dst.lo,$src\n\t"
11260             "XOR    $dst.hi,$dst.hi" %}
11261   opcode(0x33); // XOR
11262   ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11263   ins_pipe( ialu_reg_reg_long );
11264 %}
11265 
11266 // Zero-extend long
11267 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11268   match(Set dst (AndL src mask) );
11269   effect( KILL flags );
11270   ins_cost(250);
11271   format %{ "MOV    $dst.lo,$src.lo\n\t"
11272             "XOR    $dst.hi,$dst.hi\n\t" %}
11273   opcode(0x33); // XOR
11274   ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11275   ins_pipe( ialu_reg_reg_long );
11276 %}
11277 
11278 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11279   predicate (UseSSE<=1);
11280   match(Set dst (ConvL2D src));
11281   effect( KILL cr );
11282   format %{ "PUSH   $src.hi\t# Convert long to double\n\t"
11283             "PUSH   $src.lo\n\t"
11284             "FILD   ST,[ESP + #0]\n\t"
11285             "ADD    ESP,8\n\t"
11286             "FSTP_D $dst\t# D-round" %}
11287   opcode(0xDF, 0x5);  /* DF /5 */
11288   ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11289   ins_pipe( pipe_slow );
11290 %}
11291 
11292 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11293   predicate (UseSSE>=2);
11294   match(Set dst (ConvL2D src));
11295   effect( KILL cr );
11296   format %{ "PUSH   $src.hi\t# Convert long to double\n\t"
11297             "PUSH   $src.lo\n\t"
11298             "FILD_D [ESP]\n\t"
11299             "FSTP_D [ESP]\n\t"
11300             "MOVSD  $dst,[ESP]\n\t"
11301             "ADD    ESP,8" %}
11302   opcode(0xDF, 0x5);  /* DF /5 */
11303   ins_encode(convert_long_double2(src), Push_ResultD(dst));
11304   ins_pipe( pipe_slow );
11305 %}
11306 
11307 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11308   predicate (UseSSE>=1);
11309   match(Set dst (ConvL2F src));
11310   effect( KILL cr );
11311   format %{ "PUSH   $src.hi\t# Convert long to single float\n\t"
11312             "PUSH   $src.lo\n\t"
11313             "FILD_D [ESP]\n\t"
11314             "FSTP_S [ESP]\n\t"
11315             "MOVSS  $dst,[ESP]\n\t"
11316             "ADD    ESP,8" %}
11317   opcode(0xDF, 0x5);  /* DF /5 */
11318   ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11319   ins_pipe( pipe_slow );
11320 %}
11321 
11322 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11323   match(Set dst (ConvL2F src));
11324   effect( KILL cr );
11325   format %{ "PUSH   $src.hi\t# Convert long to single float\n\t"
11326             "PUSH   $src.lo\n\t"
11327             "FILD   ST,[ESP + #0]\n\t"
11328             "ADD    ESP,8\n\t"
11329             "FSTP_S $dst\t# F-round" %}
11330   opcode(0xDF, 0x5);  /* DF /5 */
11331   ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11332   ins_pipe( pipe_slow );
11333 %}
11334 
11335 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11336   match(Set dst (ConvL2I src));
11337   effect( DEF dst, USE src );
11338   format %{ "MOV    $dst,$src.lo" %}
11339   ins_encode(enc_CopyL_Lo(dst,src));
11340   ins_pipe( ialu_reg_reg );
11341 %}
11342 
11343 
11344 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11345   match(Set dst (MoveF2I src));
11346   effect( DEF dst, USE src );
11347   ins_cost(100);
11348   format %{ "MOV    $dst,$src\t# MoveF2I_stack_reg" %}
11349   ins_encode %{
11350     __ movl($dst$$Register, Address(rsp, $src$$disp));
11351   %}
11352   ins_pipe( ialu_reg_mem );
11353 %}
11354 
11355 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11356   predicate(UseSSE==0);
11357   match(Set dst (MoveF2I src));
11358   effect( DEF dst, USE src );
11359 
11360   ins_cost(125);
11361   format %{ "FST_S  $dst,$src\t# MoveF2I_reg_stack" %}
11362   ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11363   ins_pipe( fpu_mem_reg );
11364 %}
11365 
11366 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11367   predicate(UseSSE>=1);
11368   match(Set dst (MoveF2I src));
11369   effect( DEF dst, USE src );
11370 
11371   ins_cost(95);
11372   format %{ "MOVSS  $dst,$src\t# MoveF2I_reg_stack_sse" %}
11373   ins_encode %{
11374     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11375   %}
11376   ins_pipe( pipe_slow );
11377 %}
11378 
11379 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11380   predicate(UseSSE>=2);
11381   match(Set dst (MoveF2I src));
11382   effect( DEF dst, USE src );
11383   ins_cost(85);
11384   format %{ "MOVD   $dst,$src\t# MoveF2I_reg_reg_sse" %}
11385   ins_encode %{
11386     __ movdl($dst$$Register, $src$$XMMRegister);
11387   %}
11388   ins_pipe( pipe_slow );
11389 %}
11390 
11391 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11392   match(Set dst (MoveI2F src));
11393   effect( DEF dst, USE src );
11394 
11395   ins_cost(100);
11396   format %{ "MOV    $dst,$src\t# MoveI2F_reg_stack" %}
11397   ins_encode %{
11398     __ movl(Address(rsp, $dst$$disp), $src$$Register);
11399   %}
11400   ins_pipe( ialu_mem_reg );
11401 %}
11402 
11403 
11404 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11405   predicate(UseSSE==0);
11406   match(Set dst (MoveI2F src));
11407   effect(DEF dst, USE src);
11408 
11409   ins_cost(125);
11410   format %{ "FLD_S  $src\n\t"
11411             "FSTP   $dst\t# MoveI2F_stack_reg" %}
11412   opcode(0xD9);               /* D9 /0, FLD m32real */
11413   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11414               Pop_Reg_FPR(dst) );
11415   ins_pipe( fpu_reg_mem );
11416 %}
11417 
11418 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11419   predicate(UseSSE>=1);
11420   match(Set dst (MoveI2F src));
11421   effect( DEF dst, USE src );
11422 
11423   ins_cost(95);
11424   format %{ "MOVSS  $dst,$src\t# MoveI2F_stack_reg_sse" %}
11425   ins_encode %{
11426     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11427   %}
11428   ins_pipe( pipe_slow );
11429 %}
11430 
11431 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11432   predicate(UseSSE>=2);
11433   match(Set dst (MoveI2F src));
11434   effect( DEF dst, USE src );
11435 
11436   ins_cost(85);
11437   format %{ "MOVD   $dst,$src\t# MoveI2F_reg_reg_sse" %}
11438   ins_encode %{
11439     __ movdl($dst$$XMMRegister, $src$$Register);
11440   %}
11441   ins_pipe( pipe_slow );
11442 %}
11443 
11444 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11445   match(Set dst (MoveD2L src));
11446   effect(DEF dst, USE src);
11447 
11448   ins_cost(250);
11449   format %{ "MOV    $dst.lo,$src\n\t"
11450             "MOV    $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11451   opcode(0x8B, 0x8B);
11452   ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11453   ins_pipe( ialu_mem_long_reg );
11454 %}
11455 
11456 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11457   predicate(UseSSE<=1);
11458   match(Set dst (MoveD2L src));
11459   effect(DEF dst, USE src);
11460 
11461   ins_cost(125);
11462   format %{ "FST_D  $dst,$src\t# MoveD2L_reg_stack" %}
11463   ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11464   ins_pipe( fpu_mem_reg );
11465 %}
11466 
11467 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11468   predicate(UseSSE>=2);
11469   match(Set dst (MoveD2L src));
11470   effect(DEF dst, USE src);
11471   ins_cost(95);
11472   format %{ "MOVSD  $dst,$src\t# MoveD2L_reg_stack_sse" %}
11473   ins_encode %{
11474     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11475   %}
11476   ins_pipe( pipe_slow );
11477 %}
11478 
11479 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11480   predicate(UseSSE>=2);
11481   match(Set dst (MoveD2L src));
11482   effect(DEF dst, USE src, TEMP tmp);
11483   ins_cost(85);
11484   format %{ "MOVD   $dst.lo,$src\n\t"
11485             "PSHUFLW $tmp,$src,0x4E\n\t"
11486             "MOVD   $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11487   ins_encode %{
11488     __ movdl($dst$$Register, $src$$XMMRegister);
11489     __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11490     __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11491   %}
11492   ins_pipe( pipe_slow );
11493 %}
11494 
11495 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11496   match(Set dst (MoveL2D src));
11497   effect(DEF dst, USE src);
11498 
11499   ins_cost(200);
11500   format %{ "MOV    $dst,$src.lo\n\t"
11501             "MOV    $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11502   opcode(0x89, 0x89);
11503   ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11504   ins_pipe( ialu_mem_long_reg );
11505 %}
11506 
11507 
11508 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11509   predicate(UseSSE<=1);
11510   match(Set dst (MoveL2D src));
11511   effect(DEF dst, USE src);
11512   ins_cost(125);
11513 
11514   format %{ "FLD_D  $src\n\t"
11515             "FSTP   $dst\t# MoveL2D_stack_reg" %}
11516   opcode(0xDD);               /* DD /0, FLD m64real */
11517   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11518               Pop_Reg_DPR(dst) );
11519   ins_pipe( fpu_reg_mem );
11520 %}
11521 
11522 
11523 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11524   predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11525   match(Set dst (MoveL2D src));
11526   effect(DEF dst, USE src);
11527 
11528   ins_cost(95);
11529   format %{ "MOVSD  $dst,$src\t# MoveL2D_stack_reg_sse" %}
11530   ins_encode %{
11531     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11532   %}
11533   ins_pipe( pipe_slow );
11534 %}
11535 
11536 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11537   predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11538   match(Set dst (MoveL2D src));
11539   effect(DEF dst, USE src);
11540 
11541   ins_cost(95);
11542   format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11543   ins_encode %{
11544     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11545   %}
11546   ins_pipe( pipe_slow );
11547 %}
11548 
11549 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11550   predicate(UseSSE>=2);
11551   match(Set dst (MoveL2D src));
11552   effect(TEMP dst, USE src, TEMP tmp);
11553   ins_cost(85);
11554   format %{ "MOVD   $dst,$src.lo\n\t"
11555             "MOVD   $tmp,$src.hi\n\t"
11556             "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11557   ins_encode %{
11558     __ movdl($dst$$XMMRegister, $src$$Register);
11559     __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11560     __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11561   %}
11562   ins_pipe( pipe_slow );
11563 %}
11564 
11565 
11566 // =======================================================================
11567 // fast clearing of an array
11568 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11569   predicate(!UseFastStosb);
11570   match(Set dummy (ClearArray cnt base));
11571   effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11572   format %{ "XOR    EAX,EAX\t# ClearArray:\n\t"
11573             "SHL    ECX,1\t# Convert doublewords to words\n\t"
11574             "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11575   ins_encode %{ 
11576     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11577   %}
11578   ins_pipe( pipe_slow );
11579 %}
11580 
11581 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11582   predicate(UseFastStosb);
11583   match(Set dummy (ClearArray cnt base));
11584   effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11585   format %{ "XOR    EAX,EAX\t# ClearArray:\n\t"
11586             "SHL    ECX,3\t# Convert doublewords to bytes\n\t"
11587             "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11588   ins_encode %{ 
11589     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11590   %}
11591   ins_pipe( pipe_slow );
11592 %}
11593 
11594 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11595                         eAXRegI result, regD tmp1, eFlagsReg cr) %{
11596   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11597   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11598 
11599   format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11600   ins_encode %{
11601     __ string_compare($str1$$Register, $str2$$Register,
11602                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11603                       $tmp1$$XMMRegister);
11604   %}
11605   ins_pipe( pipe_slow );
11606 %}
11607 
11608 // fast string equals
11609 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11610                        regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11611   match(Set result (StrEquals (Binary str1 str2) cnt));
11612   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11613 
11614   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11615   ins_encode %{
11616     __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11617                           $cnt$$Register, $result$$Register, $tmp3$$Register,
11618                           $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11619   %}
11620   ins_pipe( pipe_slow );
11621 %}
11622 
11623 // fast search of substring with known size.
11624 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11625                             eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11626   predicate(UseSSE42Intrinsics);
11627   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11628   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11629 
11630   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11631   ins_encode %{
11632     int icnt2 = (int)$int_cnt2$$constant;
11633     if (icnt2 >= 8) {
11634       // IndexOf for constant substrings with size >= 8 elements
11635       // which don't need to be loaded through stack.
11636       __ string_indexofC8($str1$$Register, $str2$$Register,
11637                           $cnt1$$Register, $cnt2$$Register,
11638                           icnt2, $result$$Register,
11639                           $vec$$XMMRegister, $tmp$$Register);
11640     } else {
11641       // Small strings are loaded through stack if they cross page boundary.
11642       __ string_indexof($str1$$Register, $str2$$Register,
11643                         $cnt1$$Register, $cnt2$$Register,
11644                         icnt2, $result$$Register,
11645                         $vec$$XMMRegister, $tmp$$Register);
11646     }
11647   %}
11648   ins_pipe( pipe_slow );
11649 %}
11650 
11651 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11652                         eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11653   predicate(UseSSE42Intrinsics);
11654   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11655   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11656 
11657   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11658   ins_encode %{
11659     __ string_indexof($str1$$Register, $str2$$Register,
11660                       $cnt1$$Register, $cnt2$$Register,
11661                       (-1), $result$$Register,
11662                       $vec$$XMMRegister, $tmp$$Register);
11663   %}
11664   ins_pipe( pipe_slow );
11665 %}
11666 
11667 // fast array equals
11668 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11669                       regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11670 %{
11671   match(Set result (AryEq ary1 ary2));
11672   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11673   //ins_cost(300);
11674 
11675   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11676   ins_encode %{
11677     __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11678                           $tmp3$$Register, $result$$Register, $tmp4$$Register,
11679                           $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11680   %}
11681   ins_pipe( pipe_slow );
11682 %}
11683 
11684 // encode char[] to byte[] in ISO_8859_1
11685 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11686                           regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11687                           eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11688   match(Set result (EncodeISOArray src (Binary dst len)));
11689   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11690 
11691   format %{ "Encode array $src,$dst,$len -> $result    // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11692   ins_encode %{
11693     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11694                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11695                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11696   %}
11697   ins_pipe( pipe_slow );
11698 %}
11699 
11700 
11701 //----------Control Flow Instructions------------------------------------------
11702 // Signed compare Instructions
11703 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11704   match(Set cr (CmpI op1 op2));
11705   effect( DEF cr, USE op1, USE op2 );
11706   format %{ "CMP    $op1,$op2" %}
11707   opcode(0x3B);  /* Opcode 3B /r */
11708   ins_encode( OpcP, RegReg( op1, op2) );
11709   ins_pipe( ialu_cr_reg_reg );
11710 %}
11711 
11712 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11713   match(Set cr (CmpI op1 op2));
11714   effect( DEF cr, USE op1 );
11715   format %{ "CMP    $op1,$op2" %}
11716   opcode(0x81,0x07);  /* Opcode 81 /7 */
11717   // ins_encode( RegImm( op1, op2) );  /* Was CmpImm */
11718   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11719   ins_pipe( ialu_cr_reg_imm );
11720 %}
11721 
11722 // Cisc-spilled version of cmpI_eReg
11723 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11724   match(Set cr (CmpI op1 (LoadI op2)));
11725 
11726   format %{ "CMP    $op1,$op2" %}
11727   ins_cost(500);
11728   opcode(0x3B);  /* Opcode 3B /r */
11729   ins_encode( OpcP, RegMem( op1, op2) );
11730   ins_pipe( ialu_cr_reg_mem );
11731 %}
11732 
11733 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11734   match(Set cr (CmpI src zero));
11735   effect( DEF cr, USE src );
11736 
11737   format %{ "TEST   $src,$src" %}
11738   opcode(0x85);
11739   ins_encode( OpcP, RegReg( src, src ) );
11740   ins_pipe( ialu_cr_reg_imm );
11741 %}
11742 
11743 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11744   match(Set cr (CmpI (AndI src con) zero));
11745 
11746   format %{ "TEST   $src,$con" %}
11747   opcode(0xF7,0x00);
11748   ins_encode( OpcP, RegOpc(src), Con32(con) );
11749   ins_pipe( ialu_cr_reg_imm );
11750 %}
11751 
11752 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11753   match(Set cr (CmpI (AndI src mem) zero));
11754 
11755   format %{ "TEST   $src,$mem" %}
11756   opcode(0x85);
11757   ins_encode( OpcP, RegMem( src, mem ) );
11758   ins_pipe( ialu_cr_reg_mem );
11759 %}
11760 
11761 // Unsigned compare Instructions; really, same as signed except they
11762 // produce an eFlagsRegU instead of eFlagsReg.
11763 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11764   match(Set cr (CmpU op1 op2));
11765 
11766   format %{ "CMPu   $op1,$op2" %}
11767   opcode(0x3B);  /* Opcode 3B /r */
11768   ins_encode( OpcP, RegReg( op1, op2) );
11769   ins_pipe( ialu_cr_reg_reg );
11770 %}
11771 
11772 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11773   match(Set cr (CmpU op1 op2));
11774 
11775   format %{ "CMPu   $op1,$op2" %}
11776   opcode(0x81,0x07);  /* Opcode 81 /7 */
11777   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11778   ins_pipe( ialu_cr_reg_imm );
11779 %}
11780 
11781 // // Cisc-spilled version of cmpU_eReg
11782 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11783   match(Set cr (CmpU op1 (LoadI op2)));
11784 
11785   format %{ "CMPu   $op1,$op2" %}
11786   ins_cost(500);
11787   opcode(0x3B);  /* Opcode 3B /r */
11788   ins_encode( OpcP, RegMem( op1, op2) );
11789   ins_pipe( ialu_cr_reg_mem );
11790 %}
11791 
11792 // // Cisc-spilled version of cmpU_eReg
11793 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11794 //  match(Set cr (CmpU (LoadI op1) op2));
11795 //
11796 //  format %{ "CMPu   $op1,$op2" %}
11797 //  ins_cost(500);
11798 //  opcode(0x39);  /* Opcode 39 /r */
11799 //  ins_encode( OpcP, RegMem( op1, op2) );
11800 //%}
11801 
11802 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11803   match(Set cr (CmpU src zero));
11804 
11805   format %{ "TESTu  $src,$src" %}
11806   opcode(0x85);
11807   ins_encode( OpcP, RegReg( src, src ) );
11808   ins_pipe( ialu_cr_reg_imm );
11809 %}
11810 
11811 // Unsigned pointer compare Instructions
11812 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11813   match(Set cr (CmpP op1 op2));
11814 
11815   format %{ "CMPu   $op1,$op2" %}
11816   opcode(0x3B);  /* Opcode 3B /r */
11817   ins_encode( OpcP, RegReg( op1, op2) );
11818   ins_pipe( ialu_cr_reg_reg );
11819 %}
11820 
11821 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11822   match(Set cr (CmpP op1 op2));
11823 
11824   format %{ "CMPu   $op1,$op2" %}
11825   opcode(0x81,0x07);  /* Opcode 81 /7 */
11826   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11827   ins_pipe( ialu_cr_reg_imm );
11828 %}
11829 
11830 // // Cisc-spilled version of cmpP_eReg
11831 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11832   match(Set cr (CmpP op1 (LoadP op2)));
11833 
11834   format %{ "CMPu   $op1,$op2" %}
11835   ins_cost(500);
11836   opcode(0x3B);  /* Opcode 3B /r */
11837   ins_encode( OpcP, RegMem( op1, op2) );
11838   ins_pipe( ialu_cr_reg_mem );
11839 %}
11840 
11841 // // Cisc-spilled version of cmpP_eReg
11842 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11843 //  match(Set cr (CmpP (LoadP op1) op2));
11844 //
11845 //  format %{ "CMPu   $op1,$op2" %}
11846 //  ins_cost(500);
11847 //  opcode(0x39);  /* Opcode 39 /r */
11848 //  ins_encode( OpcP, RegMem( op1, op2) );
11849 //%}
11850 
11851 // Compare raw pointer (used in out-of-heap check).
11852 // Only works because non-oop pointers must be raw pointers
11853 // and raw pointers have no anti-dependencies.
11854 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11855   predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11856   match(Set cr (CmpP op1 (LoadP op2)));
11857 
11858   format %{ "CMPu   $op1,$op2" %}
11859   opcode(0x3B);  /* Opcode 3B /r */
11860   ins_encode( OpcP, RegMem( op1, op2) );
11861   ins_pipe( ialu_cr_reg_mem );
11862 %}
11863 
11864 //
11865 // This will generate a signed flags result. This should be ok
11866 // since any compare to a zero should be eq/neq.
11867 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11868   match(Set cr (CmpP src zero));
11869 
11870   format %{ "TEST   $src,$src" %}
11871   opcode(0x85);
11872   ins_encode( OpcP, RegReg( src, src ) );
11873   ins_pipe( ialu_cr_reg_imm );
11874 %}
11875 
11876 // Cisc-spilled version of testP_reg
11877 // This will generate a signed flags result. This should be ok
11878 // since any compare to a zero should be eq/neq.
11879 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11880   match(Set cr (CmpP (LoadP op) zero));
11881 
11882   format %{ "TEST   $op,0xFFFFFFFF" %}
11883   ins_cost(500);
11884   opcode(0xF7);               /* Opcode F7 /0 */
11885   ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11886   ins_pipe( ialu_cr_reg_imm );
11887 %}
11888 
11889 // Yanked all unsigned pointer compare operations.
11890 // Pointer compares are done with CmpP which is already unsigned.
11891 
11892 //----------Max and Min--------------------------------------------------------
11893 // Min Instructions
11894 ////
11895 //   *** Min and Max using the conditional move are slower than the
11896 //   *** branch version on a Pentium III.
11897 // // Conditional move for min
11898 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11899 //  effect( USE_DEF op2, USE op1, USE cr );
11900 //  format %{ "CMOVlt $op2,$op1\t! min" %}
11901 //  opcode(0x4C,0x0F);
11902 //  ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11903 //  ins_pipe( pipe_cmov_reg );
11904 //%}
11905 //
11906 //// Min Register with Register (P6 version)
11907 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11908 //  predicate(VM_Version::supports_cmov() );
11909 //  match(Set op2 (MinI op1 op2));
11910 //  ins_cost(200);
11911 //  expand %{
11912 //    eFlagsReg cr;
11913 //    compI_eReg(cr,op1,op2);
11914 //    cmovI_reg_lt(op2,op1,cr);
11915 //  %}
11916 //%}
11917 
11918 // Min Register with Register (generic version)
11919 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11920   match(Set dst (MinI dst src));
11921   effect(KILL flags);
11922   ins_cost(300);
11923 
11924   format %{ "MIN    $dst,$src" %}
11925   opcode(0xCC);
11926   ins_encode( min_enc(dst,src) );
11927   ins_pipe( pipe_slow );
11928 %}
11929 
11930 // Max Register with Register
11931 //   *** Min and Max using the conditional move are slower than the
11932 //   *** branch version on a Pentium III.
11933 // // Conditional move for max
11934 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11935 //  effect( USE_DEF op2, USE op1, USE cr );
11936 //  format %{ "CMOVgt $op2,$op1\t! max" %}
11937 //  opcode(0x4F,0x0F);
11938 //  ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11939 //  ins_pipe( pipe_cmov_reg );
11940 //%}
11941 //
11942 // // Max Register with Register (P6 version)
11943 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11944 //  predicate(VM_Version::supports_cmov() );
11945 //  match(Set op2 (MaxI op1 op2));
11946 //  ins_cost(200);
11947 //  expand %{
11948 //    eFlagsReg cr;
11949 //    compI_eReg(cr,op1,op2);
11950 //    cmovI_reg_gt(op2,op1,cr);
11951 //  %}
11952 //%}
11953 
11954 // Max Register with Register (generic version)
11955 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11956   match(Set dst (MaxI dst src));
11957   effect(KILL flags);
11958   ins_cost(300);
11959 
11960   format %{ "MAX    $dst,$src" %}
11961   opcode(0xCC);
11962   ins_encode( max_enc(dst,src) );
11963   ins_pipe( pipe_slow );
11964 %}
11965 
11966 // ============================================================================
11967 // Counted Loop limit node which represents exact final iterator value.
11968 // Note: the resulting value should fit into integer range since
11969 // counted loops have limit check on overflow.
11970 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11971   match(Set limit (LoopLimit (Binary init limit) stride));
11972   effect(TEMP limit_hi, TEMP tmp, KILL flags);
11973   ins_cost(300);
11974 
11975   format %{ "loopLimit $init,$limit,$stride  # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11976   ins_encode %{
11977     int strd = (int)$stride$$constant;
11978     assert(strd != 1 && strd != -1, "sanity");
11979     int m1 = (strd > 0) ? 1 : -1;
11980     // Convert limit to long (EAX:EDX)
11981     __ cdql();
11982     // Convert init to long (init:tmp)
11983     __ movl($tmp$$Register, $init$$Register);
11984     __ sarl($tmp$$Register, 31);
11985     // $limit - $init
11986     __ subl($limit$$Register, $init$$Register);
11987     __ sbbl($limit_hi$$Register, $tmp$$Register);
11988     // + ($stride - 1)
11989     if (strd > 0) {
11990       __ addl($limit$$Register, (strd - 1));
11991       __ adcl($limit_hi$$Register, 0);
11992       __ movl($tmp$$Register, strd);
11993     } else {
11994       __ addl($limit$$Register, (strd + 1));
11995       __ adcl($limit_hi$$Register, -1);
11996       __ lneg($limit_hi$$Register, $limit$$Register);
11997       __ movl($tmp$$Register, -strd);
11998     }
11999     // signed devision: (EAX:EDX) / pos_stride
12000     __ idivl($tmp$$Register);
12001     if (strd < 0) {
12002       // restore sign
12003       __ negl($tmp$$Register);
12004     }
12005     // (EAX) * stride
12006     __ mull($tmp$$Register);
12007     // + init (ignore upper bits)
12008     __ addl($limit$$Register, $init$$Register);
12009   %}
12010   ins_pipe( pipe_slow );
12011 %}
12012 
12013 // ============================================================================
12014 // Branch Instructions
12015 // Jump Table
12016 instruct jumpXtnd(rRegI switch_val) %{
12017   match(Jump switch_val);
12018   ins_cost(350);
12019   format %{  "JMP    [$constantaddress](,$switch_val,1)\n\t" %}
12020   ins_encode %{
12021     // Jump to Address(table_base + switch_reg)
12022     Address index(noreg, $switch_val$$Register, Address::times_1);
12023     __ jump(ArrayAddress($constantaddress, index));
12024   %}
12025   ins_pipe(pipe_jmp);
12026 %}
12027 
12028 // Jump Direct - Label defines a relative address from JMP+1
12029 instruct jmpDir(label labl) %{
12030   match(Goto);
12031   effect(USE labl);
12032 
12033   ins_cost(300);
12034   format %{ "JMP    $labl" %}
12035   size(5);
12036   ins_encode %{
12037     Label* L = $labl$$label;
12038     __ jmp(*L, false); // Always long jump
12039   %}
12040   ins_pipe( pipe_jmp );
12041 %}
12042 
12043 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12044 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12045   match(If cop cr);
12046   effect(USE labl);
12047 
12048   ins_cost(300);
12049   format %{ "J$cop    $labl" %}
12050   size(6);
12051   ins_encode %{
12052     Label* L = $labl$$label;
12053     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12054   %}
12055   ins_pipe( pipe_jcc );
12056 %}
12057 
12058 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12059 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12060   match(CountedLoopEnd cop cr);
12061   effect(USE labl);
12062 
12063   ins_cost(300);
12064   format %{ "J$cop    $labl\t# Loop end" %}
12065   size(6);
12066   ins_encode %{
12067     Label* L = $labl$$label;
12068     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12069   %}
12070   ins_pipe( pipe_jcc );
12071 %}
12072 
12073 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12074 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12075   match(CountedLoopEnd cop cmp);
12076   effect(USE labl);
12077 
12078   ins_cost(300);
12079   format %{ "J$cop,u  $labl\t# Loop end" %}
12080   size(6);
12081   ins_encode %{
12082     Label* L = $labl$$label;
12083     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12084   %}
12085   ins_pipe( pipe_jcc );
12086 %}
12087 
12088 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12089   match(CountedLoopEnd cop cmp);
12090   effect(USE labl);
12091 
12092   ins_cost(200);
12093   format %{ "J$cop,u  $labl\t# Loop end" %}
12094   size(6);
12095   ins_encode %{
12096     Label* L = $labl$$label;
12097     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12098   %}
12099   ins_pipe( pipe_jcc );
12100 %}
12101 
12102 // Jump Direct Conditional - using unsigned comparison
12103 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12104   match(If cop cmp);
12105   effect(USE labl);
12106 
12107   ins_cost(300);
12108   format %{ "J$cop,u  $labl" %}
12109   size(6);
12110   ins_encode %{
12111     Label* L = $labl$$label;
12112     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12113   %}
12114   ins_pipe(pipe_jcc);
12115 %}
12116 
12117 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12118   match(If cop cmp);
12119   effect(USE labl);
12120 
12121   ins_cost(200);
12122   format %{ "J$cop,u  $labl" %}
12123   size(6);
12124   ins_encode %{
12125     Label* L = $labl$$label;
12126     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12127   %}
12128   ins_pipe(pipe_jcc);
12129 %}
12130 
12131 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12132   match(If cop cmp);
12133   effect(USE labl);
12134 
12135   ins_cost(200);
12136   format %{ $$template
12137     if ($cop$$cmpcode == Assembler::notEqual) {
12138       $$emit$$"JP,u   $labl\n\t"
12139       $$emit$$"J$cop,u   $labl"
12140     } else {
12141       $$emit$$"JP,u   done\n\t"
12142       $$emit$$"J$cop,u   $labl\n\t"
12143       $$emit$$"done:"
12144     }
12145   %}
12146   ins_encode %{
12147     Label* l = $labl$$label;
12148     if ($cop$$cmpcode == Assembler::notEqual) {
12149       __ jcc(Assembler::parity, *l, false);
12150       __ jcc(Assembler::notEqual, *l, false);
12151     } else if ($cop$$cmpcode == Assembler::equal) {
12152       Label done;
12153       __ jccb(Assembler::parity, done);
12154       __ jcc(Assembler::equal, *l, false);
12155       __ bind(done);
12156     } else {
12157        ShouldNotReachHere();
12158     }
12159   %}
12160   ins_pipe(pipe_jcc);
12161 %}
12162 
12163 // ============================================================================
12164 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
12165 // array for an instance of the superklass.  Set a hidden internal cache on a
12166 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
12167 // NZ for a miss or zero for a hit.  The encoding ALSO sets flags.
12168 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12169   match(Set result (PartialSubtypeCheck sub super));
12170   effect( KILL rcx, KILL cr );
12171 
12172   ins_cost(1100);  // slightly larger than the next version
12173   format %{ "MOV    EDI,[$sub+Klass::secondary_supers]\n\t"
12174             "MOV    ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12175             "ADD    EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12176             "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12177             "JNE,s  miss\t\t# Missed: EDI not-zero\n\t"
12178             "MOV    [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12179             "XOR    $result,$result\t\t Hit: EDI zero\n\t"
12180      "miss:\t" %}
12181 
12182   opcode(0x1); // Force a XOR of EDI
12183   ins_encode( enc_PartialSubtypeCheck() );
12184   ins_pipe( pipe_slow );
12185 %}
12186 
12187 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12188   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12189   effect( KILL rcx, KILL result );
12190 
12191   ins_cost(1000);
12192   format %{ "MOV    EDI,[$sub+Klass::secondary_supers]\n\t"
12193             "MOV    ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12194             "ADD    EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12195             "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12196             "JNE,s  miss\t\t# Missed: flags NZ\n\t"
12197             "MOV    [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12198      "miss:\t" %}
12199 
12200   opcode(0x0);  // No need to XOR EDI
12201   ins_encode( enc_PartialSubtypeCheck() );
12202   ins_pipe( pipe_slow );
12203 %}
12204 
12205 // ============================================================================
12206 // Branch Instructions -- short offset versions
12207 //
12208 // These instructions are used to replace jumps of a long offset (the default
12209 // match) with jumps of a shorter offset.  These instructions are all tagged
12210 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12211 // match rules in general matching.  Instead, the ADLC generates a conversion
12212 // method in the MachNode which can be used to do in-place replacement of the
12213 // long variant with the shorter variant.  The compiler will determine if a
12214 // branch can be taken by the is_short_branch_offset() predicate in the machine
12215 // specific code section of the file.
12216 
12217 // Jump Direct - Label defines a relative address from JMP+1
12218 instruct jmpDir_short(label labl) %{
12219   match(Goto);
12220   effect(USE labl);
12221 
12222   ins_cost(300);
12223   format %{ "JMP,s  $labl" %}
12224   size(2);
12225   ins_encode %{
12226     Label* L = $labl$$label;
12227     __ jmpb(*L);
12228   %}
12229   ins_pipe( pipe_jmp );
12230   ins_short_branch(1);
12231 %}
12232 
12233 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12234 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12235   match(If cop cr);
12236   effect(USE labl);
12237 
12238   ins_cost(300);
12239   format %{ "J$cop,s  $labl" %}
12240   size(2);
12241   ins_encode %{
12242     Label* L = $labl$$label;
12243     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12244   %}
12245   ins_pipe( pipe_jcc );
12246   ins_short_branch(1);
12247 %}
12248 
12249 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12250 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12251   match(CountedLoopEnd cop cr);
12252   effect(USE labl);
12253 
12254   ins_cost(300);
12255   format %{ "J$cop,s  $labl\t# Loop end" %}
12256   size(2);
12257   ins_encode %{
12258     Label* L = $labl$$label;
12259     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12260   %}
12261   ins_pipe( pipe_jcc );
12262   ins_short_branch(1);
12263 %}
12264 
12265 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12266 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12267   match(CountedLoopEnd cop cmp);
12268   effect(USE labl);
12269 
12270   ins_cost(300);
12271   format %{ "J$cop,us $labl\t# Loop end" %}
12272   size(2);
12273   ins_encode %{
12274     Label* L = $labl$$label;
12275     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12276   %}
12277   ins_pipe( pipe_jcc );
12278   ins_short_branch(1);
12279 %}
12280 
12281 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12282   match(CountedLoopEnd cop cmp);
12283   effect(USE labl);
12284 
12285   ins_cost(300);
12286   format %{ "J$cop,us $labl\t# Loop end" %}
12287   size(2);
12288   ins_encode %{
12289     Label* L = $labl$$label;
12290     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12291   %}
12292   ins_pipe( pipe_jcc );
12293   ins_short_branch(1);
12294 %}
12295 
12296 // Jump Direct Conditional - using unsigned comparison
12297 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12298   match(If cop cmp);
12299   effect(USE labl);
12300 
12301   ins_cost(300);
12302   format %{ "J$cop,us $labl" %}
12303   size(2);
12304   ins_encode %{
12305     Label* L = $labl$$label;
12306     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12307   %}
12308   ins_pipe( pipe_jcc );
12309   ins_short_branch(1);
12310 %}
12311 
12312 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12313   match(If cop cmp);
12314   effect(USE labl);
12315 
12316   ins_cost(300);
12317   format %{ "J$cop,us $labl" %}
12318   size(2);
12319   ins_encode %{
12320     Label* L = $labl$$label;
12321     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12322   %}
12323   ins_pipe( pipe_jcc );
12324   ins_short_branch(1);
12325 %}
12326 
12327 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12328   match(If cop cmp);
12329   effect(USE labl);
12330 
12331   ins_cost(300);
12332   format %{ $$template
12333     if ($cop$$cmpcode == Assembler::notEqual) {
12334       $$emit$$"JP,u,s   $labl\n\t"
12335       $$emit$$"J$cop,u,s   $labl"
12336     } else {
12337       $$emit$$"JP,u,s   done\n\t"
12338       $$emit$$"J$cop,u,s  $labl\n\t"
12339       $$emit$$"done:"
12340     }
12341   %}
12342   size(4);
12343   ins_encode %{
12344     Label* l = $labl$$label;
12345     if ($cop$$cmpcode == Assembler::notEqual) {
12346       __ jccb(Assembler::parity, *l);
12347       __ jccb(Assembler::notEqual, *l);
12348     } else if ($cop$$cmpcode == Assembler::equal) {
12349       Label done;
12350       __ jccb(Assembler::parity, done);
12351       __ jccb(Assembler::equal, *l);
12352       __ bind(done);
12353     } else {
12354        ShouldNotReachHere();
12355     }
12356   %}
12357   ins_pipe(pipe_jcc);
12358   ins_short_branch(1);
12359 %}
12360 
12361 // ============================================================================
12362 // Long Compare
12363 //
12364 // Currently we hold longs in 2 registers.  Comparing such values efficiently
12365 // is tricky.  The flavor of compare used depends on whether we are testing
12366 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
12367 // The GE test is the negated LT test.  The LE test can be had by commuting
12368 // the operands (yielding a GE test) and then negating; negate again for the
12369 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
12370 // NE test is negated from that.
12371 
12372 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12373 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
12374 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
12375 // are collapsed internally in the ADLC's dfa-gen code.  The match for
12376 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12377 // foo match ends up with the wrong leaf.  One fix is to not match both
12378 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
12379 // both forms beat the trinary form of long-compare and both are very useful
12380 // on Intel which has so few registers.
12381 
12382 // Manifest a CmpL result in an integer register.  Very painful.
12383 // This is the test to avoid.
12384 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12385   match(Set dst (CmpL3 src1 src2));
12386   effect( KILL flags );
12387   ins_cost(1000);
12388   format %{ "XOR    $dst,$dst\n\t"
12389             "CMP    $src1.hi,$src2.hi\n\t"
12390             "JLT,s  m_one\n\t"
12391             "JGT,s  p_one\n\t"
12392             "CMP    $src1.lo,$src2.lo\n\t"
12393             "JB,s   m_one\n\t"
12394             "JEQ,s  done\n"
12395     "p_one:\tINC    $dst\n\t"
12396             "JMP,s  done\n"
12397     "m_one:\tDEC    $dst\n"
12398      "done:" %}
12399   ins_encode %{
12400     Label p_one, m_one, done;
12401     __ xorptr($dst$$Register, $dst$$Register);
12402     __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12403     __ jccb(Assembler::less,    m_one);
12404     __ jccb(Assembler::greater, p_one);
12405     __ cmpl($src1$$Register, $src2$$Register);
12406     __ jccb(Assembler::below,   m_one);
12407     __ jccb(Assembler::equal,   done);
12408     __ bind(p_one);
12409     __ incrementl($dst$$Register);
12410     __ jmpb(done);
12411     __ bind(m_one);
12412     __ decrementl($dst$$Register);
12413     __ bind(done);
12414   %}
12415   ins_pipe( pipe_slow );
12416 %}
12417 
12418 //======
12419 // Manifest a CmpL result in the normal flags.  Only good for LT or GE
12420 // compares.  Can be used for LE or GT compares by reversing arguments.
12421 // NOT GOOD FOR EQ/NE tests.
12422 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12423   match( Set flags (CmpL src zero ));
12424   ins_cost(100);
12425   format %{ "TEST   $src.hi,$src.hi" %}
12426   opcode(0x85);
12427   ins_encode( OpcP, RegReg_Hi2( src, src ) );
12428   ins_pipe( ialu_cr_reg_reg );
12429 %}
12430 
12431 // Manifest a CmpL result in the normal flags.  Only good for LT or GE
12432 // compares.  Can be used for LE or GT compares by reversing arguments.
12433 // NOT GOOD FOR EQ/NE tests.
12434 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12435   match( Set flags (CmpL src1 src2 ));
12436   effect( TEMP tmp );
12437   ins_cost(300);
12438   format %{ "CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12439             "MOV    $tmp,$src1.hi\n\t"
12440             "SBB    $tmp,$src2.hi\t! Compute flags for long compare" %}
12441   ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12442   ins_pipe( ialu_cr_reg_reg );
12443 %}
12444 
12445 // Long compares reg < zero/req OR reg >= zero/req.
12446 // Just a wrapper for a normal branch, plus the predicate test.
12447 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12448   match(If cmp flags);
12449   effect(USE labl);
12450   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12451   expand %{
12452     jmpCon(cmp,flags,labl);    // JLT or JGE...
12453   %}
12454 %}
12455 
12456 // Compare 2 longs and CMOVE longs.
12457 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12458   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12459   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12460   ins_cost(400);
12461   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12462             "CMOV$cmp $dst.hi,$src.hi" %}
12463   opcode(0x0F,0x40);
12464   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12465   ins_pipe( pipe_cmov_reg_long );
12466 %}
12467 
12468 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12469   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12470   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12471   ins_cost(500);
12472   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12473             "CMOV$cmp $dst.hi,$src.hi" %}
12474   opcode(0x0F,0x40);
12475   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12476   ins_pipe( pipe_cmov_reg_long );
12477 %}
12478 
12479 // Compare 2 longs and CMOVE ints.
12480 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12481   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12482   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12483   ins_cost(200);
12484   format %{ "CMOV$cmp $dst,$src" %}
12485   opcode(0x0F,0x40);
12486   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12487   ins_pipe( pipe_cmov_reg );
12488 %}
12489 
12490 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12491   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12492   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12493   ins_cost(250);
12494   format %{ "CMOV$cmp $dst,$src" %}
12495   opcode(0x0F,0x40);
12496   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12497   ins_pipe( pipe_cmov_mem );
12498 %}
12499 
12500 // Compare 2 longs and CMOVE ints.
12501 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12502   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12503   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12504   ins_cost(200);
12505   format %{ "CMOV$cmp $dst,$src" %}
12506   opcode(0x0F,0x40);
12507   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12508   ins_pipe( pipe_cmov_reg );
12509 %}
12510 
12511 // Compare 2 longs and CMOVE doubles
12512 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12513   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12514   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12515   ins_cost(200);
12516   expand %{
12517     fcmovDPR_regS(cmp,flags,dst,src);
12518   %}
12519 %}
12520 
12521 // Compare 2 longs and CMOVE doubles
12522 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12523   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12524   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12525   ins_cost(200);
12526   expand %{
12527     fcmovD_regS(cmp,flags,dst,src);
12528   %}
12529 %}
12530 
12531 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12532   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12533   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12534   ins_cost(200);
12535   expand %{
12536     fcmovFPR_regS(cmp,flags,dst,src);
12537   %}
12538 %}
12539 
12540 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12541   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12542   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12543   ins_cost(200);
12544   expand %{
12545     fcmovF_regS(cmp,flags,dst,src);
12546   %}
12547 %}
12548 
12549 //======
12550 // Manifest a CmpL result in the normal flags.  Only good for EQ/NE compares.
12551 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12552   match( Set flags (CmpL src zero ));
12553   effect(TEMP tmp);
12554   ins_cost(200);
12555   format %{ "MOV    $tmp,$src.lo\n\t"
12556             "OR     $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12557   ins_encode( long_cmp_flags0( src, tmp ) );
12558   ins_pipe( ialu_reg_reg_long );
12559 %}
12560 
12561 // Manifest a CmpL result in the normal flags.  Only good for EQ/NE compares.
12562 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12563   match( Set flags (CmpL src1 src2 ));
12564   ins_cost(200+300);
12565   format %{ "CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12566             "JNE,s  skip\n\t"
12567             "CMP    $src1.hi,$src2.hi\n\t"
12568      "skip:\t" %}
12569   ins_encode( long_cmp_flags1( src1, src2 ) );
12570   ins_pipe( ialu_cr_reg_reg );
12571 %}
12572 
12573 // Long compare reg == zero/reg OR reg != zero/reg
12574 // Just a wrapper for a normal branch, plus the predicate test.
12575 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12576   match(If cmp flags);
12577   effect(USE labl);
12578   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12579   expand %{
12580     jmpCon(cmp,flags,labl);    // JEQ or JNE...
12581   %}
12582 %}
12583 
12584 // Compare 2 longs and CMOVE longs.
12585 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12586   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12587   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12588   ins_cost(400);
12589   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12590             "CMOV$cmp $dst.hi,$src.hi" %}
12591   opcode(0x0F,0x40);
12592   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12593   ins_pipe( pipe_cmov_reg_long );
12594 %}
12595 
12596 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12597   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12598   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12599   ins_cost(500);
12600   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12601             "CMOV$cmp $dst.hi,$src.hi" %}
12602   opcode(0x0F,0x40);
12603   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12604   ins_pipe( pipe_cmov_reg_long );
12605 %}
12606 
12607 // Compare 2 longs and CMOVE ints.
12608 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12609   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12610   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12611   ins_cost(200);
12612   format %{ "CMOV$cmp $dst,$src" %}
12613   opcode(0x0F,0x40);
12614   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12615   ins_pipe( pipe_cmov_reg );
12616 %}
12617 
12618 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12619   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12620   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12621   ins_cost(250);
12622   format %{ "CMOV$cmp $dst,$src" %}
12623   opcode(0x0F,0x40);
12624   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12625   ins_pipe( pipe_cmov_mem );
12626 %}
12627 
12628 // Compare 2 longs and CMOVE ints.
12629 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12630   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12631   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12632   ins_cost(200);
12633   format %{ "CMOV$cmp $dst,$src" %}
12634   opcode(0x0F,0x40);
12635   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12636   ins_pipe( pipe_cmov_reg );
12637 %}
12638 
12639 // Compare 2 longs and CMOVE doubles
12640 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12641   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12642   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12643   ins_cost(200);
12644   expand %{
12645     fcmovDPR_regS(cmp,flags,dst,src);
12646   %}
12647 %}
12648 
12649 // Compare 2 longs and CMOVE doubles
12650 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12651   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12652   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12653   ins_cost(200);
12654   expand %{
12655     fcmovD_regS(cmp,flags,dst,src);
12656   %}
12657 %}
12658 
12659 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12660   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12661   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12662   ins_cost(200);
12663   expand %{
12664     fcmovFPR_regS(cmp,flags,dst,src);
12665   %}
12666 %}
12667 
12668 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12669   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12670   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12671   ins_cost(200);
12672   expand %{
12673     fcmovF_regS(cmp,flags,dst,src);
12674   %}
12675 %}
12676 
12677 //======
12678 // Manifest a CmpL result in the normal flags.  Only good for LE or GT compares.
12679 // Same as cmpL_reg_flags_LEGT except must negate src
12680 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12681   match( Set flags (CmpL src zero ));
12682   effect( TEMP tmp );
12683   ins_cost(300);
12684   format %{ "XOR    $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12685             "CMP    $tmp,$src.lo\n\t"
12686             "SBB    $tmp,$src.hi\n\t" %}
12687   ins_encode( long_cmp_flags3(src, tmp) );
12688   ins_pipe( ialu_reg_reg_long );
12689 %}
12690 
12691 // Manifest a CmpL result in the normal flags.  Only good for LE or GT compares.
12692 // Same as cmpL_reg_flags_LTGE except operands swapped.  Swapping operands
12693 // requires a commuted test to get the same result.
12694 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12695   match( Set flags (CmpL src1 src2 ));
12696   effect( TEMP tmp );
12697   ins_cost(300);
12698   format %{ "CMP    $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12699             "MOV    $tmp,$src2.hi\n\t"
12700             "SBB    $tmp,$src1.hi\t! Compute flags for long compare" %}
12701   ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12702   ins_pipe( ialu_cr_reg_reg );
12703 %}
12704 
12705 // Long compares reg < zero/req OR reg >= zero/req.
12706 // Just a wrapper for a normal branch, plus the predicate test
12707 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12708   match(If cmp flags);
12709   effect(USE labl);
12710   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12711   ins_cost(300);
12712   expand %{
12713     jmpCon(cmp,flags,labl);    // JGT or JLE...
12714   %}
12715 %}
12716 
12717 // Compare 2 longs and CMOVE longs.
12718 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12719   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12720   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12721   ins_cost(400);
12722   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12723             "CMOV$cmp $dst.hi,$src.hi" %}
12724   opcode(0x0F,0x40);
12725   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12726   ins_pipe( pipe_cmov_reg_long );
12727 %}
12728 
12729 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12730   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12731   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12732   ins_cost(500);
12733   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12734             "CMOV$cmp $dst.hi,$src.hi+4" %}
12735   opcode(0x0F,0x40);
12736   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12737   ins_pipe( pipe_cmov_reg_long );
12738 %}
12739 
12740 // Compare 2 longs and CMOVE ints.
12741 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12742   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12743   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12744   ins_cost(200);
12745   format %{ "CMOV$cmp $dst,$src" %}
12746   opcode(0x0F,0x40);
12747   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12748   ins_pipe( pipe_cmov_reg );
12749 %}
12750 
12751 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12752   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12753   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12754   ins_cost(250);
12755   format %{ "CMOV$cmp $dst,$src" %}
12756   opcode(0x0F,0x40);
12757   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12758   ins_pipe( pipe_cmov_mem );
12759 %}
12760 
12761 // Compare 2 longs and CMOVE ptrs.
12762 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12763   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12764   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12765   ins_cost(200);
12766   format %{ "CMOV$cmp $dst,$src" %}
12767   opcode(0x0F,0x40);
12768   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12769   ins_pipe( pipe_cmov_reg );
12770 %}
12771 
12772 // Compare 2 longs and CMOVE doubles
12773 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12774   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12775   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12776   ins_cost(200);
12777   expand %{
12778     fcmovDPR_regS(cmp,flags,dst,src);
12779   %}
12780 %}
12781 
12782 // Compare 2 longs and CMOVE doubles
12783 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12784   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12785   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12786   ins_cost(200);
12787   expand %{
12788     fcmovD_regS(cmp,flags,dst,src);
12789   %}
12790 %}
12791 
12792 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12793   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12794   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12795   ins_cost(200);
12796   expand %{
12797     fcmovFPR_regS(cmp,flags,dst,src);
12798   %}
12799 %}
12800 
12801 
12802 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12803   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12804   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12805   ins_cost(200);
12806   expand %{
12807     fcmovF_regS(cmp,flags,dst,src);
12808   %}
12809 %}
12810 
12811 
12812 // ============================================================================
12813 // Procedure Call/Return Instructions
12814 // Call Java Static Instruction
12815 // Note: If this code changes, the corresponding ret_addr_offset() and
12816 //       compute_padding() functions will have to be adjusted.
12817 instruct CallStaticJavaDirect(method meth) %{
12818   match(CallStaticJava);
12819   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12820   effect(USE meth);
12821 
12822   ins_cost(300);
12823   format %{ "CALL,static " %}
12824   opcode(0xE8); /* E8 cd */
12825   ins_encode( pre_call_resets,
12826               Java_Static_Call( meth ),
12827               call_epilog,
12828               post_call_FPU );
12829   ins_pipe( pipe_slow );
12830   ins_alignment(4);
12831 %}
12832 
12833 // Call Java Static Instruction (method handle version)
12834 // Note: If this code changes, the corresponding ret_addr_offset() and
12835 //       compute_padding() functions will have to be adjusted.
12836 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12837   match(CallStaticJava);
12838   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12839   effect(USE meth);
12840   // EBP is saved by all callees (for interpreter stack correction).
12841   // We use it here for a similar purpose, in {preserve,restore}_SP.
12842 
12843   ins_cost(300);
12844   format %{ "CALL,static/MethodHandle " %}
12845   opcode(0xE8); /* E8 cd */
12846   ins_encode( pre_call_resets,
12847               preserve_SP,
12848               Java_Static_Call( meth ),
12849               restore_SP,
12850               call_epilog,
12851               post_call_FPU );
12852   ins_pipe( pipe_slow );
12853   ins_alignment(4);
12854 %}
12855 
12856 // Call Java Dynamic Instruction
12857 // Note: If this code changes, the corresponding ret_addr_offset() and
12858 //       compute_padding() functions will have to be adjusted.
12859 instruct CallDynamicJavaDirect(method meth) %{
12860   match(CallDynamicJava);
12861   effect(USE meth);
12862 
12863   ins_cost(300);
12864   format %{ "MOV    EAX,(oop)-1\n\t"
12865             "CALL,dynamic" %}
12866   opcode(0xE8); /* E8 cd */
12867   ins_encode( pre_call_resets,
12868               Java_Dynamic_Call( meth ),
12869               call_epilog,
12870               post_call_FPU );
12871   ins_pipe( pipe_slow );
12872   ins_alignment(4);
12873 %}
12874 
12875 // Call Runtime Instruction
12876 instruct CallRuntimeDirect(method meth) %{
12877   match(CallRuntime );
12878   effect(USE meth);
12879 
12880   ins_cost(300);
12881   format %{ "CALL,runtime " %}
12882   opcode(0xE8); /* E8 cd */
12883   // Use FFREEs to clear entries in float stack
12884   ins_encode( pre_call_resets,
12885               FFree_Float_Stack_All,
12886               Java_To_Runtime( meth ),
12887               post_call_FPU );
12888   ins_pipe( pipe_slow );
12889 %}
12890 
12891 // Call runtime without safepoint
12892 instruct CallLeafDirect(method meth) %{
12893   match(CallLeaf);
12894   effect(USE meth);
12895 
12896   ins_cost(300);
12897   format %{ "CALL_LEAF,runtime " %}
12898   opcode(0xE8); /* E8 cd */
12899   ins_encode( pre_call_resets,
12900               FFree_Float_Stack_All,
12901               Java_To_Runtime( meth ),
12902               Verify_FPU_For_Leaf, post_call_FPU );
12903   ins_pipe( pipe_slow );
12904 %}
12905 
12906 instruct CallLeafNoFPDirect(method meth) %{
12907   match(CallLeafNoFP);
12908   effect(USE meth);
12909 
12910   ins_cost(300);
12911   format %{ "CALL_LEAF_NOFP,runtime " %}
12912   opcode(0xE8); /* E8 cd */
12913   ins_encode(Java_To_Runtime(meth));
12914   ins_pipe( pipe_slow );
12915 %}
12916 
12917 
12918 // Return Instruction
12919 // Remove the return address & jump to it.
12920 instruct Ret() %{
12921   match(Return);
12922   format %{ "RET" %}
12923   opcode(0xC3);
12924   ins_encode(OpcP);
12925   ins_pipe( pipe_jmp );
12926 %}
12927 
12928 // Tail Call; Jump from runtime stub to Java code.
12929 // Also known as an 'interprocedural jump'.
12930 // Target of jump will eventually return to caller.
12931 // TailJump below removes the return address.
12932 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12933   match(TailCall jump_target method_oop );
12934   ins_cost(300);
12935   format %{ "JMP    $jump_target \t# EBX holds method oop" %}
12936   opcode(0xFF, 0x4);  /* Opcode FF /4 */
12937   ins_encode( OpcP, RegOpc(jump_target) );
12938   ins_pipe( pipe_jmp );
12939 %}
12940 
12941 
12942 // Tail Jump; remove the return address; jump to target.
12943 // TailCall above leaves the return address around.
12944 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12945   match( TailJump jump_target ex_oop );
12946   ins_cost(300);
12947   format %{ "POP    EDX\t# pop return address into dummy\n\t"
12948             "JMP    $jump_target " %}
12949   opcode(0xFF, 0x4);  /* Opcode FF /4 */
12950   ins_encode( enc_pop_rdx,
12951               OpcP, RegOpc(jump_target) );
12952   ins_pipe( pipe_jmp );
12953 %}
12954 
12955 // Create exception oop: created by stack-crawling runtime code.
12956 // Created exception is now available to this handler, and is setup
12957 // just prior to jumping to this handler.  No code emitted.
12958 instruct CreateException( eAXRegP ex_oop )
12959 %{
12960   match(Set ex_oop (CreateEx));
12961 
12962   size(0);
12963   // use the following format syntax
12964   format %{ "# exception oop is in EAX; no code emitted" %}
12965   ins_encode();
12966   ins_pipe( empty );
12967 %}
12968 
12969 
12970 // Rethrow exception:
12971 // The exception oop will come in the first argument position.
12972 // Then JUMP (not call) to the rethrow stub code.
12973 instruct RethrowException()
12974 %{
12975   match(Rethrow);
12976 
12977   // use the following format syntax
12978   format %{ "JMP    rethrow_stub" %}
12979   ins_encode(enc_rethrow);
12980   ins_pipe( pipe_jmp );
12981 %}
12982 
12983 // inlined locking and unlocking
12984 
12985 
12986 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12987   match( Set cr (FastLock object box) );
12988   effect( TEMP tmp, TEMP scr, USE_KILL box );
12989   ins_cost(300);
12990   format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12991   ins_encode( Fast_Lock(object,box,tmp,scr) );
12992   ins_pipe( pipe_slow );
12993 %}
12994 
12995 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12996   match( Set cr (FastUnlock object box) );
12997   effect( TEMP tmp, USE_KILL box );
12998   ins_cost(300);
12999   format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13000   ins_encode( Fast_Unlock(object,box,tmp) );
13001   ins_pipe( pipe_slow );
13002 %}
13003 
13004 
13005 
13006 // ============================================================================
13007 // Safepoint Instruction
13008 instruct safePoint_poll(eFlagsReg cr) %{
13009   match(SafePoint);
13010   effect(KILL cr);
13011 
13012   // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13013   // On SPARC that might be acceptable as we can generate the address with
13014   // just a sethi, saving an or.  By polling at offset 0 we can end up
13015   // putting additional pressure on the index-0 in the D$.  Because of
13016   // alignment (just like the situation at hand) the lower indices tend
13017   // to see more traffic.  It'd be better to change the polling address
13018   // to offset 0 of the last $line in the polling page.
13019 
13020   format %{ "TSTL   #polladdr,EAX\t! Safepoint: poll for GC" %}
13021   ins_cost(125);
13022   size(6) ;
13023   ins_encode( Safepoint_Poll() );
13024   ins_pipe( ialu_reg_mem );
13025 %}
13026 
13027 
13028 // ============================================================================
13029 // This name is KNOWN by the ADLC and cannot be changed.
13030 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13031 // for this guy.
13032 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13033   match(Set dst (ThreadLocal));
13034   effect(DEF dst, KILL cr);
13035 
13036   format %{ "MOV    $dst, Thread::current()" %}
13037   ins_encode %{
13038     Register dstReg = as_Register($dst$$reg);
13039     __ get_thread(dstReg);
13040   %}
13041   ins_pipe( ialu_reg_fat );
13042 %}
13043 
13044 
13045 
13046 //----------PEEPHOLE RULES-----------------------------------------------------
13047 // These must follow all instruction definitions as they use the names
13048 // defined in the instructions definitions.
13049 //
13050 // peepmatch ( root_instr_name [preceding_instruction]* );
13051 //
13052 // peepconstraint %{
13053 // (instruction_number.operand_name relational_op instruction_number.operand_name
13054 //  [, ...] );
13055 // // instruction numbers are zero-based using left to right order in peepmatch
13056 //
13057 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
13058 // // provide an instruction_number.operand_name for each operand that appears
13059 // // in the replacement instruction's match rule
13060 //
13061 // ---------VM FLAGS---------------------------------------------------------
13062 //
13063 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13064 //
13065 // Each peephole rule is given an identifying number starting with zero and
13066 // increasing by one in the order seen by the parser.  An individual peephole
13067 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13068 // on the command-line.
13069 //
13070 // ---------CURRENT LIMITATIONS----------------------------------------------
13071 //
13072 // Only match adjacent instructions in same basic block
13073 // Only equality constraints
13074 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13075 // Only one replacement instruction
13076 //
13077 // ---------EXAMPLE----------------------------------------------------------
13078 //
13079 // // pertinent parts of existing instructions in architecture description
13080 // instruct movI(rRegI dst, rRegI src) %{
13081 //   match(Set dst (CopyI src));
13082 // %}
13083 //
13084 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13085 //   match(Set dst (AddI dst src));
13086 //   effect(KILL cr);
13087 // %}
13088 //
13089 // // Change (inc mov) to lea
13090 // peephole %{
13091 //   // increment preceeded by register-register move
13092 //   peepmatch ( incI_eReg movI );
13093 //   // require that the destination register of the increment
13094 //   // match the destination register of the move
13095 //   peepconstraint ( 0.dst == 1.dst );
13096 //   // construct a replacement instruction that sets
13097 //   // the destination to ( move's source register + one )
13098 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13099 // %}
13100 //
13101 // Implementation no longer uses movX instructions since
13102 // machine-independent system no longer uses CopyX nodes.
13103 //
13104 // peephole %{
13105 //   peepmatch ( incI_eReg movI );
13106 //   peepconstraint ( 0.dst == 1.dst );
13107 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13108 // %}
13109 //
13110 // peephole %{
13111 //   peepmatch ( decI_eReg movI );
13112 //   peepconstraint ( 0.dst == 1.dst );
13113 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13114 // %}
13115 //
13116 // peephole %{
13117 //   peepmatch ( addI_eReg_imm movI );
13118 //   peepconstraint ( 0.dst == 1.dst );
13119 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13120 // %}
13121 //
13122 // peephole %{
13123 //   peepmatch ( addP_eReg_imm movP );
13124 //   peepconstraint ( 0.dst == 1.dst );
13125 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13126 // %}
13127 
13128 // // Change load of spilled value to only a spill
13129 // instruct storeI(memory mem, rRegI src) %{
13130 //   match(Set mem (StoreI mem src));
13131 // %}
13132 //
13133 // instruct loadI(rRegI dst, memory mem) %{
13134 //   match(Set dst (LoadI mem));
13135 // %}
13136 //
13137 peephole %{
13138   peepmatch ( loadI storeI );
13139   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13140   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13141 %}
13142 
13143 //----------SMARTSPILL RULES---------------------------------------------------
13144 // These must follow all instruction definitions as they use the names
13145 // defined in the instructions definitions.