src/share/vm/opto/matcher.cpp

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rev 5661 : 8024921: PPC64 (part 113): Extend Load and Store nodes to know about memory ordering.


 808     STACK_ONLY_mask.Insert(i);
 809   // Also set the "infinite stack" bit.
 810   STACK_ONLY_mask.set_AllStack();
 811 
 812   // Copy the register names over into the shared world
 813   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 814     // SharedInfo::regName[i] = regName[i];
 815     // Handy RegMasks per machine register
 816     mreg2regmask[i].Insert(i);
 817   }
 818 
 819   // Grab the Frame Pointer
 820   Node *fp  = ret->in(TypeFunc::FramePtr);
 821   Node *mem = ret->in(TypeFunc::Memory);
 822   const TypePtr* atp = TypePtr::BOTTOM;
 823   // Share frame pointer while making spill ops
 824   set_shared(fp);
 825 
 826   // Compute generic short-offset Loads
 827 #ifdef _LP64
 828   MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
 829 #endif
 830   MachNode *spillI  = match_tree(new (C) LoadINode(NULL,mem,fp,atp));
 831   MachNode *spillL  = match_tree(new (C) LoadLNode(NULL,mem,fp,atp));
 832   MachNode *spillF  = match_tree(new (C) LoadFNode(NULL,mem,fp,atp));
 833   MachNode *spillD  = match_tree(new (C) LoadDNode(NULL,mem,fp,atp));
 834   MachNode *spillP  = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
 835   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 836          spillD != NULL && spillP != NULL, "");
 837 
 838   // Get the ADLC notion of the right regmask, for each basic type.
 839 #ifdef _LP64
 840   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 841 #endif
 842   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 843   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 844   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 845   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 846   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 847 
 848   // Vector regmasks.
 849   if (Matcher::vector_size_supported(T_BYTE,4)) {
 850     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 851     MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 852     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 853   }
 854   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 855     MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 856     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 857   }




 808     STACK_ONLY_mask.Insert(i);
 809   // Also set the "infinite stack" bit.
 810   STACK_ONLY_mask.set_AllStack();
 811 
 812   // Copy the register names over into the shared world
 813   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 814     // SharedInfo::regName[i] = regName[i];
 815     // Handy RegMasks per machine register
 816     mreg2regmask[i].Insert(i);
 817   }
 818 
 819   // Grab the Frame Pointer
 820   Node *fp  = ret->in(TypeFunc::FramePtr);
 821   Node *mem = ret->in(TypeFunc::Memory);
 822   const TypePtr* atp = TypePtr::BOTTOM;
 823   // Share frame pointer while making spill ops
 824   set_shared(fp);
 825 
 826   // Compute generic short-offset Loads
 827 #ifdef _LP64
 828   MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,LoadNode::unordered));
 829 #endif
 830   MachNode *spillI  = match_tree(new (C) LoadINode(NULL,mem,fp,atp,TypeInt::INT,LoadNode::unordered));
 831   MachNode *spillL  = match_tree(new (C) LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,false,LoadNode::unordered));
 832   MachNode *spillF  = match_tree(new (C) LoadFNode(NULL,mem,fp,atp,Type::FLOAT,LoadNode::unordered));
 833   MachNode *spillD  = match_tree(new (C) LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,LoadNode::unordered));
 834   MachNode *spillP  = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,LoadNode::unordered));
 835   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 836          spillD != NULL && spillP != NULL, "");

 837   // Get the ADLC notion of the right regmask, for each basic type.
 838 #ifdef _LP64
 839   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 840 #endif
 841   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 842   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 843   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 844   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 845   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 846 
 847   // Vector regmasks.
 848   if (Matcher::vector_size_supported(T_BYTE,4)) {
 849     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 850     MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 851     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 852   }
 853   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 854     MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 855     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 856   }