src/share/vm/opto/mulnode.cpp

rev 5661 : 8024921: PPC64 (part 113): Extend Load and Store nodes to know about memory ordering.

@@ -483,22 +483,24 @@
       load->outcnt() == 1 && load->unique_out() == this) {
     if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
       Node *ldus = new (phase->C) LoadUSNode(load->in(MemNode::Control),
                                              load->in(MemNode::Memory),
                                              load->in(MemNode::Address),
-                                             load->adr_type());
+                                             load->adr_type(),
+                                             TypeInt::CHAR, LoadNode::unordered);
       ldus = phase->transform(ldus);
       return new (phase->C) AndINode(ldus, phase->intcon(mask & 0xFFFF));
     }
 
     // Masking sign bits off of a Byte?  Do an unsigned byte load plus
     // an and.
     if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
       Node* ldub = new (phase->C) LoadUBNode(load->in(MemNode::Control),
                                              load->in(MemNode::Memory),
                                              load->in(MemNode::Address),
-                                             load->adr_type());
+                                             load->adr_type(),
+                                             TypeInt::UBYTE, LoadNode::unordered);
       ldub = phase->transform(ldub);
       return new (phase->C) AndINode(ldub, phase->intcon(mask));
     }
   }
 

@@ -931,11 +933,12 @@
              ld->outcnt() == 1 && ld->unique_out() == shl)
       // Replace zero-extension-load with sign-extension-load
       return new (phase->C) LoadSNode( ld->in(MemNode::Control),
                                 ld->in(MemNode::Memory),
                                 ld->in(MemNode::Address),
-                                ld->adr_type());
+                                       ld->adr_type(), TypeInt::SHORT,
+                                       LoadNode::unordered);
   }
 
   // Check for "(byte[i] <<24)>>24" which simply sign-extends
   if( shift == 24 &&
       (t3 = phase->type(shl->in(2))->isa_int()) &&