1442 count++;
1443 uint i4;
1444 for (i4 = 0; i4 < last_inst; ++i4) {
1445 if (block->get_node(i4) == oop_store) {
1446 break;
1447 }
1448 }
1449 // Note: This test can provide a false failure if other precedence
1450 // edges have been added to the storeCMNode.
1451 assert(i4 == last_inst || i4 < storeCM_idx, "CM card-mark executes before oop-store");
1452 }
1453 assert(count > 0, "storeCM expects at least one precedence edge");
1454 }
1455 #endif
1456 else if (!n->is_Proj()) {
1457 // Remember the beginning of the previous instruction, in case
1458 // it's followed by a flag-kill and a null-check. Happens on
1459 // Intel all the time, with add-to-memory kind of opcodes.
1460 previous_offset = current_offset;
1461 }
1462 }
1463
1464 // Verify that there is sufficient space remaining
1465 cb->insts()->maybe_expand_to_ensure_remaining(MAX_inst_size);
1466 if ((cb->blob() == NULL) || (!CompileBroker::should_compile_new_jobs())) {
1467 C->record_failure("CodeCache is full");
1468 return;
1469 }
1470
1471 // Save the offset for the listing
1472 #ifndef PRODUCT
1473 if (node_offsets && n->_idx < node_offset_limit)
1474 node_offsets[n->_idx] = cb->insts_size();
1475 #endif
1476
1477 // "Normal" instruction case
1478 DEBUG_ONLY( uint instr_offset = cb->insts_size(); )
1479 n->emit(*cb, _regalloc);
1480 current_offset = cb->insts_size();
1481
1708 }
1709 }
1710 }
1711 }
1712 assert(found_p, "no matching predecessor found");
1713 // Note: Due to empty block removal, one block may have
1714 // several CatchProj inputs, from the same Catch.
1715 }
1716
1717 // Set the offset of the return from the call
1718 _handler_table.add_subtable(call_return, &handler_bcis, NULL, &handler_pcos);
1719 continue;
1720 }
1721
1722 // Handle implicit null exception table updates
1723 if (n->is_MachNullCheck()) {
1724 uint block_num = block->non_connector_successor(0)->_pre_order;
1725 _inc_table.append(inct_starts[inct_cnt++], blk_labels[block_num].loc_pos());
1726 continue;
1727 }
1728 } // End of for all blocks fill in exception table entries
1729 }
1730
1731 // Static Variables
1732 #ifndef PRODUCT
1733 uint Scheduling::_total_nop_size = 0;
1734 uint Scheduling::_total_method_size = 0;
1735 uint Scheduling::_total_branches = 0;
1736 uint Scheduling::_total_unconditional_delays = 0;
1737 uint Scheduling::_total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+1];
1738 #endif
1739
1740 // Initializer for class Scheduling
1741
1742 Scheduling::Scheduling(Arena *arena, Compile &compile)
1743 : _arena(arena),
1744 _cfg(compile.cfg()),
1745 _regalloc(compile.regalloc()),
1746 _reg_node(arena),
1747 _bundle_instr_count(0),
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1442 count++;
1443 uint i4;
1444 for (i4 = 0; i4 < last_inst; ++i4) {
1445 if (block->get_node(i4) == oop_store) {
1446 break;
1447 }
1448 }
1449 // Note: This test can provide a false failure if other precedence
1450 // edges have been added to the storeCMNode.
1451 assert(i4 == last_inst || i4 < storeCM_idx, "CM card-mark executes before oop-store");
1452 }
1453 assert(count > 0, "storeCM expects at least one precedence edge");
1454 }
1455 #endif
1456 else if (!n->is_Proj()) {
1457 // Remember the beginning of the previous instruction, in case
1458 // it's followed by a flag-kill and a null-check. Happens on
1459 // Intel all the time, with add-to-memory kind of opcodes.
1460 previous_offset = current_offset;
1461 }
1462
1463 // Not an else-if!
1464 // If this is a trap based cmp then add its offset to the list.
1465 if (mach->is_TrapBasedCheckNode()) {
1466 inct_starts[inct_cnt++] = current_offset;
1467 }
1468 }
1469
1470 // Verify that there is sufficient space remaining
1471 cb->insts()->maybe_expand_to_ensure_remaining(MAX_inst_size);
1472 if ((cb->blob() == NULL) || (!CompileBroker::should_compile_new_jobs())) {
1473 C->record_failure("CodeCache is full");
1474 return;
1475 }
1476
1477 // Save the offset for the listing
1478 #ifndef PRODUCT
1479 if (node_offsets && n->_idx < node_offset_limit)
1480 node_offsets[n->_idx] = cb->insts_size();
1481 #endif
1482
1483 // "Normal" instruction case
1484 DEBUG_ONLY( uint instr_offset = cb->insts_size(); )
1485 n->emit(*cb, _regalloc);
1486 current_offset = cb->insts_size();
1487
1714 }
1715 }
1716 }
1717 }
1718 assert(found_p, "no matching predecessor found");
1719 // Note: Due to empty block removal, one block may have
1720 // several CatchProj inputs, from the same Catch.
1721 }
1722
1723 // Set the offset of the return from the call
1724 _handler_table.add_subtable(call_return, &handler_bcis, NULL, &handler_pcos);
1725 continue;
1726 }
1727
1728 // Handle implicit null exception table updates
1729 if (n->is_MachNullCheck()) {
1730 uint block_num = block->non_connector_successor(0)->_pre_order;
1731 _inc_table.append(inct_starts[inct_cnt++], blk_labels[block_num].loc_pos());
1732 continue;
1733 }
1734 // Handle implicit exception table updates: trap instructions.
1735 if (n->is_Mach() && n->as_Mach()->is_TrapBasedCheckNode()) {
1736 uint block_num = block->non_connector_successor(0)->_pre_order;
1737 _inc_table.append(inct_starts[inct_cnt++], blk_labels[block_num].loc_pos());
1738 continue;
1739 }
1740 } // End of for all blocks fill in exception table entries
1741 }
1742
1743 // Static Variables
1744 #ifndef PRODUCT
1745 uint Scheduling::_total_nop_size = 0;
1746 uint Scheduling::_total_method_size = 0;
1747 uint Scheduling::_total_branches = 0;
1748 uint Scheduling::_total_unconditional_delays = 0;
1749 uint Scheduling::_total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+1];
1750 #endif
1751
1752 // Initializer for class Scheduling
1753
1754 Scheduling::Scheduling(Arena *arena, Compile &compile)
1755 : _arena(arena),
1756 _cfg(compile.cfg()),
1757 _regalloc(compile.regalloc()),
1758 _reg_node(arena),
1759 _bundle_instr_count(0),
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